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asm! support for the Xtensa architecture (#68)
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@MabezDev
MabezDev committed Feb 22, 2022
1 parent 7fbd858 commit 9d4ab85
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8 changes: 8 additions & 0 deletions compiler/rustc_codegen_llvm/src/asm.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -329,6 +329,7 @@ impl<'ll, 'tcx> AsmBuilderMethods<'tcx> for Builder<'_, 'll, 'tcx> {
InlineAsmArch::S390x => {}
InlineAsmArch::SpirV => {}
InlineAsmArch::Wasm32 | InlineAsmArch::Wasm64 => {}
InlineAsmArch::Xtensa => {}
InlineAsmArch::Bpf => {}
}
}
Expand Down Expand Up @@ -669,6 +670,9 @@ fn reg_to_llvm(reg: InlineAsmRegOrRegClass, layout: Option<&TyAndLayout<'_>>) ->
X86InlineAsmRegClass::x87_reg | X86InlineAsmRegClass::mmx_reg,
) => unreachable!("clobber-only"),
InlineAsmRegClass::Wasm(WasmInlineAsmRegClass::local) => "r",
InlineAsmRegClass::Xtensa(XtensaInlineAsmRegClass::reg) => "r",
InlineAsmRegClass::Xtensa(XtensaInlineAsmRegClass::freg) => "f",
InlineAsmRegClass::Xtensa(XtensaInlineAsmRegClass::breg) => "b",
InlineAsmRegClass::Bpf(BpfInlineAsmRegClass::reg) => "r",
InlineAsmRegClass::Bpf(BpfInlineAsmRegClass::wreg) => "w",
InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg) => "r",
Expand Down Expand Up @@ -721,6 +725,7 @@ fn modifier_to_llvm(
InlineAsmRegClass::Mips(_) => None,
InlineAsmRegClass::Nvptx(_) => None,
InlineAsmRegClass::PowerPC(_) => None,
InlineAsmRegClass::Xtensa(_) => None,
InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::reg)
| InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::freg) => None,
InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::vreg) => {
Expand Down Expand Up @@ -823,6 +828,9 @@ fn dummy_output_type<'ll>(cx: &CodegenCx<'ll, '_>, reg: InlineAsmRegClass) -> &'
unreachable!("clobber-only")
}
InlineAsmRegClass::Wasm(WasmInlineAsmRegClass::local) => cx.type_i32(),
InlineAsmRegClass::Xtensa(XtensaInlineAsmRegClass::reg) => cx.type_i32(),
InlineAsmRegClass::Xtensa(XtensaInlineAsmRegClass::freg) => cx.type_f32(),
InlineAsmRegClass::Xtensa(XtensaInlineAsmRegClass::breg) => cx.type_i1(),
InlineAsmRegClass::Bpf(BpfInlineAsmRegClass::reg) => cx.type_i64(),
InlineAsmRegClass::Bpf(BpfInlineAsmRegClass::wreg) => cx.type_i32(),
InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg) => cx.type_i8(),
Expand Down
31 changes: 31 additions & 0 deletions compiler/rustc_codegen_ssa/src/target_features.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -221,6 +221,35 @@ const WASM_ALLOWED_FEATURES: &[(&str, Option<Symbol>)] = &[
("nontrapping-fptoint", Some(sym::wasm_target_feature)),
];

const XTENSA_ALLOWED_FEATURES: &[(&str, Option<Symbol>)] = &[
("fp", Some(sym::xtensa_target_feature)),
("windowed", Some(sym::xtensa_target_feature)),
("bool", Some(sym::xtensa_target_feature)),
("loop", Some(sym::xtensa_target_feature)),
("sext", Some(sym::xtensa_target_feature)),
("nsa", Some(sym::xtensa_target_feature)),
("mul32", Some(sym::xtensa_target_feature)),
("mul32high", Some(sym::xtensa_target_feature)),
("div32", Some(sym::xtensa_target_feature)),
("mac16", Some(sym::xtensa_target_feature)),
("dfpaccel", Some(sym::xtensa_target_feature)),
("s32c1i", Some(sym::xtensa_target_feature)),
("threadptr", Some(sym::xtensa_target_feature)),
("extendedl32r", Some(sym::xtensa_target_feature)),
("atomctl", Some(sym::xtensa_target_feature)),
("memctl", Some(sym::xtensa_target_feature)),
("debug", Some(sym::xtensa_target_feature)),
("exception", Some(sym::xtensa_target_feature)),
("highpriinterrupts", Some(sym::xtensa_target_feature)),
("coprocessor", Some(sym::xtensa_target_feature)),
("interrupt", Some(sym::xtensa_target_feature)),
("rvector", Some(sym::xtensa_target_feature)),
("timerint", Some(sym::xtensa_target_feature)),
("prid", Some(sym::xtensa_target_feature)),
("regprotect", Some(sym::xtensa_target_feature)),
("miscsr", Some(sym::xtensa_target_feature)),
];

const BPF_ALLOWED_FEATURES: &[(&str, Option<Symbol>)] = &[("alu32", Some(sym::bpf_target_feature))];

/// When rustdoc is running, provide a list of all known features so that all their respective
Expand All @@ -237,6 +266,7 @@ pub fn all_known_features() -> impl Iterator<Item = (&'static str, Option<Symbol
.chain(MIPS_ALLOWED_FEATURES.iter())
.chain(RISCV_ALLOWED_FEATURES.iter())
.chain(WASM_ALLOWED_FEATURES.iter())
.chain(XTENSA_ALLOWED_FEATURES.iter())
.chain(BPF_ALLOWED_FEATURES.iter())
.cloned()
}
Expand All @@ -251,6 +281,7 @@ pub fn supported_target_features(sess: &Session) -> &'static [(&'static str, Opt
"powerpc" | "powerpc64" => POWERPC_ALLOWED_FEATURES,
"riscv32" | "riscv64" => RISCV_ALLOWED_FEATURES,
"wasm32" | "wasm64" => WASM_ALLOWED_FEATURES,
"xtensa" => XTENSA_ALLOWED_FEATURES,
"bpf" => BPF_ALLOWED_FEATURES,
_ => &[],
}
Expand Down
2 changes: 2 additions & 0 deletions compiler/rustc_span/src/symbol.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -385,6 +385,7 @@ symbols! {
braced_empty_structs,
branch,
breakpoint,
breg,
bridge,
bswap,
c_str,
Expand Down Expand Up @@ -1453,6 +1454,7 @@ symbols! {
x87_reg,
xer,
xmm_reg,
xtensa_target_feature,
ymm_reg,
zmm_reg,
}
Expand Down
28 changes: 28 additions & 0 deletions compiler/rustc_target/src/asm/mod.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -159,6 +159,7 @@ mod s390x;
mod spirv;
mod wasm;
mod x86;
mod xtensa;

pub use aarch64::{AArch64InlineAsmReg, AArch64InlineAsmRegClass};
pub use arm::{ArmInlineAsmReg, ArmInlineAsmRegClass};
Expand All @@ -172,6 +173,7 @@ pub use riscv::{RiscVInlineAsmReg, RiscVInlineAsmRegClass};
pub use s390x::{S390xInlineAsmReg, S390xInlineAsmRegClass};
pub use spirv::{SpirVInlineAsmReg, SpirVInlineAsmRegClass};
pub use wasm::{WasmInlineAsmReg, WasmInlineAsmRegClass};
pub use xtensa::{XtensaInlineAsmReg, XtensaInlineAsmRegClass};
pub use x86::{X86InlineAsmReg, X86InlineAsmRegClass};

#[derive(Copy, Clone, Encodable, Decodable, Debug, Eq, PartialEq, Hash)]
Expand All @@ -192,6 +194,7 @@ pub enum InlineAsmArch {
SpirV,
Wasm32,
Wasm64,
Xtensa,
Bpf,
Avr,
}
Expand All @@ -217,6 +220,7 @@ impl FromStr for InlineAsmArch {
"spirv" => Ok(Self::SpirV),
"wasm32" => Ok(Self::Wasm32),
"wasm64" => Ok(Self::Wasm64),
"xtensa" => Ok(Self::Xtensa),
"bpf" => Ok(Self::Bpf),
"avr" => Ok(Self::Avr),
_ => Err(()),
Expand Down Expand Up @@ -248,6 +252,7 @@ pub enum InlineAsmReg {
S390x(S390xInlineAsmReg),
SpirV(SpirVInlineAsmReg),
Wasm(WasmInlineAsmReg),
Xtensa(XtensaInlineAsmReg),
Bpf(BpfInlineAsmReg),
Avr(AvrInlineAsmReg),
// Placeholder for invalid register constraints for the current target
Expand All @@ -265,6 +270,7 @@ impl InlineAsmReg {
Self::Hexagon(r) => r.name(),
Self::Mips(r) => r.name(),
Self::S390x(r) => r.name(),
Self::Xtensa(r) => r.name(),
Self::Bpf(r) => r.name(),
Self::Avr(r) => r.name(),
Self::Err => "<reg>",
Expand All @@ -281,6 +287,7 @@ impl InlineAsmReg {
Self::Hexagon(r) => InlineAsmRegClass::Hexagon(r.reg_class()),
Self::Mips(r) => InlineAsmRegClass::Mips(r.reg_class()),
Self::S390x(r) => InlineAsmRegClass::S390x(r.reg_class()),
Self::Xtensa(r) => InlineAsmRegClass::Xtensa(r.reg_class()),
Self::Bpf(r) => InlineAsmRegClass::Bpf(r.reg_class()),
Self::Avr(r) => InlineAsmRegClass::Avr(r.reg_class()),
Self::Err => InlineAsmRegClass::Err,
Expand Down Expand Up @@ -330,6 +337,9 @@ impl InlineAsmReg {
InlineAsmArch::Wasm32 | InlineAsmArch::Wasm64 => {
Self::Wasm(WasmInlineAsmReg::parse(arch, has_feature, target, name)?)
}
InlineAsmArch::Xtensa => {
Self::Xtensa(XtensaInlineAsmReg::parse(arch, has_feature, target, &name)?)
}
InlineAsmArch::Bpf => {
Self::Bpf(BpfInlineAsmReg::parse(arch, has_feature, target, name)?)
}
Expand All @@ -356,6 +366,7 @@ impl InlineAsmReg {
Self::Hexagon(r) => r.emit(out, arch, modifier),
Self::Mips(r) => r.emit(out, arch, modifier),
Self::S390x(r) => r.emit(out, arch, modifier),
Self::Xtensa(r) => r.emit(out, arch, modifier),
Self::Bpf(r) => r.emit(out, arch, modifier),
Self::Avr(r) => r.emit(out, arch, modifier),
Self::Err => unreachable!("Use of InlineAsmReg::Err"),
Expand All @@ -372,6 +383,7 @@ impl InlineAsmReg {
Self::Hexagon(r) => r.overlapping_regs(|r| cb(Self::Hexagon(r))),
Self::Mips(_) => cb(self),
Self::S390x(_) => cb(self),
Self::Xtensa(_) => cb(self),
Self::Bpf(r) => r.overlapping_regs(|r| cb(Self::Bpf(r))),
Self::Avr(r) => r.overlapping_regs(|r| cb(Self::Avr(r))),
Self::Err => unreachable!("Use of InlineAsmReg::Err"),
Expand Down Expand Up @@ -403,6 +415,7 @@ pub enum InlineAsmRegClass {
S390x(S390xInlineAsmRegClass),
SpirV(SpirVInlineAsmRegClass),
Wasm(WasmInlineAsmRegClass),
Xtensa(XtensaInlineAsmRegClass),
Bpf(BpfInlineAsmRegClass),
Avr(AvrInlineAsmRegClass),
// Placeholder for invalid register constraints for the current target
Expand All @@ -423,6 +436,7 @@ impl InlineAsmRegClass {
Self::S390x(r) => r.name(),
Self::SpirV(r) => r.name(),
Self::Wasm(r) => r.name(),
Self::Xtensa(r) => r.name(),
Self::Bpf(r) => r.name(),
Self::Avr(r) => r.name(),
Self::Err => rustc_span::symbol::sym::reg,
Expand All @@ -445,6 +459,7 @@ impl InlineAsmRegClass {
Self::S390x(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::S390x),
Self::SpirV(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::SpirV),
Self::Wasm(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::Wasm),
Self::Xtensa(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::Xtensa),
Self::Bpf(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::Bpf),
Self::Avr(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::Avr),
Self::Err => unreachable!("Use of InlineAsmRegClass::Err"),
Expand Down Expand Up @@ -474,6 +489,7 @@ impl InlineAsmRegClass {
Self::S390x(r) => r.suggest_modifier(arch, ty),
Self::SpirV(r) => r.suggest_modifier(arch, ty),
Self::Wasm(r) => r.suggest_modifier(arch, ty),
Self::Xtensa(r) => r.suggest_modifier(arch, ty),
Self::Bpf(r) => r.suggest_modifier(arch, ty),
Self::Avr(r) => r.suggest_modifier(arch, ty),
Self::Err => unreachable!("Use of InlineAsmRegClass::Err"),
Expand All @@ -499,6 +515,7 @@ impl InlineAsmRegClass {
Self::S390x(r) => r.default_modifier(arch),
Self::SpirV(r) => r.default_modifier(arch),
Self::Wasm(r) => r.default_modifier(arch),
Self::Xtensa(r) => r.default_modifier(arch),
Self::Bpf(r) => r.default_modifier(arch),
Self::Avr(r) => r.default_modifier(arch),
Self::Err => unreachable!("Use of InlineAsmRegClass::Err"),
Expand All @@ -523,6 +540,7 @@ impl InlineAsmRegClass {
Self::S390x(r) => r.supported_types(arch),
Self::SpirV(r) => r.supported_types(arch),
Self::Wasm(r) => r.supported_types(arch),
Self::Xtensa(r) => r.supported_types(arch),
Self::Bpf(r) => r.supported_types(arch),
Self::Avr(r) => r.supported_types(arch),
Self::Err => unreachable!("Use of InlineAsmRegClass::Err"),
Expand Down Expand Up @@ -552,6 +570,7 @@ impl InlineAsmRegClass {
InlineAsmArch::Wasm32 | InlineAsmArch::Wasm64 => {
Self::Wasm(WasmInlineAsmRegClass::parse(arch, name)?)
}
InlineAsmArch::Xtensa => Self::Xtensa(XtensaInlineAsmRegClass::parse(arch, name)?),
InlineAsmArch::Bpf => Self::Bpf(BpfInlineAsmRegClass::parse(arch, name)?),
InlineAsmArch::Avr => Self::Avr(AvrInlineAsmRegClass::parse(arch, name)?),
})
Expand All @@ -572,6 +591,7 @@ impl InlineAsmRegClass {
Self::S390x(r) => r.valid_modifiers(arch),
Self::SpirV(r) => r.valid_modifiers(arch),
Self::Wasm(r) => r.valid_modifiers(arch),
Self::Xtensa(r) => r.valid_modifiers(arch),
Self::Bpf(r) => r.valid_modifiers(arch),
Self::Avr(r) => r.valid_modifiers(arch),
Self::Err => unreachable!("Use of InlineAsmRegClass::Err"),
Expand Down Expand Up @@ -623,6 +643,7 @@ impl fmt::Display for InlineAsmRegOrRegClass {
/// Set of types which can be used with a particular register class.
#[derive(Copy, Clone, Debug, Eq, PartialEq)]
pub enum InlineAsmType {
I1,
I8,
I16,
I32,
Expand All @@ -646,6 +667,7 @@ impl InlineAsmType {

pub fn size(self) -> Size {
Size::from_bytes(match self {
Self::I1 => return Size::from_bits(1),
Self::I8 => 1,
Self::I16 => 2,
Self::I32 => 4,
Expand All @@ -667,6 +689,7 @@ impl InlineAsmType {
impl fmt::Display for InlineAsmType {
fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
match *self {
Self::I1 => f.write_str("i1"),
Self::I8 => f.write_str("i8"),
Self::I16 => f.write_str("i16"),
Self::I32 => f.write_str("i32"),
Expand Down Expand Up @@ -754,6 +777,11 @@ pub fn allocatable_registers(
wasm::fill_reg_map(arch, has_feature, target, &mut map);
map
}
InlineAsmArch::Xtensa => {
let mut map = xtensa::regclass_map();
xtensa::fill_reg_map(arch, has_feature, target, &mut map);
map
}
InlineAsmArch::Bpf => {
let mut map = bpf::regclass_map();
bpf::fill_reg_map(arch, has_feature, target, &mut map);
Expand Down
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