From 8dee8000eeff4e63c1865856973929ea7a24a8c0 Mon Sep 17 00:00:00 2001
From: DarioGHub <49622669+DarioGHub@users.noreply.github.com>
Date: Sat, 28 May 2022 23:20:13 -0600
Subject: [PATCH] Fix DTR offset value (#8586)

Correct value from uart_registers.h mask
> #define UART_DTRN (BIT(29))
---
 cores/esp8266/esp8266_peri.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/cores/esp8266/esp8266_peri.h b/cores/esp8266/esp8266_peri.h
index 33b1e5822f..29a15744b0 100644
--- a/cores/esp8266/esp8266_peri.h
+++ b/cores/esp8266/esp8266_peri.h
@@ -255,7 +255,7 @@ extern volatile uint32_t* const esp8266_gpioToFn[16];
 //UART STATUS Registers Bits
 #define USTX    31 //TX PIN Level (Doesn't seem to work, always reads as 0 for both uarts. HW bug? Possible workaround: Enable loopback UxC0 |= 1<<UCLBE and read USRXD, see https://github.com/esp8266/Arduino/issues/7256 for discussion.)
 #define USRTS   30 //RTS PIN Level
-#define USDTR   39 //DTR PIN Level
+#define USDTR   29 //DTR PIN Level
 #define USTXC   16 //TX FIFO COUNT (8bit)
 #define USRXD   15 //RX PIN Level
 #define USCTS   14 //CTS PIN Level