diff --git a/cores/esp8266/hwdt_app_entry.cpp b/cores/esp8266/hwdt_app_entry.cpp
index 28b8914d90..0f0bee8d4e 100644
--- a/cores/esp8266/hwdt_app_entry.cpp
+++ b/cores/esp8266/hwdt_app_entry.cpp
@@ -277,6 +277,7 @@
 #include <esp8266_peri.h>
 #include <uart.h>
 #include <pgmspace.h>
+#include "umm_malloc/umm_malloc.h"
 #include "mmu_iram.h"
 
 extern "C" {
diff --git a/cores/esp8266/mmu_iram.cpp b/cores/esp8266/mmu_iram.cpp
index 9f1b05d455..c54e9994c8 100644
--- a/cores/esp8266/mmu_iram.cpp
+++ b/cores/esp8266/mmu_iram.cpp
@@ -197,9 +197,38 @@ extern void Cache_Read_Enable(uint8_t map, uint8_t p, uint8_t v);
 #endif  // #if (MMU_ICACHE_SIZE == 0x4000)
 
 /*
- * This wrapper is for running code from IROM (flash) before the SDK starts.
+ * This wrapper is for running code early from IROM (flash) before the SDK
+ * starts. Since the NONOS SDK will do a full and proper flash device init for
+ * speed and mode, we only do a minimum to make ICACHE functional, keeping IRAM
+ * use to a minimum. After the SDK has started, this function is not needed and
+ * must not be called.
  */
 void IRAM_ATTR mmu_wrap_irom_fn(void (*fn)(void)) {
+  // Cache Read must be disabled. This is always the case on entry when called
+  // from the right context.
+  // Cache_Read_Disable();
+
+  // The SPI_CS_SETUP parameter has been observed set by RTOS SDK and NONOS SDK
+  // as part of flash init/configuration. It may be necessary for some flash
+  // chips to perform correctly with ICACHE hardware access. Turning on and
+  // leaving it on should be okay.
+  //
+  // One SPI bus clock cycle time is inserted between #CS active and 1st SPI bus
+  // clock cycle. The number of clock cycles is in SPI_CNTRL2 SPI_SETUP_TIME,
+  // defaults to 1.
+  SPI0U |= SPIUCSSETUP; // SPI_CS_SETUP or BIT5
+
+  // phy_get_bb_evm is the key function, called from fix_cache_bug in the NONOS
+  // SDK. This addition resolves the PUYA Flash issue with exception 0, when
+  // early Cache_Read_Enable is used.
+  extern uint32_t phy_get_bb_evm(void); // undocumented
+  phy_get_bb_evm();
+
+  // For early Cache_Read_Enable, only do ICACHE_SIZE_16. With this option,
+  // Cache_Read_Disable will fully restore the original register states. With
+  // ICACHE_SIZE_32, one bit is missed when disabling. Leave the full access
+  // calls for the NONOS SDK.
+  // This only works with image slice 0, which is all we do presently.
   Cache_Read_Enable(0, 0, ICACHE_SIZE_16);
   fn();
   Cache_Read_Disable();
diff --git a/cores/esp8266/umm_malloc/umm_malloc_cfgport.h b/cores/esp8266/umm_malloc/umm_malloc_cfgport.h
index 7dccbff932..233671304f 100644
--- a/cores/esp8266/umm_malloc/umm_malloc_cfgport.h
+++ b/cores/esp8266/umm_malloc/umm_malloc_cfgport.h
@@ -27,7 +27,7 @@
  */
 
 /*
- * -DUMM_INIT_USE_IRAM
+ * -DUMM_INIT_USE_ICACHE
  *
  * Historically, the umm_init() call path has been in IRAM. The umm_init() call
  * path is now in ICACHE (flash). Use the build option UMM_INIT_USE_IRAM to
@@ -37,10 +37,16 @@
  * app_entry_redefinable() in core_esp8266_app_entry_noextra4k.cpp for an
  * example of how to toggle between ICACHE and IRAM in your build.
  *
- * The default is to use ICACHE.
+ * ~The default is to use ICACHE.~
+ * For now revert default back to IRAM
+ * define UMM_INIT_USE_ICACHE to use ICACHE/IROM
  */
-// #define UMM_INIT_USE_IRAM 1
-
+#ifdef UMM_INIT_USE_ICACHE
+#undef UMM_INIT_USE_IRAM
+#else
+#undef UMM_INIT_USE_IRAM
+#define UMM_INIT_USE_IRAM 1
+#endif
 
 /*
  * Start addresses and the size of the heap