From f92d1df464275f617295fb483678699b0840baa0 Mon Sep 17 00:00:00 2001 From: Jesse Braham Date: Wed, 11 Jan 2023 11:00:52 -0800 Subject: [PATCH] New SVDs for all devices --- svd/esp32.svd | 1482 +-- svd/esp32c2.svd | 108 +- svd/esp32c3.svd | 10 +- svd/esp32c6.svd | 3430 +----- svd/esp32h2.svd | 28612 +++++++++++++++++++++++++++++++++++++++------- svd/esp32s2.svd | 136 +- svd/esp32s3.svd | 549 +- 7 files changed, 25449 insertions(+), 8878 deletions(-) diff --git a/svd/esp32.svd b/svd/esp32.svd index 783023f..913f39d 100644 --- a/svd/esp32.svd +++ b/svd/esp32.svd @@ -3,11 +3,11 @@ ESPRESSIF SYSTEMS (SHANGHAI) CO., LTD. ESPRESSIF ESP32 - ESP32 - 8 + ESP32 Series + 9 32-bit MCU & 2.4 GHz Wi-Fi & Bluetooth/Bluetooth LE - Copyright 2022 Espressif Systems (Shanghai) PTE LTD + Copyright 2023 Espressif Systems (Shanghai) PTE LTD Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -20578,111 +20578,114 @@ - U0_CONF0 + 8 + 0xC + 0-7 + U%s_CONF0 0x0 0x20 0x00003C10 - FILTER_THRES_U0 + FILTER_THRES This register is used to filter pluse whose width is smaller than this value for unit0. 0 10 read-write - FILTER_EN_U0 + FILTER_EN This is the enable bit for filtering input signals for unit0. 10 1 read-write - THR_ZERO_EN_U0 + THR_ZERO_EN This is the enable bit for comparing unit0's count with 0 value. 11 1 read-write - THR_H_LIM_EN_U0 + THR_H_LIM_EN This is the enable bit for comparing unit0's count with thr_h_lim value. 12 1 read-write - THR_L_LIM_EN_U0 + THR_L_LIM_EN This is the enable bit for comparing unit0's count with thr_l_lim value. 13 1 read-write - THR_THRES0_EN_U0 + THR_THRES0_EN This is the enable bit for comparing unit0's count with thres0 value. 14 1 read-write - THR_THRES1_EN_U0 + THR_THRES1_EN This is the enable bit for comparing unit0's count with thres1 value . 15 1 read-write - CH0_NEG_MODE_U0 + CH0_NEG_MODE This register is used to control the mode of channel0's input negedge signal for unit0. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden 16 2 read-write - CH0_POS_MODE_U0 + CH0_POS_MODE This register is used to control the mode of channel0's input posedge signal for unit0. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden 18 2 read-write - CH0_HCTRL_MODE_U0 + CH0_HCTRL_MODE This register is used to control the mode of channel0's high control signal for unit0. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden 20 2 read-write - CH0_LCTRL_MODE_U0 + CH0_LCTRL_MODE This register is used to control the mode of channel0's low control signal for unit0. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden 22 2 read-write - CH1_NEG_MODE_U0 + CH1_NEG_MODE This register is used to control the mode of channel1's input negedge signal for unit0. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden 24 2 read-write - CH1_POS_MODE_U0 + CH1_POS_MODE This register is used to control the mode of channel1's input posedge signal for unit0. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden 26 2 read-write - CH1_HCTRL_MODE_U0 + CH1_HCTRL_MODE This register is used to control the mode of channel1's high control signal for unit0. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden 28 2 read-write - CH1_LCTRL_MODE_U0 + CH1_LCTRL_MODE This register is used to control the mode of channel1's low control signal for unit0. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden 30 2 @@ -20691,19 +20694,22 @@ - U0_CONF1 + 8 + 0xC + 0-7 + U%s_CONF1 0x4 0x20 - CNT_THRES0_U0 + CNT_THRES0 This register is used to configure thres0 value for unit0. 0 16 read-write - CNT_THRES1_U0 + CNT_THRES1 This register is used to configure thres1 value for unit0. 16 16 @@ -20712,19 +20718,22 @@ - U0_CONF2 + 8 + 0xC + 0-7 + U%s_CONF2 0x8 0x20 - CNT_H_LIM_U0 + CNT_H_LIM This register is used to configure thr_h_lim value for unit0. 0 16 read-write - CNT_L_LIM_U0 + CNT_L_LIM This register is used to confiugre thr_l_lim value for unit0. 16 16 @@ -20733,1097 +20742,15 @@ - U1_CONF0 - 0xC - 0x20 - 0x00003C10 - - - FILTER_THRES_U1 - This register is used to filter pluse whose width is smaller than this value for unit1. - 0 - 10 - read-write - - - FILTER_EN_U1 - This is the enable bit for filtering input signals for unit1. - 10 - 1 - read-write - - - THR_ZERO_EN_U1 - This is the enable bit for comparing unit1's count with 0 value. - 11 - 1 - read-write - - - THR_H_LIM_EN_U1 - This is the enable bit for comparing unit1's count with thr_h_lim value. - 12 - 1 - read-write - - - THR_L_LIM_EN_U1 - This is the enable bit for comparing unit1's count with thr_l_lim value. - 13 - 1 - read-write - - - THR_THRES0_EN_U1 - This is the enable bit for comparing unit1's count with thres0 value. - 14 - 1 - read-write - - - THR_THRES1_EN_U1 - This is the enable bit for comparing unit1's count with thres1 value . - 15 - 1 - read-write - - - CH0_NEG_MODE_U1 - This register is used to control the mode of channel0's input negedge signal for unit1. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden - 16 - 2 - read-write - - - CH0_POS_MODE_U1 - This register is used to control the mode of channel0's input posedge signal for unit1. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden - 18 - 2 - read-write - - - CH0_HCTRL_MODE_U1 - This register is used to control the mode of channel0's high control signal for unit1. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden - 20 - 2 - read-write - - - CH0_LCTRL_MODE_U1 - This register is used to control the mode of channel0's low control signal for unit1. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden - 22 - 2 - read-write - - - CH1_NEG_MODE_U1 - This register is used to control the mode of channel1's input negedge signal for unit1. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden - 24 - 2 - read-write - - - CH1_POS_MODE_U1 - This register is used to control the mode of channel1's input posedge signal for unit1. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden - 26 - 2 - read-write - - - CH1_HCTRL_MODE_U1 - This register is used to control the mode of channel1's high control signal for unit1. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden - 28 - 2 - read-write - - - CH1_LCTRL_MODE_U1 - This register is used to control the mode of channel1's low control signal for unit1. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden - 30 - 2 - read-write - - - - - U1_CONF1 - 0x10 - 0x20 - - - CNT_THRES0_U1 - This register is used to configure thres0 value for unit1. - 0 - 16 - read-write - - - CNT_THRES1_U1 - This register is used to configure thres1 value for unit1. - 16 - 16 - read-write - - - - - U1_CONF2 - 0x14 - 0x20 - - - CNT_H_LIM_U1 - This register is used to configure thr_h_lim value for unit1. - 0 - 16 - read-write - - - CNT_L_LIM_U1 - This register is used to confiugre thr_l_lim value for unit1. - 16 - 16 - read-write - - - - - U2_CONF0 - 0x18 - 0x20 - 0x00003C10 - - - FILTER_THRES_U2 - This register is used to filter pluse whose width is smaller than this value for unit2. - 0 - 10 - read-write - - - FILTER_EN_U2 - This is the enable bit for filtering input signals for unit2. - 10 - 1 - read-write - - - THR_ZERO_EN_U2 - This is the enable bit for comparing unit2's count with 0 value. - 11 - 1 - read-write - - - THR_H_LIM_EN_U2 - This is the enable bit for comparing unit2's count with thr_h_lim value. - 12 - 1 - read-write - - - THR_L_LIM_EN_U2 - This is the enable bit for comparing unit2's count with thr_l_lim value. - 13 - 1 - read-write - - - THR_THRES0_EN_U2 - This is the enable bit for comparing unit2's count with thres0 value. - 14 - 1 - read-write - - - THR_THRES1_EN_U2 - This is the enable bit for comparing unit2's count with thres1 value . - 15 - 1 - read-write - - - CH0_NEG_MODE_U2 - This register is used to control the mode of channel0's input negedge signal for unit2. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden - 16 - 2 - read-write - - - CH0_POS_MODE_U2 - This register is used to control the mode of channel0's input posedge signal for unit2. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden - 18 - 2 - read-write - - - CH0_HCTRL_MODE_U2 - This register is used to control the mode of channel0's high control signal for unit2. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden - 20 - 2 - read-write - - - CH0_LCTRL_MODE_U2 - This register is used to control the mode of channel0's low control signal for unit2. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden - 22 - 2 - read-write - - - CH1_NEG_MODE_U2 - This register is used to control the mode of channel1's input negedge signal for unit2. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden - 24 - 2 - read-write - - - CH1_POS_MODE_U2 - This register is used to control the mode of channel1's input posedge signal for unit2. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden - 26 - 2 - read-write - - - CH1_HCTRL_MODE_U2 - This register is used to control the mode of channel1's high control signal for unit2. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden - 28 - 2 - read-write - - - CH1_LCTRL_MODE_U2 - This register is used to control the mode of channel1's low control signal for unit2. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden - 30 - 2 - read-write - - - - - U2_CONF1 - 0x1C - 0x20 - - - CNT_THRES0_U2 - This register is used to configure thres0 value for unit2. - 0 - 16 - read-write - - - CNT_THRES1_U2 - This register is used to configure thres1 value for unit2. - 16 - 16 - read-write - - - - - U2_CONF2 - 0x20 - 0x20 - - - CNT_H_LIM_U2 - This register is used to configure thr_h_lim value for unit2. - 0 - 16 - read-write - - - CNT_L_LIM_U2 - This register is used to confiugre thr_l_lim value for unit2. - 16 - 16 - read-write - - - - - U3_CONF0 - 0x24 - 0x20 - 0x00003C10 - - - FILTER_THRES_U3 - This register is used to filter pluse whose width is smaller than this value for unit3. - 0 - 10 - read-write - - - FILTER_EN_U3 - This is the enable bit for filtering input signals for unit3. - 10 - 1 - read-write - - - THR_ZERO_EN_U3 - This is the enable bit for comparing unit3's count with 0 value. - 11 - 1 - read-write - - - THR_H_LIM_EN_U3 - This is the enable bit for comparing unit3's count with thr_h_lim value. - 12 - 1 - read-write - - - THR_L_LIM_EN_U3 - This is the enable bit for comparing unit3's count with thr_l_lim value. - 13 - 1 - read-write - - - THR_THRES0_EN_U3 - This is the enable bit for comparing unit3's count with thres0 value. - 14 - 1 - read-write - - - THR_THRES1_EN_U3 - This is the enable bit for comparing unit3's count with thres1 value . - 15 - 1 - read-write - - - CH0_NEG_MODE_U3 - This register is used to control the mode of channel0's input negedge signal for unit3. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden - 16 - 2 - read-write - - - CH0_POS_MODE_U3 - This register is used to control the mode of channel0's input posedge signal for unit3. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden - 18 - 2 - read-write - - - CH0_HCTRL_MODE_U3 - This register is used to control the mode of channel0's high control signal for unit3. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden - 20 - 2 - read-write - - - CH0_LCTRL_MODE_U3 - This register is used to control the mode of channel0's low control signal for unit3. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden - 22 - 2 - read-write - - - CH1_NEG_MODE_U3 - This register is used to control the mode of channel1's input negedge signal for unit3. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden - 24 - 2 - read-write - - - CH1_POS_MODE_U3 - This register is used to control the mode of channel1's input posedge signal for unit3. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden - 26 - 2 - read-write - - - CH1_HCTRL_MODE_U3 - This register is used to control the mode of channel1's high control signal for unit3. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden - 28 - 2 - read-write - - - CH1_LCTRL_MODE_U3 - This register is used to control the mode of channel1's low control signal for unit3. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden - 30 - 2 - read-write - - - - - U3_CONF1 - 0x28 - 0x20 - - - CNT_THRES0_U3 - This register is used to configure thres0 value for unit3. - 0 - 16 - read-write - - - CNT_THRES1_U3 - This register is used to configure thres1 value for unit3. - 16 - 16 - read-write - - - - - U3_CONF2 - 0x2C - 0x20 - - - CNT_H_LIM_U3 - This register is used to configure thr_h_lim value for unit3. - 0 - 16 - read-write - - - CNT_L_LIM_U3 - This register is used to confiugre thr_l_lim value for unit3. - 16 - 16 - read-write - - - - - U4_CONF0 - 0x30 - 0x20 - 0x00003C10 - - - FILTER_THRES_U4 - This register is used to filter pluse whose width is smaller than this value for unit4. - 0 - 10 - read-write - - - FILTER_EN_U4 - This is the enable bit for filtering input signals for unit4. - 10 - 1 - read-write - - - THR_ZERO_EN_U4 - This is the enable bit for comparing unit4's count with 0 value. - 11 - 1 - read-write - - - THR_H_LIM_EN_U4 - This is the enable bit for comparing unit4's count with thr_h_lim value. - 12 - 1 - read-write - - - THR_L_LIM_EN_U4 - This is the enable bit for comparing unit4's count with thr_l_lim value. - 13 - 1 - read-write - - - THR_THRES0_EN_U4 - This is the enable bit for comparing unit4's count with thres0 value. - 14 - 1 - read-write - - - THR_THRES1_EN_U4 - This is the enable bit for comparing unit4's count with thres1 value . - 15 - 1 - read-write - - - CH0_NEG_MODE_U4 - This register is used to control the mode of channel0's input negedge signal for unit4. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden - 16 - 2 - read-write - - - CH0_POS_MODE_U4 - This register is used to control the mode of channel0's input posedge signal for unit4. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden - 18 - 2 - read-write - - - CH0_HCTRL_MODE_U4 - This register is used to control the mode of channel0's high control signal for unit4. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden - 20 - 2 - read-write - - - CH0_LCTRL_MODE_U4 - This register is used to control the mode of channel0's low control signal for unit4. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden - 22 - 2 - read-write - - - CH1_NEG_MODE_U4 - This register is used to control the mode of channel1's input negedge signal for unit4. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden - 24 - 2 - read-write - - - CH1_POS_MODE_U4 - This register is used to control the mode of channel1's input posedge signal for unit4. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden - 26 - 2 - read-write - - - CH1_HCTRL_MODE_U4 - This register is used to control the mode of channel1's high control signal for unit4. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden - 28 - 2 - read-write - - - CH1_LCTRL_MODE_U4 - This register is used to control the mode of channel1's low control signal for unit4. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden - 30 - 2 - read-write - - - - - U4_CONF1 - 0x34 - 0x20 - - - CNT_THRES0_U4 - This register is used to configure thres0 value for unit4. - 0 - 16 - read-write - - - CNT_THRES1_U4 - This register is used to configure thres1 value for unit4. - 16 - 16 - read-write - - - - - U4_CONF2 - 0x38 - 0x20 - - - CNT_H_LIM_U4 - This register is used to configure thr_h_lim value for unit4. - 0 - 16 - read-write - - - CNT_L_LIM_U4 - This register is used to confiugre thr_l_lim value for unit4. - 16 - 16 - read-write - - - - - U5_CONF0 - 0x3C - 0x20 - 0x00003C10 - - - FILTER_THRES_U5 - This register is used to filter pluse whose width is smaller than this value for unit5. - 0 - 10 - read-write - - - FILTER_EN_U5 - This is the enable bit for filtering input signals for unit5. - 10 - 1 - read-write - - - THR_ZERO_EN_U5 - This is the enable bit for comparing unit5's count with 0 value. - 11 - 1 - read-write - - - THR_H_LIM_EN_U5 - This is the enable bit for comparing unit5's count with thr_h_lim value. - 12 - 1 - read-write - - - THR_L_LIM_EN_U5 - This is the enable bit for comparing unit5's count with thr_l_lim value. - 13 - 1 - read-write - - - THR_THRES0_EN_U5 - This is the enable bit for comparing unit5's count with thres0 value. - 14 - 1 - read-write - - - THR_THRES1_EN_U5 - This is the enable bit for comparing unit5's count with thres1 value . - 15 - 1 - read-write - - - CH0_NEG_MODE_U5 - This register is used to control the mode of channel0's input negedge signal for unit5. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden - 16 - 2 - read-write - - - CH0_POS_MODE_U5 - This register is used to control the mode of channel0's input posedge signal for unit5. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden - 18 - 2 - read-write - - - CH0_HCTRL_MODE_U5 - This register is used to control the mode of channel0's high control signal for unit5. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden - 20 - 2 - read-write - - - CH0_LCTRL_MODE_U5 - This register is used to control the mode of channel0's low control signal for unit5. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden - 22 - 2 - read-write - - - CH1_NEG_MODE_U5 - This register is used to control the mode of channel1's input negedge signal for unit5. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden - 24 - 2 - read-write - - - CH1_POS_MODE_U5 - This register is used to control the mode of channel1's input posedge signal for unit5. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden - 26 - 2 - read-write - - - CH1_HCTRL_MODE_U5 - This register is used to control the mode of channel1's high control signal for unit5. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden - 28 - 2 - read-write - - - CH1_LCTRL_MODE_U5 - This register is used to control the mode of channel1's low control signal for unit5. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden - 30 - 2 - read-write - - - - - U5_CONF1 - 0x40 - 0x20 - - - CNT_THRES0_U5 - This register is used to configure thres0 value for unit5. - 0 - 16 - read-write - - - CNT_THRES1_U5 - This register is used to configure thres1 value for unit5. - 16 - 16 - read-write - - - - - U5_CONF2 - 0x44 - 0x20 - - - CNT_H_LIM_U5 - This register is used to configure thr_h_lim value for unit5. - 0 - 16 - read-write - - - CNT_L_LIM_U5 - This register is used to confiugre thr_l_lim value for unit5. - 16 - 16 - read-write - - - - - U6_CONF0 - 0x48 - 0x20 - 0x00003C10 - - - FILTER_THRES_U6 - This register is used to filter pluse whose width is smaller than this value for unit6. - 0 - 10 - read-write - - - FILTER_EN_U6 - This is the enable bit for filtering input signals for unit6. - 10 - 1 - read-write - - - THR_ZERO_EN_U6 - This is the enable bit for comparing unit6's count with 0 value. - 11 - 1 - read-write - - - THR_H_LIM_EN_U6 - This is the enable bit for comparing unit6's count with thr_h_lim value. - 12 - 1 - read-write - - - THR_L_LIM_EN_U6 - This is the enable bit for comparing unit6's count with thr_l_lim value. - 13 - 1 - read-write - - - THR_THRES0_EN_U6 - This is the enable bit for comparing unit6's count with thres0 value. - 14 - 1 - read-write - - - THR_THRES1_EN_U6 - This is the enable bit for comparing unit6's count with thres1 value . - 15 - 1 - read-write - - - CH0_NEG_MODE_U6 - This register is used to control the mode of channel0's input negedge signal for unit6. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden - 16 - 2 - read-write - - - CH0_POS_MODE_U6 - This register is used to control the mode of channel0's input posedge signal for unit6. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden - 18 - 2 - read-write - - - CH0_HCTRL_MODE_U6 - This register is used to control the mode of channel0's high control signal for unit6. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden - 20 - 2 - read-write - - - CH0_LCTRL_MODE_U6 - This register is used to control the mode of channel0's low control signal for unit6. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden - 22 - 2 - read-write - - - CH1_NEG_MODE_U6 - This register is used to control the mode of channel1's input negedge signal for unit6. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden - 24 - 2 - read-write - - - CH1_POS_MODE_U6 - This register is used to control the mode of channel1's input posedge signal for unit6. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden - 26 - 2 - read-write - - - CH1_HCTRL_MODE_U6 - This register is used to control the mode of channel1's high control signal for unit6. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden - 28 - 2 - read-write - - - CH1_LCTRL_MODE_U6 - This register is used to control the mode of channel1's low control signal for unit6. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden - 30 - 2 - read-write - - - - - U6_CONF1 - 0x4C - 0x20 - - - CNT_THRES0_U6 - This register is used to configure thres0 value for unit6. - 0 - 16 - read-write - - - CNT_THRES1_U6 - This register is used to configure thres1 value for unit6. - 16 - 16 - read-write - - - - - U6_CONF2 - 0x50 - 0x20 - - - CNT_H_LIM_U6 - This register is used to configure thr_h_lim value for unit6. - 0 - 16 - read-write - - - CNT_L_LIM_U6 - This register is used to confiugre thr_l_lim value for unit6. - 16 - 16 - read-write - - - - - U7_CONF0 - 0x54 - 0x20 - 0x00003C10 - - - FILTER_THRES_U7 - This register is used to filter pluse whose width is smaller than this value for unit7. - 0 - 10 - read-write - - - FILTER_EN_U7 - This is the enable bit for filtering input signals for unit7. - 10 - 1 - read-write - - - THR_ZERO_EN_U7 - This is the enable bit for comparing unit7's count with 0 value. - 11 - 1 - read-write - - - THR_H_LIM_EN_U7 - This is the enable bit for comparing unit7's count with thr_h_lim value. - 12 - 1 - read-write - - - THR_L_LIM_EN_U7 - This is the enable bit for comparing unit7's count with thr_l_lim value. - 13 - 1 - read-write - - - THR_THRES0_EN_U7 - This is the enable bit for comparing unit7's count with thres0 value. - 14 - 1 - read-write - - - THR_THRES1_EN_U7 - This is the enable bit for comparing unit7's count with thres1 value . - 15 - 1 - read-write - - - CH0_NEG_MODE_U7 - This register is used to control the mode of channel0's input negedge signal for unit7. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden - 16 - 2 - read-write - - - CH0_POS_MODE_U7 - This register is used to control the mode of channel0's input posedge signal for unit7. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden - 18 - 2 - read-write - - - CH0_HCTRL_MODE_U7 - This register is used to control the mode of channel0's high control signal for unit7. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden - 20 - 2 - read-write - - - CH0_LCTRL_MODE_U7 - This register is used to control the mode of channel0's low control signal for unit7. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden - 22 - 2 - read-write - - - CH1_NEG_MODE_U7 - This register is used to control the mode of channel1's input negedge signal for unit7. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden - 24 - 2 - read-write - - - CH1_POS_MODE_U7 - This register is used to control the mode of channel1's input posedge signal for unit7. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden - 26 - 2 - read-write - - - CH1_HCTRL_MODE_U7 - This register is used to control the mode of channel1's high control signal for unit7. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden - 28 - 2 - read-write - - - CH1_LCTRL_MODE_U7 - This register is used to control the mode of channel1's low control signal for unit7. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden - 30 - 2 - read-write - - - - - U7_CONF1 - 0x58 - 0x20 - - - CNT_THRES0_U7 - This register is used to configure thres0 value for unit7. - 0 - 16 - read-write - - - CNT_THRES1_U7 - This register is used to configure thres1 value for unit7. - 16 - 16 - read-write - - - - - U7_CONF2 - 0x5C - 0x20 - - - CNT_H_LIM_U7 - This register is used to configure thr_h_lim value for unit7. - 0 - 16 - read-write - - - CNT_L_LIM_U7 - This register is used to confiugre thr_l_lim value for unit7. - 16 - 16 - read-write - - - - - U0_CNT + 8 + 0x4 + 0-7 + U%s_CNT 0x60 0x20 - PLUS_CNT_U0 + CNT This register stores the current pulse count value for unit0. 0 16 @@ -21831,160 +20758,62 @@ - - U1_CNT - 0x64 - 0x20 - - - PLUS_CNT_U1 - This register stores the current pulse count value for unit1. - 0 - 16 - read-only - - - - - U2_CNT - 0x68 - 0x20 - - - PLUS_CNT_U2 - This register stores the current pulse count value for unit2. - 0 - 16 - read-only - - - - - U3_CNT - 0x6C - 0x20 - - - PLUS_CNT_U3 - This register stores the current pulse count value for unit3. - 0 - 16 - read-only - - - - - U4_CNT - 0x70 - 0x20 - - - PLUS_CNT_U4 - This register stores the current pulse count value for unit4. - 0 - 16 - read-only - - - - - U5_CNT - 0x74 - 0x20 - - - PLUS_CNT_U5 - This register stores the current pulse count value for unit5. - 0 - 16 - read-only - - - - - U6_CNT - 0x78 - 0x20 - - - PLUS_CNT_U6 - This register stores the current pulse count value for unit6. - 0 - 16 - read-only - - - - - U7_CNT - 0x7C - 0x20 - - - PLUS_CNT_U7 - This register stores the current pulse count value for unit7. - 0 - 16 - read-only - - - INT_RAW 0x80 0x20 - CNT_THR_EVENT_U0_INT_RAW + CNT_THR_EVENT_U0 This is the interrupt raw bit for channel0 event. 0 1 read-only - CNT_THR_EVENT_U1_INT_RAW + CNT_THR_EVENT_U1 This is the interrupt raw bit for channel1 event. 1 1 read-only - CNT_THR_EVENT_U2_INT_RAW + CNT_THR_EVENT_U2 This is the interrupt raw bit for channel2 event. 2 1 read-only - CNT_THR_EVENT_U3_INT_RAW + CNT_THR_EVENT_U3 This is the interrupt raw bit for channel3 event. 3 1 read-only - CNT_THR_EVENT_U4_INT_RAW + CNT_THR_EVENT_U4 This is the interrupt raw bit for channel4 event. 4 1 read-only - CNT_THR_EVENT_U5_INT_RAW + CNT_THR_EVENT_U5 This is the interrupt raw bit for channel5 event. 5 1 read-only - CNT_THR_EVENT_U6_INT_RAW + CNT_THR_EVENT_U6 This is the interrupt raw bit for channel6 event. 6 1 read-only - CNT_THR_EVENT_U7_INT_RAW + CNT_THR_EVENT_U7 This is the interrupt raw bit for channel7 event. 7 1 @@ -21998,56 +20827,56 @@ 0x20 - CNT_THR_EVENT_U0_INT_ST + CNT_THR_EVENT_U0 This is the interrupt status bit for channel0 event. 0 1 read-only - CNT_THR_EVENT_U1_INT_ST + CNT_THR_EVENT_U1 This is the interrupt status bit for channel1 event. 1 1 read-only - CNT_THR_EVENT_U2_INT_ST + CNT_THR_EVENT_U2 This is the interrupt status bit for channel2 event. 2 1 read-only - CNT_THR_EVENT_U3_INT_ST + CNT_THR_EVENT_U3 This is the interrupt status bit for channel3 event. 3 1 read-only - CNT_THR_EVENT_U4_INT_ST + CNT_THR_EVENT_U4 This is the interrupt status bit for channel4 event. 4 1 read-only - CNT_THR_EVENT_U5_INT_ST + CNT_THR_EVENT_U5 This is the interrupt status bit for channel5 event. 5 1 read-only - CNT_THR_EVENT_U6_INT_ST + CNT_THR_EVENT_U6 This is the interrupt status bit for channel6 event. 6 1 read-only - CNT_THR_EVENT_U7_INT_ST + CNT_THR_EVENT_U7 This is the interrupt status bit for channel7 event. 7 1 @@ -22061,56 +20890,56 @@ 0x20 - CNT_THR_EVENT_U0_INT_ENA + CNT_THR_EVENT_U0 This is the interrupt enable bit for channel0 event. 0 1 read-write - CNT_THR_EVENT_U1_INT_ENA + CNT_THR_EVENT_U1 This is the interrupt enable bit for channel1 event. 1 1 read-write - CNT_THR_EVENT_U2_INT_ENA + CNT_THR_EVENT_U2 This is the interrupt enable bit for channel2 event. 2 1 read-write - CNT_THR_EVENT_U3_INT_ENA + CNT_THR_EVENT_U3 This is the interrupt enable bit for channel3 event. 3 1 read-write - CNT_THR_EVENT_U4_INT_ENA + CNT_THR_EVENT_U4 This is the interrupt enable bit for channel4 event. 4 1 read-write - CNT_THR_EVENT_U5_INT_ENA + CNT_THR_EVENT_U5 This is the interrupt enable bit for channel5 event. 5 1 read-write - CNT_THR_EVENT_U6_INT_ENA + CNT_THR_EVENT_U6 This is the interrupt enable bit for channel6 event. 6 1 read-write - CNT_THR_EVENT_U7_INT_ENA + CNT_THR_EVENT_U7 This is the interrupt enable bit for channel7 event. 7 1 @@ -22124,56 +20953,56 @@ 0x20 - CNT_THR_EVENT_U0_INT_CLR + CNT_THR_EVENT_U0 Set this bit to clear channel0 event interrupt. 0 1 write-only - CNT_THR_EVENT_U1_INT_CLR + CNT_THR_EVENT_U1 Set this bit to clear channel1 event interrupt. 1 1 write-only - CNT_THR_EVENT_U2_INT_CLR + CNT_THR_EVENT_U2 Set this bit to clear channel2 event interrupt. 2 1 write-only - CNT_THR_EVENT_U3_INT_CLR + CNT_THR_EVENT_U3 Set this bit to clear channel3 event interrupt. 3 1 write-only - CNT_THR_EVENT_U4_INT_CLR + CNT_THR_EVENT_U4 Set this bit to clear channel4 event interrupt. 4 1 write-only - CNT_THR_EVENT_U5_INT_CLR + CNT_THR_EVENT_U5 Set this bit to clear channel5 event interrupt. 5 1 write-only - CNT_THR_EVENT_U6_INT_CLR + CNT_THR_EVENT_U6 Set this bit to clear channel6 event interrupt. 6 1 write-only - CNT_THR_EVENT_U7_INT_CLR + CNT_THR_EVENT_U7 Set this bit to clear channel7 event interrupt. 7 1 @@ -22182,7 +21011,10 @@ - U0_STATUS + 8 + 0x4 + 0-7 + U%s_STATUS 0x90 0x20 @@ -22193,134 +21025,43 @@ read-only - STATUS_CNT_MODE + ZERO_MODE 0 2 read-write - STATUS_THRES1 + THRES1 2 1 read-write - STATUS_THRES0 + THRES0 3 1 read-write - STATUS_L_LIM + L_LIM 4 1 read-write - STATUS_H_LIM + H_LIM 5 1 read-write - STATUS_ZERO + ZERO 6 1 read-write - - U1_STATUS - 0x94 - 0x20 - - - CORE_STATUS_U1 - 0 - 32 - read-only - - - - - U2_STATUS - 0x98 - 0x20 - - - CORE_STATUS_U2 - 0 - 32 - read-only - - - - - U3_STATUS - 0x9C - 0x20 - - - CORE_STATUS_U3 - 0 - 32 - read-only - - - - - U4_STATUS - 0xA0 - 0x20 - - - CORE_STATUS_U4 - 0 - 32 - read-only - - - - - U5_STATUS - 0xA4 - 0x20 - - - CORE_STATUS_U5 - 0 - 32 - read-only - - - - - U6_STATUS - 0xA8 - 0x20 - - - CORE_STATUS_U6 - 0 - 32 - read-only - - - - - U7_STATUS - 0xAC - 0x20 - - - CORE_STATUS_U7 - 0 - 32 - read-only - - - CTRL 0xB0 @@ -22328,7 +21069,7 @@ 0x00005555 - PLUS_CNT_RST_U0 + CNT_RST_U0 Set this bit to clear unit0's counter. 0 1 @@ -22342,7 +21083,7 @@ read-write - PLUS_CNT_RST_U1 + CNT_RST_U1 Set this bit to clear unit1's counter. 2 1 @@ -22356,7 +21097,7 @@ read-write - PLUS_CNT_RST_U2 + CNT_RST_U2 Set this bit to clear unit2's counter. 4 1 @@ -22370,7 +21111,7 @@ read-write - PLUS_CNT_RST_U3 + CNT_RST_U3 Set this bit to clear unit3's counter. 6 1 @@ -22384,7 +21125,7 @@ read-write - PLUS_CNT_RST_U4 + CNT_RST_U4 Set this bit to clear unit4's counter. 8 1 @@ -22398,7 +21139,7 @@ read-write - PLUS_CNT_RST_U5 + CNT_RST_U5 Set this bit to clear unit5's counter. 10 1 @@ -22412,7 +21153,7 @@ read-write - PLUS_CNT_RST_U6 + CNT_RST_U6 Set this bit to clear unit6's counter. 12 1 @@ -22426,7 +21167,7 @@ read-write - PLUS_CNT_RST_U7 + CNT_RST_U7 Set this bit to clear unit7's counter. 14 1 @@ -31627,7 +30368,7 @@ IDINTEN[4]: DU Interrupt. 32 0x4 - TEXT_%s + TEXT%s 0x0 0x20 @@ -31635,7 +30376,7 @@ IDINTEN[4]: DU Interrupt. TEXT SHA Message block and hash result register. 0 - 8 + 32 read-write @@ -31656,7 +30397,7 @@ IDINTEN[4]: DU Interrupt. SHA1_CONTINUE - 0x80 + 0x84 0x20 @@ -31692,7 +30433,7 @@ IDINTEN[4]: DU Interrupt. SHA-1 operation status: 1 if the SHA accelerator is processing data, 0 if it is idle. 0 1 - write-only + read-only @@ -31712,7 +30453,7 @@ IDINTEN[4]: DU Interrupt. SHA256_LOAD - 0x90 + 0x98 0x20 @@ -42660,12 +41401,14 @@ IDINTEN[4]: DU Interrupt. Baud Rate Prescaler, determines the frequency dividing ratio. 0 14 + read-write SYNC_JUMP_WIDTH Synchronization Jump Width (SJW), 1 \verb+~+ 14 Tq wide. 14 2 + read-write @@ -42680,18 +41423,21 @@ IDINTEN[4]: DU Interrupt. The width of PBS1. 0 4 + read-write TIME_SEG2 The width of PBS2. 4 3 + read-write TIME_SAMP The number of sample points. 0: the bus is sampled once; 1: the bus is sampled three times 7 1 + read-write @@ -42751,6 +41497,7 @@ IDINTEN[4]: DU Interrupt. Error warning threshold. In the case when any of a error counter value exceeds the threshold, or all the error counter values are below the threshold, an error warning interrupt will be triggered (given the enable signal is valid). 0 8 + read-write @@ -42765,6 +41512,7 @@ IDINTEN[4]: DU Interrupt. The RX error counter register, reflects value changes under reception status. 0 8 + read-write @@ -42779,6 +41527,7 @@ IDINTEN[4]: DU Interrupt. The TX error counter register, reflects value changes under transmission status. 0 8 + read-write @@ -42793,7 +41542,7 @@ IDINTEN[4]: DU Interrupt. In reset mode, it is acceptance code register 0 with R/W Permission. In operation mode, it stores the 0th byte information of the data to be transmitted under operating mode. 0 8 - write-only + read-write @@ -42808,7 +41557,7 @@ IDINTEN[4]: DU Interrupt. In reset mode, it is acceptance code register 1 with R/W Permission. In operation mode, it stores the 1st byte information of the data to be transmitted under operating mode. 0 8 - write-only + read-write @@ -42823,7 +41572,7 @@ IDINTEN[4]: DU Interrupt. In reset mode, it is acceptance code register 2 with R/W Permission. In operation mode, it stores the 2nd byte information of the data to be transmitted under operating mode. 0 8 - write-only + read-write @@ -42838,7 +41587,7 @@ IDINTEN[4]: DU Interrupt. In reset mode, it is acceptance code register 3 with R/W Permission. In operation mode, it stores the 3rd byte information of the data to be transmitted under operating mode. 0 8 - write-only + read-write @@ -42853,7 +41602,7 @@ IDINTEN[4]: DU Interrupt. In reset mode, it is acceptance mask register 0 with R/W Permission. In operation mode, it stores the 4th byte information of the data to be transmitted under operating mode. 0 8 - write-only + read-write @@ -42868,7 +41617,7 @@ IDINTEN[4]: DU Interrupt. In reset mode, it is acceptance mask register 1 with R/W Permission. In operation mode, it stores the 5th byte information of the data to be transmitted under operating mode. 0 8 - write-only + read-write @@ -42883,7 +41632,7 @@ IDINTEN[4]: DU Interrupt. In reset mode, it is acceptance mask register 2 with R/W Permission. In operation mode, it stores the 6th byte information of the data to be transmitted under operating mode. 0 8 - write-only + read-write @@ -42898,7 +41647,7 @@ IDINTEN[4]: DU Interrupt. In reset mode, it is acceptance mask register 3 with R/W Permission. In operation mode, it stores the 7th byte information of the data to be transmitted under operating mode. 0 8 - write-only + read-write @@ -42913,7 +41662,7 @@ IDINTEN[4]: DU Interrupt. Stored the 8th byte information of the data to be transmitted under operating mode. 0 8 - write-only + read-write @@ -42928,7 +41677,7 @@ IDINTEN[4]: DU Interrupt. Stored the 9th byte information of the data to be transmitted under operating mode. 0 8 - write-only + read-write @@ -42943,7 +41692,7 @@ IDINTEN[4]: DU Interrupt. Stored the 10th byte information of the data to be transmitted under operating mode. 0 8 - write-only + read-write @@ -42958,7 +41707,7 @@ IDINTEN[4]: DU Interrupt. Stored the 11th byte information of the data to be transmitted under operating mode. 0 8 - write-only + read-write @@ -42973,7 +41722,7 @@ IDINTEN[4]: DU Interrupt. Stored the 12th byte information of the data to be transmitted under operating mode. 0 8 - write-only + read-write @@ -43010,6 +41759,7 @@ IDINTEN[4]: DU Interrupt. This bit can be configured under reset mode. 1: Disable the external CLKOUT pin; 0: Enable the external CLKOUT pin 8 1 + read-write diff --git a/svd/esp32c2.svd b/svd/esp32c2.svd index 59e0529..6885e93 100644 --- a/svd/esp32c2.svd +++ b/svd/esp32c2.svd @@ -3,11 +3,11 @@ ESPRESSIF SYSTEMS (SHANGHAI) CO., LTD. ESPRESSIF ESP32-C2 - ESP32-C2 - 4 + ESP32 C-Series + 5 32-bit RISC-V MCU - Copyright 2022 Espressif Systems (Shanghai) PTE LTD + Copyright 2023 Espressif Systems (Shanghai) PTE LTD Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -545,7 +545,7 @@ - REDCY_SIG0_REG + REDCY_SIG0 APB_CTRL_REDCY_SIG0_REG_REG 0x94 0x20 @@ -567,7 +567,7 @@ - REDCY_SIG1_REG + REDCY_SIG1 APB_CTRL_REDCY_SIG1_REG_REG 0x98 0x20 @@ -760,7 +760,7 @@ - PERI_BACKUP_CONFIG_REG + PERI_BACKUP_CONFIG APB_CTRL_PERI_BACKUP_CONFIG_REG_REG 0xB4 0x20 @@ -818,7 +818,7 @@ - PERI_BACKUP_APB_ADDR_REG + PERI_BACKUP_APB_ADDR APB_CTRL_PERI_BACKUP_APB_ADDR_REG_REG 0xB8 0x20 @@ -833,7 +833,7 @@ - PERI_BACKUP_MEM_ADDR_REG + PERI_BACKUP_MEM_ADDR APB_CTRL_PERI_BACKUP_MEM_ADDR_REG_REG 0xBC 0x20 @@ -1862,6 +1862,10 @@ 0x38 registers + + ASSIST_DEBUG_INTR + 40 + CORE_0_INTR_ENA @@ -5957,7 +5961,7 @@ - CLOCK_GATE_REG + CLOCK_GATE GPIO clock gate register 0x62C 0x20 @@ -5973,7 +5977,7 @@ - REG_DATE_REG + REG_DATE GPIO version register 0x6FC 0x20 @@ -6000,10 +6004,6 @@ 0x88 registers - - I2C_MST - 11 - I2C_EXT0 22 @@ -7161,6 +7161,86 @@ level. 0x150 registers + + WIFI_MAC + 0 + + + WIFI_MAC_NMI + 1 + + + WIFI_PWR + 2 + + + WIFI_BB + 3 + + + BT_MAC + 4 + + + BT_BB + 5 + + + BT_BB_NMI + 6 + + + LP_TIMER + 7 + + + COEX + 8 + + + BLE_TIMER + 9 + + + BLE_SEC + 10 + + + CACHE_IA + 11 + + + ICACHE_PRELOAD0 + 30 + + + ICACHE_SYNC0 + 31 + + + ECC + 35 + + + SW_INTR_0 + 36 + + + SW_INTR_1 + 37 + + + SW_INTR_2 + 38 + + + SW_INTR_3 + 39 + + + PERI_VIO_SIZE_INTR + 41 + MAC_INTR_MAP diff --git a/svd/esp32c3.svd b/svd/esp32c3.svd index 532b90b..c64be7b 100644 --- a/svd/esp32c3.svd +++ b/svd/esp32c3.svd @@ -3,11 +3,11 @@ ESPRESSIF SYSTEMS (SHANGHAI) CO., LTD. ESPRESSIF ESP32-C3 - ESP32-C3 - 10 + ESP32 C-Series + 11 32-bit RISC-V MCU & 2.4 GHz Wi-Fi & Bluetooth 5 (LE) - Copyright 2022 Espressif Systems (Shanghai) PTE LTD + Copyright 2023 Espressif Systems (Shanghai) PTE LTD Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -29221,7 +29221,7 @@ read-write - CAN_CLK_EN + TWAI_CLK_EN reg_can_clk_en 19 1 @@ -29532,7 +29532,7 @@ read-write - CAN_RST + TWAI_RST reg_can_rst 19 1 diff --git a/svd/esp32c6.svd b/svd/esp32c6.svd index ae2dae4..842d308 100644 --- a/svd/esp32c6.svd +++ b/svd/esp32c6.svd @@ -3,11 +3,11 @@ ESPRESSIF SYSTEMS (SHANGHAI) CO., LTD. ESPRESSIF ESP32-C6 - ESP32-C6 - 1 + ESP32 C-Series + 2 32-bit RISC-V MCU & 2.4 GHz Wi-Fi 6 & Bluetooth 5 (LE) & IEEE 802.15.4 - Copyright 2022 Espressif Systems (Shanghai) PTE LTD + Copyright 2023 Espressif Systems (Shanghai) PTE LTD Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -2423,7 +2423,7 @@ ATOMIC - Peripheral ATOMIC + Atomic Locker ATOMIC 0x60011000 @@ -3964,7 +3964,7 @@ ECC - Peripheral ECC + ECC (ECC Hardware Accelerator) ECC 0x6008B000 @@ -13522,7 +13522,7 @@ 0x60091000 0x0 - 0x314 + 0x39C registers @@ -14059,2818 +14059,31 @@ - FUNC0_IN_SEL_CFG - GPIO input function configuration register - 0x154 - 0x20 - 0x0000003C - - - FUNC0_IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 - read-write - - - FUNC0_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG0_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write - - - - - FUNC6_IN_SEL_CFG - GPIO input function configuration register - 0x16C - 0x20 - 0x0000003C - - - FUNC6_IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 - read-write - - - FUNC6_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG6_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write - - - - - FUNC7_IN_SEL_CFG - GPIO input function configuration register - 0x170 - 0x20 - 0x0000003C - - - FUNC7_IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 - read-write - - - FUNC7_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG7_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write - - - - - FUNC8_IN_SEL_CFG - GPIO input function configuration register - 0x174 - 0x20 - 0x0000003C - - - FUNC8_IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 - read-write - - - FUNC8_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG8_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write - - - - - FUNC9_IN_SEL_CFG - GPIO input function configuration register - 0x178 - 0x20 - 0x00000038 - - - FUNC9_IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 - read-write - - - FUNC9_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG9_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write - - - - - FUNC10_IN_SEL_CFG - GPIO input function configuration register - 0x17C - 0x20 - 0x0000003C - - - FUNC10_IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 - read-write - - - FUNC10_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG10_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write - - - - - FUNC11_IN_SEL_CFG - GPIO input function configuration register - 0x180 - 0x20 - 0x0000003C - - - FUNC11_IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 - read-write - - - FUNC11_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG11_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write - - - - - FUNC12_IN_SEL_CFG - GPIO input function configuration register - 0x184 - 0x20 - 0x0000003C - - - FUNC12_IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 - read-write - - - FUNC12_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG12_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write - - - - - FUNC13_IN_SEL_CFG - GPIO input function configuration register - 0x188 - 0x20 - 0x0000003C - - - FUNC13_IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 - read-write - - - FUNC13_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG13_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write - - - - - FUNC14_IN_SEL_CFG - GPIO input function configuration register - 0x18C - 0x20 - 0x0000003C - - - FUNC14_IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 - read-write - - - FUNC14_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG14_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write - - - - - FUNC15_IN_SEL_CFG - GPIO input function configuration register - 0x190 - 0x20 - 0x0000003C - - - FUNC15_IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 - read-write - - - FUNC15_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG15_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write - - - - - FUNC16_IN_SEL_CFG - GPIO input function configuration register - 0x194 - 0x20 - 0x0000003C - - - FUNC16_IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 - read-write - - - FUNC16_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG16_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write - - - - - FUNC17_IN_SEL_CFG - GPIO input function configuration register - 0x198 - 0x20 - 0x0000003C - - - FUNC17_IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 - read-write - - - FUNC17_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG17_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write - - - - - FUNC19_IN_SEL_CFG - GPIO input function configuration register - 0x1A0 - 0x20 - 0x0000003C - - - FUNC19_IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 - read-write - - - FUNC19_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG19_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write - - - - - FUNC28_IN_SEL_CFG - GPIO input function configuration register - 0x1C4 - 0x20 - 0x0000003C - - - FUNC28_IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 - read-write - - - FUNC28_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG28_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write - - - - - FUNC29_IN_SEL_CFG - GPIO input function configuration register - 0x1C8 - 0x20 - 0x0000003C - - - FUNC29_IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 - read-write - - - FUNC29_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG29_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write - - - - - FUNC30_IN_SEL_CFG - GPIO input function configuration register - 0x1CC - 0x20 - 0x0000003C - - - FUNC30_IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 - read-write - - - FUNC30_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG30_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write - - - - - FUNC31_IN_SEL_CFG - GPIO input function configuration register - 0x1D0 - 0x20 - 0x0000003C - - - FUNC31_IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 - read-write - - - FUNC31_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG31_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write - - - - - FUNC32_IN_SEL_CFG - GPIO input function configuration register - 0x1D4 - 0x20 - 0x0000003C - - - FUNC32_IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 - read-write - - - FUNC32_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG32_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write - - - - - FUNC33_IN_SEL_CFG - GPIO input function configuration register - 0x1D8 - 0x20 - 0x0000003C - - - FUNC33_IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 - read-write - - - FUNC33_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG33_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write - - - - - FUNC34_IN_SEL_CFG - GPIO input function configuration register - 0x1DC - 0x20 - 0x0000003C - - - FUNC34_IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 - read-write - - - FUNC34_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG34_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write - - - - - FUNC35_IN_SEL_CFG - GPIO input function configuration register - 0x1E0 - 0x20 - 0x0000003C - - - FUNC35_IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 - read-write - - - FUNC35_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG35_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write - - - - - FUNC40_IN_SEL_CFG - GPIO input function configuration register - 0x1F4 - 0x20 - 0x0000003C - - - FUNC40_IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 - read-write - - - FUNC40_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG40_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write - - - - - FUNC41_IN_SEL_CFG - GPIO input function configuration register - 0x1F8 - 0x20 - 0x0000003C - - - FUNC41_IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 - read-write - - - FUNC41_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG41_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write - - - - - FUNC42_IN_SEL_CFG - GPIO input function configuration register - 0x1FC - 0x20 - 0x0000003C - - - FUNC42_IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 - read-write - - - FUNC42_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG42_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write - - - - - FUNC45_IN_SEL_CFG - GPIO input function configuration register - 0x208 - 0x20 - 0x00000038 - - - FUNC45_IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 - read-write - - - FUNC45_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG45_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write - - - - - FUNC46_IN_SEL_CFG - GPIO input function configuration register - 0x20C - 0x20 - 0x00000038 - - - FUNC46_IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 - read-write - - - FUNC46_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG46_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write - - - - - FUNC47_IN_SEL_CFG - GPIO input function configuration register - 0x210 - 0x20 - 0x0000003C - - - FUNC47_IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 - read-write - - - FUNC47_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG47_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write - - - - - FUNC48_IN_SEL_CFG - GPIO input function configuration register - 0x214 - 0x20 - 0x0000003C - - - FUNC48_IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 - read-write - - - FUNC48_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG48_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write - - - - - FUNC49_IN_SEL_CFG - GPIO input function configuration register - 0x218 - 0x20 - 0x0000003C - - - FUNC49_IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 - read-write - - - FUNC49_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG49_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write - - - - - FUNC50_IN_SEL_CFG - GPIO input function configuration register - 0x21C - 0x20 - 0x0000003C - - - FUNC50_IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 - read-write - - - FUNC50_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG50_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write - - - - - FUNC51_IN_SEL_CFG - GPIO input function configuration register - 0x220 - 0x20 - 0x0000003C - - - FUNC51_IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 - read-write - - - FUNC51_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG51_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write - - - - - FUNC52_IN_SEL_CFG - GPIO input function configuration register - 0x224 - 0x20 - 0x0000003C - - - FUNC52_IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 - read-write - - - FUNC52_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG52_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write - - - - - FUNC53_IN_SEL_CFG - GPIO input function configuration register - 0x228 - 0x20 - 0x0000003C - - - FUNC53_IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 - read-write - - - FUNC53_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG53_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write - - - - - FUNC54_IN_SEL_CFG - GPIO input function configuration register - 0x22C - 0x20 - 0x0000003C - - - FUNC54_IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 - read-write - - - FUNC54_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG54_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write - - - - - FUNC55_IN_SEL_CFG - GPIO input function configuration register - 0x230 - 0x20 - 0x0000003C - - - FUNC55_IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 - read-write - - - FUNC55_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG55_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write - - - - - FUNC56_IN_SEL_CFG - GPIO input function configuration register - 0x234 - 0x20 - 0x0000003C - - - FUNC56_IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 - read-write - - - FUNC56_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG56_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write - - - - - FUNC57_IN_SEL_CFG - GPIO input function configuration register - 0x238 - 0x20 - 0x0000003C - - - FUNC57_IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 - read-write - - - FUNC57_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG57_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write - - - - - FUNC58_IN_SEL_CFG - GPIO input function configuration register - 0x23C - 0x20 - 0x0000003C - - - FUNC58_IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 - read-write - - - FUNC58_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG58_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write - - - - - FUNC59_IN_SEL_CFG - GPIO input function configuration register - 0x240 - 0x20 - 0x0000003C - - - FUNC59_IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 - read-write - - - FUNC59_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG59_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write - - - - - FUNC60_IN_SEL_CFG - GPIO input function configuration register - 0x244 - 0x20 - 0x0000003C - - - FUNC60_IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 - read-write - - - FUNC60_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG60_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write - - - - - FUNC61_IN_SEL_CFG - GPIO input function configuration register - 0x248 - 0x20 - 0x0000003C - - - FUNC61_IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 - read-write - - - FUNC61_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG61_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write - - - - - FUNC62_IN_SEL_CFG - GPIO input function configuration register - 0x24C - 0x20 - 0x0000003C - - - FUNC62_IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 - read-write - - - FUNC62_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG62_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write - - - - - FUNC63_IN_SEL_CFG - GPIO input function configuration register - 0x250 - 0x20 - 0x0000003C - - - FUNC63_IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 - read-write - - - FUNC63_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG63_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write - - - - - FUNC64_IN_SEL_CFG - GPIO input function configuration register - 0x254 - 0x20 - 0x0000003C - - - FUNC64_IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 - read-write - - - FUNC64_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG64_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write - - - - - FUNC65_IN_SEL_CFG - GPIO input function configuration register - 0x258 - 0x20 - 0x0000003C - - - FUNC65_IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 - read-write - - - FUNC65_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG65_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write - - - - - FUNC66_IN_SEL_CFG - GPIO input function configuration register - 0x25C - 0x20 - 0x0000003C - - - FUNC66_IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 - read-write - - - FUNC66_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG66_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write - - - - - FUNC67_IN_SEL_CFG - GPIO input function configuration register - 0x260 - 0x20 - 0x0000003C - - - FUNC67_IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 - read-write - - - FUNC67_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG67_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write - - - - - FUNC68_IN_SEL_CFG - GPIO input function configuration register - 0x264 - 0x20 - 0x0000003C - - - FUNC68_IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 - read-write - - - FUNC68_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG68_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write - - - - - FUNC69_IN_SEL_CFG - GPIO input function configuration register - 0x268 - 0x20 - 0x0000003C - - - FUNC69_IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 - read-write - - - FUNC69_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG69_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write - - - - - FUNC70_IN_SEL_CFG - GPIO input function configuration register - 0x26C - 0x20 - 0x0000003C - - - FUNC70_IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 - read-write - - - FUNC70_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG70_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write - - - - - FUNC71_IN_SEL_CFG - GPIO input function configuration register - 0x270 - 0x20 - 0x0000003C - - - FUNC71_IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 - read-write - - - FUNC71_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG71_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write - - - - - FUNC72_IN_SEL_CFG - GPIO input function configuration register - 0x274 - 0x20 - 0x0000003C - - - FUNC72_IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 - read-write - - - FUNC72_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG72_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write - - - - - FUNC73_IN_SEL_CFG - GPIO input function configuration register - 0x278 - 0x20 - 0x00000038 - - - FUNC73_IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 - read-write - - - FUNC73_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG73_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write - - - - - FUNC77_IN_SEL_CFG - GPIO input function configuration register - 0x288 - 0x20 - 0x00000038 - - - FUNC77_IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 - read-write - - - FUNC77_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG77_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write - - - - - FUNC81_IN_SEL_CFG - GPIO input function configuration register - 0x298 - 0x20 - 0x0000003C - - - FUNC81_IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 - read-write - - - FUNC81_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG81_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write - - - - - FUNC82_IN_SEL_CFG - GPIO input function configuration register - 0x29C - 0x20 - 0x0000003C - - - FUNC82_IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 - read-write - - - FUNC82_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG82_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write - - - - - FUNC87_IN_SEL_CFG - GPIO input function configuration register - 0x2B0 - 0x20 - 0x0000003C - - - FUNC87_IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 - read-write - - - FUNC87_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG87_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write - - - - - FUNC88_IN_SEL_CFG - GPIO input function configuration register - 0x2B4 - 0x20 - 0x0000003C - - - FUNC88_IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 - read-write - - - FUNC88_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG88_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write - - - - - FUNC89_IN_SEL_CFG - GPIO input function configuration register - 0x2B8 - 0x20 - 0x0000003C - - - FUNC89_IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 - read-write - - - FUNC89_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG89_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write - - - - - FUNC90_IN_SEL_CFG - GPIO input function configuration register - 0x2BC - 0x20 - 0x0000003C - - - FUNC90_IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 - read-write - - - FUNC90_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG90_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write - - - - - FUNC91_IN_SEL_CFG - GPIO input function configuration register - 0x2C0 - 0x20 - 0x0000003C - - - FUNC91_IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 - read-write - - - FUNC91_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG91_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write - - - - - FUNC92_IN_SEL_CFG - GPIO input function configuration register - 0x2C4 - 0x20 - 0x0000003C - - - FUNC92_IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 - read-write - - - FUNC92_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG92_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write - - - - - FUNC93_IN_SEL_CFG - GPIO input function configuration register - 0x2C8 - 0x20 - 0x0000003C - - - FUNC93_IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 - read-write - - - FUNC93_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG93_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write - - - - - FUNC94_IN_SEL_CFG - GPIO input function configuration register - 0x2CC - 0x20 - 0x0000003C - - - FUNC94_IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 - read-write - - - FUNC94_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG94_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write - - - - - FUNC95_IN_SEL_CFG - GPIO input function configuration register - 0x2D0 - 0x20 - 0x0000003C - - - FUNC95_IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 - read-write - - - FUNC95_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG95_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write - - - - - FUNC97_IN_SEL_CFG - GPIO input function configuration register - 0x2D8 - 0x20 - 0x0000003C - - - FUNC97_IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 - read-write - - - FUNC97_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG97_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write - - - - - FUNC98_IN_SEL_CFG - GPIO input function configuration register - 0x2DC - 0x20 - 0x0000003C - - - FUNC98_IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 - read-write - - - FUNC98_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG98_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write - - - - - FUNC99_IN_SEL_CFG - GPIO input function configuration register - 0x2E0 - 0x20 - 0x0000003C - - - FUNC99_IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 - read-write - - - FUNC99_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG99_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write - - - - - FUNC100_IN_SEL_CFG - GPIO input function configuration register - 0x2E4 - 0x20 - 0x0000003C - - - FUNC100_IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 - read-write - - - FUNC100_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG100_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write - - - - - FUNC101_IN_SEL_CFG - GPIO input function configuration register - 0x2E8 - 0x20 - 0x0000003C - - - FUNC101_IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 - read-write - - - FUNC101_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG101_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write - - - - - FUNC102_IN_SEL_CFG - GPIO input function configuration register - 0x2EC - 0x20 - 0x0000003C - - - FUNC102_IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 - read-write - - - FUNC102_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG102_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write - - - - - FUNC103_IN_SEL_CFG - GPIO input function configuration register - 0x2F0 - 0x20 - 0x0000003C - - - FUNC103_IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 - read-write - - - FUNC103_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG103_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write - - - - - FUNC104_IN_SEL_CFG - GPIO input function configuration register - 0x2F4 - 0x20 - 0x0000003C - - - FUNC104_IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 - read-write - - - FUNC104_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG104_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write - - - - - FUNC105_IN_SEL_CFG - GPIO input function configuration register - 0x2F8 - 0x20 - 0x0000003C - - - FUNC105_IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 - read-write - - - FUNC105_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG105_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write - - - - - FUNC106_IN_SEL_CFG - GPIO input function configuration register - 0x2FC - 0x20 - 0x0000003C - - - FUNC106_IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 - read-write - - - FUNC106_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG106_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write - - - - - FUNC107_IN_SEL_CFG - GPIO input function configuration register - 0x300 - 0x20 - 0x0000003C - - - FUNC107_IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 - read-write - - - FUNC107_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG107_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write - - - - - FUNC108_IN_SEL_CFG - GPIO input function configuration register - 0x304 - 0x20 - 0x0000003C - - - FUNC108_IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 - read-write - - - FUNC108_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG108_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write - - - - - FUNC109_IN_SEL_CFG - GPIO input function configuration register - 0x308 - 0x20 - 0x0000003C - - - FUNC109_IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 - read-write - - - FUNC109_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG109_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write - - - - - FUNC110_IN_SEL_CFG - GPIO input function configuration register - 0x30C - 0x20 - 0x0000003C - - - FUNC110_IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 - read-write - - - FUNC110_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG110_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write - - - - - FUNC111_IN_SEL_CFG - GPIO input function configuration register - 0x310 - 0x20 - 0x0000003C - - - FUNC111_IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 - read-write - - - FUNC111_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG111_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write - - - - - FUNC112_IN_SEL_CFG - GPIO input function configuration register - 0x314 - 0x20 - 0x0000003C - - - FUNC112_IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 - read-write - - - FUNC112_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG112_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write - - - - - FUNC113_IN_SEL_CFG - GPIO input function configuration register - 0x318 - 0x20 - 0x0000003C - - - FUNC113_IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 - read-write - - - FUNC113_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG113_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write - - - - - FUNC114_IN_SEL_CFG - GPIO input function configuration register - 0x31C - 0x20 - 0x0000003C - - - FUNC114_IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 - read-write - - - FUNC114_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG114_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write - - - - - FUNC115_IN_SEL_CFG - GPIO input function configuration register - 0x320 - 0x20 - 0x0000003C - - - FUNC115_IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 - read-write - - - FUNC115_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG115_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write - - - - - FUNC116_IN_SEL_CFG - GPIO input function configuration register - 0x324 - 0x20 - 0x0000003C - - - FUNC116_IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 - read-write - - - FUNC116_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG116_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write - - - - - FUNC117_IN_SEL_CFG - GPIO input function configuration register - 0x328 - 0x20 - 0x0000003C - - - FUNC117_IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 - read-write - - - FUNC117_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG117_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write - - - - - FUNC118_IN_SEL_CFG - GPIO input function configuration register - 0x32C - 0x20 - 0x0000003C - - - FUNC118_IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 - read-write - - - FUNC118_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG118_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write - - - - - FUNC119_IN_SEL_CFG - GPIO input function configuration register - 0x330 - 0x20 - 0x0000003C - - - FUNC119_IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 - read-write - - - FUNC119_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG119_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write - - - - - FUNC120_IN_SEL_CFG - GPIO input function configuration register - 0x334 - 0x20 - 0x0000003C - - - FUNC120_IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 - read-write - - - FUNC120_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG120_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write - - - - - FUNC121_IN_SEL_CFG - GPIO input function configuration register - 0x338 - 0x20 - 0x0000003C - - - FUNC121_IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 - read-write - - - FUNC121_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG121_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write - - - - - FUNC122_IN_SEL_CFG - GPIO input function configuration register - 0x33C - 0x20 - 0x0000003C - - - FUNC122_IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 - read-write - - - FUNC122_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG122_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write - - - - - FUNC123_IN_SEL_CFG - GPIO input function configuration register - 0x340 - 0x20 - 0x0000003C - - - FUNC123_IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 - read-write - - - FUNC123_IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SIG123_IN_SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write - - - - - FUNC124_IN_SEL_CFG + 128 + 0x4 + 0-127 + FUNC%s_IN_SEL_CFG GPIO input function configuration register - 0x344 + 0x154 0x20 0x0000003C - FUNC124_IN_SEL + IN_SEL set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. 0 6 read-write - FUNC124_IN_INV_SEL + IN_INV_SEL set this bit to invert input signal. 1:invert. 0:not invert. 6 1 read-write - SIG124_IN_SEL + SEL set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 7 1 @@ -16888,28 +14101,28 @@ 0x00000080 - FUNC_OUT_SEL + OUT_SEL The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals GPIO_OUT_REG[n]. 0 8 read-write - FUNC_OUT_INV_SEL + INV_SEL set this bit to invert output signal.1:invert.0:not invert. 8 1 read-write - FUNC_OEN_SEL + OEN_SEL set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output enable signal.0:use peripheral output enable signal. 9 1 read-write - FUNC_OEN_INV_SEL + OEN_INV_SEL set this bit to invert output enable signal.1:invert.0:not invert. 10 1 @@ -18616,6 +15829,22 @@ 0x114 registers + + HP_APM_M0 + 35 + + + HP_APM_M1 + 36 + + + HP_APM_M2 + 37 + + + HP_APM_M3 + 38 + REGION_FILTER_EN @@ -20670,7 +17899,7 @@ HP_SYS - Peripheral HP_SYS + High-Power System HP_SYS 0x60095000 @@ -22314,8 +19543,11 @@ in I2C module clock cycles, the I2C controller will ignore that pulse. - COMD0 - I2C command register 0 + 8 + 0x4 + 0-7 + COMD%s + I2C command register %s 0x58 0x20 @@ -22340,192 +19572,6 @@ level. - - COMD1 - I2C command register 1 - 0x5C - 0x20 - - - COMMAND1 - This is the content of command 1. It consists of three parts: -op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. -Byte_num represents the number of bytes that need to be sent or received. -ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more -Information. - 0 - 14 - read-write - - - COMMAND1_DONE - When command 1 is done in I2C Master mode, this bit changes to high -level. - 31 - 1 - read-write - - - - - COMD2 - I2C command register 2 - 0x60 - 0x20 - - - COMMAND2 - This is the content of command 2. It consists of three parts: -op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. -Byte_num represents the number of bytes that need to be sent or received. -ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more -Information. - 0 - 14 - read-write - - - COMMAND2_DONE - When command 2 is done in I2C Master mode, this bit changes to high -Level. - 31 - 1 - read-write - - - - - COMD3 - I2C command register 3 - 0x64 - 0x20 - - - COMMAND3 - This is the content of command 3. It consists of three parts: -op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. -Byte_num represents the number of bytes that need to be sent or received. -ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more -Information. - 0 - 14 - read-write - - - COMMAND3_DONE - When command 3 is done in I2C Master mode, this bit changes to high -level. - 31 - 1 - read-write - - - - - COMD4 - I2C command register 4 - 0x68 - 0x20 - - - COMMAND4 - This is the content of command 4. It consists of three parts: -op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. -Byte_num represents the number of bytes that need to be sent or received. -ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more -Information. - 0 - 14 - read-write - - - COMMAND4_DONE - When command 4 is done in I2C Master mode, this bit changes to high -level. - 31 - 1 - read-write - - - - - COMD5 - I2C command register 5 - 0x6C - 0x20 - - - COMMAND5 - This is the content of command 5. It consists of three parts: -op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. -Byte_num represents the number of bytes that need to be sent or received. -ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more -Information. - 0 - 14 - read-write - - - COMMAND5_DONE - When command 5 is done in I2C Master mode, this bit changes to high level. - 31 - 1 - read-write - - - - - COMD6 - I2C command register 6 - 0x70 - 0x20 - - - COMMAND6 - This is the content of command 6. It consists of three parts: -op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. -Byte_num represents the number of bytes that need to be sent or received. -ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more -Information. - 0 - 14 - read-write - - - COMMAND6_DONE - When command 6 is done in I2C Master mode, this bit changes to high level. - 31 - 1 - read-write - - - - - COMD7 - I2C command register 7 - 0x74 - 0x20 - - - COMMAND7 - This is the content of command 7. It consists of three parts: -op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. -Byte_num represents the number of bytes that need to be sent or received. -ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more -Information. - 0 - 14 - read-write - - - COMMAND7_DONE - When command 7 is done in I2C Master mode, this bit changes to high level. - 31 - 1 - read-write - - - SCL_ST_TIME_OUT SCL status time out register @@ -23983,7 +21029,7 @@ Information. - INTMTX_CORE0 + INTERRUPT_CORE0 Interrupt Core INTMTX_CORE0 0x60010000 @@ -23992,6 +21038,50 @@ Information. 0x148 registers + + WIFI_MAC + 0 + + + WIFI_MAC_NMI + 1 + + + WIFI_PWR + 2 + + + WIFI_BB + 3 + + + BT_MAC + 4 + + + BT_BB + 5 + + + BT_BB_NMI + 6 + + + LP_TIMER + 7 + + + COEX + 8 + + + BLE_TIMER + 9 + + + BLE_SEC + 10 + WIFI_MAC_INTR_MAP @@ -27594,8 +24684,8 @@ The least significant eight bits represent the fractional part. - LPPERI - Peripheral LPPERI + LP_PERI + Peripheral LP_PERI LPPERI 0x600B2800 @@ -27603,6 +24693,10 @@ The least significant eight bits represent the fractional part. 0x28 registers + + LP_PERI_TIMEOUT + 19 + CLK_EN @@ -28673,6 +25767,18 @@ The least significant eight bits represent the fractional part. 0x64 registers + + LP_APM_M0 + 20 + + + LP_APM_M1 + 21 + + + LP_APM0 + 39 + REGION_FILTER_EN @@ -30336,6 +27442,10 @@ The least significant eight bits represent the fractional part. 0x88 registers + + LP_I2C + 17 + I2C_SCL_LOW_PERIOD @@ -33641,6 +30751,10 @@ Information. 0x84 registers + + LP_UART + 16 + FIFO @@ -35470,7 +32584,7 @@ Information. MCPWM - Peripheral MCPWM + Motor Control Pulse-Width Modulation MCPWM 0x60014000 @@ -35478,6 +32592,10 @@ Information. 0x130 registers + + PWM + 61 + CLK_CFG @@ -65151,14 +62269,14 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0x60002000 - T_USE_XTAL + USE_XTAL 1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the source clock of timer group. 9 1 read-write - T_ALARM_EN + ALARM_EN When set, the alarm is enabled. This bit is automatically cleared once an alarm occurs. 10 @@ -65166,28 +62284,28 @@ alarm occurs. read-write - T_DIVCNT_RST + DIVCNT_RST When set, Timer %s 's clock divider counter will be reset. 12 1 write-only - T_DIVIDER + DIVIDER Timer %s clock (T%s_clk) prescaler value. 13 16 read-write - T_AUTORELOAD + AUTORELOAD When set, timer %s auto-reload at alarm is enabled. 29 1 read-write - T_INCREASE + INCREASE When set, the timer %s time-base counter will increment every clock tick. When cleared, the timer %s time-base counter will decrement. 30 @@ -65195,7 +62313,7 @@ cleared, the timer %s time-base counter will decrement. read-write - T_EN + EN When set, the timer %s time-base counter is enabled. 31 1 @@ -65210,7 +62328,7 @@ cleared, the timer %s time-base counter will decrement. 0x20 - T_LO + LO After writing to TIMG_T%sUPDATE_REG, the low 32 bits of the time-base counter of timer %s can be read here. 0 @@ -65226,7 +62344,7 @@ of timer %s can be read here. 0x20 - T_HI + HI After writing to TIMG_T%sUPDATE_REG, the high 22 bits of the time-base counter of timer %s can be read here. 0 @@ -65242,7 +62360,7 @@ of timer %s can be read here. 0x20 - T_UPDATE + UPDATE After writing 0 or 1 to TIMG_T%sUPDATE_REG, the counter value is latched. 31 1 @@ -65257,7 +62375,7 @@ of timer %s can be read here. 0x20 - T_ALARM_LO + ALARM_LO Timer %s alarm trigger time-base counter value, low 32 bits. 0 32 @@ -65272,7 +62390,7 @@ of timer %s can be read here. 0x20 - T_ALARM_HI + ALARM_HI Timer %s alarm trigger time-base counter value, high 22 bits. 0 22 @@ -65287,7 +62405,7 @@ of timer %s can be read here. 0x20 - T_LOAD_LO + LOAD_LO Low 32 bits of the value that a reload will load onto timer %s time-base Counter. 0 @@ -65303,7 +62421,7 @@ Counter. 0x20 - T_LOAD_HI + LOAD_HI High 22 bits of the value that a reload will load onto timer %s time-base counter. 0 @@ -65319,7 +62437,7 @@ counter. 0x20 - T_LOAD + LOAD Write any value to trigger a timer %s time-base counter reload. 0 @@ -69615,7 +66733,7 @@ protection is enabled. 0x20 - USB_SERIAL_JTAG_RDWR_BYTE + RDWR_BYTE Write and read byte data to/from UART Tx/Rx FIFO through this field. When USB_DEVICE_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 bytes) into UART Tx FIFO. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is set, user can check USB_DEVICE_OUT_EP1_WR_ADDR USB_DEVICE_OUT_EP0_RD_ADDR to know how many data is received, then read data from UART Rx FIFO. 0 8 @@ -69631,21 +66749,21 @@ protection is enabled. 0x00000002 - USB_SERIAL_JTAG_WR_DONE + WR_DONE Set this bit to indicate writing byte data to UART Tx FIFO is done. 0 1 write-only - USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE + SERIAL_IN_EP_DATA_FREE 1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writing USB_DEVICE_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by USB Host. 1 1 read-only - USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL + SERIAL_OUT_EP_DATA_AVAIL 1'b1: Indicate there is data in UART Rx FIFO. 2 1 @@ -69661,112 +66779,112 @@ protection is enabled. 0x00000008 - USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW + JTAG_IN_FLUSH_INT_RAW The raw interrupt bit turns to high level when flush cmd is received for IN endpoint 2 of JTAG. 0 1 read-only - USB_SERIAL_JTAG_SOF_INT_RAW + SOF_INT_RAW The raw interrupt bit turns to high level when SOF frame is received. 1 1 read-only - USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW + SERIAL_OUT_RECV_PKT_INT_RAW The raw interrupt bit turns to high level when Serial Port OUT Endpoint received one packet. 2 1 read-only - USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW + SERIAL_IN_EMPTY_INT_RAW The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty. 3 1 read-only - USB_SERIAL_JTAG_PID_ERR_INT_RAW + PID_ERR_INT_RAW The raw interrupt bit turns to high level when pid error is detected. 4 1 read-only - USB_SERIAL_JTAG_CRC5_ERR_INT_RAW + CRC5_ERR_INT_RAW The raw interrupt bit turns to high level when CRC5 error is detected. 5 1 read-only - USB_SERIAL_JTAG_CRC16_ERR_INT_RAW + CRC16_ERR_INT_RAW The raw interrupt bit turns to high level when CRC16 error is detected. 6 1 read-only - USB_SERIAL_JTAG_STUFF_ERR_INT_RAW + STUFF_ERR_INT_RAW The raw interrupt bit turns to high level when stuff error is detected. 7 1 read-only - USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW + IN_TOKEN_REC_IN_EP1_INT_RAW The raw interrupt bit turns to high level when IN token for IN endpoint 1 is received. 8 1 read-only - USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW + USB_BUS_RESET_INT_RAW The raw interrupt bit turns to high level when usb bus reset is detected. 9 1 read-only - USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW + OUT_EP1_ZERO_PAYLOAD_INT_RAW The raw interrupt bit turns to high level when OUT endpoint 1 received packet with zero palyload. 10 1 read-only - USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW + OUT_EP2_ZERO_PAYLOAD_INT_RAW The raw interrupt bit turns to high level when OUT endpoint 2 received packet with zero palyload. 11 1 read-only - USB_SERIAL_JTAG_RTS_CHG_INT_RAW + RTS_CHG_INT_RAW The raw interrupt bit turns to high level when level of RTS from usb serial channel is changed. 12 1 read-only - USB_SERIAL_JTAG_DTR_CHG_INT_RAW + DTR_CHG_INT_RAW The raw interrupt bit turns to high level when level of DTR from usb serial channel is changed. 13 1 read-only - USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW + GET_LINE_CODE_INT_RAW The raw interrupt bit turns to high level when level of GET LINE CODING request is received. 14 1 read-only - USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW + SET_LINE_CODE_INT_RAW The raw interrupt bit turns to high level when level of SET LINE CODING request is received. 15 1 @@ -69781,112 +66899,112 @@ protection is enabled. 0x20 - USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST + JTAG_IN_FLUSH_INT_ST The raw interrupt status bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt. 0 1 read-only - USB_SERIAL_JTAG_SOF_INT_ST + SOF_INT_ST The raw interrupt status bit for the USB_DEVICE_SOF_INT interrupt. 1 1 read-only - USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST + SERIAL_OUT_RECV_PKT_INT_ST The raw interrupt status bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt. 2 1 read-only - USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST + SERIAL_IN_EMPTY_INT_ST The raw interrupt status bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt. 3 1 read-only - USB_SERIAL_JTAG_PID_ERR_INT_ST + PID_ERR_INT_ST The raw interrupt status bit for the USB_DEVICE_PID_ERR_INT interrupt. 4 1 read-only - USB_SERIAL_JTAG_CRC5_ERR_INT_ST + CRC5_ERR_INT_ST The raw interrupt status bit for the USB_DEVICE_CRC5_ERR_INT interrupt. 5 1 read-only - USB_SERIAL_JTAG_CRC16_ERR_INT_ST + CRC16_ERR_INT_ST The raw interrupt status bit for the USB_DEVICE_CRC16_ERR_INT interrupt. 6 1 read-only - USB_SERIAL_JTAG_STUFF_ERR_INT_ST + STUFF_ERR_INT_ST The raw interrupt status bit for the USB_DEVICE_STUFF_ERR_INT interrupt. 7 1 read-only - USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST + IN_TOKEN_REC_IN_EP1_INT_ST The raw interrupt status bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt. 8 1 read-only - USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST + USB_BUS_RESET_INT_ST The raw interrupt status bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt. 9 1 read-only - USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST + OUT_EP1_ZERO_PAYLOAD_INT_ST The raw interrupt status bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt. 10 1 read-only - USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST + OUT_EP2_ZERO_PAYLOAD_INT_ST The raw interrupt status bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt. 11 1 read-only - USB_SERIAL_JTAG_RTS_CHG_INT_ST + RTS_CHG_INT_ST The raw interrupt status bit for the USB_DEVICE_RTS_CHG_INT interrupt. 12 1 read-only - USB_SERIAL_JTAG_DTR_CHG_INT_ST + DTR_CHG_INT_ST The raw interrupt status bit for the USB_DEVICE_DTR_CHG_INT interrupt. 13 1 read-only - USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST + GET_LINE_CODE_INT_ST The raw interrupt status bit for the USB_DEVICE_GET_LINE_CODE_INT interrupt. 14 1 read-only - USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST + SET_LINE_CODE_INT_ST The raw interrupt status bit for the USB_DEVICE_SET_LINE_CODE_INT interrupt. 15 1 @@ -69901,112 +67019,112 @@ protection is enabled. 0x20 - USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA + JTAG_IN_FLUSH_INT_ENA The interrupt enable bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt. 0 1 read-write - USB_SERIAL_JTAG_SOF_INT_ENA + SOF_INT_ENA The interrupt enable bit for the USB_DEVICE_SOF_INT interrupt. 1 1 read-write - USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA + SERIAL_OUT_RECV_PKT_INT_ENA The interrupt enable bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt. 2 1 read-write - USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA + SERIAL_IN_EMPTY_INT_ENA The interrupt enable bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt. 3 1 read-write - USB_SERIAL_JTAG_PID_ERR_INT_ENA + PID_ERR_INT_ENA The interrupt enable bit for the USB_DEVICE_PID_ERR_INT interrupt. 4 1 read-write - USB_SERIAL_JTAG_CRC5_ERR_INT_ENA + CRC5_ERR_INT_ENA The interrupt enable bit for the USB_DEVICE_CRC5_ERR_INT interrupt. 5 1 read-write - USB_SERIAL_JTAG_CRC16_ERR_INT_ENA + CRC16_ERR_INT_ENA The interrupt enable bit for the USB_DEVICE_CRC16_ERR_INT interrupt. 6 1 read-write - USB_SERIAL_JTAG_STUFF_ERR_INT_ENA + STUFF_ERR_INT_ENA The interrupt enable bit for the USB_DEVICE_STUFF_ERR_INT interrupt. 7 1 read-write - USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA + IN_TOKEN_REC_IN_EP1_INT_ENA The interrupt enable bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt. 8 1 read-write - USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA + USB_BUS_RESET_INT_ENA The interrupt enable bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt. 9 1 read-write - USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA + OUT_EP1_ZERO_PAYLOAD_INT_ENA The interrupt enable bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt. 10 1 read-write - USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA + OUT_EP2_ZERO_PAYLOAD_INT_ENA The interrupt enable bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt. 11 1 read-write - USB_SERIAL_JTAG_RTS_CHG_INT_ENA + RTS_CHG_INT_ENA The interrupt enable bit for the USB_DEVICE_RTS_CHG_INT interrupt. 12 1 read-write - USB_SERIAL_JTAG_DTR_CHG_INT_ENA + DTR_CHG_INT_ENA The interrupt enable bit for the USB_DEVICE_DTR_CHG_INT interrupt. 13 1 read-write - USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA + GET_LINE_CODE_INT_ENA The interrupt enable bit for the USB_DEVICE_GET_LINE_CODE_INT interrupt. 14 1 read-write - USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA + SET_LINE_CODE_INT_ENA The interrupt enable bit for the USB_DEVICE_SET_LINE_CODE_INT interrupt. 15 1 @@ -70021,112 +67139,112 @@ protection is enabled. 0x20 - USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR + JTAG_IN_FLUSH_INT_CLR Set this bit to clear the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt. 0 1 write-only - USB_SERIAL_JTAG_SOF_INT_CLR + SOF_INT_CLR Set this bit to clear the USB_DEVICE_JTAG_SOF_INT interrupt. 1 1 write-only - USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR + SERIAL_OUT_RECV_PKT_INT_CLR Set this bit to clear the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt. 2 1 write-only - USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR + SERIAL_IN_EMPTY_INT_CLR Set this bit to clear the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt. 3 1 write-only - USB_SERIAL_JTAG_PID_ERR_INT_CLR + PID_ERR_INT_CLR Set this bit to clear the USB_DEVICE_PID_ERR_INT interrupt. 4 1 write-only - USB_SERIAL_JTAG_CRC5_ERR_INT_CLR + CRC5_ERR_INT_CLR Set this bit to clear the USB_DEVICE_CRC5_ERR_INT interrupt. 5 1 write-only - USB_SERIAL_JTAG_CRC16_ERR_INT_CLR + CRC16_ERR_INT_CLR Set this bit to clear the USB_DEVICE_CRC16_ERR_INT interrupt. 6 1 write-only - USB_SERIAL_JTAG_STUFF_ERR_INT_CLR + STUFF_ERR_INT_CLR Set this bit to clear the USB_DEVICE_STUFF_ERR_INT interrupt. 7 1 write-only - USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR + IN_TOKEN_REC_IN_EP1_INT_CLR Set this bit to clear the USB_DEVICE_IN_TOKEN_IN_EP1_INT interrupt. 8 1 write-only - USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR + USB_BUS_RESET_INT_CLR Set this bit to clear the USB_DEVICE_USB_BUS_RESET_INT interrupt. 9 1 write-only - USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR + OUT_EP1_ZERO_PAYLOAD_INT_CLR Set this bit to clear the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt. 10 1 write-only - USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR + OUT_EP2_ZERO_PAYLOAD_INT_CLR Set this bit to clear the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt. 11 1 write-only - USB_SERIAL_JTAG_RTS_CHG_INT_CLR + RTS_CHG_INT_CLR Set this bit to clear the USB_DEVICE_RTS_CHG_INT interrupt. 12 1 write-only - USB_SERIAL_JTAG_DTR_CHG_INT_CLR + DTR_CHG_INT_CLR Set this bit to clear the USB_DEVICE_DTR_CHG_INT interrupt. 13 1 write-only - USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR + GET_LINE_CODE_INT_CLR Set this bit to clear the USB_DEVICE_GET_LINE_CODE_INT interrupt. 14 1 write-only - USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR + SET_LINE_CODE_INT_CLR Set this bit to clear the USB_DEVICE_SET_LINE_CODE_INT interrupt. 15 1 @@ -70142,98 +67260,98 @@ protection is enabled. 0x00004200 - USB_SERIAL_JTAG_PHY_SEL + PHY_SEL Select internal/external PHY 0 1 read-write - USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE + EXCHG_PINS_OVERRIDE Enable software control USB D+ D- exchange 1 1 read-write - USB_SERIAL_JTAG_EXCHG_PINS + EXCHG_PINS USB D+ D- exchange 2 1 read-write - USB_SERIAL_JTAG_VREFH + VREFH Control single-end input high threshold,1.76V to 2V, step 80mV 3 2 read-write - USB_SERIAL_JTAG_VREFL + VREFL Control single-end input low threshold,0.8V to 1.04V, step 80mV 5 2 read-write - USB_SERIAL_JTAG_VREF_OVERRIDE + VREF_OVERRIDE Enable software control input threshold 7 1 read-write - USB_SERIAL_JTAG_PAD_PULL_OVERRIDE + PAD_PULL_OVERRIDE Enable software control USB D+ D- pullup pulldown 8 1 read-write - USB_SERIAL_JTAG_DP_PULLUP + DP_PULLUP Control USB D+ pull up. 9 1 read-write - USB_SERIAL_JTAG_DP_PULLDOWN + DP_PULLDOWN Control USB D+ pull down. 10 1 read-write - USB_SERIAL_JTAG_DM_PULLUP + DM_PULLUP Control USB D- pull up. 11 1 read-write - USB_SERIAL_JTAG_DM_PULLDOWN + DM_PULLDOWN Control USB D- pull down. 12 1 read-write - USB_SERIAL_JTAG_PULLUP_VALUE + PULLUP_VALUE Control pull up value. 13 1 read-write - USB_SERIAL_JTAG_USB_PAD_ENABLE + USB_PAD_ENABLE Enable USB pad function. 14 1 read-write - USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN + USB_JTAG_BRIDGE_EN Set this bit usb_jtag, the connection between usb_jtag and internal JTAG is disconnected, and MTMS, MTDI, MTCK are output through GPIO Matrix, MTDO is input through GPIO Matrix. 15 1 @@ -70249,49 +67367,49 @@ protection is enabled. 0x00000030 - USB_SERIAL_JTAG_TEST_ENABLE + TEST_ENABLE Enable test of the USB pad 0 1 read-write - USB_SERIAL_JTAG_TEST_USB_OE + TEST_USB_OE USB pad oen in test 1 1 read-write - USB_SERIAL_JTAG_TEST_TX_DP + TEST_TX_DP USB D+ tx value in test 2 1 read-write - USB_SERIAL_JTAG_TEST_TX_DM + TEST_TX_DM USB D- tx value in test 3 1 read-write - USB_SERIAL_JTAG_TEST_RX_RCV + TEST_RX_RCV USB RCV value in test 4 1 read-only - USB_SERIAL_JTAG_TEST_RX_DP + TEST_RX_DP USB D+ rx value in test 5 1 read-only - USB_SERIAL_JTAG_TEST_RX_DM + TEST_RX_DM USB D- rx value in test 6 1 @@ -70307,56 +67425,56 @@ protection is enabled. 0x00000044 - USB_SERIAL_JTAG_IN_FIFO_CNT + IN_FIFO_CNT JTAT in fifo counter. 0 2 read-only - USB_SERIAL_JTAG_IN_FIFO_EMPTY + IN_FIFO_EMPTY 1: JTAG in fifo is empty. 2 1 read-only - USB_SERIAL_JTAG_IN_FIFO_FULL + IN_FIFO_FULL 1: JTAG in fifo is full. 3 1 read-only - USB_SERIAL_JTAG_OUT_FIFO_CNT + OUT_FIFO_CNT JTAT out fifo counter. 4 2 read-only - USB_SERIAL_JTAG_OUT_FIFO_EMPTY + OUT_FIFO_EMPTY 1: JTAG out fifo is empty. 6 1 read-only - USB_SERIAL_JTAG_OUT_FIFO_FULL + OUT_FIFO_FULL 1: JTAG out fifo is full. 7 1 read-only - USB_SERIAL_JTAG_IN_FIFO_RESET + IN_FIFO_RESET Write 1 to reset JTAG in fifo. 8 1 read-write - USB_SERIAL_JTAG_OUT_FIFO_RESET + OUT_FIFO_RESET Write 1 to reset JTAG out fifo. 9 1 @@ -70371,7 +67489,7 @@ protection is enabled. 0x20 - USB_SERIAL_JTAG_SOF_FRAME_INDEX + SOF_FRAME_INDEX Frame index of received SOF frame. 0 11 @@ -70387,21 +67505,21 @@ protection is enabled. 0x00000001 - USB_SERIAL_JTAG_IN_EP0_STATE + IN_EP0_STATE State of IN Endpoint 0. 0 2 read-only - USB_SERIAL_JTAG_IN_EP0_WR_ADDR + IN_EP0_WR_ADDR Write data address of IN endpoint 0. 2 7 read-only - USB_SERIAL_JTAG_IN_EP0_RD_ADDR + IN_EP0_RD_ADDR Read data address of IN endpoint 0. 9 7 @@ -70417,21 +67535,21 @@ protection is enabled. 0x00000001 - USB_SERIAL_JTAG_IN_EP1_STATE + IN_EP1_STATE State of IN Endpoint 1. 0 2 read-only - USB_SERIAL_JTAG_IN_EP1_WR_ADDR + IN_EP1_WR_ADDR Write data address of IN endpoint 1. 2 7 read-only - USB_SERIAL_JTAG_IN_EP1_RD_ADDR + IN_EP1_RD_ADDR Read data address of IN endpoint 1. 9 7 @@ -70447,21 +67565,21 @@ protection is enabled. 0x00000001 - USB_SERIAL_JTAG_IN_EP2_STATE + IN_EP2_STATE State of IN Endpoint 2. 0 2 read-only - USB_SERIAL_JTAG_IN_EP2_WR_ADDR + IN_EP2_WR_ADDR Write data address of IN endpoint 2. 2 7 read-only - USB_SERIAL_JTAG_IN_EP2_RD_ADDR + IN_EP2_RD_ADDR Read data address of IN endpoint 2. 9 7 @@ -70477,21 +67595,21 @@ protection is enabled. 0x00000001 - USB_SERIAL_JTAG_IN_EP3_STATE + IN_EP3_STATE State of IN Endpoint 3. 0 2 read-only - USB_SERIAL_JTAG_IN_EP3_WR_ADDR + IN_EP3_WR_ADDR Write data address of IN endpoint 3. 2 7 read-only - USB_SERIAL_JTAG_IN_EP3_RD_ADDR + IN_EP3_RD_ADDR Read data address of IN endpoint 3. 9 7 @@ -70506,21 +67624,21 @@ protection is enabled. 0x20 - USB_SERIAL_JTAG_OUT_EP0_STATE + OUT_EP0_STATE State of OUT Endpoint 0. 0 2 read-only - USB_SERIAL_JTAG_OUT_EP0_WR_ADDR + OUT_EP0_WR_ADDR Write data address of OUT endpoint 0. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0. 2 7 read-only - USB_SERIAL_JTAG_OUT_EP0_RD_ADDR + OUT_EP0_RD_ADDR Read data address of OUT endpoint 0. 9 7 @@ -70535,28 +67653,28 @@ protection is enabled. 0x20 - USB_SERIAL_JTAG_OUT_EP1_STATE + OUT_EP1_STATE State of OUT Endpoint 1. 0 2 read-only - USB_SERIAL_JTAG_OUT_EP1_WR_ADDR + OUT_EP1_WR_ADDR Write data address of OUT endpoint 1. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1. 2 7 read-only - USB_SERIAL_JTAG_OUT_EP1_RD_ADDR + OUT_EP1_RD_ADDR Read data address of OUT endpoint 1. 9 7 read-only - USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT + OUT_EP1_REC_DATA_CNT Data count in OUT endpoint 1 when one packet is received. 16 7 @@ -70571,21 +67689,21 @@ protection is enabled. 0x20 - USB_SERIAL_JTAG_OUT_EP2_STATE + OUT_EP2_STATE State of OUT Endpoint 2. 0 2 read-only - USB_SERIAL_JTAG_OUT_EP2_WR_ADDR + OUT_EP2_WR_ADDR Write data address of OUT endpoint 2. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2. 2 7 read-only - USB_SERIAL_JTAG_OUT_EP2_RD_ADDR + OUT_EP2_RD_ADDR Read data address of OUT endpoint 2. 9 7 @@ -70600,7 +67718,7 @@ protection is enabled. 0x20 - USB_SERIAL_JTAG_CLK_EN + CLK_EN 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers. 0 1 @@ -70616,14 +67734,14 @@ protection is enabled. 0x00000002 - USB_SERIAL_JTAG_USB_MEM_PD + USB_MEM_PD 1: power down usb memory. 0 1 read-write - USB_SERIAL_JTAG_USB_MEM_CLK_EN + USB_MEM_CLK_EN 1: Force clock on for usb memory. 1 1 @@ -70638,21 +67756,21 @@ protection is enabled. 0x20 - USB_SERIAL_JTAG_RTS + RTS 1: Chip reset is detected from usb serial channel. Software write 1 to clear it. 0 1 read-only - USB_SERIAL_JTAG_DTR + DTR 1: Chip reset is detected from usb jtag channel. Software write 1 to clear it. 1 1 read-only - USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS + USB_UART_CHIP_RST_DIS Set this bit to disable chip reset from usb serial channel to reset chip. 2 1 @@ -70667,7 +67785,7 @@ protection is enabled. 0x20 - USB_SERIAL_JTAG_DW_DTE_RATE + DW_DTE_RATE The value of dwDTERate set by host through SET_LINE_CODING command. 0 32 @@ -70682,21 +67800,21 @@ protection is enabled. 0x20 - USB_SERIAL_JTAG_BCHAR_FORMAT + BCHAR_FORMAT The value of bCharFormat set by host through SET_LINE_CODING command. 0 8 read-only - USB_SERIAL_JTAG_BPARITY_TYPE + BPARITY_TYPE The value of bParityTpye set by host through SET_LINE_CODING command. 8 8 read-only - USB_SERIAL_JTAG_BDATA_BITS + BDATA_BITS The value of bDataBits set by host through SET_LINE_CODING command. 16 8 @@ -70711,7 +67829,7 @@ protection is enabled. 0x20 - USB_SERIAL_JTAG_GET_DW_DTE_RATE + GET_DW_DTE_RATE The value of dwDTERate set by software which is requested by GET_LINE_CODING command. 0 32 @@ -70726,21 +67844,21 @@ protection is enabled. 0x20 - USB_SERIAL_JTAG_GET_BDATA_BITS + GET_BDATA_BITS The value of bCharFormat set by software which is requested by GET_LINE_CODING command. 0 8 read-write - USB_SERIAL_JTAG_GET_BPARITY_TYPE + GET_BPARITY_TYPE The value of bParityTpye set by software which is requested by GET_LINE_CODING command. 8 8 read-write - USB_SERIAL_JTAG_GET_BCHAR_FORMAT + GET_BCHAR_FORMAT The value of bDataBits set by software which is requested by GET_LINE_CODING command. 16 8 @@ -70755,7 +67873,7 @@ protection is enabled. 0x20 - USB_SERIAL_JTAG_CONFIG_UPDATE + CONFIG_UPDATE Write 1 to this register would update the value of configure registers from APB clock domain to 48MHz clock domain. 0 1 @@ -70771,42 +67889,42 @@ protection is enabled. 0x00000010 - USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR + SERIAL_IN_AFIFO_RESET_WR Write 1 to reset CDC_ACM IN async FIFO write clock domain. 0 1 read-write - USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD + SERIAL_IN_AFIFO_RESET_RD Write 1 to reset CDC_ACM IN async FIFO read clock domain. 1 1 read-write - USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR + SERIAL_OUT_AFIFO_RESET_WR Write 1 to reset CDC_ACM OUT async FIFO write clock domain. 2 1 read-write - USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD + SERIAL_OUT_AFIFO_RESET_RD Write 1 to reset CDC_ACM OUT async FIFO read clock domain. 3 1 read-write - USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY + SERIAL_OUT_AFIFO_REMPTY CDC_ACM OUTOUT async FIFO empty signal in read clock domain. 4 1 read-only - USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL + SERIAL_IN_AFIFO_WFULL CDC_ACM OUT IN async FIFO empty signal in write clock domain. 5 1 @@ -70822,7 +67940,7 @@ protection is enabled. 0x00000001 - USB_SERIAL_JTAG_USB_BUS_RESET_ST + USB_BUS_RESET_ST USB bus reset status. 0: USB-Serial-JTAG is in usb bus reset status. 1: USB bus reset is released. 0 1 @@ -70838,7 +67956,7 @@ protection is enabled. 0x02109220 - USB_SERIAL_JTAG_DATE + DATE register version. 0 32 diff --git a/svd/esp32h2.svd b/svd/esp32h2.svd index 8a5d293..0eba39c 100644 --- a/svd/esp32h2.svd +++ b/svd/esp32h2.svd @@ -4,10 +4,10 @@ ESPRESSIF ESP32-H2 ESP32 H-Series - 1 + 2 32-bit RISC-V MCU & IEEE 802.15.4 & Bluetooth 5 (LE) - Copyright 2022 Espressif Systems (Shanghai) PTE LTD + Copyright 2023 Espressif Systems (Shanghai) PTE LTD Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -39,7 +39,7 @@ AES AES (Advanced Encryption Standard) Accelerator AES - 0x6003A000 + 0x60088000 0x0 0xBC @@ -554,7 +554,7 @@ APB_SARADC Successive Approximation Register Analog to Digital Converter APB_SARADC - 0x60040000 + 0x6000E000 0x0 0x70 @@ -2421,7 +2421,7 @@ GDMA DMA (Direct Memory Access) Controller DMA - 0x6003F000 + 0x60080000 0x0 0x1A4 @@ -3858,7 +3858,7 @@ ECC ECC (ECC Hardware Accelerator) ECC - 0x60039000 + 0x6008B000 0x0 0x78 @@ -4043,7 +4043,7 @@ EFUSE eFuse Controller EFUSE - 0x6001A000 + 0x600B0800 0x0 0x1D0 @@ -6837,10 +6837,10 @@ GPIO General Purpose Input/Output GPIO - 0x60004000 + 0x60091000 0x0 - 0x2A8 + 0x34C registers @@ -7167,7 +7167,10 @@ - FUNC0_IN_SEL_CFG + 128 + 0x4 + 0-127 + FUNC%s_IN_SEL_CFG GPIO input function configuration register 0x154 0x20 @@ -7197,2619 +7200,2386 @@ - FUNC6_IN_SEL_CFG - GPIO input function configuration register - 0x16C + 32 + 0x4 + FUNC%s_OUT_SEL_CFG + GPIO output function select register + 0x554 0x20 - 0x0000003C + 0x00000080 - IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + OUT_SEL + The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals GPIO_OUT_REG[n]. 0 - 6 + 8 read-write - IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 + INV_SEL + set this bit to invert output signal.1:invert.0:not invert. + 8 1 read-write - SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + OEN_SEL + set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output enable signal.0:use peripheral output enable signal. + 9 + 1 + read-write + + + OEN_INV_SEL + set this bit to invert output enable signal.1:invert.0:not invert. + 10 1 read-write - FUNC7_IN_SEL_CFG - GPIO input function configuration register - 0x170 + CLOCK_GATE + GPIO clock gate register + 0x62C 0x20 - 0x0000003C + 0x00000001 - IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + CLK_EN + set this bit to enable GPIO clock gate 0 - 6 - read-write - - - IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 1 read-write - FUNC8_IN_SEL_CFG - GPIO input function configuration register - 0x174 + DATE + GPIO version register + 0x6FC 0x20 - 0x0000003C + 0x02201120 - IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + DATE + version register 0 - 6 + 28 read-write + + + + + + HMAC + HMAC (Hash-based Message Authentication Code) Accelerator + HMAC + 0x6008D000 + + 0x0 + 0xA4 + registers + + + + SET_START + Process control register 0. + 0x40 + 0x20 + - IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 + SET_START + Start hmac operation. + 0 1 - read-write + write-only + + + + SET_PARA_PURPOSE + Configure purpose. + 0x44 + 0x20 + - SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + PURPOSE_SET + Set hmac parameter purpose. + 0 + 4 + write-only - FUNC9_IN_SEL_CFG - GPIO input function configuration register - 0x178 + SET_PARA_KEY + Configure key. + 0x48 0x20 - 0x00000038 - IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + KEY_SET + Set hmac parameter key. 0 - 6 - read-write + 3 + write-only + + + + SET_PARA_FINISH + Finish initial configuration. + 0x4C + 0x20 + - IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 + SET_PARA_END + Finish hmac configuration. + 0 1 - read-write + write-only + + + + SET_MESSAGE_ONE + Process control register 1. + 0x50 + 0x20 + - SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + SET_TEXT_ONE + Call SHA to calculate one message block. + 0 1 - read-write + write-only - FUNC10_IN_SEL_CFG - GPIO input function configuration register - 0x17C + SET_MESSAGE_ING + Process control register 2. + 0x54 0x20 - 0x0000003C - IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + SET_TEXT_ING + Continue typical hmac. 0 - 6 - read-write - - - IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 1 - read-write + write-only + + + + SET_MESSAGE_END + Process control register 3. + 0x58 + 0x20 + - SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + SET_TEXT_END + Start hardware padding. + 0 1 - read-write + write-only - FUNC11_IN_SEL_CFG - GPIO input function configuration register - 0x180 + SET_RESULT_FINISH + Process control register 4. + 0x5C 0x20 - 0x0000003C - IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + SET_RESULT_END + After read result from upstream, then let hmac back to idle. 0 - 6 - read-write - - - IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 1 - read-write + write-only + + + + SET_INVALIDATE_JTAG + Invalidate register 0. + 0x60 + 0x20 + - SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + SET_INVALIDATE_JTAG + Clear result from hmac downstream JTAG. + 0 1 - read-write + write-only - FUNC12_IN_SEL_CFG - GPIO input function configuration register - 0x184 + SET_INVALIDATE_DS + Invalidate register 1. + 0x64 0x20 - 0x0000003C - IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + SET_INVALIDATE_DS + Clear result from hmac downstream DS. 0 - 6 - read-write - - - IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 1 - read-write + write-only + + + + QUERY_ERROR + Error register. + 0x68 + 0x20 + - SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + QUREY_CHECK + Hmac configuration state. 0: key are agree with purpose. 1: error + 0 1 - read-write + read-only - FUNC13_IN_SEL_CFG - GPIO input function configuration register - 0x188 + QUERY_BUSY + Busy register. + 0x6C 0x20 - 0x0000003C - IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + BUSY_STATE + Hmac state. 1'b0: idle. 1'b1: busy 0 - 6 - read-write - - - IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 1 - read-write + read-only + + + + 64 + 0x1 + WR_MESSAGE_MEM[%s] + Message block memory. + 0x80 + 0x8 + + + 32 + 0x1 + RD_RESULT_MEM[%s] + Result from upstream. + 0xC0 + 0x8 + + + SET_MESSAGE_PAD + Process control register 5. + 0xF0 + 0x20 + - SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + SET_TEXT_PAD + Start software padding. + 0 1 - read-write + write-only - FUNC14_IN_SEL_CFG - GPIO input function configuration register - 0x18C + ONE_BLOCK + Process control register 6. + 0xF4 0x20 - 0x0000003C - IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + SET_ONE_BLOCK + Don't have to do padding. 0 - 6 - read-write - - - IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 1 - read-write + write-only + + + + SOFT_JTAG_CTRL + Jtag register 0. + 0xF8 + 0x20 + - SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + SOFT_JTAG_CTRL + Turn on JTAG verification. + 0 1 - read-write + write-only - FUNC15_IN_SEL_CFG - GPIO input function configuration register - 0x190 + WR_JTAG + Jtag register 1. + 0xFC 0x20 - 0x0000003C - IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + WR_JTAG + 32-bit of key to be compared. 0 - 6 - read-write - - - IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write + 32 + write-only + + + + DATE + Date register. + 0x1FC + 0x20 + 0x20200618 + - SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 + DATE + Hmac date information/ hmac version information. + 0 + 30 read-write + + + + HP_APM + Peripheral HP_APM + HP_APM + 0x60099000 + + 0x0 + 0x114 + registers + + - FUNC16_IN_SEL_CFG - GPIO input function configuration register - 0x194 + REGION_FILTER_EN + Region filter enable register + 0x0 0x20 - 0x0000003C + 0x00000001 - IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + REGION_FILTER_EN + Region filter enable 0 - 6 + 16 read-write + + + + REGION0_ADDR_START + Region address register + 0x4 + 0x20 + - IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 + REGION0_ADDR_START + Start address of region0 + 0 + 32 read-write + + + + REGION0_ADDR_END + Region address register + 0x8 + 0x20 + 0xFFFFFFFF + - SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 + REGION0_ADDR_END + End address of region0 + 0 + 32 read-write - FUNC17_IN_SEL_CFG - GPIO input function configuration register - 0x198 + REGION0_PMS_ATTR + Region access authority attribute register + 0xC 0x20 - 0x0000003C - IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + REGION0_R0_PMS_X + Region execute authority in REE_MODE0 0 - 6 + 1 read-write - IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 + REGION0_R0_PMS_W + Region write authority in REE_MODE0 + 1 1 read-write - SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + REGION0_R0_PMS_R + Region read authority in REE_MODE0 + 2 1 read-write - - - - FUNC19_IN_SEL_CFG - GPIO input function configuration register - 0x1A0 - 0x20 - 0x0000003C - - IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 + REGION0_R1_PMS_X + Region execute authority in REE_MODE1 + 4 + 1 read-write - IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 + REGION0_R1_PMS_W + Region write authority in REE_MODE1 + 5 1 read-write - SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + REGION0_R1_PMS_R + Region read authority in REE_MODE1 + 6 1 read-write - - - - FUNC28_IN_SEL_CFG - GPIO input function configuration register - 0x1C4 - 0x20 - 0x0000003C - - IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 + REGION0_R2_PMS_X + Region execute authority in REE_MODE2 + 8 + 1 read-write - IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 + REGION0_R2_PMS_W + Region write authority in REE_MODE2 + 9 1 read-write - SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + REGION0_R2_PMS_R + Region read authority in REE_MODE2 + 10 1 read-write - FUNC29_IN_SEL_CFG - GPIO input function configuration register - 0x1C8 + REGION1_ADDR_START + Region address register + 0x10 0x20 - 0x0000003C - IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + REGION1_ADDR_START + Start address of region1 0 - 6 + 32 read-write + + + + REGION1_ADDR_END + Region address register + 0x14 + 0x20 + 0xFFFFFFFF + - IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 + REGION1_ADDR_END + End address of region1 + 0 + 32 read-write - FUNC30_IN_SEL_CFG - GPIO input function configuration register - 0x1CC + REGION1_PMS_ATTR + Region access authority attribute register + 0x18 0x20 - 0x0000003C - IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + REGION1_R0_PMS_X + Region execute authority in REE_MODE0 0 - 6 + 1 read-write - IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 + REGION1_R0_PMS_W + Region write authority in REE_MODE0 + 1 1 read-write - SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + REGION1_R0_PMS_R + Region read authority in REE_MODE0 + 2 1 read-write - - - - FUNC31_IN_SEL_CFG - GPIO input function configuration register - 0x1D0 - 0x20 - 0x0000003C - - IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 + REGION1_R1_PMS_X + Region execute authority in REE_MODE1 + 4 + 1 read-write - IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 + REGION1_R1_PMS_W + Region write authority in REE_MODE1 + 5 1 read-write - SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + REGION1_R1_PMS_R + Region read authority in REE_MODE1 + 6 1 read-write - - - - FUNC32_IN_SEL_CFG - GPIO input function configuration register - 0x1D4 - 0x20 - 0x0000003C - - IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 + REGION1_R2_PMS_X + Region execute authority in REE_MODE2 + 8 + 1 read-write - IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 + REGION1_R2_PMS_W + Region write authority in REE_MODE2 + 9 1 read-write - SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + REGION1_R2_PMS_R + Region read authority in REE_MODE2 + 10 1 read-write - FUNC33_IN_SEL_CFG - GPIO input function configuration register - 0x1D8 + REGION2_ADDR_START + Region address register + 0x1C 0x20 - 0x0000003C - IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + REGION2_ADDR_START + Start address of region2 0 - 6 - read-write - - - IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 + 32 read-write + + + + REGION2_ADDR_END + Region address register + 0x20 + 0x20 + 0xFFFFFFFF + - SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 + REGION2_ADDR_END + End address of region2 + 0 + 32 read-write - FUNC34_IN_SEL_CFG - GPIO input function configuration register - 0x1DC + REGION2_PMS_ATTR + Region access authority attribute register + 0x24 0x20 - 0x0000003C - IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + REGION2_R0_PMS_X + Region execute authority in REE_MODE0 0 - 6 + 1 read-write - IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 + REGION2_R0_PMS_W + Region write authority in REE_MODE0 + 1 1 read-write - SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + REGION2_R0_PMS_R + Region read authority in REE_MODE0 + 2 1 read-write - - - - FUNC35_IN_SEL_CFG - GPIO input function configuration register - 0x1E0 - 0x20 - 0x0000003C - - IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 + REGION2_R1_PMS_X + Region execute authority in REE_MODE1 + 4 + 1 read-write - IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 + REGION2_R1_PMS_W + Region write authority in REE_MODE1 + 5 1 read-write - SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + REGION2_R1_PMS_R + Region read authority in REE_MODE1 + 6 1 read-write - - - - FUNC40_IN_SEL_CFG - GPIO input function configuration register - 0x1F4 - 0x20 - 0x0000003C - - IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 + REGION2_R2_PMS_X + Region execute authority in REE_MODE2 + 8 + 1 read-write - IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 + REGION2_R2_PMS_W + Region write authority in REE_MODE2 + 9 1 read-write - SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + REGION2_R2_PMS_R + Region read authority in REE_MODE2 + 10 1 read-write - FUNC41_IN_SEL_CFG - GPIO input function configuration register - 0x1F8 + REGION3_ADDR_START + Region address register + 0x28 0x20 - 0x0000003C - IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + REGION3_ADDR_START + Start address of region3 0 - 6 - read-write - - - IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 + 32 read-write + + + + REGION3_ADDR_END + Region address register + 0x2C + 0x20 + 0xFFFFFFFF + - SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 + REGION3_ADDR_END + End address of region3 + 0 + 32 read-write - FUNC42_IN_SEL_CFG - GPIO input function configuration register - 0x1FC + REGION3_PMS_ATTR + Region access authority attribute register + 0x30 0x20 - 0x0000003C - IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + REGION3_R0_PMS_X + Region execute authority in REE_MODE0 0 - 6 + 1 read-write - IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 + REGION3_R0_PMS_W + Region write authority in REE_MODE0 + 1 1 read-write - SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + REGION3_R0_PMS_R + Region read authority in REE_MODE0 + 2 1 read-write - - - - FUNC45_IN_SEL_CFG - GPIO input function configuration register - 0x208 - 0x20 - 0x00000038 - - IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 + REGION3_R1_PMS_X + Region execute authority in REE_MODE1 + 4 + 1 read-write - IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 + REGION3_R1_PMS_W + Region write authority in REE_MODE1 + 5 1 read-write - SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + REGION3_R1_PMS_R + Region read authority in REE_MODE1 + 6 1 read-write - - - - FUNC46_IN_SEL_CFG - GPIO input function configuration register - 0x20C - 0x20 - 0x00000038 - - IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 + REGION3_R2_PMS_X + Region execute authority in REE_MODE2 + 8 + 1 read-write - IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 + REGION3_R2_PMS_W + Region write authority in REE_MODE2 + 9 1 read-write - SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + REGION3_R2_PMS_R + Region read authority in REE_MODE2 + 10 1 read-write - FUNC47_IN_SEL_CFG - GPIO input function configuration register - 0x210 + REGION4_ADDR_START + Region address register + 0x34 0x20 - 0x0000003C - IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + REGION4_ADDR_START + Start address of region4 0 - 6 - read-write - - - IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 + 32 read-write + + + + REGION4_ADDR_END + Region address register + 0x38 + 0x20 + 0xFFFFFFFF + - SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 + REGION4_ADDR_END + End address of region4 + 0 + 32 read-write - FUNC48_IN_SEL_CFG - GPIO input function configuration register - 0x214 + REGION4_PMS_ATTR + Region access authority attribute register + 0x3C 0x20 - 0x0000003C - IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + REGION4_R0_PMS_X + Region execute authority in REE_MODE0 0 - 6 + 1 read-write - IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 + REGION4_R0_PMS_W + Region write authority in REE_MODE0 + 1 1 read-write - SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + REGION4_R0_PMS_R + Region read authority in REE_MODE0 + 2 1 read-write - - - - FUNC49_IN_SEL_CFG - GPIO input function configuration register - 0x218 - 0x20 - 0x0000003C - - IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 + REGION4_R1_PMS_X + Region execute authority in REE_MODE1 + 4 + 1 read-write - IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 + REGION4_R1_PMS_W + Region write authority in REE_MODE1 + 5 1 read-write - SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + REGION4_R1_PMS_R + Region read authority in REE_MODE1 + 6 1 read-write - - - - FUNC50_IN_SEL_CFG - GPIO input function configuration register - 0x21C - 0x20 - 0x0000003C - - IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 + REGION4_R2_PMS_X + Region execute authority in REE_MODE2 + 8 + 1 read-write - IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 + REGION4_R2_PMS_W + Region write authority in REE_MODE2 + 9 1 read-write - SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + REGION4_R2_PMS_R + Region read authority in REE_MODE2 + 10 1 read-write - FUNC51_IN_SEL_CFG - GPIO input function configuration register - 0x220 + REGION5_ADDR_START + Region address register + 0x40 0x20 - 0x0000003C - IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + REGION5_ADDR_START + Start address of region5 0 - 6 - read-write - - - IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 + 32 read-write + + + + REGION5_ADDR_END + Region address register + 0x44 + 0x20 + 0xFFFFFFFF + - SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 + REGION5_ADDR_END + End address of region5 + 0 + 32 read-write - FUNC52_IN_SEL_CFG - GPIO input function configuration register - 0x224 + REGION5_PMS_ATTR + Region access authority attribute register + 0x48 0x20 - 0x0000003C - IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + REGION5_R0_PMS_X + Region execute authority in REE_MODE0 0 - 6 + 1 read-write - IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 + REGION5_R0_PMS_W + Region write authority in REE_MODE0 + 1 1 read-write - SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + REGION5_R0_PMS_R + Region read authority in REE_MODE0 + 2 1 read-write - - - - FUNC53_IN_SEL_CFG - GPIO input function configuration register - 0x228 - 0x20 - 0x0000003C - - IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 + REGION5_R1_PMS_X + Region execute authority in REE_MODE1 + 4 + 1 read-write - IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 + REGION5_R1_PMS_W + Region write authority in REE_MODE1 + 5 1 read-write - SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + REGION5_R1_PMS_R + Region read authority in REE_MODE1 + 6 1 read-write - - - - FUNC54_IN_SEL_CFG - GPIO input function configuration register - 0x22C - 0x20 - 0x0000003C - - IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 + REGION5_R2_PMS_X + Region execute authority in REE_MODE2 + 8 + 1 read-write - IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 + REGION5_R2_PMS_W + Region write authority in REE_MODE2 + 9 1 read-write - SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + REGION5_R2_PMS_R + Region read authority in REE_MODE2 + 10 1 read-write - FUNC55_IN_SEL_CFG - GPIO input function configuration register - 0x230 + REGION6_ADDR_START + Region address register + 0x4C 0x20 - 0x00000038 - IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + REGION6_ADDR_START + Start address of region6 0 - 6 - read-write - - - IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 + 32 read-write + + + + REGION6_ADDR_END + Region address register + 0x50 + 0x20 + 0xFFFFFFFF + - SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 + REGION6_ADDR_END + End address of region6 + 0 + 32 read-write - FUNC56_IN_SEL_CFG - GPIO input function configuration register - 0x234 + REGION6_PMS_ATTR + Region access authority attribute register + 0x54 0x20 - 0x00000038 - IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + REGION6_R0_PMS_X + Region execute authority in REE_MODE0 0 - 6 + 1 read-write - IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 + REGION6_R0_PMS_W + Region write authority in REE_MODE0 + 1 1 read-write - SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + REGION6_R0_PMS_R + Region read authority in REE_MODE0 + 2 1 read-write - - - - FUNC63_IN_SEL_CFG - GPIO input function configuration register - 0x250 - 0x20 - 0x0000003C - - IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 + REGION6_R1_PMS_X + Region execute authority in REE_MODE1 + 4 + 1 read-write - IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 + REGION6_R1_PMS_W + Region write authority in REE_MODE1 + 5 1 read-write - SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + REGION6_R1_PMS_R + Region read authority in REE_MODE1 + 6 1 read-write - - - - FUNC64_IN_SEL_CFG - GPIO input function configuration register - 0x254 - 0x20 - 0x0000003C - - IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 + REGION6_R2_PMS_X + Region execute authority in REE_MODE2 + 8 + 1 read-write - IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 + REGION6_R2_PMS_W + Region write authority in REE_MODE2 + 9 1 read-write - SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + REGION6_R2_PMS_R + Region read authority in REE_MODE2 + 10 1 read-write - FUNC65_IN_SEL_CFG - GPIO input function configuration register - 0x258 + REGION7_ADDR_START + Region address register + 0x58 0x20 - 0x0000003C - IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + REGION7_ADDR_START + Start address of region7 0 - 6 + 32 read-write + + + + REGION7_ADDR_END + Region address register + 0x5C + 0x20 + 0xFFFFFFFF + - IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 + REGION7_ADDR_END + End address of region7 + 0 + 32 read-write - FUNC66_IN_SEL_CFG - GPIO input function configuration register - 0x25C + REGION7_PMS_ATTR + Region access authority attribute register + 0x60 0x20 - 0x0000003C - IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + REGION7_R0_PMS_X + Region execute authority in REE_MODE0 0 - 6 + 1 read-write - IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 + REGION7_R0_PMS_W + Region write authority in REE_MODE0 + 1 1 read-write - SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + REGION7_R0_PMS_R + Region read authority in REE_MODE0 + 2 1 read-write - - - - FUNC67_IN_SEL_CFG - GPIO input function configuration register - 0x260 - 0x20 - 0x0000003C - - IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 + REGION7_R1_PMS_X + Region execute authority in REE_MODE1 + 4 + 1 read-write - IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 + REGION7_R1_PMS_W + Region write authority in REE_MODE1 + 5 1 read-write - SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + REGION7_R1_PMS_R + Region read authority in REE_MODE1 + 6 1 read-write - - - - FUNC68_IN_SEL_CFG - GPIO input function configuration register - 0x264 - 0x20 - 0x0000003C - - IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 + REGION7_R2_PMS_X + Region execute authority in REE_MODE2 + 8 + 1 read-write - IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 + REGION7_R2_PMS_W + Region write authority in REE_MODE2 + 9 1 read-write - SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + REGION7_R2_PMS_R + Region read authority in REE_MODE2 + 10 1 read-write - FUNC69_IN_SEL_CFG - GPIO input function configuration register - 0x268 + REGION8_ADDR_START + Region address register + 0x64 0x20 - 0x0000003C - IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + REGION8_ADDR_START + Start address of region8 0 - 6 - read-write - - - IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 + 32 read-write - FUNC70_IN_SEL_CFG - GPIO input function configuration register - 0x26C + REGION8_ADDR_END + Region address register + 0x68 0x20 - 0x0000003C + 0xFFFFFFFF - IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + REGION8_ADDR_END + End address of region8 0 - 6 - read-write - - - IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 + 32 read-write - FUNC71_IN_SEL_CFG - GPIO input function configuration register - 0x270 + REGION8_PMS_ATTR + Region access authority attribute register + 0x6C 0x20 - 0x0000003C - IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + REGION8_R0_PMS_X + Region execute authority in REE_MODE0 0 - 6 + 1 read-write - IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 + REGION8_R0_PMS_W + Region write authority in REE_MODE0 + 1 1 read-write - SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + REGION8_R0_PMS_R + Region read authority in REE_MODE0 + 2 1 read-write - - - - FUNC72_IN_SEL_CFG - GPIO input function configuration register - 0x274 - 0x20 - 0x0000003C - - IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 + REGION8_R1_PMS_X + Region execute authority in REE_MODE1 + 4 + 1 read-write - IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 + REGION8_R1_PMS_W + Region write authority in REE_MODE1 + 5 1 read-write - SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + REGION8_R1_PMS_R + Region read authority in REE_MODE1 + 6 1 read-write - - - - FUNC73_IN_SEL_CFG - GPIO input function configuration register - 0x278 - 0x20 - 0x00000038 - - IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 + REGION8_R2_PMS_X + Region execute authority in REE_MODE2 + 8 + 1 read-write - IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 + REGION8_R2_PMS_W + Region write authority in REE_MODE2 + 9 1 read-write - SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + REGION8_R2_PMS_R + Region read authority in REE_MODE2 + 10 1 read-write - FUNC81_IN_SEL_CFG - GPIO input function configuration register - 0x298 + REGION9_ADDR_START + Region address register + 0x70 0x20 - 0x0000003C - IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + REGION9_ADDR_START + Start address of region9 0 - 6 - read-write - - - IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 + 32 read-write + + + + REGION9_ADDR_END + Region address register + 0x74 + 0x20 + 0xFFFFFFFF + - SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 + REGION9_ADDR_END + End address of region9 + 0 + 32 read-write - FUNC82_IN_SEL_CFG - GPIO input function configuration register - 0x29C + REGION9_PMS_ATTR + Region access authority attribute register + 0x78 0x20 - 0x0000003C - IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + REGION9_R0_PMS_X + Region execute authority in REE_MODE0 0 - 6 + 1 read-write - IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 + REGION9_R0_PMS_W + Region write authority in REE_MODE0 + 1 1 read-write - SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + REGION9_R0_PMS_R + Region read authority in REE_MODE0 + 2 1 read-write - - - - FUNC87_IN_SEL_CFG - GPIO input function configuration register - 0x2B0 - 0x20 - 0x0000003C - - IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 + REGION9_R1_PMS_X + Region execute authority in REE_MODE1 + 4 + 1 read-write - IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 + REGION9_R1_PMS_W + Region write authority in REE_MODE1 + 5 1 read-write - SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + REGION9_R1_PMS_R + Region read authority in REE_MODE1 + 6 1 read-write - - - - FUNC88_IN_SEL_CFG - GPIO input function configuration register - 0x2B4 - 0x20 - 0x0000003C - - IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 + REGION9_R2_PMS_X + Region execute authority in REE_MODE2 + 8 + 1 read-write - IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 + REGION9_R2_PMS_W + Region write authority in REE_MODE2 + 9 1 read-write - SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + REGION9_R2_PMS_R + Region read authority in REE_MODE2 + 10 1 read-write - FUNC89_IN_SEL_CFG - GPIO input function configuration register - 0x2B8 + REGION10_ADDR_START + Region address register + 0x7C 0x20 - 0x0000003C - IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + REGION10_ADDR_START + Start address of region10 0 - 6 - read-write - - - IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 + 32 read-write + + + + REGION10_ADDR_END + Region address register + 0x80 + 0x20 + 0xFFFFFFFF + - SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 + REGION10_ADDR_END + End address of region10 + 0 + 32 read-write - FUNC90_IN_SEL_CFG - GPIO input function configuration register - 0x2BC + REGION10_PMS_ATTR + Region access authority attribute register + 0x84 0x20 - 0x0000003C - IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + REGION10_R0_PMS_X + Region execute authority in REE_MODE0 0 - 6 + 1 read-write - IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 + REGION10_R0_PMS_W + Region write authority in REE_MODE0 + 1 1 read-write - SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + REGION10_R0_PMS_R + Region read authority in REE_MODE0 + 2 1 read-write - - - - FUNC91_IN_SEL_CFG - GPIO input function configuration register - 0x2C0 - 0x20 - 0x0000003C - - IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 + REGION10_R1_PMS_X + Region execute authority in REE_MODE1 + 4 + 1 read-write - IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 + REGION10_R1_PMS_W + Region write authority in REE_MODE1 + 5 1 read-write - SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + REGION10_R1_PMS_R + Region read authority in REE_MODE1 + 6 1 read-write - - - - FUNC92_IN_SEL_CFG - GPIO input function configuration register - 0x2C4 - 0x20 - 0x0000003C - - IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 + REGION10_R2_PMS_X + Region execute authority in REE_MODE2 + 8 + 1 read-write - IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 + REGION10_R2_PMS_W + Region write authority in REE_MODE2 + 9 1 read-write - SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + REGION10_R2_PMS_R + Region read authority in REE_MODE2 + 10 1 read-write - FUNC93_IN_SEL_CFG - GPIO input function configuration register - 0x2C8 + REGION11_ADDR_START + Region address register + 0x88 0x20 - 0x0000003C - IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + REGION11_ADDR_START + Start address of region11 0 - 6 - read-write - - - IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 + 32 read-write + + + + REGION11_ADDR_END + Region address register + 0x8C + 0x20 + 0xFFFFFFFF + - SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 + REGION11_ADDR_END + End address of region11 + 0 + 32 read-write - FUNC94_IN_SEL_CFG - GPIO input function configuration register - 0x2CC + REGION11_PMS_ATTR + Region access authority attribute register + 0x90 0x20 - 0x0000003C - IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + REGION11_R0_PMS_X + Region execute authority in REE_MODE0 0 - 6 + 1 read-write - IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 + REGION11_R0_PMS_W + Region write authority in REE_MODE0 + 1 1 read-write - SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + REGION11_R0_PMS_R + Region read authority in REE_MODE0 + 2 1 read-write - - - - FUNC95_IN_SEL_CFG - GPIO input function configuration register - 0x2D0 - 0x20 - 0x0000003C - - IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 + REGION11_R1_PMS_X + Region execute authority in REE_MODE1 + 4 + 1 read-write - IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 + REGION11_R1_PMS_W + Region write authority in REE_MODE1 + 5 1 read-write - SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + REGION11_R1_PMS_R + Region read authority in REE_MODE1 + 6 1 read-write - - - - FUNC97_IN_SEL_CFG - GPIO input function configuration register - 0x2D8 - 0x20 - 0x0000003C - - IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 + REGION11_R2_PMS_X + Region execute authority in REE_MODE2 + 8 + 1 read-write - IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 + REGION11_R2_PMS_W + Region write authority in REE_MODE2 + 9 1 read-write - SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + REGION11_R2_PMS_R + Region read authority in REE_MODE2 + 10 1 read-write - FUNC98_IN_SEL_CFG - GPIO input function configuration register - 0x2DC + REGION12_ADDR_START + Region address register + 0x94 0x20 - 0x0000003C - IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + REGION12_ADDR_START + Start address of region12 0 - 6 - read-write - - - IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 + 32 read-write + + + + REGION12_ADDR_END + Region address register + 0x98 + 0x20 + 0xFFFFFFFF + - SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 + REGION12_ADDR_END + End address of region12 + 0 + 32 read-write - FUNC99_IN_SEL_CFG - GPIO input function configuration register - 0x2E0 + REGION12_PMS_ATTR + Region access authority attribute register + 0x9C 0x20 - 0x0000003C - IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + REGION12_R0_PMS_X + Region execute authority in REE_MODE0 0 - 6 + 1 read-write - IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 + REGION12_R0_PMS_W + Region write authority in REE_MODE0 + 1 1 read-write - SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + REGION12_R0_PMS_R + Region read authority in REE_MODE0 + 2 1 read-write - - - - FUNC100_IN_SEL_CFG - GPIO input function configuration register - 0x2E4 - 0x20 - 0x0000003C - - IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 + REGION12_R1_PMS_X + Region execute authority in REE_MODE1 + 4 + 1 read-write - IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 + REGION12_R1_PMS_W + Region write authority in REE_MODE1 + 5 1 read-write - SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + REGION12_R1_PMS_R + Region read authority in REE_MODE1 + 6 1 read-write - - - - FUNC101_IN_SEL_CFG - GPIO input function configuration register - 0x2E8 - 0x20 - 0x0000003C - - IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 + REGION12_R2_PMS_X + Region execute authority in REE_MODE2 + 8 + 1 read-write - IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 + REGION12_R2_PMS_W + Region write authority in REE_MODE2 + 9 1 read-write - SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + REGION12_R2_PMS_R + Region read authority in REE_MODE2 + 10 1 read-write - FUNC102_IN_SEL_CFG - GPIO input function configuration register - 0x2EC + REGION13_ADDR_START + Region address register + 0xA0 0x20 - 0x0000003C - IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + REGION13_ADDR_START + Start address of region13 0 - 6 - read-write - - - IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 + 32 read-write + + + + REGION13_ADDR_END + Region address register + 0xA4 + 0x20 + 0xFFFFFFFF + - SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 + REGION13_ADDR_END + End address of region13 + 0 + 32 read-write - FUNC103_IN_SEL_CFG - GPIO input function configuration register - 0x2F0 + REGION13_PMS_ATTR + Region access authority attribute register + 0xA8 0x20 - 0x0000003C - IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + REGION13_R0_PMS_X + Region execute authority in REE_MODE0 0 - 6 + 1 read-write - IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 + REGION13_R0_PMS_W + Region write authority in REE_MODE0 + 1 1 read-write - SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + REGION13_R0_PMS_R + Region read authority in REE_MODE0 + 2 1 read-write - - - - FUNC104_IN_SEL_CFG - GPIO input function configuration register - 0x2F4 - 0x20 - 0x0000003C - - IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 + REGION13_R1_PMS_X + Region execute authority in REE_MODE1 + 4 + 1 read-write - IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 + REGION13_R1_PMS_W + Region write authority in REE_MODE1 + 5 1 read-write - SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + REGION13_R1_PMS_R + Region read authority in REE_MODE1 + 6 1 read-write - - - - FUNC105_IN_SEL_CFG - GPIO input function configuration register - 0x2F8 - 0x20 - 0x0000003C - - IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 + REGION13_R2_PMS_X + Region execute authority in REE_MODE2 + 8 + 1 read-write - IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 + REGION13_R2_PMS_W + Region write authority in REE_MODE2 + 9 1 read-write - SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + REGION13_R2_PMS_R + Region read authority in REE_MODE2 + 10 1 read-write - FUNC106_IN_SEL_CFG - GPIO input function configuration register - 0x2FC + REGION14_ADDR_START + Region address register + 0xAC 0x20 - 0x0000003C - IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + REGION14_ADDR_START + Start address of region14 0 - 6 - read-write - - - IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 + 32 read-write + + + + REGION14_ADDR_END + Region address register + 0xB0 + 0x20 + 0xFFFFFFFF + - SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 + REGION14_ADDR_END + End address of region14 + 0 + 32 read-write - FUNC107_IN_SEL_CFG - GPIO input function configuration register - 0x300 + REGION14_PMS_ATTR + Region access authority attribute register + 0xB4 0x20 - 0x0000003C - IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + REGION14_R0_PMS_X + Region execute authority in REE_MODE0 0 - 6 + 1 read-write - IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 + REGION14_R0_PMS_W + Region write authority in REE_MODE0 + 1 1 read-write - SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + REGION14_R0_PMS_R + Region read authority in REE_MODE0 + 2 1 read-write - - - - FUNC108_IN_SEL_CFG - GPIO input function configuration register - 0x304 - 0x20 - 0x0000003C - - IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 + REGION14_R1_PMS_X + Region execute authority in REE_MODE1 + 4 + 1 read-write - IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 + REGION14_R1_PMS_W + Region write authority in REE_MODE1 + 5 1 read-write - SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + REGION14_R1_PMS_R + Region read authority in REE_MODE1 + 6 1 read-write - - - - FUNC109_IN_SEL_CFG - GPIO input function configuration register - 0x308 - 0x20 - 0x0000003C - - IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 + REGION14_R2_PMS_X + Region execute authority in REE_MODE2 + 8 + 1 read-write - IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 + REGION14_R2_PMS_W + Region write authority in REE_MODE2 + 9 1 read-write - SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + REGION14_R2_PMS_R + Region read authority in REE_MODE2 + 10 1 read-write - FUNC110_IN_SEL_CFG - GPIO input function configuration register - 0x30C + REGION15_ADDR_START + Region address register + 0xB8 0x20 - 0x0000003C - IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + REGION15_ADDR_START + Start address of region15 0 - 6 - read-write - - - IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 + 32 read-write + + + + REGION15_ADDR_END + Region address register + 0xBC + 0x20 + 0xFFFFFFFF + - SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 + REGION15_ADDR_END + End address of region15 + 0 + 32 read-write - FUNC111_IN_SEL_CFG - GPIO input function configuration register - 0x310 + REGION15_PMS_ATTR + Region access authority attribute register + 0xC0 0x20 - 0x0000003C - IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + REGION15_R0_PMS_X + Region execute authority in REE_MODE0 0 - 6 + 1 read-write - IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 + REGION15_R0_PMS_W + Region write authority in REE_MODE0 + 1 1 read-write - SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + REGION15_R0_PMS_R + Region read authority in REE_MODE0 + 2 1 read-write - - - - FUNC112_IN_SEL_CFG - GPIO input function configuration register - 0x314 - 0x20 - 0x0000003C - - IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 + REGION15_R1_PMS_X + Region execute authority in REE_MODE1 + 4 + 1 read-write - IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 + REGION15_R1_PMS_W + Region write authority in REE_MODE1 + 5 1 read-write - SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + REGION15_R1_PMS_R + Region read authority in REE_MODE1 + 6 1 read-write - - - - FUNC113_IN_SEL_CFG - GPIO input function configuration register - 0x318 - 0x20 - 0x0000003C - - IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. - 0 - 6 + REGION15_R2_PMS_X + Region execute authority in REE_MODE2 + 8 + 1 read-write - IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 + REGION15_R2_PMS_W + Region write authority in REE_MODE2 + 9 1 read-write - SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + REGION15_R2_PMS_R + Region read authority in REE_MODE2 + 10 1 read-write - FUNC114_IN_SEL_CFG - GPIO input function configuration register - 0x31C + FUNC_CTRL + PMS function control register + 0xC4 0x20 - 0x0000003C + 0x0000000F - IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + M0_PMS_FUNC_EN + PMS M0 function enable 0 - 6 + 1 read-write - IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 + M1_PMS_FUNC_EN + PMS M1 function enable + 1 1 read-write - SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + M2_PMS_FUNC_EN + PMS M2 function enable + 2 + 1 + read-write + + + M3_PMS_FUNC_EN + PMS M3 function enable + 3 1 read-write - FUNC115_IN_SEL_CFG - GPIO input function configuration register - 0x320 + M0_STATUS + M0 status register + 0xC8 0x20 - 0x0000003C - IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + M0_EXCEPTION_STATUS + Exception status 0 - 6 - read-write - - - IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write + 2 + read-only + + + + M0_STATUS_CLR + M0 status clear register + 0xCC + 0x20 + - SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + M0_REGION_STATUS_CLR + Clear exception status + 0 1 - read-write + write-only - FUNC116_IN_SEL_CFG - GPIO input function configuration register - 0x324 + M0_EXCEPTION_INFO0 + M0 exception_info0 register + 0xD0 0x20 - 0x0000003C - IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + M0_EXCEPTION_REGION + Exception region 0 - 6 - read-write + 16 + read-only - IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write + M0_EXCEPTION_MODE + Exception mode + 16 + 2 + read-only - SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + M0_EXCEPTION_ID + Exception id information + 18 + 5 + read-only - FUNC117_IN_SEL_CFG - GPIO input function configuration register - 0x328 + M0_EXCEPTION_INFO1 + M0 exception_info1 register + 0xD4 0x20 - 0x0000003C - IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + M0_EXCEPTION_ADDR + Exception addr 0 - 6 - read-write + 32 + read-only + + + + M1_STATUS + M1 status register + 0xD8 + 0x20 + - IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write + M1_EXCEPTION_STATUS + Exception status + 0 + 2 + read-only + + + + M1_STATUS_CLR + M1 status clear register + 0xDC + 0x20 + - SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + M1_REGION_STATUS_CLR + Clear exception status + 0 1 - read-write + write-only - FUNC118_IN_SEL_CFG - GPIO input function configuration register - 0x32C + M1_EXCEPTION_INFO0 + M1 exception_info0 register + 0xE0 0x20 - 0x0000003C - IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + M1_EXCEPTION_REGION + Exception region 0 - 6 - read-write + 16 + read-only - IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write + M1_EXCEPTION_MODE + Exception mode + 16 + 2 + read-only - SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + M1_EXCEPTION_ID + Exception id information + 18 + 5 + read-only - FUNC119_IN_SEL_CFG - GPIO input function configuration register - 0x330 + M1_EXCEPTION_INFO1 + M1 exception_info1 register + 0xE4 0x20 - 0x0000003C - IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + M1_EXCEPTION_ADDR + Exception addr 0 - 6 - read-write + 32 + read-only + + + + M2_STATUS + M2 status register + 0xE8 + 0x20 + - IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write + M2_EXCEPTION_STATUS + Exception status + 0 + 2 + read-only + + + + M2_STATUS_CLR + M2 status clear register + 0xEC + 0x20 + - SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + M2_REGION_STATUS_CLR + Clear exception status + 0 1 - read-write + write-only - FUNC120_IN_SEL_CFG - GPIO input function configuration register - 0x334 + M2_EXCEPTION_INFO0 + M2 exception_info0 register + 0xF0 0x20 - 0x0000003C - IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + M2_EXCEPTION_REGION + Exception region 0 - 6 - read-write + 16 + read-only - IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write + M2_EXCEPTION_MODE + Exception mode + 16 + 2 + read-only - SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + M2_EXCEPTION_ID + Exception id information + 18 + 5 + read-only - FUNC121_IN_SEL_CFG - GPIO input function configuration register - 0x338 + M2_EXCEPTION_INFO1 + M2 exception_info1 register + 0xF4 0x20 - 0x0000003C - IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + M2_EXCEPTION_ADDR + Exception addr 0 - 6 - read-write + 32 + read-only + + + + M3_STATUS + M3 status register + 0xF8 + 0x20 + - IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write + M3_EXCEPTION_STATUS + Exception status + 0 + 2 + read-only + + + + M3_STATUS_CLR + M3 status clear register + 0xFC + 0x20 + - SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 + M3_REGION_STATUS_CLR + Clear exception status + 0 1 - read-write + write-only - FUNC122_IN_SEL_CFG - GPIO input function configuration register - 0x33C + M3_EXCEPTION_INFO0 + M3 exception_info0 register + 0x100 0x20 - 0x0000003C - IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + M3_EXCEPTION_REGION + Exception region 0 - 6 - read-write + 16 + read-only - IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write + M3_EXCEPTION_MODE + Exception mode + 16 + 2 + read-only - SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + M3_EXCEPTION_ID + Exception id information + 18 + 5 + read-only - FUNC123_IN_SEL_CFG - GPIO input function configuration register - 0x340 + M3_EXCEPTION_INFO1 + M3 exception_info1 register + 0x104 0x20 - 0x0000003C - IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + M3_EXCEPTION_ADDR + Exception addr 0 - 6 - read-write - - - IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - read-write + 32 + read-only - FUNC124_IN_SEL_CFG - GPIO input function configuration register - 0x344 + INT_EN + APM interrupt enable register + 0x108 0x20 - 0x0000003C - IN_SEL - set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + M0_APM_INT_EN + APM M0 interrupt enable 0 - 6 - read-write - - - IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - read-write - - - SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 1 read-write - - - - 32 - 0x4 - FUNC%s_OUT_SEL_CFG - GPIO output function select register - 0x554 - 0x20 - 0x00000080 - - OUT_SEL - The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals GPIO_OUT_REG[n]. - 0 - 8 - read-write - - - INV_SEL - set this bit to invert output signal.1:invert.0:not invert. - 8 + M1_APM_INT_EN + APM M1 interrupt enable + 1 1 read-write - OEN_SEL - set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output enable signal.0:use peripheral output enable signal. - 9 + M2_APM_INT_EN + APM M2 interrupt enable + 2 1 read-write - OEN_INV_SEL - set this bit to invert output enable signal.1:invert.0:not invert. - 10 + M3_APM_INT_EN + APM M3 interrupt enable + 3 1 read-write @@ -9817,14 +9587,14 @@ CLOCK_GATE - GPIO clock gate register - 0x62C + clock gating register + 0x10C 0x20 0x00000001 CLK_EN - set this bit to enable GPIO clock gate + reg_clk_en 0 1 read-write @@ -9833,14 +9603,14 @@ DATE - GPIO version register - 0x6FC + Version register + 0x7FC 0x20 - 0x02201120 + 0x02205240 DATE - version register + reg_date 0 28 read-write @@ -9850,284 +9620,377 @@ - HMAC - HMAC (Hash-based Message Authentication Code) Accelerator - HMAC - 0x6003E000 + HP_SYS + Peripheral HP_SYS + HP_SYS + 0x60095000 0x0 - 0xA4 + 0x44 registers - SET_START - Process control register 0. - 0x40 + EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL + EXTERNAL DEVICE ENCRYPTION/DECRYPTION configuration register + 0x0 0x20 - SET_START - Start hmac operation. + ENABLE_SPI_MANUAL_ENCRYPT + Set this bit as 1 to enable mspi xts manual encrypt in spi boot mode. 0 1 - write-only + read-write + + + ENABLE_DOWNLOAD_DB_ENCRYPT + reserved + 1 + 1 + read-only + + + ENABLE_DOWNLOAD_G0CB_DECRYPT + Set this bit as 1 to enable mspi xts auto decrypt in download boot mode. + 2 + 1 + read-write + + + ENABLE_DOWNLOAD_MANUAL_ENCRYPT + Set this bit as 1 to enable mspi xts manual encrypt in download boot mode. + 3 + 1 + read-write - SET_PARA_PURPOSE - Configure purpose. - 0x44 + SRAM_USAGE_CONF + HP memory usage configuration register + 0x4 0x20 - PURPOSE_SET - Set hmac parameter purpose. - 0 - 4 - write-only + SRAM_USAGE + 0: cpu use hp-memory. 1: mac-dump accessing hp-memory. + 10 + 5 + read-write + + + MAC_DUMP_ALLOC + reserved. + 20 + 5 + read-write + + + CACHE_USAGE + reserved + 31 + 1 + read-only - SET_PARA_KEY - Configure key. - 0x48 + SEC_DPA_CONF + HP anti-DPA security configuration register + 0x8 0x20 - KEY_SET - Set hmac parameter key. + SEC_DPA_LEVEL + 0: anti-DPA disable. 1~3: anti-DPA enable with different security level. The larger the number, the stronger the ability to resist DPA attacks and the higher the security level, but it will increase the computational overhead of the hardware crypto-accelerators. Only avaliable if HP_SYS_SEC_DPA_CFG_SEL is 0. 0 - 3 - write-only + 2 + read-write + + + SEC_DPA_CFG_SEL + This field is used to select either HP_SYS_SEC_DPA_LEVEL or EFUSE_SEC_DPA_LEVEL (from efuse) to control dpa_level. 0: EFUSE_SEC_DPA_LEVEL, 1: HP_SYS_SEC_DPA_LEVEL. + 2 + 1 + read-write - SET_PARA_FINISH - Finish initial configuration. - 0x4C + CPU_PERI_TIMEOUT_CONF + CPU_PERI_TIMEOUT configuration register + 0xC 0x20 + 0x0002FFFF - SET_PARA_END - Finish hmac configuration. + CPU_PERI_TIMEOUT_THRES + Set the timeout threshold for bus access, corresponding to the number of clock cycles of the clock domain. 0 + 16 + read-write + + + CPU_PERI_TIMEOUT_INT_CLEAR + Set this bit as 1 to clear timeout interrupt + 16 1 write-only + + CPU_PERI_TIMEOUT_PROTECT_EN + Set this bit as 1 to enable timeout protection for accessing cpu peripheral registers + 17 + 1 + read-write + - SET_MESSAGE_ONE - Process control register 1. - 0x50 + CPU_PERI_TIMEOUT_ADDR + CPU_PERI_TIMEOUT_ADDR register + 0x10 0x20 - SET_TEXT_ONE - Call SHA to calculate one message block. + CPU_PERI_TIMEOUT_ADDR + Record the address information of abnormal access 0 - 1 - write-only + 32 + read-only - SET_MESSAGE_ING - Process control register 2. - 0x54 + CPU_PERI_TIMEOUT_UID + CPU_PERI_TIMEOUT_UID register + 0x14 0x20 - SET_TEXT_ING - Continue typical hmac. + CPU_PERI_TIMEOUT_UID + Record master id[4:0] & master permission[6:5] when trigger timeout. This register will be cleared after the interrupt is cleared. 0 - 1 - write-only + 7 + read-only - SET_MESSAGE_END - Process control register 3. - 0x58 + HP_PERI_TIMEOUT_CONF + HP_PERI_TIMEOUT configuration register + 0x18 0x20 + 0x0002FFFF - SET_TEXT_END - Start hardware padding. + HP_PERI_TIMEOUT_THRES + Set the timeout threshold for bus access, corresponding to the number of clock cycles of the clock domain. 0 + 16 + read-write + + + HP_PERI_TIMEOUT_INT_CLEAR + Set this bit as 1 to clear timeout interrupt + 16 1 write-only + + HP_PERI_TIMEOUT_PROTECT_EN + Set this bit as 1 to enable timeout protection for accessing hp peripheral registers + 17 + 1 + read-write + - SET_RESULT_FINISH - Process control register 4. - 0x5C + HP_PERI_TIMEOUT_ADDR + HP_PERI_TIMEOUT_ADDR register + 0x1C 0x20 - SET_RESULT_END - After read result from upstream, then let hmac back to idle. + HP_PERI_TIMEOUT_ADDR + Record the address information of abnormal access 0 - 1 - write-only + 32 + read-only - SET_INVALIDATE_JTAG - Invalidate register 0. - 0x60 + HP_PERI_TIMEOUT_UID + HP_PERI_TIMEOUT_UID register + 0x20 0x20 - SET_INVALIDATE_JTAG - Clear result from hmac downstream JTAG. + HP_PERI_TIMEOUT_UID + Record master id[4:0] & master permission[6:5] when trigger timeout. This register will be cleared after the interrupt is cleared. 0 - 1 - write-only + 7 + read-only - SET_INVALIDATE_DS - Invalidate register 1. - 0x64 + ROM_TABLE_LOCK + Rom-Table lock register + 0x24 0x20 - SET_INVALIDATE_DS - Clear result from hmac downstream DS. + ROM_TABLE_LOCK + XXXX 0 1 - write-only + read-write - QUERY_ERROR - Error register. - 0x68 + ROM_TABLE + Rom-Table register + 0x28 0x20 - QUREY_CHECK - Hmac configuration state. 0: key are agree with purpose. 1: error + ROM_TABLE + XXXX 0 - 1 - read-only + 32 + read-write - QUERY_BUSY - Busy register. - 0x6C + MEM_TEST_CONF + MEM_TEST configuration register + 0x2C 0x20 + 0x00002228 - BUSY_STATE - Hmac state. 1'b0: idle. 1'b1: busy + HP_MEM_WPULSE + This field controls hp system memory WPULSE parameter. 0b000 for 1.1V/1.0V/0.9V operating Voltage. 0 - 1 - read-only + 3 + read-write + + + HP_MEM_WA + This field controls hp system memory WA parameter. 0b100 for 1.1V operating Voltage, 0b101 for 1.0V, 0b110 for 0.9V. + 3 + 3 + read-write + + + HP_MEM_RA + This field controls hp system memory RA parameter. 0b00 for 1.1V/1.0V operating Voltage, 0b01 for 0.9V. + 6 + 2 + read-write + + + HP_MEM_RM + This field controls hp system memory RM parameter. 0b0011 for 1.1V operating Voltage, 0b0010 for 1.0V, 0b0000 for 0.9V. + 8 + 4 + read-write + + + ROM_RM + This field controls rom RM parameter. 0b0011 for 1.1V operating Voltage, 0b0010 for 1.0V, 0b0010(default) or 0b0001(slow) for 0.9V. + 12 + 4 + read-write - 64 - 0x1 - WR_MESSAGE_MEM[%s] - Message block memory. - 0x80 - 0x8 - - - 32 - 0x1 - RD_RESULT_MEM[%s] - Result from upstream. - 0xC0 - 0x8 - - - SET_MESSAGE_PAD - Process control register 5. - 0xF0 + RND_ECO + redcy eco register. + 0x3E0 0x20 - SET_TEXT_PAD - Start software padding. + REDCY_ENA + Only reserved for ECO. 0 1 - write-only + read-write + + + REDCY_RESULT + Only reserved for ECO. + 1 + 1 + read-only - ONE_BLOCK - Process control register 6. - 0xF4 + RND_ECO_LOW + redcy eco low register. + 0x3E4 0x20 - SET_ONE_BLOCK - Don't have to do padding. + REDCY_LOW + Only reserved for ECO. 0 - 1 - write-only + 32 + read-write - SOFT_JTAG_CTRL - Jtag register 0. - 0xF8 + RND_ECO_HIGH + redcy eco high register. + 0x3E8 0x20 + 0xFFFFFFFF - SOFT_JTAG_CTRL - Turn on JTAG verification. + REDCY_HIGH + Only reserved for ECO. 0 - 1 - write-only + 32 + read-write - WR_JTAG - Jtag register 1. - 0xFC + CLOCK_GATE + HP-SYSTEM clock gating configure register + 0x3F8 0x20 - WR_JTAG - 32-bit of key to be compared. + CLK_EN + Set this bit as 1 to force on clock gating. 0 - 32 - write-only + 1 + read-write DATE Date register. - 0x1FC + 0x3FC 0x20 - 0x20200618 + 0x02209271 DATE - Hmac date information/ hmac version information. + HP-SYSTEM date information/ HP-SYSTEM version information. 0 - 30 + 28 read-write @@ -10138,7 +10001,7 @@ I2C0 I2C (Inter-Integrated Circuit) Controller I2C - 0x60013000 + 0x60004000 0x0 0x90 @@ -11495,11 +11358,16 @@ level. + + I2C1 + I2C (Inter-Integrated Circuit) Controller + 0x60005000 + I2S0 I2S (Inter-IC Sound) Controller I2S - 0x6002D000 + 0x6000D000 0x0 0x60 @@ -12793,764 +12661,1258 @@ level. - IO_MUX - Input/Output Multiplexer - IO_MUX - 0x60009000 + INTERRUPT_CORE0 + Peripheral INTERRUPT_CORE0 + INTMTX_CORE0 + 0x60010000 0x0 - 0x7C + 0x118 registers + + WIFI_MAC + 0 + + + WIFI_NMI + 1 + + + WIFI_PWR + 2 + + + WIFI_BB + 3 + + + BT_MAC + 4 + + + BT_BB + 5 + + + BT_BB_NMI + 6 + + + RWBT + 7 + + + RWBLE + 8 + + + RWBT_NMI + 9 + + + RWBLE_NMI + 10 + - PIN_CTRL - Clock Output Configuration Register + PMU_INTR_MAP + register description 0x0 0x20 - 0x00001DEF - CLK_OUT1 - If you want to output clock for I2S to CLK_OUT_out1, set this register to 0x0. CLK_OUT_out1 can be found in peripheral output signals. + PMU_INTR_MAP + CORE0_PMU_INTR mapping register 0 5 read-write + + + + EFUSE_INTR_MAP + register description + 0x4 + 0x20 + - CLK_OUT2 - If you want to output clock for I2S to CLK_OUT_out2, set this register to 0x0. CLK_OUT_out2 can be found in peripheral output signals. - 5 + EFUSE_INTR_MAP + CORE0_EFUSE_INTR mapping register + 0 5 read-write + + + + LP_RTC_TIMER_INTR_MAP + register description + 0x8 + 0x20 + - CLK_OUT3 - If you want to output clock for I2S to CLK_OUT_out3, set this register to 0x0. CLK_OUT_out3 can be found in peripheral output signals. - 10 + LP_RTC_TIMER_INTR_MAP + CORE0_LP_RTC_TIMER_INTR mapping register + 0 5 read-write - 28 - 0x4 - GPIO%s - IO MUX Configure Register for pad GPIO0 - 0x4 + LP_BLE_TIMER_INTR_MAP + register description + 0xC 0x20 - 0x00000800 - MCU_OE - Output enable of the pad in sleep mode. 1: output enabled. 0: output disabled. + LP_BLE_TIMER_INTR_MAP + CORE0_LP_BLE_TIMER_INTR mapping register 0 - 1 + 5 read-write + + + + LP_WDT_INTR_MAP + register description + 0x10 + 0x20 + - SLP_SEL - Sleep mode selection of this pad. Set to 1 to put the pad in pad mode. - 1 - 1 + LP_WDT_INTR_MAP + CORE0_LP_WDT_INTR mapping register + 0 + 5 read-write + + + + LP_PERI_TIMEOUT_INTR_MAP + register description + 0x14 + 0x20 + - MCU_WPD - Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled. 0: internal pull-down disabled. - 2 - 1 + LP_PERI_TIMEOUT_INTR_MAP + CORE0_LP_PERI_TIMEOUT_INTR mapping register + 0 + 5 read-write + + + + LP_APM_M0_INTR_MAP + register description + 0x18 + 0x20 + - MCU_WPU - Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled. 0: internal pull-up disabled. - 3 - 1 + LP_APM_M0_INTR_MAP + CORE0_LP_APM_M0_INTR mapping register + 0 + 5 read-write + + + + CPU_INTR_FROM_CPU_0_MAP + register description + 0x1C + 0x20 + - MCU_IE - Input enable of the pad during sleep mode. 1: input enabled. 0: input disabled. - 4 - 1 + CPU_INTR_FROM_CPU_0_MAP + CORE0_CPU_INTR_FROM_CPU_0 mapping register + 0 + 5 read-write + + + + CPU_INTR_FROM_CPU_1_MAP + register description + 0x20 + 0x20 + - MCU_DRV - Select the drive strength of the pad during sleep mode. 0: ~5 mA. 1: ~10mA. 2: ~20mA. 3: ~40mA. - 5 - 2 + CPU_INTR_FROM_CPU_1_MAP + CORE0_CPU_INTR_FROM_CPU_1 mapping register + 0 + 5 read-write + + + + CPU_INTR_FROM_CPU_2_MAP + register description + 0x24 + 0x20 + - FUN_WPD - Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down disabled. - 7 - 1 + CPU_INTR_FROM_CPU_2_MAP + CORE0_CPU_INTR_FROM_CPU_2 mapping register + 0 + 5 read-write + + + + CPU_INTR_FROM_CPU_3_MAP + register description + 0x28 + 0x20 + - FUN_WPU - Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up disabled. - 8 - 1 + CPU_INTR_FROM_CPU_3_MAP + CORE0_CPU_INTR_FROM_CPU_3 mapping register + 0 + 5 read-write + + + + ASSIST_DEBUG_INTR_MAP + register description + 0x2C + 0x20 + - FUN_IE - Input enable of the pad. 1: input enabled. 0: input disabled. - 9 - 1 + ASSIST_DEBUG_INTR_MAP + CORE0_ASSIST_DEBUG_INTR mapping register + 0 + 5 read-write + + + + TRACE_INTR_MAP + register description + 0x30 + 0x20 + - FUN_DRV - Select the drive strength of the pad. 0: ~5 mA. 1: ~10mA. 2: ~20mA. 3: ~40mA. - 10 - 2 + TRACE_INTR_MAP + CORE0_TRACE_INTR mapping register + 0 + 5 read-write + + + + CACHE_INTR_MAP + register description + 0x34 + 0x20 + - MCU_SEL - Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2. etc. - 12 - 3 + CACHE_INTR_MAP + CORE0_CACHE_INTR mapping register + 0 + 5 read-write + + + + CPU_PERI_TIMEOUT_INTR_MAP + register description + 0x38 + 0x20 + - FILTER_EN - Enable filter for pin input signals. 1: Filter enabled. 0: Filter disabled. - 15 - 1 + CPU_PERI_TIMEOUT_INTR_MAP + CORE0_CPU_PERI_TIMEOUT_INTR mapping register + 0 + 5 read-write + + + + BT_MAC_INTR_MAP + register description + 0x3C + 0x20 + - HYS_EN - Software enables hysteresis function for the pad. 1: Hysteresis enabled. 0: Hysteresis disabled. - 16 - 1 + BT_MAC_INTR_MAP + CORE0_BT_MAC_INTR mapping register + 0 + 5 read-write + + + + BT_BB_INTR_MAP + register description + 0x40 + 0x20 + - HYS_SEL - Select enabling signals of the pad from software and efuse hardware. 1: Select enabling siganl from slftware. 0: Select enabling signal from efuse hardware. - 17 - 1 + BT_BB_INTR_MAP + CORE0_BT_BB_INTR mapping register + 0 + 5 read-write - MODEM_DIAG_EN - GPIO MATRIX Configure Register for modem diag - 0xBC + BT_BB_NMI_MAP + register description + 0x44 0x20 - MODEM_DIAG_EN - bit i to enable modem_diag[i] into gpio matrix. 1:enable modem_diag[i] into gpio matrix. 0:enable other signals into gpio matrix + BT_BB_NMI_MAP + CORE0_BT_BB_NMI mapping register 0 - 32 + 5 read-write - DATE - IO MUX Version Control Register - 0xFC + COEX_INTR_MAP + register description + 0x48 0x20 - 0x02207270 - REG_DATE - Version control register + COEX_INTR_MAP + CORE0_COEX_INTR mapping register 0 - 28 + 5 read-write - - - - LEDC - LED Control PWM (Pulse Width Modulation) - LEDC - 0x60019000 - - 0x0 - 0x154 - registers - - - LEDC - 23 - - - 6 - 0x14 - CH%s_CONF0 - Configuration register 0 for channel %s - 0x0 + BLE_TIMER_INTR_MAP + register description + 0x4C 0x20 - TIMER_SEL_CH - This field is used to select one of timers for channel %s. - -0: select timer0, 1: select timer1, 2: select timer2, 3: select timer3 + BLE_TIMER_INTR_MAP + CORE0_BLE_TIMER_INTR mapping register 0 - 2 + 5 read-write + + + + BLE_SEC_INTR_MAP + register description + 0x50 + 0x20 + - SIG_OUT_EN_CH - Set this bit to enable signal output on channel %s. - 2 - 1 + BLE_SEC_INTR_MAP + CORE0_BLE_SEC_INTR mapping register + 0 + 5 read-write + + + + ZB_MAC_INTR_MAP + register description + 0x54 + 0x20 + - IDLE_LV_CH - This bit is used to control the output value when channel %s is inactive (when LEDC_SIG_OUT_EN_CH%s is 0). - 3 - 1 + ZB_MAC_INTR_MAP + CORE0_ZB_MAC_INTR mapping register + 0 + 5 read-write + + + + GPIO_INTERRUPT_PRO_MAP + register description + 0x58 + 0x20 + - PARA_UP_CH - This bit is used to update LEDC_HPOINT_CH%s, LEDC_DUTY_START_CH%s, LEDC_SIG_OUT_EN_CH%s, LEDC_TIMER_SEL_CH%s, LEDC_DUTY_NUM_CH%s, LEDC_DUTY_CYCLE_CH%s, LEDC_DUTY_SCALE_CH%s, LEDC_DUTY_INC_CH%s, and LEDC_OVF_CNT_EN_CH%s fields for channel %s, and will be automatically cleared by hardware. - 4 - 1 - write-only + GPIO_INTERRUPT_PRO_MAP + CORE0_GPIO_INTERRUPT_PRO mapping register + 0 + 5 + read-write + + + + GPIO_INTERRUPT_PRO_NMI_MAP + register description + 0x5C + 0x20 + - OVF_NUM_CH - This register is used to configure the maximum times of overflow minus 1. - -The LEDC_OVF_CNT_CH%s_INT interrupt will be triggered when channel %s overflows for (LEDC_OVF_NUM_CH%s + 1) times. - 5 - 10 + GPIO_INTERRUPT_PRO_NMI_MAP + CORE0_GPIO_INTERRUPT_PRO_NMI mapping register + 0 + 5 read-write + + + + PAU_INTR_MAP + register description + 0x60 + 0x20 + - OVF_CNT_EN_CH - This bit is used to enable the ovf_cnt of channel %s. - 15 - 1 + PAU_INTR_MAP + CORE0_PAU_INTR mapping register + 0 + 5 read-write + + + + HP_PERI_TIMEOUT_INTR_MAP + register description + 0x64 + 0x20 + - OVF_CNT_RESET_CH - Set this bit to reset the ovf_cnt of channel %s. - 16 - 1 - write-only + HP_PERI_TIMEOUT_INTR_MAP + CORE0_HP_PERI_TIMEOUT_INTR mapping register + 0 + 5 + read-write - 6 - 0x14 - CH%s_HPOINT - High point register for channel %s - 0x4 + HP_APM_M0_INTR_MAP + register description + 0x68 0x20 - HPOINT_CH - The output value changes to high when the selected timers has reached the value specified by this register. + HP_APM_M0_INTR_MAP + CORE0_HP_APM_M0_INTR mapping register 0 - 20 + 5 read-write - 6 - 0x14 - CH%s_DUTY - Initial duty cycle for channel %s - 0x8 + HP_APM_M1_INTR_MAP + register description + 0x6C 0x20 - DUTY_CH - This register is used to change the output duty by controlling the Lpoint. - -The output value turns to low when the selected timers has reached the Lpoint. + HP_APM_M1_INTR_MAP + CORE0_HP_APM_M1_INTR mapping register 0 - 25 + 5 read-write - 6 - 0x14 - CH%s_CONF1 - Configuration register 1 for channel %s - 0xC + HP_APM_M2_INTR_MAP + register description + 0x70 0x20 - DUTY_START_CH - Other configured fields in LEDC_CH%s_CONF1_REG will start to take effect when this bit is set to 1. - 31 - 1 + HP_APM_M2_INTR_MAP + CORE0_HP_APM_M2_INTR mapping register + 0 + 5 read-write - 6 - 0x14 - CH%s_DUTY_R - Current duty cycle for channel %s - 0x10 + HP_APM_M3_INTR_MAP + register description + 0x74 0x20 - DUTY_CH_R - This register stores the current duty of output signal on channel %s. + HP_APM_M3_INTR_MAP + CORE0_HP_APM_M3_INTR mapping register 0 - 25 - read-only + 5 + read-write - 4 - 0x8 - TIMER%s_CONF - Timer %s configuration - 0xA0 + MSPI_INTR_MAP + register description + 0x78 0x20 - 0x01000000 - TIMER_DUTY_RES - This register is used to control the range of the counter in timer %s. + MSPI_INTR_MAP + CORE0_MSPI_INTR mapping register 0 5 read-write + + + + I2S1_INTR_MAP + register description + 0x7C + 0x20 + - CLK_DIV_TIMER - This register is used to configure the divisor for the divider in timer %s. - -The least significant eight bits represent the fractional part. - 5 - 18 + I2S1_INTR_MAP + CORE0_I2S1_INTR mapping register + 0 + 5 read-write + + + + UHCI0_INTR_MAP + register description + 0x80 + 0x20 + - TIMER_PAUSE - This bit is used to suspend the counter in timer %s. - 23 - 1 + UHCI0_INTR_MAP + CORE0_UHCI0_INTR mapping register + 0 + 5 read-write + + + + UART0_INTR_MAP + register description + 0x84 + 0x20 + - TIMER_RST - This bit is used to reset timer %s. The counter will show 0 after reset. - 24 - 1 + UART0_INTR_MAP + CORE0_UART0_INTR mapping register + 0 + 5 read-write + + + + UART1_INTR_MAP + register description + 0x88 + 0x20 + - TICK_SEL_TIMER - This bit is used to select clock for timer %s. When this bit is set to 1 LEDC_APB_CLK_SEL[1:0] should be 1, otherwise the timer clock may be not accurate. - -1'h0: SLOW_CLK 1'h1: REF_TICK - 25 - 1 + UART1_INTR_MAP + CORE0_UART1_INTR mapping register + 0 + 5 read-write + + + + LEDC_INTR_MAP + register description + 0x8C + 0x20 + - TIMER_PARA_UP - Set this bit to update LEDC_CLK_DIV_TIMER%s and LEDC_TIMER%s_DUTY_RES. - 26 - 1 - write-only + LEDC_INTR_MAP + CORE0_LEDC_INTR mapping register + 0 + 5 + read-write - 4 - 0x8 - TIMER%s_VALUE - Timer %s current counter value - 0xA4 + CAN0_INTR_MAP + register description + 0x90 0x20 - TIMER_CNT - This register stores the current counter value of timer %s. + CAN0_INTR_MAP + CORE0_CAN0_INTR mapping register 0 - 20 - read-only + 5 + read-write - INT_RAW - Raw interrupt status - 0xC0 + USB_INTR_MAP + register description + 0x94 0x20 - TIMER0_OVF_INT_RAW - Triggered when the timer0 has reached its maximum counter value. + USB_INTR_MAP + CORE0_USB_INTR mapping register 0 - 1 - read-only + 5 + read-write + + + + RMT_INTR_MAP + register description + 0x98 + 0x20 + - TIMER1_OVF_INT_RAW - Triggered when the timer1 has reached its maximum counter value. - 1 - 1 - read-only + RMT_INTR_MAP + CORE0_RMT_INTR mapping register + 0 + 5 + read-write + + + + I2C_EXT0_INTR_MAP + register description + 0x9C + 0x20 + - TIMER2_OVF_INT_RAW - Triggered when the timer2 has reached its maximum counter value. - 2 - 1 - read-only + I2C_EXT0_INTR_MAP + CORE0_I2C_EXT0_INTR mapping register + 0 + 5 + read-write + + + + I2C_EXT1_INTR_MAP + register description + 0xA0 + 0x20 + - TIMER3_OVF_INT_RAW - Triggered when the timer3 has reached its maximum counter value. - 3 - 1 - read-only + I2C_EXT1_INTR_MAP + CORE0_I2C_EXT1_INTR mapping register + 0 + 5 + read-write + + + + TG0_T0_INTR_MAP + register description + 0xA4 + 0x20 + - DUTY_CHNG_END_CH0_INT_RAW - Interrupt raw bit for channel 0. Triggered when the gradual change of duty has finished. - 4 - 1 - read-only + TG0_T0_INTR_MAP + CORE0_TG0_T0_INTR mapping register + 0 + 5 + read-write + + + + TG0_WDT_INTR_MAP + register description + 0xA8 + 0x20 + - DUTY_CHNG_END_CH1_INT_RAW - Interrupt raw bit for channel 1. Triggered when the gradual change of duty has finished. - 5 - 1 - read-only + TG0_WDT_INTR_MAP + CORE0_TG0_WDT_INTR mapping register + 0 + 5 + read-write + + + + TG1_T0_INTR_MAP + register description + 0xAC + 0x20 + - DUTY_CHNG_END_CH2_INT_RAW - Interrupt raw bit for channel 2. Triggered when the gradual change of duty has finished. - 6 - 1 - read-only + TG1_T0_INTR_MAP + CORE0_TG1_T0_INTR mapping register + 0 + 5 + read-write + + + + TG1_WDT_INTR_MAP + register description + 0xB0 + 0x20 + - DUTY_CHNG_END_CH3_INT_RAW - Interrupt raw bit for channel 3. Triggered when the gradual change of duty has finished. - 7 - 1 - read-only + TG1_WDT_INTR_MAP + CORE0_TG1_WDT_INTR mapping register + 0 + 5 + read-write + + + + SYSTIMER_TARGET0_INTR_MAP + register description + 0xB4 + 0x20 + - DUTY_CHNG_END_CH4_INT_RAW - Interrupt raw bit for channel 4. Triggered when the gradual change of duty has finished. - 8 - 1 - read-only + SYSTIMER_TARGET0_INTR_MAP + CORE0_SYSTIMER_TARGET0_INTR mapping register + 0 + 5 + read-write + + + + SYSTIMER_TARGET1_INTR_MAP + register description + 0xB8 + 0x20 + - DUTY_CHNG_END_CH5_INT_RAW - Interrupt raw bit for channel 5. Triggered when the gradual change of duty has finished. - 9 - 1 - read-only + SYSTIMER_TARGET1_INTR_MAP + CORE0_SYSTIMER_TARGET1_INTR mapping register + 0 + 5 + read-write + + + + SYSTIMER_TARGET2_INTR_MAP + register description + 0xBC + 0x20 + - OVF_CNT_CH0_INT_RAW - Interrupt raw bit for channel 0. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH0. - 12 - 1 - read-only + SYSTIMER_TARGET2_INTR_MAP + CORE0_SYSTIMER_TARGET2_INTR mapping register + 0 + 5 + read-write + + + + APB_ADC_INTR_MAP + register description + 0xC0 + 0x20 + - OVF_CNT_CH1_INT_RAW - Interrupt raw bit for channel 1. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH1. - 13 - 1 - read-only + APB_ADC_INTR_MAP + CORE0_APB_ADC_INTR mapping register + 0 + 5 + read-write + + + + PWM_INTR_MAP + register description + 0xC4 + 0x20 + - OVF_CNT_CH2_INT_RAW - Interrupt raw bit for channel 2. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH2. - 14 - 1 - read-only + PWM_INTR_MAP + CORE0_PWM_INTR mapping register + 0 + 5 + read-write + + + + PCNT_INTR_MAP + register description + 0xC8 + 0x20 + - OVF_CNT_CH3_INT_RAW - Interrupt raw bit for channel 3. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH3. - 15 - 1 - read-only + PCNT_INTR_MAP + CORE0_PCNT_INTR mapping register + 0 + 5 + read-write + + + + PARL_IO_TX_INTR_MAP + register description + 0xCC + 0x20 + - OVF_CNT_CH4_INT_RAW - Interrupt raw bit for channel 4. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH4. - 16 - 1 - read-only + PARL_IO_TX_INTR_MAP + CORE0_PARL_IO_TX_INTR mapping register + 0 + 5 + read-write + + + + PARL_IO_RX_INTR_MAP + register description + 0xD0 + 0x20 + - OVF_CNT_CH5_INT_RAW - Interrupt raw bit for channel 5. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH5. - 17 - 1 - read-only + PARL_IO_RX_INTR_MAP + CORE0_PARL_IO_RX_INTR mapping register + 0 + 5 + read-write - INT_ST - Masked interrupt status - 0xC4 + DMA_IN_CH0_INTR_MAP + register description + 0xD4 0x20 - TIMER0_OVF_INT_ST - This is the masked interrupt status bit for the LEDC_TIMER0_OVF_INT interrupt when LEDC_TIMER0_OVF_INT_ENA is set to 1. + DMA_IN_CH0_INTR_MAP + CORE0_DMA_IN_CH0_INTR mapping register 0 - 1 - read-only + 5 + read-write + + + + DMA_IN_CH1_INTR_MAP + register description + 0xD8 + 0x20 + - TIMER1_OVF_INT_ST - This is the masked interrupt status bit for the LEDC_TIMER1_OVF_INT interrupt when LEDC_TIMER1_OVF_INT_ENA is set to 1. - 1 - 1 - read-only + DMA_IN_CH1_INTR_MAP + CORE0_DMA_IN_CH1_INTR mapping register + 0 + 5 + read-write + + + + DMA_IN_CH2_INTR_MAP + register description + 0xDC + 0x20 + - TIMER2_OVF_INT_ST - This is the masked interrupt status bit for the LEDC_TIMER2_OVF_INT interrupt when LEDC_TIMER2_OVF_INT_ENA is set to 1. - 2 - 1 - read-only + DMA_IN_CH2_INTR_MAP + CORE0_DMA_IN_CH2_INTR mapping register + 0 + 5 + read-write + + + + DMA_OUT_CH0_INTR_MAP + register description + 0xE0 + 0x20 + - TIMER3_OVF_INT_ST - This is the masked interrupt status bit for the LEDC_TIMER3_OVF_INT interrupt when LEDC_TIMER3_OVF_INT_ENA is set to 1. - 3 - 1 - read-only + DMA_OUT_CH0_INTR_MAP + CORE0_DMA_OUT_CH0_INTR mapping register + 0 + 5 + read-write + + + + DMA_OUT_CH1_INTR_MAP + register description + 0xE4 + 0x20 + - DUTY_CHNG_END_CH0_INT_ST - This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH0_INT interrupt when LEDC_DUTY_CHNG_END_CH0_INT_ENA is set to 1. - 4 - 1 - read-only + DMA_OUT_CH1_INTR_MAP + CORE0_DMA_OUT_CH1_INTR mapping register + 0 + 5 + read-write + + + + + DMA_OUT_CH2_INTR_MAP + register description + 0xE8 + 0x20 + + + DMA_OUT_CH2_INTR_MAP + CORE0_DMA_OUT_CH2_INTR mapping register + 0 + 5 + read-write + + + + GPSPI2_INTR_MAP + register description + 0xEC + 0x20 + - DUTY_CHNG_END_CH1_INT_ST - This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH1_INT interrupt when LEDC_DUTY_CHNG_END_CH1_INT_ENA is set to 1. - 5 - 1 - read-only + GPSPI2_INTR_MAP + CORE0_GPSPI2_INTR mapping register + 0 + 5 + read-write + + + + AES_INTR_MAP + register description + 0xF0 + 0x20 + - DUTY_CHNG_END_CH2_INT_ST - This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH2_INT interrupt when LEDC_DUTY_CHNG_END_CH2_INT_ENA is set to 1. - 6 - 1 - read-only + AES_INTR_MAP + CORE0_AES_INTR mapping register + 0 + 5 + read-write + + + + SHA_INTR_MAP + register description + 0xF4 + 0x20 + - DUTY_CHNG_END_CH3_INT_ST - This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH3_INT interrupt when LEDC_DUTY_CHNG_END_CH3_INT_ENA is set to 1. - 7 - 1 - read-only + SHA_INTR_MAP + CORE0_SHA_INTR mapping register + 0 + 5 + read-write + + + + RSA_INTR_MAP + register description + 0xF8 + 0x20 + - DUTY_CHNG_END_CH4_INT_ST - This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH4_INT interrupt when LEDC_DUTY_CHNG_END_CH4_INT_ENA is set to 1. - 8 - 1 - read-only + RSA_INTR_MAP + CORE0_RSA_INTR mapping register + 0 + 5 + read-write + + + + ECC_INTR_MAP + register description + 0xFC + 0x20 + - DUTY_CHNG_END_CH5_INT_ST - This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH5_INT interrupt when LEDC_DUTY_CHNG_END_CH5_INT_ENA is set to 1. - 9 - 1 - read-only + ECC_INTR_MAP + CORE0_ECC_INTR mapping register + 0 + 5 + read-write + + + + ECDSA_INTR_MAP + register description + 0x100 + 0x20 + - OVF_CNT_CH0_INT_ST - This is the masked interrupt status bit for the LEDC_OVF_CNT_CH0_INT interrupt when LEDC_OVF_CNT_CH0_INT_ENA is set to 1. - 12 - 1 - read-only + ECDSA_INTR_MAP + CORE0_ECDSA_INTR mapping register + 0 + 5 + read-write + + + + INT_STATUS_REG_0 + register description + 0x104 + 0x20 + - OVF_CNT_CH1_INT_ST - This is the masked interrupt status bit for the LEDC_OVF_CNT_CH1_INT interrupt when LEDC_OVF_CNT_CH1_INT_ENA is set to 1. - 13 - 1 + INT_STATUS_0 + Status register for interrupt sources 0~31 mapping register + 0 + 32 read-only + + + + INT_STATUS_REG_1 + register description + 0x108 + 0x20 + - OVF_CNT_CH2_INT_ST - This is the masked interrupt status bit for the LEDC_OVF_CNT_CH2_INT interrupt when LEDC_OVF_CNT_CH2_INT_ENA is set to 1. - 14 - 1 + INT_STATUS_1 + Status register for interrupt sources 32~63 mapping register + 0 + 32 read-only + + + + INT_STATUS_REG_2 + register description + 0x10C + 0x20 + - OVF_CNT_CH3_INT_ST - This is the masked interrupt status bit for the LEDC_OVF_CNT_CH3_INT interrupt when LEDC_OVF_CNT_CH3_INT_ENA is set to 1. - 15 - 1 + INT_STATUS_2 + Status register for interrupt sources 64~95 mapping register + 0 + 32 read-only + + + + CLOCK_GATE + register description + 0x110 + 0x20 + 0x00000001 + - OVF_CNT_CH4_INT_ST - This is the masked interrupt status bit for the LEDC_OVF_CNT_CH4_INT interrupt when LEDC_OVF_CNT_CH4_INT_ENA is set to 1. - 16 + REG_CLK_EN + Clock register + 0 1 - read-only + read-write + + + + INTERRUPT_REG_DATE + register description + 0x7FC + 0x20 + 0x02209150 + - OVF_CNT_CH5_INT_ST - This is the masked interrupt status bit for the LEDC_OVF_CNT_CH5_INT interrupt when LEDC_OVF_CNT_CH5_INT_ENA is set to 1. - 17 - 1 - read-only + INTERRUPT_REG_DATE + Version control register + 0 + 28 + read-write + + + + IO_MUX + Input/Output Multiplexer + IO_MUX + 0x60090000 + + 0x0 + 0x7C + registers + + - INT_ENA - Interrupt enable bits - 0xC8 + PIN_CTRL + Clock Output Configuration Register + 0x0 0x20 + 0x00001DEF - TIMER0_OVF_INT_ENA - The interrupt enable bit for the LEDC_TIMER0_OVF_INT interrupt. + CLK_OUT1 + If you want to output clock for I2S to CLK_OUT_out1, set this register to 0x0. CLK_OUT_out1 can be found in peripheral output signals. + 0 + 5 + read-write + + + CLK_OUT2 + If you want to output clock for I2S to CLK_OUT_out2, set this register to 0x0. CLK_OUT_out2 can be found in peripheral output signals. + 5 + 5 + read-write + + + CLK_OUT3 + If you want to output clock for I2S to CLK_OUT_out3, set this register to 0x0. CLK_OUT_out3 can be found in peripheral output signals. + 10 + 5 + read-write + + + + + 28 + 0x4 + GPIO%s + IO MUX Configure Register for pad GPIO0 + 0x4 + 0x20 + 0x00000800 + + + MCU_OE + Output enable of the pad in sleep mode. 1: output enabled. 0: output disabled. 0 1 read-write - TIMER1_OVF_INT_ENA - The interrupt enable bit for the LEDC_TIMER1_OVF_INT interrupt. + SLP_SEL + Sleep mode selection of this pad. Set to 1 to put the pad in pad mode. 1 1 read-write - TIMER2_OVF_INT_ENA - The interrupt enable bit for the LEDC_TIMER2_OVF_INT interrupt. + MCU_WPD + Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled. 0: internal pull-down disabled. 2 1 read-write - TIMER3_OVF_INT_ENA - The interrupt enable bit for the LEDC_TIMER3_OVF_INT interrupt. + MCU_WPU + Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled. 0: internal pull-up disabled. 3 1 read-write - DUTY_CHNG_END_CH0_INT_ENA - The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH0_INT interrupt. + MCU_IE + Input enable of the pad during sleep mode. 1: input enabled. 0: input disabled. 4 1 read-write - DUTY_CHNG_END_CH1_INT_ENA - The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH1_INT interrupt. + MCU_DRV + Select the drive strength of the pad during sleep mode. 0: ~5 mA. 1: ~10mA. 2: ~20mA. 3: ~40mA. 5 - 1 - read-write - - - DUTY_CHNG_END_CH2_INT_ENA - The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH2_INT interrupt. - 6 - 1 + 2 read-write - DUTY_CHNG_END_CH3_INT_ENA - The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH3_INT interrupt. + FUN_WPD + Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down disabled. 7 1 read-write - DUTY_CHNG_END_CH4_INT_ENA - The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH4_INT interrupt. + FUN_WPU + Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up disabled. 8 1 read-write - DUTY_CHNG_END_CH5_INT_ENA - The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH5_INT interrupt. + FUN_IE + Input enable of the pad. 1: input enabled. 0: input disabled. 9 1 read-write - OVF_CNT_CH0_INT_ENA - The interrupt enable bit for the LEDC_OVF_CNT_CH0_INT interrupt. - 12 - 1 - read-write - - - OVF_CNT_CH1_INT_ENA - The interrupt enable bit for the LEDC_OVF_CNT_CH1_INT interrupt. - 13 - 1 + FUN_DRV + Select the drive strength of the pad. 0: ~5 mA. 1: ~10mA. 2: ~20mA. 3: ~40mA. + 10 + 2 read-write - OVF_CNT_CH2_INT_ENA - The interrupt enable bit for the LEDC_OVF_CNT_CH2_INT interrupt. - 14 - 1 + MCU_SEL + Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2. etc. + 12 + 3 read-write - OVF_CNT_CH3_INT_ENA - The interrupt enable bit for the LEDC_OVF_CNT_CH3_INT interrupt. + FILTER_EN + Enable filter for pin input signals. 1: Filter enabled. 0: Filter disabled. 15 1 read-write - OVF_CNT_CH4_INT_ENA - The interrupt enable bit for the LEDC_OVF_CNT_CH4_INT interrupt. + HYS_EN + Software enables hysteresis function for the pad. 1: Hysteresis enabled. 0: Hysteresis disabled. 16 1 read-write - OVF_CNT_CH5_INT_ENA - The interrupt enable bit for the LEDC_OVF_CNT_CH5_INT interrupt. + HYS_SEL + Select enabling signals of the pad from software and efuse hardware. 1: Select enabling siganl from slftware. 0: Select enabling signal from efuse hardware. 17 1 read-write @@ -13558,2974 +13920,22990 @@ The least significant eight bits represent the fractional part. - INT_CLR - Interrupt clear bits - 0xCC + MODEM_DIAG_EN + GPIO MATRIX Configure Register for modem diag + 0xBC 0x20 - TIMER0_OVF_INT_CLR - Set this bit to clear the LEDC_TIMER0_OVF_INT interrupt. + MODEM_DIAG_EN + bit i to enable modem_diag[i] into gpio matrix. 1:enable modem_diag[i] into gpio matrix. 0:enable other signals into gpio matrix 0 - 1 - write-only + 32 + read-write + + + + DATE + IO MUX Version Control Register + 0xFC + 0x20 + 0x02207270 + - TIMER1_OVF_INT_CLR - Set this bit to clear the LEDC_TIMER1_OVF_INT interrupt. - 1 - 1 - write-only + REG_DATE + Version control register + 0 + 28 + read-write + + + + + + + LEDC + LED Control PWM (Pulse Width Modulation) + LEDC + 0x60008000 + + 0x0 + 0x154 + registers + + + LEDC + 23 + + + TIMER1 + 30 + + + TIMER2 + 31 + + + + 6 + 0x14 + CH%s_CONF0 + Configuration register 0 for channel %s + 0x0 + 0x20 + + + TIMER_SEL_CH + This field is used to select one of timers for channel %s. + +0: select timer0, 1: select timer1, 2: select timer2, 3: select timer3 + 0 + 2 + read-write - TIMER2_OVF_INT_CLR - Set this bit to clear the LEDC_TIMER2_OVF_INT interrupt. + SIG_OUT_EN_CH + Set this bit to enable signal output on channel %s. 2 1 - write-only + read-write - TIMER3_OVF_INT_CLR - Set this bit to clear the LEDC_TIMER3_OVF_INT interrupt. + IDLE_LV_CH + This bit is used to control the output value when channel %s is inactive (when LEDC_SIG_OUT_EN_CH%s is 0). 3 1 - write-only + read-write - DUTY_CHNG_END_CH0_INT_CLR - Set this bit to clear the LEDC_DUTY_CHNG_END_CH0_INT interrupt. + PARA_UP_CH + This bit is used to update LEDC_HPOINT_CH%s, LEDC_DUTY_START_CH%s, LEDC_SIG_OUT_EN_CH%s, LEDC_TIMER_SEL_CH%s, LEDC_DUTY_NUM_CH%s, LEDC_DUTY_CYCLE_CH%s, LEDC_DUTY_SCALE_CH%s, LEDC_DUTY_INC_CH%s, and LEDC_OVF_CNT_EN_CH%s fields for channel %s, and will be automatically cleared by hardware. 4 1 write-only - DUTY_CHNG_END_CH1_INT_CLR - Set this bit to clear the LEDC_DUTY_CHNG_END_CH1_INT interrupt. + OVF_NUM_CH + This register is used to configure the maximum times of overflow minus 1. + +The LEDC_OVF_CNT_CH%s_INT interrupt will be triggered when channel %s overflows for (LEDC_OVF_NUM_CH%s + 1) times. 5 - 1 - write-only - - - DUTY_CHNG_END_CH2_INT_CLR - Set this bit to clear the LEDC_DUTY_CHNG_END_CH2_INT interrupt. - 6 - 1 - write-only - - - DUTY_CHNG_END_CH3_INT_CLR - Set this bit to clear the LEDC_DUTY_CHNG_END_CH3_INT interrupt. - 7 - 1 - write-only - - - DUTY_CHNG_END_CH4_INT_CLR - Set this bit to clear the LEDC_DUTY_CHNG_END_CH4_INT interrupt. - 8 - 1 - write-only - - - DUTY_CHNG_END_CH5_INT_CLR - Set this bit to clear the LEDC_DUTY_CHNG_END_CH5_INT interrupt. - 9 - 1 - write-only - - - OVF_CNT_CH0_INT_CLR - Set this bit to clear the LEDC_OVF_CNT_CH0_INT interrupt. - 12 - 1 - write-only - - - OVF_CNT_CH1_INT_CLR - Set this bit to clear the LEDC_OVF_CNT_CH1_INT interrupt. - 13 - 1 - write-only - - - OVF_CNT_CH2_INT_CLR - Set this bit to clear the LEDC_OVF_CNT_CH2_INT interrupt. - 14 - 1 - write-only + 10 + read-write - OVF_CNT_CH3_INT_CLR - Set this bit to clear the LEDC_OVF_CNT_CH3_INT interrupt. + OVF_CNT_EN_CH + This bit is used to enable the ovf_cnt of channel %s. 15 1 - write-only + read-write - OVF_CNT_CH4_INT_CLR - Set this bit to clear the LEDC_OVF_CNT_CH4_INT interrupt. + OVF_CNT_RESET_CH + Set this bit to reset the ovf_cnt of channel %s. 16 1 write-only - - OVF_CNT_CH5_INT_CLR - Set this bit to clear the LEDC_OVF_CNT_CH5_INT interrupt. - 17 - 1 - write-only - 6 - 0x10 - CH%s_GAMMA_WR - Ledc ch%s gamma ram write register. - 0x100 + 0x14 + CH%s_HPOINT + High point register for channel %s + 0x4 0x20 - CH_GAMMA_DUTY_INC - Ledc ch%s gamma duty inc of current ram write address.This register is used to increase or decrease the duty of output signal on channel %s. - -1: Increase 0: Decrease. + HPOINT_CH + The output value changes to high when the selected timers has reached the value specified by this register. 0 - 1 - read-write - - - CH_GAMMA_DUTY_CYCLE - Ledc ch%s gamma duty cycle of current ram write address.The duty will change every LEDC_CH%s_GAMMA_DUTY_CYCLE on channel %s. - 1 - 10 - read-write - - - CH_GAMMA_SCALE - Ledc ch%s gamma scale of current ram write address.This register is used to configure the changing step scale of duty on channel %s. - 11 - 10 - read-write - - - CH_GAMMA_DUTY_NUM - Ledc ch%s gamma duty num of current ram write address.This register is used to control the number of times the duty cycle will be changed. - 21 - 10 + 20 read-write 6 - 0x10 - CH%s_GAMMA_WR_ADDR - Ledc ch%s gamma ram write address register. - 0x104 + 0x14 + CH%s_DUTY + Initial duty cycle for channel %s + 0x8 0x20 - CH_GAMMA_WR_ADDR - Ledc ch%s gamma ram write address. + DUTY_CH + This register is used to change the output duty by controlling the Lpoint. + +The output value turns to low when the selected timers has reached the Lpoint. 0 - 4 + 25 read-write 6 - 0x10 - CH%s_GAMMA_RD_ADDR - Ledc ch%s gamma ram read address register. - 0x108 + 0x14 + CH%s_CONF1 + Configuration register 1 for channel %s + 0xC 0x20 - CH_GAMMA_RD_ADDR - Ledc ch%s gamma ram read address. - 0 - 4 + DUTY_START_CH + Other configured fields in LEDC_CH%s_CONF1_REG will start to take effect when this bit is set to 1. + 31 + 1 read-write 6 - 0x10 - CH%s_GAMMA_RD_DATA - Ledc ch%s gamma ram read data register. - 0x10C + 0x14 + CH%s_DUTY_R + Current duty cycle for channel %s + 0x10 0x20 - CH_GAMMA_RD_DATA - Ledc ch%s gamma ram read data. + DUTY_CH_R + This register stores the current duty of output signal on channel %s. 0 - 31 + 25 read-only - 6 - 0x4 - CH%s_GAMMA_CONF - Ledc ch%s gamma config register. - 0x180 + 4 + 0x8 + TIMER%s_CONF + Timer %s configuration + 0xA0 0x20 + 0x01000000 - CH_GAMMA_ENTRY_NUM - Ledc ch%s gamma entry num. + TIMER_DUTY_RES + This register is used to control the range of the counter in timer %s. 0 5 read-write - CH_GAMMA_PAUSE - Ledc ch%s gamma pause, write 1 to pause. + CLK_DIV_TIMER + This register is used to configure the divisor for the divider in timer %s. + +The least significant eight bits represent the fractional part. 5 + 18 + read-write + + + TIMER_PAUSE + This bit is used to suspend the counter in timer %s. + 23 1 - write-only + read-write - CH_GAMMA_RESUME - Ledc ch%s gamma resume, write 1 to resume. - 6 + TIMER_RST + This bit is used to reset timer %s. The counter will show 0 after reset. + 24 + 1 + read-write + + + TICK_SEL_TIMER + This bit is used to select clock for timer %s. When this bit is set to 1 LEDC_APB_CLK_SEL[1:0] should be 1, otherwise the timer clock may be not accurate. + +1'h0: SLOW_CLK 1'h1: REF_TICK + 25 + 1 + read-write + + + TIMER_PARA_UP + Set this bit to update LEDC_CLK_DIV_TIMER%s and LEDC_TIMER%s_DUTY_RES. + 26 1 write-only - EVT_TASK_EN0 - Ledc event task enable bit register0. - 0x1A0 + 4 + 0x8 + TIMER%s_VALUE + Timer %s current counter value + 0xA4 0x20 - EVT_DUTY_CHNG_END_CH0_EN - Ledc ch0 duty change end event enable register, write 1 to enable this event. + TIMER_CNT + This register stores the current counter value of timer %s. + 0 + 20 + read-only + + + + + INT_RAW + Raw interrupt status + 0xC0 + 0x20 + + + TIMER0_OVF_INT_RAW + Triggered when the timer0 has reached its maximum counter value. 0 1 - read-write + read-only - EVT_DUTY_CHNG_END_CH1_EN - Ledc ch1 duty change end event enable register, write 1 to enable this event. + TIMER1_OVF_INT_RAW + Triggered when the timer1 has reached its maximum counter value. 1 1 - read-write + read-only - EVT_DUTY_CHNG_END_CH2_EN - Ledc ch2 duty change end event enable register, write 1 to enable this event. + TIMER2_OVF_INT_RAW + Triggered when the timer2 has reached its maximum counter value. 2 1 - read-write + read-only - EVT_DUTY_CHNG_END_CH3_EN - Ledc ch3 duty change end event enable register, write 1 to enable this event. + TIMER3_OVF_INT_RAW + Triggered when the timer3 has reached its maximum counter value. 3 1 - read-write + read-only - EVT_DUTY_CHNG_END_CH4_EN - Ledc ch4 duty change end event enable register, write 1 to enable this event. + DUTY_CHNG_END_CH0_INT_RAW + Interrupt raw bit for channel 0. Triggered when the gradual change of duty has finished. 4 1 - read-write + read-only - EVT_DUTY_CHNG_END_CH5_EN - Ledc ch5 duty change end event enable register, write 1 to enable this event. + DUTY_CHNG_END_CH1_INT_RAW + Interrupt raw bit for channel 1. Triggered when the gradual change of duty has finished. 5 1 - read-write + read-only - EVT_OVF_CNT_PLS_CH0_EN - Ledc ch0 overflow count pulse event enable register, write 1 to enable this event. - 8 + DUTY_CHNG_END_CH2_INT_RAW + Interrupt raw bit for channel 2. Triggered when the gradual change of duty has finished. + 6 1 - read-write + read-only - EVT_OVF_CNT_PLS_CH1_EN - Ledc ch1 overflow count pulse event enable register, write 1 to enable this event. - 9 + DUTY_CHNG_END_CH3_INT_RAW + Interrupt raw bit for channel 3. Triggered when the gradual change of duty has finished. + 7 1 - read-write + read-only - EVT_OVF_CNT_PLS_CH2_EN - Ledc ch2 overflow count pulse event enable register, write 1 to enable this event. - 10 + DUTY_CHNG_END_CH4_INT_RAW + Interrupt raw bit for channel 4. Triggered when the gradual change of duty has finished. + 8 1 - read-write + read-only - EVT_OVF_CNT_PLS_CH3_EN - Ledc ch3 overflow count pulse event enable register, write 1 to enable this event. - 11 + DUTY_CHNG_END_CH5_INT_RAW + Interrupt raw bit for channel 5. Triggered when the gradual change of duty has finished. + 9 1 - read-write + read-only - EVT_OVF_CNT_PLS_CH4_EN - Ledc ch4 overflow count pulse event enable register, write 1 to enable this event. + OVF_CNT_CH0_INT_RAW + Interrupt raw bit for channel 0. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH0. 12 1 - read-write + read-only - EVT_OVF_CNT_PLS_CH5_EN - Ledc ch5 overflow count pulse event enable register, write 1 to enable this event. + OVF_CNT_CH1_INT_RAW + Interrupt raw bit for channel 1. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH1. 13 1 - read-write + read-only - EVT_TIME_OVF_TIMER0_EN - Ledc timer0 overflow event enable register, write 1 to enable this event. - 16 + OVF_CNT_CH2_INT_RAW + Interrupt raw bit for channel 2. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH2. + 14 1 - read-write + read-only - EVT_TIME_OVF_TIMER1_EN - Ledc timer1 overflow event enable register, write 1 to enable this event. - 17 + OVF_CNT_CH3_INT_RAW + Interrupt raw bit for channel 3. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH3. + 15 1 - read-write + read-only - EVT_TIME_OVF_TIMER2_EN - Ledc timer2 overflow event enable register, write 1 to enable this event. - 18 + OVF_CNT_CH4_INT_RAW + Interrupt raw bit for channel 4. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH4. + 16 1 - read-write + read-only - EVT_TIME_OVF_TIMER3_EN - Ledc timer3 overflow event enable register, write 1 to enable this event. - 19 + OVF_CNT_CH5_INT_RAW + Interrupt raw bit for channel 5. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH5. + 17 1 - read-write + read-only + + + + INT_ST + Masked interrupt status + 0xC4 + 0x20 + - EVT_TIME0_CMP_EN - Ledc timer0 compare event enable register, write 1 to enable this event. - 20 + TIMER0_OVF_INT_ST + This is the masked interrupt status bit for the LEDC_TIMER0_OVF_INT interrupt when LEDC_TIMER0_OVF_INT_ENA is set to 1. + 0 1 - read-write + read-only - EVT_TIME1_CMP_EN - Ledc timer1 compare event enable register, write 1 to enable this event. - 21 + TIMER1_OVF_INT_ST + This is the masked interrupt status bit for the LEDC_TIMER1_OVF_INT interrupt when LEDC_TIMER1_OVF_INT_ENA is set to 1. + 1 1 - read-write + read-only - EVT_TIME2_CMP_EN - Ledc timer2 compare event enable register, write 1 to enable this event. - 22 + TIMER2_OVF_INT_ST + This is the masked interrupt status bit for the LEDC_TIMER2_OVF_INT interrupt when LEDC_TIMER2_OVF_INT_ENA is set to 1. + 2 1 - read-write + read-only - EVT_TIME3_CMP_EN - Ledc timer3 compare event enable register, write 1 to enable this event. - 23 + TIMER3_OVF_INT_ST + This is the masked interrupt status bit for the LEDC_TIMER3_OVF_INT interrupt when LEDC_TIMER3_OVF_INT_ENA is set to 1. + 3 1 - read-write + read-only - TASK_DUTY_SCALE_UPDATE_CH0_EN - Ledc ch0 duty scale update task enable register, write 1 to enable this task. - 24 + DUTY_CHNG_END_CH0_INT_ST + This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH0_INT interrupt when LEDC_DUTY_CHNG_END_CH0_INT_ENA is set to 1. + 4 1 - read-write + read-only - TASK_DUTY_SCALE_UPDATE_CH1_EN - Ledc ch1 duty scale update task enable register, write 1 to enable this task. - 25 + DUTY_CHNG_END_CH1_INT_ST + This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH1_INT interrupt when LEDC_DUTY_CHNG_END_CH1_INT_ENA is set to 1. + 5 1 - read-write + read-only - TASK_DUTY_SCALE_UPDATE_CH2_EN - Ledc ch2 duty scale update task enable register, write 1 to enable this task. - 26 + DUTY_CHNG_END_CH2_INT_ST + This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH2_INT interrupt when LEDC_DUTY_CHNG_END_CH2_INT_ENA is set to 1. + 6 1 - read-write + read-only - TASK_DUTY_SCALE_UPDATE_CH3_EN - Ledc ch3 duty scale update task enable register, write 1 to enable this task. - 27 + DUTY_CHNG_END_CH3_INT_ST + This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH3_INT interrupt when LEDC_DUTY_CHNG_END_CH3_INT_ENA is set to 1. + 7 1 - read-write + read-only - TASK_DUTY_SCALE_UPDATE_CH4_EN - Ledc ch4 duty scale update task enable register, write 1 to enable this task. - 28 + DUTY_CHNG_END_CH4_INT_ST + This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH4_INT interrupt when LEDC_DUTY_CHNG_END_CH4_INT_ENA is set to 1. + 8 1 - read-write + read-only - TASK_DUTY_SCALE_UPDATE_CH5_EN - Ledc ch5 duty scale update task enable register, write 1 to enable this task. - 29 + DUTY_CHNG_END_CH5_INT_ST + This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH5_INT interrupt when LEDC_DUTY_CHNG_END_CH5_INT_ENA is set to 1. + 9 1 - read-write + read-only + + + OVF_CNT_CH0_INT_ST + This is the masked interrupt status bit for the LEDC_OVF_CNT_CH0_INT interrupt when LEDC_OVF_CNT_CH0_INT_ENA is set to 1. + 12 + 1 + read-only + + + OVF_CNT_CH1_INT_ST + This is the masked interrupt status bit for the LEDC_OVF_CNT_CH1_INT interrupt when LEDC_OVF_CNT_CH1_INT_ENA is set to 1. + 13 + 1 + read-only + + + OVF_CNT_CH2_INT_ST + This is the masked interrupt status bit for the LEDC_OVF_CNT_CH2_INT interrupt when LEDC_OVF_CNT_CH2_INT_ENA is set to 1. + 14 + 1 + read-only + + + OVF_CNT_CH3_INT_ST + This is the masked interrupt status bit for the LEDC_OVF_CNT_CH3_INT interrupt when LEDC_OVF_CNT_CH3_INT_ENA is set to 1. + 15 + 1 + read-only + + + OVF_CNT_CH4_INT_ST + This is the masked interrupt status bit for the LEDC_OVF_CNT_CH4_INT interrupt when LEDC_OVF_CNT_CH4_INT_ENA is set to 1. + 16 + 1 + read-only + + + OVF_CNT_CH5_INT_ST + This is the masked interrupt status bit for the LEDC_OVF_CNT_CH5_INT interrupt when LEDC_OVF_CNT_CH5_INT_ENA is set to 1. + 17 + 1 + read-only - EVT_TASK_EN1 - Ledc event task enable bit register1. - 0x1A4 + INT_ENA + Interrupt enable bits + 0xC8 0x20 - TASK_TIMER0_RES_UPDATE_EN - Ledc timer0 res update task enable register, write 1 to enable this task. + TIMER0_OVF_INT_ENA + The interrupt enable bit for the LEDC_TIMER0_OVF_INT interrupt. 0 1 read-write - TASK_TIMER1_RES_UPDATE_EN - Ledc timer1 res update task enable register, write 1 to enable this task. + TIMER1_OVF_INT_ENA + The interrupt enable bit for the LEDC_TIMER1_OVF_INT interrupt. 1 1 read-write - TASK_TIMER2_RES_UPDATE_EN - Ledc timer2 res update task enable register, write 1 to enable this task. + TIMER2_OVF_INT_ENA + The interrupt enable bit for the LEDC_TIMER2_OVF_INT interrupt. 2 1 read-write - TASK_TIMER3_RES_UPDATE_EN - Ledc timer3 res update task enable register, write 1 to enable this task. + TIMER3_OVF_INT_ENA + The interrupt enable bit for the LEDC_TIMER3_OVF_INT interrupt. 3 1 read-write - TASK_TIMER0_CAP_EN - Ledc timer0 capture task enable register, write 1 to enable this task. + DUTY_CHNG_END_CH0_INT_ENA + The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH0_INT interrupt. 4 1 read-write - TASK_TIMER1_CAP_EN - Ledc timer1 capture task enable register, write 1 to enable this task. + DUTY_CHNG_END_CH1_INT_ENA + The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH1_INT interrupt. 5 1 read-write - TASK_TIMER2_CAP_EN - Ledc timer2 capture task enable register, write 1 to enable this task. + DUTY_CHNG_END_CH2_INT_ENA + The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH2_INT interrupt. 6 1 read-write - TASK_TIMER3_CAP_EN - Ledc timer3 capture task enable register, write 1 to enable this task. + DUTY_CHNG_END_CH3_INT_ENA + The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH3_INT interrupt. 7 1 read-write - TASK_SIG_OUT_DIS_CH0_EN - Ledc ch0 signal out disable task enable register, write 1 to enable this task. + DUTY_CHNG_END_CH4_INT_ENA + The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH4_INT interrupt. 8 1 read-write - TASK_SIG_OUT_DIS_CH1_EN - Ledc ch1 signal out disable task enable register, write 1 to enable this task. + DUTY_CHNG_END_CH5_INT_ENA + The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH5_INT interrupt. 9 1 read-write - TASK_SIG_OUT_DIS_CH2_EN - Ledc ch2 signal out disable task enable register, write 1 to enable this task. - 10 + OVF_CNT_CH0_INT_ENA + The interrupt enable bit for the LEDC_OVF_CNT_CH0_INT interrupt. + 12 1 read-write - TASK_SIG_OUT_DIS_CH3_EN - Ledc ch3 signal out disable task enable register, write 1 to enable this task. - 11 + OVF_CNT_CH1_INT_ENA + The interrupt enable bit for the LEDC_OVF_CNT_CH1_INT interrupt. + 13 1 read-write - TASK_SIG_OUT_DIS_CH4_EN - Ledc ch4 signal out disable task enable register, write 1 to enable this task. - 12 + OVF_CNT_CH2_INT_ENA + The interrupt enable bit for the LEDC_OVF_CNT_CH2_INT interrupt. + 14 1 read-write - TASK_SIG_OUT_DIS_CH5_EN - Ledc ch5 signal out disable task enable register, write 1 to enable this task. - 13 + OVF_CNT_CH3_INT_ENA + The interrupt enable bit for the LEDC_OVF_CNT_CH3_INT interrupt. + 15 1 read-write - TASK_OVF_CNT_RST_CH0_EN - Ledc ch0 overflow count reset task enable register, write 1 to enable this task. + OVF_CNT_CH4_INT_ENA + The interrupt enable bit for the LEDC_OVF_CNT_CH4_INT interrupt. 16 1 read-write - TASK_OVF_CNT_RST_CH1_EN - Ledc ch1 overflow count reset task enable register, write 1 to enable this task. + OVF_CNT_CH5_INT_ENA + The interrupt enable bit for the LEDC_OVF_CNT_CH5_INT interrupt. 17 1 read-write + + + + INT_CLR + Interrupt clear bits + 0xCC + 0x20 + - TASK_OVF_CNT_RST_CH2_EN - Ledc ch2 overflow count reset task enable register, write 1 to enable this task. - 18 + TIMER0_OVF_INT_CLR + Set this bit to clear the LEDC_TIMER0_OVF_INT interrupt. + 0 + 1 + write-only + + + TIMER1_OVF_INT_CLR + Set this bit to clear the LEDC_TIMER1_OVF_INT interrupt. + 1 + 1 + write-only + + + TIMER2_OVF_INT_CLR + Set this bit to clear the LEDC_TIMER2_OVF_INT interrupt. + 2 + 1 + write-only + + + TIMER3_OVF_INT_CLR + Set this bit to clear the LEDC_TIMER3_OVF_INT interrupt. + 3 + 1 + write-only + + + DUTY_CHNG_END_CH0_INT_CLR + Set this bit to clear the LEDC_DUTY_CHNG_END_CH0_INT interrupt. + 4 + 1 + write-only + + + DUTY_CHNG_END_CH1_INT_CLR + Set this bit to clear the LEDC_DUTY_CHNG_END_CH1_INT interrupt. + 5 + 1 + write-only + + + DUTY_CHNG_END_CH2_INT_CLR + Set this bit to clear the LEDC_DUTY_CHNG_END_CH2_INT interrupt. + 6 + 1 + write-only + + + DUTY_CHNG_END_CH3_INT_CLR + Set this bit to clear the LEDC_DUTY_CHNG_END_CH3_INT interrupt. + 7 + 1 + write-only + + + DUTY_CHNG_END_CH4_INT_CLR + Set this bit to clear the LEDC_DUTY_CHNG_END_CH4_INT interrupt. + 8 + 1 + write-only + + + DUTY_CHNG_END_CH5_INT_CLR + Set this bit to clear the LEDC_DUTY_CHNG_END_CH5_INT interrupt. + 9 + 1 + write-only + + + OVF_CNT_CH0_INT_CLR + Set this bit to clear the LEDC_OVF_CNT_CH0_INT interrupt. + 12 + 1 + write-only + + + OVF_CNT_CH1_INT_CLR + Set this bit to clear the LEDC_OVF_CNT_CH1_INT interrupt. + 13 + 1 + write-only + + + OVF_CNT_CH2_INT_CLR + Set this bit to clear the LEDC_OVF_CNT_CH2_INT interrupt. + 14 + 1 + write-only + + + OVF_CNT_CH3_INT_CLR + Set this bit to clear the LEDC_OVF_CNT_CH3_INT interrupt. + 15 + 1 + write-only + + + OVF_CNT_CH4_INT_CLR + Set this bit to clear the LEDC_OVF_CNT_CH4_INT interrupt. + 16 + 1 + write-only + + + OVF_CNT_CH5_INT_CLR + Set this bit to clear the LEDC_OVF_CNT_CH5_INT interrupt. + 17 + 1 + write-only + + + + + 6 + 0x10 + CH%s_GAMMA_WR + Ledc ch%s gamma ram write register. + 0x100 + 0x20 + + + CH_GAMMA_DUTY_INC + Ledc ch%s gamma duty inc of current ram write address.This register is used to increase or decrease the duty of output signal on channel %s. + +1: Increase 0: Decrease. + 0 1 read-write - TASK_OVF_CNT_RST_CH3_EN - Ledc ch3 overflow count reset task enable register, write 1 to enable this task. - 19 + CH_GAMMA_DUTY_CYCLE + Ledc ch%s gamma duty cycle of current ram write address.The duty will change every LEDC_CH%s_GAMMA_DUTY_CYCLE on channel %s. + 1 + 10 + read-write + + + CH_GAMMA_SCALE + Ledc ch%s gamma scale of current ram write address.This register is used to configure the changing step scale of duty on channel %s. + 11 + 10 + read-write + + + CH_GAMMA_DUTY_NUM + Ledc ch%s gamma duty num of current ram write address.This register is used to control the number of times the duty cycle will be changed. + 21 + 10 + read-write + + + + + 6 + 0x10 + CH%s_GAMMA_WR_ADDR + Ledc ch%s gamma ram write address register. + 0x104 + 0x20 + + + CH_GAMMA_WR_ADDR + Ledc ch%s gamma ram write address. + 0 + 4 + read-write + + + + + 6 + 0x10 + CH%s_GAMMA_RD_ADDR + Ledc ch%s gamma ram read address register. + 0x108 + 0x20 + + + CH_GAMMA_RD_ADDR + Ledc ch%s gamma ram read address. + 0 + 4 + read-write + + + + + 6 + 0x10 + CH%s_GAMMA_RD_DATA + Ledc ch%s gamma ram read data register. + 0x10C + 0x20 + + + CH_GAMMA_RD_DATA + Ledc ch%s gamma ram read data. + 0 + 31 + read-only + + + + + 6 + 0x4 + CH%s_GAMMA_CONF + Ledc ch%s gamma config register. + 0x180 + 0x20 + + + CH_GAMMA_ENTRY_NUM + Ledc ch%s gamma entry num. + 0 + 5 + read-write + + + CH_GAMMA_PAUSE + Ledc ch%s gamma pause, write 1 to pause. + 5 + 1 + write-only + + + CH_GAMMA_RESUME + Ledc ch%s gamma resume, write 1 to resume. + 6 + 1 + write-only + + + + + EVT_TASK_EN0 + Ledc event task enable bit register0. + 0x1A0 + 0x20 + + + EVT_DUTY_CHNG_END_CH0_EN + Ledc ch0 duty change end event enable register, write 1 to enable this event. + 0 1 read-write - TASK_OVF_CNT_RST_CH4_EN - Ledc ch4 overflow count reset task enable register, write 1 to enable this task. - 20 + EVT_DUTY_CHNG_END_CH1_EN + Ledc ch1 duty change end event enable register, write 1 to enable this event. + 1 1 read-write - TASK_OVF_CNT_RST_CH5_EN - Ledc ch5 overflow count reset task enable register, write 1 to enable this task. - 21 + EVT_DUTY_CHNG_END_CH2_EN + Ledc ch2 duty change end event enable register, write 1 to enable this event. + 2 1 read-write - TASK_TIMER0_RST_EN - Ledc timer0 reset task enable register, write 1 to enable this task. - 24 + EVT_DUTY_CHNG_END_CH3_EN + Ledc ch3 duty change end event enable register, write 1 to enable this event. + 3 1 read-write - TASK_TIMER1_RST_EN - Ledc timer1 reset task enable register, write 1 to enable this task. - 25 + EVT_DUTY_CHNG_END_CH4_EN + Ledc ch4 duty change end event enable register, write 1 to enable this event. + 4 1 read-write - TASK_TIMER2_RST_EN - Ledc timer2 reset task enable register, write 1 to enable this task. - 26 + EVT_DUTY_CHNG_END_CH5_EN + Ledc ch5 duty change end event enable register, write 1 to enable this event. + 5 1 read-write - TASK_TIMER3_RST_EN - Ledc timer3 reset task enable register, write 1 to enable this task. - 27 + EVT_OVF_CNT_PLS_CH0_EN + Ledc ch0 overflow count pulse event enable register, write 1 to enable this event. + 8 1 read-write - TASK_TIMER0_PAUSE_RESUME_EN - Ledc timer0 pause resume task enable register, write 1 to enable this task. - 28 + EVT_OVF_CNT_PLS_CH1_EN + Ledc ch1 overflow count pulse event enable register, write 1 to enable this event. + 9 1 read-write - TASK_TIMER1_PAUSE_RESUME_EN - Ledc timer1 pause resume task enable register, write 1 to enable this task. - 29 + EVT_OVF_CNT_PLS_CH2_EN + Ledc ch2 overflow count pulse event enable register, write 1 to enable this event. + 10 1 read-write - TASK_TIMER2_PAUSE_RESUME_EN - Ledc timer2 pause resume task enable register, write 1 to enable this task. - 30 + EVT_OVF_CNT_PLS_CH3_EN + Ledc ch3 overflow count pulse event enable register, write 1 to enable this event. + 11 1 read-write - TASK_TIMER3_PAUSE_RESUME_EN - Ledc timer3 pause resume task enable register, write 1 to enable this task. - 31 + EVT_OVF_CNT_PLS_CH4_EN + Ledc ch4 overflow count pulse event enable register, write 1 to enable this event. + 12 1 read-write - - + + EVT_OVF_CNT_PLS_CH5_EN + Ledc ch5 overflow count pulse event enable register, write 1 to enable this event. + 13 + 1 + read-write + + + EVT_TIME_OVF_TIMER0_EN + Ledc timer0 overflow event enable register, write 1 to enable this event. + 16 + 1 + read-write + + + EVT_TIME_OVF_TIMER1_EN + Ledc timer1 overflow event enable register, write 1 to enable this event. + 17 + 1 + read-write + + + EVT_TIME_OVF_TIMER2_EN + Ledc timer2 overflow event enable register, write 1 to enable this event. + 18 + 1 + read-write + + + EVT_TIME_OVF_TIMER3_EN + Ledc timer3 overflow event enable register, write 1 to enable this event. + 19 + 1 + read-write + + + EVT_TIME0_CMP_EN + Ledc timer0 compare event enable register, write 1 to enable this event. + 20 + 1 + read-write + + + EVT_TIME1_CMP_EN + Ledc timer1 compare event enable register, write 1 to enable this event. + 21 + 1 + read-write + + + EVT_TIME2_CMP_EN + Ledc timer2 compare event enable register, write 1 to enable this event. + 22 + 1 + read-write + + + EVT_TIME3_CMP_EN + Ledc timer3 compare event enable register, write 1 to enable this event. + 23 + 1 + read-write + + + TASK_DUTY_SCALE_UPDATE_CH0_EN + Ledc ch0 duty scale update task enable register, write 1 to enable this task. + 24 + 1 + read-write + + + TASK_DUTY_SCALE_UPDATE_CH1_EN + Ledc ch1 duty scale update task enable register, write 1 to enable this task. + 25 + 1 + read-write + + + TASK_DUTY_SCALE_UPDATE_CH2_EN + Ledc ch2 duty scale update task enable register, write 1 to enable this task. + 26 + 1 + read-write + + + TASK_DUTY_SCALE_UPDATE_CH3_EN + Ledc ch3 duty scale update task enable register, write 1 to enable this task. + 27 + 1 + read-write + + + TASK_DUTY_SCALE_UPDATE_CH4_EN + Ledc ch4 duty scale update task enable register, write 1 to enable this task. + 28 + 1 + read-write + + + TASK_DUTY_SCALE_UPDATE_CH5_EN + Ledc ch5 duty scale update task enable register, write 1 to enable this task. + 29 + 1 + read-write + + + + + EVT_TASK_EN1 + Ledc event task enable bit register1. + 0x1A4 + 0x20 + + + TASK_TIMER0_RES_UPDATE_EN + Ledc timer0 res update task enable register, write 1 to enable this task. + 0 + 1 + read-write + + + TASK_TIMER1_RES_UPDATE_EN + Ledc timer1 res update task enable register, write 1 to enable this task. + 1 + 1 + read-write + + + TASK_TIMER2_RES_UPDATE_EN + Ledc timer2 res update task enable register, write 1 to enable this task. + 2 + 1 + read-write + + + TASK_TIMER3_RES_UPDATE_EN + Ledc timer3 res update task enable register, write 1 to enable this task. + 3 + 1 + read-write + + + TASK_TIMER0_CAP_EN + Ledc timer0 capture task enable register, write 1 to enable this task. + 4 + 1 + read-write + + + TASK_TIMER1_CAP_EN + Ledc timer1 capture task enable register, write 1 to enable this task. + 5 + 1 + read-write + + + TASK_TIMER2_CAP_EN + Ledc timer2 capture task enable register, write 1 to enable this task. + 6 + 1 + read-write + + + TASK_TIMER3_CAP_EN + Ledc timer3 capture task enable register, write 1 to enable this task. + 7 + 1 + read-write + + + TASK_SIG_OUT_DIS_CH0_EN + Ledc ch0 signal out disable task enable register, write 1 to enable this task. + 8 + 1 + read-write + + + TASK_SIG_OUT_DIS_CH1_EN + Ledc ch1 signal out disable task enable register, write 1 to enable this task. + 9 + 1 + read-write + + + TASK_SIG_OUT_DIS_CH2_EN + Ledc ch2 signal out disable task enable register, write 1 to enable this task. + 10 + 1 + read-write + + + TASK_SIG_OUT_DIS_CH3_EN + Ledc ch3 signal out disable task enable register, write 1 to enable this task. + 11 + 1 + read-write + + + TASK_SIG_OUT_DIS_CH4_EN + Ledc ch4 signal out disable task enable register, write 1 to enable this task. + 12 + 1 + read-write + + + TASK_SIG_OUT_DIS_CH5_EN + Ledc ch5 signal out disable task enable register, write 1 to enable this task. + 13 + 1 + read-write + + + TASK_OVF_CNT_RST_CH0_EN + Ledc ch0 overflow count reset task enable register, write 1 to enable this task. + 16 + 1 + read-write + + + TASK_OVF_CNT_RST_CH1_EN + Ledc ch1 overflow count reset task enable register, write 1 to enable this task. + 17 + 1 + read-write + + + TASK_OVF_CNT_RST_CH2_EN + Ledc ch2 overflow count reset task enable register, write 1 to enable this task. + 18 + 1 + read-write + + + TASK_OVF_CNT_RST_CH3_EN + Ledc ch3 overflow count reset task enable register, write 1 to enable this task. + 19 + 1 + read-write + + + TASK_OVF_CNT_RST_CH4_EN + Ledc ch4 overflow count reset task enable register, write 1 to enable this task. + 20 + 1 + read-write + + + TASK_OVF_CNT_RST_CH5_EN + Ledc ch5 overflow count reset task enable register, write 1 to enable this task. + 21 + 1 + read-write + + + TASK_TIMER0_RST_EN + Ledc timer0 reset task enable register, write 1 to enable this task. + 24 + 1 + read-write + + + TASK_TIMER1_RST_EN + Ledc timer1 reset task enable register, write 1 to enable this task. + 25 + 1 + read-write + + + TASK_TIMER2_RST_EN + Ledc timer2 reset task enable register, write 1 to enable this task. + 26 + 1 + read-write + + + TASK_TIMER3_RST_EN + Ledc timer3 reset task enable register, write 1 to enable this task. + 27 + 1 + read-write + + + TASK_TIMER0_PAUSE_RESUME_EN + Ledc timer0 pause resume task enable register, write 1 to enable this task. + 28 + 1 + read-write + + + TASK_TIMER1_PAUSE_RESUME_EN + Ledc timer1 pause resume task enable register, write 1 to enable this task. + 29 + 1 + read-write + + + TASK_TIMER2_PAUSE_RESUME_EN + Ledc timer2 pause resume task enable register, write 1 to enable this task. + 30 + 1 + read-write + + + TASK_TIMER3_PAUSE_RESUME_EN + Ledc timer3 pause resume task enable register, write 1 to enable this task. + 31 + 1 + read-write + + + + + EVT_TASK_EN2 + Ledc event task enable bit register2. + 0x1A8 + 0x20 + + + TASK_GAMMA_RESTART_CH0_EN + Ledc ch0 gamma restart task enable register, write 1 to enable this task. + 0 + 1 + read-write + + + TASK_GAMMA_RESTART_CH1_EN + Ledc ch1 gamma restart task enable register, write 1 to enable this task. + 1 + 1 + read-write + + + TASK_GAMMA_RESTART_CH2_EN + Ledc ch2 gamma restart task enable register, write 1 to enable this task. + 2 + 1 + read-write + + + TASK_GAMMA_RESTART_CH3_EN + Ledc ch3 gamma restart task enable register, write 1 to enable this task. + 3 + 1 + read-write + + + TASK_GAMMA_RESTART_CH4_EN + Ledc ch4 gamma restart task enable register, write 1 to enable this task. + 4 + 1 + read-write + + + TASK_GAMMA_RESTART_CH5_EN + Ledc ch5 gamma restart task enable register, write 1 to enable this task. + 5 + 1 + read-write + + + TASK_GAMMA_PAUSE_CH0_EN + Ledc ch0 gamma pause task enable register, write 1 to enable this task. + 8 + 1 + read-write + + + TASK_GAMMA_PAUSE_CH1_EN + Ledc ch1 gamma pause task enable register, write 1 to enable this task. + 9 + 1 + read-write + + + TASK_GAMMA_PAUSE_CH2_EN + Ledc ch2 gamma pause task enable register, write 1 to enable this task. + 10 + 1 + read-write + + + TASK_GAMMA_PAUSE_CH3_EN + Ledc ch3 gamma pause task enable register, write 1 to enable this task. + 11 + 1 + read-write + + + TASK_GAMMA_PAUSE_CH4_EN + Ledc ch4 gamma pause task enable register, write 1 to enable this task. + 12 + 1 + read-write + + + TASK_GAMMA_PAUSE_CH5_EN + Ledc ch5 gamma pause task enable register, write 1 to enable this task. + 13 + 1 + read-write + + + TASK_GAMMA_RESUME_CH0_EN + Ledc ch0 gamma resume task enable register, write 1 to enable this task. + 16 + 1 + read-write + + + TASK_GAMMA_RESUME_CH1_EN + Ledc ch1 gamma resume task enable register, write 1 to enable this task. + 17 + 1 + read-write + + + TASK_GAMMA_RESUME_CH2_EN + Ledc ch2 gamma resume task enable register, write 1 to enable this task. + 18 + 1 + read-write + + + TASK_GAMMA_RESUME_CH3_EN + Ledc ch3 gamma resume task enable register, write 1 to enable this task. + 19 + 1 + read-write + + + TASK_GAMMA_RESUME_CH4_EN + Ledc ch4 gamma resume task enable register, write 1 to enable this task. + 20 + 1 + read-write + + + TASK_GAMMA_RESUME_CH5_EN + Ledc ch5 gamma resume task enable register, write 1 to enable this task. + 21 + 1 + read-write + + + + + 4 + 0x4 + TIMER%s_CMP + Ledc timer%s compare value register. + 0x1B0 + 0x20 + + + TIMER_CMP + This register stores ledc timer%s compare value. + 0 + 20 + read-write + + + + + 4 + 0x4 + TIMER%s_CNT_CAP + Ledc timer%s count value capture register. + 0x1C0 + 0x20 + + + TIMER_CNT_CAP + This register stores ledc timer%s count value. + 0 + 20 + read-only + + + + + CONF + Global ledc configuration register + 0x1F0 + 0x20 + + + APB_CLK_SEL + This bit is used to select clock source for the 4 timers . + +2'd1: APB_CLK 2'd2: RTC8M_CLK 2'd3: XTAL_CLK + 0 + 2 + read-write + + + GAMMA_RAM_CLK_EN_CH0 + This bit is used to control clock. + +1'b1: Force clock on for gamma ram. 1'h0: Support clock only when application writes or read gamma ram. + 2 + 1 + read-write + + + GAMMA_RAM_CLK_EN_CH1 + This bit is used to control clock. + +1'b1: Force clock on for gamma ram. 1'h0: Support clock only when application writes or read gamma ram. + 3 + 1 + read-write + + + GAMMA_RAM_CLK_EN_CH2 + This bit is used to control clock. + +1'b1: Force clock on for gamma ram. 1'h0: Support clock only when application writes or read gamma ram. + 4 + 1 + read-write + + + GAMMA_RAM_CLK_EN_CH3 + This bit is used to control clock. + +1'b1: Force clock on for gamma ram. 1'h0: Support clock only when application writes or read gamma ram. + 5 + 1 + read-write + + + GAMMA_RAM_CLK_EN_CH4 + This bit is used to control clock. + +1'b1: Force clock on for gamma ram. 1'h0: Support clock only when application writes or read gamma ram. + 6 + 1 + read-write + + + GAMMA_RAM_CLK_EN_CH5 + This bit is used to control clock. + +1'b1: Force clock on for gamma ram. 1'h0: Support clock only when application writes or read gamma ram. + 7 + 1 + read-write + + + CLK_EN + This bit is used to control clock. + +1'b1: Force clock on for register. 1'h0: Support clock only when application writes registers. + 31 + 1 + read-write + + + + + DATE + Version control register + 0x1FC + 0x20 + 0x02111150 + + + LEDC_DATE + This is the version control register. + 0 + 28 + read-write + + + + + + + LP_PERI + Peripheral LP_PERI + LPPERI + 0x600B2800 + + 0x0 + 0x30 + registers + + + + CLK_EN + need_des + 0x0 + 0x20 + 0x7F000000 + + + RNG_CK_EN + need_des + 24 + 1 + read-write + + + OTP_DBG_CK_EN + need_des + 25 + 1 + read-write + + + LP_UART_CK_EN + need_des + 26 + 1 + read-write + + + LP_IO_CK_EN + need_des + 27 + 1 + read-write + + + LP_EXT_I2C_CK_EN + need_des + 28 + 1 + read-write + + + LP_ANA_I2C_CK_EN + need_des + 29 + 1 + read-write + + + EFUSE_CK_EN + need_des + 30 + 1 + read-write + + + LP_CPU_CK_EN + need_des + 31 + 1 + read-write + + + + + RESET_EN + need_des + 0x4 + 0x20 + + + BUS_RESET_EN + need_des + 23 + 1 + write-only + + + LP_BLE_TIMER_RESET_EN + need_des + 24 + 1 + read-write + + + OTP_DBG_RESET_EN + need_des + 25 + 1 + read-write + + + LP_UART_RESET_EN + need_des + 26 + 1 + read-write + + + LP_IO_RESET_EN + need_des + 27 + 1 + read-write + + + LP_EXT_I2C_RESET_EN + need_des + 28 + 1 + read-write + + + LP_ANA_I2C_RESET_EN + need_des + 29 + 1 + read-write + + + EFUSE_RESET_EN + need_des + 30 + 1 + read-write + + + LP_CPU_RESET_EN + need_des + 31 + 1 + write-only + + + + + RNG_DATA + need_des + 0x8 + 0x20 + + + RND_DATA + need_des + 0 + 32 + read-only + + + + + CPU + need_des + 0xC + 0x20 + 0x80000000 + + + LPCORE_DBGM_UNAVALIABLE + need_des + 31 + 1 + read-write + + + + + BUS_TIMEOUT + need_des + 0x10 + 0x20 + 0xBFFFC000 + + + LP_PERI_TIMEOUT_THRES + need_des + 14 + 16 + read-write + + + LP_PERI_TIMEOUT_INT_CLEAR + need_des + 30 + 1 + write-only + + + LP_PERI_TIMEOUT_PROTECT_EN + need_des + 31 + 1 + read-write + + + + + BUS_TIMEOUT_ADDR + need_des + 0x14 + 0x20 + + + LP_PERI_TIMEOUT_ADDR + need_des + 0 + 32 + read-only + + + + + BUS_TIMEOUT_UID + need_des + 0x18 + 0x20 + + + LP_PERI_TIMEOUT_UID + need_des + 0 + 7 + read-only + + + + + MEM_CTRL + need_des + 0x1C + 0x20 + 0x80000000 + + + UART_WAKEUP_FLAG_CLR + need_des + 0 + 1 + write-only + + + UART_WAKEUP_FLAG + need_des + 1 + 1 + read-only + + + UART_WAKEUP_EN + need_des + 29 + 1 + read-write + + + UART_MEM_FORCE_PD + need_des + 30 + 1 + read-write + + + UART_MEM_FORCE_PU + need_des + 31 + 1 + read-write + + + + + INTERRUPT_SOURCE + need_des + 0x20 + 0x20 + + + LP_INTERRUPT_SOURCE + BIT5~BIT0: pmu_lp_int, modem_lp_int, lp_timer_lp_int, lp_uart_int, lp_i2c_int, lp_io_int + 0 + 6 + read-only + + + + + DEBUG_SEL0 + need des + 0x24 + 0x20 + + + DEBUG_SEL0 + need des + 0 + 7 + read-write + + + DEBUG_SEL1 + need des + 7 + 7 + read-write + + + DEBUG_SEL2 + need des + 14 + 7 + read-write + + + DEBUG_SEL3 + need des + 21 + 7 + read-write + + + + + DEBUG_SEL1 + need des + 0x28 + 0x20 + + + DEBUG_SEL4 + need des + 0 + 7 + read-write + + + + + DATE + need_des + 0x3FC + 0x20 + 0x02206130 + + + LPPERI_DATE + need_des + 0 + 31 + read-write + + + CLK_EN + need_des + 31 + 1 + read-write + + + + + + + LP_ANA + Peripheral LP_ANA + LP_ANA + 0x600B2C00 + + 0x0 + 0x44 + registers + + + + BOD_MODE0_CNTL + need_des + 0x0 + 0x20 + 0x0FFC0100 + + + BOD_MODE0_CLOSE_FLASH_ENA + need_des + 6 + 1 + read-write + + + BOD_MODE0_PD_RF_ENA + need_des + 7 + 1 + read-write + + + BOD_MODE0_INTR_WAIT + need_des + 8 + 10 + read-write + + + BOD_MODE0_RESET_WAIT + need_des + 18 + 10 + read-write + + + BOD_MODE0_CNT_CLR + need_des + 28 + 1 + read-write + + + BOD_MODE0_INTR_ENA + need_des + 29 + 1 + read-write + + + BOD_MODE0_RESET_SEL + need_des + 30 + 1 + read-write + + + BOD_MODE0_RESET_ENA + need_des + 31 + 1 + read-write + + + + + BOD_MODE1_CNTL + need_des + 0x4 + 0x20 + + + BOD_MODE1_RESET_ENA + need_des + 31 + 1 + read-write + + + + + VDD_SOURCE_CNTL + need_des + 0x8 + 0x20 + 0x040000FF + + + DETMODE_SEL + need_des + 0 + 8 + read-write + + + VGOOD_EVENT_RECORD + need_des + 8 + 8 + read-only + + + VBAT_EVENT_RECORD_CLR + need_des + 16 + 8 + write-only + + + BOD_SOURCE_ENA + need_des + 24 + 8 + read-write + + + + + VDDBAT_BOD_CNTL + need_des + 0xC + 0x20 + 0xFFC00000 + + + VDDBAT_UNDERVOLTAGE_FLAG + need_des + 0 + 1 + read-only + + + VDDBAT_CHARGER + need_des + 10 + 1 + read-write + + + VDDBAT_CNT_CLR + need_des + 11 + 1 + read-write + + + VDDBAT_UPVOLTAGE_TARGET + need_des + 12 + 10 + read-write + + + VDDBAT_UNDERVOLTAGE_TARGET + need_des + 22 + 10 + read-write + + + + + VDDBAT_CHARGE_CNTL + need_des + 0x10 + 0x20 + 0xFFC00000 + + + VDDBAT_CHARGE_UNDERVOLTAGE_FLAG + need_des + 0 + 1 + read-only + + + VDDBAT_CHARGE_CHARGER + need_des + 10 + 1 + read-write + + + VDDBAT_CHARGE_CNT_CLR + need_des + 11 + 1 + read-write + + + VDDBAT_CHARGE_UPVOLTAGE_TARGET + need_des + 12 + 10 + read-write + + + VDDBAT_CHARGE_UNDERVOLTAGE_TARGET + need_des + 22 + 10 + read-write + + + + + CK_GLITCH_CNTL + need_des + 0x14 + 0x20 + + + CK_GLITCH_RESET_ENA + need_des + 31 + 1 + read-write + + + + + PG_GLITCH_CNTL + need_des + 0x18 + 0x20 + + + POWER_GLITCH_RESET_ENA + need_des + 31 + 1 + read-write + + + + + FIB_ENABLE + need_des + 0x1C + 0x20 + 0xFFFFFFFF + + + ANA_FIB_ENA + need_des + 0 + 32 + read-write + + + + + INT_RAW + need_des + 0x20 + 0x20 + + + VDDBAT_CHARGE_UPVOLTAGE_INT_RAW + need_des + 27 + 1 + read-only + + + VDDBAT_CHARGE_UNDERVOLTAGE_INT_RAW + need_des + 28 + 1 + read-only + + + VDDBAT_UPVOLTAGE_INT_RAW + need_des + 29 + 1 + read-only + + + VDDBAT_UNDERVOLTAGE_INT_RAW + need_des + 30 + 1 + read-only + + + BOD_MODE0_INT_RAW + need_des + 31 + 1 + read-only + + + + + INT_ST + need_des + 0x24 + 0x20 + + + VDDBAT_CHARGE_UPVOLTAGE_INT_ST + need_des + 27 + 1 + read-only + + + VDDBAT_CHARGE_UNDERVOLTAGE_INT_ST + need_des + 28 + 1 + read-only + + + VDDBAT_UPVOLTAGE_INT_ST + need_des + 29 + 1 + read-only + + + VDDBAT_UNDERVOLTAGE_INT_ST + need_des + 30 + 1 + read-only + + + BOD_MODE0_INT_ST + need_des + 31 + 1 + read-only + + + + + INT_ENA + need_des + 0x28 + 0x20 + + + VDDBAT_CHARGE_UPVOLTAGE_INT_ENA + need_des + 27 + 1 + read-write + + + VDDBAT_CHARGE_UNDERVOLTAGE_INT_ENA + need_des + 28 + 1 + read-write + + + VDDBAT_UPVOLTAGE_INT_ENA + need_des + 29 + 1 + read-write + + + VDDBAT_UNDERVOLTAGE_INT_ENA + need_des + 30 + 1 + read-write + + + BOD_MODE0_INT_ENA + need_des + 31 + 1 + read-write + + + + + INT_CLR + need_des + 0x2C + 0x20 + + + VDDBAT_CHARGE_UPVOLTAGE_INT_CLR + need_des + 27 + 1 + write-only + + + VDDBAT_CHARGE_UNDERVOLTAGE_INT_CLR + need_des + 28 + 1 + write-only + + + VDDBAT_UPVOLTAGE_INT_CLR + need_des + 29 + 1 + write-only + + + VDDBAT_UNDERVOLTAGE_INT_CLR + need_des + 30 + 1 + write-only + + + BOD_MODE0_INT_CLR + need_des + 31 + 1 + write-only + + + + + LP_INT_RAW + need_des + 0x30 + 0x20 + + + BOD_MODE0_LP_INT_RAW + need_des + 31 + 1 + read-only + + + + + LP_INT_ST + need_des + 0x34 + 0x20 + + + BOD_MODE0_LP_INT_ST + need_des + 31 + 1 + read-only + + + + + LP_INT_ENA + need_des + 0x38 + 0x20 + + + BOD_MODE0_LP_INT_ENA + need_des + 31 + 1 + read-write + + + + + LP_INT_CLR + need_des + 0x3C + 0x20 + + + BOD_MODE0_LP_INT_CLR + need_des + 31 + 1 + write-only + + + + + DATE + need_des + 0x3FC + 0x20 + 0x02208250 + + + LP_ANA_DATE + need_des + 0 + 31 + read-write + + + CLK_EN + need_des + 31 + 1 + read-write + + + + + + + LP_AON + Peripheral LP_AON + LP_AON + 0x600B1000 + + 0x0 + 0x60 + registers + + + + STORE0 + need_des + 0x0 + 0x20 + + + LP_AON_STORE0 + need_des + 0 + 32 + read-write + + + + + STORE1 + need_des + 0x4 + 0x20 + + + LP_AON_STORE1 + need_des + 0 + 32 + read-write + + + + + STORE2 + need_des + 0x8 + 0x20 + + + LP_AON_STORE2 + need_des + 0 + 32 + read-write + + + + + STORE3 + need_des + 0xC + 0x20 + + + LP_AON_STORE3 + need_des + 0 + 32 + read-write + + + + + STORE4 + need_des + 0x10 + 0x20 + + + LP_AON_STORE4 + need_des + 0 + 32 + read-write + + + + + STORE5 + need_des + 0x14 + 0x20 + + + LP_AON_STORE5 + need_des + 0 + 32 + read-write + + + + + STORE6 + need_des + 0x18 + 0x20 + + + LP_AON_STORE6 + need_des + 0 + 32 + read-write + + + + + STORE7 + need_des + 0x1C + 0x20 + + + LP_AON_STORE7 + need_des + 0 + 32 + read-write + + + + + STORE8 + need_des + 0x20 + 0x20 + + + LP_AON_STORE8 + need_des + 0 + 32 + read-write + + + + + STORE9 + need_des + 0x24 + 0x20 + + + LP_AON_STORE9 + need_des + 0 + 32 + read-write + + + + + GPIO_MUX + need_des + 0x28 + 0x20 + + + SEL + need_des + 0 + 8 + read-write + + + + + GPIO_HOLD0 + need_des + 0x2C + 0x20 + + + GPIO_HOLD0 + need_des + 0 + 32 + read-write + + + + + GPIO_HOLD1 + need_des + 0x30 + 0x20 + + + GPIO_HOLD1 + need_des + 0 + 32 + read-write + + + + + SYS_CFG + need_des + 0x34 + 0x20 + 0x00000007 + + + ANA_FIB_SWD_ENABLE + need_des + 0 + 1 + read-only + + + ANA_FIB_CK_GLITCH_ENABLE + need_des + 1 + 1 + read-only + + + ANA_FIB_BOD_ENABLE + need_des + 2 + 1 + read-only + + + FORCE_DOWNLOAD_BOOT + need_des + 30 + 1 + read-write + + + HPSYS_SW_RESET + need_des + 31 + 1 + write-only + + + + + CPUCORE0_CFG + need_des + 0x38 + 0x20 + 0x40000000 + + + CPU_CORE0_SW_STALL + need_des + 0 + 8 + read-write + + + CPU_CORE0_SW_RESET + need_des + 28 + 1 + write-only + + + CPU_CORE0_OCD_HALT_ON_RESET + need_des + 29 + 1 + read-write + + + CPU_CORE0_STAT_VECTOR_SEL + need_des + 30 + 1 + read-write + + + CPU_CORE0_DRESET_MASK + need_des + 31 + 1 + read-write + + + + + IO_MUX + need_des + 0x3C + 0x20 + + + PULL_LDO + need_des + 28 + 3 + read-write + + + RESET_DISABLE + need_des + 31 + 1 + read-write + + + + + EXT_WAKEUP_CNTL + need_des + 0x40 + 0x20 + + + EXT_WAKEUP_STATUS + need_des + 0 + 8 + read-only + + + EXT_WAKEUP_STATUS_CLR + need_des + 14 + 1 + write-only + + + EXT_WAKEUP_SEL + need_des + 15 + 8 + read-write + + + EXT_WAKEUP_LV + need_des + 23 + 8 + read-write + + + EXT_WAKEUP_FILTER + need_des + 31 + 1 + read-write + + + + + USB + need_des + 0x44 + 0x20 + + + RESET_DISABLE + need_des + 31 + 1 + read-write + + + + + LPBUS + need_des + 0x48 + 0x20 + 0x02280000 + + + FAST_MEM_WPULSE + This field controls fast memory WPULSE parameter. 0b000 for 1.1V/1.0V/0.9V operating Voltage. + 16 + 3 + read-write + + + FAST_MEM_WA + This field controls fast memory WA parameter. 0b100 for 1.1V operating Voltage, 0b101 for 1.0V, 0b110 for 0.9V. + 19 + 3 + read-write + + + FAST_MEM_RA + This field controls fast memory RA parameter. 0b00 for 1.1V/1.0V operating Voltage, 0b01 for 0.9V. + 22 + 2 + read-write + + + FAST_MEM_RM + This field controls fast memory RM parameter. 0b0011 for 1.1V operating Voltage, 0b0010 for 1.0V, 0b0000 for 0.9V. + 24 + 4 + read-write + + + FAST_MEM_MUX_FSM_IDLE + reserved + 28 + 1 + read-only + + + FAST_MEM_MUX_SEL_STATUS + reserved + 29 + 1 + read-only + + + FAST_MEM_MUX_SEL_UPDATE + reserved + 30 + 1 + read-only + + + FAST_MEM_MUX_SEL + reserved + 31 + 1 + read-only + + + + + SDIO_ACTIVE + need_des + 0x4C + 0x20 + 0x02800000 + + + SDIO_ACT_DNUM + need_des + 22 + 10 + read-write + + + + + LPCORE + need_des + 0x50 + 0x20 + + + ETM_WAKEUP_FLAG_CLR + need_des + 0 + 1 + write-only + + + ETM_WAKEUP_FLAG + need_des + 1 + 1 + read-only + + + DISABLE + need_des + 31 + 1 + read-write + + + + + SAR_CCT + need_des + 0x54 + 0x20 + + + SAR2_PWDET_CCT + need_des + 29 + 3 + read-write + + + + + JTAG_SEL + need_des + 0x58 + 0x20 + 0x80000000 + + + SOFT + If strapping_sel_jtag feature is disabled by efuse, and if neither pad_jtag or usb_jtag is disabled by efuse, this field determines which one jtag between usb_jtag and pad_jtag will be used. 1'b1(default): usb_jtag, 1'b0: pad_jtag. + 31 + 1 + read-write + + + + + DATE + need_des + 0x3FC + 0x20 + 0x02210090 + + + DATE + need_des + 0 + 31 + read-write + + + CLK_EN + need_des + 31 + 1 + read-write + + + + + + + LP_APM + Peripheral LP_APM + LP_APM + 0x600B3800 + + 0x0 + 0x3C + registers + + + + REGION_FILTER_EN + Region filter enable register + 0x0 + 0x20 + 0x00000001 + + + REGION_FILTER_EN + Region filter enable + 0 + 2 + read-write + + + + + REGION0_ADDR_START + Region address register + 0x4 + 0x20 + + + REGION0_ADDR_START + Start address of region0 + 0 + 32 + read-write + + + + + REGION0_ADDR_END + Region address register + 0x8 + 0x20 + 0xFFFFFFFF + + + REGION0_ADDR_END + End address of region0 + 0 + 32 + read-write + + + + + REGION0_PMS_ATTR + Region access authority attribute register + 0xC + 0x20 + + + REGION0_R0_PMS_X + Region execute authority in REE_MODE0 + 0 + 1 + read-write + + + REGION0_R0_PMS_W + Region write authority in REE_MODE0 + 1 + 1 + read-write + + + REGION0_R0_PMS_R + Region read authority in REE_MODE0 + 2 + 1 + read-write + + + REGION0_R1_PMS_X + Region execute authority in REE_MODE1 + 4 + 1 + read-write + + + REGION0_R1_PMS_W + Region write authority in REE_MODE1 + 5 + 1 + read-write + + + REGION0_R1_PMS_R + Region read authority in REE_MODE1 + 6 + 1 + read-write + + + REGION0_R2_PMS_X + Region execute authority in REE_MODE2 + 8 + 1 + read-write + + + REGION0_R2_PMS_W + Region write authority in REE_MODE2 + 9 + 1 + read-write + + + REGION0_R2_PMS_R + Region read authority in REE_MODE2 + 10 + 1 + read-write + + + + + REGION1_ADDR_START + Region address register + 0x10 + 0x20 + + + REGION1_ADDR_START + Start address of region1 + 0 + 32 + read-write + + + + + REGION1_ADDR_END + Region address register + 0x14 + 0x20 + 0xFFFFFFFF + + + REGION1_ADDR_END + End address of region1 + 0 + 32 + read-write + + + + + REGION1_PMS_ATTR + Region access authority attribute register + 0x18 + 0x20 + + + REGION1_R0_PMS_X + Region execute authority in REE_MODE0 + 0 + 1 + read-write + + + REGION1_R0_PMS_W + Region write authority in REE_MODE0 + 1 + 1 + read-write + + + REGION1_R0_PMS_R + Region read authority in REE_MODE0 + 2 + 1 + read-write + + + REGION1_R1_PMS_X + Region execute authority in REE_MODE1 + 4 + 1 + read-write + + + REGION1_R1_PMS_W + Region write authority in REE_MODE1 + 5 + 1 + read-write + + + REGION1_R1_PMS_R + Region read authority in REE_MODE1 + 6 + 1 + read-write + + + REGION1_R2_PMS_X + Region execute authority in REE_MODE2 + 8 + 1 + read-write + + + REGION1_R2_PMS_W + Region write authority in REE_MODE2 + 9 + 1 + read-write + + + REGION1_R2_PMS_R + Region read authority in REE_MODE2 + 10 + 1 + read-write + + + + + FUNC_CTRL + PMS function control register + 0xC4 + 0x20 + 0x00000001 + + + M0_PMS_FUNC_EN + PMS M0 function enable + 0 + 1 + read-write + + + + + M0_STATUS + M0 status register + 0xC8 + 0x20 + + + M0_EXCEPTION_STATUS + Exception status + 0 + 2 + read-only + + + + + M0_STATUS_CLR + M0 status clear register + 0xCC + 0x20 + + + M0_REGION_STATUS_CLR + Clear exception status + 0 + 1 + write-only + + + + + M0_EXCEPTION_INFO0 + M0 exception_info0 register + 0xD0 + 0x20 + + + M0_EXCEPTION_REGION + Exception region + 0 + 2 + read-only + + + M0_EXCEPTION_MODE + Exception mode + 16 + 2 + read-only + + + M0_EXCEPTION_ID + Exception id information + 18 + 5 + read-only + + + + + M0_EXCEPTION_INFO1 + M0 exception_info1 register + 0xD4 + 0x20 + + + M0_EXCEPTION_ADDR + Exception addr + 0 + 32 + read-only + + + + + INT_EN + APM interrupt enable register + 0xE8 + 0x20 + + + M0_APM_INT_EN + APM M0 interrupt enable + 0 + 1 + read-write + + + + + CLOCK_GATE + clock gating register + 0xEC + 0x20 + 0x00000001 + + + CLK_EN + reg_clk_en + 0 + 1 + read-write + + + + + DATE + Version register + 0xFC + 0x20 + 0x02207260 + + + DATE + reg_date + 0 + 28 + read-write + + + + + + + LP_CLKRST + Peripheral LP_CLKRST + LP_CLKRST + 0x600B0400 + + 0x0 + 0x34 + registers + + + + LP_CLK_CONF + need_des + 0x0 + 0x20 + 0x00000004 + + + SLOW_CLK_SEL + need_des + 0 + 2 + read-write + + + FAST_CLK_SEL + need_des + 2 + 2 + read-write + + + LP_PERI_DIV_NUM + need_des + 4 + 8 + read-write + + + + + LP_CLK_PO_EN + need_des + 0x4 + 0x20 + 0x000007FF + + + AON_SLOW_OEN + need_des + 0 + 1 + read-write + + + AON_FAST_OEN + need_des + 1 + 1 + read-write + + + SOSC_OEN + need_des + 2 + 1 + read-write + + + FOSC_OEN + need_des + 3 + 1 + read-write + + + OSC32K_OEN + need_des + 4 + 1 + read-write + + + XTAL32K_OEN + need_des + 5 + 1 + read-write + + + CORE_EFUSE_OEN + need_des + 6 + 1 + read-write + + + SLOW_OEN + need_des + 7 + 1 + read-write + + + FAST_OEN + need_des + 8 + 1 + read-write + + + RNG_OEN + need_des + 9 + 1 + read-write + + + LPBUS_OEN + need_des + 10 + 1 + read-write + + + + + LP_CLK_EN + need_des + 0x8 + 0x20 + + + FAST_ORI_GATE + need_des + 31 + 1 + read-write + + + + + LP_RST_EN + need_des + 0xC + 0x20 + + + AON_EFUSE_CORE_RESET_EN + need_des + 28 + 1 + read-write + + + LP_TIMER_RESET_EN + need_des + 29 + 1 + read-write + + + WDT_RESET_EN + need_des + 30 + 1 + read-write + + + ANA_PERI_RESET_EN + need_des + 31 + 1 + read-write + + + + + RESET_CAUSE + need_des + 0x10 + 0x20 + 0x00000020 + + + RESET_CAUSE + need_des + 0 + 5 + read-only + + + CORE0_RESET_FLAG + need_des + 5 + 1 + read-only + + + CORE0_RESET_CAUSE_CLR + need_des + 29 + 1 + write-only + + + CORE0_RESET_FLAG_SET + need_des + 30 + 1 + write-only + + + CORE0_RESET_FLAG_CLR + need_des + 31 + 1 + write-only + + + + + CPU_RESET + need_des + 0x14 + 0x20 + 0x04400000 + + + RTC_WDT_CPU_RESET_LENGTH + need_des + 22 + 3 + read-write + + + RTC_WDT_CPU_RESET_EN + need_des + 25 + 1 + read-write + + + CPU_STALL_WAIT + need_des + 26 + 5 + read-write + + + CPU_STALL_EN + need_des + 31 + 1 + read-write + + + + + FOSC_CNTL + need_des + 0x18 + 0x20 + 0x96000000 + + + FOSC_DFREQ + need_des + 22 + 10 + read-write + + + + + RC32K_CNTL + need_des + 0x1C + 0x20 + 0xA2800000 + + + RC32K_DFREQ + need_des + 22 + 10 + read-write + + + + + CLK_TO_HP + need_des + 0x20 + 0x20 + 0xF0000000 + + + ICG_HP_XTAL32K + need_des + 28 + 1 + read-write + + + ICG_HP_SOSC + need_des + 29 + 1 + read-write + + + ICG_HP_OSC32K + need_des + 30 + 1 + read-write + + + ICG_HP_FOSC + need_des + 31 + 1 + read-write + + + + + LPMEM_FORCE + need_des + 0x24 + 0x20 + + + LPMEM_CLK_FORCE_ON + need_des + 31 + 1 + read-write + + + + + LPPERI + need_des + 0x28 + 0x20 + 0x20000000 + + + LP_BLETIMER_DIV_NUM + need_des + 12 + 12 + read-write + + + LP_BLETIMER_32K_SEL + need_des + 24 + 2 + read-write + + + LP_SEL_OSC_SLOW + need_des + 26 + 1 + read-write + + + LP_SEL_OSC_FAST + need_des + 27 + 1 + read-write + + + LP_SEL_XTAL + need_des + 28 + 1 + read-write + + + LP_SEL_XTAL32K + need_des + 29 + 1 + read-write + + + LP_I2C_CLK_SEL + need_des + 30 + 1 + read-write + + + LP_UART_CLK_SEL + need_des + 31 + 1 + read-write + + + + + XTAL32K + need_des + 0x2C + 0x20 + 0x66C00000 + + + DRES_XTAL32K + need_des + 22 + 3 + read-write + + + DGM_XTAL32K + need_des + 25 + 3 + read-write + + + DBUF_XTAL32K + need_des + 28 + 1 + read-write + + + DAC_XTAL32K + need_des + 29 + 3 + read-write + + + + + DATE + need_des + 0x3FC + 0x20 + 0x02207280 + + + CLKRST_DATE + need_des + 0 + 31 + read-write + + + CLK_EN + need_des + 31 + 1 + read-write + + + + + + + LP_TIMER + Peripheral LP_TIMER + LP_TIMER + 0x600B0C00 + + 0x0 + 0x34 + registers + + + + TAR0_LOW + need_des + 0x0 + 0x20 + + + MAIN_TIMER_TAR_LOW0 + need_des + 0 + 32 + read-write + + + + + TAR0_HIGH + need_des + 0x4 + 0x20 + + + MAIN_TIMER_TAR_HIGH0 + need_des + 0 + 16 + read-write + + + MAIN_TIMER_TAR_EN0 + need_des + 31 + 1 + write-only + + + + + UPDATE + need_des + 0x10 + 0x20 + + + MAIN_TIMER_UPDATE + need_des + 28 + 1 + write-only + + + MAIN_TIMER_XTAL_OFF + need_des + 29 + 1 + read-write + + + MAIN_TIMER_SYS_STALL + need_des + 30 + 1 + read-write + + + MAIN_TIMER_SYS_RST + need_des + 31 + 1 + read-write + + + + + MAIN_BUF0_LOW + need_des + 0x14 + 0x20 + + + MAIN_TIMER_BUF0_LOW + need_des + 0 + 32 + read-only + + + + + MAIN_BUF0_HIGH + need_des + 0x18 + 0x20 + + + MAIN_TIMER_BUF0_HIGH + need_des + 0 + 16 + read-only + + + + + MAIN_BUF1_LOW + need_des + 0x1C + 0x20 + + + MAIN_TIMER_BUF1_LOW + need_des + 0 + 32 + read-only + + + + + MAIN_BUF1_HIGH + need_des + 0x20 + 0x20 + + + MAIN_TIMER_BUF1_HIGH + need_des + 0 + 16 + read-only + + + + + MAIN_OVERFLOW + need_des + 0x24 + 0x20 + + + MAIN_TIMER_ALARM_LOAD + need_des + 31 + 1 + write-only + + + + + INT_RAW + need_des + 0x28 + 0x20 + + + OVERFLOW_RAW + need_des + 30 + 1 + read-only + + + SOC_WAKEUP_INT_RAW + need_des + 31 + 1 + read-only + + + + + INT_ST + need_des + 0x2C + 0x20 + + + OVERFLOW_ST + need_des + 30 + 1 + read-only + + + SOC_WAKEUP_INT_ST + need_des + 31 + 1 + read-only + + + + + INT_ENA + need_des + 0x30 + 0x20 + + + OVERFLOW_ENA + need_des + 30 + 1 + read-write + + + SOC_WAKEUP_INT_ENA + need_des + 31 + 1 + read-write + + + + + INT_CLR + need_des + 0x34 + 0x20 + + + OVERFLOW_CLR + need_des + 30 + 1 + write-only + + + SOC_WAKEUP_INT_CLR + need_des + 31 + 1 + write-only + + + + + DATE + need_des + 0x3FC + 0x20 + 0x02111150 + + + DATE + need_des + 0 + 31 + read-write + + + CLK_EN + need_des + 31 + 1 + read-write + + + + + + + LP_WDT + Peripheral LP_WDT + LP_WDT + 0x600B1C00 + + 0x0 + 0x3C + registers + + + + CONFIG0 + need_des + 0x0 + 0x20 + 0x00013200 + + + WDT_PAUSE_IN_SLP + need_des + 9 + 1 + read-write + + + WDT_APPCPU_RESET_EN + need_des + 10 + 1 + read-write + + + WDT_PROCPU_RESET_EN + need_des + 11 + 1 + read-write + + + WDT_FLASHBOOT_MOD_EN + need_des + 12 + 1 + read-write + + + WDT_SYS_RESET_LENGTH + need_des + 13 + 3 + read-write + + + WDT_CPU_RESET_LENGTH + need_des + 16 + 3 + read-write + + + WDT_STG3 + need_des + 19 + 3 + read-write + + + WDT_STG2 + need_des + 22 + 3 + read-write + + + WDT_STG1 + need_des + 25 + 3 + read-write + + + WDT_STG0 + need_des + 28 + 3 + read-write + + + WDT_EN + need_des + 31 + 1 + read-write + + + + + CONFIG1 + need_des + 0x4 + 0x20 + 0x00030D40 + + + WDT_STG0_HOLD + need_des + 0 + 32 + read-write + + + + + CONFIG2 + need_des + 0x8 + 0x20 + 0x00013880 + + + WDT_STG1_HOLD + need_des + 0 + 32 + read-write + + + + + CONFIG3 + need_des + 0xC + 0x20 + 0x00000FFF + + + WDT_STG2_HOLD + need_des + 0 + 32 + read-write + + + + + CONFIG4 + need_des + 0x10 + 0x20 + 0x00000FFF + + + WDT_STG3_HOLD + need_des + 0 + 32 + read-write + + + + + CONFIG5 + need_des + 0x14 + 0x20 + 0x000000FF + + + CHIP_RESET_TARGET + need_des + 0 + 8 + read-write + + + CHIP_RESET_EN + need_des + 8 + 1 + read-write + + + CHIP_RESET_KEY + need_des + 9 + 8 + read-write + + + + + FEED + need_des + 0x18 + 0x20 + + + RTC_WDT_FEED + need_des + 31 + 1 + write-only + + + + + WPROTECT + need_des + 0x1C + 0x20 + + + WDT_WKEY + need_des + 0 + 32 + read-write + + + + + SWD_CONFIG + need_des + 0x20 + 0x20 + 0x12C00000 + + + SWD_RESET_FLAG + need_des + 0 + 1 + read-only + + + SWD_AUTO_FEED_EN + need_des + 18 + 1 + read-write + + + SWD_RST_FLAG_CLR + need_des + 19 + 1 + write-only + + + SWD_SIGNAL_WIDTH + need_des + 20 + 10 + read-write + + + SWD_DISABLE + need_des + 30 + 1 + read-write + + + SWD_FEED + need_des + 31 + 1 + write-only + + + + + SWD_WPROTECT + need_des + 0x24 + 0x20 + + + SWD_WKEY + need_des + 0 + 32 + read-write + + + + + INT_RAW + need_des + 0x28 + 0x20 + + + SUPER_WDT_INT_RAW + need_des + 30 + 1 + read-only + + + LP_WDT_INT_RAW + need_des + 31 + 1 + read-only + + + + + INT_ST + need_des + 0x2C + 0x20 + + + SUPER_WDT_INT_ST + need_des + 30 + 1 + read-only + + + LP_WDT_INT_ST + need_des + 31 + 1 + read-only + + + + + INT_ENA + need_des + 0x30 + 0x20 + + + SUPER_WDT_INT_ENA + need_des + 30 + 1 + read-write + + + LP_WDT_INT_ENA + need_des + 31 + 1 + read-write + + + + + INT_CLR + need_des + 0x34 + 0x20 + + + SUPER_WDT_INT_CLR + need_des + 30 + 1 + write-only + + + LP_WDT_INT_CLR + need_des + 31 + 1 + write-only + + + + + DATE + need_des + 0x3FC + 0x20 + 0x02112080 + + + LP_WDT_DATE + need_des + 0 + 31 + read-write + + + CLK_EN + need_des + 31 + 1 + read-write + + + + + + + MCPWM + Motor Control Pulse-Width Modulation + MCPWM + 0x60014000 + + 0x0 + 0x130 + registers + + + + CLK_CFG + PWM clock prescaler register. + 0x0 + 0x20 + + + CLK_PRESCALE + Period of PWM_clk = 6.25ns * (PWM_CLK_PRESCALE + 1) + 0 + 8 + read-write + + + + + TIMER0_CFG0 + PWM timer0 period and update method configuration register. + 0x4 + 0x20 + 0x0000FF00 + + + TIMER0_PRESCALE + period of PT0_clk = Period of PWM_clk * (PWM_TIMER0_PRESCALE + 1) + 0 + 8 + read-write + + + TIMER0_PERIOD + period shadow register of PWM timer0 + 8 + 16 + read-write + + + TIMER0_PERIOD_UPMETHOD + Update method for active register of PWM timer0 period, 0: immediate, 1: TEZ, 2: sync, 3: TEZ | sync. TEZ here and below means timer equal zero event + 24 + 2 + read-write + + + + + TIMER0_CFG1 + PWM timer0 working mode and start/stop control configuration register. + 0x8 + 0x20 + + + TIMER0_START + PWM timer0 start and stop control. 0: if PWM timer0 starts, then stops at TEZ, 1: if timer0 starts, then stops at TEP, 2: PWM timer0 starts and runs on, 3: timer0 starts and stops at the next TEZ, 4: timer0 starts and stops at the next TEP. TEP here and below means the event that happens when the timer equals to period + 0 + 3 + read-write + + + TIMER0_MOD + PWM timer0 working mode, 0: freeze, 1: increase mode, 2: decrease mode, 3: up-down mode + 3 + 2 + read-write + + + + + TIMER0_SYNC + PWM timer0 sync function configuration register. + 0xC + 0x20 + + + TIMER0_SYNCI_EN + When set, timer reloading with phase on sync input event is enabled. + 0 + 1 + read-write + + + SW + Toggling this bit will trigger a software sync. + 1 + 1 + read-write + + + TIMER0_SYNCO_SEL + PWM timer0 sync_out selection, 0: sync_in, 1: TEZ, 2: TEP, and sync out will always generate when toggling the reg_timer0_sync_sw bit + 2 + 2 + read-write + + + TIMER0_PHASE + phase for timer reload on sync event + 4 + 16 + read-write + + + TIMER0_PHASE_DIRECTION + Configure the PWM timer0's direction when timer0 mode is up-down mode: 0-increase,1-decrease + 20 + 1 + read-write + + + + + TIMER0_STATUS + PWM timer0 status register. + 0x10 + 0x20 + + + TIMER0_VALUE + current PWM timer0 counter value + 0 + 16 + read-only + + + TIMER0_DIRECTION + current PWM timer0 counter direction, 0: increment 1: decrement + 16 + 1 + read-only + + + + + TIMER1_CFG0 + PWM timer1 period and update method configuration register. + 0x14 + 0x20 + 0x0000FF00 + + + TIMER1_PRESCALE + period of PT0_clk = Period of PWM_clk * (PWM_timer1_PRESCALE + 1) + 0 + 8 + read-write + + + TIMER1_PERIOD + period shadow register of PWM timer1 + 8 + 16 + read-write + + + TIMER1_PERIOD_UPMETHOD + Update method for active register of PWM timer1 period, 0: immediate, 1: TEZ, 2: sync, 3: TEZ | sync. TEZ here and below means timer equal zero event + 24 + 2 + read-write + + + + + TIMER1_CFG1 + PWM timer1 working mode and start/stop control configuration register. + 0x18 + 0x20 + + + TIMER1_START + PWM timer1 start and stop control. 0: if PWM timer1 starts, then stops at TEZ, 1: if timer1 starts, then stops at TEP, 2: PWM timer1 starts and runs on, 3: timer1 starts and stops at the next TEZ, 4: timer1 starts and stops at the next TEP. TEP here and below means the event that happens when the timer equals to period + 0 + 3 + read-write + + + TIMER1_MOD + PWM timer1 working mode, 0: freeze, 1: increase mode, 2: decrease mode, 3: up-down mode + 3 + 2 + read-write + + + + + TIMER1_SYNC + PWM timer1 sync function configuration register. + 0x1C + 0x20 + + + TIMER1_SYNCI_EN + When set, timer reloading with phase on sync input event is enabled. + 0 + 1 + read-write + + + SW + Toggling this bit will trigger a software sync. + 1 + 1 + read-write + + + TIMER1_SYNCO_SEL + PWM timer1 sync_out selection, 0: sync_in, 1: TEZ, 2: TEP, and sync out will always generate when toggling the reg_timer1_sync_sw bit + 2 + 2 + read-write + + + TIMER1_PHASE + phase for timer reload on sync event + 4 + 16 + read-write + + + TIMER1_PHASE_DIRECTION + Configure the PWM timer1's direction when timer1 mode is up-down mode: 0-increase,1-decrease + 20 + 1 + read-write + + + + + TIMER1_STATUS + PWM timer1 status register. + 0x20 + 0x20 + + + TIMER1_VALUE + current PWM timer1 counter value + 0 + 16 + read-only + + + TIMER1_DIRECTION + current PWM timer1 counter direction, 0: increment 1: decrement + 16 + 1 + read-only + + + + + TIMER2_CFG0 + PWM timer2 period and update method configuration register. + 0x24 + 0x20 + 0x0000FF00 + + + TIMER2_PRESCALE + period of PT0_clk = Period of PWM_clk * (PWM_timer2_PRESCALE + 1) + 0 + 8 + read-write + + + TIMER2_PERIOD + period shadow register of PWM timer2 + 8 + 16 + read-write + + + TIMER2_PERIOD_UPMETHOD + Update method for active register of PWM timer2 period, 0: immediate, 1: TEZ, 2: sync, 3: TEZ | sync. TEZ here and below means timer equal zero event + 24 + 2 + read-write + + + + + TIMER2_CFG1 + PWM timer2 working mode and start/stop control configuration register. + 0x28 + 0x20 + + + TIMER2_START + PWM timer2 start and stop control. 0: if PWM timer2 starts, then stops at TEZ, 1: if timer2 starts, then stops at TEP, 2: PWM timer2 starts and runs on, 3: timer2 starts and stops at the next TEZ, 4: timer2 starts and stops at the next TEP. TEP here and below means the event that happens when the timer equals to period + 0 + 3 + read-write + + + TIMER2_MOD + PWM timer2 working mode, 0: freeze, 1: increase mode, 2: decrease mode, 3: up-down mode + 3 + 2 + read-write + + + + + TIMER2_SYNC + PWM timer2 sync function configuration register. + 0x2C + 0x20 + + + TIMER2_SYNCI_EN + When set, timer reloading with phase on sync input event is enabled. + 0 + 1 + read-write + + + SW + Toggling this bit will trigger a software sync. + 1 + 1 + read-write + + + TIMER2_SYNCO_SEL + PWM timer2 sync_out selection, 0: sync_in, 1: TEZ, 2: TEP, and sync out will always generate when toggling the reg_timer0_sync_sw bit + 2 + 2 + read-write + + + TIMER2_PHASE + phase for timer reload on sync event + 4 + 16 + read-write + + + TIMER2_PHASE_DIRECTION + Configure the PWM timer2's direction when timer2 mode is up-down mode: 0-increase,1-decrease + 20 + 1 + read-write + + + + + TIMER2_STATUS + PWM timer2 status register. + 0x30 + 0x20 + + + TIMER2_VALUE + current PWM timer2 counter value + 0 + 16 + read-only + + + TIMER2_DIRECTION + current PWM timer2 counter direction, 0: increment 1: decrement + 16 + 1 + read-only + + + + + TIMER_SYNCI_CFG + Synchronization input selection for three PWM timers. + 0x34 + 0x20 + + + TIMER0_SYNCISEL + select sync input for PWM timer0, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected + 0 + 3 + read-write + + + TIMER1_SYNCISEL + select sync input for PWM timer1, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected + 3 + 3 + read-write + + + TIMER2_SYNCISEL + select sync input for PWM timer2, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected + 6 + 3 + read-write + + + EXTERNAL_SYNCI0_INVERT + invert SYNC0 from GPIO matrix + 9 + 1 + read-write + + + EXTERNAL_SYNCI1_INVERT + invert SYNC1 from GPIO matrix + 10 + 1 + read-write + + + EXTERNAL_SYNCI2_INVERT + invert SYNC2 from GPIO matrix + 11 + 1 + read-write + + + + + OPERATOR_TIMERSEL + Select specific timer for PWM operators. + 0x38 + 0x20 + + + OPERATOR0_TIMERSEL + Select which PWM timer's is the timing reference for PWM operator0, 0: timer0, 1: timer1, 2: timer2 + 0 + 2 + read-write + + + OPERATOR1_TIMERSEL + Select which PWM timer's is the timing reference for PWM operator1, 0: timer0, 1: timer1, 2: timer2 + 2 + 2 + read-write + + + OPERATOR2_TIMERSEL + Select which PWM timer's is the timing reference for PWM operator2, 0: timer0, 1: timer1, 2: timer2 + 4 + 2 + read-write + + + + + GEN0_STMP_CFG + Transfer status and update method for time stamp registers A and B + 0x3C + 0x20 + + + CMPR0_A_UPMETHOD + Update method for PWM generator 0 time stamp A's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update. + 0 + 4 + read-write + + + CMPR0_B_UPMETHOD + Update method for PWM generator 0 time stamp B's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update. + 4 + 4 + read-write + + + CMPR0_A_SHDW_FULL + Set and reset by hardware. If set, PWM generator 0 time stamp A's shadow reg is filled and waiting to be transferred to A's active reg. If cleared, A's active reg has been updated with shadow register latest value + 8 + 1 + read-write + + + CMPR0_B_SHDW_FULL + Set and reset by hardware. If set, PWM generator 0 time stamp B's shadow reg is filled and waiting to be transferred to B's active reg. If cleared, B's active reg has been updated with shadow register latest value + 9 + 1 + read-write + + + + + GEN0_TSTMP_A + Shadow register for register A. + 0x40 + 0x20 + + + CMPR0_A + PWM generator 0 time stamp A's shadow register + 0 + 16 + read-write + + + + + GEN0_TSTMP_B + Shadow register for register B. + 0x44 + 0x20 + + + CMPR0_B + PWM generator 0 time stamp B's shadow register + 0 + 16 + read-write + + + + + GEN0_CFG0 + Fault event T0 and T1 handling + 0x48 + 0x20 + + + GEN0_CFG_UPMETHOD + Update method for PWM generator 0's active register of configuration. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1:TEP,when bit2 is set to 1:sync,when bit3 is set to 1:disable the update + 0 + 4 + read-write + + + GEN0_T0_SEL + Source selection for PWM generator 0 event_t0, take effect immediately, 0: fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none + 4 + 3 + read-write + + + GEN0_T1_SEL + Source selection for PWM generator 0 event_t1, take effect immediately, 0: fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none + 7 + 3 + read-write + + + + + GEN0_FORCE + Permissives to force PWM0A and PWM0B outputs by software + 0x4C + 0x20 + 0x00000020 + + + GEN0_CNTUFORCE_UPMETHOD + Updating method for continuous software force of PWM generator0. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ,,when bit1 is set to 1: TEP, when bit2 is set to 1: TEA, when bit3 is set to 1: TEB, when bit4 is set to 1: sync, when bit5 is set to 1: disable update. (TEA/B here and below means an event generated when the timer's value equals to that of register A/B.) + 0 + 6 + read-write + + + GEN0_A_CNTUFORCE_MODE + Continuous software force mode for PWM0A. 0: disabled, 1: low, 2: high, 3: disabled + 6 + 2 + read-write + + + GEN0_B_CNTUFORCE_MODE + Continuous software force mode for PWM0B. 0: disabled, 1: low, 2: high, 3: disabled + 8 + 2 + read-write + + + GEN0_A_NCIFORCE + Trigger of non-continuous immediate software-force event for PWM0A, a toggle will trigger a force event. + 10 + 1 + read-write + + + GEN0_A_NCIFORCE_MODE + non-continuous immediate software force mode for PWM0A, 0: disabled, 1: low, 2: high, 3: disabled + 11 + 2 + read-write + + + GEN0_B_NCIFORCE + Trigger of non-continuous immediate software-force event for PWM0B, a toggle will trigger a force event. + 13 + 1 + read-write + + + GEN0_B_NCIFORCE_MODE + non-continuous immediate software force mode for PWM0B, 0: disabled, 1: low, 2: high, 3: disabled + 14 + 2 + read-write + + + + + GEN0_A + Actions triggered by events on PWM0A + 0x50 + 0x20 + + + UTEZ + Action on PWM0A triggered by event TEZ when timer increasing + 0 + 2 + read-write + + + UTEP + Action on PWM0A triggered by event TEP when timer increasing + 2 + 2 + read-write + + + UTEA + Action on PWM0A triggered by event TEA when timer increasing + 4 + 2 + read-write + + + UTEB + Action on PWM0A triggered by event TEB when timer increasing + 6 + 2 + read-write + + + UT0 + Action on PWM0A triggered by event_t0 when timer increasing + 8 + 2 + read-write + + + UT1 + Action on PWM0A triggered by event_t1 when timer increasing + 10 + 2 + read-write + + + DTEZ + Action on PWM0A triggered by event TEZ when timer decreasing + 12 + 2 + read-write + + + DTEP + Action on PWM0A triggered by event TEP when timer decreasing + 14 + 2 + read-write + + + DTEA + Action on PWM0A triggered by event TEA when timer decreasing + 16 + 2 + read-write + + + DTEB + Action on PWM0A triggered by event TEB when timer decreasing + 18 + 2 + read-write + + + DT0 + Action on PWM0A triggered by event_t0 when timer decreasing + 20 + 2 + read-write + + + DT1 + Action on PWM0A triggered by event_t1 when timer decreasing. 0: no change, 1: low, 2: high, 3: toggle + 22 + 2 + read-write + + + + + GEN0_B + Actions triggered by events on PWM0B + 0x54 + 0x20 + + + UTEZ + Action on PWM0B triggered by event TEZ when timer increasing + 0 + 2 + read-write + + + UTEP + Action on PWM0B triggered by event TEP when timer increasing + 2 + 2 + read-write + + + UTEA + Action on PWM0B triggered by event TEA when timer increasing + 4 + 2 + read-write + + + UTEB + Action on PWM0B triggered by event TEB when timer increasing + 6 + 2 + read-write + + + UT0 + Action on PWM0B triggered by event_t0 when timer increasing + 8 + 2 + read-write + + + UT1 + Action on PWM0B triggered by event_t1 when timer increasing + 10 + 2 + read-write + + + DTEZ + Action on PWM0B triggered by event TEZ when timer decreasing + 12 + 2 + read-write + + + DTEP + Action on PWM0B triggered by event TEP when timer decreasing + 14 + 2 + read-write + + + DTEA + Action on PWM0B triggered by event TEA when timer decreasing + 16 + 2 + read-write + + + DTEB + Action on PWM0B triggered by event TEB when timer decreasing + 18 + 2 + read-write + + + DT0 + Action on PWM0B triggered by event_t0 when timer decreasing + 20 + 2 + read-write + + + DT1 + Action on PWM0B triggered by event_t1 when timer decreasing. 0: no change, 1: low, 2: high, 3: toggle + 22 + 2 + read-write + + + + + DT0_CFG + dead time type selection and configuration + 0x58 + 0x20 + 0x00018000 + + + DB0_FED_UPMETHOD + Update method for FED (rising edge delay) active register. 0: immediate, when bit0 is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when bit3 is set to 1: disable the update + 0 + 4 + read-write + + + DB0_RED_UPMETHOD + Update method for RED (rising edge delay) active register. 0: immediate, when bit0 is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when bit3 is set to 1: disable the update + 4 + 4 + read-write + + + DB0_DEB_MODE + S8 in table, dual-edge B mode, 0: fed/red take effect on different path separately, 1: fed/red take effect on B path, A out is in bypass or dulpB mode + 8 + 1 + read-write + + + DB0_A_OUTSWAP + S6 in table + 9 + 1 + read-write + + + DB0_B_OUTSWAP + S7 in table + 10 + 1 + read-write + + + DB0_RED_INSEL + S4 in table + 11 + 1 + read-write + + + DB0_FED_INSEL + S5 in table + 12 + 1 + read-write + + + DB0_RED_OUTINVERT + S2 in table + 13 + 1 + read-write + + + DB0_FED_OUTINVERT + S3 in table + 14 + 1 + read-write + + + DB0_A_OUTBYPASS + S1 in table + 15 + 1 + read-write + + + DB0_B_OUTBYPASS + S0 in table + 16 + 1 + read-write + + + DB0_CLK_SEL + Dead time generator 0 clock selection. 0: PWM_clk, 1: PT_clk + 17 + 1 + read-write + + + + + DT0_FED_CFG + Shadow register for falling edge delay (FED). + 0x5C + 0x20 + + + DB0_FED + Shadow register for FED + 0 + 16 + read-write + + + + + DT0_RED_CFG + Shadow register for rising edge delay (RED). + 0x60 + 0x20 + + + DB0_RED + Shadow register for RED + 0 + 16 + read-write + + + + + CARRIER0_CFG + Carrier enable and configuratoin + 0x64 + 0x20 + + + CHOPPER0_EN + When set, carrier0 function is enabled. When cleared, carrier0 is bypassed + 0 + 1 + read-write + + + CHOPPER0_PRESCALE + PWM carrier0 clock (PC_clk) prescale value. Period of PC_clk = period of PWM_clk * (PWM_CARRIER0_PRESCALE + 1) + 1 + 4 + read-write + + + CHOPPER0_DUTY + carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8 + 5 + 3 + read-write + + + CHOPPER0_OSHTWTH + width of the first pulse in number of periods of the carrier + 8 + 4 + read-write + + + CHOPPER0_OUT_INVERT + when set, invert the output of PWM0A and PWM0B for this submodule + 12 + 1 + read-write + + + CHOPPER0_IN_INVERT + when set, invert the input of PWM0A and PWM0B for this submodule + 13 + 1 + read-write + + + + + FH0_CFG0 + Actions on PWM0A and PWM0B trip events + 0x68 + 0x20 + + + TZ0_SW_CBC + Enable register for software force cycle-by-cycle mode action. 0: disable, 1: enable + 0 + 1 + read-write + + + TZ0_F2_CBC + event_f2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + 1 + 1 + read-write + + + TZ0_F1_CBC + event_f1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + 2 + 1 + read-write + + + TZ0_F0_CBC + event_f0 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + 3 + 1 + read-write + + + TZ0_SW_OST + Enable register for software force one-shot mode action. 0: disable, 1: enable + 4 + 1 + read-write + + + TZ0_F2_OST + event_f2 will trigger one-shot mode action. 0: disable, 1: enable + 5 + 1 + read-write + + + TZ0_F1_OST + event_f1 will trigger one-shot mode action. 0: disable, 1: enable + 6 + 1 + read-write + + + TZ0_F0_OST + event_f0 will trigger one-shot mode action. 0: disable, 1: enable + 7 + 1 + read-write + + + TZ0_A_CBC_D + Cycle-by-cycle mode action on PWM0A when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + 8 + 2 + read-write + + + TZ0_A_CBC_U + Cycle-by-cycle mode action on PWM0A when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + 10 + 2 + read-write + + + TZ0_A_OST_D + One-shot mode action on PWM0A when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + 12 + 2 + read-write + + + TZ0_A_OST_U + One-shot mode action on PWM0A when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + 14 + 2 + read-write + + + TZ0_B_CBC_D + Cycle-by-cycle mode action on PWM0B when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + 16 + 2 + read-write + + + TZ0_B_CBC_U + Cycle-by-cycle mode action on PWM0B when fault event occurs and timer is increasing. 0: do nothing,1: force low, 2: force high, 3: toggle + 18 + 2 + read-write + + + TZ0_B_OST_D + One-shot mode action on PWM0B when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + 20 + 2 + read-write + + + TZ0_B_OST_U + One-shot mode action on PWM0B when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + 22 + 2 + read-write + + + + + FH0_CFG1 + Software triggers for fault handler actions + 0x6C + 0x20 + + + TZ0_CLR_OST + a rising edge will clear on going one-shot mode action + 0 + 1 + read-write + + + TZ0_CBCPULSE + cycle-by-cycle mode action refresh moment selection. When bit0 is set to 1: TEZ, when bit1 is set to 1:TEP + 1 + 2 + read-write + + + TZ0_FORCE_CBC + a toggle trigger a cycle-by-cycle mode action + 3 + 1 + read-write + + + TZ0_FORCE_OST + a toggle (software negate its value) triggers a one-shot mode action + 4 + 1 + read-write + + + + + FH0_STATUS + Status of fault events. + 0x70 + 0x20 + + + TZ0_CBC_ON + Set and reset by hardware. If set, a cycle-by-cycle mode action is on going + 0 + 1 + read-only + + + TZ0_OST_ON + Set and reset by hardware. If set, an one-shot mode action is on going + 1 + 1 + read-only + + + + + GEN1_STMP_CFG + Transfer status and update method for time stamp registers A and B + 0x74 + 0x20 + + + CMPR1_A_UPMETHOD + Update method for PWM generator 1 time stamp A's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update. + 0 + 4 + read-write + + + CMPR1_B_UPMETHOD + Update method for PWM generator 1 time stamp B's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update. + 4 + 4 + read-write + + + CMPR1_A_SHDW_FULL + Set and reset by hardware. If set, PWM generator 1 time stamp A's shadow reg is filled and waiting to be transferred to A's active reg. If cleared, A's active reg has been updated with shadow register latest value + 8 + 1 + read-write + + + CMPR1_B_SHDW_FULL + Set and reset by hardware. If set, PWM generator 1 time stamp B's shadow reg is filled and waiting to be transferred to B's active reg. If cleared, B's active reg has been updated with shadow register latest value + 9 + 1 + read-write + + + + + GEN1_TSTMP_A + Shadow register for register A. + 0x78 + 0x20 + + + CMPR1_A + PWM generator 1 time stamp A's shadow register + 0 + 16 + read-write + + + + + GEN1_TSTMP_B + Shadow register for register B. + 0x7C + 0x20 + + + CMPR1_B + PWM generator 1 time stamp B's shadow register + 0 + 16 + read-write + + + + + GEN1_CFG0 + Fault event T0 and T1 handling + 0x80 + 0x20 + + + GEN1_CFG_UPMETHOD + Update method for PWM generator 1's active register of configuration. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1:sync;when bit3 is set to 1:disable the update. + 0 + 4 + read-write + + + GEN1_T0_SEL + Source selection for PWM generator 1 event_t0, take effect immediately, 0: fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none + 4 + 3 + read-write + + + GEN1_T1_SEL + Source selection for PWM generator 1 event_t1, take effect immediately, 0: fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none + 7 + 3 + read-write + + + + + GEN1_FORCE + Permissives to force PWM1A and PWM1B outputs by software + 0x84 + 0x20 + 0x00000020 + + + GEN1_CNTUFORCE_UPMETHOD + Updating method for continuous software force of PWM generator 1. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ,,when bit1 is set to 1: TEP, when bit2 is set to 1: TEA, when bit3 is set to 1: TEB, when bit4 is set to 1: sync, when bit5 is set to 1: disable update. (TEA/B here and below means an event generated when the timer's value equals to that of register A/B.) + 0 + 6 + read-write + + + GEN1_A_CNTUFORCE_MODE + Continuous software force mode for PWM1A. 0: disabled, 1: low, 2: high, 3: disabled + 6 + 2 + read-write + + + GEN1_B_CNTUFORCE_MODE + Continuous software force mode for PWM1B. 0: disabled, 1: low, 2: high, 3: disabled + 8 + 2 + read-write + + + GEN1_A_NCIFORCE + Trigger of non-continuous immediate software-force event for PWM1A, a toggle will trigger a force event. + 10 + 1 + read-write + + + GEN1_A_NCIFORCE_MODE + non-continuous immediate software force mode for PWM1A, 0: disabled, 1: low, 2: high, 3: disabled + 11 + 2 + read-write + + + GEN1_B_NCIFORCE + Trigger of non-continuous immediate software-force event for PWM1B, a toggle will trigger a force event. + 13 + 1 + read-write + + + GEN1_B_NCIFORCE_MODE + non-continuous immediate software force mode for PWM1B, 0: disabled, 1: low, 2: high, 3: disabled + 14 + 2 + read-write + + + + + GEN1_A + Actions triggered by events on PWM1A + 0x88 + 0x20 + + + UTEZ + Action on PWM1A triggered by event TEZ when timer increasing + 0 + 2 + read-write + + + UTEP + Action on PWM1A triggered by event TEP when timer increasing + 2 + 2 + read-write + + + UTEA + Action on PWM1A triggered by event TEA when timer increasing + 4 + 2 + read-write + + + UTEB + Action on PWM1A triggered by event TEB when timer increasing + 6 + 2 + read-write + + + UT0 + Action on PWM1A triggered by event_t0 when timer increasing + 8 + 2 + read-write + + + UT1 + Action on PWM1A triggered by event_t1 when timer increasing + 10 + 2 + read-write + + + DTEZ + Action on PWM1A triggered by event TEZ when timer decreasing + 12 + 2 + read-write + + + DTEP + Action on PWM1A triggered by event TEP when timer decreasing + 14 + 2 + read-write + + + DTEA + Action on PWM1A triggered by event TEA when timer decreasing + 16 + 2 + read-write + + + DTEB + Action on PWM1A triggered by event TEB when timer decreasing + 18 + 2 + read-write + + + DT0 + Action on PWM1A triggered by event_t0 when timer decreasing + 20 + 2 + read-write + + + DT1 + Action on PWM1A triggered by event_t1 when timer decreasing. 0: no change, 1: low, 2: high, 3: toggle + 22 + 2 + read-write + + + + + GEN1_B + Actions triggered by events on PWM1B + 0x8C + 0x20 + + + UTEZ + Action on PWM1B triggered by event TEZ when timer increasing + 0 + 2 + read-write + + + UTEP + Action on PWM1B triggered by event TEP when timer increasing + 2 + 2 + read-write + + + UTEA + Action on PWM1B triggered by event TEA when timer increasing + 4 + 2 + read-write + + + UTEB + Action on PWM1B triggered by event TEB when timer increasing + 6 + 2 + read-write + + + UT0 + Action on PWM1B triggered by event_t0 when timer increasing + 8 + 2 + read-write + + + UT1 + Action on PWM1B triggered by event_t1 when timer increasing + 10 + 2 + read-write + + + DTEZ + Action on PWM1B triggered by event TEZ when timer decreasing + 12 + 2 + read-write + + + DTEP + Action on PWM1B triggered by event TEP when timer decreasing + 14 + 2 + read-write + + + DTEA + Action on PWM1B triggered by event TEA when timer decreasing + 16 + 2 + read-write + + + DTEB + Action on PWM1B triggered by event TEB when timer decreasing + 18 + 2 + read-write + + + DT0 + Action on PWM1B triggered by event_t0 when timer decreasing + 20 + 2 + read-write + + + DT1 + Action on PWM1B triggered by event_t1 when timer decreasing. 0: no change, 1: low, 2: high, 3: toggle + 22 + 2 + read-write + + + + + DT1_CFG + dead time type selection and configuration + 0x90 + 0x20 + 0x00018000 + + + DB1_FED_UPMETHOD + Update method for FED (falling edge delay) active register. 0: immediate, when bit0 is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when bit3 is set to 1: disable the update + 0 + 4 + read-write + + + DB1_RED_UPMETHOD + Update method for RED (rising edge delay) active register. 0: immediate,when bit0 is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when bit3 is set to 1: disable the update + 4 + 4 + read-write + + + DB1_DEB_MODE + S8 in table, dual-edge B mode, 0: fed/red take effect on different path separately, 1: fed/red take effect on B path, A out is in bypass or dulpB mode + 8 + 1 + read-write + + + DB1_A_OUTSWAP + S6 in table + 9 + 1 + read-write + + + DB1_B_OUTSWAP + S7 in table + 10 + 1 + read-write + + + DB1_RED_INSEL + S4 in table + 11 + 1 + read-write + + + DB1_FED_INSEL + S5 in table + 12 + 1 + read-write + + + DB1_RED_OUTINVERT + S2 in table + 13 + 1 + read-write + + + DB1_FED_OUTINVERT + S3 in table + 14 + 1 + read-write + + + DB1_A_OUTBYPASS + S1 in table + 15 + 1 + read-write + + + DB1_B_OUTBYPASS + S0 in table + 16 + 1 + read-write + + + DB1_CLK_SEL + Dead time generator 1 clock selection. 0: PWM_clk, 1: PT_clk + 17 + 1 + read-write + + + + + DT1_FED_CFG + Shadow register for falling edge delay (FED). + 0x94 + 0x20 + + + DB1_FED + Shadow register for FED + 0 + 16 + read-write + + + + + DT1_RED_CFG + Shadow register for rising edge delay (RED). + 0x98 + 0x20 + + + DB1_RED + Shadow register for RED + 0 + 16 + read-write + + + + + CARRIER1_CFG + Carrier enable and configuratoin + 0x9C + 0x20 + + + CHOPPER1_EN + When set, carrier1 function is enabled. When cleared, carrier1 is bypassed + 0 + 1 + read-write + + + CHOPPER1_PRESCALE + PWM carrier1 clock (PC_clk) prescale value. Period of PC_clk = period of PWM_clk * (PWM_CARRIER0_PRESCALE + 1) + 1 + 4 + read-write + + + CHOPPER1_DUTY + carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8 + 5 + 3 + read-write + + + CHOPPER1_OSHTWTH + width of the first pulse in number of periods of the carrier + 8 + 4 + read-write + + + CHOPPER1_OUT_INVERT + when set, invert the output of PWM1A and PWM1B for this submodule + 12 + 1 + read-write + + + CHOPPER1_IN_INVERT + when set, invert the input of PWM1A and PWM1B for this submodule + 13 + 1 + read-write + + + + + FH1_CFG0 + Actions on PWM1A and PWM1B trip events + 0xA0 + 0x20 + + + TZ1_SW_CBC + Enable register for software force cycle-by-cycle mode action. 0: disable, 1: enable + 0 + 1 + read-write + + + TZ1_F2_CBC + event_f2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + 1 + 1 + read-write + + + TZ1_F1_CBC + event_f1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + 2 + 1 + read-write + + + TZ1_F0_CBC + event_f0 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + 3 + 1 + read-write + + + TZ1_SW_OST + Enable register for software force one-shot mode action. 0: disable, 1: enable + 4 + 1 + read-write + + + TZ1_F2_OST + event_f2 will trigger one-shot mode action. 0: disable, 1: enable + 5 + 1 + read-write + + + TZ1_F1_OST + event_f1 will trigger one-shot mode action. 0: disable, 1: enable + 6 + 1 + read-write + + + TZ1_F0_OST + event_f0 will trigger one-shot mode action. 0: disable, 1: enable + 7 + 1 + read-write + + + TZ1_A_CBC_D + Cycle-by-cycle mode action on PWM1A when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + 8 + 2 + read-write + + + TZ1_A_CBC_U + Cycle-by-cycle mode action on PWM1A when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + 10 + 2 + read-write + + + TZ1_A_OST_D + One-shot mode action on PWM1A when fault event occurs and timer is decreasing. 0: do nothing,1: force low, 2: force high, 3: toggle + 12 + 2 + read-write + + + TZ1_A_OST_U + One-shot mode action on PWM1A when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + 14 + 2 + read-write + + + TZ1_B_CBC_D + Cycle-by-cycle mode action on PWM1B when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + 16 + 2 + read-write + + + TZ1_B_CBC_U + Cycle-by-cycle mode action on PWM1B when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + 18 + 2 + read-write + + + TZ1_B_OST_D + One-shot mode action on PWM1B when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + 20 + 2 + read-write + + + TZ1_B_OST_U + One-shot mode action on PWM1B when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + 22 + 2 + read-write + + + + + FH1_CFG1 + Software triggers for fault handler actions + 0xA4 + 0x20 + + + TZ1_CLR_OST + a rising edge will clear on going one-shot mode action + 0 + 1 + read-write + + + TZ1_CBCPULSE + cycle-by-cycle mode action refresh moment selection. When bit0 is set to 1: TEZ, when bit1 is set to 1:TEP + 1 + 2 + read-write + + + TZ1_FORCE_CBC + a toggle trigger a cycle-by-cycle mode action + 3 + 1 + read-write + + + TZ1_FORCE_OST + a toggle (software negate its value) triggers a one-shot mode action + 4 + 1 + read-write + + + + + FH1_STATUS + Status of fault events. + 0xA8 + 0x20 + + + TZ1_CBC_ON + Set and reset by hardware. If set, a cycle-by-cycle mode action is on going + 0 + 1 + read-only + + + TZ1_OST_ON + Set and reset by hardware. If set, an one-shot mode action is on going + 1 + 1 + read-only + + + + + GEN2_STMP_CFG + Transfer status and update method for time stamp registers A and B + 0xAC + 0x20 + + + CMPR2_A_UPMETHOD + Update method for PWM generator 2 time stamp A's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update. + 0 + 4 + read-write + + + CMPR2_B_UPMETHOD + Update method for PWM generator 2 time stamp B's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update. + 4 + 4 + read-write + + + CMPR2_A_SHDW_FULL + Set and reset by hardware. If set, PWM generator 2 time stamp A's shadow reg is filled and waiting to be transferred to A's active reg. If cleared, A's active reg has been updated with shadow register latest value + 8 + 1 + read-write + + + CMPR2_B_SHDW_FULL + Set and reset by hardware. If set, PWM generator 2 time stamp B's shadow reg is filled and waiting to be transferred to B's active reg. If cleared, B's active reg has been updated with shadow register latest value + 9 + 1 + read-write + + + + + GEN2_TSTMP_A + Shadow register for register A. + 0xB0 + 0x20 + + + CMPR2_A + PWM generator 2 time stamp A's shadow register + 0 + 16 + read-write + + + + + GEN2_TSTMP_B + Shadow register for register B. + 0xB4 + 0x20 + + + CMPR2_B + PWM generator 2 time stamp B's shadow register + 0 + 16 + read-write + + + + + GEN2_CFG0 + Fault event T0 and T1 handling + 0xB8 + 0x20 + + + GEN2_CFG_UPMETHOD + Update method for PWM generator 2's active register of configuration. 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1:sync;when bit3 is set to 1:disable the update. + 0 + 4 + read-write + + + GEN2_T0_SEL + Source selection for PWM generator 2 event_t0, take effect immediately, 0: fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none + 4 + 3 + read-write + + + GEN2_T1_SEL + Source selection for PWM generator 2 event_t1, take effect immediately, 0: fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none + 7 + 3 + read-write + + + + + GEN2_FORCE + Permissives to force PWM2A and PWM2B outputs by software + 0xBC + 0x20 + 0x00000020 + + + GEN2_CNTUFORCE_UPMETHOD + Updating method for continuous software force of PWM generator 2. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ,when bit1 is set to 1: TEP, when bit2 is set to 1: TEA, when bit3 is set to 1: TEB, when bit4 is set to 1: sync, when bit5 is set to 1: disable update. (TEA/B here and below means an event generated when the timer's value equals to that of register A/B.) + 0 + 6 + read-write + + + GEN2_A_CNTUFORCE_MODE + Continuous software force mode for PWM2A. 0: disabled, 1: low, 2: high, 3: disabled + 6 + 2 + read-write + + + GEN2_B_CNTUFORCE_MODE + Continuous software force mode for PWM2B. 0: disabled, 1: low, 2: high, 3: disabled + 8 + 2 + read-write + + + GEN2_A_NCIFORCE + Trigger of non-continuous immediate software-force event for PWM2A, a toggle will trigger a force event. + 10 + 1 + read-write + + + GEN2_A_NCIFORCE_MODE + non-continuous immediate software force mode for PWM2A, 0: disabled, 1: low, 2: high, 3: disabled + 11 + 2 + read-write + + + GEN2_B_NCIFORCE + Trigger of non-continuous immediate software-force event for PWM2B, a toggle will trigger a force event. + 13 + 1 + read-write + + + GEN2_B_NCIFORCE_MODE + non-continuous immediate software force mode for PWM2B, 0: disabled, 1: low, 2: high, 3: disabled + 14 + 2 + read-write + + + + + GEN2_A + Actions triggered by events on PWM2A + 0xC0 + 0x20 + + + UTEZ + Action on PWM2A triggered by event TEZ when timer increasing + 0 + 2 + read-write + + + UTEP + Action on PWM2A triggered by event TEP when timer increasing + 2 + 2 + read-write + + + UTEA + Action on PWM2A triggered by event TEA when timer increasing + 4 + 2 + read-write + + + UTEB + Action on PWM2A triggered by event TEB when timer increasing + 6 + 2 + read-write + + + UT0 + Action on PWM2A triggered by event_t0 when timer increasing + 8 + 2 + read-write + + + UT1 + Action on PWM2A triggered by event_t1 when timer increasing + 10 + 2 + read-write + + + DTEZ + Action on PWM2A triggered by event TEZ when timer decreasing + 12 + 2 + read-write + + + DTEP + Action on PWM2A triggered by event TEP when timer decreasing + 14 + 2 + read-write + + + DTEA + Action on PWM2A triggered by event TEA when timer decreasing + 16 + 2 + read-write + + + DTEB + Action on PWM2A triggered by event TEB when timer decreasing + 18 + 2 + read-write + + + DT0 + Action on PWM2A triggered by event_t0 when timer decreasing + 20 + 2 + read-write + + + DT1 + Action on PWM2A triggered by event_t1 when timer decreasing. 0: no change, 1: low, 2: high, 3: toggle + 22 + 2 + read-write + + + + + GEN2_B + Actions triggered by events on PWM2B + 0xC4 + 0x20 + + + UTEZ + Action on PWM2B triggered by event TEZ when timer increasing + 0 + 2 + read-write + + + UTEP + Action on PWM2B triggered by event TEP when timer increasing + 2 + 2 + read-write + + + UTEA + Action on PWM2B triggered by event TEA when timer increasing + 4 + 2 + read-write + + + UTEB + Action on PWM2B triggered by event TEB when timer increasing + 6 + 2 + read-write + + + UT0 + Action on PWM2B triggered by event_t0 when timer increasing + 8 + 2 + read-write + + + UT1 + Action on PWM2B triggered by event_t1 when timer increasing + 10 + 2 + read-write + + + DTEZ + Action on PWM2B triggered by event TEZ when timer decreasing + 12 + 2 + read-write + + + DTEP + Action on PWM2B triggered by event TEP when timer decreasing + 14 + 2 + read-write + + + DTEA + Action on PWM2B triggered by event TEA when timer decreasing + 16 + 2 + read-write + + + DTEB + Action on PWM2B triggered by event TEB when timer decreasing + 18 + 2 + read-write + + + DT0 + Action on PWM2B triggered by event_t0 when timer decreasing + 20 + 2 + read-write + + + DT1 + Action on PWM2B triggered by event_t1 when timer decreasing. 0: no change, 1: low, 2: high, 3: toggle + 22 + 2 + read-write + + + + + DT2_CFG + dead time type selection and configuration + 0xC8 + 0x20 + 0x00018000 + + + DB2_FED_UPMETHOD + Update method for FED (falling edge delay) active register. 0: immediate,when bit0 is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when bit3 is set to 1: disable the update + 0 + 4 + read-write + + + DB2_RED_UPMETHOD + Update method for RED (rising edge delay) active register. 0: immediate,when bit0 is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when bit3 is set to 1: disable the update + 4 + 4 + read-write + + + DB2_DEB_MODE + S8 in table, dual-edge B mode, 0: fed/red take effect on different path separately, 1: fed/red take effect on B path, A out is in bypass or dulpB mode + 8 + 1 + read-write + + + DB2_A_OUTSWAP + S6 in table + 9 + 1 + read-write + + + DB2_B_OUTSWAP + S7 in table + 10 + 1 + read-write + + + DB2_RED_INSEL + S4 in table + 11 + 1 + read-write + + + DB2_FED_INSEL + S5 in table + 12 + 1 + read-write + + + DB2_RED_OUTINVERT + S2 in table + 13 + 1 + read-write + + + DB2_FED_OUTINVERT + S3 in table + 14 + 1 + read-write + + + DB2_A_OUTBYPASS + S1 in table + 15 + 1 + read-write + + + DB2_B_OUTBYPASS + S0 in table + 16 + 1 + read-write + + + DB2_CLK_SEL + Dead time generator 2 clock selection. 0: PWM_clk, 1: PT_clk + 17 + 1 + read-write + + + + + DT2_FED_CFG + Shadow register for falling edge delay (FED). + 0xCC + 0x20 + + + DB2_FED + Shadow register for FED + 0 + 16 + read-write + + + + + DT2_RED_CFG + Shadow register for rising edge delay (RED). + 0xD0 + 0x20 + + + DB2_RED + Shadow register for RED + 0 + 16 + read-write + + + + + CARRIER2_CFG + Carrier enable and configuratoin + 0xD4 + 0x20 + + + CHOPPER2_EN + When set, carrier2 function is enabled. When cleared, carrier2 is bypassed + 0 + 1 + read-write + + + CHOPPER2_PRESCALE + PWM carrier2 clock (PC_clk) prescale value. Period of PC_clk = period of PWM_clk * (PWM_CARRIER0_PRESCALE + 1) + 1 + 4 + read-write + + + CHOPPER2_DUTY + carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8 + 5 + 3 + read-write + + + CHOPPER2_OSHTWTH + width of the first pulse in number of periods of the carrier + 8 + 4 + read-write + + + CHOPPER2_OUT_INVERT + when set, invert the output of PWM2A and PWM2B for this submodule + 12 + 1 + read-write + + + CHOPPER2_IN_INVERT + when set, invert the input of PWM2A and PWM2B for this submodule + 13 + 1 + read-write + + + + + FH2_CFG0 + Actions on PWM2A and PWM2B trip events + 0xD8 + 0x20 + + + TZ2_SW_CBC + Enable register for software force cycle-by-cycle mode action. 0: disable, 1: enable + 0 + 1 + read-write + + + TZ2_F2_CBC + event_f2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + 1 + 1 + read-write + + + TZ2_F1_CBC + event_f1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + 2 + 1 + read-write + + + TZ2_F0_CBC + event_f0 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + 3 + 1 + read-write + + + TZ2_SW_OST + Enable register for software force one-shot mode action. 0: disable, 1: enable + 4 + 1 + read-write + + + TZ2_F2_OST + event_f2 will trigger one-shot mode action. 0: disable, 1: enable + 5 + 1 + read-write + + + TZ2_F1_OST + event_f1 will trigger one-shot mode action. 0: disable, 1: enable + 6 + 1 + read-write + + + TZ2_F0_OST + event_f0 will trigger one-shot mode action. 0: disable, 1: enable + 7 + 1 + read-write + + + TZ2_A_CBC_D + Cycle-by-cycle mode action on PWM2A when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + 8 + 2 + read-write + + + TZ2_A_CBC_U + Cycle-by-cycle mode action on PWM2A when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + 10 + 2 + read-write + + + TZ2_A_OST_D + One-shot mode action on PWM2A when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + 12 + 2 + read-write + + + TZ2_A_OST_U + One-shot mode action on PWM2A when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + 14 + 2 + read-write + + + TZ2_B_CBC_D + Cycle-by-cycle mode action on PWM2B when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + 16 + 2 + read-write + + + TZ2_B_CBC_U + Cycle-by-cycle mode action on PWM2B when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + 18 + 2 + read-write + + + TZ2_B_OST_D + One-shot mode action on PWM2B when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + 20 + 2 + read-write + + + TZ2_B_OST_U + One-shot mode action on PWM2B when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + 22 + 2 + read-write + + + + + FH2_CFG1 + Software triggers for fault handler actions + 0xDC + 0x20 + + + TZ2_CLR_OST + a rising edge will clear on going one-shot mode action + 0 + 1 + read-write + + + TZ2_CBCPULSE + cycle-by-cycle mode action refresh moment selection. When bit0 is set to 1: TEZ, when bit1 is set to 1:TEP + 1 + 2 + read-write + + + TZ2_FORCE_CBC + a toggle trigger a cycle-by-cycle mode action + 3 + 1 + read-write + + + TZ2_FORCE_OST + a toggle (software negate its value) triggers a one-shot mode action + 4 + 1 + read-write + + + + + FH2_STATUS + Status of fault events. + 0xE0 + 0x20 + + + TZ2_CBC_ON + Set and reset by hardware. If set, a cycle-by-cycle mode action is on going + 0 + 1 + read-only + + + TZ2_OST_ON + Set and reset by hardware. If set, an one-shot mode action is on going + 1 + 1 + read-only + + + + + FAULT_DETECT + Fault detection configuration and status + 0xE4 + 0x20 + + + F0_EN + When set, event_f0 generation is enabled + 0 + 1 + read-write + + + F1_EN + When set, event_f1 generation is enabled + 1 + 1 + read-write + + + F2_EN + When set, event_f2 generation is enabled + 2 + 1 + read-write + + + F0_POLE + Set event_f0 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1: level high + 3 + 1 + read-write + + + F1_POLE + Set event_f1 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1: level high + 4 + 1 + read-write + + + F2_POLE + Set event_f2 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1: level high + 5 + 1 + read-write + + + EVENT_F0 + Set and reset by hardware. If set, event_f0 is on going + 6 + 1 + read-only + + + EVENT_F1 + Set and reset by hardware. If set, event_f1 is on going + 7 + 1 + read-only + + + EVENT_F2 + Set and reset by hardware. If set, event_f2 is on going + 8 + 1 + read-only + + + + + CAP_TIMER_CFG + Configure capture timer + 0xE8 + 0x20 + + + CAP_TIMER_EN + When set, capture timer incrementing under APB_clk is enabled. + 0 + 1 + read-write + + + CAP_SYNCI_EN + When set, capture timer sync is enabled. + 1 + 1 + read-write + + + CAP_SYNCI_SEL + capture module sync input selection. 0: none, 1: timer0 sync_out, 2: timer1 sync_out, 3: timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix + 2 + 3 + read-write + + + CAP_SYNC_SW + When reg_cap_synci_en is 1, write 1 will trigger a capture timer sync, capture timer is loaded with value in phase register. + 5 + 1 + write-only + + + + + CAP_TIMER_PHASE + Phase for capture timer sync + 0xEC + 0x20 + + + CAP_PHASE + Phase value for capture timer sync operation. + 0 + 32 + read-write + + + + + CAP_CH0_CFG + Capture channel 0 configuration and enable + 0xF0 + 0x20 + + + CAP0_EN + When set, capture on channel 0 is enabled + 0 + 1 + read-write + + + CAP0_MODE + Edge of capture on channel 0 after prescaling. When bit0 is set to 1: enable capture on the negative edge, When bit1 is set to 1: enable capture on the positive edge. + 1 + 2 + read-write + + + CAP0_PRESCALE + Value of prescaling on possitive edge of CAP0. Prescale value = PWM_CAP0_PRESCALE + 1 + 3 + 8 + read-write + + + CAP0_IN_INVERT + when set, CAP0 form GPIO matrix is inverted before prescale + 11 + 1 + read-write + + + CAP0_SW + Write 1 will trigger a software forced capture on channel 0 + 12 + 1 + write-only + + + + + CAP_CH1_CFG + Capture channel 1 configuration and enable + 0xF4 + 0x20 + + + CAP1_EN + When set, capture on channel 2 is enabled + 0 + 1 + read-write + + + CAP1_MODE + Edge of capture on channel 1 after prescaling. When bit0 is set to 1: enable capture on the negative edge, When bit1 is set to 1: enable capture on the positive edge. + 1 + 2 + read-write + + + CAP1_PRESCALE + Value of prescaling on possitive edge of CAP1. Prescale value = PWM_CAP1_PRESCALE + 1 + 3 + 8 + read-write + + + CAP1_IN_INVERT + when set, CAP1 form GPIO matrix is inverted before prescale + 11 + 1 + read-write + + + CAP1_SW + Write 1 will trigger a software forced capture on channel 1 + 12 + 1 + write-only + + + + + CAP_CH2_CFG + Capture channel 2 configuration and enable + 0xF8 + 0x20 + + + CAP2_EN + When set, capture on channel 2 is enabled + 0 + 1 + read-write + + + CAP2_MODE + Edge of capture on channel 2 after prescaling. When bit0 is set to 1: enable capture on the negative edge, When bit1 is set to 1: enable capture on the positive edge. + 1 + 2 + read-write + + + CAP2_PRESCALE + Value of prescaling on possitive edge of CAP2. Prescale value = PWM_CAP2_PRESCALE + 1 + 3 + 8 + read-write + + + CAP2_IN_INVERT + when set, CAP2 form GPIO matrix is inverted before prescale + 11 + 1 + read-write + + + CAP2_SW + Write 1 will trigger a software forced capture on channel 2 + 12 + 1 + write-only + + + + + CAP_CH0 + ch0 capture value status register + 0xFC + 0x20 + + + CAP0_VALUE + Value of last capture on channel 0 + 0 + 32 + read-only + + + + + CAP_CH1 + ch1 capture value status register + 0x100 + 0x20 + + + CAP1_VALUE + Value of last capture on channel 1 + 0 + 32 + read-only + + + + + CAP_CH2 + ch2 capture value status register + 0x104 + 0x20 + + + CAP2_VALUE + Value of last capture on channel 2 + 0 + 32 + read-only + + + + + CAP_STATUS + Edge of last capture trigger + 0x108 + 0x20 + + + CAP0_EDGE + Edge of last capture trigger on channel 0, 0: posedge, 1: negedge + 0 + 1 + read-only + + + CAP1_EDGE + Edge of last capture trigger on channel 1, 0: posedge, 1: negedge + 1 + 1 + read-only + + + CAP2_EDGE + Edge of last capture trigger on channel 2, 0: posedge, 1: negedge + 2 + 1 + read-only + + + + + UPDATE_CFG + Enable update. + 0x10C + 0x20 + 0x00000055 + + + GLOBAL_UP_EN + The global enable of update of all active registers in MCPWM module + 0 + 1 + read-write + + + GLOBAL_FORCE_UP + a toggle (software invert its value) will trigger a forced update of all active registers in MCPWM module + 1 + 1 + read-write + + + OP0_UP_EN + When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 0 are enabled + 2 + 1 + read-write + + + OP0_FORCE_UP + a toggle (software invert its value) will trigger a forced update of active registers in PWM operator 0 + 3 + 1 + read-write + + + OP1_UP_EN + When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 1 are enabled + 4 + 1 + read-write + + + OP1_FORCE_UP + a toggle (software invert its value) will trigger a forced update of active registers in PWM operator 1 + 5 + 1 + read-write + + + OP2_UP_EN + When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 2 are enabled + 6 + 1 + read-write + + + OP2_FORCE_UP + a toggle (software invert its value) will trigger a forced update of active registers in PWM operator 2 + 7 + 1 + read-write + + + + + INT_ENA + Interrupt enable bits + 0x110 + 0x20 + + + TIMER0_STOP_INT_ENA + The enable bit for the interrupt triggered when the timer 0 stops. + 0 + 1 + read-write + + + TIMER1_STOP_INT_ENA + The enable bit for the interrupt triggered when the timer 1 stops. + 1 + 1 + read-write + + + TIMER2_STOP_INT_ENA + The enable bit for the interrupt triggered when the timer 2 stops. + 2 + 1 + read-write + + + TIMER0_TEZ_INT_ENA + The enable bit for the interrupt triggered by a PWM timer 0 TEZ event. + 3 + 1 + read-write + + + TIMER1_TEZ_INT_ENA + The enable bit for the interrupt triggered by a PWM timer 1 TEZ event. + 4 + 1 + read-write + + + TIMER2_TEZ_INT_ENA + The enable bit for the interrupt triggered by a PWM timer 2 TEZ event. + 5 + 1 + read-write + + + TIMER0_TEP_INT_ENA + The enable bit for the interrupt triggered by a PWM timer 0 TEP event. + 6 + 1 + read-write + + + TIMER1_TEP_INT_ENA + The enable bit for the interrupt triggered by a PWM timer 1 TEP event. + 7 + 1 + read-write + + + TIMER2_TEP_INT_ENA + The enable bit for the interrupt triggered by a PWM timer 2 TEP event. + 8 + 1 + read-write + + + FAULT0_INT_ENA + The enable bit for the interrupt triggered when event_f0 starts. + 9 + 1 + read-write + + + FAULT1_INT_ENA + The enable bit for the interrupt triggered when event_f1 starts. + 10 + 1 + read-write + + + FAULT2_INT_ENA + The enable bit for the interrupt triggered when event_f2 starts. + 11 + 1 + read-write + + + FAULT0_CLR_INT_ENA + The enable bit for the interrupt triggered when event_f0 ends. + 12 + 1 + read-write + + + FAULT1_CLR_INT_ENA + The enable bit for the interrupt triggered when event_f1 ends. + 13 + 1 + read-write + + + FAULT2_CLR_INT_ENA + The enable bit for the interrupt triggered when event_f2 ends. + 14 + 1 + read-write + + + CMPR0_TEA_INT_ENA + The enable bit for the interrupt triggered by a PWM operator 0 TEA event + 15 + 1 + read-write + + + CMPR1_TEA_INT_ENA + The enable bit for the interrupt triggered by a PWM operator 1 TEA event + 16 + 1 + read-write + + + CMPR2_TEA_INT_ENA + The enable bit for the interrupt triggered by a PWM operator 2 TEA event + 17 + 1 + read-write + + + CMPR0_TEB_INT_ENA + The enable bit for the interrupt triggered by a PWM operator 0 TEB event + 18 + 1 + read-write + + + CMPR1_TEB_INT_ENA + The enable bit for the interrupt triggered by a PWM operator 1 TEB event + 19 + 1 + read-write + + + CMPR2_TEB_INT_ENA + The enable bit for the interrupt triggered by a PWM operator 2 TEB event + 20 + 1 + read-write + + + TZ0_CBC_INT_ENA + The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0. + 21 + 1 + read-write + + + TZ1_CBC_INT_ENA + The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1. + 22 + 1 + read-write + + + TZ2_CBC_INT_ENA + The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2. + 23 + 1 + read-write + + + TZ0_OST_INT_ENA + The enable bit for the interrupt triggered by a one-shot mode action on PWM0. + 24 + 1 + read-write + + + TZ1_OST_INT_ENA + The enable bit for the interrupt triggered by a one-shot mode action on PWM1. + 25 + 1 + read-write + + + TZ2_OST_INT_ENA + The enable bit for the interrupt triggered by a one-shot mode action on PWM2. + 26 + 1 + read-write + + + CAP0_INT_ENA + The enable bit for the interrupt triggered by capture on channel 0. + 27 + 1 + read-write + + + CAP1_INT_ENA + The enable bit for the interrupt triggered by capture on channel 1. + 28 + 1 + read-write + + + CAP2_INT_ENA + The enable bit for the interrupt triggered by capture on channel 2. + 29 + 1 + read-write + + + + + INT_RAW + Raw interrupt status + 0x114 + 0x20 + + + TIMER0_STOP_INT_RAW + The raw status bit for the interrupt triggered when the timer 0 stops. + 0 + 1 + read-only + + + TIMER1_STOP_INT_RAW + The raw status bit for the interrupt triggered when the timer 1 stops. + 1 + 1 + read-only + + + TIMER2_STOP_INT_RAW + The raw status bit for the interrupt triggered when the timer 2 stops. + 2 + 1 + read-only + + + TIMER0_TEZ_INT_RAW + The raw status bit for the interrupt triggered by a PWM timer 0 TEZ event. + 3 + 1 + read-only + + + TIMER1_TEZ_INT_RAW + The raw status bit for the interrupt triggered by a PWM timer 1 TEZ event. + 4 + 1 + read-only + + + TIMER2_TEZ_INT_RAW + The raw status bit for the interrupt triggered by a PWM timer 2 TEZ event. + 5 + 1 + read-only + + + TIMER0_TEP_INT_RAW + The raw status bit for the interrupt triggered by a PWM timer 0 TEP event. + 6 + 1 + read-only + + + TIMER1_TEP_INT_RAW + The raw status bit for the interrupt triggered by a PWM timer 1 TEP event. + 7 + 1 + read-only + + + TIMER2_TEP_INT_RAW + The raw status bit for the interrupt triggered by a PWM timer 2 TEP event. + 8 + 1 + read-only + + + FAULT0_INT_RAW + The raw status bit for the interrupt triggered when event_f0 starts. + 9 + 1 + read-only + + + FAULT1_INT_RAW + The raw status bit for the interrupt triggered when event_f1 starts. + 10 + 1 + read-only + + + FAULT2_INT_RAW + The raw status bit for the interrupt triggered when event_f2 starts. + 11 + 1 + read-only + + + FAULT0_CLR_INT_RAW + The raw status bit for the interrupt triggered when event_f0 ends. + 12 + 1 + read-only + + + FAULT1_CLR_INT_RAW + The raw status bit for the interrupt triggered when event_f1 ends. + 13 + 1 + read-only + + + FAULT2_CLR_INT_RAW + The raw status bit for the interrupt triggered when event_f2 ends. + 14 + 1 + read-only + + + CMPR0_TEA_INT_RAW + The raw status bit for the interrupt triggered by a PWM operator 0 TEA event + 15 + 1 + read-only + + + CMPR1_TEA_INT_RAW + The raw status bit for the interrupt triggered by a PWM operator 1 TEA event + 16 + 1 + read-only + + + CMPR2_TEA_INT_RAW + The raw status bit for the interrupt triggered by a PWM operator 2 TEA event + 17 + 1 + read-only + + + CMPR0_TEB_INT_RAW + The raw status bit for the interrupt triggered by a PWM operator 0 TEB event + 18 + 1 + read-only + + + CMPR1_TEB_INT_RAW + The raw status bit for the interrupt triggered by a PWM operator 1 TEB event + 19 + 1 + read-only + + + CMPR2_TEB_INT_RAW + The raw status bit for the interrupt triggered by a PWM operator 2 TEB event + 20 + 1 + read-only + + + TZ0_CBC_INT_RAW + The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0. + 21 + 1 + read-only + + + TZ1_CBC_INT_RAW + The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1. + 22 + 1 + read-only + + + TZ2_CBC_INT_RAW + The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2. + 23 + 1 + read-only + + + TZ0_OST_INT_RAW + The raw status bit for the interrupt triggered by a one-shot mode action on PWM0. + 24 + 1 + read-only + + + TZ1_OST_INT_RAW + The raw status bit for the interrupt triggered by a one-shot mode action on PWM1. + 25 + 1 + read-only + + + TZ2_OST_INT_RAW + The raw status bit for the interrupt triggered by a one-shot mode action on PWM2. + 26 + 1 + read-only + + + CAP0_INT_RAW + The raw status bit for the interrupt triggered by capture on channel 0. + 27 + 1 + read-only + + + CAP1_INT_RAW + The raw status bit for the interrupt triggered by capture on channel 1. + 28 + 1 + read-only + + + CAP2_INT_RAW + The raw status bit for the interrupt triggered by capture on channel 2. + 29 + 1 + read-only + + + + + INT_ST + Masked interrupt status + 0x118 + 0x20 + + + TIMER0_STOP_INT_ST + The masked status bit for the interrupt triggered when the timer 0 stops. + 0 + 1 + read-only + + + TIMER1_STOP_INT_ST + The masked status bit for the interrupt triggered when the timer 1 stops. + 1 + 1 + read-only + + + TIMER2_STOP_INT_ST + The masked status bit for the interrupt triggered when the timer 2 stops. + 2 + 1 + read-only + + + TIMER0_TEZ_INT_ST + The masked status bit for the interrupt triggered by a PWM timer 0 TEZ event. + 3 + 1 + read-only + + + TIMER1_TEZ_INT_ST + The masked status bit for the interrupt triggered by a PWM timer 1 TEZ event. + 4 + 1 + read-only + + + TIMER2_TEZ_INT_ST + The masked status bit for the interrupt triggered by a PWM timer 2 TEZ event. + 5 + 1 + read-only + + + TIMER0_TEP_INT_ST + The masked status bit for the interrupt triggered by a PWM timer 0 TEP event. + 6 + 1 + read-only + + + TIMER1_TEP_INT_ST + The masked status bit for the interrupt triggered by a PWM timer 1 TEP event. + 7 + 1 + read-only + + + TIMER2_TEP_INT_ST + The masked status bit for the interrupt triggered by a PWM timer 2 TEP event. + 8 + 1 + read-only + + + FAULT0_INT_ST + The masked status bit for the interrupt triggered when event_f0 starts. + 9 + 1 + read-only + + + FAULT1_INT_ST + The masked status bit for the interrupt triggered when event_f1 starts. + 10 + 1 + read-only + + + FAULT2_INT_ST + The masked status bit for the interrupt triggered when event_f2 starts. + 11 + 1 + read-only + + + FAULT0_CLR_INT_ST + The masked status bit for the interrupt triggered when event_f0 ends. + 12 + 1 + read-only + + + FAULT1_CLR_INT_ST + The masked status bit for the interrupt triggered when event_f1 ends. + 13 + 1 + read-only + + + FAULT2_CLR_INT_ST + The masked status bit for the interrupt triggered when event_f2 ends. + 14 + 1 + read-only + + + CMPR0_TEA_INT_ST + The masked status bit for the interrupt triggered by a PWM operator 0 TEA event + 15 + 1 + read-only + + + CMPR1_TEA_INT_ST + The masked status bit for the interrupt triggered by a PWM operator 1 TEA event + 16 + 1 + read-only + + + CMPR2_TEA_INT_ST + The masked status bit for the interrupt triggered by a PWM operator 2 TEA event + 17 + 1 + read-only + + + CMPR0_TEB_INT_ST + The masked status bit for the interrupt triggered by a PWM operator 0 TEB event + 18 + 1 + read-only + + + CMPR1_TEB_INT_ST + The masked status bit for the interrupt triggered by a PWM operator 1 TEB event + 19 + 1 + read-only + + + CMPR2_TEB_INT_ST + The masked status bit for the interrupt triggered by a PWM operator 2 TEB event + 20 + 1 + read-only + + + TZ0_CBC_INT_ST + The masked status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0. + 21 + 1 + read-only + + + TZ1_CBC_INT_ST + The masked status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1. + 22 + 1 + read-only + + + TZ2_CBC_INT_ST + The masked status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2. + 23 + 1 + read-only + + + TZ0_OST_INT_ST + The masked status bit for the interrupt triggered by a one-shot mode action on PWM0. + 24 + 1 + read-only + + + TZ1_OST_INT_ST + The masked status bit for the interrupt triggered by a one-shot mode action on PWM1. + 25 + 1 + read-only + + + TZ2_OST_INT_ST + The masked status bit for the interrupt triggered by a one-shot mode action on PWM2. + 26 + 1 + read-only + + + CAP0_INT_ST + The masked status bit for the interrupt triggered by capture on channel 0. + 27 + 1 + read-only + + + CAP1_INT_ST + The masked status bit for the interrupt triggered by capture on channel 1. + 28 + 1 + read-only + + + CAP2_INT_ST + The masked status bit for the interrupt triggered by capture on channel 2. + 29 + 1 + read-only + + + + + INT_CLR + Interrupt clear bits + 0x11C + 0x20 + + + TIMER0_STOP_INT_CLR + Set this bit to clear the interrupt triggered when the timer 0 stops. + 0 + 1 + write-only + + + TIMER1_STOP_INT_CLR + Set this bit to clear the interrupt triggered when the timer 1 stops. + 1 + 1 + write-only + + + TIMER2_STOP_INT_CLR + Set this bit to clear the interrupt triggered when the timer 2 stops. + 2 + 1 + write-only + + + TIMER0_TEZ_INT_CLR + Set this bit to clear the interrupt triggered by a PWM timer 0 TEZ event. + 3 + 1 + write-only + + + TIMER1_TEZ_INT_CLR + Set this bit to clear the interrupt triggered by a PWM timer 1 TEZ event. + 4 + 1 + write-only + + + TIMER2_TEZ_INT_CLR + Set this bit to clear the interrupt triggered by a PWM timer 2 TEZ event. + 5 + 1 + write-only + + + TIMER0_TEP_INT_CLR + Set this bit to clear the interrupt triggered by a PWM timer 0 TEP event. + 6 + 1 + write-only + + + TIMER1_TEP_INT_CLR + Set this bit to clear the interrupt triggered by a PWM timer 1 TEP event. + 7 + 1 + write-only + + + TIMER2_TEP_INT_CLR + Set this bit to clear the interrupt triggered by a PWM timer 2 TEP event. + 8 + 1 + write-only + + + FAULT0_INT_CLR + Set this bit to clear the interrupt triggered when event_f0 starts. + 9 + 1 + write-only + + + FAULT1_INT_CLR + Set this bit to clear the interrupt triggered when event_f1 starts. + 10 + 1 + write-only + + + FAULT2_INT_CLR + Set this bit to clear the interrupt triggered when event_f2 starts. + 11 + 1 + write-only + + + FAULT0_CLR_INT_CLR + Set this bit to clear the interrupt triggered when event_f0 ends. + 12 + 1 + write-only + + + FAULT1_CLR_INT_CLR + Set this bit to clear the interrupt triggered when event_f1 ends. + 13 + 1 + write-only + + + FAULT2_CLR_INT_CLR + Set this bit to clear the interrupt triggered when event_f2 ends. + 14 + 1 + write-only + + + CMPR0_TEA_INT_CLR + Set this bit to clear the interrupt triggered by a PWM operator 0 TEA event + 15 + 1 + write-only + + + CMPR1_TEA_INT_CLR + Set this bit to clear the interrupt triggered by a PWM operator 1 TEA event + 16 + 1 + write-only + + + CMPR2_TEA_INT_CLR + Set this bit to clear the interrupt triggered by a PWM operator 2 TEA event + 17 + 1 + write-only + + + CMPR0_TEB_INT_CLR + Set this bit to clear the interrupt triggered by a PWM operator 0 TEB event + 18 + 1 + write-only + + + CMPR1_TEB_INT_CLR + Set this bit to clear the interrupt triggered by a PWM operator 1 TEB event + 19 + 1 + write-only + + + CMPR2_TEB_INT_CLR + Set this bit to clear the interrupt triggered by a PWM operator 2 TEB event + 20 + 1 + write-only + + + TZ0_CBC_INT_CLR + Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on PWM0. + 21 + 1 + write-only + + + TZ1_CBC_INT_CLR + Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on PWM1. + 22 + 1 + write-only + + + TZ2_CBC_INT_CLR + Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on PWM2. + 23 + 1 + write-only + + + TZ0_OST_INT_CLR + Set this bit to clear the interrupt triggered by a one-shot mode action on PWM0. + 24 + 1 + write-only + + + TZ1_OST_INT_CLR + Set this bit to clear the interrupt triggered by a one-shot mode action on PWM1. + 25 + 1 + write-only + + + TZ2_OST_INT_CLR + Set this bit to clear the interrupt triggered by a one-shot mode action on PWM2. + 26 + 1 + write-only + + + CAP0_INT_CLR + Set this bit to clear the interrupt triggered by capture on channel 0. + 27 + 1 + write-only + + + CAP1_INT_CLR + Set this bit to clear the interrupt triggered by capture on channel 1. + 28 + 1 + write-only + + + CAP2_INT_CLR + Set this bit to clear the interrupt triggered by capture on channel 2. + 29 + 1 + write-only + + + + + EVT_EN + MCPWM event enable register + 0x120 + 0x20 + + + EVT_TIMER0_STOP_EN + set this bit high to enable timer0 stop event generate + 0 + 1 + read-write + + + EVT_TIMER1_STOP_EN + set this bit high to enable timer1 stop event generate + 1 + 1 + read-write + + + EVT_TIMER2_STOP_EN + set this bit high to enable timer2 stop event generate + 2 + 1 + read-write + + + EVT_TIMER0_TEZ_EN + set this bit high to enable timer0 equal zero event generate + 3 + 1 + read-write + + + EVT_TIMER1_TEZ_EN + set this bit high to enable timer1 equal zero event generate + 4 + 1 + read-write + + + EVT_TIMER2_TEZ_EN + set this bit high to enable timer2 equal zero event generate + 5 + 1 + read-write + + + EVT_TIMER0_TEP_EN + set this bit high to enable timer0 equal period event generate + 6 + 1 + read-write + + + EVT_TIMER1_TEP_EN + set this bit high to enable timer1 equal period event generate + 7 + 1 + read-write + + + EVT_TIMER2_TEP_EN + set this bit high to enable timer2 equal period event generate + 8 + 1 + read-write + + + EVT_OP0_TEA_EN + set this bit high to enable PWM generator0 timer equal a event generate + 9 + 1 + read-write + + + EVT_OP1_TEA_EN + set this bit high to enable PWM generator1 timer equal a event generate + 10 + 1 + read-write + + + EVT_OP2_TEA_EN + set this bit high to enable PWM generator2 timer equal a event generate + 11 + 1 + read-write + + + EVT_OP0_TEB_EN + set this bit high to enable PWM generator0 timer equal b event generate + 12 + 1 + read-write + + + EVT_OP1_TEB_EN + set this bit high to enable PWM generator1 timer equal b event generate + 13 + 1 + read-write + + + EVT_OP2_TEB_EN + set this bit high to enable PWM generator2 timer equal b event generate + 14 + 1 + read-write + + + EVT_F0_EN + set this bit high to enable fault0 event generate + 15 + 1 + read-write + + + EVT_F1_EN + set this bit high to enable fault1 event generate + 16 + 1 + read-write + + + EVT_F2_EN + set this bit high to enable fault2 event generate + 17 + 1 + read-write + + + EVT_F0_CLR_EN + set this bit high to enable fault0 clear event generate + 18 + 1 + read-write + + + EVT_F1_CLR_EN + set this bit high to enable fault1 clear event generate + 19 + 1 + read-write + + + EVT_F2_CLR_EN + set this bit high to enable fault2 clear event generate + 20 + 1 + read-write + + + EVT_TZ0_CBC_EN + set this bit high to enable cycle by cycle trip0 event generate + 21 + 1 + read-write + + + EVT_TZ1_CBC_EN + set this bit high to enable cycle by cycle trip1 event generate + 22 + 1 + read-write + + + EVT_TZ2_CBC_EN + set this bit high to enable cycle by cycle trip2 event generate + 23 + 1 + read-write + + + EVT_TZ0_OST_EN + set this bit high to enable one shot trip0 event generate + 24 + 1 + read-write + + + EVT_TZ1_OST_EN + set this bit high to enable one shot trip1 event generate + 25 + 1 + read-write + + + EVT_TZ2_OST_EN + set this bit high to enable one shot trip2 event generate + 26 + 1 + read-write + + + EVT_CAP0_EN + set this bit high to enable capture0 event generate + 27 + 1 + read-write + + + EVT_CAP1_EN + set this bit high to enable capture1 event generate + 28 + 1 + read-write + + + EVT_CAP2_EN + set this bit high to enable capture2 event generate + 29 + 1 + read-write + + + + + TASK_EN + MCPWM task enable register + 0x124 + 0x20 + + + TASK_CMPR0_A_UP_EN + set this bit high to enable PWM generator0 timer stamp A's shadow register update task receive + 0 + 1 + read-write + + + TASK_CMPR1_A_UP_EN + set this bit high to enable PWM generator1 timer stamp A's shadow register update task receive + 1 + 1 + read-write + + + TASK_CMPR2_A_UP_EN + set this bit high to enable PWM generator2 timer stamp A's shadow register update task receive + 2 + 1 + read-write + + + TASK_CMPR0_B_UP_EN + set this bit high to enable PWM generator0 timer stamp B's shadow register update task receive + 3 + 1 + read-write + + + TASK_CMPR1_B_UP_EN + set this bit high to enable PWM generator1 timer stamp B's shadow register update task receive + 4 + 1 + read-write + + + TASK_CMPR2_B_UP_EN + set this bit high to enable PWM generator2 timer stamp B's shadow register update task receive + 5 + 1 + read-write + + + TASK_GEN_STOP_EN + set this bit high to enable all PWM generate stop task receive + 6 + 1 + read-write + + + TASK_TIMER0_SYNC_EN + set this bit high to enable timer0 sync task receive + 7 + 1 + read-write + + + TASK_TIMER1_SYNC_EN + set this bit high to enable timer1 sync task receive + 8 + 1 + read-write + + + TASK_TIMER2_SYNC_EN + set this bit high to enable timer2 sync task receive + 9 + 1 + read-write + + + TASK_TIMER0_PERIOD_UP_EN + set this bit high to enable timer0 period update task receive + 10 + 1 + read-write + + + TASK_TIMER1_PERIOD_UP_EN + set this bit high to enable timer1 period update task receive + 11 + 1 + read-write + + + TASK_TIMER2_PERIOD_UP_EN + set this bit high to enable timer2 period update task receive + 12 + 1 + read-write + + + TASK_TZ0_OST_EN + set this bit high to enable one shot trip0 task receive + 13 + 1 + read-write + + + TASK_TZ1_OST_EN + set this bit high to enable one shot trip1 task receive + 14 + 1 + read-write + + + TASK_TZ2_OST_EN + set this bit high to enable one shot trip2 task receive + 15 + 1 + read-write + + + TASK_CLR0_OST_EN + set this bit high to enable one shot trip0 clear task receive + 16 + 1 + read-write + + + TASK_CLR1_OST_EN + set this bit high to enable one shot trip1 clear task receive + 17 + 1 + read-write + + + TASK_CLR2_OST_EN + set this bit high to enable one shot trip2 clear task receive + 18 + 1 + read-write + + + TASK_CAP0_EN + set this bit high to enable capture0 task receive + 19 + 1 + read-write + + + TASK_CAP1_EN + set this bit high to enable capture1 task receive + 20 + 1 + read-write + + + TASK_CAP2_EN + set this bit high to enable capture2 task receive + 21 + 1 + read-write + + + + + CLK + MCPWM APB configuration register + 0x128 + 0x20 + + + EN + Force clock on for this register file + 0 + 1 + read-write + + + + + VERSION + Version register. + 0x12C + 0x20 + 0x02201240 + + + DATE + Version of this register file + 0 + 28 + read-write + + + + + + + MEM_MONITOR + Peripheral MEM_MONITOR + MEM_MONITOR + 0x60092000 + + 0x0 + 0x30 + registers + + + + LOG_SETTING + log config regsiter + 0x0 + 0x20 + 0x00000080 + + + LOG_ENA + enable bus log. BIT0: hp-cpu, BIT1: lp-cpu, BIT2: DMA.823 don't support lp-cpu + 0 + 3 + read-write + + + LOG_MODE + This field must be onehot. 4'b0001 : WR monitor, 4'b0010: WORD monitor, 4'b0100: HALFWORD monitor, 4'b1000: BYTE monitor. + 3 + 4 + read-write + + + LOG_MEM_LOOP_ENABLE + Set 1 enable mem_loop, it will loop write at the range of MEM_START and MEM_END + 7 + 1 + read-write + + + + + LOG_CHECK_DATA + check data regsiter + 0x4 + 0x20 + + + LOG_CHECK_DATA + The special check data, when write this special data, it will trigger logging. + 0 + 32 + read-write + + + + + LOG_DATA_MASK + check data mask register + 0x8 + 0x20 + + + LOG_DATA_MASK + byte mask enable, BIT0 mask the first byte of MEM_MONITOR_LOG_CHECK_DATA, and BIT1 mask second byte, and so on. + 0 + 4 + read-write + + + + + LOG_MIN + log boundary regsiter + 0xC + 0x20 + + + LOG_MIN + the min address of log range + 0 + 32 + read-write + + + + + LOG_MAX + log boundary regsiter + 0x10 + 0x20 + + + LOG_MAX + the max address of log range + 0 + 32 + read-write + + + + + LOG_MEM_START + log message store range register + 0x14 + 0x20 + + + LOG_MEM_START + the start address of writing logging message + 0 + 32 + read-write + + + + + LOG_MEM_END + log message store range register + 0x18 + 0x20 + + + LOG_MEM_END + the end address of writing logging message + 0 + 32 + read-write + + + + + LOG_MEM_CURRENT_ADDR + current writing address. + 0x1C + 0x20 + + + LOG_MEM_CURRENT_ADDR + means next writing address + 0 + 32 + read-only + + + + + LOG_MEM_ADDR_UPDATE + writing address update + 0x20 + 0x20 + + + LOG_MEM_ADDR_UPDATE + Set 1 to updata MEM_MONITOR_LOG_MEM_CURRENT_ADDR, when set 1, MEM_MONITOR_LOG_MEM_CURRENT_ADDR will update to MEM_MONITOR_LOG_MEM_START + 0 + 1 + write-only + + + + + LOG_MEM_FULL_FLAG + full flag status register + 0x24 + 0x20 + + + LOG_MEM_FULL_FLAG + 1 means memory write loop at least one time at the range of MEM_START and MEM_END + 0 + 1 + read-only + + + CLR_LOG_MEM_FULL_FLAG + Set 1 to clr MEM_MONITOR_LOG_MEM_FULL_FLAG + 1 + 1 + write-only + + + + + CLOCK_GATE + clock gate force on register + 0x28 + 0x20 + + + CLK_EN + Set 1 to force on the clk of mem_monitor register + 0 + 1 + read-write + + + + + DATE + version register + 0x3FC + 0x20 + 0x02202140 + + + DATE + version register + 0 + 28 + read-write + + + + + + + OTP_DEBUG + Peripheral OTP_DEBUG + OTP_DEBUG + 0x600B3C00 + + 0x0 + 0x210 + registers + + + + WR_DIS + Otp debuger block0 data register1. + 0x0 + 0x20 + + + BLOCK0_WR_DIS + Otp block0 write disable data. + 0 + 32 + read-only + + + + + BLK0_BACKUP1_W1 + Otp debuger block0 data register2. + 0x4 + 0x20 + + + OTP_BEBUG_BLOCK0_BACKUP1_W1 + Otp block0 backup1 word1 data. + 0 + 32 + read-only + + + + + BLK0_BACKUP1_W2 + Otp debuger block0 data register3. + 0x8 + 0x20 + + + OTP_BEBUG_BLOCK0_BACKUP1_W2 + Otp block0 backup1 word2 data. + 0 + 32 + read-only + + + + + BLK0_BACKUP1_W3 + Otp debuger block0 data register4. + 0xC + 0x20 + + + OTP_BEBUG_BLOCK0_BACKUP1_W3 + Otp block0 backup1 word3 data. + 0 + 32 + read-only + + + + + BLK0_BACKUP1_W4 + Otp debuger block0 data register5. + 0x10 + 0x20 + + + OTP_BEBUG_BLOCK0_BACKUP1_W4 + Otp block0 backup1 word4 data. + 0 + 32 + read-only + + + + + BLK0_BACKUP1_W5 + Otp debuger block0 data register6. + 0x14 + 0x20 + + + OTP_BEBUG_BLOCK0_BACKUP1_W5 + Otp block0 backup1 word5 data. + 0 + 32 + read-only + + + + + BLK0_BACKUP2_W1 + Otp debuger block0 data register7. + 0x18 + 0x20 + + + OTP_BEBUG_BLOCK0_BACKUP2_W1 + Otp block0 backup2 word1 data. + 0 + 32 + read-only + + + + + BLK0_BACKUP2_W2 + Otp debuger block0 data register8. + 0x1C + 0x20 + + + OTP_BEBUG_BLOCK0_BACKUP2_W2 + Otp block0 backup2 word2 data. + 0 + 32 + read-only + + + + + BLK0_BACKUP2_W3 + Otp debuger block0 data register9. + 0x20 + 0x20 + + + OTP_BEBUG_BLOCK0_BACKUP2_W3 + Otp block0 backup2 word3 data. + 0 + 32 + read-only + + + + + BLK0_BACKUP2_W4 + Otp debuger block0 data register10. + 0x24 + 0x20 + + + OTP_BEBUG_BLOCK0_BACKUP2_W4 + Otp block0 backup2 word4 data. + 0 + 32 + read-only + + + + + BLK0_BACKUP2_W5 + Otp debuger block0 data register11. + 0x28 + 0x20 + + + OTP_BEBUG_BLOCK0_BACKUP2_W5 + Otp block0 backup2 word5 data. + 0 + 32 + read-only + + + + + BLK0_BACKUP3_W1 + Otp debuger block0 data register12. + 0x2C + 0x20 + + + OTP_BEBUG_BLOCK0_BACKUP3_W1 + Otp block0 backup3 word1 data. + 0 + 32 + read-only + + + + + BLK0_BACKUP3_W2 + Otp debuger block0 data register13. + 0x30 + 0x20 + + + OTP_BEBUG_BLOCK0_BACKUP3_W2 + Otp block0 backup3 word2 data. + 0 + 32 + read-only + + + + + BLK0_BACKUP3_W3 + Otp debuger block0 data register14. + 0x34 + 0x20 + + + OTP_BEBUG_BLOCK0_BACKUP3_W3 + Otp block0 backup3 word3 data. + 0 + 32 + read-only + + + + + BLK0_BACKUP3_W4 + Otp debuger block0 data register15. + 0x38 + 0x20 + + + OTP_BEBUG_BLOCK0_BACKUP3_W4 + Otp block0 backup3 word4 data. + 0 + 32 + read-only + + + + + BLK0_BACKUP3_W5 + Otp debuger block0 data register16. + 0x3C + 0x20 + + + OTP_BEBUG_BLOCK0_BACKUP3_W5 + Otp block0 backup3 word5 data. + 0 + 32 + read-only + + + + + BLK0_BACKUP4_W1 + Otp debuger block0 data register17. + 0x40 + 0x20 + + + OTP_BEBUG_BLOCK0_BACKUP4_W1 + Otp block0 backup4 word1 data. + 0 + 32 + read-only + + + + + BLK0_BACKUP4_W2 + Otp debuger block0 data register18. + 0x44 + 0x20 + + + OTP_BEBUG_BLOCK0_BACKUP4_W2 + Otp block0 backup4 word2 data. + 0 + 32 + read-only + + + + + BLK0_BACKUP4_W3 + Otp debuger block0 data register19. + 0x48 + 0x20 + + + OTP_BEBUG_BLOCK0_BACKUP4_W3 + Otp block0 backup4 word3 data. + 0 + 32 + read-only + + + + + BLK0_BACKUP4_W4 + Otp debuger block0 data register20. + 0x4C + 0x20 + + + OTP_BEBUG_BLOCK0_BACKUP4_W4 + Otp block0 backup4 word4 data. + 0 + 32 + read-only + + + + + BLK0_BACKUP4_W5 + Otp debuger block0 data register21. + 0x50 + 0x20 + + + OTP_BEBUG_BLOCK0_BACKUP4_W5 + Otp block0 backup4 word5 data. + 0 + 32 + read-only + + + + + BLK1_W1 + Otp debuger block1 data register1. + 0x54 + 0x20 + + + BLOCK1_W1 + Otp block1 word1 data. + 0 + 32 + read-only + + + + + BLK1_W2 + Otp debuger block1 data register2. + 0x58 + 0x20 + + + BLOCK1_W2 + Otp block1 word2 data. + 0 + 32 + read-only + + + + + BLK1_W3 + Otp debuger block1 data register3. + 0x5C + 0x20 + + + BLOCK1_W3 + Otp block1 word3 data. + 0 + 32 + read-only + + + + + BLK1_W4 + Otp debuger block1 data register4. + 0x60 + 0x20 + + + BLOCK1_W4 + Otp block1 word4 data. + 0 + 32 + read-only + + + + + BLK1_W5 + Otp debuger block1 data register5. + 0x64 + 0x20 + + + BLOCK1_W5 + Otp block1 word5 data. + 0 + 32 + read-only + + + + + BLK1_W6 + Otp debuger block1 data register6. + 0x68 + 0x20 + + + BLOCK1_W6 + Otp block1 word6 data. + 0 + 32 + read-only + + + + + BLK1_W7 + Otp debuger block1 data register7. + 0x6C + 0x20 + + + BLOCK1_W7 + Otp block1 word7 data. + 0 + 32 + read-only + + + + + BLK1_W8 + Otp debuger block1 data register8. + 0x70 + 0x20 + + + BLOCK1_W8 + Otp block1 word8 data. + 0 + 32 + read-only + + + + + BLK1_W9 + Otp debuger block1 data register9. + 0x74 + 0x20 + + + BLOCK1_W9 + Otp block1 word9 data. + 0 + 32 + read-only + + + + + BLK2_W1 + Otp debuger block2 data register1. + 0x78 + 0x20 + + + BLOCK2_W1 + Otp block2 word1 data. + 0 + 32 + read-only + + + + + BLK2_W2 + Otp debuger block2 data register2. + 0x7C + 0x20 + + + BLOCK2_W2 + Otp block2 word2 data. + 0 + 32 + read-only + + + + + BLK2_W3 + Otp debuger block2 data register3. + 0x80 + 0x20 + + + BLOCK2_W3 + Otp block2 word3 data. + 0 + 32 + read-only + + + + + BLK2_W4 + Otp debuger block2 data register4. + 0x84 + 0x20 + + + BLOCK2_W4 + Otp block2 word4 data. + 0 + 32 + read-only + + + + + BLK2_W5 + Otp debuger block2 data register5. + 0x88 + 0x20 + + + BLOCK2_W5 + Otp block2 word5 data. + 0 + 32 + read-only + + + + + BLK2_W6 + Otp debuger block2 data register6. + 0x8C + 0x20 + + + BLOCK2_W6 + Otp block2 word6 data. + 0 + 32 + read-only + + + + + BLK2_W7 + Otp debuger block2 data register7. + 0x90 + 0x20 + + + BLOCK2_W7 + Otp block2 word7 data. + 0 + 32 + read-only + + + + + BLK2_W8 + Otp debuger block2 data register8. + 0x94 + 0x20 + + + BLOCK2_W8 + Otp block2 word8 data. + 0 + 32 + read-only + + + + + BLK2_W9 + Otp debuger block2 data register9. + 0x98 + 0x20 + + + BLOCK2_W9 + Otp block2 word9 data. + 0 + 32 + read-only + + + + + BLK2_W10 + Otp debuger block2 data register10. + 0x9C + 0x20 + + + BLOCK2_W10 + Otp block2 word10 data. + 0 + 32 + read-only + + + + + BLK2_W11 + Otp debuger block2 data register11. + 0xA0 + 0x20 + + + BLOCK2_W11 + Otp block2 word11 data. + 0 + 32 + read-only + + + + + BLK3_W1 + Otp debuger block3 data register1. + 0xA4 + 0x20 + + + BLOCK3_W1 + Otp block3 word1 data. + 0 + 32 + read-only + + + + + BLK3_W2 + Otp debuger block3 data register2. + 0xA8 + 0x20 + + + BLOCK3_W2 + Otp block3 word2 data. + 0 + 32 + read-only + + + + + BLK3_W3 + Otp debuger block3 data register3. + 0xAC + 0x20 + + + BLOCK3_W3 + Otp block3 word3 data. + 0 + 32 + read-only + + + + + BLK3_W4 + Otp debuger block3 data register4. + 0xB0 + 0x20 + + + BLOCK3_W4 + Otp block3 word4 data. + 0 + 32 + read-only + + + + + BLK3_W5 + Otp debuger block3 data register5. + 0xB4 + 0x20 + + + BLOCK3_W5 + Otp block3 word5 data. + 0 + 32 + read-only + + + + + BLK3_W6 + Otp debuger block3 data register6. + 0xB8 + 0x20 + + + BLOCK3_W6 + Otp block3 word6 data. + 0 + 32 + read-only + + + + + BLK3_W7 + Otp debuger block3 data register7. + 0xBC + 0x20 + + + BLOCK3_W7 + Otp block3 word7 data. + 0 + 32 + read-only + + + + + BLK3_W8 + Otp debuger block3 data register8. + 0xC0 + 0x20 + + + BLOCK3_W8 + Otp block3 word8 data. + 0 + 32 + read-only + + + + + BLK3_W9 + Otp debuger block3 data register9. + 0xC4 + 0x20 + + + BLOCK3_W9 + Otp block3 word9 data. + 0 + 32 + read-only + + + + + BLK3_W10 + Otp debuger block3 data register10. + 0xC8 + 0x20 + + + BLOCK3_W10 + Otp block3 word10 data. + 0 + 32 + read-only + + + + + BLK3_W11 + Otp debuger block3 data register11. + 0xCC + 0x20 + + + BLOCK3_W11 + Otp block3 word11 data. + 0 + 32 + read-only + + + + + BLK4_W1 + Otp debuger block4 data register1. + 0xD0 + 0x20 + + + BLOCK4_W1 + Otp block4 word1 data. + 0 + 32 + read-only + + + + + BLK4_W2 + Otp debuger block4 data register2. + 0xD4 + 0x20 + + + BLOCK4_W2 + Otp block4 word2 data. + 0 + 32 + read-only + + + + + BLK4_W3 + Otp debuger block4 data register3. + 0xD8 + 0x20 + + + BLOCK4_W3 + Otp block4 word3 data. + 0 + 32 + read-only + + + + + BLK4_W4 + Otp debuger block4 data register4. + 0xDC + 0x20 + + + BLOCK4_W4 + Otp block4 word4 data. + 0 + 32 + read-only + + + + + BLK4_W5 + Otp debuger block4 data register5. + 0xE0 + 0x20 + + + BLOCK4_W5 + Otp block4 word5 data. + 0 + 32 + read-only + + + + + BLK4_W6 + Otp debuger block4 data register6. + 0xE4 + 0x20 + + + BLOCK4_W6 + Otp block4 word6 data. + 0 + 32 + read-only + + + + + BLK4_W7 + Otp debuger block4 data register7. + 0xE8 + 0x20 + + + BLOCK4_W7 + Otp block4 word7 data. + 0 + 32 + read-only + + + + + BLK4_W8 + Otp debuger block4 data register8. + 0xEC + 0x20 + + + BLOCK4_W8 + Otp block4 word8 data. + 0 + 32 + read-only + + + + + BLK4_W9 + Otp debuger block4 data register9. + 0xF0 + 0x20 + + + BLOCK4_W9 + Otp block4 word9 data. + 0 + 32 + read-only + + + + + BLK4_W10 + Otp debuger block4 data registe10. + 0xF4 + 0x20 + + + BLOCK4_W10 + Otp block4 word10 data. + 0 + 32 + read-only + + + + + BLK4_W11 + Otp debuger block4 data register11. + 0xF8 + 0x20 + + + BLOCK4_W11 + Otp block4 word11 data. + 0 + 32 + read-only + + + + + BLK5_W1 + Otp debuger block5 data register1. + 0xFC + 0x20 + + + BLOCK5_W1 + Otp block5 word1 data. + 0 + 32 + read-only + + + + + BLK5_W2 + Otp debuger block5 data register2. + 0x100 + 0x20 + + + BLOCK5_W2 + Otp block5 word2 data. + 0 + 32 + read-only + + + + + BLK5_W3 + Otp debuger block5 data register3. + 0x104 + 0x20 + + + BLOCK5_W3 + Otp block5 word3 data. + 0 + 32 + read-only + + + + + BLK5_W4 + Otp debuger block5 data register4. + 0x108 + 0x20 + + + BLOCK5_W4 + Otp block5 word4 data. + 0 + 32 + read-only + + + + + BLK5_W5 + Otp debuger block5 data register5. + 0x10C + 0x20 + + + BLOCK5_W5 + Otp block5 word5 data. + 0 + 32 + read-only + + + + + BLK5_W6 + Otp debuger block5 data register6. + 0x110 + 0x20 + + + BLOCK5_W6 + Otp block5 word6 data. + 0 + 32 + read-only + + + + + BLK5_W7 + Otp debuger block5 data register7. + 0x114 + 0x20 + + + BLOCK5_W7 + Otp block5 word7 data. + 0 + 32 + read-only + + + + + BLK5_W8 + Otp debuger block5 data register8. + 0x118 + 0x20 + + + BLOCK5_W8 + Otp block5 word8 data. + 0 + 32 + read-only + + + + + BLK5_W9 + Otp debuger block5 data register9. + 0x11C + 0x20 + + + BLOCK5_W9 + Otp block5 word9 data. + 0 + 32 + read-only + + + + + BLK5_W10 + Otp debuger block5 data register10. + 0x120 + 0x20 + + + BLOCK5_W10 + Otp block5 word10 data. + 0 + 32 + read-only + + + + + BLK5_W11 + Otp debuger block5 data register11. + 0x124 + 0x20 + + + BLOCK5_W11 + Otp block5 word11 data. + 0 + 32 + read-only + + + + + BLK6_W1 + Otp debuger block6 data register1. + 0x128 + 0x20 + + + BLOCK6_W1 + Otp block6 word1 data. + 0 + 32 + read-only + + + + + BLK6_W2 + Otp debuger block6 data register2. + 0x12C + 0x20 + + + BLOCK6_W2 + Otp block6 word2 data. + 0 + 32 + read-only + + + + + BLK6_W3 + Otp debuger block6 data register3. + 0x130 + 0x20 + + + BLOCK6_W3 + Otp block6 word3 data. + 0 + 32 + read-only + + + + + BLK6_W4 + Otp debuger block6 data register4. + 0x134 + 0x20 + + + BLOCK6_W4 + Otp block6 word4 data. + 0 + 32 + read-only + + + + + BLK6_W5 + Otp debuger block6 data register5. + 0x138 + 0x20 + + + BLOCK6_W5 + Otp block6 word5 data. + 0 + 32 + read-only + + + + + BLK6_W6 + Otp debuger block6 data register6. + 0x13C + 0x20 + + + BLOCK6_W6 + Otp block6 word6 data. + 0 + 32 + read-only + + + + + BLK6_W7 + Otp debuger block6 data register7. + 0x140 + 0x20 + + + BLOCK6_W7 + Otp block6 word7 data. + 0 + 32 + read-only + + + + + BLK6_W8 + Otp debuger block6 data register8. + 0x144 + 0x20 + + + BLOCK6_W8 + Otp block6 word8 data. + 0 + 32 + read-only + + + + + BLK6_W9 + Otp debuger block6 data register9. + 0x148 + 0x20 + + + BLOCK6_W9 + Otp block6 word9 data. + 0 + 32 + read-only + + + + + BLK6_W10 + Otp debuger block6 data register10. + 0x14C + 0x20 + + + BLOCK6_W10 + Otp block6 word10 data. + 0 + 32 + read-only + + + + + BLK6_W11 + Otp debuger block6 data register11. + 0x150 + 0x20 + + + BLOCK6_W11 + Otp block6 word11 data. + 0 + 32 + read-only + + + + + BLK7_W1 + Otp debuger block7 data register1. + 0x154 + 0x20 + + + BLOCK7_W1 + Otp block7 word1 data. + 0 + 32 + read-only + + + + + BLK7_W2 + Otp debuger block7 data register2. + 0x158 + 0x20 + + + BLOCK7_W2 + Otp block7 word2 data. + 0 + 32 + read-only + + + + + BLK7_W3 + Otp debuger block7 data register3. + 0x15C + 0x20 + + + BLOCK7_W3 + Otp block7 word3 data. + 0 + 32 + read-only + + + + + BLK7_W4 + Otp debuger block7 data register4. + 0x160 + 0x20 + + + BLOCK7_W4 + Otp block7 word4 data. + 0 + 32 + read-only + + + + + BLK7_W5 + Otp debuger block7 data register5. + 0x164 + 0x20 + + + BLOCK7_W5 + Otp block7 word5 data. + 0 + 32 + read-only + + + + + BLK7_W6 + Otp debuger block7 data register6. + 0x168 + 0x20 + + + BLOCK7_W6 + Otp block7 word6 data. + 0 + 32 + read-only + + + + + BLK7_W7 + Otp debuger block7 data register7. + 0x16C + 0x20 + + + BLOCK7_W7 + Otp block7 word7 data. + 0 + 32 + read-only + + + + + BLK7_W8 + Otp debuger block7 data register8. + 0x170 + 0x20 + + + BLOCK7_W8 + Otp block7 word8 data. + 0 + 32 + read-only + + + + + BLK7_W9 + Otp debuger block7 data register9. + 0x174 + 0x20 + + + BLOCK7_W9 + Otp block7 word9 data. + 0 + 32 + read-only + + + + + BLK7_W10 + Otp debuger block7 data register10. + 0x178 + 0x20 + + + BLOCK7_W10 + Otp block7 word10 data. + 0 + 32 + read-only + + + + + BLK7_W11 + Otp debuger block7 data register11. + 0x17C + 0x20 + + + BLOCK7_W11 + Otp block7 word11 data. + 0 + 32 + read-only + + + + + BLK8_W1 + Otp debuger block8 data register1. + 0x180 + 0x20 + + + BLOCK8_W1 + Otp block8 word1 data. + 0 + 32 + read-only + + + + + BLK8_W2 + Otp debuger block8 data register2. + 0x184 + 0x20 + + + BLOCK8_W2 + Otp block8 word2 data. + 0 + 32 + read-only + + + + + BLK8_W3 + Otp debuger block8 data register3. + 0x188 + 0x20 + + + BLOCK8_W3 + Otp block8 word3 data. + 0 + 32 + read-only + + + + + BLK8_W4 + Otp debuger block8 data register4. + 0x18C + 0x20 + + + BLOCK8_W4 + Otp block8 word4 data. + 0 + 32 + read-only + + + + + BLK8_W5 + Otp debuger block8 data register5. + 0x190 + 0x20 + + + BLOCK8_W5 + Otp block8 word5 data. + 0 + 32 + read-only + + + + + BLK8_W6 + Otp debuger block8 data register6. + 0x194 + 0x20 + + + BLOCK8_W6 + Otp block8 word6 data. + 0 + 32 + read-only + + + + + BLK8_W7 + Otp debuger block8 data register7. + 0x198 + 0x20 + + + BLOCK8_W7 + Otp block8 word7 data. + 0 + 32 + read-only + + + + + BLK8_W8 + Otp debuger block8 data register8. + 0x19C + 0x20 + + + BLOCK8_W8 + Otp block8 word8 data. + 0 + 32 + read-only + + + + + BLK8_W9 + Otp debuger block8 data register9. + 0x1A0 + 0x20 + + + BLOCK8_W9 + Otp block8 word9 data. + 0 + 32 + read-only + + + + + BLK8_W10 + Otp debuger block8 data register10. + 0x1A4 + 0x20 + + + BLOCK8_W10 + Otp block8 word10 data. + 0 + 32 + read-only + + + + + BLK8_W11 + Otp debuger block8 data register11. + 0x1A8 + 0x20 + + + BLOCK8_W11 + Otp block8 word11 data. + 0 + 32 + read-only + + + + + BLK9_W1 + Otp debuger block9 data register1. + 0x1AC + 0x20 + + + BLOCK9_W1 + Otp block9 word1 data. + 0 + 32 + read-only + + + + + BLK9_W2 + Otp debuger block9 data register2. + 0x1B0 + 0x20 + + + BLOCK9_W2 + Otp block9 word2 data. + 0 + 32 + read-only + + + + + BLK9_W3 + Otp debuger block9 data register3. + 0x1B4 + 0x20 + + + BLOCK9_W3 + Otp block9 word3 data. + 0 + 32 + read-only + + + + + BLK9_W4 + Otp debuger block9 data register4. + 0x1B8 + 0x20 + + + BLOCK9_W4 + Otp block9 word4 data. + 0 + 32 + read-only + + + + + BLK9_W5 + Otp debuger block9 data register5. + 0x1BC + 0x20 + + + BLOCK9_W5 + Otp block9 word5 data. + 0 + 32 + read-only + + + + + BLK9_W6 + Otp debuger block9 data register6. + 0x1C0 + 0x20 + + + BLOCK9_W6 + Otp block9 word6 data. + 0 + 32 + read-only + + + + + BLK9_W7 + Otp debuger block9 data register7. + 0x1C4 + 0x20 + + + BLOCK9_W7 + Otp block9 word7 data. + 0 + 32 + read-only + + + + + BLK9_W8 + Otp debuger block9 data register8. + 0x1C8 + 0x20 + + + BLOCK9_W8 + Otp block9 word8 data. + 0 + 32 + read-only + + + + + BLK9_W9 + Otp debuger block9 data register9. + 0x1CC + 0x20 + + + BLOCK9_W9 + Otp block9 word9 data. + 0 + 32 + read-only + + + + + BLK9_W10 + Otp debuger block9 data register10. + 0x1D0 + 0x20 + + + BLOCK9_W10 + Otp block9 word10 data. + 0 + 32 + read-only + + + + + BLK9_W11 + Otp debuger block9 data register11. + 0x1D4 + 0x20 + + + BLOCK9_W11 + Otp block9 word11 data. + 0 + 32 + read-only + + + + + BLK10_W1 + Otp debuger block10 data register1. + 0x1D8 + 0x20 + + + BLOCK10_W1 + Otp block10 word1 data. + 0 + 32 + read-only + + + + + BLK10_W2 + Otp debuger block10 data register2. + 0x1DC + 0x20 + + + BLOCK10_W2 + Otp block10 word2 data. + 0 + 32 + read-only + + + + + BLK10_W3 + Otp debuger block10 data register3. + 0x1E0 + 0x20 + + + BLOCK10_W3 + Otp block10 word3 data. + 0 + 32 + read-only + + + + + BLK10_W4 + Otp debuger block10 data register4. + 0x1E4 + 0x20 + + + BLOCK10_W4 + Otp block10 word4 data. + 0 + 32 + read-only + + + + + BLK10_W5 + Otp debuger block10 data register5. + 0x1E8 + 0x20 + + + BLOCK10_W5 + Otp block10 word5 data. + 0 + 32 + read-only + + + + + BLK10_W6 + Otp debuger block10 data register6. + 0x1EC + 0x20 + + + BLOCK10_W6 + Otp block10 word6 data. + 0 + 32 + read-only + + + + + BLK10_W7 + Otp debuger block10 data register7. + 0x1F0 + 0x20 + + + BLOCK10_W7 + Otp block10 word7 data. + 0 + 32 + read-only + + + + + BLK10_W8 + Otp debuger block10 data register8. + 0x1F4 + 0x20 + + + BLOCK10_W8 + Otp block10 word8 data. + 0 + 32 + read-only + + + + + BLK10_W9 + Otp debuger block10 data register9. + 0x1F8 + 0x20 + + + BLOCK10_W9 + Otp block10 word9 data. + 0 + 32 + read-only + + + + + BLK10_W10 + Otp debuger block10 data register10. + 0x1FC + 0x20 + + + BLOCK19_W10 + Otp block10 word10 data. + 0 + 32 + read-only + + + + + BLK10_W11 + Otp debuger block10 data register11. + 0x200 + 0x20 + + + BLOCK10_W11 + Otp block10 word11 data. + 0 + 32 + read-only + + + + + CLK + Otp debuger clk_en configuration register. + 0x204 + 0x20 + + + EN + Force clock on for this register file. + 0 + 1 + read-write + + + + + APB2OTP_EN + Otp_debuger apb2otp enable configuration register. + 0x208 + 0x20 + + + APB2OTP_EN + Debug mode enable signal. + 0 + 1 + read-write + + + + + DATE + eFuse version register. + 0x20C + 0x20 + 0x20211028 + + + DATE + Stores otp_debug version. + 0 + 28 + read-write + + + + + + + PARL_IO + Peripheral PARL_IO + PARL_IO + 0x60015000 + + 0x0 + 0x54 + registers + + + + RX_MODE_CFG + Parallel RX Sampling mode configuration register. + 0x0 + 0x20 + 0x00E00000 + + + RX_EXT_EN_SEL + Configures rx external enable signal selection from IO PAD. + 21 + 4 + read-write + + + RX_SW_EN + Set this bit to enable data sampling by software. + 25 + 1 + read-write + + + RX_EXT_EN_INV + Set this bit to invert the external enable signal. + 26 + 1 + read-write + + + RX_PULSE_SUBMODE_SEL + Configures the rxd pulse sampling submode. +4'd0: positive pulse start(data bit included) && positive pulse end(data bit included) +4'd1: positive pulse start(data bit included) && positive pulse end (data bit excluded) +4'd2: positive pulse start(data bit excluded) && positive pulse end (data bit included) +4'd3: positive pulse start(data bit excluded) && positive pulse end (data bit excluded) +4'd4: positive pulse start(data bit included) && length end +4'd5: positive pulse start(data bit excluded) && length end + 27 + 3 + read-write + + + RX_SMP_MODE_SEL + Configures the rxd sampling mode. +2'b00: external level enable mode +2'b01: external pulse enable mode +2'b10: internal software enable mode + 30 + 2 + read-write + + + + + RX_DATA_CFG + Parallel RX data configuration register. + 0x4 + 0x20 + 0x60000000 + + + RX_BITLEN + Configures expected byte number of received data. + 9 + 19 + read-write + + + RX_DATA_ORDER_INV + Set this bit to invert bit order of one byte sent from RX_FIFO to DMA. + 28 + 1 + read-write + + + RX_BUS_WID_SEL + Configures the rxd bus width. +3'd0: bus width is 1. +3'd1: bus width is 2. +3'd2: bus width is 4. +3'd3: bus width is 8. + 29 + 3 + read-write + + + + + RX_GENRL_CFG + Parallel RX general configuration register. + 0x8 + 0x20 + 0x21FFE000 + + + RX_GATING_EN + Set this bit to enable the clock gating of output rx clock. + 12 + 1 + read-write + + + RX_TIMEOUT_THRES + Configures threshold of timeout counter. + 13 + 16 + read-write + + + RX_TIMEOUT_EN + Set this bit to enable timeout function to generate error eof. + 29 + 1 + read-write + + + RX_EOF_GEN_SEL + Configures the DMA eof generated mechanism. 1'b0: eof generated by data byte length. 1'b1: eof generated by external enable signal. + 30 + 1 + read-write + + + + + RX_START_CFG + Parallel RX Start configuration register. + 0xC + 0x20 + + + RX_START + Set this bit to start rx data sampling. + 31 + 1 + read-write + + + + + TX_DATA_CFG + Parallel TX data configuration register. + 0x10 + 0x20 + 0x60000000 + + + TX_BITLEN + Configures expected byte number of sent data. + 9 + 19 + read-write + + + TX_DATA_ORDER_INV + Set this bit to invert bit order of one byte sent from TX_FIFO to IO data. + 28 + 1 + read-write + + + TX_BUS_WID_SEL + Configures the txd bus width. +3'd0: bus width is 1. +3'd1: bus width is 2. +3'd2: bus width is 4. +3'd3: bus width is 8. + 29 + 3 + read-write + + + + + TX_START_CFG + Parallel TX Start configuration register. + 0x14 + 0x20 + + + TX_START + Set this bit to start tx data transmit. + 31 + 1 + read-write + + + + + TX_GENRL_CFG + Parallel TX general configuration register. + 0x18 + 0x20 + + + TX_IDLE_VALUE + Configures bus value of transmitter in IDLE state. + 14 + 16 + read-write + + + TX_GATING_EN + Set this bit to enable the clock gating of output tx clock. + 30 + 1 + read-write + + + TX_VALID_OUTPUT_EN + Set this bit to enable the output of tx data valid signal. + 31 + 1 + read-write + + + + + FIFO_CFG + Parallel IO FIFO configuration register. + 0x1C + 0x20 + + + TX_FIFO_SRST + Set this bit to reset async fifo in tx module. + 30 + 1 + read-write + + + RX_FIFO_SRST + Set this bit to reset async fifo in rx module. + 31 + 1 + read-write + + + + + REG_UPDATE + Parallel IO FIFO configuration register. + 0x20 + 0x20 + + + RX_REG_UPDATE + Set this bit to update rx register configuration. + 31 + 1 + write-only + + + + + ST + Parallel IO module status register0. + 0x24 + 0x20 + + + TX_READY + Represents the status that tx is ready to transmit. + 31 + 1 + read-only + + + + + INT_ENA + Parallel IO interrupt enable singal configuration register. + 0x28 + 0x20 + + + TX_FIFO_REMPTY_INT_ENA + Set this bit to enable TX_FIFO_REMPTY_INT. + 0 + 1 + read-write + + + RX_FIFO_WOVF_INT_ENA + Set this bit to enable RX_FIFO_WOVF_INT. + 1 + 1 + read-write + + + TX_EOF_INT_ENA + Set this bit to enable TX_EOF_INT. + 2 + 1 + read-write + + + + + INT_RAW + Parallel IO interrupt raw singal status register. + 0x2C + 0x20 + + + TX_FIFO_REMPTY_INT_RAW + The raw interrupt status of TX_FIFO_REMPTY_INT. + 0 + 1 + read-only + + + RX_FIFO_WOVF_INT_RAW + The raw interrupt status of RX_FIFO_WOVF_INT. + 1 + 1 + read-only + + + TX_EOF_INT_RAW + The raw interrupt status of TX_EOF_INT. + 2 + 1 + read-only + + + + + INT_ST + Parallel IO interrupt singal status register. + 0x30 + 0x20 + + + TX_FIFO_REMPTY_INT_ST + The masked interrupt status of TX_FIFO_REMPTY_INT. + 0 + 1 + read-only + + + RX_FIFO_WOVF_INT_ST + The masked interrupt status of RX_FIFO_WOVF_INT. + 1 + 1 + read-only + + + TX_EOF_INT_ST + The masked interrupt status of TX_EOF_INT. + 2 + 1 + read-only + + + + + INT_CLR + Parallel IO interrupt clear singal configuration register. + 0x34 + 0x20 + + + TX_FIFO_REMPTY_INT_CLR + Set this bit to clear TX_FIFO_REMPTY_INT. + 0 + 1 + write-only + + + RX_FIFO_WOVF_INT_CLR + Set this bit to clear RX_FIFO_WOVF_INT. + 1 + 1 + write-only + + + TX_EOF_INT_CLR + Set this bit to clear TX_EOF_INT. + 2 + 1 + write-only + + + + + RX_ST0 + Parallel IO RX status register0 + 0x38 + 0x20 + + + RX_CNT + Indicates the cycle number of reading Rx FIFO. + 9 + 4 + read-only + + + RX_FIFO_WR_BIT_CNT + Indicates the current written bit number into Rx FIFO. + 13 + 19 + read-only + + + + + RX_ST1 + Parallel IO RX status register1 + 0x3C + 0x20 + + + RX_FIFO_RD_BIT_CNT + Indicates the current read bit number from Rx FIFO. + 13 + 19 + read-only + + + + + TX_ST0 + Parallel IO TX status register0 + 0x40 + 0x20 + + + TX_CNT + Indicates the cycle number of reading Tx FIFO. + 6 + 7 + read-only + + + TX_FIFO_RD_BIT_CNT + Indicates the current read bit number from Tx FIFO. + 13 + 19 + read-only + + + + + RX_CLK_CFG + Parallel IO RX clk configuration register + 0x44 + 0x20 + + + RX_CLK_I_INV + Set this bit to invert the input Rx core clock. + 30 + 1 + read-write + + + RX_CLK_O_INV + Set this bit to invert the output Rx core clock. + 31 + 1 + read-write + + + + + TX_CLK_CFG + Parallel IO TX clk configuration register + 0x48 + 0x20 + + + TX_CLK_I_INV + Set this bit to invert the input Tx core clock. + 30 + 1 + read-write + + + TX_CLK_O_INV + Set this bit to invert the output Tx core clock. + 31 + 1 + read-write + + + + + CLK + Parallel IO clk configuration register + 0x120 + 0x20 + + + EN + Force clock on for this register file + 31 + 1 + read-write + + + + + VERSION + Version register. + 0x3FC + 0x20 + 0x02208240 + + + DATE + Version of this register file + 0 + 28 + read-write + + + + + + + PAU + Peripheral PAU + PAU + 0x60093000 + + 0x0 + 0x4C + registers + + + + REGDMA_CONF + Peri backup control register + 0x0 + 0x20 + + + FLOW_ERR + backup error type + 0 + 3 + read-only + + + START + backup start signal + 3 + 1 + write-only + + + TO_MEM + backup direction(reg to mem / mem to reg) + 4 + 1 + read-write + + + LINK_SEL + Link select + 5 + 2 + read-write + + + START_MAC + mac sw backup start signal + 7 + 1 + write-only + + + TO_MEM_MAC + mac sw backup direction(reg to mem / mem to reg) + 8 + 1 + read-write + + + SEL_MAC + mac hw/sw select + 9 + 1 + read-write + + + + + REGDMA_CLK_CONF + Clock control register + 0x4 + 0x20 + + + CLK_EN + clock enable + 0 + 1 + read-write + + + + + REGDMA_ETM_CTRL + ETM start ctrl reg + 0x8 + 0x20 + + + ETM_START_0 + etm_start_0 reg + 0 + 1 + write-only + + + ETM_START_1 + etm_start_1 reg + 1 + 1 + write-only + + + ETM_START_2 + etm_start_2 reg + 2 + 1 + write-only + + + ETM_START_3 + etm_start_3 reg + 3 + 1 + write-only + + + + + REGDMA_LINK_0_ADDR + link_0_addr + 0xC + 0x20 + + + LINK_ADDR_0 + link_0_addr reg + 0 + 32 + read-write + + + + + REGDMA_LINK_1_ADDR + Link_1_addr + 0x10 + 0x20 + + + LINK_ADDR_1 + Link_1_addr reg + 0 + 32 + read-write + + + + + REGDMA_LINK_2_ADDR + Link_2_addr + 0x14 + 0x20 + + + LINK_ADDR_2 + Link_2_addr reg + 0 + 32 + read-write + + + + + REGDMA_LINK_3_ADDR + Link_3_addr + 0x18 + 0x20 + + + LINK_ADDR_3 + Link_3_addr reg + 0 + 32 + read-write + + + + + REGDMA_LINK_MAC_ADDR + Link_mac_addr + 0x1C + 0x20 + + + LINK_ADDR_MAC + Link_mac_addr reg + 0 + 32 + read-write + + + + + REGDMA_CURRENT_LINK_ADDR + current link addr + 0x20 + 0x20 + + + CURRENT_LINK_ADDR + current link addr reg + 0 + 32 + read-only + + + + + REGDMA_BACKUP_ADDR + Backup addr + 0x24 + 0x20 + + + BACKUP_ADDR + backup addr reg + 0 + 32 + read-only + + + + + REGDMA_MEM_ADDR + mem addr + 0x28 + 0x20 + + + MEM_ADDR + mem addr reg + 0 + 32 + read-only + + + + + REGDMA_BKP_CONF + backup config + 0x2C + 0x20 + 0x7D101920 + + + READ_INTERVAL + Link read_interval + 0 + 7 + read-write + + + LINK_TOUT_THRES + link wait timeout threshold + 7 + 10 + read-write + + + BURST_LIMIT + burst limit + 17 + 5 + read-write + + + BACKUP_TOUT_THRES + Backup timeout threshold + 22 + 10 + read-write + + + + + RETENTION_LINK_BASE + retention dma link base + 0x30 + 0x20 + + + LINK_BASE_ADDR + retention dma link base + 0 + 27 + read-write + + + + + RETENTION_CFG + retention_cfg + 0x34 + 0x20 + 0xFFFFFFFF + + + RET_INV_CFG + retention inv scan out + 0 + 32 + read-write + + + + + INT_ENA + Read only register for error and done + 0x38 + 0x20 + + + DONE_INT_ENA + backup done flag + 0 + 1 + read-write + + + ERROR_INT_ENA + error flag + 1 + 1 + read-write + + + + + INT_RAW + Read only register for error and done + 0x3C + 0x20 + + + DONE_INT_RAW + backup done flag + 0 + 1 + read-only + + + ERROR_INT_RAW + error flag + 1 + 1 + read-only + + + + + INT_CLR + Read only register for error and done + 0x40 + 0x20 + + + DONE_INT_CLR + backup done flag + 0 + 1 + write-only + + + ERROR_INT_CLR + error flag + 1 + 1 + write-only + + + + + INT_ST + Read only register for error and done + 0x44 + 0x20 + + + DONE_INT_ST + backup done flag + 0 + 1 + read-only + + + ERROR_INT_ST + error flag + 1 + 1 + read-only + + + + + DATE + Date register. + 0x3FC + 0x20 + 0x02203070 + + + DATE + REGDMA date information/ REGDMA version information. + 0 + 28 + read-write + + + + + + + PCNT + Pulse Counter + PCNT + 0x60012000 + + 0x0 + 0x68 + registers + + + + 4 + 0xC + U%s_CONF0 + Configuration register 0 for unit %s + 0x0 + 0x20 + 0x00003C10 + + + FILTER_THRES_U + This sets the maximum threshold, in APB_CLK cycles, for the filter. + +Any pulses with width less than this will be ignored when the filter is enabled. + 0 + 10 + read-write + + + FILTER_EN_U + This is the enable bit for unit %s's input filter. + 10 + 1 + read-write + + + THR_ZERO_EN_U + This is the enable bit for unit %s's zero comparator. + 11 + 1 + read-write + + + THR_H_LIM_EN_U + This is the enable bit for unit %s's thr_h_lim comparator. Configures it to enable the high limit interrupt. + 12 + 1 + read-write + + + THR_L_LIM_EN_U + This is the enable bit for unit %s's thr_l_lim comparator. Configures it to enable the low limit interrupt. + 13 + 1 + read-write + + + THR_THRES0_EN_U + This is the enable bit for unit %s's thres0 comparator. + 14 + 1 + read-write + + + THR_THRES1_EN_U + This is the enable bit for unit %s's thres1 comparator. + 15 + 1 + read-write + + + CH0_NEG_MODE_U + This register sets the behavior when the signal input of channel 0 detects a negative edge. + +1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter + 16 + 2 + read-write + + + CH0_POS_MODE_U + This register sets the behavior when the signal input of channel 0 detects a positive edge. + +1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter + 18 + 2 + read-write + + + CH0_HCTRL_MODE_U + This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is high. + +0: No modification.1: Invert behavior (increase -> decrease, decrease -> increase).2, 3: Inhibit counter modification + 20 + 2 + read-write + + + CH0_LCTRL_MODE_U + This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is low. + +0: No modification.1: Invert behavior (increase -> decrease, decrease -> increase).2, 3: Inhibit counter modification + 22 + 2 + read-write + + + CH1_NEG_MODE_U + This register sets the behavior when the signal input of channel 1 detects a negative edge. + +1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter + 24 + 2 + read-write + + + CH1_POS_MODE_U + This register sets the behavior when the signal input of channel 1 detects a positive edge. + +1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter + 26 + 2 + read-write + + + CH1_HCTRL_MODE_U + This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is high. + +0: No modification.1: Invert behavior (increase -> decrease, decrease -> increase).2, 3: Inhibit counter modification + 28 + 2 + read-write + + + CH1_LCTRL_MODE_U + This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is low. + +0: No modification.1: Invert behavior (increase -> decrease, decrease -> increase).2, 3: Inhibit counter modification + 30 + 2 + read-write + + + + + 4 + 0xC + U%s_CONF1 + Configuration register 1 for unit %s + 0x4 + 0x20 + + + CNT_THRES0_U + This register is used to configure the thres0 value for unit %s. + 0 + 16 + read-write + + + CNT_THRES1_U + This register is used to configure the thres1 value for unit %s. + 16 + 16 + read-write + + + + + 4 + 0xC + U%s_CONF2 + Configuration register 2 for unit %s + 0x8 + 0x20 + + + CNT_H_LIM_U + This register is used to configure the thr_h_lim value for unit %s. When pluse_cnt reaches this value, the counter will be cleared to 0. + 0 + 16 + read-write + + + CNT_L_LIM_U + This register is used to configure the thr_l_lim value for unit %s. When pluse_cnt reaches this value, the counter will be cleared to 0. + 16 + 16 + read-write + + + + + 4 + 0x4 + U%s_CNT + Counter value for unit %s + 0x30 + 0x20 + + + PULSE_CNT_U + This register stores the current pulse count value for unit %s. + 0 + 16 + read-only + + + + + INT_RAW + Interrupt raw status register + 0x40 + 0x20 + + + CNT_THR_EVENT_U0_INT_RAW + The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. + 0 + 1 + read-only + + + CNT_THR_EVENT_U1_INT_RAW + The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. + 1 + 1 + read-only + + + CNT_THR_EVENT_U2_INT_RAW + The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. + 2 + 1 + read-only + + + CNT_THR_EVENT_U3_INT_RAW + The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. + 3 + 1 + read-only + + + + + INT_ST + Interrupt status register + 0x44 + 0x20 + + + CNT_THR_EVENT_U0_INT_ST + The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. + 0 + 1 + read-only + + + CNT_THR_EVENT_U1_INT_ST + The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. + 1 + 1 + read-only + + + CNT_THR_EVENT_U2_INT_ST + The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. + 2 + 1 + read-only + + + CNT_THR_EVENT_U3_INT_ST + The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. + 3 + 1 + read-only + + + + + INT_ENA + Interrupt enable register + 0x48 + 0x20 + + + CNT_THR_EVENT_U0_INT_ENA + The interrupt enable bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. + 0 + 1 + read-write + + + CNT_THR_EVENT_U1_INT_ENA + The interrupt enable bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. + 1 + 1 + read-write + + + CNT_THR_EVENT_U2_INT_ENA + The interrupt enable bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. + 2 + 1 + read-write + + + CNT_THR_EVENT_U3_INT_ENA + The interrupt enable bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. + 3 + 1 + read-write + + + + + INT_CLR + Interrupt clear register + 0x4C + 0x20 + + + CNT_THR_EVENT_U0_INT_CLR + Set this bit to clear the PCNT_CNT_THR_EVENT_U0_INT interrupt. + 0 + 1 + write-only + + + CNT_THR_EVENT_U1_INT_CLR + Set this bit to clear the PCNT_CNT_THR_EVENT_U1_INT interrupt. + 1 + 1 + write-only + + + CNT_THR_EVENT_U2_INT_CLR + Set this bit to clear the PCNT_CNT_THR_EVENT_U2_INT interrupt. + 2 + 1 + write-only + + + CNT_THR_EVENT_U3_INT_CLR + Set this bit to clear the PCNT_CNT_THR_EVENT_U3_INT interrupt. + 3 + 1 + write-only + + + + + 4 + 0x4 + U%s_STATUS + PNCT UNIT%s status register + 0x50 + 0x20 + + + CNT_THR_ZERO_MODE_U + The pulse counter status of PCNT_U%s corresponding to 0. 0: pulse counter decreases from positive to 0. 1: pulse counter increases from negative to 0. 2: pulse counter is negative. 3: pulse counter is positive. + 0 + 2 + read-only + + + CNT_THR_THRES1_LAT_U + The latched value of thres1 event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thres1 and thres1 event is valid. 0: others + 2 + 1 + read-only + + + CNT_THR_THRES0_LAT_U + The latched value of thres0 event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thres0 and thres0 event is valid. 0: others + 3 + 1 + read-only + + + CNT_THR_L_LIM_LAT_U + The latched value of low limit event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thr_l_lim and low limit event is valid. 0: others + 4 + 1 + read-only + + + CNT_THR_H_LIM_LAT_U + The latched value of high limit event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thr_h_lim and high limit event is valid. 0: others + 5 + 1 + read-only + + + CNT_THR_ZERO_LAT_U + The latched value of zero threshold event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to 0 and zero threshold event is valid. 0: others + 6 + 1 + read-only + + + + + CTRL + Control register for all counters + 0x60 + 0x20 + 0x00000001 + + + PULSE_CNT_RST_U0 + Set this bit to clear unit 0's counter. + 0 + 1 + read-write + + + CNT_PAUSE_U0 + Set this bit to freeze unit 0's counter. + 1 + 1 + read-write + + + PULSE_CNT_RST_U1 + Set this bit to clear unit 1's counter. + 2 + 1 + read-write + + + CNT_PAUSE_U1 + Set this bit to freeze unit 1's counter. + 3 + 1 + read-write + + + PULSE_CNT_RST_U2 + Set this bit to clear unit 2's counter. + 4 + 1 + read-write + + + CNT_PAUSE_U2 + Set this bit to freeze unit 2's counter. + 5 + 1 + read-write + + + PULSE_CNT_RST_U3 + Set this bit to clear unit 3's counter. + 6 + 1 + read-write + + + CNT_PAUSE_U3 + Set this bit to freeze unit 3's counter. + 7 + 1 + read-write + + + CLK_EN + The registers clock gate enable signal of PCNT module. 1: the registers can be read and written by application. 0: the registers can not be read or written by application + 16 + 1 + read-write + + + + + DATE + PCNT version control register + 0xFC + 0x20 + 0x18072600 + + + DATE + This is the PCNT version control register. + 0 + 32 + read-write + + + + + + + PCR + Peripheral PCR + PCR + 0x60096000 + + 0x0 + 0x164 + registers + + + + UART0_CONF + UART0 configuration register + 0x0 + 0x20 + 0x00000005 + + + UART0_CLK_EN + Set 1 to enable uart0 apb clock + 0 + 1 + read-write + + + UART0_RST_EN + Set 0 to reset uart0 module + 1 + 1 + read-write + + + UART0_READY + Query this field after reset uart0 module + 2 + 1 + read-only + + + + + UART0_SCLK_CONF + UART0_SCLK configuration register + 0x4 + 0x20 + 0x00700000 + + + UART0_SCLK_DIV_A + The denominator of the frequency divider factor of the uart0 function clock. + 0 + 6 + read-write + + + UART0_SCLK_DIV_B + The numerator of the frequency divider factor of the uart0 function clock. + 6 + 6 + read-write + + + UART0_SCLK_DIV_NUM + The integral part of the frequency divider factor of the uart0 function clock. + 12 + 8 + read-write + + + UART0_SCLK_SEL + set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2: FOSC, 3(default): XTAL. + 20 + 2 + read-write + + + UART0_SCLK_EN + Set 1 to enable uart0 function clock + 22 + 1 + read-write + + + + + UART0_PD_CTRL + UART0 power control register + 0x8 + 0x20 + 0x00000002 + + + UART0_MEM_FORCE_PU + Set this bit to force power down UART0 memory. + 1 + 1 + read-write + + + UART0_MEM_FORCE_PD + Set this bit to force power up UART0 memory. + 2 + 1 + read-write + + + + + UART1_CONF + UART1 configuration register + 0xC + 0x20 + 0x00000005 + + + UART1_CLK_EN + Set 1 to enable uart1 apb clock + 0 + 1 + read-write + + + UART1_RST_EN + Set 0 to reset uart1 module + 1 + 1 + read-write + + + UART1_READY + Query this field after reset uart1 module + 2 + 1 + read-only + + + + + UART1_SCLK_CONF + UART1_SCLK configuration register + 0x10 + 0x20 + 0x00700000 + + + UART1_SCLK_DIV_A + The denominator of the frequency divider factor of the uart1 function clock. + 0 + 6 + read-write + + + UART1_SCLK_DIV_B + The numerator of the frequency divider factor of the uart1 function clock. + 6 + 6 + read-write + + + UART1_SCLK_DIV_NUM + The integral part of the frequency divider factor of the uart1 function clock. + 12 + 8 + read-write + + + UART1_SCLK_SEL + set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2: FOSC, 3(default): XTAL. + 20 + 2 + read-write + + + UART1_SCLK_EN + Set 1 to enable uart0 function clock + 22 + 1 + read-write + + + + + UART1_PD_CTRL + UART1 power control register + 0x14 + 0x20 + 0x00000002 + + + UART1_MEM_FORCE_PU + Set this bit to force power down UART1 memory. + 1 + 1 + read-write + + + UART1_MEM_FORCE_PD + Set this bit to force power up UART1 memory. + 2 + 1 + read-write + + + + + MSPI_CONF + MSPI configuration register + 0x18 + 0x20 + 0x00000025 + + + MSPI_CLK_EN + Set 1 to enable mspi clock, include mspi pll clock + 0 + 1 + read-write + + + MSPI_RST_EN + Set 0 to reset mspi module + 1 + 1 + read-write + + + MSPI_PLL_CLK_EN + Set 1 to enable mspi pll clock + 2 + 1 + read-write + + + MSPI_CLK_SEL + set this field to select clock-source. + 3 + 2 + read-write + + + MSPI_READY + Query this field after reset mspi module + 5 + 1 + read-only + + + + + MSPI_CLK_CONF + MSPI_CLK configuration register + 0x1C + 0x20 + + + MSPI_FAST_DIV_NUM + Set as one within (0,1,2) to generate div1(default)/div2/div4 of low-speed clock-source to drive clk_mspi_fast. Only avaiable whe the clck-source is a low-speed clock-source such as XTAL/FOSC. + 0 + 8 + read-write + + + + + I2C0_CONF + I2C configuration register + 0x20 + 0x20 + 0x00000005 + + + I2C0_CLK_EN + Set 1 to enable i2c apb clock + 0 + 1 + read-write + + + I2C0_RST_EN + Set 0 to reset i2c module + 1 + 1 + read-write + + + I2C0_READY + Query this field after reset i2c0 module + 2 + 1 + read-only + + + + + I2C0_SCLK_CONF + I2C_SCLK configuration register + 0x24 + 0x20 + 0x00400000 + + + I2C0_SCLK_DIV_A + The denominator of the frequency divider factor of the i2c function clock. + 0 + 6 + read-write + + + I2C0_SCLK_DIV_B + The numerator of the frequency divider factor of the i2c function clock. + 6 + 6 + read-write + + + I2C0_SCLK_DIV_NUM + The integral part of the frequency divider factor of the i2c function clock. + 12 + 8 + read-write + + + I2C0_SCLK_SEL + set this field to select clock-source. 0(default): XTAL, 1: FOSC. + 20 + 1 + read-write + + + I2C0_SCLK_EN + Set 1 to enable i2c function clock + 22 + 1 + read-write + + + + + I2C1_CONF + I2C configuration register + 0x28 + 0x20 + 0x00000005 + + + I2C1_CLK_EN + Set 1 to enable i2c apb clock + 0 + 1 + read-write + + + I2C1_RST_EN + Set 0 to reset i2c module + 1 + 1 + read-write + + + I2C1_READY + Query this field after reset i2c1 module + 2 + 1 + read-only + + + + + I2C1_SCLK_CONF + I2C_SCLK configuration register + 0x2C + 0x20 + 0x00400000 + + + I2C1_SCLK_DIV_A + The denominator of the frequency divider factor of the i2c function clock. + 0 + 6 + read-write + + + I2C1_SCLK_DIV_B + The numerator of the frequency divider factor of the i2c function clock. + 6 + 6 + read-write + + + I2C1_SCLK_DIV_NUM + The integral part of the frequency divider factor of the i2c function clock. + 12 + 8 + read-write + + + I2C1_SCLK_SEL + set this field to select clock-source. 0(default): XTAL, 1: FOSC. + 20 + 1 + read-write + + + I2C1_SCLK_EN + Set 1 to enable i2c function clock + 22 + 1 + read-write + + + + + UHCI_CONF + UHCI configuration register + 0x30 + 0x20 + 0x00000005 + + + UHCI_CLK_EN + Set 1 to enable uhci clock + 0 + 1 + read-write + + + UHCI_RST_EN + Set 0 to reset uhci module + 1 + 1 + read-write + + + UHCI_READY + Query this field after reset uhci module + 2 + 1 + read-only + + + + + RMT_CONF + RMT configuration register + 0x34 + 0x20 + 0x00000005 + + + RMT_CLK_EN + Set 1 to enable rmt apb clock + 0 + 1 + read-write + + + RMT_RST_EN + Set 0 to reset rmt module + 1 + 1 + read-write + + + RMT_READY + Query this field after reset rmt module + 2 + 1 + read-only + + + + + RMT_SCLK_CONF + RMT_SCLK configuration register + 0x38 + 0x20 + 0x00301000 + + + RMT_SCLK_DIV_A + The denominator of the frequency divider factor of the rmt function clock. + 0 + 6 + read-write + + + RMT_SCLK_DIV_B + The numerator of the frequency divider factor of the rmt function clock. + 6 + 6 + read-write + + + RMT_SCLK_DIV_NUM + The integral part of the frequency divider factor of the rmt function clock. + 12 + 8 + read-write + + + RMT_SCLK_SEL + set this field to select clock-source. 0: do not select anyone clock, 1(default): 80MHz, 2: FOSC, 3: XTAL. + 20 + 1 + read-write + + + RMT_SCLK_EN + Set 1 to enable rmt function clock + 21 + 1 + read-write + + + + + LEDC_CONF + LEDC configuration register + 0x3C + 0x20 + 0x00000005 + + + LEDC_CLK_EN + Set 1 to enable ledc apb clock + 0 + 1 + read-write + + + LEDC_RST_EN + Set 0 to reset ledc module + 1 + 1 + read-write + + + LEDC_READY + Query this field after reset ledc module + 2 + 1 + read-only + + + + + LEDC_SCLK_CONF + LEDC_SCLK configuration register + 0x40 + 0x20 + 0x00400000 + + + LEDC_SCLK_SEL + set this field to select clock-source. 0(default): do not select anyone clock, 1: 80MHz, 2: FOSC, 3: XTAL. + 20 + 2 + read-write + + + LEDC_SCLK_EN + Set 1 to enable ledc function clock + 22 + 1 + read-write + + + + + TIMERGROUP0_CONF + TIMERGROUP0 configuration register + 0x44 + 0x20 + 0x0000001D + + + TG0_CLK_EN + Set 1 to enable timer_group0 apb clock + 0 + 1 + read-write + + + TG0_RST_EN + Set 0 to reset timer_group0 module + 1 + 1 + read-write + + + TG0_WDT_READY + Query this field after reset timer_group0 wdt module + 2 + 1 + read-only + + + TG0_TIMER0_READY + Query this field after reset timer_group0 timer0 module + 3 + 1 + read-only + + + TG0_TIMER1_READY + reserved + 4 + 1 + read-only + + + + + TIMERGROUP0_TIMER_CLK_CONF + TIMERGROUP0_TIMER_CLK configuration register + 0x48 + 0x20 + 0x00400000 + + + TG0_TIMER_CLK_SEL + set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: reserved. + 20 + 2 + read-write + + + TG0_TIMER_CLK_EN + Set 1 to enable timer_group0 timer clock + 22 + 1 + read-write + + + + + TIMERGROUP0_WDT_CLK_CONF + TIMERGROUP0_WDT_CLK configuration register + 0x4C + 0x20 + 0x00400000 + + + TG0_WDT_CLK_SEL + set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: reserved. + 20 + 2 + read-write + + + TG0_WDT_CLK_EN + Set 1 to enable timer_group0 wdt clock + 22 + 1 + read-write + + + + + TIMERGROUP1_CONF + TIMERGROUP1 configuration register + 0x50 + 0x20 + 0x0000001D + + + TG1_CLK_EN + Set 1 to enable timer_group1 apb clock + 0 + 1 + read-write + + + TG1_RST_EN + Set 0 to reset timer_group1 module + 1 + 1 + read-write + + + TG1_WDT_READY + Query this field after reset timer_group1 wdt module + 2 + 1 + read-only + + + TG1_TIMER0_READY + Query this field after reset timer_group1 timer0 module + 3 + 1 + read-only + + + TG1_TIMER1_READY + reserved + 4 + 1 + read-only + + + + + TIMERGROUP1_TIMER_CLK_CONF + TIMERGROUP1_TIMER_CLK configuration register + 0x54 + 0x20 + 0x00400000 + + + TG1_TIMER_CLK_SEL + set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: reserved. + 20 + 2 + read-write + + + TG1_TIMER_CLK_EN + Set 1 to enable timer_group1 timer clock + 22 + 1 + read-write + + + + + TIMERGROUP1_WDT_CLK_CONF + TIMERGROUP1_WDT_CLK configuration register + 0x58 + 0x20 + 0x00400000 + + + TG1_WDT_CLK_SEL + set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: reserved. + 20 + 2 + read-write + + + TG1_WDT_CLK_EN + Set 1 to enable timer_group0 wdt clock + 22 + 1 + read-write + + + + + SYSTIMER_CONF + SYSTIMER configuration register + 0x5C + 0x20 + 0x00000005 + + + SYSTIMER_CLK_EN + Set 1 to enable systimer apb clock + 0 + 1 + read-write + + + SYSTIMER_RST_EN + Set 0 to reset systimer module + 1 + 1 + read-write + + + SYSTIMER_READY + Query this field after reset systimer module + 2 + 1 + read-only + + + + + SYSTIMER_FUNC_CLK_CONF + SYSTIMER_FUNC_CLK configuration register + 0x60 + 0x20 + 0x00400000 + + + SYSTIMER_FUNC_CLK_SEL + set this field to select clock-source. 0(default): XTAL, 1: FOSC. + 20 + 1 + read-write + + + SYSTIMER_FUNC_CLK_EN + Set 1 to enable systimer function clock + 22 + 1 + read-write + + + + + TWAI0_CONF + TWAI0 configuration register + 0x64 + 0x20 + 0x00000005 + + + TWAI0_CLK_EN + Set 1 to enable twai0 apb clock + 0 + 1 + read-write + + + TWAI0_RST_EN + Set 0 to reset twai0 module + 1 + 1 + read-write + + + TWAI0_READY + Query this field after reset twai0 module + 2 + 1 + read-only + + + + + TWAI0_FUNC_CLK_CONF + TWAI0_FUNC_CLK configuration register + 0x68 + 0x20 + 0x00400000 + + + TWAI0_FUNC_CLK_SEL + set this field to select clock-source. 0(default): XTAL, 1: FOSC. + 20 + 1 + read-write + + + TWAI0_FUNC_CLK_EN + Set 1 to enable twai0 function clock + 22 + 1 + read-write + + + + + I2S_CONF + I2S configuration register + 0x6C + 0x20 + 0x0000000D + + + I2S_CLK_EN + Set 1 to enable i2s apb clock + 0 + 1 + read-write + + + I2S_RST_EN + Set 0 to reset i2s module + 1 + 1 + read-write + + + I2S_RX_READY + Query this field before using i2s rx function, after reset i2s module + 2 + 1 + read-only + + + I2S_TX_READY + Query this field before using i2s tx function, after reset i2s module + 3 + 1 + read-only + + + + + I2S_TX_CLKM_CONF + I2S_TX_CLKM configuration register + 0x70 + 0x20 + 0x00402000 + + + I2S_TX_CLKM_DIV_NUM + Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <= a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x * (n+1)-div] + y * (n+1)-div. + 12 + 8 + read-write + + + I2S_TX_CLKM_SEL + Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in. + 20 + 2 + read-write + + + I2S_TX_CLKM_EN + Set 1 to enable i2s_tx function clock + 22 + 1 + read-write + + + + + I2S_TX_CLKM_DIV_CONF + I2S_TX_CLKM_DIV configuration register + 0x74 + 0x20 + 0x00000200 + + + I2S_TX_CLKM_DIV_Z + For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_TX_CLKM_DIV_Z is (a-b). + 0 + 9 + read-write + + + I2S_TX_CLKM_DIV_Y + For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_TX_CLKM_DIV_Y is (a%(a-b)). + 9 + 9 + read-write + + + I2S_TX_CLKM_DIV_X + For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1. + 18 + 9 + read-write + + + I2S_TX_CLKM_DIV_YN1 + For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_TX_CLKM_DIV_YN1 is 1. + 27 + 1 + read-write + + + + + I2S_RX_CLKM_CONF + I2S_RX_CLKM configuration register + 0x78 + 0x20 + 0x00402000 + + + I2S_RX_CLKM_DIV_NUM + Integral I2S clock divider value + 12 + 8 + read-write + + + I2S_RX_CLKM_SEL + Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in. + 20 + 2 + read-write + + + I2S_RX_CLKM_EN + Set 1 to enable i2s_rx function clock + 22 + 1 + read-write + + + I2S_MCLK_SEL + This field is used to select master-clock. 0(default): clk_i2s_rx, 1: clk_i2s_tx + 23 + 1 + read-write + + + + + I2S_RX_CLKM_DIV_CONF + I2S_RX_CLKM_DIV configuration register + 0x7C + 0x20 + 0x00000200 + + + I2S_RX_CLKM_DIV_Z + For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_RX_CLKM_DIV_Z is (a-b). + 0 + 9 + read-write + + + I2S_RX_CLKM_DIV_Y + For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_RX_CLKM_DIV_Y is (a%(a-b)). + 9 + 9 + read-write + + + I2S_RX_CLKM_DIV_X + For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1. + 18 + 9 + read-write + + + I2S_RX_CLKM_DIV_YN1 + For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_RX_CLKM_DIV_YN1 is 1. + 27 + 1 + read-write + + + + + SARADC_CONF + SARADC configuration register + 0x80 + 0x20 + 0x00000005 + + + SARADC_CLK_EN + no use + 0 + 1 + read-write + + + SARADC_RST_EN + Set 0 to reset function_register of saradc module + 1 + 1 + read-write + + + SARADC_REG_CLK_EN + Set 1 to enable saradc apb clock + 2 + 1 + read-write + + + SARADC_REG_RST_EN + Set 0 to reset apb_register of saradc module + 3 + 1 + read-write + + + + + SARADC_CLKM_CONF + SARADC_CLKM configuration register + 0x84 + 0x20 + 0x00404000 + + + SARADC_CLKM_DIV_A + The denominator of the frequency divider factor of the saradc function clock. + 0 + 6 + read-write + + + SARADC_CLKM_DIV_B + The numerator of the frequency divider factor of the saradc function clock. + 6 + 6 + read-write + + + SARADC_CLKM_DIV_NUM + The integral part of the frequency divider factor of the saradc function clock. + 12 + 8 + read-write + + + SARADC_CLKM_SEL + set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: FOSC, 3: reserved. + 20 + 2 + read-write + + + SARADC_CLKM_EN + Set 1 to enable saradc function clock + 22 + 1 + read-write + + + + + TSENS_CLK_CONF + TSENS_CLK configuration register + 0x88 + 0x20 + 0x00400000 + + + TSENS_CLK_SEL + set this field to select clock-source. 0(default): FOSC, 1: XTAL. + 20 + 1 + read-write + + + TSENS_CLK_EN + Set 1 to enable tsens clock + 22 + 1 + read-write + + + TSENS_RST_EN + Set 0 to reset tsens module + 23 + 1 + read-write + + + + + USB_DEVICE_CONF + USB_DEVICE configuration register + 0x8C + 0x20 + 0x00000005 + + + USB_DEVICE_CLK_EN + Set 1 to enable usb_device clock + 0 + 1 + read-write + + + USB_DEVICE_RST_EN + Set 0 to reset usb_device module + 1 + 1 + read-write + + + USB_DEVICE_READY + Query this field after reset usb_device module + 2 + 1 + read-only + + + + + INTMTX_CONF + INTMTX configuration register + 0x90 + 0x20 + 0x00000005 + + + INTMTX_CLK_EN + Set 1 to enable intmtx clock + 0 + 1 + read-write + + + INTMTX_RST_EN + Set 0 to reset intmtx module + 1 + 1 + read-write + + + INTMTX_READY + Query this field after reset intmtx module + 2 + 1 + read-only + + + + + PCNT_CONF + PCNT configuration register + 0x94 + 0x20 + 0x00000005 + + + PCNT_CLK_EN + Set 1 to enable pcnt clock + 0 + 1 + read-write + + + PCNT_RST_EN + Set 0 to reset pcnt module + 1 + 1 + read-write + + + PCNT_READY + Query this field after reset pcnt module + 2 + 1 + read-only + + + + + ETM_CONF + ETM configuration register + 0x98 + 0x20 + 0x00000005 + + + ETM_CLK_EN + Set 1 to enable etm clock + 0 + 1 + read-write + + + ETM_RST_EN + Set 0 to reset etm module + 1 + 1 + read-write + + + ETM_READY + Query this field after reset etm module + 2 + 1 + read-only + + + + + PWM_CONF + PWM configuration register + 0x9C + 0x20 + 0x00000005 + + + PWM_CLK_EN + Set 1 to enable pwm clock + 0 + 1 + read-write + + + PWM_RST_EN + Set 0 to reset pwm module + 1 + 1 + read-write + + + PWM_READY + Query this field after reset pwm module + 2 + 1 + read-only + + + + + PWM_CLK_CONF + PWM_CLK configuration register + 0xA0 + 0x20 + 0x00404000 + + + PWM_DIV_NUM + The integral part of the frequency divider factor of the pwm function clock. + 12 + 8 + read-write + + + PWM_CLKM_SEL + set this field to select clock-source. 0(default): do not select anyone clock, 1: 160MHz, 2: XTAL, 3: FOSC. + 20 + 2 + read-write + + + PWM_CLKM_EN + set this field as 1 to activate pwm clkm. + 22 + 1 + read-write + + + + + PARL_IO_CONF + PARL_IO configuration register + 0xA4 + 0x20 + 0x00000005 + + + PARL_CLK_EN + Set 1 to enable parl apb clock + 0 + 1 + read-write + + + PARL_RST_EN + Set 0 to reset parl apb reg + 1 + 1 + read-write + + + PARL_READY + Query this field after reset parl module + 2 + 1 + read-only + + + + + PARL_CLK_RX_CONF + PARL_CLK_RX configuration register + 0xA8 + 0x20 + 0x00040000 + + + PARL_CLK_RX_DIV_NUM + The integral part of the frequency divider factor of the parl rx clock. + 0 + 16 + read-write + + + PARL_CLK_RX_SEL + set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: FOSC, 3: user clock from pad. + 16 + 2 + read-write + + + PARL_CLK_RX_EN + Set 1 to enable parl rx clock + 18 + 1 + read-write + + + PARL_RX_RST_EN + Set 0 to reset parl rx module + 19 + 1 + read-write + + + + + PARL_CLK_TX_CONF + PARL_CLK_TX configuration register + 0xAC + 0x20 + 0x00040000 + + + PARL_CLK_TX_DIV_NUM + The integral part of the frequency divider factor of the parl tx clock. + 0 + 16 + read-write + + + PARL_CLK_TX_SEL + set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: FOSC, 3: user clock from pad. + 16 + 2 + read-write + + + PARL_CLK_TX_EN + Set 1 to enable parl tx clock + 18 + 1 + read-write + + + PARL_TX_RST_EN + Set 0 to reset parl tx module + 19 + 1 + read-write + + + + + PVT_MONITOR_CONF + PVT_MONITOR configuration register + 0xB0 + 0x20 + 0x0000001D + + + PVT_MONITOR_CLK_EN + Set 1 to enable apb clock of pvt module + 0 + 1 + read-write + + + PVT_MONITOR_RST_EN + Set 0 to reset all pvt monitor module + 1 + 1 + read-write + + + PVT_MONITOR_SITE1_CLK_EN + Set 1 to enable function clock of modem pvt module + 2 + 1 + read-write + + + PVT_MONITOR_SITE2_CLK_EN + Set 1 to enable function clock of cpu pvt module + 3 + 1 + read-write + + + PVT_MONITOR_SITE3_CLK_EN + Set 1 to enable function clock of hp_peri pvt module + 4 + 1 + read-write + + + + + PVT_MONITOR_FUNC_CLK_CONF + PVT_MONITOR function clock configuration register + 0xB4 + 0x20 + 0x00400000 + + + PVT_MONITOR_FUNC_CLK_DIV_NUM + The integral part of the frequency divider factor of the pvt_monitor function clock. + 0 + 4 + read-write + + + PVT_MONITOR_FUNC_CLK_SEL + set this field to select clock-source. 0: XTAL, 1(default): 160MHz drived by SPLL divided by 3. + 20 + 1 + read-write + + + PVT_MONITOR_FUNC_CLK_EN + Set 1 to enable source clock of pvt sitex + 22 + 1 + read-write + + + + + GDMA_CONF + GDMA configuration register + 0xB8 + 0x20 + 0x00000001 + + + GDMA_CLK_EN + Set 1 to enable gdma clock + 0 + 1 + read-write + + + GDMA_RST_EN + Set 0 to reset gdma module + 1 + 1 + read-write + + + + + SPI2_CONF + SPI2 configuration register + 0xBC + 0x20 + 0x00000005 + + + SPI2_CLK_EN + Set 1 to enable spi2 apb clock + 0 + 1 + read-write + + + SPI2_RST_EN + Set 0 to reset spi2 module + 1 + 1 + read-write + + + SPI2_READY + Query this field after reset spi2 module + 2 + 1 + read-only + + + + + SPI2_CLKM_CONF + SPI2_CLKM configuration register + 0xC0 + 0x20 + 0x00400000 + + + SPI2_CLKM_SEL + set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: reserved. + 20 + 2 + read-write + + + SPI2_CLKM_EN + Set 1 to enable spi2 function clock + 22 + 1 + read-write + + + + + AES_CONF + AES configuration register + 0xC4 + 0x20 + 0x00000005 + + + AES_CLK_EN + Set 1 to enable aes clock + 0 + 1 + read-write + + + AES_RST_EN + Set 0 to reset aes module + 1 + 1 + read-write + + + AES_READY + Query this field after reset aes module + 2 + 1 + read-only + + + + + SHA_CONF + SHA configuration register + 0xC8 + 0x20 + 0x00000005 + + + SHA_CLK_EN + Set 1 to enable sha clock + 0 + 1 + read-write + + + SHA_RST_EN + Set 0 to reset sha module + 1 + 1 + read-write + + + SHA_READY + Query this field after reset sha module + 2 + 1 + read-only + + + + + RSA_CONF + RSA configuration register + 0xCC + 0x20 + 0x00000005 + + + RSA_CLK_EN + Set 1 to enable rsa clock + 0 + 1 + read-write + + + RSA_RST_EN + Set 0 to reset rsa module + 1 + 1 + read-write + + + RSA_READY + Query this field after reset rsa module + 2 + 1 + read-only + + + + + RSA_PD_CTRL + RSA power control register + 0xD0 + 0x20 + 0x00000002 + + + RSA_MEM_PD + Set this bit to power down rsa internal memory. + 0 + 1 + read-write + + + RSA_MEM_FORCE_PU + Set this bit to force power up rsa internal memory + 1 + 1 + read-write + + + RSA_MEM_FORCE_PD + Set this bit to force power down rsa internal memory. + 2 + 1 + read-write + + + + + ECC_CONF + ECC configuration register + 0xD4 + 0x20 + 0x00000005 + + + ECC_CLK_EN + Set 1 to enable ecc clock + 0 + 1 + read-write + + + ECC_RST_EN + Set 0 to reset ecc module + 1 + 1 + read-write + + + ECC_READY + Query this field after reset ecc module + 2 + 1 + read-only + + + + + ECC_PD_CTRL + ECC power control register + 0xD8 + 0x20 + 0x00000002 + + + ECC_MEM_PD + Set this bit to power down ecc internal memory. + 0 + 1 + read-write + + + ECC_MEM_FORCE_PU + Set this bit to force power up ecc internal memory + 1 + 1 + read-write + + + ECC_MEM_FORCE_PD + Set this bit to force power down ecc internal memory. + 2 + 1 + read-write + + + + + DS_CONF + DS configuration register + 0xDC + 0x20 + 0x00000005 + + + DS_CLK_EN + Set 1 to enable ds clock + 0 + 1 + read-write + + + DS_RST_EN + Set 0 to reset ds module + 1 + 1 + read-write + + + DS_READY + Query this field after reset ds module + 2 + 1 + read-only + + + + + HMAC_CONF + HMAC configuration register + 0xE0 + 0x20 + 0x00000005 + + + HMAC_CLK_EN + Set 1 to enable hmac clock + 0 + 1 + read-write + + + HMAC_RST_EN + Set 0 to reset hmac module + 1 + 1 + read-write + + + HMAC_READY + Query this field after reset hmac module + 2 + 1 + read-only + + + + + ECDSA_CONF + ECDSA configuration register + 0xE4 + 0x20 + 0x00000005 + + + ECDSA_CLK_EN + Set 1 to enable ecdsa clock + 0 + 1 + read-write + + + ECDSA_RST_EN + Set 0 to reset ecdsa module + 1 + 1 + read-write + + + ECDSA_READY + Query this field after reset ecdsa module + 2 + 1 + read-only + + + + + IOMUX_CONF + IOMUX configuration register + 0xE8 + 0x20 + 0x00000001 + + + IOMUX_CLK_EN + Set 1 to enable iomux apb clock + 0 + 1 + read-write + + + IOMUX_RST_EN + Set 0 to reset iomux module + 1 + 1 + read-write + + + + + IOMUX_CLK_CONF + IOMUX_CLK configuration register + 0xEC + 0x20 + 0x00400000 + + + IOMUX_FUNC_CLK_SEL + set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2: FOSC, 3(default): XTAL. + 20 + 2 + read-write + + + IOMUX_FUNC_CLK_EN + Set 1 to enable iomux function clock + 22 + 1 + read-write + + + + + MEM_MONITOR_CONF + MEM_MONITOR configuration register + 0xF0 + 0x20 + 0x00000005 + + + MEM_MONITOR_CLK_EN + Set 1 to enable mem_monitor clock + 0 + 1 + read-write + + + MEM_MONITOR_RST_EN + Set 0 to reset mem_monitor module + 1 + 1 + read-write + + + MEM_MONITOR_READY + Query this field after reset mem_monitor module + 2 + 1 + read-only + + + + + REGDMA_CONF + REGDMA configuration register + 0xF4 + 0x20 + + + REGDMA_CLK_EN + Set 1 to enable regdma clock + 0 + 1 + read-write + + + REGDMA_RST_EN + Set 0 to reset regdma module + 1 + 1 + read-write + + + + + TRACE_CONF + TRACE configuration register + 0xF8 + 0x20 + 0x00000001 + + + TRACE_CLK_EN + Set 1 to enable trace clock + 0 + 1 + read-write + + + TRACE_RST_EN + Set 0 to reset trace module + 1 + 1 + read-write + + + + + ASSIST_CONF + ASSIST configuration register + 0xFC + 0x20 + 0x00000001 + + + ASSIST_CLK_EN + Set 1 to enable assist clock + 0 + 1 + read-write + + + ASSIST_RST_EN + Set 0 to reset assist module + 1 + 1 + read-write + + + + + CACHE_CONF + CACHE configuration register + 0x100 + 0x20 + 0x00000001 + + + CACHE_CLK_EN + Set 1 to enable cache clock + 0 + 1 + read-write + + + CACHE_RST_EN + Set 0 to reset cache module + 1 + 1 + read-write + + + + + MODEM_CONF + MODEM_APB configuration register + 0x104 + 0x20 + 0x00000002 + + + MODEM_CLK_SEL + xxxx + 0 + 1 + read-write + + + MODEM_CLK_EN + xxxx + 1 + 1 + read-write + + + MODEM_RST_EN + Set this file as 1 to reset modem-subsystem. + 2 + 1 + read-write + + + + + TIMEOUT_CONF + TIMEOUT configuration register + 0x108 + 0x20 + + + CPU_TIMEOUT_RST_EN + Set 0 to reset cpu_peri timeout module + 1 + 1 + read-write + + + HP_TIMEOUT_RST_EN + Set 0 to reset hp_peri timeout module and hp_modem timeout module + 2 + 1 + read-write + + + + + SYSCLK_CONF + SYSCLK configuration register + 0x10C + 0x20 + 0x20000200 + + + LS_DIV_NUM + clk_hproot is div1 of low-speed clock-source if clck-source is a low-speed clock-source such as XTAL/FOSC. + 0 + 8 + read-only + + + HS_DIV_NUM + clk_hproot is div3 of SPLL if the clock-source is high-speed clock SPLL. + 8 + 8 + read-only + + + SOC_CLK_SEL + This field is used to select clock source. 0: XTAL, 1: SPLL, 2: FOSC, 3: reserved. + 16 + 2 + read-write + + + CLK_XTAL_FREQ + This field indicates the frequency(MHz) of XTAL. + 24 + 7 + read-only + + + + + CPU_WAITI_CONF + CPU_WAITI configuration register + 0x110 + 0x20 + 0x0000000D + + + CPUPERIOD_SEL + Reserved. This filed has been replaced by PCR_CPU_DIV_NUM + 0 + 2 + read-only + + + PLL_FREQ_SEL + Reserved. This filed has been replaced by PCR_CPU_DIV_NUM + 2 + 1 + read-only + + + CPU_WAIT_MODE_FORCE_ON + Set 1 to force cpu_waiti_clk enable. + 3 + 1 + read-write + + + CPU_WAITI_DELAY_NUM + This field used to set delay cycle when cpu enter waiti mode, after delay waiti_clk will close + 4 + 4 + read-write + + + + + CPU_FREQ_CONF + CPU_FREQ configuration register + 0x114 + 0x20 + + + CPU_DIV_NUM + Set this field to generate clk_cpu drived by clk_hproot. The clk_cpu is div1(default)/div2/div4 of clk_hproot. This field is only avaliable for low-speed clock-source such as XTAL/FOSC, and should be used together with PCR_AHB_DIV_NUM. + 0 + 8 + read-write + + + + + AHB_FREQ_CONF + AHB_FREQ configuration register + 0x118 + 0x20 + + + AHB_DIV_NUM + Set this field to generate clk_ahb drived by clk_hproot. The clk_ahb is div1(default)/div2/div4/div8 of clk_hproot. This field is only avaliable for low-speed clock-source such as XTAL/FOSC, and should be used together with PCR_CPU_DIV_NUM. + 0 + 8 + read-write + + + + + APB_FREQ_CONF + APB_FREQ configuration register + 0x11C + 0x20 + + + APB_DECREASE_DIV_NUM + If this field's value is grater than PCR_APB_DIV_NUM, the clk_apb will be automatically down to clk_apb_decrease only when no access is on apb-bus, and will recover to the previous frequency when a new access appears on apb-bus. Set as one within (0,1,3) to set clk_apb_decrease as div1/div2/div4(default) of clk_ahb. Note that enable this function will reduce performance. Users can set this field as zero to disable the auto-decrease-apb-freq function. By default, this function is disable. + 0 + 8 + read-write + + + APB_DIV_NUM + Set as one within (0,1,3) to generate clk_apb drived by clk_ahb. The clk_apb is div1(default)/div2/div4 of clk_ahb. + 8 + 8 + read-write + + + + + SYSCLK_FREQ_QUERY_0 + SYSCLK frequency query 0 register + 0x120 + 0x20 + 0x00006008 + + + FOSC_FREQ + This field indicates the frequency(MHz) of FOSC. + 0 + 8 + read-only + + + PLL_FREQ + This field indicates the frequency(MHz) of SPLL. + 8 + 10 + read-only + + + + + PLL_DIV_CLK_EN + SPLL DIV clock-gating configuration register + 0x124 + 0x20 + 0x0000003F + + + PLL_240M_CLK_EN + This field is used to open 96 MHz clock (SPLL) drived from SPLL. 0: close, 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + 0 + 1 + read-write + + + PLL_160M_CLK_EN + This field is used to open 64 MHz clock (div3 of SPLL) drived from SPLL. 0: close, 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + 1 + 1 + read-write + + + PLL_120M_CLK_EN + This field is used to open 48 MHz clock (div4 of SPLL) drived from SPLL. 0: close, 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + 2 + 1 + read-write + + + PLL_80M_CLK_EN + This field is used to open 32 MHz clock (div6 of SPLL) drived from SPLL. 0: close, 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + 3 + 1 + read-write + + + PLL_48M_CLK_EN + This field is used to open 16 MHz clock (div10 of SPLL) drived from SPLL. 0: close, 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + 4 + 1 + read-write + + + PLL_40M_CLK_EN + This field is used to open 8 MHz clock (div12 of SPLL) drived from SPLL. 0: close, 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + 5 + 1 + read-write + + + + + CTRL_CLK_OUT_EN + CLK_OUT_EN configuration register + 0x128 + 0x20 + 0x0000007F + + + CLK8_OEN + Set 1 to enable 8m clock + 0 + 1 + read-write + + + CLK16_OEN + Set 1 to enable 16m clock + 1 + 1 + read-write + + + CLK32_OEN + Set 1 to enable 32m clock + 2 + 1 + read-write + + + CLK_ADC_INF_OEN + Reserved + 3 + 1 + read-write + + + CLK_DFM_INF_OEN + Reserved + 4 + 1 + read-write + + + CLK_SDM_MOD_OEN + Reserved + 5 + 1 + read-write + + + CLK_XTAL_OEN + Set 1 to enable xtal clock + 6 + 1 + read-write + + + + + CTRL_TICK_CONF + TICK configuration register + 0x12C + 0x20 + 0x00010727 + + + XTAL_TICK_NUM + ******* Description *********** + 0 + 8 + read-write + + + FOSC_TICK_NUM + ******* Description *********** + 8 + 8 + read-write + + + TICK_ENABLE + ******* Description *********** + 16 + 1 + read-write + + + RST_TICK_CNT + ******* Description *********** + 17 + 1 + read-write + + + + + CTRL_32K_CONF + 32KHz clock configuration register + 0x130 + 0x20 + + + _32K_SEL + This field indicates which one 32KHz clock will be used by timergroup. 0: OSC32K(default), 1: XTAL32K, 2/3: 32KHz from pad GPIO0. + 0 + 2 + read-write + + + _32K_MODEM_SEL + This field indicates which one 32KHz clock will be used by MODEM_SYSTEM. 0: OSC32K(default), 1: XTAL32K, 2/3: 32KHz from pad GPIO0. + 2 + 2 + read-write + + + + + SRAM_POWER_CONF_0 + HP SRAM/ROM configuration register + 0x134 + 0x20 + 0x00006000 + + + ROM_FORCE_PU + Set this bit to force power up ROM + 13 + 2 + read-write + + + ROM_FORCE_PD + Set this bit to force power down ROM. + 15 + 2 + read-write + + + ROM_CLKGATE_FORCE_ON + 1: Force to open the clock and bypass the gate-clock when accessing the ROM. 0: A gate-clock will be used when accessing the ROM. + 17 + 2 + read-write + + + + + SRAM_POWER_CONF_1 + HP SRAM/ROM configuration register + 0x138 + 0x20 + 0x0000001F + + + SRAM_FORCE_PU + Set this bit to force power up SRAM + 0 + 5 + read-write + + + SRAM_FORCE_PD + Set this bit to force power down SRAM. + 10 + 5 + read-write + + + SRAM_CLKGATE_FORCE_ON + 1: Force to open the clock and bypass the gate-clock when accessing the SRAM. 0: A gate-clock will be used when accessing the SRAM. + 25 + 5 + read-write + + + + + SEC_CONF + xxxx + 0x13C + 0x20 + + + SEC_CLK_SEL + xxxx + 0 + 2 + read-write + + + + + ADC_INV_PHASE_CONF + xxxx + 0x140 + 0x20 + + + CLK_ADC_INV_PHASE_ENA + xxxx + 0 + 1 + read-write + + + + + SDM_INV_PHASE_CONF + xxxx + 0x144 + 0x20 + + + CLK_SDM_INV_PHASE_ENA + xxxx + 0 + 1 + read-write + + + CLK_SDM_INV_PHASE_SEL + xxxx + 1 + 3 + read-write + + + + + BUS_CLK_UPDATE + xxxx + 0x148 + 0x20 + + + BUS_CLOCK_UPDATE + xxxx + 0 + 1 + read-write + + + + + SAR_CLK_DIV + xxxx + 0x14C + 0x20 + 0x00000404 + + + SAR2_CLK_DIV_NUM + xxxx + 0 + 8 + read-write + + + SAR1_CLK_DIV_NUM + xxxx + 8 + 8 + read-write + + + + + PWDET_SAR_CLK_CONF + xxxx + 0x150 + 0x20 + 0x00000107 + + + PWDET_SAR_CLK_DIV_NUM + xxxx + 0 + 8 + read-write + + + PWDET_SAR_READER_EN + xxxx + 8 + 1 + read-write + + + + + RESET_EVENT_BYPASS + reset event bypass backdoor configuration register + 0xFF0 + 0x20 + 0x00000002 + + + APM + This field is used to control reset event relationship for tee_reg/apm_reg/hp_system_reg. 1: tee_reg/apm_reg/hp_system_reg will only be reset by power-reset. some reset event will be bypass. 0: tee_reg/apm_reg/hp_system_reg will not only be reset by power-reset, but also some reset event. + 0 + 1 + read-write + + + RESET_EVENT_BYPASS + This field is used to control reset event relationship for system-bus. 1: system bus (including arbiter/router) will only be reset by power-reset. some reset event will be bypass. 0: system bus (including arbiter/router) will not only be reset by power-reset, but also some reset event. + 1 + 1 + read-write + + + + + FPGA_DEBUG + fpga debug register + 0xFF4 + 0x20 + 0xFFFFFFFF + + + FPGA_DEBUG + Only used in fpga debug. + 0 + 32 + read-write + + + + + CLOCK_GATE + PCR clock gating configure register + 0xFF8 + 0x20 + + + CLK_EN + Set this bit as 1 to force on clock gating. + 0 + 1 + read-write + + + + + DATE + Date register. + 0xFFC + 0x20 + 0x02210080 + + + DATE + PCR version information. + 0 + 28 + read-write + + + + + + + PMU + Peripheral PMU + PMU + 0x600B0000 + + 0x0 + 0x1AC + registers + + + + HP_ACTIVE_DIG_POWER + need_des + 0x0 + 0x20 + + + HP_ACTIVE_VDD_SPI_PD_EN + need_des + 21 + 1 + read-write + + + HP_ACTIVE_HP_MEM_DSLP + need_des + 22 + 1 + read-write + + + HP_ACTIVE_PD_HP_MEM_PD_EN + need_des + 23 + 4 + read-write + + + HP_ACTIVE_PD_HP_WIFI_PD_EN + need_des + 27 + 1 + read-write + + + HP_ACTIVE_PD_HP_CPU_PD_EN + need_des + 29 + 1 + read-write + + + HP_ACTIVE_PD_HP_AON_PD_EN + need_des + 30 + 1 + read-write + + + HP_ACTIVE_PD_TOP_PD_EN + need_des + 31 + 1 + read-write + + + + + HP_ACTIVE_ICG_HP_FUNC + need_des + 0x4 + 0x20 + 0xFFFFFFFF + + + HP_ACTIVE_DIG_ICG_FUNC_EN + need_des + 0 + 32 + read-write + + + + + HP_ACTIVE_ICG_HP_APB + need_des + 0x8 + 0x20 + 0xFFFFFFFF + + + HP_ACTIVE_DIG_ICG_APB_EN + need_des + 0 + 32 + read-write + + + + + HP_ACTIVE_ICG_MODEM + need_des + 0xC + 0x20 + + + HP_ACTIVE_DIG_ICG_MODEM_CODE + need_des + 30 + 2 + read-write + + + + + HP_ACTIVE_HP_SYS_CNTL + need_des + 0x10 + 0x20 + + + HP_ACTIVE_UART_WAKEUP_EN + need_des + 24 + 1 + read-write + + + HP_ACTIVE_LP_PAD_HOLD_ALL + need_des + 25 + 1 + read-write + + + HP_ACTIVE_HP_PAD_HOLD_ALL + need_des + 26 + 1 + read-write + + + HP_ACTIVE_DIG_PAD_SLP_SEL + need_des + 27 + 1 + read-write + + + HP_ACTIVE_DIG_PAUSE_WDT + need_des + 28 + 1 + read-write + + + HP_ACTIVE_DIG_CPU_STALL + need_des + 29 + 1 + read-write + + + + + HP_ACTIVE_HP_CK_POWER + need_des + 0x14 + 0x20 + + + HP_ACTIVE_I2C_ISO_EN + need_des + 26 + 1 + read-write + + + HP_ACTIVE_I2C_RETENTION + need_des + 27 + 1 + read-write + + + HP_ACTIVE_XPD_BB_I2C + need_des + 28 + 1 + read-write + + + HP_ACTIVE_XPD_BBPLL_I2C + need_des + 29 + 1 + read-write + + + HP_ACTIVE_XPD_BBPLL + need_des + 30 + 1 + read-write + + + + + HP_ACTIVE_BIAS + need_des + 0x18 + 0x20 + 0x01000000 + + + HP_ACTIVE_XPD_TRX + need_des + 24 + 1 + read-write + + + HP_ACTIVE_XPD_BIAS + need_des + 25 + 1 + read-write + + + HP_ACTIVE_PD_CUR + need_des + 30 + 1 + read-write + + + SLEEP + need_des + 31 + 1 + read-write + + + + + HP_ACTIVE_BACKUP + need_des + 0x1C + 0x20 + + + HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE + need_des + 4 + 2 + read-write + + + HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE + need_des + 6 + 2 + read-write + + + HP_ACTIVE_RETENTION_MODE + need_des + 10 + 1 + read-write + + + HP_SLEEP2ACTIVE_RETENTION_EN + need_des + 11 + 1 + read-write + + + HP_MODEM2ACTIVE_RETENTION_EN + need_des + 12 + 1 + read-write + + + HP_SLEEP2ACTIVE_BACKUP_CLK_SEL + need_des + 14 + 2 + read-write + + + HP_MODEM2ACTIVE_BACKUP_CLK_SEL + need_des + 16 + 2 + read-write + + + HP_SLEEP2ACTIVE_BACKUP_MODE + need_des + 20 + 3 + read-write + + + HP_MODEM2ACTIVE_BACKUP_MODE + need_des + 23 + 3 + read-write + + + HP_SLEEP2ACTIVE_BACKUP_EN + need_des + 29 + 1 + read-write + + + HP_MODEM2ACTIVE_BACKUP_EN + need_des + 30 + 1 + read-write + + + + + HP_ACTIVE_BACKUP_CLK + need_des + 0x20 + 0x20 + + + HP_ACTIVE_BACKUP_ICG_FUNC_EN + need_des + 0 + 32 + read-write + + + + + HP_ACTIVE_SYSCLK + need_des + 0x24 + 0x20 + + + HP_ACTIVE_DIG_SYS_CLK_NO_DIV + need_des + 26 + 1 + read-write + + + HP_ACTIVE_ICG_SYS_CLOCK_EN + need_des + 27 + 1 + read-write + + + HP_ACTIVE_SYS_CLK_SLP_SEL + need_des + 28 + 1 + read-write + + + HP_ACTIVE_ICG_SLP_SEL + need_des + 29 + 1 + read-write + + + HP_ACTIVE_DIG_SYS_CLK_SEL + need_des + 30 + 2 + read-write + + + + + HP_ACTIVE_HP_REGULATOR0 + need_des + 0x28 + 0x20 + 0x84476110 + + + HP_ACTIVE_HP_POWER_DET_BYPASS + need_des + 0 + 1 + read-write + + + LP_DBIAS_VOL + need_des + 4 + 5 + read-only + + + HP_DBIAS_VOL + need_des + 9 + 5 + read-only + + + DIG_REGULATOR0_DBIAS_SEL + need_des + 14 + 1 + read-write + + + DIG_DBIAS_INIT + need_des + 15 + 1 + write-only + + + HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD + need_des + 16 + 1 + read-write + + + HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD + need_des + 17 + 1 + read-write + + + HP_ACTIVE_HP_REGULATOR_XPD + need_des + 18 + 1 + read-write + + + HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS + need_des + 19 + 4 + read-write + + + HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS + need_des + 23 + 4 + read-write + + + HP_ACTIVE_HP_REGULATOR_DBIAS + need_des + 27 + 5 + read-write + + + + + HP_ACTIVE_HP_REGULATOR1 + need_des + 0x2C + 0x20 + + + HP_ACTIVE_HP_REGULATOR_DRV_B + need_des + 8 + 24 + read-write + + + + + HP_ACTIVE_XTAL + need_des + 0x30 + 0x20 + 0x80000000 + + + HP_ACTIVE_XPD_XTAL + need_des + 31 + 1 + read-write + + + + + HP_MODEM_DIG_POWER + need_des + 0x34 + 0x20 + + + HP_MODEM_VDD_SPI_PD_EN + need_des + 21 + 1 + read-write + + + HP_MODEM_HP_MEM_DSLP + need_des + 22 + 1 + read-write + + + HP_MODEM_PD_HP_MEM_PD_EN + need_des + 23 + 4 + read-write + + + HP_MODEM_PD_HP_WIFI_PD_EN + need_des + 27 + 1 + read-write + + + HP_MODEM_PD_HP_CPU_PD_EN + need_des + 29 + 1 + read-write + + + HP_MODEM_PD_HP_AON_PD_EN + need_des + 30 + 1 + read-write + + + HP_MODEM_PD_TOP_PD_EN + need_des + 31 + 1 + read-write + + + + + HP_MODEM_ICG_HP_FUNC + need_des + 0x38 + 0x20 + 0xFFFFFFFF + + + HP_MODEM_DIG_ICG_FUNC_EN + need_des + 0 + 32 + read-write + + + + + HP_MODEM_ICG_HP_APB + need_des + 0x3C + 0x20 + 0xFFFFFFFF + + + HP_MODEM_DIG_ICG_APB_EN + need_des + 0 + 32 + read-write + + + + + HP_MODEM_ICG_MODEM + need_des + 0x40 + 0x20 + + + HP_MODEM_DIG_ICG_MODEM_CODE + need_des + 30 + 2 + read-write + + + + + HP_MODEM_HP_SYS_CNTL + need_des + 0x44 + 0x20 + + + HP_MODEM_UART_WAKEUP_EN + need_des + 24 + 1 + read-write + + + HP_MODEM_LP_PAD_HOLD_ALL + need_des + 25 + 1 + read-write + + + HP_MODEM_HP_PAD_HOLD_ALL + need_des + 26 + 1 + read-write + + + HP_MODEM_DIG_PAD_SLP_SEL + need_des + 27 + 1 + read-write + + + HP_MODEM_DIG_PAUSE_WDT + need_des + 28 + 1 + read-write + + + HP_MODEM_DIG_CPU_STALL + need_des + 29 + 1 + read-write + + + + + HP_MODEM_HP_CK_POWER + need_des + 0x48 + 0x20 + + + HP_MODEM_I2C_ISO_EN + need_des + 26 + 1 + read-write + + + HP_MODEM_I2C_RETENTION + need_des + 27 + 1 + read-write + + + HP_MODEM_XPD_BB_I2C + need_des + 28 + 1 + read-write + + + HP_MODEM_XPD_BBPLL_I2C + need_des + 29 + 1 + read-write + + + HP_MODEM_XPD_BBPLL + need_des + 30 + 1 + read-write + + + + + HP_MODEM_BIAS + need_des + 0x4C + 0x20 + 0x01000000 + + + HP_MODEM_XPD_TRX + need_des + 24 + 1 + read-write + + + HP_MODEM_XPD_BIAS + need_des + 25 + 1 + read-write + + + HP_MODEM_PD_CUR + need_des + 30 + 1 + read-write + + + SLEEP + need_des + 31 + 1 + read-write + + + + + HP_MODEM_BACKUP + need_des + 0x50 + 0x20 + + + HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE + need_des + 4 + 2 + read-write + + + HP_MODEM_RETENTION_MODE + need_des + 10 + 1 + read-write + + + HP_SLEEP2MODEM_RETENTION_EN + need_des + 11 + 1 + read-write + + + HP_SLEEP2MODEM_BACKUP_CLK_SEL + need_des + 14 + 2 + read-write + + + HP_SLEEP2MODEM_BACKUP_MODE + need_des + 20 + 3 + read-write + + + HP_SLEEP2MODEM_BACKUP_EN + need_des + 29 + 1 + read-write + + + + + HP_MODEM_BACKUP_CLK + need_des + 0x54 + 0x20 + + + HP_MODEM_BACKUP_ICG_FUNC_EN + need_des + 0 + 32 + read-write + + + + + HP_MODEM_SYSCLK + need_des + 0x58 + 0x20 + + + HP_MODEM_DIG_SYS_CLK_NO_DIV + need_des + 26 + 1 + read-write + + + HP_MODEM_ICG_SYS_CLOCK_EN + need_des + 27 + 1 + read-write + + + HP_MODEM_SYS_CLK_SLP_SEL + need_des + 28 + 1 + read-write + + + HP_MODEM_ICG_SLP_SEL + need_des + 29 + 1 + read-write + + + HP_MODEM_DIG_SYS_CLK_SEL + need_des + 30 + 2 + read-write + + + + + HP_MODEM_HP_REGULATOR0 + need_des + 0x5C + 0x20 + 0x84470000 + + + HP_MODEM_HP_POWER_DET_BYPASS + need_des + 0 + 1 + read-write + + + HP_MODEM_HP_REGULATOR_SLP_MEM_XPD + need_des + 16 + 1 + read-write + + + HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD + need_des + 17 + 1 + read-write + + + HP_MODEM_HP_REGULATOR_XPD + need_des + 18 + 1 + read-write + + + HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS + need_des + 19 + 4 + read-write + + + HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS + need_des + 23 + 4 + read-write + + + HP_MODEM_HP_REGULATOR_DBIAS + need_des + 27 + 5 + read-write + + + + + HP_MODEM_HP_REGULATOR1 + need_des + 0x60 + 0x20 + + + HP_MODEM_HP_REGULATOR_DRV_B + need_des + 8 + 24 + read-write + + + + + HP_MODEM_XTAL + need_des + 0x64 + 0x20 + 0x80000000 + + + HP_MODEM_XPD_XTAL + need_des + 31 + 1 + read-write + + + + + HP_SLEEP_DIG_POWER + need_des + 0x68 + 0x20 + + + HP_SLEEP_VDD_SPI_PD_EN + need_des + 21 + 1 + read-write + + + HP_SLEEP_HP_MEM_DSLP + need_des + 22 + 1 + read-write + + + HP_SLEEP_PD_HP_MEM_PD_EN + need_des + 23 + 4 + read-write + + + HP_SLEEP_PD_HP_WIFI_PD_EN + need_des + 27 + 1 + read-write + + + HP_SLEEP_PD_HP_CPU_PD_EN + need_des + 29 + 1 + read-write + + + HP_SLEEP_PD_HP_AON_PD_EN + need_des + 30 + 1 + read-write + + + HP_SLEEP_PD_TOP_PD_EN + need_des + 31 + 1 + read-write + + + + + HP_SLEEP_ICG_HP_FUNC + need_des + 0x6C + 0x20 + 0xFFFFFFFF + + + HP_SLEEP_DIG_ICG_FUNC_EN + need_des + 0 + 32 + read-write + + + + + HP_SLEEP_ICG_HP_APB + need_des + 0x70 + 0x20 + 0xFFFFFFFF + + + HP_SLEEP_DIG_ICG_APB_EN + need_des + 0 + 32 + read-write + + + + + HP_SLEEP_ICG_MODEM + need_des + 0x74 + 0x20 + + + HP_SLEEP_DIG_ICG_MODEM_CODE + need_des + 30 + 2 + read-write + + + + + HP_SLEEP_HP_SYS_CNTL + need_des + 0x78 + 0x20 + + + HP_SLEEP_UART_WAKEUP_EN + need_des + 24 + 1 + read-write + + + HP_SLEEP_LP_PAD_HOLD_ALL + need_des + 25 + 1 + read-write + + + HP_SLEEP_HP_PAD_HOLD_ALL + need_des + 26 + 1 + read-write + + + HP_SLEEP_DIG_PAD_SLP_SEL + need_des + 27 + 1 + read-write + + + HP_SLEEP_DIG_PAUSE_WDT + need_des + 28 + 1 + read-write + + + HP_SLEEP_DIG_CPU_STALL + need_des + 29 + 1 + read-write + + + + + HP_SLEEP_HP_CK_POWER + need_des + 0x7C + 0x20 + + + HP_SLEEP_I2C_ISO_EN + need_des + 26 + 1 + read-write + + + HP_SLEEP_I2C_RETENTION + need_des + 27 + 1 + read-write + + + HP_SLEEP_XPD_BB_I2C + need_des + 28 + 1 + read-write + + + HP_SLEEP_XPD_BBPLL_I2C + need_des + 29 + 1 + read-write + + + HP_SLEEP_XPD_BBPLL + need_des + 30 + 1 + read-write + + + + + HP_SLEEP_BIAS + need_des + 0x80 + 0x20 + 0x01000000 + + + HP_SLEEP_XPD_TRX + need_des + 24 + 1 + read-write + + + HP_SLEEP_XPD_BIAS + need_des + 25 + 1 + read-write + + + HP_SLEEP_PD_CUR + need_des + 30 + 1 + read-write + + + SLEEP + need_des + 31 + 1 + read-write + + + + + HP_SLEEP_BACKUP + need_des + 0x84 + 0x20 + + + HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE + need_des + 6 + 2 + read-write + + + HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE + need_des + 8 + 2 + read-write + + + HP_SLEEP_RETENTION_MODE + need_des + 10 + 1 + read-write + + + HP_MODEM2SLEEP_RETENTION_EN + need_des + 12 + 1 + read-write + + + HP_ACTIVE2SLEEP_RETENTION_EN + need_des + 13 + 1 + read-write + + + HP_MODEM2SLEEP_BACKUP_CLK_SEL + need_des + 16 + 2 + read-write + + + HP_ACTIVE2SLEEP_BACKUP_CLK_SEL + need_des + 18 + 2 + read-write + + + HP_MODEM2SLEEP_BACKUP_MODE + need_des + 23 + 3 + read-write + + + HP_ACTIVE2SLEEP_BACKUP_MODE + need_des + 26 + 3 + read-write + + + HP_MODEM2SLEEP_BACKUP_EN + need_des + 30 + 1 + read-write + + + HP_ACTIVE2SLEEP_BACKUP_EN + need_des + 31 + 1 + read-write + + + + + HP_SLEEP_BACKUP_CLK + need_des + 0x88 + 0x20 + + + HP_SLEEP_BACKUP_ICG_FUNC_EN + need_des + 0 + 32 + read-write + + + + + HP_SLEEP_SYSCLK + need_des + 0x8C + 0x20 + + + HP_SLEEP_DIG_SYS_CLK_NO_DIV + need_des + 26 + 1 + read-write + + + HP_SLEEP_ICG_SYS_CLOCK_EN + need_des + 27 + 1 + read-write + + + HP_SLEEP_SYS_CLK_SLP_SEL + need_des + 28 + 1 + read-write + + + HP_SLEEP_ICG_SLP_SEL + need_des + 29 + 1 + read-write + + + HP_SLEEP_DIG_SYS_CLK_SEL + need_des + 30 + 2 + read-write + + + + + HP_SLEEP_HP_REGULATOR0 + need_des + 0x90 + 0x20 + 0x84470000 + + + HP_SLEEP_HP_POWER_DET_BYPASS + need_des + 0 + 1 + read-write + + + HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD + need_des + 16 + 1 + read-write + + + HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD + need_des + 17 + 1 + read-write + + + HP_SLEEP_HP_REGULATOR_XPD + need_des + 18 + 1 + read-write + + + HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS + need_des + 19 + 4 + read-write + + + HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS + need_des + 23 + 4 + read-write + + + HP_SLEEP_HP_REGULATOR_DBIAS + need_des + 27 + 5 + read-write + + + + + HP_SLEEP_HP_REGULATOR1 + need_des + 0x94 + 0x20 + + + HP_SLEEP_HP_REGULATOR_DRV_B + need_des + 8 + 24 + read-write + + + + + HP_SLEEP_XTAL + need_des + 0x98 + 0x20 + 0x80000000 + + + HP_SLEEP_XPD_XTAL + need_des + 31 + 1 + read-write + + + + + HP_SLEEP_LP_REGULATOR0 + need_des + 0x9C + 0x20 + 0x8C600000 + + + HP_SLEEP_LP_REGULATOR_SLP_XPD + need_des + 21 + 1 + read-write + + + HP_SLEEP_LP_REGULATOR_XPD + need_des + 22 + 1 + read-write + + + HP_SLEEP_LP_REGULATOR_SLP_DBIAS + need_des + 23 + 4 + read-write + + + HP_SLEEP_LP_REGULATOR_DBIAS + need_des + 27 + 5 + read-write + + + + + HP_SLEEP_LP_REGULATOR1 + need_des + 0xA0 + 0x20 + + + HP_SLEEP_LP_REGULATOR_DRV_B + need_des + 28 + 4 + read-write + + + + + HP_SLEEP_LP_DCDC_RESERVE + need_des + 0xA4 + 0x20 + + + HP_SLEEP_LP_DCDC_RESERVE + need_des + 0 + 32 + write-only + + + + + HP_SLEEP_LP_DIG_POWER + need_des + 0xA8 + 0x20 + + + HP_SLEEP_BOD_SOURCE_SEL + need_des + 27 + 1 + read-write + + + HP_SLEEP_VDDBAT_MODE + need_des + 28 + 2 + read-write + + + HP_SLEEP_LP_MEM_DSLP + need_des + 30 + 1 + read-write + + + HP_SLEEP_PD_LP_PERI_PD_EN + need_des + 31 + 1 + read-write + + + + + HP_SLEEP_LP_CK_POWER + need_des + 0xAC + 0x20 + 0x40000000 + + + HP_SLEEP_XPD_LPPLL + need_des + 27 + 1 + read-write + + + HP_SLEEP_XPD_XTAL32K + need_des + 28 + 1 + read-write + + + HP_SLEEP_XPD_RC32K + need_des + 29 + 1 + read-write + + + HP_SLEEP_XPD_FOSC_CLK + need_des + 30 + 1 + read-write + + + HP_SLEEP_PD_OSC_CLK + need_des + 31 + 1 + read-write + + + + + LP_SLEEP_LP_BIAS_RESERVE + need_des + 0xB0 + 0x20 + + + LP_SLEEP_LP_BIAS_RESERVE + need_des + 0 + 32 + write-only + + + + + LP_SLEEP_LP_REGULATOR0 + need_des + 0xB4 + 0x20 + 0x8C600000 + + + LP_SLEEP_LP_REGULATOR_SLP_XPD + need_des + 21 + 1 + read-write + + + LP_SLEEP_LP_REGULATOR_XPD + need_des + 22 + 1 + read-write + + + LP_SLEEP_LP_REGULATOR_SLP_DBIAS + need_des + 23 + 4 + read-write + + + LP_SLEEP_LP_REGULATOR_DBIAS + need_des + 27 + 5 + read-write + + + + + LP_SLEEP_LP_REGULATOR1 + need_des + 0xB8 + 0x20 + + + LP_SLEEP_LP_REGULATOR_DRV_B + need_des + 28 + 4 + read-write + + + + + LP_SLEEP_XTAL + need_des + 0xBC + 0x20 + 0x80000000 + + + LP_SLEEP_XPD_XTAL + need_des + 31 + 1 + read-write + + + + + LP_SLEEP_LP_DIG_POWER + need_des + 0xC0 + 0x20 + + + LP_SLEEP_BOD_SOURCE_SEL + need_des + 27 + 1 + read-write + + + LP_SLEEP_VDDBAT_MODE + need_des + 28 + 2 + read-write + + + LP_SLEEP_LP_MEM_DSLP + need_des + 30 + 1 + read-write + + + LP_SLEEP_PD_LP_PERI_PD_EN + need_des + 31 + 1 + read-write + + + + + LP_SLEEP_LP_CK_POWER + need_des + 0xC4 + 0x20 + 0x40000000 + + + LP_SLEEP_XPD_LPPLL + need_des + 27 + 1 + read-write + + + LP_SLEEP_XPD_XTAL32K + need_des + 28 + 1 + read-write + + + LP_SLEEP_XPD_RC32K + need_des + 29 + 1 + read-write + + + LP_SLEEP_XPD_FOSC_CLK + need_des + 30 + 1 + read-write + + + LP_SLEEP_PD_OSC_CLK + need_des + 31 + 1 + read-write + + + + + LP_SLEEP_BIAS + need_des + 0xC8 + 0x20 + + + LP_SLEEP_XPD_BIAS + need_des + 25 + 1 + read-write + + + LP_SLEEP_PD_CUR + need_des + 30 + 1 + read-write + + + SLEEP + need_des + 31 + 1 + read-write + + + + + IMM_HP_CK_POWER + need_des + 0xCC + 0x20 + + + TIE_LOW_GLOBAL_BBPLL_ICG + need_des + 0 + 1 + write-only + + + TIE_LOW_GLOBAL_XTAL_ICG + need_des + 1 + 1 + write-only + + + TIE_LOW_I2C_RETENTION + need_des + 2 + 1 + write-only + + + TIE_LOW_XPD_BB_I2C + need_des + 3 + 1 + write-only + + + TIE_LOW_XPD_BBPLL_I2C + need_des + 4 + 1 + write-only + + + TIE_LOW_XPD_BBPLL + need_des + 5 + 1 + write-only + + + TIE_LOW_XPD_XTAL + need_des + 6 + 1 + write-only + + + TIE_HIGH_GLOBAL_BBPLL_ICG + need_des + 25 + 1 + write-only + + + TIE_HIGH_GLOBAL_XTAL_ICG + need_des + 26 + 1 + write-only + + + TIE_HIGH_I2C_RETENTION + need_des + 27 + 1 + write-only + + + TIE_HIGH_XPD_BB_I2C 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write-only + + + + + HP_REGULATOR_CFG + need_des + 0x18C + 0x20 + + + DIG_REGULATOR_EN_CAL + need_des + 31 + 1 + read-write + + + + + MAIN_STATE + need_des + 0x190 + 0x20 + 0x08100800 + + + MAIN_LAST_ST_STATE + need_des + 11 + 7 + read-only + + + MAIN_TAR_ST_STATE + need_des + 18 + 7 + read-only + + + MAIN_CUR_ST_STATE + need_des + 25 + 7 + read-only + + + + + PWR_STATE + need_des + 0x194 + 0x20 + 0x00802000 + + + BACKUP_ST_STATE + need_des + 13 + 5 + read-only + + + LP_PWR_ST_STATE + need_des + 18 + 5 + read-only + + + HP_PWR_ST_STATE + need_des + 23 + 9 + read-only + + + + + CLK_STATE0 + need_des + 0x198 + 0x20 + 0x00000003 + + + STABLE_XPD_BBPLL_STATE + need_des + 0 + 1 + read-only + + + STABLE_XPD_XTAL_STATE + need_des + 1 + 1 + read-only + + + SYS_CLK_SLP_SEL_STATE + need_des + 15 + 1 + read-only + + + SYS_CLK_SEL_STATE + need_des + 16 + 2 + read-only + + + SYS_CLK_NO_DIV_STATE + need_des + 18 + 1 + read-only + + + ICG_SYS_CLK_EN_STATE + need_des + 19 + 1 + read-only + + + ICG_MODEM_SWITCH_STATE + need_des + 20 + 1 + read-only + + + ICG_MODEM_CODE_STATE + need_des + 21 + 2 + read-only + + + ICG_SLP_SEL_STATE + need_des + 23 + 1 + read-only + + + ICG_GLOBAL_XTAL_STATE + need_des + 24 + 1 + read-only + + + ICG_GLOBAL_PLL_STATE + need_des + 25 + 1 + read-only + + + ANA_I2C_ISO_EN_STATE + need_des + 26 + 1 + read-only + + + ANA_I2C_RETENTION_STATE + need_des + 27 + 1 + read-only + + + ANA_XPD_BB_I2C_STATE + need_des + 28 + 1 + read-only + + + ANA_XPD_BBPLL_I2C_STATE + need_des + 29 + 1 + read-only + + + ANA_XPD_BBPLL_STATE + need_des + 30 + 1 + read-only + + + ANA_XPD_XTAL_STATE + need_des + 31 + 1 + read-only + + + + + CLK_STATE1 + need_des + 0x19C + 0x20 + 0xFFFFFFFF + + + ICG_FUNC_EN_STATE + need_des + 0 + 32 + read-only + + + + + CLK_STATE2 + need_des + 0x1A0 + 0x20 + 0xFFFFFFFF + + + ICG_APB_EN_STATE + need_des + 0 + 32 + read-only + + + + + VDD_SPI_STATUS + need_des + 0x1A4 + 0x20 + + + STABLE_VDD_SPI_PWR_DRV + need_des + 31 + 1 + read-only + + + + + DATE + need_des + 0x3FC + 0x20 + 0x02209200 + + + PMU_DATE + need_des + 0 + 31 + read-write + + + CLK_EN + need_des + 31 + 1 + read-write + + + + + + + RMT + Remote Control Peripheral + RMT + 0x60007000 + + 0x0 + 0x78 + registers + + + RMT + 28 + + + + 4 + 0x4 + TX_CH%sDATA + The read and write data register for CHANNEL%s by apb fifo access. + 0x0 + 0x20 + + + CHDATA + Read and write data for channel %s via APB FIFO. + 0 + 32 + read-only + + + + + 2 + 0x4 + TX_CH%sCONF0 + Channel %s configure register 0 + 0x10 + 0x20 + 0x00710200 + + + TX_START_CH0 + Set this bit to start sending data on CHANNEL%s. + 0 + 1 + write-only + + + MEM_RD_RST_CH0 + Set this bit to reset read ram address for CHANNEL%s by accessing transmitter. + 1 + 1 + write-only + + + APB_MEM_RST_CH0 + Set this bit to reset W/R ram address for CHANNEL%s by accessing apb fifo. + 2 + 1 + write-only + + + TX_CONTI_MODE_CH0 + Set this bit to restart transmission from the first data to the last data in CHANNEL%s. + 3 + 1 + read-write + + + MEM_TX_WRAP_EN_CH0 + This is the channel %s enable bit for wraparound mode: it will resume sending at the start when the data to be sent is more than its memory size. + 4 + 1 + read-write + + + IDLE_OUT_LV_CH0 + This bit configures the level of output signal in CHANNEL%s when the latter is in IDLE state. + 5 + 1 + read-write + + + IDLE_OUT_EN_CH0 + This is the output enable-control bit for CHANNEL%s in IDLE state. + 6 + 1 + read-write + + + TX_STOP_CH0 + Set this bit to stop the transmitter of CHANNEL%s sending data out. + 7 + 1 + read-write + + + DIV_CNT_CH0 + This register is used to configure the divider for clock of CHANNEL%s. + 8 + 8 + read-write + + + MEM_SIZE_CH0 + This register is used to configure the maximum size of memory allocated to CHANNEL%s. + 16 + 3 + read-write + + + CARRIER_EFF_EN_CH0 + 1: Add carrier modulation on the output signal only at the send data state for CHANNEL%s. 0: Add carrier modulation on the output signal at all state for CHANNEL%s. Only valid when RMT_CARRIER_EN_CH%s is 1. + 20 + 1 + read-write + + + CARRIER_EN_CH0 + This is the carrier modulation enable-control bit for CHANNEL%s. 1: Add carrier modulation in the output signal. 0: No carrier modulation in sig_out. + 21 + 1 + read-write + + + CARRIER_OUT_LV_CH0 + This bit is used to configure the position of carrier wave for CHANNEL%s. + +1'h0: add carrier wave on low level. + +1'h1: add carrier wave on high level. + 22 + 1 + read-write + + + AFIFO_RST_CH0 + Reserved + 23 + 1 + write-only + + + CONF_UPDATE_CH0 + synchronization bit for CHANNEL%s + 24 + 1 + write-only + + + + + 2 + 0x8 + RX_CH%sCONF0 + Channel %s configure register 0 + 0x18 + 0x20 + 0x30FFFF02 + + + DIV_CNT_CH2 + This register is used to configure the divider for clock of CHANNEL%s. + 0 + 8 + read-write + + + IDLE_THRES_CH2 + When no edge is detected on the input signal and continuous clock cycles is longer than this register value, received process is finished. + 8 + 15 + read-write + + + MEM_SIZE_CH2 + This register is used to configure the maximum size of memory allocated to CHANNEL%s. + 23 + 3 + read-write + + + CARRIER_EN_CH2 + This is the carrier modulation enable-control bit for CHANNEL%s. 1: Add carrier modulation in the output signal. 0: No carrier modulation in sig_out. + 28 + 1 + read-write + + + CARRIER_OUT_LV_CH2 + This bit is used to configure the position of carrier wave for CHANNEL%s. + +1'h0: add carrier wave on low level. + +1'h1: add carrier wave on high level. + 29 + 1 + read-write + + + + + 2 + 0x8 + RX_CH%sCONF1 + Channel %s configure register 1 + 0x1C + 0x20 + 0x000001E8 + + + RX_EN_CH2 + Set this bit to enable receiver to receive data on CHANNEL%s. + 0 + 1 + read-write + + + MEM_WR_RST_CH2 + Set this bit to reset write ram address for CHANNEL%s by accessing receiver. + 1 + 1 + write-only + + + APB_MEM_RST_CH2 + Set this bit to reset W/R ram address for CHANNEL%s by accessing apb fifo. + 2 + 1 + write-only + + + MEM_OWNER_CH2 + This register marks the ownership of CHANNEL%s's ram block. + +1'h1: Receiver is using the ram. + +1'h0: APB bus is using the ram. + 3 + 1 + read-write + + + RX_FILTER_EN_CH2 + This is the receive filter's enable bit for CHANNEL%s. + 4 + 1 + read-write + + + RX_FILTER_THRES_CH2 + Ignores the input pulse when its width is smaller than this register value in APB clock periods (in receive mode). + 5 + 8 + read-write + + + MEM_RX_WRAP_EN_CH2 + This is the channel %s enable bit for wraparound mode: it will resume receiving at the start when the data to be received is more than its memory size. + 13 + 1 + read-write + + + AFIFO_RST_CH2 + Reserved + 14 + 1 + write-only + + + CONF_UPDATE_CH2 + synchronization bit for CHANNEL%s + 15 + 1 + write-only + + + + + 2 + 0x4 + TX_CH%sSTATUS + Channel %s status register + 0x28 + 0x20 + + + MEM_RADDR_EX_CH0 + This register records the memory address offset when transmitter of CHANNEL%s is using the RAM. + 0 + 9 + read-only + + + STATE_CH0 + This register records the FSM status of CHANNEL%s. + 9 + 3 + read-only + + + APB_MEM_WADDR_CH0 + This register records the memory address offset when writes RAM over APB bus. + 12 + 9 + read-only + + + APB_MEM_RD_ERR_CH0 + This status bit will be set if the offset address out of memory size when reading via APB bus. + 21 + 1 + read-only + + + MEM_EMPTY_CH0 + This status bit will be set when the data to be set is more than memory size and the wraparound mode is disabled. + 22 + 1 + read-only + + + APB_MEM_WR_ERR_CH0 + This status bit will be set if the offset address out of memory size when writes via APB bus. + 23 + 1 + read-only + + + APB_MEM_RADDR_CH0 + This register records the memory address offset when reading RAM over APB bus. + 24 + 8 + read-only + + + + + 2 + 0x4 + RX_CH%sSTATUS + Channel %s status register + 0x30 + 0x20 + + + MEM_WADDR_EX_CH2 + This register records the memory address offset when receiver of CHANNEL%s is using the RAM. + 0 + 9 + read-only + + + APB_MEM_RADDR_CH2 + This register records the memory address offset when reads RAM over APB bus. + 12 + 9 + read-only + + + STATE_CH2 + This register records the FSM status of CHANNEL%s. + 22 + 3 + read-only + + + MEM_OWNER_ERR_CH2 + This status bit will be set when the ownership of memory block is wrong. + 25 + 1 + read-only + + + MEM_FULL_CH2 + This status bit will be set if the receiver receives more data than the memory size. + 26 + 1 + read-only + + + APB_MEM_RD_ERR_CH2 + This status bit will be set if the offset address out of memory size when reads via APB bus. + 27 + 1 + read-only + + + + + INT_RAW + Raw interrupt status + 0x38 + 0x20 + + + CH0_TX_END_INT_RAW + The interrupt raw bit for CHANNEL0. Triggered when transmission done. + 0 + 1 + read-only + + + CH1_TX_END_INT_RAW + The interrupt raw bit for CHANNEL1. Triggered when transmission done. + 1 + 1 + read-only + + + CH2_RX_END_INT_RAW + The interrupt raw bit for CHANNEL2. Triggered when reception done. + 2 + 1 + read-only + + + CH3_RX_END_INT_RAW + The interrupt raw bit for CHANNEL3. Triggered when reception done. + 3 + 1 + read-only + + + TX_CH0_ERR_INT_RAW + The interrupt raw bit for CHANNEL4. Triggered when error occurs. + 4 + 1 + read-only + + + TX_CH1_ERR_INT_RAW + The interrupt raw bit for CHANNEL5. Triggered when error occurs. + 5 + 1 + read-only + + + TX_CH2_ERR_INT_RAW + The interrupt raw bit for CHANNEL6. Triggered when error occurs. + 6 + 1 + read-only + + + TX_CH3_ERR_INT_RAW + The interrupt raw bit for CHANNEL7. Triggered when error occurs. + 7 + 1 + read-only + + + CH0_TX_THR_EVENT_INT_RAW + The interrupt raw bit for CHANNEL0. Triggered when transmitter sent more data than configured value. + 8 + 1 + read-only + + + CH1_TX_THR_EVENT_INT_RAW + The interrupt raw bit for CHANNEL1. Triggered when transmitter sent more data than configured value. + 9 + 1 + read-only + + + CH2_RX_THR_EVENT_INT_RAW + The interrupt raw bit for CHANNEL2. Triggered when receiver receive more data than configured value. + 10 + 1 + read-only + + + CH3_RX_THR_EVENT_INT_RAW + The interrupt raw bit for CHANNEL3. Triggered when receiver receive more data than configured value. + 11 + 1 + read-only + + + CH0_TX_LOOP_INT_RAW + The interrupt raw bit for CHANNEL0. Triggered when the loop count reaches the configured threshold value. + 12 + 1 + read-only + + + CH1_TX_LOOP_INT_RAW + The interrupt raw bit for CHANNEL1. Triggered when the loop count reaches the configured threshold value. + 13 + 1 + read-only + + + + + INT_ST + Masked interrupt status + 0x3C + 0x20 + + + CH0_TX_END_INT_ST + The masked interrupt status bit for CH0_TX_END_INT. + 0 + 1 + read-only + + + CH1_TX_END_INT_ST + The masked interrupt status bit for CH1_TX_END_INT. + 1 + 1 + read-only + + + CH2_RX_END_INT_ST + The masked interrupt status bit for CH2_RX_END_INT. + 2 + 1 + read-only + + + CH3_RX_END_INT_ST + The masked interrupt status bit for CH3_RX_END_INT. + 3 + 1 + read-only + + + RX_CH0_ERR_INT_ST + The masked interrupt status bit for CH4_ERR_INT. + 4 + 1 + read-only + + + RX_CH1_ERR_INT_ST + The masked interrupt status bit for CH5_ERR_INT. + 5 + 1 + read-only + + + RX_CH2_ERR_INT_ST + The masked interrupt status bit for CH6_ERR_INT. + 6 + 1 + read-only + + + RX_CH3_ERR_INT_ST + The masked interrupt status bit for CH7_ERR_INT. + 7 + 1 + read-only + + + CH0_TX_THR_EVENT_INT_ST + The masked interrupt status bit for CH0_TX_THR_EVENT_INT. + 8 + 1 + read-only + + + CH1_TX_THR_EVENT_INT_ST + The masked interrupt status bit for CH1_TX_THR_EVENT_INT. + 9 + 1 + read-only + + + CH2_RX_THR_EVENT_INT_ST + The masked interrupt status bit for CH2_RX_THR_EVENT_INT. + 10 + 1 + read-only + + + CH3_RX_THR_EVENT_INT_ST + The masked interrupt status bit for CH3_RX_THR_EVENT_INT. + 11 + 1 + read-only + + + CH0_TX_LOOP_INT_ST + The masked interrupt status bit for CH0_TX_LOOP_INT. + 12 + 1 + read-only + + + CH1_TX_LOOP_INT_ST + The masked interrupt status bit for CH1_TX_LOOP_INT. + 13 + 1 + read-only + + + + + INT_ENA + Interrupt enable bits + 0x40 + 0x20 + + + CH0_TX_END_INT_ENA + The interrupt enable bit for CH0_TX_END_INT. + 0 + 1 + read-write + + + CH1_TX_END_INT_ENA + The interrupt enable bit for CH1_TX_END_INT. + 1 + 1 + read-write + + + CH2_RX_END_INT_ENA + The interrupt enable bit for CH2_RX_END_INT. + 2 + 1 + read-write + + + CH3_RX_END_INT_ENA + The interrupt enable bit for CH3_RX_END_INT. + 3 + 1 + read-write + + + CH0_ERR_INT_ENA + The interrupt enable bit for CH4_ERR_INT. + 4 + 1 + read-write + + + CH1_ERR_INT_ENA + The interrupt enable bit for CH5_ERR_INT. + 5 + 1 + read-write + + + CH2_ERR_INT_ENA + The interrupt enable bit for CH6_ERR_INT. + 6 + 1 + read-write + + + CH3_ERR_INT_ENA + The interrupt enable bit for CH7_ERR_INT. + 7 + 1 + read-write + + + CH0_TX_THR_EVENT_INT_ENA + The interrupt enable bit for CH0_TX_THR_EVENT_INT. + 8 + 1 + read-write + + + CH1_TX_THR_EVENT_INT_ENA + The interrupt enable bit for CH1_TX_THR_EVENT_INT. + 9 + 1 + read-write + + + CH2_RX_THR_EVENT_INT_ENA + The interrupt enable bit for CH2_RX_THR_EVENT_INT. + 10 + 1 + read-write + + + CH3_RX_THR_EVENT_INT_ENA + The interrupt enable bit for CH3_RX_THR_EVENT_INT. + 11 + 1 + read-write + + + CH0_TX_LOOP_INT_ENA + The interrupt enable bit for CH0_TX_LOOP_INT. + 12 + 1 + read-write + + + CH1_TX_LOOP_INT_ENA + The interrupt enable bit for CH1_TX_LOOP_INT. + 13 + 1 + read-write + + + + + INT_CLR + Interrupt clear bits + 0x44 + 0x20 + + + CH0_TX_END_INT_CLR + Set this bit to clear theCH0_TX_END_INT interrupt. + 0 + 1 + write-only + + + CH1_TX_END_INT_CLR + Set this bit to clear theCH1_TX_END_INT interrupt. + 1 + 1 + write-only + + + CH2_RX_END_INT_CLR + Set this bit to clear theCH2_RX_END_INT interrupt. + 2 + 1 + write-only + + + CH3_RX_END_INT_CLR + Set this bit to clear theCH3_RX_END_INT interrupt. + 3 + 1 + write-only + + + RX_CH0_ERR_INT_CLR + Set this bit to clear theCH4_ERR_INT interrupt. + 4 + 1 + write-only + + + RX_CH1_ERR_INT_CLR + Set this bit to clear theCH5_ERR_INT interrupt. + 5 + 1 + write-only + + + RX_CH2_ERR_INT_CLR + Set this bit to clear theCH6_ERR_INT interrupt. + 6 + 1 + write-only + + + RX_CH3_ERR_INT_CLR + Set this bit to clear theCH7_ERR_INT interrupt. + 7 + 1 + write-only + + + CH0_TX_THR_EVENT_INT_CLR + Set this bit to clear theCH0_TX_THR_EVENT_INT interrupt. + 8 + 1 + write-only + + + CH1_TX_THR_EVENT_INT_CLR + Set this bit to clear theCH1_TX_THR_EVENT_INT interrupt. + 9 + 1 + write-only + + + CH2_RX_THR_EVENT_INT_CLR + Set this bit to clear theCH2_RX_THR_EVENT_INT interrupt. + 10 + 1 + write-only + + + CH3_RX_THR_EVENT_INT_CLR + Set this bit to clear theCH3_RX_THR_EVENT_INT interrupt. + 11 + 1 + write-only + + + CH0_TX_LOOP_INT_CLR + Set this bit to clear theCH0_TX_LOOP_INT interrupt. + 12 + 1 + write-only + + + CH1_TX_LOOP_INT_CLR + Set this bit to clear theCH1_TX_LOOP_INT interrupt. + 13 + 1 + write-only + + + + + 2 + 0x4 + CH%sCARRIER_DUTY + Channel %s duty cycle configuration register + 0x48 + 0x20 + 0x00400040 + + + CARRIER_LOW_CH0 + This register is used to configure carrier wave 's low level clock period for CHANNEL%s. + 0 + 16 + read-write + + + CARRIER_HIGH_CH0 + This register is used to configure carrier wave 's high level clock period for CHANNEL%s. + 16 + 16 + read-write + + + + + 2 + 0x4 + CH%s_RX_CARRIER_RM + Channel %s carrier remove register + 0x50 + 0x20 + + + CARRIER_LOW_THRES_CH2 + The low level period in a carrier modulation mode is (REG_RMT_REG_CARRIER_LOW_THRES_CH%s + 1) for channel %s. + 0 + 16 + read-write + + + CARRIER_HIGH_THRES_CH2 + The high level period in a carrier modulation mode is (REG_RMT_REG_CARRIER_HIGH_THRES_CH%s + 1) for channel %s. + 16 + 16 + read-write + + + + + 2 + 0x4 + CH%s_TX_LIM + Channel %s Tx event configuration register + 0x58 + 0x20 + 0x00000080 + + + TX_LIM_CH0 + This register is used to configure the maximum entries that CHANNEL%s can send out. + 0 + 9 + read-write + + + TX_LOOP_NUM_CH0 + This register is used to configure the maximum loop count when tx_conti_mode is valid. + 9 + 10 + read-write + + + TX_LOOP_CNT_EN_CH0 + This register is the enabled bit for loop count. + 19 + 1 + read-write + + + LOOP_COUNT_RESET_CH0 + This register is used to reset the loop count when tx_conti_mode is valid. + 20 + 1 + write-only + + + LOOP_STOP_EN_CH0 + This bit is used to enable the loop send stop function after the loop counter counts to loop number for CHANNEL%s. + 21 + 1 + read-write + + + + + 2 + 0x4 + CH%s_RX_LIM + Channel %s Rx event configuration register + 0x60 + 0x20 + 0x00000080 + + + RMT_RX_LIM_CH2 + This register is used to configure the maximum entries that CHANNEL%s can receive. + 0 + 9 + read-write + + + + + SYS_CONF + RMT apb configuration register + 0x68 + 0x20 + 0x05000010 + + + APB_FIFO_MASK + 1'h1: access memory directly. 1'h0: access memory by FIFO. + 0 + 1 + read-write + + + MEM_CLK_FORCE_ON + Set this bit to enable the clock for RMT memory. + 1 + 1 + read-write + + + RMT_MEM_FORCE_PD + Set this bit to power down RMT memory. + 2 + 1 + read-write + + + RMT_MEM_FORCE_PU + 1: Disable RMT memory light sleep power down function. 0: Power down RMT memory when RMT is in light sleep mode. + 3 + 1 + read-write + + + RMT_SCLK_DIV_NUM + the integral part of the fractional divisor + 4 + 8 + read-write + + + RMT_SCLK_DIV_A + the numerator of the fractional part of the fractional divisor + 12 + 6 + read-write + + + RMT_SCLK_DIV_B + the denominator of the fractional part of the fractional divisor + 18 + 6 + read-write + + + RMT_SCLK_SEL + choose the clock source of rmt_sclk. 1:CLK_80Mhz,2:CLK_FOSC, 3:XTAL + 24 + 2 + read-write + + + RMT_SCLK_ACTIVE + rmt_sclk switch + 26 + 1 + read-write + + + CLK_EN + RMT register clock gate enable signal. 1: Power up the drive clock of registers. 0: Power down the drive clock of registers + 31 + 1 + read-write + + + + + TX_SIM + RMT TX synchronous register + 0x6C + 0x20 + + + CH0 + Set this bit to enable CHANNEL0 to start sending data synchronously with other enabled channels. + 0 + 1 + read-write + + + CH1 + Set this bit to enable CHANNEL1 to start sending data synchronously with other enabled channels. + 1 + 1 + read-write + + + EN + This register is used to enable multiple of channels to start sending data synchronously. + 2 + 1 + read-write + + + + + REF_CNT_RST + RMT clock divider reset register + 0x70 + 0x20 + + + TX_REF_CNT_RST_CH0 + This register is used to reset the clock divider of CHANNEL0. + 0 + 1 + write-only + + + TX_REF_CNT_RST_CH1 + This register is used to reset the clock divider of CHANNEL1. + 1 + 1 + write-only + + + RX_REF_CNT_RST_CH2 + This register is used to reset the clock divider of CHANNEL2. + 2 + 1 + write-only + + + RX_REF_CNT_RST_CH3 + This register is used to reset the clock divider of CHANNEL3. + 3 + 1 + write-only + + + + + DATE + RMT version register + 0xCC + 0x20 + 0x02108213 + + + RMT_DATE + This is the version register. + 0 + 28 + read-write + + + + + + + RNG + Hardware random number generator + RNG + 0x600260B0 + + 0x0 + 0x4 + registers + + + + DATA + Random number data + 0x0 + 0x20 + + + + + RSA + RSA (Rivest Shamir Adleman) Accelerator + RSA + 0x6008A000 + + 0x0 + 0x74 + registers + + + RSA + 47 + + + + 16 + 0x1 + M_MEM[%s] + Represents M + 0x0 + 0x8 + + + 16 + 0x1 + Z_MEM[%s] + Represents Z + 0x200 + 0x8 + + + 16 + 0x1 + Y_MEM[%s] + Represents Y + 0x400 + 0x8 + + + 16 + 0x1 + X_MEM[%s] + Represents X + 0x600 + 0x8 + + + M_PRIME + Represents M’ + 0x800 + 0x20 + + + M_PRIME + Represents M’ + 0 + 32 + read-write + + + + + MODE + Configures RSA length + 0x804 + 0x20 + + + MODE + Configures the RSA length. + 0 + 7 + read-write + + + + + QUERY_CLEAN + RSA clean register + 0x808 + 0x20 + + + QUERY_CLEAN + Represents whether or not the RSA memory completes initialization. + +0: Not complete + +1: Completed + + + 0 + 1 + read-only + + + + + SET_START_MODEXP + Starts modular exponentiation + 0x80C + 0x20 + + + SET_START_MODEXP + Configure whether or not to start the modular exponentiation. + +0: No effect + +1: Start + + + 0 + 1 + write-only + + + + + SET_START_MODMULT + Starts modular multiplication + 0x810 + 0x20 + + + SET_START_MODMULT + Configure whether or not to start the modular multiplication. + +0: No effect + +1: Start + + + 0 + 1 + write-only + + + + + SET_START_MULT + Starts multiplication + 0x814 + 0x20 + + + SET_START_MULT + Configure whether or not to start the multiplication. + +0: No effect + +1: Start + + + 0 + 1 + write-only + + + + + QUERY_IDLE + Represents the RSA status + 0x818 + 0x20 + + + QUERY_IDLE + Represents the RSA status. + +0: Busy + +1: Idle + + + 0 + 1 + read-only + + + + + INT_CLR + Clears RSA interrupt + 0x81C + 0x20 + + + CLEAR_INTERRUPT + Write 1 to clear the RSA interrupt. + 0 + 1 + write-only + + + + + CONSTANT_TIME + Configures the constant_time option + 0x820 + 0x20 + 0x00000001 + + + CONSTANT_TIME + Configures the constant_time option. + +0: Acceleration + +1: No acceleration (default) + + + 0 + 1 + read-write + + + + + SEARCH_ENABLE + Configures the search option + 0x824 + 0x20 + + + SEARCH_ENABLE + Configure the search option. + +0: No acceleration (default) + +1: Acceleration + +This option should be used together with RSA_SEARCH_POS. + 0 + 1 + read-write + + + + + SEARCH_POS + Configures the search position + 0x828 + 0x20 + + + SEARCH_POS + Configures the starting address to start search. This field should be used together with RSA_SEARCH_ENABLE. The field is only valid when RSA_SEARCH_ENABLE is high. + 0 + 12 + read-write + + + + + INT_ENA + Enables the RSA interrupt + 0x82C + 0x20 + + + INT_ENA + Write 1 to enable the RSA interrupt. + 0 + 1 + read-write + + + + + DATE + Version control register + 0x830 + 0x20 + 0x20200618 + + + DATE + Version control register. + 0 + 30 + read-write + + + + + + + SHA + SHA (Secure Hash Algorithm) Accelerator + SHA + 0x60089000 + + 0x0 + 0xB0 + registers + + + SHA + 49 + + + + MODE + Initial configuration register. + 0x0 + 0x20 + + + MODE + Sha mode. + 0 + 3 + read-write + + + + + T_STRING + SHA 512/t configuration register 0. + 0x4 + 0x20 + + + T_STRING + Sha t_string (used if and only if mode == SHA_512/t). + 0 + 32 + read-write + + + + + T_LENGTH + SHA 512/t configuration register 1. + 0x8 + 0x20 + + + T_LENGTH + Sha t_length (used if and only if mode == SHA_512/t). + 0 + 6 + read-write + + + + + DMA_BLOCK_NUM + DMA configuration register 0. + 0xC + 0x20 + + + DMA_BLOCK_NUM + Dma-sha block number. + 0 + 6 + read-write + + + + + START + Typical SHA configuration register 0. + 0x10 + 0x20 + + + START + Reserved. + 1 + 31 + read-only + + + + + CONTINUE + Typical SHA configuration register 1. + 0x14 + 0x20 + + + CONTINUE + Reserved. + 1 + 31 + read-only + + + + + BUSY + Busy register. + 0x18 + 0x20 + + + STATE + Sha busy state. 1'b0: idle. 1'b1: busy. + 0 + 1 + read-only + + + + + DMA_START + DMA configuration register 1. + 0x1C + 0x20 + + + DMA_START + Start dma-sha. + 0 + 1 + write-only + + + + + DMA_CONTINUE + DMA configuration register 2. + 0x20 + 0x20 + + + DMA_CONTINUE + Continue dma-sha. + 0 + 1 + write-only + + + + + CLEAR_IRQ + Interrupt clear register. + 0x24 + 0x20 + + + CLEAR_INTERRUPT + Clear sha interrupt. + 0 + 1 + write-only + + + + + IRQ_ENA + Interrupt enable register. + 0x28 + 0x20 + + + INTERRUPT_ENA + Sha interrupt enable register. 1'b0: disable(default). 1'b1: enable. + 0 + 1 + read-write + + + + + DATE + Date register. + 0x2C + 0x20 + 0x20201229 + + + DATE + Sha date information/ sha version information. + 0 + 30 + read-write + + + + + 64 + 0x1 + H_MEM[%s] + Sha H memory which contains intermediate hash or finial hash. + 0x40 + 0x8 + + + 64 + 0x1 + M_MEM[%s] + Sha M memory which contains message. + 0x80 + 0x8 + + + + + SOC_ETM + Peripheral SOC_ETM + SOC_ETM + 0x60013000 + + 0x0 + 0x1B0 + registers + + - EVT_TASK_EN2 - Ledc event task enable bit register2. - 0x1A8 + CH_ENA_AD0 + channel enable register + 0x0 0x20 - TASK_GAMMA_RESTART_CH0_EN - Ledc ch0 gamma restart task enable register, write 1 to enable this task. + CH_ENA0 + ch0 enable 0 1 read-write - TASK_GAMMA_RESTART_CH1_EN - Ledc ch1 gamma restart task enable register, write 1 to enable this task. + CH_ENA1 + ch1 enable 1 1 read-write - TASK_GAMMA_RESTART_CH2_EN - Ledc ch2 gamma restart task enable register, write 1 to enable this task. + CH_ENA2 + ch2 enable 2 1 read-write - TASK_GAMMA_RESTART_CH3_EN - Ledc ch3 gamma restart task enable register, write 1 to enable this task. + CH_ENA3 + ch3 enable 3 1 read-write - TASK_GAMMA_RESTART_CH4_EN - Ledc ch4 gamma restart task enable register, write 1 to enable this task. + CH_ENA4 + ch4 enable 4 1 read-write - TASK_GAMMA_RESTART_CH5_EN - Ledc ch5 gamma restart task enable register, write 1 to enable this task. + CH_ENA5 + ch5 enable 5 1 read-write - TASK_GAMMA_PAUSE_CH0_EN - Ledc ch0 gamma pause task enable register, write 1 to enable this task. + CH_ENA6 + ch6 enable + 6 + 1 + read-write + + + CH_ENA7 + ch7 enable + 7 + 1 + read-write + + + CH_ENA8 + ch8 enable 8 1 read-write - TASK_GAMMA_PAUSE_CH1_EN - Ledc ch1 gamma pause task enable register, write 1 to enable this task. + CH_ENA9 + ch9 enable 9 1 read-write - TASK_GAMMA_PAUSE_CH2_EN - Ledc ch2 gamma pause task enable register, write 1 to enable this task. + CH_ENA10 + ch10 enable 10 1 read-write - TASK_GAMMA_PAUSE_CH3_EN - Ledc ch3 gamma pause task enable register, write 1 to enable this task. + CH_ENA11 + ch11 enable 11 1 read-write - TASK_GAMMA_PAUSE_CH4_EN - Ledc ch4 gamma pause task enable register, write 1 to enable this task. + CH_ENA12 + ch12 enable 12 1 read-write - TASK_GAMMA_PAUSE_CH5_EN - Ledc ch5 gamma pause task enable register, write 1 to enable this task. + CH_ENA13 + ch13 enable 13 1 read-write - TASK_GAMMA_RESUME_CH0_EN - Ledc ch0 gamma resume task enable register, write 1 to enable this task. + CH_ENA14 + ch14 enable + 14 + 1 + read-write + + + CH_ENA15 + ch15 enable + 15 + 1 + read-write + + + CH_ENA16 + ch16 enable 16 1 read-write - TASK_GAMMA_RESUME_CH1_EN - Ledc ch1 gamma resume task enable register, write 1 to enable this task. + CH_ENA17 + ch17 enable 17 1 read-write - TASK_GAMMA_RESUME_CH2_EN - Ledc ch2 gamma resume task enable register, write 1 to enable this task. + CH_ENA18 + ch18 enable 18 1 read-write - TASK_GAMMA_RESUME_CH3_EN - Ledc ch3 gamma resume task enable register, write 1 to enable this task. + CH_ENA19 + ch19 enable 19 1 read-write - TASK_GAMMA_RESUME_CH4_EN - Ledc ch4 gamma resume task enable register, write 1 to enable this task. + CH_ENA20 + ch20 enable 20 1 read-write - TASK_GAMMA_RESUME_CH5_EN - Ledc ch5 gamma resume task enable register, write 1 to enable this task. + CH_ENA21 + ch21 enable 21 1 read-write - - - - 4 - 0x4 - TIMER%s_CMP - Ledc timer%s compare value register. - 0x1B0 - 0x20 - - TIMER_CMP - This register stores ledc timer%s compare value. - 0 - 20 + CH_ENA22 + ch22 enable + 22 + 1 read-write - - - - 4 - 0x4 - TIMER%s_CNT_CAP - Ledc timer%s count value capture register. - 0x1C0 - 0x20 - - - TIMER_CNT_CAP - This register stores ledc timer%s count value. - 0 - 20 - read-only - - - - - CONF - Global ledc configuration register - 0x1F0 - 0x20 - - APB_CLK_SEL - This bit is used to select clock source for the 4 timers . - -2'd1: APB_CLK 2'd2: RTC8M_CLK 2'd3: XTAL_CLK - 0 - 2 + CH_ENA23 + ch23 enable + 23 + 1 read-write - GAMMA_RAM_CLK_EN_CH0 - This bit is used to control clock. - -1'b1: Force clock on for gamma ram. 1'h0: Support clock only when application writes or read gamma ram. - 2 + CH_ENA24 + ch24 enable + 24 1 read-write - GAMMA_RAM_CLK_EN_CH1 - This bit is used to control clock. - -1'b1: Force clock on for gamma ram. 1'h0: Support clock only when application writes or read gamma ram. - 3 + CH_ENA25 + ch25 enable + 25 1 read-write - GAMMA_RAM_CLK_EN_CH2 - This bit is used to control clock. - -1'b1: Force clock on for gamma ram. 1'h0: Support clock only when application writes or read gamma ram. - 4 + CH_ENA26 + ch26 enable + 26 1 read-write - GAMMA_RAM_CLK_EN_CH3 - This bit is used to control clock. - -1'b1: Force clock on for gamma ram. 1'h0: Support clock only when application writes or read gamma ram. - 5 + CH_ENA27 + ch27 enable + 27 1 read-write - GAMMA_RAM_CLK_EN_CH4 - This bit is used to control clock. - -1'b1: Force clock on for gamma ram. 1'h0: Support clock only when application writes or read gamma ram. - 6 + CH_ENA28 + ch28 enable + 28 1 read-write - GAMMA_RAM_CLK_EN_CH5 - This bit is used to control clock. - -1'b1: Force clock on for gamma ram. 1'h0: Support clock only when application writes or read gamma ram. - 7 + CH_ENA29 + ch29 enable + 29 1 read-write - CLK_EN - This bit is used to control clock. - -1'b1: Force clock on for register. 1'h0: Support clock only when application writes registers. - 31 + CH_ENA30 + ch30 enable + 30 1 read-write - - - - DATE - Version control register - 0x1FC - 0x20 - 0x02111150 - - LEDC_DATE - This is the version control register. - 0 - 28 + CH_ENA31 + ch31 enable + 31 + 1 read-write - - - - PCNT - Pulse Counter - PCNT - 0x60017000 - - 0x0 - 0x68 - registers - - - 4 - 0xC - U%s_CONF0 - Configuration register 0 for unit %s - 0x0 + CH_ENA_AD0_SET + channel enable set register + 0x4 0x20 - 0x00003C10 - FILTER_THRES_U - This sets the maximum threshold, in APB_CLK cycles, for the filter. - -Any pulses with width less than this will be ignored when the filter is enabled. + CH_SET0 + ch0 set 0 - 10 - read-write - - - FILTER_EN_U - This is the enable bit for unit %s's input filter. - 10 1 - read-write + write-only - THR_ZERO_EN_U - This is the enable bit for unit %s's zero comparator. - 11 + CH_SET1 + ch1 set + 1 1 - read-write + write-only - THR_H_LIM_EN_U - This is the enable bit for unit %s's thr_h_lim comparator. Configures it to enable the high limit interrupt. - 12 + CH_SET2 + ch2 set + 2 1 - read-write + write-only - THR_L_LIM_EN_U - This is the enable bit for unit %s's thr_l_lim comparator. Configures it to enable the low limit interrupt. - 13 + CH_SET3 + ch3 set + 3 1 - read-write + write-only - THR_THRES0_EN_U - This is the enable bit for unit %s's thres0 comparator. - 14 + CH_SET4 + ch4 set + 4 1 - read-write + write-only - THR_THRES1_EN_U - This is the enable bit for unit %s's thres1 comparator. - 15 + CH_SET5 + ch5 set + 5 1 - read-write - - - CH0_NEG_MODE_U - This register sets the behavior when the signal input of channel 0 detects a negative edge. - -1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter - 16 - 2 - read-write - - - CH0_POS_MODE_U - This register sets the behavior when the signal input of channel 0 detects a positive edge. - -1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter - 18 - 2 - read-write - - - CH0_HCTRL_MODE_U - This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is high. - -0: No modification.1: Invert behavior (increase -> decrease, decrease -> increase).2, 3: Inhibit counter modification - 20 - 2 - read-write - - - CH0_LCTRL_MODE_U - This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is low. - -0: No modification.1: Invert behavior (increase -> decrease, decrease -> increase).2, 3: Inhibit counter modification - 22 - 2 - read-write - - - CH1_NEG_MODE_U - This register sets the behavior when the signal input of channel 1 detects a negative edge. - -1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter - 24 - 2 - read-write - - - CH1_POS_MODE_U - This register sets the behavior when the signal input of channel 1 detects a positive edge. - -1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter - 26 - 2 - read-write - - - CH1_HCTRL_MODE_U - This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is high. - -0: No modification.1: Invert behavior (increase -> decrease, decrease -> increase).2, 3: Inhibit counter modification - 28 - 2 - read-write - - - CH1_LCTRL_MODE_U - This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is low. - -0: No modification.1: Invert behavior (increase -> decrease, decrease -> increase).2, 3: Inhibit counter modification - 30 - 2 - read-write - - - - - 4 - 0xC - U%s_CONF1 - Configuration register 1 for unit %s - 0x4 - 0x20 - - - CNT_THRES0_U - This register is used to configure the thres0 value for unit %s. - 0 - 16 - read-write + write-only - CNT_THRES1_U - This register is used to configure the thres1 value for unit %s. - 16 - 16 - read-write + CH_SET6 + ch6 set + 6 + 1 + write-only - - - - 4 - 0xC - U%s_CONF2 - Configuration register 2 for unit %s - 0x8 - 0x20 - - CNT_H_LIM_U - This register is used to configure the thr_h_lim value for unit %s. When pluse_cnt reaches this value, the counter will be cleared to 0. - 0 - 16 - read-write + CH_SET7 + ch7 set + 7 + 1 + write-only - CNT_L_LIM_U - This register is used to configure the thr_l_lim value for unit %s. When pluse_cnt reaches this value, the counter will be cleared to 0. - 16 - 16 - read-write + CH_SET8 + ch8 set + 8 + 1 + write-only - - - - 4 - 0x4 - U%s_CNT - Counter value for unit %s - 0x30 - 0x20 - - PULSE_CNT_U - This register stores the current pulse count value for unit %s. - 0 - 16 - read-only + CH_SET9 + ch9 set + 9 + 1 + write-only - - - - INT_RAW - Interrupt raw status register - 0x40 - 0x20 - - CNT_THR_EVENT_U0_INT_RAW - The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. - 0 + CH_SET10 + ch10 set + 10 1 - read-only + write-only - CNT_THR_EVENT_U1_INT_RAW - The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. - 1 + CH_SET11 + ch11 set + 11 1 - read-only + write-only - CNT_THR_EVENT_U2_INT_RAW - The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. - 2 + CH_SET12 + ch12 set + 12 1 - read-only + write-only - CNT_THR_EVENT_U3_INT_RAW - The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. - 3 + CH_SET13 + ch13 set + 13 1 - read-only + write-only - - - - INT_ST - Interrupt status register - 0x44 - 0x20 - - CNT_THR_EVENT_U0_INT_ST - The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. - 0 + CH_SET14 + ch14 set + 14 1 - read-only + write-only - CNT_THR_EVENT_U1_INT_ST - The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. - 1 + CH_SET15 + ch15 set + 15 1 - read-only + write-only - CNT_THR_EVENT_U2_INT_ST - The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. - 2 + CH_SET16 + ch16 set + 16 1 - read-only + write-only - CNT_THR_EVENT_U3_INT_ST - The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. - 3 + CH_SET17 + ch17 set + 17 1 - read-only + write-only - - - - INT_ENA - Interrupt enable register - 0x48 - 0x20 - - CNT_THR_EVENT_U0_INT_ENA - The interrupt enable bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. - 0 + CH_SET18 + ch18 set + 18 1 - read-write + write-only - CNT_THR_EVENT_U1_INT_ENA - The interrupt enable bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. - 1 + CH_SET19 + ch19 set + 19 1 - read-write + write-only - CNT_THR_EVENT_U2_INT_ENA - The interrupt enable bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. - 2 + CH_SET20 + ch20 set + 20 1 - read-write + write-only - CNT_THR_EVENT_U3_INT_ENA - The interrupt enable bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. - 3 + CH_SET21 + ch21 set + 21 1 - read-write + write-only - - - - INT_CLR - Interrupt clear register - 0x4C - 0x20 - - CNT_THR_EVENT_U0_INT_CLR - Set this bit to clear the PCNT_CNT_THR_EVENT_U0_INT interrupt. - 0 + CH_SET22 + ch22 set + 22 1 write-only - CNT_THR_EVENT_U1_INT_CLR - Set this bit to clear the PCNT_CNT_THR_EVENT_U1_INT interrupt. - 1 + CH_SET23 + ch23 set + 23 1 write-only - CNT_THR_EVENT_U2_INT_CLR - Set this bit to clear the PCNT_CNT_THR_EVENT_U2_INT interrupt. - 2 + CH_SET24 + ch24 set + 24 1 write-only - CNT_THR_EVENT_U3_INT_CLR - Set this bit to clear the PCNT_CNT_THR_EVENT_U3_INT interrupt. - 3 + CH_SET25 + ch25 set + 25 1 write-only - - - - 4 - 0x4 - U%s_STATUS - PNCT UNIT%s status register - 0x50 - 0x20 - - - CNT_THR_ZERO_MODE_U - The pulse counter status of PCNT_U%s corresponding to 0. 0: pulse counter decreases from positive to 0. 1: pulse counter increases from negative to 0. 2: pulse counter is negative. 3: pulse counter is positive. - 0 - 2 - read-only + + CH_SET26 + ch26 set + 26 + 1 + write-only - CNT_THR_THRES1_LAT_U - The latched value of thres1 event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thres1 and thres1 event is valid. 0: others - 2 + CH_SET27 + ch27 set + 27 1 - read-only + write-only - CNT_THR_THRES0_LAT_U - The latched value of thres0 event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thres0 and thres0 event is valid. 0: others - 3 + CH_SET28 + ch28 set + 28 1 - read-only + write-only - CNT_THR_L_LIM_LAT_U - The latched value of low limit event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thr_l_lim and low limit event is valid. 0: others - 4 + CH_SET29 + ch29 set + 29 1 - read-only + write-only - CNT_THR_H_LIM_LAT_U - The latched value of high limit event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thr_h_lim and high limit event is valid. 0: others - 5 + CH_SET30 + ch30 set + 30 1 - read-only + write-only - CNT_THR_ZERO_LAT_U - The latched value of zero threshold event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to 0 and zero threshold event is valid. 0: others - 6 + CH_SET31 + ch31 set + 31 1 - read-only + write-only - CTRL - Control register for all counters - 0x60 + CH_ENA_AD0_CLR + channel enable clear register + 0x8 0x20 - 0x00000001 - PULSE_CNT_RST_U0 - Set this bit to clear unit 0's counter. + CH_CLR0 + ch0 clear 0 1 - read-write + write-only - CNT_PAUSE_U0 - Set this bit to freeze unit 0's counter. + CH_CLR1 + ch1 clear 1 1 - read-write + write-only - PULSE_CNT_RST_U1 - Set this bit to clear unit 1's counter. + CH_CLR2 + ch2 clear 2 1 - read-write + write-only - CNT_PAUSE_U1 - Set this bit to freeze unit 1's counter. + CH_CLR3 + ch3 clear 3 1 - read-write + write-only - PULSE_CNT_RST_U2 - Set this bit to clear unit 2's counter. + CH_CLR4 + ch4 clear 4 1 - read-write + write-only - CNT_PAUSE_U2 - Set this bit to freeze unit 2's counter. + CH_CLR5 + ch5 clear 5 1 - read-write + write-only - PULSE_CNT_RST_U3 - Set this bit to clear unit 3's counter. + CH_CLR6 + ch6 clear 6 1 - read-write + write-only - CNT_PAUSE_U3 - Set this bit to freeze unit 3's counter. + CH_CLR7 + ch7 clear 7 1 - read-write + write-only - CLK_EN - The registers clock gate enable signal of PCNT module. 1: the registers can be read and written by application. 0: the registers can not be read or written by application - 16 + CH_CLR8 + ch8 clear + 8 1 - read-write - - - - - DATE - PCNT version control register - 0xFC - 0x20 - 0x18072600 - - - DATE - This is the PCNT version control register. - 0 - 32 - read-write + write-only - - - - - - RMT - Remote Control Peripheral - RMT - 0x60016000 - - 0x0 - 0x78 - registers - - - RMT - 28 - - - - 4 - 0x4 - TX_CH%sDATA - The read and write data register for CHANNEL%s by apb fifo access. - 0x0 - 0x20 - - CHDATA - Read and write data for channel %s via APB FIFO. - 0 - 32 - read-only + CH_CLR9 + ch9 clear + 9 + 1 + write-only - - - - 2 - 0x4 - TX_CH%sCONF0 - Channel %s configure register 0 - 0x10 - 0x20 - 0x00710200 - - TX_START_CH0 - Set this bit to start sending data on CHANNEL%s. - 0 + CH_CLR10 + ch10 clear + 10 1 write-only - MEM_RD_RST_CH0 - Set this bit to reset read ram address for CHANNEL%s by accessing transmitter. - 1 + CH_CLR11 + ch11 clear + 11 1 write-only - APB_MEM_RST_CH0 - Set this bit to reset W/R ram address for CHANNEL%s by accessing apb fifo. - 2 + CH_CLR12 + ch12 clear + 12 1 write-only - TX_CONTI_MODE_CH0 - Set this bit to restart transmission from the first data to the last data in CHANNEL%s. - 3 + CH_CLR13 + ch13 clear + 13 1 - read-write + write-only - MEM_TX_WRAP_EN_CH0 - This is the channel %s enable bit for wraparound mode: it will resume sending at the start when the data to be sent is more than its memory size. - 4 + CH_CLR14 + ch14 clear + 14 1 - read-write + write-only - IDLE_OUT_LV_CH0 - This bit configures the level of output signal in CHANNEL%s when the latter is in IDLE state. - 5 + CH_CLR15 + ch15 clear + 15 1 - read-write + write-only - IDLE_OUT_EN_CH0 - This is the output enable-control bit for CHANNEL%s in IDLE state. - 6 + CH_CLR16 + ch16 clear + 16 1 - read-write + write-only - TX_STOP_CH0 - Set this bit to stop the transmitter of CHANNEL%s sending data out. - 7 + CH_CLR17 + ch17 clear + 17 1 - read-write + write-only - DIV_CNT_CH0 - This register is used to configure the divider for clock of CHANNEL%s. - 8 - 8 - read-write + CH_CLR18 + ch18 clear + 18 + 1 + write-only - MEM_SIZE_CH0 - This register is used to configure the maximum size of memory allocated to CHANNEL%s. - 16 - 3 - read-write + CH_CLR19 + ch19 clear + 19 + 1 + write-only - CARRIER_EFF_EN_CH0 - 1: Add carrier modulation on the output signal only at the send data state for CHANNEL%s. 0: Add carrier modulation on the output signal at all state for CHANNEL%s. Only valid when RMT_CARRIER_EN_CH%s is 1. + CH_CLR20 + ch20 clear 20 1 - read-write + write-only - CARRIER_EN_CH0 - This is the carrier modulation enable-control bit for CHANNEL%s. 1: Add carrier modulation in the output signal. 0: No carrier modulation in sig_out. + CH_CLR21 + ch21 clear 21 1 - read-write + write-only - CARRIER_OUT_LV_CH0 - This bit is used to configure the position of carrier wave for CHANNEL%s. - -1'h0: add carrier wave on low level. - -1'h1: add carrier wave on high level. + CH_CLR22 + ch22 clear 22 1 - read-write + write-only - AFIFO_RST_CH0 - Reserved + CH_CLR23 + ch23 clear 23 1 write-only - CONF_UPDATE_CH0 - synchronization bit for CHANNEL%s + CH_CLR24 + ch24 clear 24 1 write-only - - - - 2 - 0x8 - RX_CH%sCONF0 - Channel %s configure register 0 - 0x18 - 0x20 - 0x30FFFF02 - - DIV_CNT_CH2 - This register is used to configure the divider for clock of CHANNEL%s. - 0 - 8 - read-write + CH_CLR25 + ch25 clear + 25 + 1 + write-only - IDLE_THRES_CH2 - When no edge is detected on the input signal and continuous clock cycles is longer than this register value, received process is finished. - 8 - 15 - read-write + CH_CLR26 + ch26 clear + 26 + 1 + write-only - MEM_SIZE_CH2 - This register is used to configure the maximum size of memory allocated to CHANNEL%s. - 23 - 3 - read-write + CH_CLR27 + ch27 clear + 27 + 1 + write-only - CARRIER_EN_CH2 - This is the carrier modulation enable-control bit for CHANNEL%s. 1: Add carrier modulation in the output signal. 0: No carrier modulation in sig_out. + CH_CLR28 + ch28 clear 28 1 - read-write + write-only - CARRIER_OUT_LV_CH2 - This bit is used to configure the position of carrier wave for CHANNEL%s. - -1'h0: add carrier wave on low level. - -1'h1: add carrier wave on high level. + CH_CLR29 + ch29 clear 29 1 - read-write + write-only + + + CH_CLR30 + ch30 clear + 30 + 1 + write-only + + + CH_CLR31 + ch31 clear + 31 + 1 + write-only - 2 - 0x8 - RX_CH%sCONF1 - Channel %s configure register 1 - 0x1C + CH_ENA_AD1 + channel enable register + 0xC 0x20 - 0x000001E8 - RX_EN_CH2 - Set this bit to enable receiver to receive data on CHANNEL%s. + CH_ENA32 + ch32 enable 0 1 read-write - MEM_WR_RST_CH2 - Set this bit to reset write ram address for CHANNEL%s by accessing receiver. + CH_ENA33 + ch33 enable 1 1 - write-only + read-write - APB_MEM_RST_CH2 - Set this bit to reset W/R ram address for CHANNEL%s by accessing apb fifo. + CH_ENA34 + ch34 enable 2 1 - write-only + read-write - MEM_OWNER_CH2 - This register marks the ownership of CHANNEL%s's ram block. - -1'h1: Receiver is using the ram. - -1'h0: APB bus is using the ram. + CH_ENA35 + ch35 enable 3 1 read-write - RX_FILTER_EN_CH2 - This is the receive filter's enable bit for CHANNEL%s. + CH_ENA36 + ch36 enable 4 1 read-write - RX_FILTER_THRES_CH2 - Ignores the input pulse when its width is smaller than this register value in APB clock periods (in receive mode). + CH_ENA37 + ch37 enable 5 - 8 + 1 read-write - MEM_RX_WRAP_EN_CH2 - This is the channel %s enable bit for wraparound mode: it will resume receiving at the start when the data to be received is more than its memory size. - 13 + CH_ENA38 + ch38 enable + 6 1 read-write - AFIFO_RST_CH2 - Reserved - 14 + CH_ENA39 + ch39 enable + 7 1 - write-only + read-write - CONF_UPDATE_CH2 - synchronization bit for CHANNEL%s - 15 + CH_ENA40 + ch40 enable + 8 1 - write-only - - - - - 2 - 0x4 - TX_CH%sSTATUS - Channel %s status register - 0x28 - 0x20 - - - MEM_RADDR_EX_CH0 - This register records the memory address offset when transmitter of CHANNEL%s is using the RAM. - 0 - 9 - read-only + read-write - STATE_CH0 - This register records the FSM status of CHANNEL%s. + CH_ENA41 + ch41 enable 9 - 3 - read-only - - - APB_MEM_WADDR_CH0 - This register records the memory address offset when writes RAM over APB bus. - 12 - 9 - read-only - - - APB_MEM_RD_ERR_CH0 - This status bit will be set if the offset address out of memory size when reading via APB bus. - 21 1 - read-only + read-write - MEM_EMPTY_CH0 - This status bit will be set when the data to be set is more than memory size and the wraparound mode is disabled. - 22 + CH_ENA42 + ch42 enable + 10 1 - read-only + read-write - APB_MEM_WR_ERR_CH0 - This status bit will be set if the offset address out of memory size when writes via APB bus. - 23 + CH_ENA43 + ch43 enable + 11 1 - read-only - - - APB_MEM_RADDR_CH0 - This register records the memory address offset when reading RAM over APB bus. - 24 - 8 - read-only + read-write - - - - 2 - 0x4 - RX_CH%sSTATUS - Channel %s status register - 0x30 - 0x20 - - MEM_WADDR_EX_CH2 - This register records the memory address offset when receiver of CHANNEL%s is using the RAM. - 0 - 9 - read-only + CH_ENA44 + ch44 enable + 12 + 1 + read-write - APB_MEM_RADDR_CH2 - This register records the memory address offset when reads RAM over APB bus. - 12 - 9 - read-only + CH_ENA45 + ch45 enable + 13 + 1 + read-write - STATE_CH2 - This register records the FSM status of CHANNEL%s. - 22 - 3 - read-only + CH_ENA46 + ch46 enable + 14 + 1 + read-write - MEM_OWNER_ERR_CH2 - This status bit will be set when the ownership of memory block is wrong. - 25 + CH_ENA47 + ch47 enable + 15 1 - read-only + read-write - MEM_FULL_CH2 - This status bit will be set if the receiver receives more data than the memory size. - 26 + CH_ENA48 + ch48 enable + 16 1 - read-only + read-write - APB_MEM_RD_ERR_CH2 - This status bit will be set if the offset address out of memory size when reads via APB bus. - 27 + CH_ENA49 + ch49 enable + 17 1 - read-only + read-write - INT_RAW - Raw interrupt status - 0x38 + CH_ENA_AD1_SET + channel enable set register + 0x10 0x20 - CH0_TX_END_INT_RAW - The interrupt raw bit for CHANNEL0. Triggered when transmission done. + CH_SET32 + ch32 set 0 1 - read-only + write-only - CH1_TX_END_INT_RAW - The interrupt raw bit for CHANNEL1. Triggered when transmission done. + CH_SET33 + ch33 set 1 1 - read-only + write-only - CH2_RX_END_INT_RAW - The interrupt raw bit for CHANNEL2. Triggered when reception done. + CH_SET34 + ch34 set 2 1 - read-only + write-only - CH3_RX_END_INT_RAW - The interrupt raw bit for CHANNEL3. Triggered when reception done. + CH_SET35 + ch35 set 3 1 - read-only + write-only - TX_CH0_ERR_INT_RAW - The interrupt raw bit for CHANNEL4. Triggered when error occurs. + CH_SET36 + ch36 set 4 1 - read-only + write-only - TX_CH1_ERR_INT_RAW - The interrupt raw bit for CHANNEL5. Triggered when error occurs. + CH_SET37 + ch37 set 5 1 - read-only + write-only - TX_CH2_ERR_INT_RAW - The interrupt raw bit for CHANNEL6. Triggered when error occurs. + CH_SET38 + ch38 set 6 1 - read-only + write-only - TX_CH3_ERR_INT_RAW - The interrupt raw bit for CHANNEL7. Triggered when error occurs. + CH_SET39 + ch39 set 7 1 - read-only + write-only - CH0_TX_THR_EVENT_INT_RAW - The interrupt raw bit for CHANNEL0. Triggered when transmitter sent more data than configured value. + CH_SET40 + ch40 set 8 1 - read-only + write-only - CH1_TX_THR_EVENT_INT_RAW - The interrupt raw bit for CHANNEL1. Triggered when transmitter sent more data than configured value. + CH_SET41 + ch41 set 9 1 - read-only + write-only - CH2_RX_THR_EVENT_INT_RAW - The interrupt raw bit for CHANNEL2. Triggered when receiver receive more data than configured value. + CH_SET42 + ch42 set 10 1 - read-only + write-only - CH3_RX_THR_EVENT_INT_RAW - The interrupt raw bit for CHANNEL3. Triggered when receiver receive more data than configured value. + CH_SET43 + ch43 set 11 1 - read-only + write-only - CH0_TX_LOOP_INT_RAW - The interrupt raw bit for CHANNEL0. Triggered when the loop count reaches the configured threshold value. + CH_SET44 + ch44 set 12 1 - read-only + write-only - CH1_TX_LOOP_INT_RAW - The interrupt raw bit for CHANNEL1. Triggered when the loop count reaches the configured threshold value. + CH_SET45 + ch45 set 13 1 - read-only + write-only + + + CH_SET46 + ch46 set + 14 + 1 + write-only + + + CH_SET47 + ch47 set + 15 + 1 + write-only + + + CH_SET48 + ch48 set + 16 + 1 + write-only + + + CH_SET49 + ch49 set + 17 + 1 + write-only - INT_ST - Masked interrupt status - 0x3C + CH_ENA_AD1_CLR + channel enable clear register + 0x14 0x20 - CH0_TX_END_INT_ST - The masked interrupt status bit for CH0_TX_END_INT. + CH_CLR32 + ch32 clear 0 1 - read-only + write-only - CH1_TX_END_INT_ST - The masked interrupt status bit for CH1_TX_END_INT. + CH_CLR33 + ch33 clear 1 1 - read-only + write-only - CH2_RX_END_INT_ST - The masked interrupt status bit for CH2_RX_END_INT. + CH_CLR34 + ch34 clear 2 1 - read-only + write-only - CH3_RX_END_INT_ST - The masked interrupt status bit for CH3_RX_END_INT. + CH_CLR35 + ch35 clear 3 1 - read-only + write-only - RX_CH0_ERR_INT_ST - The masked interrupt status bit for CH4_ERR_INT. + CH_CLR36 + ch36 clear 4 1 - read-only + write-only - RX_CH1_ERR_INT_ST - The masked interrupt status bit for CH5_ERR_INT. + CH_CLR37 + ch37 clear 5 1 - read-only + write-only - RX_CH2_ERR_INT_ST - The masked interrupt status bit for CH6_ERR_INT. + CH_CLR38 + ch38 clear 6 1 - read-only + write-only - RX_CH3_ERR_INT_ST - The masked interrupt status bit for CH7_ERR_INT. + CH_CLR39 + ch39 clear 7 1 - read-only + write-only - CH0_TX_THR_EVENT_INT_ST - The masked interrupt status bit for CH0_TX_THR_EVENT_INT. + CH_CLR40 + ch40 clear 8 1 - read-only + write-only - CH1_TX_THR_EVENT_INT_ST - The masked interrupt status bit for CH1_TX_THR_EVENT_INT. + CH_CLR41 + ch41 clear 9 1 - read-only + write-only - CH2_RX_THR_EVENT_INT_ST - The masked interrupt status bit for CH2_RX_THR_EVENT_INT. + CH_CLR42 + ch42 clear 10 1 - read-only + write-only - CH3_RX_THR_EVENT_INT_ST - The masked interrupt status bit for CH3_RX_THR_EVENT_INT. + CH_CLR43 + ch43 clear 11 1 - read-only + write-only - CH0_TX_LOOP_INT_ST - The masked interrupt status bit for CH0_TX_LOOP_INT. + CH_CLR44 + ch44 clear 12 1 - read-only + write-only - CH1_TX_LOOP_INT_ST - The masked interrupt status bit for CH1_TX_LOOP_INT. + CH_CLR45 + ch45 clear 13 1 - read-only + write-only + + + CH_CLR46 + ch46 clear + 14 + 1 + write-only + + + CH_CLR47 + ch47 clear + 15 + 1 + write-only + + + CH_CLR48 + ch48 clear + 16 + 1 + write-only + + + CH_CLR49 + ch49 clear + 17 + 1 + write-only - INT_ENA - Interrupt enable bits + CH0_EVT_ID + channel0 event id register + 0x18 + 0x20 + + + CH0_EVT_ID + ch0_evt_id + 0 + 8 + read-write + + + + + CH0_TASK_ID + channel0 task id register + 0x1C + 0x20 + + + CH0_TASK_ID + ch0_task_id + 0 + 8 + read-write + + + + + CH1_EVT_ID + channel1 event id register + 0x20 + 0x20 + + + CH1_EVT_ID + ch1_evt_id + 0 + 8 + read-write + + + + + CH1_TASK_ID + channel1 task id register + 0x24 + 0x20 + + + CH1_TASK_ID + ch1_task_id + 0 + 8 + read-write + + + + + CH2_EVT_ID + channel2 event id register + 0x28 + 0x20 + + + CH2_EVT_ID + ch2_evt_id + 0 + 8 + read-write + + + + + CH2_TASK_ID + channel2 task id register + 0x2C + 0x20 + + + CH2_TASK_ID + ch2_task_id + 0 + 8 + read-write + + + + + CH3_EVT_ID + channel3 event id register + 0x30 + 0x20 + + + CH3_EVT_ID + ch3_evt_id + 0 + 8 + read-write + + + + + CH3_TASK_ID + channel3 task id register + 0x34 + 0x20 + + + CH3_TASK_ID + ch3_task_id + 0 + 8 + read-write + + + + + CH4_EVT_ID + channel4 event id register + 0x38 + 0x20 + + + CH4_EVT_ID + ch4_evt_id + 0 + 8 + read-write + + + + + CH4_TASK_ID + channel4 task id register + 0x3C + 0x20 + + + CH4_TASK_ID + ch4_task_id + 0 + 8 + read-write + + + + + CH5_EVT_ID + channel5 event id register 0x40 0x20 - CH0_TX_END_INT_ENA - The interrupt enable bit for CH0_TX_END_INT. + CH5_EVT_ID + ch5_evt_id 0 - 1 + 8 read-write + + + + CH5_TASK_ID + channel5 task id register + 0x44 + 0x20 + - CH1_TX_END_INT_ENA - The interrupt enable bit for CH1_TX_END_INT. - 1 - 1 + CH5_TASK_ID + ch5_task_id + 0 + 8 read-write + + + + CH6_EVT_ID + channel6 event id register + 0x48 + 0x20 + - CH2_RX_END_INT_ENA - The interrupt enable bit for CH2_RX_END_INT. - 2 - 1 + CH6_EVT_ID + ch6_evt_id + 0 + 8 read-write + + + + CH6_TASK_ID + channel6 task id register + 0x4C + 0x20 + - CH3_RX_END_INT_ENA - The interrupt enable bit for CH3_RX_END_INT. - 3 - 1 + CH6_TASK_ID + ch6_task_id + 0 + 8 read-write + + + + CH7_EVT_ID + channel7 event id register + 0x50 + 0x20 + - CH0_ERR_INT_ENA - The interrupt enable bit for CH4_ERR_INT. - 4 - 1 + CH7_EVT_ID + ch7_evt_id + 0 + 8 read-write + + + + CH7_TASK_ID + channel7 task id register + 0x54 + 0x20 + - CH1_ERR_INT_ENA - The interrupt enable bit for CH5_ERR_INT. - 5 - 1 + CH7_TASK_ID + ch7_task_id + 0 + 8 read-write + + + + CH8_EVT_ID + channel8 event id register + 0x58 + 0x20 + - CH2_ERR_INT_ENA - The interrupt enable bit for CH6_ERR_INT. - 6 - 1 + CH8_EVT_ID + ch8_evt_id + 0 + 8 read-write + + + + CH8_TASK_ID + channel8 task id register + 0x5C + 0x20 + - CH3_ERR_INT_ENA - The interrupt enable bit for CH7_ERR_INT. - 7 - 1 + CH8_TASK_ID + ch8_task_id + 0 + 8 read-write + + + + CH9_EVT_ID + channel9 event id register + 0x60 + 0x20 + - CH0_TX_THR_EVENT_INT_ENA - The interrupt enable bit for CH0_TX_THR_EVENT_INT. - 8 - 1 + CH9_EVT_ID + ch9_evt_id + 0 + 8 read-write + + + + CH9_TASK_ID + channel9 task id register + 0x64 + 0x20 + - CH1_TX_THR_EVENT_INT_ENA - The interrupt enable bit for CH1_TX_THR_EVENT_INT. - 9 - 1 + CH9_TASK_ID + ch9_task_id + 0 + 8 read-write + + + + CH10_EVT_ID + channel10 event id register + 0x68 + 0x20 + - CH2_RX_THR_EVENT_INT_ENA - The interrupt enable bit for CH2_RX_THR_EVENT_INT. - 10 - 1 + CH10_EVT_ID + ch10_evt_id + 0 + 8 read-write + + + + CH10_TASK_ID + channel10 task id register + 0x6C + 0x20 + - CH3_RX_THR_EVENT_INT_ENA - The interrupt enable bit for CH3_RX_THR_EVENT_INT. - 11 - 1 + CH10_TASK_ID + ch10_task_id + 0 + 8 read-write + + + + CH11_EVT_ID + channel11 event id register + 0x70 + 0x20 + - CH0_TX_LOOP_INT_ENA - The interrupt enable bit for CH0_TX_LOOP_INT. - 12 - 1 + CH11_EVT_ID + ch11_evt_id + 0 + 8 read-write + + + + CH11_TASK_ID + channel11 task id register + 0x74 + 0x20 + - CH1_TX_LOOP_INT_ENA - The interrupt enable bit for CH1_TX_LOOP_INT. - 13 - 1 + CH11_TASK_ID + ch11_task_id + 0 + 8 read-write - INT_CLR - Interrupt clear bits - 0x44 + CH12_EVT_ID + channel12 event id register + 0x78 0x20 - CH0_TX_END_INT_CLR - Set this bit to clear theCH0_TX_END_INT interrupt. + CH12_EVT_ID + ch12_evt_id 0 - 1 - write-only + 8 + read-write + + + + CH12_TASK_ID + channel12 task id register + 0x7C + 0x20 + - CH1_TX_END_INT_CLR - Set this bit to clear theCH1_TX_END_INT interrupt. - 1 - 1 - write-only + CH12_TASK_ID + ch12_task_id + 0 + 8 + read-write + + + + CH13_EVT_ID + channel13 event id register + 0x80 + 0x20 + - CH2_RX_END_INT_CLR - Set this bit to clear theCH2_RX_END_INT interrupt. - 2 - 1 - write-only + CH13_EVT_ID + ch13_evt_id + 0 + 8 + read-write + + + + + CH13_TASK_ID + channel13 task id register + 0x84 + 0x20 + + + CH13_TASK_ID + ch13_task_id + 0 + 8 + read-write + + + + CH14_EVT_ID + channel14 event id register + 0x88 + 0x20 + - CH3_RX_END_INT_CLR - Set this bit to clear theCH3_RX_END_INT interrupt. - 3 - 1 - write-only + CH14_EVT_ID + ch14_evt_id + 0 + 8 + read-write + + + + CH14_TASK_ID + channel14 task id register + 0x8C + 0x20 + - RX_CH0_ERR_INT_CLR - Set this bit to clear theCH4_ERR_INT interrupt. - 4 - 1 - write-only + CH14_TASK_ID + ch14_task_id + 0 + 8 + read-write + + + + CH15_EVT_ID + channel15 event id register + 0x90 + 0x20 + - RX_CH1_ERR_INT_CLR - Set this bit to clear theCH5_ERR_INT interrupt. - 5 - 1 - write-only + CH15_EVT_ID + ch15_evt_id + 0 + 8 + read-write + + + + CH15_TASK_ID + channel15 task id register + 0x94 + 0x20 + - RX_CH2_ERR_INT_CLR - Set this bit to clear theCH6_ERR_INT interrupt. - 6 - 1 - write-only + CH15_TASK_ID + ch15_task_id + 0 + 8 + read-write + + + + CH16_EVT_ID + channel16 event id register + 0x98 + 0x20 + - RX_CH3_ERR_INT_CLR - Set this bit to clear theCH7_ERR_INT interrupt. - 7 - 1 - write-only + CH16_EVT_ID + ch16_evt_id + 0 + 8 + read-write + + + + + CH16_TASK_ID + channel16 task id register + 0x9C + 0x20 + + + CH16_TASK_ID + ch16_task_id + 0 + 8 + read-write + + + + + CH17_EVT_ID + channel17 event id register + 0xA0 + 0x20 + + + CH17_EVT_ID + ch17_evt_id + 0 + 8 + read-write + + + + + CH17_TASK_ID + channel17 task id register + 0xA4 + 0x20 + + + CH17_TASK_ID + ch17_task_id + 0 + 8 + read-write + + + + + CH18_EVT_ID + channel18 event id register + 0xA8 + 0x20 + + + CH18_EVT_ID + ch18_evt_id + 0 + 8 + read-write + + + + + CH18_TASK_ID + channel18 task id register + 0xAC + 0x20 + + + CH18_TASK_ID + ch18_task_id + 0 + 8 + read-write + + + + CH19_EVT_ID + channel19 event id register + 0xB0 + 0x20 + - CH0_TX_THR_EVENT_INT_CLR - Set this bit to clear theCH0_TX_THR_EVENT_INT interrupt. - 8 - 1 - write-only + CH19_EVT_ID + ch19_evt_id + 0 + 8 + read-write + + + + CH19_TASK_ID + channel19 task id register + 0xB4 + 0x20 + - CH1_TX_THR_EVENT_INT_CLR - Set this bit to clear theCH1_TX_THR_EVENT_INT interrupt. - 9 - 1 - write-only + CH19_TASK_ID + ch19_task_id + 0 + 8 + read-write + + + + CH20_EVT_ID + channel20 event id register + 0xB8 + 0x20 + - CH2_RX_THR_EVENT_INT_CLR - Set this bit to clear theCH2_RX_THR_EVENT_INT interrupt. - 10 - 1 - write-only + CH20_EVT_ID + ch20_evt_id + 0 + 8 + read-write + + + + CH20_TASK_ID + channel20 task id register + 0xBC + 0x20 + - CH3_RX_THR_EVENT_INT_CLR - Set this bit to clear theCH3_RX_THR_EVENT_INT interrupt. - 11 - 1 - write-only + CH20_TASK_ID + ch20_task_id + 0 + 8 + read-write + + + + CH21_EVT_ID + channel21 event id register + 0xC0 + 0x20 + - CH0_TX_LOOP_INT_CLR - Set this bit to clear theCH0_TX_LOOP_INT interrupt. - 12 - 1 - write-only + CH21_EVT_ID + ch21_evt_id + 0 + 8 + read-write + + + + CH21_TASK_ID + channel21 task id register + 0xC4 + 0x20 + - CH1_TX_LOOP_INT_CLR - Set this bit to clear theCH1_TX_LOOP_INT interrupt. - 13 - 1 - write-only + CH21_TASK_ID + ch21_task_id + 0 + 8 + read-write - 2 - 0x4 - CH%sCARRIER_DUTY - Channel %s duty cycle configuration register - 0x48 + CH22_EVT_ID + channel22 event id register + 0xC8 0x20 - 0x00400040 - CARRIER_LOW_CH0 - This register is used to configure carrier wave 's low level clock period for CHANNEL%s. + CH22_EVT_ID + ch22_evt_id 0 - 16 + 8 read-write + + + + CH22_TASK_ID + channel22 task id register + 0xCC + 0x20 + - CARRIER_HIGH_CH0 - This register is used to configure carrier wave 's high level clock period for CHANNEL%s. - 16 - 16 + CH22_TASK_ID + ch22_task_id + 0 + 8 read-write - 2 - 0x4 - CH%s_RX_CARRIER_RM - Channel %s carrier remove register - 0x50 + CH23_EVT_ID + channel23 event id register + 0xD0 0x20 - CARRIER_LOW_THRES_CH2 - The low level period in a carrier modulation mode is (REG_RMT_REG_CARRIER_LOW_THRES_CH%s + 1) for channel %s. + CH23_EVT_ID + ch23_evt_id 0 - 16 + 8 read-write + + + + CH23_TASK_ID + channel23 task id register + 0xD4 + 0x20 + - CARRIER_HIGH_THRES_CH2 - The high level period in a carrier modulation mode is (REG_RMT_REG_CARRIER_HIGH_THRES_CH%s + 1) for channel %s. - 16 - 16 + CH23_TASK_ID + ch23_task_id + 0 + 8 read-write - 2 - 0x4 - CH%s_TX_LIM - Channel %s Tx event configuration register - 0x58 + CH24_EVT_ID + channel24 event id register + 0xD8 0x20 - 0x00000080 - TX_LIM_CH0 - This register is used to configure the maximum entries that CHANNEL%s can send out. + CH24_EVT_ID + ch24_evt_id 0 - 9 + 8 read-write + + + + CH24_TASK_ID + channel24 task id register + 0xDC + 0x20 + - TX_LOOP_NUM_CH0 - This register is used to configure the maximum loop count when tx_conti_mode is valid. - 9 - 10 + CH24_TASK_ID + ch24_task_id + 0 + 8 read-write + + + + CH25_EVT_ID + channel25 event id register + 0xE0 + 0x20 + - TX_LOOP_CNT_EN_CH0 - This register is the enabled bit for loop count. - 19 - 1 + CH25_EVT_ID + ch25_evt_id + 0 + 8 read-write + + + + CH25_TASK_ID + channel25 task id register + 0xE4 + 0x20 + - LOOP_COUNT_RESET_CH0 - This register is used to reset the loop count when tx_conti_mode is valid. - 20 - 1 - write-only + CH25_TASK_ID + ch25_task_id + 0 + 8 + read-write + + + + CH26_EVT_ID + channel26 event id register + 0xE8 + 0x20 + - LOOP_STOP_EN_CH0 - This bit is used to enable the loop send stop function after the loop counter counts to loop number for CHANNEL%s. - 21 - 1 + CH26_EVT_ID + ch26_evt_id + 0 + 8 read-write - 2 - 0x4 - CH%s_RX_LIM - Channel %s Rx event configuration register - 0x60 + CH26_TASK_ID + channel26 task id register + 0xEC 0x20 - 0x00000080 - RMT_RX_LIM_CH2 - This register is used to configure the maximum entries that CHANNEL%s can receive. + CH26_TASK_ID + ch26_task_id 0 - 9 + 8 read-write - SYS_CONF - RMT apb configuration register - 0x68 + CH27_EVT_ID + channel27 event id register + 0xF0 0x20 - 0x05000010 - APB_FIFO_MASK - 1'h1: access memory directly. 1'h0: access memory by FIFO. + CH27_EVT_ID + ch27_evt_id 0 - 1 + 8 read-write + + + + CH27_TASK_ID + channel27 task id register + 0xF4 + 0x20 + - MEM_CLK_FORCE_ON - Set this bit to enable the clock for RMT memory. - 1 - 1 + CH27_TASK_ID + ch27_task_id + 0 + 8 read-write + + + + CH28_EVT_ID + channel28 event id register + 0xF8 + 0x20 + - RMT_MEM_FORCE_PD - Set this bit to power down RMT memory. - 2 - 1 + CH28_EVT_ID + ch28_evt_id + 0 + 8 read-write + + + + CH28_TASK_ID + channel28 task id register + 0xFC + 0x20 + - RMT_MEM_FORCE_PU - 1: Disable RMT memory light sleep power down function. 0: Power down RMT memory when RMT is in light sleep mode. - 3 - 1 + CH28_TASK_ID + ch28_task_id + 0 + 8 read-write + + + + CH29_EVT_ID + channel29 event id register + 0x100 + 0x20 + - RMT_SCLK_DIV_NUM - the integral part of the fractional divisor - 4 + CH29_EVT_ID + ch29_evt_id + 0 8 read-write + + + + CH29_TASK_ID + channel29 task id register + 0x104 + 0x20 + - RMT_SCLK_DIV_A - the numerator of the fractional part of the fractional divisor - 12 - 6 + CH29_TASK_ID + ch29_task_id + 0 + 8 read-write + + + + CH30_EVT_ID + channel30 event id register + 0x108 + 0x20 + - RMT_SCLK_DIV_B - the denominator of the fractional part of the fractional divisor - 18 - 6 + CH30_EVT_ID + ch30_evt_id + 0 + 8 read-write + + + + CH30_TASK_ID + channel30 task id register + 0x10C + 0x20 + - RMT_SCLK_SEL - choose the clock source of rmt_sclk. 1:CLK_80Mhz,2:CLK_FOSC, 3:XTAL - 24 - 2 + CH30_TASK_ID + ch30_task_id + 0 + 8 read-write + + + + CH31_EVT_ID + channel31 event id register + 0x110 + 0x20 + - RMT_SCLK_ACTIVE - rmt_sclk switch - 26 - 1 + CH31_EVT_ID + ch31_evt_id + 0 + 8 read-write + + + + CH31_TASK_ID + channel31 task id register + 0x114 + 0x20 + - CLK_EN - RMT register clock gate enable signal. 1: Power up the drive clock of registers. 0: Power down the drive clock of registers - 31 - 1 + CH31_TASK_ID + ch31_task_id + 0 + 8 read-write - TX_SIM - RMT TX synchronous register - 0x6C + CH32_EVT_ID + channel32 event id register + 0x118 0x20 - CH0 - Set this bit to enable CHANNEL0 to start sending data synchronously with other enabled channels. + CH32_EVT_ID + ch32_evt_id 0 - 1 + 8 read-write + + + + CH32_TASK_ID + channel32 task id register + 0x11C + 0x20 + - CH1 - Set this bit to enable CHANNEL1 to start sending data synchronously with other enabled channels. - 1 - 1 + CH32_TASK_ID + ch32_task_id + 0 + 8 read-write + + + + CH33_EVT_ID + channel33 event id register + 0x120 + 0x20 + - EN - This register is used to enable multiple of channels to start sending data synchronously. - 2 - 1 + CH33_EVT_ID + ch33_evt_id + 0 + 8 read-write - REF_CNT_RST - RMT clock divider reset register - 0x70 + CH33_TASK_ID + channel33 task id register + 0x124 0x20 - TX_REF_CNT_RST_CH0 - This register is used to reset the clock divider of CHANNEL0. + CH33_TASK_ID + ch33_task_id 0 - 1 - write-only + 8 + read-write + + + + CH34_EVT_ID + channel34 event id register + 0x128 + 0x20 + - TX_REF_CNT_RST_CH1 - This register is used to reset the clock divider of CHANNEL1. - 1 - 1 - write-only + CH34_EVT_ID + ch34_evt_id + 0 + 8 + read-write + + + + CH34_TASK_ID + channel34 task id register + 0x12C + 0x20 + - RX_REF_CNT_RST_CH2 - This register is used to reset the clock divider of CHANNEL2. - 2 - 1 - write-only + CH34_TASK_ID + ch34_task_id + 0 + 8 + read-write + + + + CH35_EVT_ID + channel35 event id register + 0x130 + 0x20 + - RX_REF_CNT_RST_CH3 - This register is used to reset the clock divider of CHANNEL3. - 3 - 1 - write-only + CH35_EVT_ID + ch35_evt_id + 0 + 8 + read-write - DATE - RMT version register - 0xCC + CH35_TASK_ID + channel35 task id register + 0x134 0x20 - 0x02108213 - RMT_DATE - This is the version register. + CH35_TASK_ID + ch35_task_id 0 - 28 + 8 read-write - - - - RNG - Hardware random number generator - RNG - 0x600260B0 - - 0x0 - 0x4 - registers - - - DATA - Random number data - 0x0 + CH36_EVT_ID + channel36 event id register + 0x138 0x20 + + + CH36_EVT_ID + ch36_evt_id + 0 + 8 + read-write + + - - - - RSA - RSA (Rivest Shamir Adleman) Accelerator - RSA - 0x6003C000 - - 0x0 - 0x74 - registers - - - RSA - 47 - - - 16 - 0x1 - M_MEM[%s] - Represents M - 0x0 - 0x8 + CH36_TASK_ID + channel36 task id register + 0x13C + 0x20 + + + CH36_TASK_ID + ch36_task_id + 0 + 8 + read-write + + - 16 - 0x1 - Z_MEM[%s] - Represents Z - 0x200 - 0x8 + CH37_EVT_ID + channel37 event id register + 0x140 + 0x20 + + + CH37_EVT_ID + ch37_evt_id + 0 + 8 + read-write + + - 16 - 0x1 - Y_MEM[%s] - Represents Y - 0x400 - 0x8 + CH37_TASK_ID + channel37 task id register + 0x144 + 0x20 + + + CH37_TASK_ID + ch37_task_id + 0 + 8 + read-write + + - 16 - 0x1 - X_MEM[%s] - Represents X - 0x600 - 0x8 + CH38_EVT_ID + channel38 event id register + 0x148 + 0x20 + + + CH38_EVT_ID + ch38_evt_id + 0 + 8 + read-write + + - M_PRIME - Represents M’ - 0x800 + CH38_TASK_ID + channel38 task id register + 0x14C 0x20 - M_PRIME - Represents M’ + CH38_TASK_ID + ch38_task_id 0 - 32 + 8 read-write - MODE - Configures RSA length - 0x804 + CH39_EVT_ID + channel39 event id register + 0x150 0x20 - MODE - Configures the RSA length. + CH39_EVT_ID + ch39_evt_id 0 - 7 + 8 read-write - QUERY_CLEAN - RSA clean register - 0x808 + CH39_TASK_ID + channel39 task id register + 0x154 0x20 - QUERY_CLEAN - Represents whether or not the RSA memory completes initialization. - -0: Not complete - -1: Completed - - + CH39_TASK_ID + ch39_task_id 0 - 1 - read-only + 8 + read-write - SET_START_MODEXP - Starts modular exponentiation - 0x80C + CH40_EVT_ID + channel40 event id register + 0x158 0x20 - SET_START_MODEXP - Configure whether or not to start the modular exponentiation. - -0: No effect - -1: Start - - + CH40_EVT_ID + ch40_evt_id 0 - 1 - write-only + 8 + read-write - SET_START_MODMULT - Starts modular multiplication - 0x810 + CH40_TASK_ID + channel40 task id register + 0x15C 0x20 - SET_START_MODMULT - Configure whether or not to start the modular multiplication. - -0: No effect - -1: Start - - + CH40_TASK_ID + ch40_task_id 0 - 1 - write-only + 8 + read-write - SET_START_MULT - Starts multiplication - 0x814 + CH41_EVT_ID + channel41 event id register + 0x160 0x20 - SET_START_MULT - Configure whether or not to start the multiplication. - -0: No effect - -1: Start - - + CH41_EVT_ID + ch41_evt_id 0 - 1 - write-only + 8 + read-write - QUERY_IDLE - Represents the RSA status - 0x818 + CH41_TASK_ID + channel41 task id register + 0x164 0x20 - QUERY_IDLE - Represents the RSA status. - -0: Busy - -1: Idle - - + CH41_TASK_ID + ch41_task_id 0 - 1 - read-only + 8 + read-write - INT_CLR - Clears RSA interrupt - 0x81C + CH42_EVT_ID + channel42 event id register + 0x168 0x20 - CLEAR_INTERRUPT - Write 1 to clear the RSA interrupt. + CH42_EVT_ID + ch42_evt_id 0 - 1 - write-only + 8 + read-write - CONSTANT_TIME - Configures the constant_time option - 0x820 + CH42_TASK_ID + channel42 task id register + 0x16C 0x20 - 0x00000001 - CONSTANT_TIME - Configures the constant_time option. - -0: Acceleration - -1: No acceleration (default) - - + CH42_TASK_ID + ch42_task_id 0 - 1 + 8 read-write - SEARCH_ENABLE - Configures the search option - 0x824 + CH43_EVT_ID + channel43 event id register + 0x170 0x20 - SEARCH_ENABLE - Configure the search option. - -0: No acceleration (default) - -1: Acceleration - -This option should be used together with RSA_SEARCH_POS. + CH43_EVT_ID + ch43_evt_id 0 - 1 + 8 read-write - SEARCH_POS - Configures the search position - 0x828 + CH43_TASK_ID + channel43 task id register + 0x174 0x20 - SEARCH_POS - Configures the starting address to start search. This field should be used together with RSA_SEARCH_ENABLE. The field is only valid when RSA_SEARCH_ENABLE is high. + CH43_TASK_ID + ch43_task_id 0 - 12 + 8 read-write - INT_ENA - Enables the RSA interrupt - 0x82C + CH44_EVT_ID + channel44 event id register + 0x178 0x20 - INT_ENA - Write 1 to enable the RSA interrupt. + CH44_EVT_ID + ch44_evt_id 0 - 1 + 8 read-write - DATE - Version control register - 0x830 + CH44_TASK_ID + channel44 task id register + 0x17C 0x20 - 0x20200618 - DATE - Version control register. + CH44_TASK_ID + ch44_task_id 0 - 30 + 8 read-write - - - - SHA - SHA (Secure Hash Algorithm) Accelerator - SHA - 0x6003B000 - - 0x0 - 0xB0 - registers - - - SHA - 49 - - - MODE - Initial configuration register. - 0x0 + CH45_EVT_ID + channel45 event id register + 0x180 0x20 - MODE - Sha mode. + CH45_EVT_ID + ch45_evt_id 0 - 3 + 8 read-write - T_STRING - SHA 512/t configuration register 0. - 0x4 + CH45_TASK_ID + channel45 task id register + 0x184 0x20 - T_STRING - Sha t_string (used if and only if mode == SHA_512/t). + CH45_TASK_ID + ch45_task_id 0 - 32 + 8 read-write - T_LENGTH - SHA 512/t configuration register 1. - 0x8 + CH46_EVT_ID + channel46 event id register + 0x188 0x20 - T_LENGTH - Sha t_length (used if and only if mode == SHA_512/t). + CH46_EVT_ID + ch46_evt_id 0 - 6 + 8 read-write - DMA_BLOCK_NUM - DMA configuration register 0. - 0xC + CH46_TASK_ID + channel46 task id register + 0x18C 0x20 - DMA_BLOCK_NUM - Dma-sha block number. + CH46_TASK_ID + ch46_task_id 0 - 6 + 8 read-write - START - Typical SHA configuration register 0. - 0x10 + CH47_EVT_ID + channel47 event id register + 0x190 0x20 - START - Reserved. - 1 - 31 - read-only + CH47_EVT_ID + ch47_evt_id + 0 + 8 + read-write - CONTINUE - Typical SHA configuration register 1. - 0x14 + CH47_TASK_ID + channel47 task id register + 0x194 0x20 - CONTINUE - Reserved. - 1 - 31 - read-only + CH47_TASK_ID + ch47_task_id + 0 + 8 + read-write - BUSY - Busy register. - 0x18 + CH48_EVT_ID + channel48 event id register + 0x198 0x20 - STATE - Sha busy state. 1'b0: idle. 1'b1: busy. + CH48_EVT_ID + ch48_evt_id 0 - 1 - read-only + 8 + read-write - DMA_START - DMA configuration register 1. - 0x1C + CH48_TASK_ID + channel48 task id register + 0x19C 0x20 - DMA_START - Start dma-sha. + CH48_TASK_ID + ch48_task_id 0 - 1 - write-only + 8 + read-write - DMA_CONTINUE - DMA configuration register 2. - 0x20 + CH49_EVT_ID + channel49 event id register + 0x1A0 0x20 - DMA_CONTINUE - Continue dma-sha. + CH49_EVT_ID + ch49_evt_id 0 - 1 - write-only + 8 + read-write - CLEAR_IRQ - Interrupt clear register. - 0x24 + CH49_TASK_ID + channel49 task id register + 0x1A4 0x20 - CLEAR_INTERRUPT - Clear sha interrupt. + CH49_TASK_ID + ch49_task_id 0 - 1 - write-only + 8 + read-write - IRQ_ENA - Interrupt enable register. - 0x28 + CLK_EN + etm clock enable register + 0x1A8 0x20 - INTERRUPT_ENA - Sha interrupt enable register. 1'b0: disable(default). 1'b1: enable. + CLK_EN + clock enable 0 1 read-write @@ -16534,43 +36912,27 @@ This option should be used together with RSA_SEARCH_POS. DATE - Date register. - 0x2C + etm date register + 0x1AC 0x20 - 0x20201229 + 0x02203092 DATE - Sha date information/ sha version information. + date 0 - 30 + 28 read-write - - 64 - 0x1 - H_MEM[%s] - Sha H memory which contains intermediate hash or finial hash. - 0x40 - 0x8 - - - 64 - 0x1 - M_MEM[%s] - Sha M memory which contains message. - 0x80 - 0x8 - SPI0 SPI (Serial Peripheral Interface) Controller SPI0 - 0x60003000 + 0x60002000 0x0 0x138 @@ -19231,7 +39593,7 @@ This option should be used together with RSA_SEARCH_POS. SPI1 SPI (Serial Peripheral Interface) Controller SPI1 - 0x60002000 + 0x60003000 0x0 0xAC @@ -20762,7 +41124,7 @@ This option should be used together with RSA_SEARCH_POS. SPI2 SPI (Serial Peripheral Interface) Controller SPI2 - 0x60024000 + 0x60081000 0x0 0x98 @@ -22831,21 +43193,11 @@ This option should be used together with RSA_SEARCH_POS. - - SPI3 - SPI (Serial Peripheral Interface) Controller - 0x60025000 - - - SPI4 - SPI (Serial Peripheral Interface) Controller - 0x60037000 - SYSTIMER System Timer SYSTIMER - 0x60023000 + 0x6000B000 0x0 0x90 @@ -24156,7 +44508,7 @@ This option should be used together with RSA_SEARCH_POS. TIMG0 Timer Group TIMG - 0x6001F000 + 0x60009000 0x0 0x68 @@ -24817,7 +45169,7 @@ protection is enabled. TIMG1 Timer Group - 0x60020000 + 0x6000A000 TG1_T0_LEVEL 34 @@ -24827,11 +45179,266 @@ protection is enabled. 35 + + TRACE + Peripheral TRACE + TRACE + 0x600C0000 + + 0x0 + 0x30 + registers + + + + MEM_START_ADDR + mem start addr + 0x0 + 0x20 + + + MEM_STAET_ADDR + The start address of trace memory + 0 + 32 + read-write + + + + + MEM_END_ADDR + mem end addr + 0x4 + 0x20 + 0xFFFFFFFF + + + MEM_END_ADDR + The end address of trace memory + 0 + 32 + read-write + + + + + MEM_CURRENT_ADDR + mem current addr + 0x8 + 0x20 + + + MEM_CURRENT_ADDR + current_mem_addr,indicate that next writing addr + 0 + 32 + read-only + + + + + MEM_ADDR_UPDATE + mem addr update + 0xC + 0x20 + + + MEM_CURRENT_ADDR_UPDATE + when set this reg, the current_mem_addr will update to start_addr + 0 + 1 + write-only + + + + + FIFO_STATUS + fifo status register + 0x10 + 0x20 + 0x00000001 + + + FIFO_EMPTY + 1 indicate that fifo is empty + 0 + 1 + read-only + + + WORK_STATUS + mem_full interrupt status + 1 + 1 + read-only + + + + + INTR_ENA + interrupt enable register + 0x14 + 0x20 + + + FIFO_OVERFLOW_INTR_ENA + Set 1 enable fifo_overflow interrupt + 0 + 1 + read-write + + + MEM_FULL_INTR_ENA + Set 1 enable mem_full interrupt + 1 + 1 + read-write + + + + + INTR_RAW + interrupt status register + 0x18 + 0x20 + + + FIFO_OVERFLOW_INTR_RAW + fifo_overflow interrupt status + 0 + 1 + read-only + + + MEM_FULL_INTR_RAW + mem_full interrupt status + 1 + 1 + read-only + + + + + INTR_CLR + interrupt clear register + 0x1C + 0x20 + + + FIFO_OVERFLOW_INTR_CLR + Set 1 clr fifo overflow interrupt + 0 + 1 + write-only + + + MEM_FULL_INTR_CLR + Set 1 clr mem full interrupt + 1 + 1 + write-only + + + + + TRIGGER + trigger register + 0x20 + 0x20 + 0x0000000C + + + ON + [0] set 1 start trace. + 0 + 1 + write-only + + + OFF + set 1 stop trace. + 1 + 1 + write-only + + + MEM_LOOP + if this reg is 1, trace will loop wrtie trace_mem. If is 0, when mem_current_addr at mem_end_addr, it will stop at the mem_end_addr + 2 + 1 + read-write + + + RESTART_ENA + enable encoder auto-restart, when lost package, the encoder will end, if enable auto-restart, when fifo empty, encoder will restart and send a sync package. + 3 + 1 + read-write + + + + + RESYNC_PROLONGED + resync configuration register + 0x24 + 0x20 + 0x00000080 + + + RESYNC_PROLONGED + count number, when count to this value, send a sync package + 0 + 24 + read-write + + + RESYNC_MODE + resyc mode sel: 0: default, cycle count 1: package num count + 24 + 1 + read-write + + + + + CLOCK_GATE + Clock gate control register + 0x28 + 0x20 + 0x00000001 + + + CLK_EN + The bit is used to enable clock gate when access all registers in this module. + 0 + 1 + read-write + + + + + DATE + Version control register + 0x3FC + 0x20 + 0x02203030 + + + DATE + version control register. Note that this default value stored is the latest date when the hardware logic was updated. + 0 + 28 + read-write + + + + + TWAI Two-Wire Automotive Interface TWAI - 0x6002B000 + 0x6000C000 0x0 0x80 @@ -27254,7 +47861,7 @@ protection is enabled. UART1 UART (Universal Asynchronous Receiver-Transmitter) Controller - 0x60010000 + 0x60001000 UART1 22 @@ -27264,7 +47871,7 @@ protection is enabled. UHCI0 Universal Host Controller Interface UHCI - 0x60014000 + 0x60006000 0x0 0x84 @@ -28307,16 +48914,11 @@ protection is enabled. - - UHCI1 - Universal Host Controller Interface - 0x6000C000 - USB_DEVICE Full-speed USB Serial/JTAG Controller USB_DEVICE - 0x60043000 + 0x6000F000 0x0 0x70 @@ -28334,7 +48936,7 @@ protection is enabled. 0x20 - USB_SERIAL_JTAG_RDWR_BYTE + RDWR_BYTE Write and read byte data to/from UART Tx/Rx FIFO through this field. When USB_DEVICE_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 bytes) into UART Tx FIFO. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is set, user can check USB_DEVICE_OUT_EP1_WR_ADDR USB_DEVICE_OUT_EP0_RD_ADDR to know how many data is received, then read data from UART Rx FIFO. 0 8 @@ -28350,21 +48952,21 @@ protection is enabled. 0x00000002 - USB_SERIAL_JTAG_WR_DONE + WR_DONE Set this bit to indicate writing byte data to UART Tx FIFO is done. 0 1 write-only - USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE + SERIAL_IN_EP_DATA_FREE 1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writing USB_DEVICE_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by USB Host. 1 1 read-only - USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL + SERIAL_OUT_EP_DATA_AVAIL 1'b1: Indicate there is data in UART Rx FIFO. 2 1 @@ -28380,112 +48982,112 @@ protection is enabled. 0x00000008 - USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW + JTAG_IN_FLUSH_INT_RAW The raw interrupt bit turns to high level when flush cmd is received for IN endpoint 2 of JTAG. 0 1 read-only - USB_SERIAL_JTAG_SOF_INT_RAW + SOF_INT_RAW The raw interrupt bit turns to high level when SOF frame is received. 1 1 read-only - USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW + SERIAL_OUT_RECV_PKT_INT_RAW The raw interrupt bit turns to high level when Serial Port OUT Endpoint received one packet. 2 1 read-only - USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW + SERIAL_IN_EMPTY_INT_RAW The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty. 3 1 read-only - USB_SERIAL_JTAG_PID_ERR_INT_RAW + PID_ERR_INT_RAW The raw interrupt bit turns to high level when pid error is detected. 4 1 read-only - USB_SERIAL_JTAG_CRC5_ERR_INT_RAW + CRC5_ERR_INT_RAW The raw interrupt bit turns to high level when CRC5 error is detected. 5 1 read-only - USB_SERIAL_JTAG_CRC16_ERR_INT_RAW + CRC16_ERR_INT_RAW The raw interrupt bit turns to high level when CRC16 error is detected. 6 1 read-only - USB_SERIAL_JTAG_STUFF_ERR_INT_RAW + STUFF_ERR_INT_RAW The raw interrupt bit turns to high level when stuff error is detected. 7 1 read-only - USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW + IN_TOKEN_REC_IN_EP1_INT_RAW The raw interrupt bit turns to high level when IN token for IN endpoint 1 is received. 8 1 read-only - USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW + USB_BUS_RESET_INT_RAW The raw interrupt bit turns to high level when usb bus reset is detected. 9 1 read-only - USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW + OUT_EP1_ZERO_PAYLOAD_INT_RAW The raw interrupt bit turns to high level when OUT endpoint 1 received packet with zero palyload. 10 1 read-only - USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW + OUT_EP2_ZERO_PAYLOAD_INT_RAW The raw interrupt bit turns to high level when OUT endpoint 2 received packet with zero palyload. 11 1 read-only - USB_SERIAL_JTAG_RTS_CHG_INT_RAW + RTS_CHG_INT_RAW The raw interrupt bit turns to high level when level of RTS from usb serial channel is changed. 12 1 read-only - USB_SERIAL_JTAG_DTR_CHG_INT_RAW + DTR_CHG_INT_RAW The raw interrupt bit turns to high level when level of DTR from usb serial channel is changed. 13 1 read-only - USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW + GET_LINE_CODE_INT_RAW The raw interrupt bit turns to high level when level of GET LINE CODING request is received. 14 1 read-only - USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW + SET_LINE_CODE_INT_RAW The raw interrupt bit turns to high level when level of SET LINE CODING request is received. 15 1 @@ -28500,112 +49102,112 @@ protection is enabled. 0x20 - USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST + JTAG_IN_FLUSH_INT_ST The raw interrupt status bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt. 0 1 read-only - USB_SERIAL_JTAG_SOF_INT_ST + SOF_INT_ST The raw interrupt status bit for the USB_DEVICE_SOF_INT interrupt. 1 1 read-only - USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST + SERIAL_OUT_RECV_PKT_INT_ST The raw interrupt status bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt. 2 1 read-only - USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST + SERIAL_IN_EMPTY_INT_ST The raw interrupt status bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt. 3 1 read-only - USB_SERIAL_JTAG_PID_ERR_INT_ST + PID_ERR_INT_ST The raw interrupt status bit for the USB_DEVICE_PID_ERR_INT interrupt. 4 1 read-only - USB_SERIAL_JTAG_CRC5_ERR_INT_ST + CRC5_ERR_INT_ST The raw interrupt status bit for the USB_DEVICE_CRC5_ERR_INT interrupt. 5 1 read-only - USB_SERIAL_JTAG_CRC16_ERR_INT_ST + CRC16_ERR_INT_ST The raw interrupt status bit for the USB_DEVICE_CRC16_ERR_INT interrupt. 6 1 read-only - USB_SERIAL_JTAG_STUFF_ERR_INT_ST + STUFF_ERR_INT_ST The raw interrupt status bit for the USB_DEVICE_STUFF_ERR_INT interrupt. 7 1 read-only - USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST + IN_TOKEN_REC_IN_EP1_INT_ST The raw interrupt status bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt. 8 1 read-only - USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST + USB_BUS_RESET_INT_ST The raw interrupt status bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt. 9 1 read-only - USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST + OUT_EP1_ZERO_PAYLOAD_INT_ST The raw interrupt status bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt. 10 1 read-only - USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST + OUT_EP2_ZERO_PAYLOAD_INT_ST The raw interrupt status bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt. 11 1 read-only - USB_SERIAL_JTAG_RTS_CHG_INT_ST + RTS_CHG_INT_ST The raw interrupt status bit for the USB_DEVICE_RTS_CHG_INT interrupt. 12 1 read-only - USB_SERIAL_JTAG_DTR_CHG_INT_ST + DTR_CHG_INT_ST The raw interrupt status bit for the USB_DEVICE_DTR_CHG_INT interrupt. 13 1 read-only - USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST + GET_LINE_CODE_INT_ST The raw interrupt status bit for the USB_DEVICE_GET_LINE_CODE_INT interrupt. 14 1 read-only - USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST + SET_LINE_CODE_INT_ST The raw interrupt status bit for the USB_DEVICE_SET_LINE_CODE_INT interrupt. 15 1 @@ -28620,112 +49222,112 @@ protection is enabled. 0x20 - USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA + JTAG_IN_FLUSH_INT_ENA The interrupt enable bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt. 0 1 read-write - USB_SERIAL_JTAG_SOF_INT_ENA + SOF_INT_ENA The interrupt enable bit for the USB_DEVICE_SOF_INT interrupt. 1 1 read-write - USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA + SERIAL_OUT_RECV_PKT_INT_ENA The interrupt enable bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt. 2 1 read-write - USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA + SERIAL_IN_EMPTY_INT_ENA The interrupt enable bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt. 3 1 read-write - USB_SERIAL_JTAG_PID_ERR_INT_ENA + PID_ERR_INT_ENA The interrupt enable bit for the USB_DEVICE_PID_ERR_INT interrupt. 4 1 read-write - USB_SERIAL_JTAG_CRC5_ERR_INT_ENA + CRC5_ERR_INT_ENA The interrupt enable bit for the USB_DEVICE_CRC5_ERR_INT interrupt. 5 1 read-write - USB_SERIAL_JTAG_CRC16_ERR_INT_ENA + CRC16_ERR_INT_ENA The interrupt enable bit for the USB_DEVICE_CRC16_ERR_INT interrupt. 6 1 read-write - USB_SERIAL_JTAG_STUFF_ERR_INT_ENA + STUFF_ERR_INT_ENA The interrupt enable bit for the USB_DEVICE_STUFF_ERR_INT interrupt. 7 1 read-write - USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA + IN_TOKEN_REC_IN_EP1_INT_ENA The interrupt enable bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt. 8 1 read-write - USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA + USB_BUS_RESET_INT_ENA The interrupt enable bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt. 9 1 read-write - USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA + OUT_EP1_ZERO_PAYLOAD_INT_ENA The interrupt enable bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt. 10 1 read-write - USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA + OUT_EP2_ZERO_PAYLOAD_INT_ENA The interrupt enable bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt. 11 1 read-write - USB_SERIAL_JTAG_RTS_CHG_INT_ENA + RTS_CHG_INT_ENA The interrupt enable bit for the USB_DEVICE_RTS_CHG_INT interrupt. 12 1 read-write - USB_SERIAL_JTAG_DTR_CHG_INT_ENA + DTR_CHG_INT_ENA The interrupt enable bit for the USB_DEVICE_DTR_CHG_INT interrupt. 13 1 read-write - USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA + GET_LINE_CODE_INT_ENA The interrupt enable bit for the USB_DEVICE_GET_LINE_CODE_INT interrupt. 14 1 read-write - USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA + SET_LINE_CODE_INT_ENA The interrupt enable bit for the USB_DEVICE_SET_LINE_CODE_INT interrupt. 15 1 @@ -28740,112 +49342,112 @@ protection is enabled. 0x20 - USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR + JTAG_IN_FLUSH_INT_CLR Set this bit to clear the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt. 0 1 write-only - USB_SERIAL_JTAG_SOF_INT_CLR + SOF_INT_CLR Set this bit to clear the USB_DEVICE_JTAG_SOF_INT interrupt. 1 1 write-only - USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR + SERIAL_OUT_RECV_PKT_INT_CLR Set this bit to clear the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt. 2 1 write-only - USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR + SERIAL_IN_EMPTY_INT_CLR Set this bit to clear the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt. 3 1 write-only - USB_SERIAL_JTAG_PID_ERR_INT_CLR + PID_ERR_INT_CLR Set this bit to clear the USB_DEVICE_PID_ERR_INT interrupt. 4 1 write-only - USB_SERIAL_JTAG_CRC5_ERR_INT_CLR + CRC5_ERR_INT_CLR Set this bit to clear the USB_DEVICE_CRC5_ERR_INT interrupt. 5 1 write-only - USB_SERIAL_JTAG_CRC16_ERR_INT_CLR + CRC16_ERR_INT_CLR Set this bit to clear the USB_DEVICE_CRC16_ERR_INT interrupt. 6 1 write-only - USB_SERIAL_JTAG_STUFF_ERR_INT_CLR + STUFF_ERR_INT_CLR Set this bit to clear the USB_DEVICE_STUFF_ERR_INT interrupt. 7 1 write-only - USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR + IN_TOKEN_REC_IN_EP1_INT_CLR Set this bit to clear the USB_DEVICE_IN_TOKEN_IN_EP1_INT interrupt. 8 1 write-only - USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR + USB_BUS_RESET_INT_CLR Set this bit to clear the USB_DEVICE_USB_BUS_RESET_INT interrupt. 9 1 write-only - USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR + OUT_EP1_ZERO_PAYLOAD_INT_CLR Set this bit to clear the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt. 10 1 write-only - USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR + OUT_EP2_ZERO_PAYLOAD_INT_CLR Set this bit to clear the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt. 11 1 write-only - USB_SERIAL_JTAG_RTS_CHG_INT_CLR + RTS_CHG_INT_CLR Set this bit to clear the USB_DEVICE_RTS_CHG_INT interrupt. 12 1 write-only - USB_SERIAL_JTAG_DTR_CHG_INT_CLR + DTR_CHG_INT_CLR Set this bit to clear the USB_DEVICE_DTR_CHG_INT interrupt. 13 1 write-only - USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR + GET_LINE_CODE_INT_CLR Set this bit to clear the USB_DEVICE_GET_LINE_CODE_INT interrupt. 14 1 write-only - USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR + SET_LINE_CODE_INT_CLR Set this bit to clear the USB_DEVICE_SET_LINE_CODE_INT interrupt. 15 1 @@ -28861,98 +49463,98 @@ protection is enabled. 0x00004200 - USB_SERIAL_JTAG_PHY_SEL + PHY_SEL Select internal/external PHY 0 1 read-write - USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE + EXCHG_PINS_OVERRIDE Enable software control USB D+ D- exchange 1 1 read-write - USB_SERIAL_JTAG_EXCHG_PINS + EXCHG_PINS USB D+ D- exchange 2 1 read-write - USB_SERIAL_JTAG_VREFH + VREFH Control single-end input high threshold,1.76V to 2V, step 80mV 3 2 read-write - USB_SERIAL_JTAG_VREFL + VREFL Control single-end input low threshold,0.8V to 1.04V, step 80mV 5 2 read-write - USB_SERIAL_JTAG_VREF_OVERRIDE + VREF_OVERRIDE Enable software control input threshold 7 1 read-write - USB_SERIAL_JTAG_PAD_PULL_OVERRIDE + PAD_PULL_OVERRIDE Enable software control USB D+ D- pullup pulldown 8 1 read-write - USB_SERIAL_JTAG_DP_PULLUP + DP_PULLUP Control USB D+ pull up. 9 1 read-write - USB_SERIAL_JTAG_DP_PULLDOWN + DP_PULLDOWN Control USB D+ pull down. 10 1 read-write - USB_SERIAL_JTAG_DM_PULLUP + DM_PULLUP Control USB D- pull up. 11 1 read-write - USB_SERIAL_JTAG_DM_PULLDOWN + DM_PULLDOWN Control USB D- pull down. 12 1 read-write - USB_SERIAL_JTAG_PULLUP_VALUE + PULLUP_VALUE Control pull up value. 13 1 read-write - USB_SERIAL_JTAG_USB_PAD_ENABLE + USB_PAD_ENABLE Enable USB pad function. 14 1 read-write - USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN + USB_JTAG_BRIDGE_EN Set this bit usb_jtag, the connection between usb_jtag and internal JTAG is disconnected, and MTMS, MTDI, MTCK are output through GPIO Matrix, MTDO is input through GPIO Matrix. 15 1 @@ -28968,49 +49570,49 @@ protection is enabled. 0x00000030 - USB_SERIAL_JTAG_TEST_ENABLE + TEST_ENABLE Enable test of the USB pad 0 1 read-write - USB_SERIAL_JTAG_TEST_USB_OE + TEST_USB_OE USB pad oen in test 1 1 read-write - USB_SERIAL_JTAG_TEST_TX_DP + TEST_TX_DP USB D+ tx value in test 2 1 read-write - USB_SERIAL_JTAG_TEST_TX_DM + TEST_TX_DM USB D- tx value in test 3 1 read-write - USB_SERIAL_JTAG_TEST_RX_RCV + TEST_RX_RCV USB RCV value in test 4 1 read-only - USB_SERIAL_JTAG_TEST_RX_DP + TEST_RX_DP USB D+ rx value in test 5 1 read-only - USB_SERIAL_JTAG_TEST_RX_DM + TEST_RX_DM USB D- rx value in test 6 1 @@ -29026,56 +49628,56 @@ protection is enabled. 0x00000044 - USB_SERIAL_JTAG_IN_FIFO_CNT + IN_FIFO_CNT JTAT in fifo counter. 0 2 read-only - USB_SERIAL_JTAG_IN_FIFO_EMPTY + IN_FIFO_EMPTY 1: JTAG in fifo is empty. 2 1 read-only - USB_SERIAL_JTAG_IN_FIFO_FULL + IN_FIFO_FULL 1: JTAG in fifo is full. 3 1 read-only - USB_SERIAL_JTAG_OUT_FIFO_CNT + OUT_FIFO_CNT JTAT out fifo counter. 4 2 read-only - USB_SERIAL_JTAG_OUT_FIFO_EMPTY + OUT_FIFO_EMPTY 1: JTAG out fifo is empty. 6 1 read-only - USB_SERIAL_JTAG_OUT_FIFO_FULL + OUT_FIFO_FULL 1: JTAG out fifo is full. 7 1 read-only - USB_SERIAL_JTAG_IN_FIFO_RESET + IN_FIFO_RESET Write 1 to reset JTAG in fifo. 8 1 read-write - USB_SERIAL_JTAG_OUT_FIFO_RESET + OUT_FIFO_RESET Write 1 to reset JTAG out fifo. 9 1 @@ -29090,7 +49692,7 @@ protection is enabled. 0x20 - USB_SERIAL_JTAG_SOF_FRAME_INDEX + SOF_FRAME_INDEX Frame index of received SOF frame. 0 11 @@ -29106,21 +49708,21 @@ protection is enabled. 0x00000001 - USB_SERIAL_JTAG_IN_EP0_STATE + IN_EP0_STATE State of IN Endpoint 0. 0 2 read-only - USB_SERIAL_JTAG_IN_EP0_WR_ADDR + IN_EP0_WR_ADDR Write data address of IN endpoint 0. 2 7 read-only - USB_SERIAL_JTAG_IN_EP0_RD_ADDR + IN_EP0_RD_ADDR Read data address of IN endpoint 0. 9 7 @@ -29136,21 +49738,21 @@ protection is enabled. 0x00000001 - USB_SERIAL_JTAG_IN_EP1_STATE + IN_EP1_STATE State of IN Endpoint 1. 0 2 read-only - USB_SERIAL_JTAG_IN_EP1_WR_ADDR + IN_EP1_WR_ADDR Write data address of IN endpoint 1. 2 7 read-only - USB_SERIAL_JTAG_IN_EP1_RD_ADDR + IN_EP1_RD_ADDR Read data address of IN endpoint 1. 9 7 @@ -29166,21 +49768,21 @@ protection is enabled. 0x00000001 - USB_SERIAL_JTAG_IN_EP2_STATE + IN_EP2_STATE State of IN Endpoint 2. 0 2 read-only - USB_SERIAL_JTAG_IN_EP2_WR_ADDR + IN_EP2_WR_ADDR Write data address of IN endpoint 2. 2 7 read-only - USB_SERIAL_JTAG_IN_EP2_RD_ADDR + IN_EP2_RD_ADDR Read data address of IN endpoint 2. 9 7 @@ -29196,21 +49798,21 @@ protection is enabled. 0x00000001 - USB_SERIAL_JTAG_IN_EP3_STATE + IN_EP3_STATE State of IN Endpoint 3. 0 2 read-only - USB_SERIAL_JTAG_IN_EP3_WR_ADDR + IN_EP3_WR_ADDR Write data address of IN endpoint 3. 2 7 read-only - USB_SERIAL_JTAG_IN_EP3_RD_ADDR + IN_EP3_RD_ADDR Read data address of IN endpoint 3. 9 7 @@ -29225,21 +49827,21 @@ protection is enabled. 0x20 - USB_SERIAL_JTAG_OUT_EP0_STATE + OUT_EP0_STATE State of OUT Endpoint 0. 0 2 read-only - USB_SERIAL_JTAG_OUT_EP0_WR_ADDR + OUT_EP0_WR_ADDR Write data address of OUT endpoint 0. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0. 2 7 read-only - USB_SERIAL_JTAG_OUT_EP0_RD_ADDR + OUT_EP0_RD_ADDR Read data address of OUT endpoint 0. 9 7 @@ -29254,28 +49856,28 @@ protection is enabled. 0x20 - USB_SERIAL_JTAG_OUT_EP1_STATE + OUT_EP1_STATE State of OUT Endpoint 1. 0 2 read-only - USB_SERIAL_JTAG_OUT_EP1_WR_ADDR + OUT_EP1_WR_ADDR Write data address of OUT endpoint 1. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1. 2 7 read-only - USB_SERIAL_JTAG_OUT_EP1_RD_ADDR + OUT_EP1_RD_ADDR Read data address of OUT endpoint 1. 9 7 read-only - USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT + OUT_EP1_REC_DATA_CNT Data count in OUT endpoint 1 when one packet is received. 16 7 @@ -29290,21 +49892,21 @@ protection is enabled. 0x20 - USB_SERIAL_JTAG_OUT_EP2_STATE + OUT_EP2_STATE State of OUT Endpoint 2. 0 2 read-only - USB_SERIAL_JTAG_OUT_EP2_WR_ADDR + OUT_EP2_WR_ADDR Write data address of OUT endpoint 2. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2. 2 7 read-only - USB_SERIAL_JTAG_OUT_EP2_RD_ADDR + OUT_EP2_RD_ADDR Read data address of OUT endpoint 2. 9 7 @@ -29319,7 +49921,7 @@ protection is enabled. 0x20 - USB_SERIAL_JTAG_CLK_EN + CLK_EN 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers. 0 1 @@ -29335,14 +49937,14 @@ protection is enabled. 0x00000002 - USB_SERIAL_JTAG_USB_MEM_PD + USB_MEM_PD 1: power down usb memory. 0 1 read-write - USB_SERIAL_JTAG_USB_MEM_CLK_EN + USB_MEM_CLK_EN 1: Force clock on for usb memory. 1 1 @@ -29357,21 +49959,21 @@ protection is enabled. 0x20 - USB_SERIAL_JTAG_RTS + RTS 1: Chip reset is detected from usb serial channel. Software write 1 to clear it. 0 1 read-only - USB_SERIAL_JTAG_DTR + DTR 1: Chip reset is detected from usb jtag channel. Software write 1 to clear it. 1 1 read-only - USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS + USB_UART_CHIP_RST_DIS Set this bit to disable chip reset from usb serial channel to reset chip. 2 1 @@ -29386,7 +49988,7 @@ protection is enabled. 0x20 - USB_SERIAL_JTAG_DW_DTE_RATE + DW_DTE_RATE The value of dwDTERate set by host through SET_LINE_CODING command. 0 32 @@ -29401,21 +50003,21 @@ protection is enabled. 0x20 - USB_SERIAL_JTAG_BCHAR_FORMAT + BCHAR_FORMAT The value of bCharFormat set by host through SET_LINE_CODING command. 0 8 read-only - USB_SERIAL_JTAG_BPARITY_TYPE + BPARITY_TYPE The value of bParityTpye set by host through SET_LINE_CODING command. 8 8 read-only - USB_SERIAL_JTAG_BDATA_BITS + BDATA_BITS The value of bDataBits set by host through SET_LINE_CODING command. 16 8 @@ -29430,7 +50032,7 @@ protection is enabled. 0x20 - USB_SERIAL_JTAG_GET_DW_DTE_RATE + GET_DW_DTE_RATE The value of dwDTERate set by software which is requested by GET_LINE_CODING command. 0 32 @@ -29445,21 +50047,21 @@ protection is enabled. 0x20 - USB_SERIAL_JTAG_GET_BDATA_BITS + GET_BDATA_BITS The value of bCharFormat set by software which is requested by GET_LINE_CODING command. 0 8 read-write - USB_SERIAL_JTAG_GET_BPARITY_TYPE + GET_BPARITY_TYPE The value of bParityTpye set by software which is requested by GET_LINE_CODING command. 8 8 read-write - USB_SERIAL_JTAG_GET_BCHAR_FORMAT + GET_BCHAR_FORMAT The value of bDataBits set by software which is requested by GET_LINE_CODING command. 16 8 @@ -29474,7 +50076,7 @@ protection is enabled. 0x20 - USB_SERIAL_JTAG_CONFIG_UPDATE + CONFIG_UPDATE Write 1 to this register would update the value of configure registers from APB clock domain to 48MHz clock domain. 0 1 @@ -29490,42 +50092,42 @@ protection is enabled. 0x00000010 - USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR + SERIAL_IN_AFIFO_RESET_WR Write 1 to reset CDC_ACM IN async FIFO write clock domain. 0 1 read-write - USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD + SERIAL_IN_AFIFO_RESET_RD Write 1 to reset CDC_ACM IN async FIFO read clock domain. 1 1 read-write - USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR + SERIAL_OUT_AFIFO_RESET_WR Write 1 to reset CDC_ACM OUT async FIFO write clock domain. 2 1 read-write - USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD + SERIAL_OUT_AFIFO_RESET_RD Write 1 to reset CDC_ACM OUT async FIFO read clock domain. 3 1 read-write - USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY + SERIAL_OUT_AFIFO_REMPTY CDC_ACM OUTOUT async FIFO empty signal in read clock domain. 4 1 read-only - USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL + SERIAL_IN_AFIFO_WFULL CDC_ACM OUT IN async FIFO empty signal in write clock domain. 5 1 @@ -29541,7 +50143,7 @@ protection is enabled. 0x00000001 - USB_SERIAL_JTAG_USB_BUS_RESET_ST + USB_BUS_RESET_ST USB bus reset status. 0: USB-Serial-JTAG is in usb bus reset status. 1: USB bus reset is released. 0 1 @@ -29557,7 +50159,7 @@ protection is enabled. 0x02109220 - USB_SERIAL_JTAG_DATE + DATE register version. 0 32 diff --git a/svd/esp32s2.svd b/svd/esp32s2.svd index 3154d59..0b945d4 100644 --- a/svd/esp32s2.svd +++ b/svd/esp32s2.svd @@ -3,11 +3,11 @@ ESPRESSIF SYSTEMS (SHANGHAI) CO., LTD. ESPRESSIF ESP32-S2 - ESP32-S2 - 11 + ESP32 S-Series + 12 32-bit MCU & 2.4 GHz Wi-Fi - Copyright 2022 Espressif Systems (Shanghai) PTE LTD + Copyright 2023 Espressif Systems (Shanghai) PTE LTD Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -16641,7 +16641,7 @@ ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd struc 0x00003C10 - FILTER_THRES_U0 + FILTER_THRES This sets the maximum threshold, in APB_CLK cycles, for the filter. Any pulses with width less than this will be ignored when the filter is enabled. 0 @@ -16649,49 +16649,49 @@ Any pulses with width less than this will be ignored when the filter is enabled. read-write - FILTER_EN_U0 + FILTER_EN This is the enable bit for unit %s's input filter. 10 1 read-write - THR_ZERO_EN_U0 + THR_ZERO_EN This is the enable bit for unit %s's zero comparator. 11 1 read-write - THR_H_LIM_EN_U0 + THR_H_LIM_EN This is the enable bit for unit %s's thr_h_lim comparator. 12 1 read-write - THR_L_LIM_EN_U0 + THR_L_LIM_EN This is the enable bit for unit %s's thr_l_lim comparator. 13 1 read-write - THR_THRES0_EN_U0 + THR_THRES0_EN This is the enable bit for unit %s's thres0 comparator. 14 1 read-write - THR_THRES1_EN_U0 + THR_THRES1_EN This is the enable bit for unit %s's thres1 comparator. 15 1 read-write - CH0_NEG_MODE_U0 + CH0_NEG_MODE This register sets the behavior when the signal input of channel 0 detects a negative edge. 1: Increase the counter. 2: Decrease the counter. 0, 3: No effect on counter. 16 @@ -16699,7 +16699,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. read-write - CH0_POS_MODE_U0 + CH0_POS_MODE This register sets the behavior when the signal input of channel 0 detects a positive edge. 1: Increase the counter. 2: Decrease the counter. 0, 3: No effect on counter. 18 @@ -16707,7 +16707,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. read-write - CH0_HCTRL_MODE_U0 + CH0_HCTRL_MODE This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is high. 0: No modification. 1: Invert behavior (increase -> decrease, decrease -> increase). 2, 3: Inhibit counter modification. 20 @@ -16715,7 +16715,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. read-write - CH0_LCTRL_MODE_U0 + CH0_LCTRL_MODE This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is low. 0: No modification. 1: Invert behavior (increase -> decrease, decrease -> increase). 2, 3: Inhibit counter modification. 22 @@ -16723,7 +16723,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. read-write - CH1_NEG_MODE_U0 + CH1_NEG_MODE This register sets the behavior when the signal input of channel 1 detects a negative edge. 1: Increment the counter. 2: Decrement the counter. 0, 3: No effect on counter. 24 @@ -16731,7 +16731,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. read-write - CH1_POS_MODE_U0 + CH1_POS_MODE This register sets the behavior when the signal input of channel 1 detects a positive edge. 1: Increment the counter. 2: Decrement the counter. 0, 3: No effect on counter. 26 @@ -16739,7 +16739,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. read-write - CH1_HCTRL_MODE_U0 + CH1_HCTRL_MODE This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is high. 0: No modification. 1: Invert behavior (increase -> decrease, decrease -> increase). 2, 3: Inhibit counter modification. 28 @@ -16747,7 +16747,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. read-write - CH1_LCTRL_MODE_U0 + CH1_LCTRL_MODE This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is low. 0: No modification. 1: Invert behavior (increase -> decrease, decrease -> increase). 2, 3: Inhibit counter modification. 30 @@ -16765,14 +16765,14 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0x20 - CNT_THRES0_U0 + CNT_THRES0 This register is used to configure the thres0 value for unit %s. 0 16 read-write - CNT_THRES1_U0 + CNT_THRES1 This register is used to configure the thres1 value for unit %s. 16 16 @@ -16789,14 +16789,14 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0x20 - CNT_H_LIM_U0 + CNT_H_LIM This register is used to configure the thr_h_lim value for unit %s. 0 16 read-write - CNT_L_LIM_U0 + CNT_L_LIM This register is used to configure the thr_l_lim value for unit %s. 16 16 @@ -16813,7 +16813,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0x20 - PULSE_CNT_U0 + CNT This register stores the current pulse count value for unit %s. 0 16 @@ -16828,28 +16828,28 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0x20 - CNT_THR_EVENT_U0_INT_RAW + CNT_THR_EVENT_U0 The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. 0 1 read-only - CNT_THR_EVENT_U1_INT_RAW + CNT_THR_EVENT_U1 The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. 1 1 read-only - CNT_THR_EVENT_U2_INT_RAW + CNT_THR_EVENT_U2 The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. 2 1 read-only - CNT_THR_EVENT_U3_INT_RAW + CNT_THR_EVENT_U3 The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. 3 1 @@ -16864,28 +16864,28 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0x20 - CNT_THR_EVENT_U0_INT_ST + CNT_THR_EVENT_U0 The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. 0 1 read-only - CNT_THR_EVENT_U1_INT_ST + CNT_THR_EVENT_U1 The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. 1 1 read-only - CNT_THR_EVENT_U2_INT_ST + CNT_THR_EVENT_U2 The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. 2 1 read-only - CNT_THR_EVENT_U3_INT_ST + CNT_THR_EVENT_U3 The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. 3 1 @@ -16900,28 +16900,28 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0x20 - CNT_THR_EVENT_U0_INT_ENA + CNT_THR_EVENT_U0 The interrupt enable bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. 0 1 read-write - CNT_THR_EVENT_U1_INT_ENA + CNT_THR_EVENT_U1 The interrupt enable bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. 1 1 read-write - CNT_THR_EVENT_U2_INT_ENA + CNT_THR_EVENT_U2 The interrupt enable bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. 2 1 read-write - CNT_THR_EVENT_U3_INT_ENA + CNT_THR_EVENT_U3 The interrupt enable bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. 3 1 @@ -16936,28 +16936,28 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0x20 - CNT_THR_EVENT_U0_INT_CLR + CNT_THR_EVENT_U0 Set this bit to clear the PCNT_CNT_THR_EVENT_U0_INT interrupt. 0 1 write-only - CNT_THR_EVENT_U1_INT_CLR + CNT_THR_EVENT_U1 Set this bit to clear the PCNT_CNT_THR_EVENT_U1_INT interrupt. 1 1 write-only - CNT_THR_EVENT_U2_INT_CLR + CNT_THR_EVENT_U2 Set this bit to clear the PCNT_CNT_THR_EVENT_U2_INT interrupt. 2 1 write-only - CNT_THR_EVENT_U3_INT_CLR + CNT_THR_EVENT_U3 Set this bit to clear the PCNT_CNT_THR_EVENT_U3_INT interrupt. 3 1 @@ -16974,42 +16974,42 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0x20 - CNT_THR_ZERO_MODE_U0 + ZERO_MODE The pulse counter status of PCNT_U%s corresponding to 0. 0: pulse counter decreases from positive to 0. 1: pulse counter increases from negative to 0. 2: pulse counter is negative. 3: pulse counter is positive. 0 2 read-only - CNT_THR_THRES1_LAT_U0 + THRES1 The latched value of thres1 event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thres1 and thres1 event is valid. 0: others. 2 1 read-only - CNT_THR_THRES0_LAT_U0 + THRES0 The latched value of thres0 event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thres0 and thres0 event is valid. 0: others. 3 1 read-only - CNT_THR_L_LIM_LAT_U0 + L_LIM The latched value of low limit event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thr_l_lim and low limit event is valid. 0: others. 4 1 read-only - CNT_THR_H_LIM_LAT_U0 + H_LIM The latched value of high limit event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thr_h_lim and high limit event is valid. 0: others. 5 1 read-only - CNT_THR_ZERO_LAT_U0 + ZERO The latched value of zero threshold event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to 0 and zero threshold event is valid. 0: others. 6 1 @@ -17025,7 +17025,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0x00000055 - PULSE_CNT_RST_U0 + CNT_RST_U0 Set this bit to clear unit 0's counter. 0 1 @@ -17039,7 +17039,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. read-write - PULSE_CNT_RST_U1 + CNT_RST_U1 Set this bit to clear unit 2's counter. 2 1 @@ -17053,7 +17053,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. read-write - PULSE_CNT_RST_U2 + CNT_RST_U2 Set this bit to clear unit 4's counter. 4 1 @@ -17067,7 +17067,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. read-write - PULSE_CNT_RST_U3 + CNT_RST_U3 Set this bit to clear unit 6's counter. 6 1 @@ -18962,7 +18962,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. - CLOCK_GATE_REG + CLOCK_GATE Clock gate register of permission control. 0x104 0x20 @@ -28001,7 +28001,7 @@ I2C_COMD0_REG in Chapter I²C Controller - CONTINUE_OP + CONTINUE_ Continues SHA operation (only effective in Typical SHA mode) 0x14 0x20 @@ -28111,7 +28111,7 @@ I2C_COMD0_REG in Chapter I²C Controller 16 0x4 - H_%s + H_MEM%s Hash value 0x40 0x20 @@ -28128,7 +28128,7 @@ I2C_COMD0_REG in Chapter I²C Controller 32 0x4 - M_%s + M_MEM%s Message 0x80 0x20 @@ -31463,7 +31463,7 @@ I2C_COMD0_REG in Chapter I²C Controller read-write - CAN_CLK_EN + TWAI_CLK_EN Set this bit to enable clock of CAN. 19 1 @@ -31745,7 +31745,7 @@ I2C_COMD0_REG in Chapter I²C Controller read-write - CAN_RST + TWAI_RST Set this bit to reset CAN. 19 1 @@ -34147,7 +34147,7 @@ Timer %s alarm trigger time-base counter value, high 32 bits. In reset mode, it is acceptance code register 0 with R/W Permission. In operation mode, it stores the 0th byte information of the data to be transmitted under operating mode. 0 8 - write-only + read-write @@ -34162,7 +34162,7 @@ Timer %s alarm trigger time-base counter value, high 32 bits. In reset mode, it is acceptance code register 1 with R/W Permission. In operation mode, it stores the 1st byte information of the data to be transmitted under operating mode. 0 8 - write-only + read-write @@ -34177,7 +34177,7 @@ Timer %s alarm trigger time-base counter value, high 32 bits. In reset mode, it is acceptance code register 2 with R/W Permission. In operation mode, it stores the 2nd byte information of the data to be transmitted under operating mode. 0 8 - write-only + read-write @@ -34192,7 +34192,7 @@ Timer %s alarm trigger time-base counter value, high 32 bits. In reset mode, it is acceptance code register 3 with R/W Permission. In operation mode, it stores the 3rd byte information of the data to be transmitted under operating mode. 0 8 - write-only + read-write @@ -34207,7 +34207,7 @@ Timer %s alarm trigger time-base counter value, high 32 bits. In reset mode, it is acceptance mask register 0 with R/W Permission. In operation mode, it stores the 4th byte information of the data to be transmitted under operating mode. 0 8 - write-only + read-write @@ -34222,7 +34222,7 @@ Timer %s alarm trigger time-base counter value, high 32 bits. In reset mode, it is acceptance mask register 1 with R/W Permission. In operation mode, it stores the 5th byte information of the data to be transmitted under operating mode. 0 8 - write-only + read-write @@ -34237,7 +34237,7 @@ Timer %s alarm trigger time-base counter value, high 32 bits. In reset mode, it is acceptance mask register 2 with R/W Permission. In operation mode, it stores the 6th byte information of the data to be transmitted under operating mode. 0 8 - write-only + read-write @@ -34252,7 +34252,7 @@ Timer %s alarm trigger time-base counter value, high 32 bits. In reset mode, it is acceptance mask register 3 with R/W Permission. In operation mode, it stores the 7th byte information of the data to be transmitted under operating mode. 0 8 - write-only + read-write @@ -34267,7 +34267,7 @@ Timer %s alarm trigger time-base counter value, high 32 bits. Stored the 8th byte information of the data to be transmitted under operating mode. 0 8 - write-only + read-write @@ -34282,7 +34282,7 @@ Timer %s alarm trigger time-base counter value, high 32 bits. Stored the 9th byte information of the data to be transmitted under operating mode. 0 8 - write-only + read-write @@ -34297,7 +34297,7 @@ Timer %s alarm trigger time-base counter value, high 32 bits. Stored the 10th byte information of the data to be transmitted under operating mode. 0 8 - write-only + read-write @@ -34312,7 +34312,7 @@ Timer %s alarm trigger time-base counter value, high 32 bits. Stored the 11th byte information of the data to be transmitted under operating mode. 0 8 - write-only + read-write @@ -34327,7 +34327,7 @@ Timer %s alarm trigger time-base counter value, high 32 bits. Stored the 12th byte information of the data to be transmitted under operating mode. 0 8 - write-only + read-write diff --git a/svd/esp32s3.svd b/svd/esp32s3.svd index b1222ec..f5c1531 100644 --- a/svd/esp32s3.svd +++ b/svd/esp32s3.svd @@ -3,11 +3,11 @@ ESPRESSIF SYSTEMS (SHANGHAI) CO., LTD. ESPRESSIF ESP32-S3 - ESP32-S3 - 12 + ESP32 S-Series + 13 32-bit MCU & 2.4 GHz Wi-Fi & Bluetooth 5 (LE) - Copyright 2022 Espressif Systems (Shanghai) PTE LTD + Copyright 2023 Espressif Systems (Shanghai) PTE LTD Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -1800,7 +1800,7 @@ - APB_ADC_ARB_CTRL + ARB_CTRL configure apb saradc arbit 0x38 0x20 @@ -2243,7 +2243,7 @@ - APB_ADC_CLKM_CONF + CLKM_CONF configure apb saradc clock 0x70 0x20 @@ -15204,34 +15204,34 @@ level. - I2S_INT_RAW + INT_RAW I2S interrupt raw register, valid in level. 0xC 0x20 - I2S_RX_DONE_INT_RAW + RX_DONE_INT_RAW The raw interrupt status bit for the i2s_rx_done_int interrupt 0 1 read-only - I2S_TX_DONE_INT_RAW + TX_DONE_INT_RAW The raw interrupt status bit for the i2s_tx_done_int interrupt 1 1 read-only - I2S_RX_HUNG_INT_RAW + RX_HUNG_INT_RAW The raw interrupt status bit for the i2s_rx_hung_int interrupt 2 1 read-only - I2S_TX_HUNG_INT_RAW + TX_HUNG_INT_RAW The raw interrupt status bit for the i2s_tx_hung_int interrupt 3 1 @@ -15240,34 +15240,34 @@ level. - I2S_INT_ST + INT_ST I2S interrupt status register. 0x10 0x20 - I2S_RX_DONE_INT_ST + RX_DONE_INT_ST The masked interrupt status bit for the i2s_rx_done_int interrupt 0 1 read-only - I2S_TX_DONE_INT_ST + TX_DONE_INT_ST The masked interrupt status bit for the i2s_tx_done_int interrupt 1 1 read-only - I2S_RX_HUNG_INT_ST + RX_HUNG_INT_ST The masked interrupt status bit for the i2s_rx_hung_int interrupt 2 1 read-only - I2S_TX_HUNG_INT_ST + TX_HUNG_INT_ST The masked interrupt status bit for the i2s_tx_hung_int interrupt 3 1 @@ -15276,34 +15276,34 @@ level. - I2S_INT_ENA + INT_ENA I2S interrupt enable register. 0x14 0x20 - I2S_RX_DONE_INT_ENA + RX_DONE_INT_ENA The interrupt enable bit for the i2s_rx_done_int interrupt 0 1 read-write - I2S_TX_DONE_INT_ENA + TX_DONE_INT_ENA The interrupt enable bit for the i2s_tx_done_int interrupt 1 1 read-write - I2S_RX_HUNG_INT_ENA + RX_HUNG_INT_ENA The interrupt enable bit for the i2s_rx_hung_int interrupt 2 1 read-write - I2S_TX_HUNG_INT_ENA + TX_HUNG_INT_ENA The interrupt enable bit for the i2s_tx_hung_int interrupt 3 1 @@ -15312,34 +15312,34 @@ level. - I2S_INT_CLR + INT_CLR I2S interrupt clear register. 0x18 0x20 - I2S_RX_DONE_INT_CLR + RX_DONE_INT_CLR Set this bit to clear the i2s_rx_done_int interrupt 0 1 write-only - I2S_TX_DONE_INT_CLR + TX_DONE_INT_CLR Set this bit to clear the i2s_tx_done_int interrupt 1 1 write-only - I2S_RX_HUNG_INT_CLR + RX_HUNG_INT_CLR Set this bit to clear the i2s_rx_hung_int interrupt 2 1 write-only - I2S_TX_HUNG_INT_CLR + TX_HUNG_INT_CLR Set this bit to clear the i2s_tx_hung_int interrupt 3 1 @@ -15348,126 +15348,126 @@ level. - I2S_RX_CONF + RX_CONF I2S RX configure register 0x20 0x20 0x00009600 - I2S_RX_RESET + RX_RESET Set this bit to reset receiver 0 1 write-only - I2S_RX_FIFO_RESET + RX_FIFO_RESET Set this bit to reset Rx AFIFO 1 1 write-only - I2S_RX_START + RX_START Set this bit to start receiving data 2 1 read-write - I2S_RX_SLAVE_MOD + RX_SLAVE_MOD Set this bit to enable slave receiver mode 3 1 read-write - I2S_RX_MONO + RX_MONO Set this bit to enable receiver in mono mode 5 1 read-write - I2S_RX_BIG_ENDIAN + RX_BIG_ENDIAN I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value. 7 1 read-write - I2S_RX_UPDATE + RX_UPDATE Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This bit will be cleared by hardware after update register done. 8 1 read-write - I2S_RX_MONO_FST_VLD + RX_MONO_FST_VLD 1: The first channel data value is valid in I2S RX mono mode. 0: The second channel data value is valid in I2S RX mono mode. 9 1 read-write - I2S_RX_PCM_CONF + RX_PCM_CONF I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. & 10 2 read-write - I2S_RX_PCM_BYPASS + RX_PCM_BYPASS Set this bit to bypass Compress/Decompress module for received data. 12 1 read-write - I2S_RX_STOP_MODE + RX_STOP_MODE 0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when reg_rx_start is 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is full. 13 2 read-write - I2S_RX_LEFT_ALIGN + RX_LEFT_ALIGN 1: I2S RX left alignment mode. 0: I2S RX right alignment mode. 15 1 read-write - I2S_RX_24_FILL_EN + RX_24_FILL_EN 1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits. 16 1 read-write - I2S_RX_WS_IDLE_POL + RX_WS_IDLE_POL 0: WS should be 0 when receiving left channel data, and WS is 1in right channel. 1: WS should be 1 when receiving left channel data, and WS is 0in right channel. 17 1 read-write - I2S_RX_BIT_ORDER + RX_BIT_ORDER I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB is received first. 18 1 read-write - I2S_RX_TDM_EN + RX_TDM_EN 1: Enable I2S TDM Rx mode . 0: Disable. 19 1 read-write - I2S_RX_PDM_EN + RX_PDM_EN 1: Enable I2S PDM Rx mode . 0: Disable. 20 1 @@ -15476,147 +15476,147 @@ level. - I2S_TX_CONF + TX_CONF I2S TX configure register 0x24 0x20 0x0000B200 - I2S_TX_RESET + TX_RESET Set this bit to reset transmitter 0 1 write-only - I2S_TX_FIFO_RESET + TX_FIFO_RESET Set this bit to reset Tx AFIFO 1 1 write-only - I2S_TX_START + TX_START Set this bit to start transmitting data 2 1 read-write - I2S_TX_SLAVE_MOD + TX_SLAVE_MOD Set this bit to enable slave transmitter mode 3 1 read-write - I2S_TX_MONO + TX_MONO Set this bit to enable transmitter in mono mode 5 1 read-write - I2S_TX_CHAN_EQUAL + TX_CHAN_EQUAL 1: The value of Left channel data is equal to the value of right channel data in I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is reg_i2s_single_data in I2S TX mono mode or TDM channel select mode. 6 1 read-write - I2S_TX_BIG_ENDIAN + TX_BIG_ENDIAN I2S Tx byte endian, 1: low addr value to high addr. 0: low addr with low addr value. 7 1 read-write - I2S_TX_UPDATE + TX_UPDATE Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This bit will be cleared by hardware after update register done. 8 1 read-write - I2S_TX_MONO_FST_VLD + TX_MONO_FST_VLD 1: The first channel data value is valid in I2S TX mono mode. 0: The second channel data value is valid in I2S TX mono mode. 9 1 read-write - I2S_TX_PCM_CONF + TX_PCM_CONF I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. & 10 2 read-write - I2S_TX_PCM_BYPASS + TX_PCM_BYPASS Set this bit to bypass Compress/Decompress module for transmitted data. 12 1 read-write - I2S_TX_STOP_EN + TX_STOP_EN Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy 13 1 read-write - I2S_TX_LEFT_ALIGN + TX_LEFT_ALIGN 1: I2S TX left alignment mode. 0: I2S TX right alignment mode. 15 1 read-write - I2S_TX_24_FILL_EN + TX_24_FILL_EN 1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode 16 1 read-write - I2S_TX_WS_IDLE_POL + TX_WS_IDLE_POL 0: WS should be 0 when sending left channel data, and WS is 1in right channel. 1: WS should be 1 when sending left channel data, and WS is 0in right channel. 17 1 read-write - I2S_TX_BIT_ORDER + TX_BIT_ORDER I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is sent first. 18 1 read-write - I2S_TX_TDM_EN + TX_TDM_EN 1: Enable I2S TDM Tx mode . 0: Disable. 19 1 read-write - I2S_TX_PDM_EN + TX_PDM_EN 1: Enable I2S PDM Tx mode . 0: Disable. 20 1 read-write - I2S_TX_CHAN_MOD + TX_CHAN_MOD I2S transmitter channel mode configuration bits. 24 3 read-write - I2S_SIG_LOOPBACK + SIG_LOOPBACK Enable signal loop back mode with transmitter module and receiver module sharing the same WS and BCK signals. 27 1 @@ -15625,49 +15625,49 @@ level. - I2S_RX_CONF1 + RX_CONF1 I2S RX configure register 1 0x28 0x20 0x2F3DE300 - I2S_RX_TDM_WS_WIDTH + RX_TDM_WS_WIDTH The width of rx_ws_out in TDM mode is (I2S_RX_TDM_WS_WIDTH[6:0] +1) * T_bck 0 7 read-write - I2S_RX_BCK_DIV_NUM + RX_BCK_DIV_NUM Bit clock configuration bits in receiver mode. 7 6 read-write - I2S_RX_BITS_MOD + RX_BITS_MOD Set the bits to configure the valid data bit length of I2S receiver channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode. 13 5 read-write - I2S_RX_HALF_SAMPLE_BITS + RX_HALF_SAMPLE_BITS I2S Rx half sample bits -1. 18 6 read-write - I2S_RX_TDM_CHAN_BITS + RX_TDM_CHAN_BITS The Rx bit number for each channel minus 1in TDM mode. 24 5 read-write - I2S_RX_MSB_SHIFT + RX_MSB_SHIFT Set this bit to enable receiver in Phillips standard mode 29 1 @@ -15676,56 +15676,56 @@ level. - I2S_TX_CONF1 + TX_CONF1 I2S TX configure register 1 0x2C 0x20 0x6F3DE300 - I2S_TX_TDM_WS_WIDTH + TX_TDM_WS_WIDTH The width of tx_ws_out in TDM mode is (I2S_TX_TDM_WS_WIDTH[6:0] +1) * T_bck 0 7 read-write - I2S_TX_BCK_DIV_NUM + TX_BCK_DIV_NUM Bit clock configuration bits in transmitter mode. 7 6 read-write - I2S_TX_BITS_MOD + TX_BITS_MOD Set the bits to configure the valid data bit length of I2S transmitter channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode. 13 5 read-write - I2S_TX_HALF_SAMPLE_BITS + TX_HALF_SAMPLE_BITS I2S Tx half sample bits -1. 18 6 read-write - I2S_TX_TDM_CHAN_BITS + TX_TDM_CHAN_BITS The Tx bit number for each channel minus 1in TDM mode. 24 5 read-write - I2S_TX_MSB_SHIFT + TX_MSB_SHIFT Set this bit to enable transmitter in Phillips standard mode 29 1 read-write - I2S_TX_BCK_NO_DLY + TX_BCK_NO_DLY 1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to generate pos/neg edge in master mode. 30 1 @@ -15734,35 +15734,35 @@ level. - I2S_RX_CLKM_CONF + RX_CLKM_CONF I2S RX clock configure register 0x30 0x20 0x00000002 - I2S_RX_CLKM_DIV_NUM + RX_CLKM_DIV_NUM Integral I2S clock divider value 0 8 read-write - I2S_RX_CLK_ACTIVE + RX_CLK_ACTIVE I2S Rx module clock enable signal. 26 1 read-write - I2S_RX_CLK_SEL + RX_CLK_SEL Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in. 27 2 read-write - I2S_MCLK_SEL + MCLK_SEL 0: UseI2S Tx module clock as I2S_MCLK_OUT. 1: UseI2S Rx module clock as I2S_MCLK_OUT. 29 1 @@ -15771,35 +15771,35 @@ level. - I2S_TX_CLKM_CONF + TX_CLKM_CONF I2S TX clock configure register 0x34 0x20 0x00000002 - I2S_TX_CLKM_DIV_NUM + TX_CLKM_DIV_NUM Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <= a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x * (n+1)-div] + y * (n+1)-div. 0 8 read-write - I2S_TX_CLK_ACTIVE + TX_CLK_ACTIVE I2S Tx module clock enable signal. 26 1 read-write - I2S_TX_CLK_SEL + TX_CLK_SEL Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in. 27 2 read-write - I2S_CLK_EN + CLK_EN Set this bit to enable clk gate 29 1 @@ -15808,35 +15808,35 @@ level. - I2S_RX_CLKM_DIV_CONF + RX_CLKM_DIV_CONF I2S RX module clock divider configure register 0x38 0x20 0x00000200 - I2S_RX_CLKM_DIV_Z + RX_CLKM_DIV_Z For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_RX_CLKM_DIV_Z is (a-b). 0 9 read-write - I2S_RX_CLKM_DIV_Y + RX_CLKM_DIV_Y For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_RX_CLKM_DIV_Y is (a%(a-b)). 9 9 read-write - I2S_RX_CLKM_DIV_X + RX_CLKM_DIV_X For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1. 18 9 read-write - I2S_RX_CLKM_DIV_YN1 + RX_CLKM_DIV_YN1 For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_RX_CLKM_DIV_YN1 is 1. 27 1 @@ -15845,35 +15845,35 @@ level. - I2S_TX_CLKM_DIV_CONF + TX_CLKM_DIV_CONF I2S TX module clock divider configure register 0x3C 0x20 0x00000200 - I2S_TX_CLKM_DIV_Z + TX_CLKM_DIV_Z For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_TX_CLKM_DIV_Z is (a-b). 0 9 read-write - I2S_TX_CLKM_DIV_Y + TX_CLKM_DIV_Y For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_TX_CLKM_DIV_Y is (a%(a-b)). 9 9 read-write - I2S_TX_CLKM_DIV_X + TX_CLKM_DIV_X For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1. 18 9 read-write - I2S_TX_CLKM_DIV_YN1 + TX_CLKM_DIV_YN1 For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_TX_CLKM_DIV_YN1 is 1. 27 1 @@ -15882,126 +15882,126 @@ level. - I2S_RX_TDM_CTRL + RX_TDM_CTRL I2S TX TDM mode control register 0x50 0x20 0x0000FFFF - I2S_RX_TDM_PDM_CHAN0_EN + RX_TDM_PDM_CHAN0_EN 1: Enable the valid data input of I2S RX TDM or PDM channel 0. 0: Disable, just input 0 in this channel. 0 1 read-write - I2S_RX_TDM_PDM_CHAN1_EN + RX_TDM_PDM_CHAN1_EN 1: Enable the valid data input of I2S RX TDM or PDM channel 1. 0: Disable, just input 0 in this channel. 1 1 read-write - I2S_RX_TDM_PDM_CHAN2_EN + RX_TDM_PDM_CHAN2_EN 1: Enable the valid data input of I2S RX TDM or PDM channel 2. 0: Disable, just input 0 in this channel. 2 1 read-write - I2S_RX_TDM_PDM_CHAN3_EN + RX_TDM_PDM_CHAN3_EN 1: Enable the valid data input of I2S RX TDM or PDM channel 3. 0: Disable, just input 0 in this channel. 3 1 read-write - I2S_RX_TDM_PDM_CHAN4_EN + RX_TDM_PDM_CHAN4_EN 1: Enable the valid data input of I2S RX TDM or PDM channel 4. 0: Disable, just input 0 in this channel. 4 1 read-write - I2S_RX_TDM_PDM_CHAN5_EN + RX_TDM_PDM_CHAN5_EN 1: Enable the valid data input of I2S RX TDM or PDM channel 5. 0: Disable, just input 0 in this channel. 5 1 read-write - I2S_RX_TDM_PDM_CHAN6_EN + RX_TDM_PDM_CHAN6_EN 1: Enable the valid data input of I2S RX TDM or PDM channel 6. 0: Disable, just input 0 in this channel. 6 1 read-write - I2S_RX_TDM_PDM_CHAN7_EN + RX_TDM_PDM_CHAN7_EN 1: Enable the valid data input of I2S RX TDM or PDM channel 7. 0: Disable, just input 0 in this channel. 7 1 read-write - I2S_RX_TDM_CHAN8_EN + RX_TDM_CHAN8_EN 1: Enable the valid data input of I2S RX TDM channel 8. 0: Disable, just input 0 in this channel. 8 1 read-write - I2S_RX_TDM_CHAN9_EN + RX_TDM_CHAN9_EN 1: Enable the valid data input of I2S RX TDM channel 9. 0: Disable, just input 0 in this channel. 9 1 read-write - I2S_RX_TDM_CHAN10_EN + RX_TDM_CHAN10_EN 1: Enable the valid data input of I2S RX TDM channel 10. 0: Disable, just input 0 in this channel. 10 1 read-write - I2S_RX_TDM_CHAN11_EN + RX_TDM_CHAN11_EN 1: Enable the valid data input of I2S RX TDM channel 11. 0: Disable, just input 0 in this channel. 11 1 read-write - I2S_RX_TDM_CHAN12_EN + RX_TDM_CHAN12_EN 1: Enable the valid data input of I2S RX TDM channel 12. 0: Disable, just input 0 in this channel. 12 1 read-write - I2S_RX_TDM_CHAN13_EN + RX_TDM_CHAN13_EN 1: Enable the valid data input of I2S RX TDM channel 13. 0: Disable, just input 0 in this channel. 13 1 read-write - I2S_RX_TDM_CHAN14_EN + RX_TDM_CHAN14_EN 1: Enable the valid data input of I2S RX TDM channel 14. 0: Disable, just input 0 in this channel. 14 1 read-write - I2S_RX_TDM_CHAN15_EN + RX_TDM_CHAN15_EN 1: Enable the valid data input of I2S RX TDM channel 15. 0: Disable, just input 0 in this channel. 15 1 read-write - I2S_RX_TDM_TOT_CHAN_NUM + RX_TDM_TOT_CHAN_NUM The total channel number of I2S TX TDM mode. 16 4 @@ -16010,133 +16010,133 @@ level. - I2S_TX_TDM_CTRL + TX_TDM_CTRL I2S TX TDM mode control register 0x54 0x20 0x0000FFFF - I2S_TX_TDM_CHAN0_EN + TX_TDM_CHAN0_EN 1: Enable the valid data output of I2S TX TDM channel 0. 0: Disable, just output 0 in this channel. 0 1 read-write - I2S_TX_TDM_CHAN1_EN + TX_TDM_CHAN1_EN 1: Enable the valid data output of I2S TX TDM channel 1. 0: Disable, just output 0 in this channel. 1 1 read-write - I2S_TX_TDM_CHAN2_EN + TX_TDM_CHAN2_EN 1: Enable the valid data output of I2S TX TDM channel 2. 0: Disable, just output 0 in this channel. 2 1 read-write - I2S_TX_TDM_CHAN3_EN + TX_TDM_CHAN3_EN 1: Enable the valid data output of I2S TX TDM channel 3. 0: Disable, just output 0 in this channel. 3 1 read-write - I2S_TX_TDM_CHAN4_EN + TX_TDM_CHAN4_EN 1: Enable the valid data output of I2S TX TDM channel 4. 0: Disable, just output 0 in this channel. 4 1 read-write - I2S_TX_TDM_CHAN5_EN + TX_TDM_CHAN5_EN 1: Enable the valid data output of I2S TX TDM channel 5. 0: Disable, just output 0 in this channel. 5 1 read-write - I2S_TX_TDM_CHAN6_EN + TX_TDM_CHAN6_EN 1: Enable the valid data output of I2S TX TDM channel 6. 0: Disable, just output 0 in this channel. 6 1 read-write - I2S_TX_TDM_CHAN7_EN + TX_TDM_CHAN7_EN 1: Enable the valid data output of I2S TX TDM channel 7. 0: Disable, just output 0 in this channel. 7 1 read-write - I2S_TX_TDM_CHAN8_EN + TX_TDM_CHAN8_EN 1: Enable the valid data output of I2S TX TDM channel 8. 0: Disable, just output 0 in this channel. 8 1 read-write - I2S_TX_TDM_CHAN9_EN + TX_TDM_CHAN9_EN 1: Enable the valid data output of I2S TX TDM channel 9. 0: Disable, just output 0 in this channel. 9 1 read-write - I2S_TX_TDM_CHAN10_EN + TX_TDM_CHAN10_EN 1: Enable the valid data output of I2S TX TDM channel 10. 0: Disable, just output 0 in this channel. 10 1 read-write - I2S_TX_TDM_CHAN11_EN + TX_TDM_CHAN11_EN 1: Enable the valid data output of I2S TX TDM channel 11. 0: Disable, just output 0 in this channel. 11 1 read-write - I2S_TX_TDM_CHAN12_EN + TX_TDM_CHAN12_EN 1: Enable the valid data output of I2S TX TDM channel 12. 0: Disable, just output 0 in this channel. 12 1 read-write - I2S_TX_TDM_CHAN13_EN + TX_TDM_CHAN13_EN 1: Enable the valid data output of I2S TX TDM channel 13. 0: Disable, just output 0 in this channel. 13 1 read-write - I2S_TX_TDM_CHAN14_EN + TX_TDM_CHAN14_EN 1: Enable the valid data output of I2S TX TDM channel 14. 0: Disable, just output 0 in this channel. 14 1 read-write - I2S_TX_TDM_CHAN15_EN + TX_TDM_CHAN15_EN 1: Enable the valid data output of I2S TX TDM channel 15. 0: Disable, just output 0 in this channel. 15 1 read-write - I2S_TX_TDM_TOT_CHAN_NUM + TX_TDM_TOT_CHAN_NUM The total channel number of I2S TX TDM mode. 16 4 read-write - I2S_TX_TDM_SKIP_MSK_EN + TX_TDM_SKIP_MSK_EN When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1) channels, and only the data of the enabled channels is sent, then this bit should be set. Clear it when all the data stored in DMA TX buffer is for enabled channels. 20 1 @@ -16145,41 +16145,41 @@ level. - I2S_RX_TIMING + RX_TIMING I2S RX timing control register 0x58 0x20 - I2S_RX_SD_IN_DM + RX_SD_IN_DM The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. 0 2 read-write - I2S_RX_WS_OUT_DM + RX_WS_OUT_DM The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. 16 2 read-write - I2S_RX_BCK_OUT_DM + RX_BCK_OUT_DM The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. 20 2 read-write - I2S_RX_WS_IN_DM + RX_WS_IN_DM The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. 24 2 read-write - I2S_RX_BCK_IN_DM + RX_BCK_IN_DM The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. 28 2 @@ -16188,48 +16188,48 @@ level. - I2S_TX_TIMING + TX_TIMING I2S TX timing control register 0x5C 0x20 - I2S_TX_SD_OUT_DM + TX_SD_OUT_DM The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. 0 2 read-write - I2S_TX_SD1_OUT_DM + TX_SD1_OUT_DM The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. 4 2 read-write - I2S_TX_WS_OUT_DM + TX_WS_OUT_DM The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. 16 2 read-write - I2S_TX_BCK_OUT_DM + TX_BCK_OUT_DM The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. 20 2 read-write - I2S_TX_WS_IN_DM + TX_WS_IN_DM The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. 24 2 read-write - I2S_TX_BCK_IN_DM + TX_BCK_IN_DM The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. 28 2 @@ -16238,28 +16238,28 @@ level. - I2S_LC_HUNG_CONF + LC_HUNG_CONF I2S HUNG configure register. 0x60 0x20 0x00000810 - I2S_LC_FIFO_TIMEOUT + LC_FIFO_TIMEOUT the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered when fifo hung counter is equal to this value 0 8 read-write - I2S_LC_FIFO_TIMEOUT_SHIFT + LC_FIFO_TIMEOUT_SHIFT The bits are used to scale tick counter threshold. The tick counter is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift 8 3 read-write - I2S_LC_FIFO_TIMEOUT_ENA + LC_FIFO_TIMEOUT_ENA The enable bit for FIFO timeout 11 1 @@ -16268,14 +16268,14 @@ level. - I2S_RXEOF_NUM + RXEOF_NUM I2S RX data number control register. 0x64 0x20 0x00000040 - I2S_RX_EOF_NUM + RX_EOF_NUM The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0] + 1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel. 0 12 @@ -16284,13 +16284,13 @@ level. - I2S_CONF_SIGLE_DATA + CONF_SIGLE_DATA I2S signal data register 0x68 0x20 - I2S_SINGLE_DATA + SINGLE_DATA The configured constant channel data to be sent out. 0 32 @@ -16299,14 +16299,14 @@ level. - I2S_STATE + STATE I2S TX status register 0x6C 0x20 0x00000001 - I2S_TX_IDLE + TX_IDLE 1: i2s_tx is idle state. 0: i2s_tx is working. 0 1 @@ -16315,14 +16315,14 @@ level. - I2S_DATE + DATE Version control register 0x80 0x20 0x02009070 - I2S_DATE + DATE I2S version control register 0 28 @@ -21916,7 +21916,7 @@ The least significant eight bits represent the fractional part. 0x00003C10 - FILTER_THRES_U + FILTER_THRES This sets the maximum threshold, in APB_CLK cycles, for the filter. Any pulses with width less than this will be ignored when the filter is enabled. @@ -21925,49 +21925,49 @@ Any pulses with width less than this will be ignored when the filter is enabled. read-write - FILTER_EN_U + FILTER_EN This is the enable bit for unit %s's input filter. 10 1 read-write - THR_ZERO_EN_U + THR_ZERO_EN This is the enable bit for unit %s's zero comparator. 11 1 read-write - THR_H_LIM_EN_U + THR_H_LIM_EN This is the enable bit for unit %s's thr_h_lim comparator. 12 1 read-write - THR_L_LIM_EN_U + THR_L_LIM_EN This is the enable bit for unit %s's thr_l_lim comparator. 13 1 read-write - THR_THRES0_EN_U + THR_THRES0_EN This is the enable bit for unit %s's thres0 comparator. 14 1 read-write - THR_THRES1_EN_U + THR_THRES1_EN This is the enable bit for unit %s's thres1 comparator. 15 1 read-write - CH0_NEG_MODE_U + CH0_NEG_MODE This register sets the behavior when the signal input of channel 0 detects a negative edge. 1: Increase the counter;2: Decrease the counter;0, 3: No effect on counter @@ -21976,7 +21976,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. read-write - CH0_POS_MODE_U + CH0_POS_MODE This register sets the behavior when the signal input of channel 0 detects a positive edge. 1: Increase the counter;2: Decrease the counter;0, 3: No effect on counter @@ -21985,7 +21985,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. read-write - CH0_HCTRL_MODE_U + CH0_HCTRL_MODE This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is high. 0: No modification;1: Invert behavior (increase -> decrease, decrease -> increase);2, 3: Inhibit counter modification @@ -21994,7 +21994,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. read-write - CH0_LCTRL_MODE_U + CH0_LCTRL_MODE This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is low. 0: No modification;1: Invert behavior (increase -> decrease, decrease -> increase);2, 3: Inhibit counter modification @@ -22003,7 +22003,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. read-write - CH1_NEG_MODE_U + CH1_NEG_MODE This register sets the behavior when the signal input of channel 1 detects a negative edge. 1: Increment the counter;2: Decrement the counter;0, 3: No effect on counter @@ -22012,7 +22012,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. read-write - CH1_POS_MODE_U + CH1_POS_MODE This register sets the behavior when the signal input of channel 1 detects a positive edge. 1: Increment the counter;2: Decrement the counter;0, 3: No effect on counter @@ -22021,7 +22021,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. read-write - CH1_HCTRL_MODE_U + CH1_HCTRL_MODE This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is high. 0: No modification;1: Invert behavior (increase -> decrease, decrease -> increase);2, 3: Inhibit counter modification @@ -22030,7 +22030,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. read-write - CH1_LCTRL_MODE_U + CH1_LCTRL_MODE This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is low. 0: No modification;1: Invert behavior (increase -> decrease, decrease -> increase);2, 3: Inhibit counter modification @@ -22049,14 +22049,14 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0x20 - CNT_THRES0_U + CNT_THRES0 This register is used to configure the thres0 value for unit %s. 0 16 read-write - CNT_THRES1_U + CNT_THRES1 This register is used to configure the thres1 value for unit %s. 16 16 @@ -22073,14 +22073,14 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0x20 - CNT_H_LIM_U + CNT_H_LIM This register is used to configure the thr_h_lim value for unit %s. 0 16 read-write - CNT_L_LIM_U + CNT_L_LIM This register is used to configure the thr_l_lim value for unit %s. 16 16 @@ -22097,7 +22097,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0x20 - PULSE_CNT_U + CNT This register stores the current pulse count value for unit %s. 0 16 @@ -22112,28 +22112,28 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0x20 - CNT_THR_EVENT_U0_INT_RAW + CNT_THR_EVENT_U0 The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. 0 1 read-only - CNT_THR_EVENT_U1_INT_RAW + CNT_THR_EVENT_U1 The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. 1 1 read-only - CNT_THR_EVENT_U2_INT_RAW + CNT_THR_EVENT_U2 The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. 2 1 read-only - CNT_THR_EVENT_U3_INT_RAW + CNT_THR_EVENT_U3 The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. 3 1 @@ -22148,28 +22148,28 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0x20 - CNT_THR_EVENT_U0_INT_ST + CNT_THR_EVENT_U0 The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. 0 1 read-only - CNT_THR_EVENT_U1_INT_ST + CNT_THR_EVENT_U1 The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. 1 1 read-only - CNT_THR_EVENT_U2_INT_ST + CNT_THR_EVENT_U2 The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. 2 1 read-only - CNT_THR_EVENT_U3_INT_ST + CNT_THR_EVENT_U3 The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. 3 1 @@ -22184,28 +22184,28 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0x20 - CNT_THR_EVENT_U0_INT_ENA + CNT_THR_EVENT_U0 The interrupt enable bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. 0 1 read-write - CNT_THR_EVENT_U1_INT_ENA + CNT_THR_EVENT_U1 The interrupt enable bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. 1 1 read-write - CNT_THR_EVENT_U2_INT_ENA + CNT_THR_EVENT_U2 The interrupt enable bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. 2 1 read-write - CNT_THR_EVENT_U3_INT_ENA + CNT_THR_EVENT_U3 The interrupt enable bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. 3 1 @@ -22220,28 +22220,28 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0x20 - CNT_THR_EVENT_U0_INT_CLR + CNT_THR_EVENT_U0 Set this bit to clear the PCNT_CNT_THR_EVENT_U0_INT interrupt. 0 1 write-only - CNT_THR_EVENT_U1_INT_CLR + CNT_THR_EVENT_U1 Set this bit to clear the PCNT_CNT_THR_EVENT_U1_INT interrupt. 1 1 write-only - CNT_THR_EVENT_U2_INT_CLR + CNT_THR_EVENT_U2 Set this bit to clear the PCNT_CNT_THR_EVENT_U2_INT interrupt. 2 1 write-only - CNT_THR_EVENT_U3_INT_CLR + CNT_THR_EVENT_U3 Set this bit to clear the PCNT_CNT_THR_EVENT_U3_INT interrupt. 3 1 @@ -22258,42 +22258,42 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0x20 - CNT_THR_ZERO_MODE_U + ZERO_MODE The pulse counter status of PCNT_U%s corresponding to 0. 0: pulse counter decreases from positive to 0. 1: pulse counter increases from negative to 0. 2: pulse counter is negative. 3: pulse counter is positive. 0 2 read-only - CNT_THR_THRES1_LAT_U + THRES1 The latched value of thres1 event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thres1 and thres1 event is valid. 0: others 2 1 read-only - CNT_THR_THRES0_LAT_U + THRES0 The latched value of thres0 event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thres0 and thres0 event is valid. 0: others 3 1 read-only - CNT_THR_L_LIM_LAT_U + L_LIM The latched value of low limit event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thr_l_lim and low limit event is valid. 0: others 4 1 read-only - CNT_THR_H_LIM_LAT_U + H_LIM The latched value of high limit event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thr_h_lim and high limit event is valid. 0: others 5 1 read-only - CNT_THR_ZERO_LAT_U + ZERO The latched value of zero threshold event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to 0 and zero threshold event is valid. 0: others 6 1 @@ -22309,7 +22309,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0x00000001 - PULSE_CNT_RST_U0 + CNT_RST_U0 Set this bit to clear unit 0's counter. 0 1 @@ -22323,7 +22323,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. read-write - PULSE_CNT_RST_U1 + CNT_RST_U1 Set this bit to clear unit 1's counter. 2 1 @@ -22337,7 +22337,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. read-write - PULSE_CNT_RST_U2 + CNT_RST_U2 Set this bit to clear unit 2's counter. 4 1 @@ -22351,7 +22351,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. read-write - PULSE_CNT_RST_U3 + CNT_RST_U3 Set this bit to clear unit 3's counter. 6 1 @@ -22787,7 +22787,14 @@ Any pulses with width less than this will be ignored when the filter is enabled. TIMER0_PHASE phase for timer reload on sync event 4 - 17 + 16 + read-write + + + TIMER0_PHASE_DIRECTION + Configure the PWM timer0's direction when timer0 mode is up-down mode. 0: increase; 1: decrease. + 20 + 1 read-write @@ -22897,7 +22904,14 @@ Any pulses with width less than this will be ignored when the filter is enabled. TIMER1_PHASE phase for timer reload on sync event 4 - 17 + 16 + read-write + + + TIMER1_PHASE_DIRECTION + Configure the PWM timer1's direction when timer1 mode is up-down mode. 0: increase; 1: decrease. + 20 + 1 read-write @@ -23007,7 +23021,14 @@ Any pulses with width less than this will be ignored when the filter is enabled. TIMER2_PHASE phase for timer reload on sync event 4 - 17 + 16 + read-write + + + TIMER2_PHASE_DIRECTION + Configure the PWM timer2's direction when timer2 mode is up-down mode. 0: increase; 1: decrease. + 20 + 1 read-write @@ -35994,28 +36015,28 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0x20 - SAR_FORCE_XPD_AMP + FORCE_XPD_AMP no public 24 2 read-write - SAR_AMP_RST_FB_FORCE + AMP_RST_FB_FORCE no public 26 2 read-write - SAR_AMP_SHORT_REF_FORCE + AMP_SHORT_REF_FORCE no public 28 2 read-write - SAR_AMP_SHORT_REF_GND_FORCE + AMP_SHORT_REF_GND_FORCE no public 30 2 @@ -36030,42 +36051,42 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0x20 - SAR_MEAS1_DATA_SAR + MEAS1_DATA_SAR SAR ADC1 data 0 16 read-only - SAR_MEAS1_DONE_SAR + MEAS1_DONE_SAR SAR ADC1 conversion done indication 16 1 read-only - SAR_MEAS1_START_SAR + MEAS1_START_SAR SAR ADC1 controller (in RTC) starts conversion 17 1 read-write - SAR_MEAS1_START_FORCE + MEAS1_START_FORCE 1: SAR ADC1 controller (in RTC) is started by SW 18 1 read-write - SAR_SAR1_EN_PAD + SAR1_EN_PAD SAR ADC1 pad enable bitmap 19 12 read-write - SAR_SAR1_EN_PAD_FORCE + SAR1_EN_PAD_FORCE 1: SAR ADC1 pad enable bitmap is controlled by SW 31 1 @@ -36080,7 +36101,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0x20 - SAR_SAR1_DIG_FORCE + SAR1_DIG_FORCE 1: SAR ADC1 controlled by DIG ADC1 CTRL 31 1 @@ -36096,7 +36117,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0xFFFFFFFF - SAR_SAR1_ATTEN + SAR1_ATTEN 2-bit attenuation for each pad 0 32 @@ -36200,49 +36221,49 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0x007338F3 - SAR_SAR1_DAC_XPD_FSM + SAR1_DAC_XPD_FSM no public 0 4 read-write - SAR_XPD_SAR_AMP_FSM + XPD_SAR_AMP_FSM no public 4 4 read-write - SAR_AMP_RST_FB_FSM + AMP_RST_FB_FSM no public 8 4 read-write - SAR_AMP_SHORT_REF_FSM + AMP_SHORT_REF_FSM no public 12 4 read-write - SAR_AMP_SHORT_REF_GND_FSM + AMP_SHORT_REF_GND_FSM no public 16 4 read-write - SAR_XPD_SAR_FSM + XPD_SAR_FSM no public 20 4 read-write - SAR_RSTB_FSM + RSTB_FSM no public 24 4 @@ -36388,42 +36409,42 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0x20 - SAR_MEAS2_DATA_SAR + MEAS2_DATA_SAR SAR ADC2 data 0 16 read-only - SAR_MEAS2_DONE_SAR + MEAS2_DONE_SAR SAR ADC2 conversion done indication 16 1 read-only - SAR_MEAS2_START_SAR + MEAS2_START_SAR SAR ADC2 controller (in RTC) starts conversion 17 1 read-write - SAR_MEAS2_START_FORCE + MEAS2_START_FORCE 1: SAR ADC2 controller (in RTC) is started by SW 18 1 read-write - SAR_SAR2_EN_PAD + SAR2_EN_PAD SAR ADC2 pad enable bitmap 19 12 read-write - SAR_SAR2_EN_PAD_FORCE + SAR2_EN_PAD_FORCE 1: SAR ADC2 pad enable bitmap is controlled by SW 31 1 @@ -36438,14 +36459,14 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0x20 - SAR_SAR2_PWDET_CCT + SAR2_PWDET_CCT SAR2_PWDET_CCT 28 3 read-write - SAR_SAR2_RTC_FORCE + SAR2_RTC_FORCE in sleep, force to use rtc to control ADC 31 1 @@ -36461,7 +36482,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0xFFFFFFFF - SAR_SAR2_ATTEN + SAR2_ATTEN 2-bit attenuation for each pad 0 32 @@ -36476,14 +36497,14 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0x20 - SAR_FORCE_XPD_SAR + FORCE_XPD_SAR force power on/off saradc 29 2 read-write - SAR_SARCLK_EN + SARCLK_EN no public 31 1 @@ -37879,28 +37900,28 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0xA0000000 - SAR_XPD_HALL + XPD_HALL Power on hall sensor and connect to VP and VN 28 1 read-write - SAR_XPD_HALL_FORCE + XPD_HALL_FORCE 1: XPD HALL is controlled by SW. 0: XPD HALL is controlled by FSM in ULP-coprocessor 29 1 read-write - SAR_HALL_PHASE + HALL_PHASE Reverse phase of hall sensor 30 1 read-write - SAR_HALL_PHASE_FORCE + HALL_PHASE_FORCE 1: HALL PHASE is controlled by SW 0: HALL PHASE is controlled by FSM in ULP-coprocessor 31 1 @@ -37930,28 +37951,28 @@ Any pulses with width less than this will be ignored when the filter is enabled. 0x20 - SAR_RTC_I2C_CLK_EN + RTC_I2C_CLK_EN enable rtc i2c clock 27 1 read-write - SAR_TSENS_CLK_EN + TSENS_CLK_EN enable tsens clock 29 1 read-write - SAR_SARADC_CLK_EN + SARADC_CLK_EN enbale saradc clock 30 1 read-write - SAR_IOMUX_CLK_EN + IOMUX_CLK_EN enable io_mux clock 31 1 @@ -44861,7 +44882,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. - CLOCK_GATE_REG + CLOCK_GATE Sensitive module clock gate configuration register. 0x308 0x20 @@ -50751,7 +50772,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. read-write - CAN_CLK_EN + TWAI_CLK_EN Set 1 to enable CAN clock 19 1 @@ -51069,7 +51090,7 @@ Any pulses with width less than this will be ignored when the filter is enabled. read-write - CAN_RST + TWAI_RST Set 1 to let CAN reset 19 1 @@ -53826,7 +53847,7 @@ protection is enabled. In reset mode, it is acceptance code register 0 with R/W Permission. In operation mode, it stores the 0th byte information of the data to be transmitted under operating mode. 0 8 - write-only + read-write @@ -53841,7 +53862,7 @@ protection is enabled. In reset mode, it is acceptance code register 1 with R/W Permission. In operation mode, it stores the 1st byte information of the data to be transmitted under operating mode. 0 8 - write-only + read-write @@ -53856,7 +53877,7 @@ protection is enabled. In reset mode, it is acceptance code register 2 with R/W Permission. In operation mode, it stores the 2nd byte information of the data to be transmitted under operating mode. 0 8 - write-only + read-write @@ -53871,7 +53892,7 @@ protection is enabled. In reset mode, it is acceptance code register 3 with R/W Permission. In operation mode, it stores the 3rd byte information of the data to be transmitted under operating mode. 0 8 - write-only + read-write @@ -53886,7 +53907,7 @@ protection is enabled. In reset mode, it is acceptance mask register 0 with R/W Permission. In operation mode, it stores the 4th byte information of the data to be transmitted under operating mode. 0 8 - write-only + read-write @@ -53901,7 +53922,7 @@ protection is enabled. In reset mode, it is acceptance mask register 1 with R/W Permission. In operation mode, it stores the 5th byte information of the data to be transmitted under operating mode. 0 8 - write-only + read-write @@ -53916,7 +53937,7 @@ protection is enabled. In reset mode, it is acceptance mask register 2 with R/W Permission. In operation mode, it stores the 6th byte information of the data to be transmitted under operating mode. 0 8 - write-only + read-write @@ -53931,7 +53952,7 @@ protection is enabled. In reset mode, it is acceptance mask register 3 with R/W Permission. In operation mode, it stores the 7th byte information of the data to be transmitted under operating mode. 0 8 - write-only + read-write @@ -53946,7 +53967,7 @@ protection is enabled. Stored the 8th byte information of the data to be transmitted under operating mode. 0 8 - write-only + read-write @@ -53961,7 +53982,7 @@ protection is enabled. Stored the 9th byte information of the data to be transmitted under operating mode. 0 8 - write-only + read-write @@ -53976,7 +53997,7 @@ protection is enabled. Stored the 10th byte information of the data to be transmitted under operating mode. 0 8 - write-only + read-write @@ -53991,7 +54012,7 @@ protection is enabled. Stored the 11th byte information of the data to be transmitted under operating mode. 0 8 - write-only + read-write @@ -54006,7 +54027,7 @@ protection is enabled. Stored the 12th byte information of the data to be transmitted under operating mode. 0 8 - write-only + read-write