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poxim-interp.cpp
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#include <fstream>
#include <iostream>
#include <queue>
#include <string>
#include <unordered_map>
#include <vector>
#include <math.h>
#include <stdint.h>
#include <stdio.h>
#include <string.h>
#include <assert.h>
// #define _DEBUG_POXIM
#define _DEBUG_OUT
#ifndef _DEBUG_POXIM
#define printf(x, ...)
#define puts(x)
#endif
#define UNUSED 0x00
#define GLOBAL
#define MEM_SIZE 1024
#if defined(__WIN32)
#pragma warning(disable : 4996)
#endif
int32_t INSTRUCTION_COUNTER = 0;
typedef volatile uint32_t vu32;
typedef float f32;
typedef uint64_t u64;
typedef uint32_t u32;
typedef uint16_t u16;
typedef uint8_t u8;
typedef int64_t i64;
typedef int32_t i32;
typedef int16_t i16;
typedef int8_t i8;
/*===========================Structures=======================*/
GLOBAL enum OP : u8 {
//:> Format Type 'U'
mov = 0b000000,
movs = 0b000001,
add = 0b000010,
sub = 0b000011,
// ==================================
// Becaful Operation with the same code
mul = 0b000100, // FREE bits op.L: 0b000
muls = 0b000100, // FREE bits op.L: 0b010
DIV = 0b000100, // FREE bits op.L: 0b100
divs = 0b000100, // FREE bits op.L: 0b110
sll = 0b000100, // FREE bits op.L: 0b001
sla = 0b000100, // FREE bits op.L: 0b011
srl = 0b000100, // FREE bits op.L: 0b101
sra = 0b000100, // FREE bits op.L: 0b111
// ==================================
CMP = 0b000101,
AND = 0b000110,
OR = 0b000111,
NOT = 0b001000,
XOR = 0b001001,
/*push pop*/
push = 0b001010,
pop = 0b001011,
//:> Format Type 'F'
addi = 0b010010,
subi = 0b010011,
muli = 0b010100,
divi = 0b010101,
remi = 0b010110,
cmpi = 0b010111,
/*Memory*/
l8 = 0b011000,
l16 = 0b011001,
l32 = 0b011010,
s8 = 0b011011,
s16 = 0b011100,
s32 = 0b011101,
/*call return*/
call = 0b011110,
ret = 0b011111,
//:> Format Type 'S'
bae = 0b101010,
bat = 0b101011,
bbe = 0b101100,
bbt = 0b101101,
beq = 0b101110,
bge = 0b101111,
bgt = 0b110000,
biv = 0b110001,
ble = 0b110010,
blt = 0b110011,
bne = 0b110100,
bni = 0b110101,
bnz = 0b110110,
bun = 0b110111,
bzd = 0b111000,
INT = 0b111111,
calli = 0b111001,
reti = 0b100000,
cbr = 0b100001, // equals last bit (0th bit) == 0
sbr = 0b100001 // equals last bit (0th bit) == 1
};
GLOBAL struct Operands {
u32 Z, X, Y, I, L;
};
GLOBAL struct Expression {
char format;
u32 expression; // Whole expresion <OP> <Operands>;
OP operation; // Just the operand <OP>
Operands operands; // Cluster of all operands in the expression <Operands>;
Expression(u32 inst) {
this->expression = inst;
this->operation =
(OP)((this->expression & 0b11111100000000000000000000000000) >> 26);
if ((expression >> 31) == 0b1) // If the first bit is 1.
{
this->format = 'S';
} else if ((expression >> 30) ==
0b1) // if the first is a 0, and the second bit is a 1
{
this->format = 'F';
} else {
this->format = 'U';
}
// Catching Outliers
if (operation == 0b100001) {
this->format = 'F';
}
this->operands = _CreateOperands();
}
private:
Operands _CreateOperands() {
Operands op{};
switch (this->format) {
case 'U': {
op.Z =
(i32)((this->expression & 0b00000011111000000000000000000000) >> 21);
op.X =
(i32)((this->expression & 0b00000000000111110000000000000000) >> 16);
op.Y =
(i32)((this->expression & 0b00000000000000001111100000000000) >> 11);
op.L =
(i32)((this->expression & 0b00000000000000000000011111111111) >> 0);
op.I = UNUSED;
break;
}
case 'F': {
op.Z =
(i32)((this->expression & 0b00000011111000000000000000000000) >> 21);
op.X =
(i32)((this->expression & 0b00000000000111110000000000000000) >> 16);
op.Y = UNUSED;
op.L = UNUSED;
op.I =
(i32)((this->expression & 0b00000000000000001111111111111111) >> 0);
break;
}
case 'S': {
op.Z = UNUSED;
op.X = UNUSED;
op.Y = UNUSED;
op.L = UNUSED;
op.I =
(i32)((this->expression & 0b00000011111111111111111111111111) >> 0);
break;
}
default:
puts("[[WARNING]] Invalid Expression Format");
break;
}
return op;
}
};
/*=============================================================*/
/*===========================Funcitons
* Start==============================================================================================*/
/*************************** Bit Manipulation Functions
* ***********************************************************************************
* These functions are zero indexed, meaning they consider 'end' as the last
* bit, the bit in position '0' [right-to-left] and 'start' as the first bit,
* ex: unsinged int (32bits) has the start bit a position '31' ex: 0b011111, the
* 'end' is the position '0' bit, which is 1 in this case, again counting from
* right-to-left in increasing order. if you want the 'start' to start at the
* first bit , then you wanna choose 'start' := 5, because the bit you wanna set
* is the 6th bit [right-to-left index] (the bit in position '5')
*/
void SetBit(u32 &number, u8 nth_bit, bool choice);
void SetBit(u64 &number, u8 nth_bit, bool choice);
u8 GetBit(const u32 &number, int nth_bit);
u8 GetBit(u64 &number, int nth_bit);
u32 GetBits(const u32 &number, u32 start, u32 end);
u32 GetBits(const u64 &number, u32 start, u32 end);
void FillBits(u32 &number, u8 start, u8 end, bool bit_choice);
void FillBits(u64 &number, u8 start, u8 end, bool bit_choice);
void ExtendBit(u32 &num, u8 bit_place);
u64 ConcatBits(const u32 &start, const u32 &end);
u32 ConcatBits(u8 first, u8 second, u8 third, u8 fourth);
u16 ConcatBits(u8 start, u8 end);
u32 SwitchEndianess(const u32 &number);
/****************************************************************************************************************************************/
void ExecuteCode(u32 instructions[]);
void ProcessExpression(Expression single_instruction);
void StoreHexInstructions(const char *filename, u32 instructions[], size_t max_instructions);
void StoreBinaryInstructions(const char *filename, u32 instructions[], size_t max_instructions);
void Branch(u32 imediate, bool is_signed);
u8 &AccessMemory(u32 index);
void PrintTerminal();
/****************************************************************************************************************************************/
bool isDevice(u32 index);
u32 &AccessDevice32(u32 index, OP op);
u16 &AccessDevice16(u32 index, OP op);
u8 &AccessDevice8(u32 index, OP op);
void Interrupt(const char type[26], Operands op = {});
void ISR();
void DefaultRoutines();
/****************************************************************************************************************************************/
void RegStr(char register_name[5], u8 id);
void ReadWriteStr(char result[256], const char *instruction, u8 bits_count,
Operands op);
void BranchStr(char dest[256], const char *instruction_name, u32 imediate);
void PushPopStr(char dest[500], const char *instruction_name, Operands op);
char *UpperStr(char *);
u32 HexToBin(const char *hex);
std::string ToHex(u32 hex);
void PrintOperation(OP op, Operands operand);
namespace inst {
void SetZN(bool value);
void SetZD(bool value);
void SetSN(bool value);
void SetOV(bool value);
void SetIV(bool value);
void SetCY(bool value);
void SetIE(bool value);
u8 GetZN();
u8 GetZD();
u8 GetSN();
u8 GetOV();
u8 GetIV();
u8 GetCY();
u8 GetIE();
//:>>/*===========================Format 'U' =======================*/
void mov(const Operands op);
void movs(const Operands op);
void add(const Operands op);
void sub(const Operands op);
void mul(const Operands op);
void muls(const Operands op);
void div(const Operands op);
void divs(const Operands op);
void sll(const Operands op);
void sla(const Operands op);
void srl(const Operands op);
void sra(const Operands op);
void CMP(const Operands op);
/*==========================BIT WISE OPERATIONS========================*/
void AND(const Operands op);
void OR(const Operands op);
void NOT(const Operands op);
void XOR(const Operands op);
/*====================================================================*/
void push(const Operands op);
void pop(const Operands op);
//:>>/*===========================Format 'F' =======================*/
void addi(Operands op);
void subi(Operands op);
void muli(Operands op);
void divi(Operands op);
void remi(Operands op);
void CMPI(Operands op);
void l8(Operands op);
void l16(Operands op);
void l32(Operands op);
void s8(Operands op);
void s16(Operands op);
void s32(Operands op);
void call(Operands op);
void ret(Operands op);
//:>>/*===========================Format 'S' =======================*/
void bae(Operands op);
void bat(Operands op);
void bbe(Operands op);
void bbt(Operands op);
void beq(Operands op);
void bge(Operands op);
void bgt(Operands op);
void biv(Operands op);
void ble(Operands op);
void blt(Operands op);
void bne(Operands op);
void bni(Operands op);
void bnz(Operands op);
void bun(Operands op);
void bzd(Operands op);
void INT(Operands op);
void calli(Operands op);
void reti(Operands op);
void sbr(Operands op);
void cbr(Operands op);
} // namespace inst
/*===========================Funcitons
* End==============================================================================================*/
/*===========================GLOBAL VARIABLES=======================*/
GLOBAL bool running = true;
GLOBAL i8 int_flag = -1;
/*===========================Extern Devices=======================*/
class Terminal {
std::queue<u8> storage{};
u8 current_index = 0;
bool used = false;
public:
u32 TERMINAL_ADRESS = (u32)0x88888888;
union {
u32 IO32 = 0;
u16 IO16[2];
u8 IO8[4];
};
void AddIn() {
this->used = true;
storage.push(IO8[3]);
}
bool HasNext() {
return (storage.size() > 0);
if (current_index > (storage.size() - 1)) {
return false;
}
if (current_index < 0) {
return false;
} else {
return true;
}
}
char Next() {
// char next_char = storage[this->current_index];
char next_char = storage.front();
storage.pop();
current_index++;
return next_char;
}
bool Used() { return this->used; }
};
struct WatchDog {
const u32 WATCHDOG_ADRESS = (u32)0x80808080;
union {
u32 WD32 = 0x0;
u16 WD16[2];
u8 WD8[4];
};
};
struct FloatDevice {
// Floating Operations : u5 actually
enum class FOP : u8 {
nop = 0b00000, // NO operation
add = 0b00001, // Z = X + Y
sub = 0b00010, // Z = X - Y
mul = 0b00011, // Z = X * Y
div = 0b00100, // Z = X / Y
atrXZ = 0b00101, // X = Z
atrYZ = 0b00110, // Y = Z
ceil = 0b00111, // Teto(Z)
floor = 0b01000, // Piso(Z)
round = 0b01001, // Round(|Z|)
};
bool should_operate = false;
i32 wait_cycles = -1;
bool Y_overwritten = false;
bool X_overwritten = false;
private:
bool Xisfloat = false;
bool Yisfloat = false;
// bool Zisfloat = false;
public:
union {
u32 FPU32[4];
u16 FPU16[4 * 2];
u8 FPU8[4 * 4];
/*0x80808880, 0x80808884, 0x80808888*/ // 0x80808880
// U is for holding OP and RO
// Z is for the Result
struct {
u32 X, Y;
f32 Z;
u32 U;
};
};
u32 code = 0x01EEE754;
u8 OP;
u8 ST;
void ClearOP() {
this->FPU8[0x0000000f] = 0;
SetRO(ST);
}
void SetRO(u8 bit) {
ST = bit;
SetBit((u32 &)this->FPU8[0x0000000f], 5, bit);
// SetBit(this->U, 5, bit);
}
void MakeInteger(std::string operand) {
if (operand == "X") {
this->Xisfloat = false;
return;
} else if (operand == "Y") {
this->Yisfloat = false;
return;
}
}
u32 CicleTime() {
FOP operation = (FOP)GetBits((u32)this->FPU8[0x0000000f], 7, 0);
// FOP operation = this->previous_operator;
switch (operation) {
case FloatDevice::FOP::nop:
case FloatDevice::FOP::atrXZ:
case FloatDevice::FOP::atrYZ:
case FloatDevice::FOP::ceil:
case FloatDevice::FOP::floor:
case FloatDevice::FOP::round: {
return 1;
}
case FloatDevice::FOP::add:
case FloatDevice::FOP::sub:
case FloatDevice::FOP::mul:
case FloatDevice::FOP::div: {
break;
}
default: {
return 1;
}
}
i32 X_time, tempX;
i32 Y_time, tempY;
tempX = SwitchEndianess(this->X);
tempY = SwitchEndianess(this->Y);
if (Xisfloat) {
X_time = GetBits(*(u32 *)(&this->X), 30, 23);
} else {
// Do I need to Switch Endianess here too?
f32 X_as_float = (f32)tempX;
X_time = GetBits(*(u32 *)&X_as_float, 30, 23);
}
if (Yisfloat) {
Y_time = GetBits(*(u32 *)(&this->Y), 30, 23);
} else {
f32 Y_as_float = (f32)tempY;
Y_time = GetBits(*(u32 *)&Y_as_float, 30, 23);
}
X_time = X_time - 127;
Y_time = Y_time - 127;
u32 base_time = abs(X_time - Y_time);
return (base_time + 1);
}
bool ReadyToOperate() {
if (should_operate == true) {
if (0 == wait_cycles) {
return true;
} else if (wait_cycles > 0) {
wait_cycles--;
return false;
} else {
wait_cycles = -1;
return false;
}
} else {
wait_cycles = -1;
return false;
}
}
void Operate() {
SetRO(0);
FOP operation = (FOP)GetBits((u32)this->FPU8[0x0000000f], 4, 0);
f32 X, Y, Z, result;
u32 tempX = SwitchEndianess(this->X);
u32 tempY = SwitchEndianess(this->Y);
(void)result;
Z = this->Z;
if (Xisfloat)
X = *(f32 *)(&(this->X));
else
X = (f32)tempX; // X = (f32)tempY; it was like this before but might be wrong
if (Yisfloat)
Y = *(f32 *)(&(this->Y));
else
Y = (f32)tempY;
if (0 == wait_cycles) {
switch (operation) {
case FloatDevice::FOP::nop: {
break;
}
case FloatDevice::FOP::add: {
this->Z = X + Y;
Interrupt("op_var");
break;
}
case FloatDevice::FOP::sub: {
this->Z = X - Y;
Interrupt("op_var");
break;
}
case FloatDevice::FOP::mul: {
this->Z = X * Y;
Interrupt("op_var");
break;
}
case FloatDevice::FOP::div: {
if (Y == 0) {
SetRO(1);
void ClearOP();
int_flag = 2;
Interrupt("op_error");
break;
} else {
this->Z = X / Y;
Interrupt("op_var");
break;
}
}
case FloatDevice::FOP::atrXZ: {
this->X = *(u32 *)&Z;
Xisfloat = true;
Interrupt("op_const");
break;
}
case FloatDevice::FOP::atrYZ: {
this->Y = *(u32 *)&Z;
Yisfloat = true;
Interrupt("op_const");
break;
}
case FloatDevice::FOP::ceil: {
this->Z = (u32)ceil(Z);
Interrupt("op_const");
break;
}
case FloatDevice::FOP::floor: {
this->Z = (u32)floor(Z);
Interrupt("op_const");
break;
}
case FloatDevice::FOP::round: {
this->Z = (u32)round(Z);
Interrupt("op_const");
break;
}
default: {
SetRO(1);
int_flag = 2;
Interrupt("op_error");
break;
}
}
}
this->should_operate = false;
wait_cycles = -1;
}
};
GLOBAL WatchDog W{};
GLOBAL Terminal T{};
GLOBAL FloatDevice F{};
GLOBAL u32 DEFAULT_DEVICE32 = (u32)0x0;
GLOBAL u16 DEFAULT_DEVICE16 = (u32)0x0;
GLOBAL u8 DEFAULT_DEVICE8 = (u32)0x0;
/*==========================Registers & RAM========================*/
typedef struct {
union {
GLOBAL u32 instructions[32 * MEM_SIZE / 4];
GLOBAL u8 RAM[32 * MEM_SIZE];
GLOBAL u16 RAM16[32 * MEM_SIZE / 2];
GLOBAL u32 RAM32[32 * MEM_SIZE / 4];
};
} Memory;
GLOBAL Memory MEM{};
GLOBAL u32 registers[32] = {};
// R0 must always be zero (0);
u32 &R0 = registers[0];
// SR => Status Register
u32 &SR = registers[31];
// SP => Stack Pointer
u32 &SP = registers[30];
// PC => Aponta para as instru��es < controla fluxo
u32 &PC = registers[29];
// Pseudo 'PC' to print correctly
u32 PPC = 0x0;
u32 SSP = 0x0;
// IR => Intruction Register < Armazena a intru��o a ser carregada
u32 &IR = registers[28];
u32 &IPC = registers[27];
u32 &CR = registers[26];
/*========================================================================*/
/*===========================IO GLOBALS=======================*/
GLOBAL std::ofstream assembly_out;
GLOBAL std::ofstream terminal_out;
/*_______________________________________________________________________________________________________________________*/
/*===========================Start of
* Program============================================================================*/
// '--bin' flag reads as binary
bool as_bin = false;
const char *as_bin_flag = "--bin";
int main(int argc, char **argv) {
if (argc > 1 && strcmp(argv[1], as_bin_flag) == 0) {
as_bin = true;
// Shift the arguments to skip the '--bin' flag
for (int i = 1; i < argc - 1; i++) {
argv[i] = argv[i + 1];
}
argv[argc - 1] = NULL;
argc--;
}
const char *filename_in = argv[1];
const char *filename_out = argv[2];
if (filename_in == nullptr) {
filename_in = ".in";
filename_out = ".out";
}
if(as_bin){
StoreBinaryInstructions(filename_in, MEM.instructions, sizeof(MEM.instructions));
} else {
StoreHexInstructions(filename_in, MEM.instructions, sizeof(MEM.instructions));
}
assembly_out.open(filename_out, std::ios::out);
// Duplicate the filename of assembly_out and remove the previous extension, if there is one
std::string terminal_out_filename = filename_out;
size_t last_dot_index = terminal_out_filename.find_last_of('.');
if (last_dot_index != std::string::npos) {
terminal_out_filename.erase(last_dot_index);
}
terminal_out_filename.append(".term");
terminal_out.open(terminal_out_filename, std::ios::out);
ExecuteCode(MEM.instructions);
// END OF PROGRAM:
// Closing IO
assembly_out.close();
return 0;
}
/*_______________________________________________________________________________________________________________________*/
/*=======================================================================================================================*/
void ExecuteCode(u32 instructions[]) {
puts("[START OF SIMULATION]");
assembly_out << "[START OF SIMULATION]\n";
SP = 0x00007ffc;
while (running) {
// memory is indexed in 32 bits or 4bytes
// we just need to devide by 4 to get our index,
// in the instructions dynamic array
INSTRUCTION_COUNTER++;
u32 intruction_index = PC / 4ul;
if (PC > MEM_SIZE * 32)
break;
if (intruction_index > (MEM_SIZE * 32) >> 2)
break;
// Seeting the Next instruction
IR = SwitchEndianess(instructions[intruction_index]);
/*
if (INSTRUCTION_COUNTER >= 15490)
{
IR = 0b111111'00000'00000'00000'00000'000000;
}
*/
Expression expression{IR};
/* char intruction_address[13] = { 0 };
snprintf(intruction_address, sizeof(intruction_address),
"0x%08X:\t", PC); assembly_out << intruction_address;
printf(intruction_address);*/
// Processing a isntruction
ProcessExpression(expression);
// Reset R0
DefaultRoutines();
bool interruption_occurred = (int_flag >= 1);
u32 tempPC, tempSP;
if (interruption_occurred) {
tempPC = PC;
tempSP = SP;
PC = PPC;
SP = SSP;
}
R0 = 0;
PC += 4ul;
// Print to File
PrintOperation(expression.operation, expression.operands);
if (interruption_occurred) {
SP = tempSP;
PC = tempPC + 4ul;
}
}
if (T.Used()) {
PrintTerminal();
}
puts("[END OF SIMULATION]");
assembly_out << "[END OF SIMULATION]";
}
void PrintTerminal() {
printf("[TERMINAL]\n");
assembly_out << "[TERMINAL]\n";
terminal_out << "[TERMINAL]\n";
T.AddIn();
while (T.HasNext()) {
char c = T.Next();
// terminal_string += std::to_string(c);
if (c) {
printf("%c", c);
assembly_out << c;
terminal_out << c;
}
}
puts("");
assembly_out << "\n";
terminal_out << "\n";
}
void ProcessExpression(Expression ex) {
// Printing PC
// Creating Adress Count
char intruction_address[13] = {0};
snprintf(intruction_address, sizeof(intruction_address), "0x%08X:\t", PC);
bool is_valid_instruction = true;
switch (ex.operation) {
/*===========================Format 'U'=======================*/
// OP = 000000 mov
case OP::mov: {
inst::mov(ex.operands);
break;
}
// OP = 000001 movs
case OP::movs: {
inst::movs(ex.operands);
break;
}
// OP = 000010 add
case OP::add: {
inst::add(ex.operands);
break;
}
case OP::sub: {
inst::sub(ex.operands);
break;
}
// OP = 011111
// NOTE(Everton): Gotta be caferul with this operation code
// these operation have the same OP code = 0b000100
case /*:>the first 3 bits of operand.L are:*/
OP::mul | // mul = op.L: 0b000
OP::muls | // muls = op.L: 0b010
OP::DIV | // div = op.L: 0b100
OP::divs | // divs = op.L: 0b110
OP::sll | // sll = op.L: 0b001
OP::sla | // sla = op.L: 0b011
OP::srl | // srl = op.L: 0b101
OP::sra: // sra = op.L: 0b111
{
switch (GetBits(ex.operands.L, 10, 8)) {
case 0b000: // mul
{
inst::mul(ex.operands);
break;
}
case 0b010: // muls
{
inst::muls(ex.operands);
break;
}
case 0b100: // div
{
inst::div(ex.operands);
break;
}
case 0b110: // divs
{
inst::divs(ex.operands);
break;
}
case 0b001: // sll
{
inst::sll(ex.operands);
break;
}
case 0b011: // sla
{
inst::sla(ex.operands);
break;
}
case 0b101: // srl
{
inst::srl(ex.operands);
break;
}
case 0b111: // sra
{
inst::sra(ex.operands);
break;
}
}
break;
}
case OP::CMP: {
inst::CMP(ex.operands);
break;
}
case OP::AND: {
inst::AND(ex.operands);
break;
}
case OP::OR: {
inst::OR(ex.operands);
break;
}
case OP::NOT: {
inst::NOT(ex.operands);
break;
}
case OP::XOR: {
inst::XOR(ex.operands);
break;
}
case OP::push: {
inst::push(ex.operands);
break;
}
case OP::pop: {
inst::pop(ex.operands);
break;
}
//:>>/*===========================Format 'F'=======================*/
// OP = 010010 addi
case OP::addi: {
inst::addi(ex.operands);
break;
}
case OP::subi: {
inst::subi(ex.operands);
break;
}
case OP::muli: {
inst::muli(ex.operands);
break;
}
case OP::divi: {
inst::divi(ex.operands);
break;
}
case OP::remi: {
inst::remi(ex.operands);
break;
}
case OP::cmpi: {
inst::CMPI(ex.operands);
break;
}
case OP::l8: {
inst::l8(ex.operands);
break;
}
case OP::l16: {
inst::l16(ex.operands);
break;
}
case OP::l32: {
inst::l32(ex.operands);
break;
}
case OP::s8: {
inst::s8(ex.operands);
break;
}
case OP::s16: {
inst::s16(ex.operands);
break;
}
case OP::s32: {
inst::s32(ex.operands);
break;
}
case OP::call: {
inst::call(ex.operands);
break;
}
case OP::ret: {
inst::ret(ex.operands);
break;
}