Deterministic/reproducible builds

[walling]

I'm new to FPGA development, so forgive me if this idea is unattainable.

Would it be possible to have a FPGA build pipeline that produces deterministic/reproducible builds, i.e. the exact same bitstream for a given Verilog input? This would enable security features, like checking that you deploy the right bitstream and traceability (bitstream hash can be mapped to source).

I guess the question really is whether non-determinism can be removed from all subsystems (synthesis, place & route, etc.) involved in the build process and what the impacts are (performance, resource usage, compile time, etc.).

[QuantamHD]

Yes, this should be possible. We have reproducible builds in the ASIC space via https://github.com/hdl/bazel_rules_hdl

We would love to add FPGA support to the repo.

[walling]

@QuantamHD That's interesting. Is it the bazel ruleset that forces the determinism or is it already supported by the individual tools (yosys, nextpnr, etc.)?