diff --git a/common/service/ipmi/include/libipmi.h b/common/service/ipmi/include/libipmi.h
index 2b66d9bf10..0ec2bd6211 100644
--- a/common/service/ipmi/include/libipmi.h
+++ b/common/service/ipmi/include/libipmi.h
@@ -27,6 +27,8 @@
 #define IPMI_OEM_SENSOR_TYPE_CPU_DIMM_HOT 0xC7
 #define IPMI_OEM_SENSOR_TYPE_SYS_STA 0xC9
 #define IPMI_OEM_SENSOR_TYPE_SYS_BOOT_STA 0xCA
+#define IPMI_OEM_SENSOR_TYPE_VR 0xCB
+#define IPMI_OEM_SENSOR_TYPE_HDT 0xCC
 
 /* event/reading type, see IPMI spec 42.1, table 42-1 */
 #define IPMI_EVENT_TYPE_THRESHOLD 0x01
diff --git a/common/shell/commands/sensor_shell.c b/common/shell/commands/sensor_shell.c
index e242c87961..b6c9a367df 100644
--- a/common/shell/commands/sensor_shell.c
+++ b/common/shell/commands/sensor_shell.c
@@ -45,6 +45,7 @@ const char *const sensor_type_name[] = {
 	sensor_name_to_num(apml_mailbox)
 	sensor_name_to_num(xdpe19283b)
 	sensor_name_to_num(g788p81u)
+	sensor_name_to_num(mp2856gut)
 };
 
 const char *const sensor_status_name[] = {
diff --git a/meta-facebook/yv35-hd/src/platform/plat_class.c b/meta-facebook/yv35-hd/src/platform/plat_class.c
index d49471a9c8..274ccd9c06 100644
--- a/meta-facebook/yv35-hd/src/platform/plat_class.c
+++ b/meta-facebook/yv35-hd/src/platform/plat_class.c
@@ -16,8 +16,6 @@
 #define I2C_DATA_SIZE 5
 #define NUMBER_OF_ADC_CHANNEL 16
 #define AST1030_ADC_BASE_ADDR 0x7e6e9000
-#define ILIM_ADJUST_DEFAULT 0b001
-#define ILIM_ADJUST_2OU_EXP 0b011
 
 static uint8_t system_class = SYS_CLASS_1;
 static uint8_t board_revision = 0x3F;
@@ -280,39 +278,6 @@ void init_platform_config()
 			if (cnt == ARRAY_SIZE(_1ou_card_mapping_table)) {
 				printf("Unknown the 1OU card type, the voltage of ADC channel-6 is %fV\n",
 				       voltage);
-			} else if (_1ou_status.card_type == TYPE_1OU_RAINBOW_FALLS) {
-				if (hsc_module == HSC_MODULE_ADM1278) {
-					gpio_set(HSC_OCP_GPIO1_R, GPIO_HIGH);
-				} else if (hsc_module == HSC_MODULE_LTC4282) {
-					uint8_t ilim_adjust_data = 0;
-
-					tx_len = 1;
-					rx_len = 1;
-					memset(data, 0, I2C_DATA_SIZE);
-					data[0] = LTC4282_ILIM_ADJUST_OFFSET;
-					i2c_msg = construct_i2c_message(I2C_BUS5, LTC4282_ADDR,
-									tx_len, data, rx_len);
-					if (!i2c_master_read(&i2c_msg, retry)) {
-						ilim_adjust_data = i2c_msg.data[0];
-					} else {
-						printf("Failed to read ILIM_ADJUST from LTC4282\n");
-					}
-					/* Set ILIM to 15.625mV by writing 0b001 to bits[7:0] */
-					tx_len = 2;
-					rx_len = 0;
-					memset(data, 0, I2C_DATA_SIZE);
-					data[0] = LTC4282_ILIM_ADJUST_OFFSET;
-					data[1] = (ilim_adjust_data & 0x1f) | 0x20;
-					i2c_msg = construct_i2c_message(I2C_BUS5, LTC4282_ADDR,
-									tx_len, data, rx_len);
-					if (i2c_master_write(&i2c_msg, retry)) {
-						printf("Failed to set ILIM_ADJUST to LTC4282\n");
-					}
-				} else {
-					printf("Unsupported HSC module %d\n", hsc_module);
-				}
-			} else {
-				printf("Unsupported 1ou card type %d\n", _1ou_status.card_type);
 			}
 		}
 	}
@@ -339,49 +304,5 @@ void init_platform_config()
 		}
 	}
 
-	/* Set HSC OCP */
-	uint8_t ilim_adjust = ILIM_ADJUST_DEFAULT;
-	if (_2ou_status.present) {
-		if (hsc_module == HSC_MODULE_ADM1278) {
-			gpio_set(HSC_OCP_GPIO1_R, GPIO_LOW);
-			gpio_set(HSC_OCP_GPIO2_R, GPIO_LOW);
-			gpio_set(HSC_OCP_GPIO3_R, GPIO_HIGH);
-		} else if (hsc_module == HSC_MODULE_LTC4282) {
-			ilim_adjust = ILIM_ADJUST_2OU_EXP;
-		} else {
-			printf("Unsupported HSC module %d\n", hsc_module);
-		}
-	} else if ((!_1ou_status.present && !_2ou_status.present) ||
-		   (_1ou_status.present && (_1ou_status.card_type == TYPE_1OU_RAINBOW_FALLS))) {
-		printf("Default HSC OCP setting\n");
-	} else {
-		printf("Unsupported configuration, 1ou card type %d\n", _1ou_status.card_type);
-	}
-
-	if (hsc_module == HSC_MODULE_LTC4282) {
-		uint8_t ilim_register_data = 0;
-
-		tx_len = 1;
-		rx_len = 1;
-		memset(data, 0, I2C_DATA_SIZE);
-		data[0] = LTC4282_ILIM_ADJUST_OFFSET;
-		i2c_msg = construct_i2c_message(I2C_BUS5, LTC4282_ADDR, tx_len, data, rx_len);
-		if (!i2c_master_read(&i2c_msg, retry)) {
-			ilim_register_data = i2c_msg.data[0];
-		} else {
-			printf("Failed to read ILIM_ADJUST from LTC4282\n");
-		}
-		/* Set OCP by writing ilim_adjust to bits[7:5] */
-		tx_len = 2;
-		rx_len = 0;
-		memset(data, 0, I2C_DATA_SIZE);
-		data[0] = LTC4282_ILIM_ADJUST_OFFSET;
-		data[1] = (ilim_register_data & 0x1f) | ((ilim_adjust << 5) & 0xe0);
-		i2c_msg = construct_i2c_message(I2C_BUS5, LTC4282_ADDR, tx_len, data, rx_len);
-		if (i2c_master_write(&i2c_msg, retry)) {
-			printf("Failed to set ILIM_ADJUST to LTC4282\n");
-		}
-	}
-
 	SAFE_FREE(data);
 }
diff --git a/meta-facebook/yv35-hd/src/platform/plat_gpio.c b/meta-facebook/yv35-hd/src/platform/plat_gpio.c
index 1c30c5c76b..1291331a5f 100644
--- a/meta-facebook/yv35-hd/src/platform/plat_gpio.c
+++ b/meta-facebook/yv35-hd/src/platform/plat_gpio.c
@@ -12,376 +12,223 @@ const char *const gpio_name[] = {
 };
 #undef gpio_name_to_num
 
+// clang-format off
+
 GPIO_CFG plat_gpio_cfg[] = {
 	//  chip, number, is_init, is_latch, direction, status, property, int_type, int_cb
 	/** Group A: 00-07 **/
 	{ CHIP_GPIO, 0, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
-	{ CHIP_GPIO, 1, ENABLE, DISABLE, GPIO_INPUT, GPIO_HIGH, OPEN_DRAIN, GPIO_INT_EDGE_BOTH,
-	  ISR_POST_COMPLETE },
-	{ CHIP_GPIO, 2, ENABLE, DISABLE, GPIO_INPUT, GPIO_HIGH, PUSH_PULL, GPIO_INT_DISABLE, NULL },
-	{ CHIP_GPIO, 3, ENABLE, DISABLE, GPIO_INPUT, GPIO_HIGH, OPEN_DRAIN, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 4, ENABLE, DISABLE, GPIO_INPUT, GPIO_HIGH, OPEN_DRAIN, GPIO_INT_DISABLE,
-	  NULL },
+	{ CHIP_GPIO, 1, ENABLE, DISABLE, GPIO_INPUT, GPIO_HIGH, OPEN_DRAIN, GPIO_INT_EDGE_BOTH, ISR_POST_COMPLETE },
+	{ CHIP_GPIO, 2, ENABLE, DISABLE, GPIO_INPUT, GPIO_HIGH, PUSH_PULL, GPIO_INT_EDGE_BOTH, ISR_SLP3 },
+	{ CHIP_GPIO, 3, ENABLE, DISABLE, GPIO_INPUT, GPIO_HIGH, OPEN_DRAIN, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 4, ENABLE, DISABLE, GPIO_INPUT, GPIO_HIGH, OPEN_DRAIN, GPIO_INT_DISABLE, NULL },
 	{ CHIP_GPIO, 5, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
-	{ CHIP_GPIO, 6, ENABLE, DISABLE, GPIO_INPUT, GPIO_HIGH, OPEN_DRAIN, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 7, ENABLE, DISABLE, GPIO_OUTPUT, GPIO_HIGH, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
+	{ CHIP_GPIO, 6, ENABLE, DISABLE, GPIO_INPUT, GPIO_HIGH, OPEN_DRAIN, GPIO_INT_EDGE_BOTH, ISR_PVDDCR_CPU0_OCP },
+	{ CHIP_GPIO, 7, ENABLE, DISABLE, GPIO_OUTPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
 
 	/** Group B: 08-15 **/
-	{ CHIP_GPIO, 8, ENABLE, DISABLE, GPIO_INPUT, GPIO_HIGH, OPEN_DRAIN, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 9, ENABLE, DISABLE, GPIO_OUTPUT, GPIO_HIGH, OPEN_DRAIN, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 10, ENABLE, DISABLE, GPIO_OUTPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 11, ENABLE, DISABLE, GPIO_OUTPUT, GPIO_HIGH, OPEN_DRAIN, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 12, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 13, ENABLE, DISABLE, GPIO_INPUT, GPIO_HIGH, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 14, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 15, ENABLE, DISABLE, GPIO_INPUT, GPIO_HIGH, OPEN_DRAIN, GPIO_INT_DISABLE,
-	  NULL },
+	{ CHIP_GPIO, 8, ENABLE, DISABLE, GPIO_INPUT, GPIO_HIGH, OPEN_DRAIN, GPIO_INT_EDGE_BOTH, ISR_PVDDCR_CPU1_OCP },
+	{ CHIP_GPIO, 9, ENABLE, DISABLE, GPIO_OUTPUT, GPIO_HIGH, OPEN_DRAIN, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 10, ENABLE, DISABLE, GPIO_OUTPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 11, ENABLE, DISABLE, GPIO_OUTPUT, GPIO_HIGH, OPEN_DRAIN, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 12, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 13, ENABLE, DISABLE, GPIO_INPUT, GPIO_HIGH, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 14, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 15, ENABLE, DISABLE, GPIO_INPUT, GPIO_HIGH, OPEN_DRAIN, GPIO_INT_DISABLE, NULL },
 
 	/** Group C: 16-23 **/
-	{ CHIP_GPIO, 16, ENABLE, DISABLE, GPIO_INPUT, GPIO_HIGH, OPEN_DRAIN, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 17, ENABLE, DISABLE, GPIO_INPUT, GPIO_HIGH, OPEN_DRAIN, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 18, ENABLE, DISABLE, GPIO_INPUT, GPIO_HIGH, OPEN_DRAIN, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 19, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 20, ENABLE, DISABLE, GPIO_INPUT, GPIO_HIGH, OPEN_DRAIN, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 21, ENABLE, DISABLE, GPIO_INPUT, GPIO_HIGH, OPEN_DRAIN, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 22, ENABLE, DISABLE, GPIO_INPUT, GPIO_HIGH, OPEN_DRAIN, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 23, ENABLE, DISABLE, GPIO_INPUT, GPIO_HIGH, OPEN_DRAIN, GPIO_INT_DISABLE,
-	  NULL },
+	{ CHIP_GPIO, 16, ENABLE, DISABLE, GPIO_INPUT, GPIO_HIGH, OPEN_DRAIN, GPIO_INT_EDGE_BOTH, ISR_HSC_OC },
+	{ CHIP_GPIO, 17, ENABLE, DISABLE, GPIO_INPUT, GPIO_HIGH, OPEN_DRAIN, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 18, ENABLE, DISABLE, GPIO_INPUT, GPIO_HIGH, OPEN_DRAIN, GPIO_INT_EDGE_BOTH, ISR_PVDDCR_CPU1_PMALERT },
+	{ CHIP_GPIO, 19, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 20, ENABLE, DISABLE, GPIO_INPUT, GPIO_HIGH, OPEN_DRAIN, GPIO_INT_EDGE_FALLING, ISR_SOC_THMALTRIP },
+	{ CHIP_GPIO, 21, ENABLE, DISABLE, GPIO_INPUT, GPIO_HIGH, OPEN_DRAIN, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 22, ENABLE, DISABLE, GPIO_INPUT, GPIO_HIGH, OPEN_DRAIN, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 23, ENABLE, DISABLE, GPIO_INPUT, GPIO_HIGH, OPEN_DRAIN, GPIO_INT_DISABLE, NULL },
 
 	/** Group D: 24-31 **/
-	{ CHIP_GPIO, 24, ENABLE, DISABLE, GPIO_INPUT, GPIO_HIGH, OPEN_DRAIN, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 25, ENABLE, DISABLE, GPIO_OUTPUT, GPIO_HIGH, OPEN_DRAIN, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 26, ENABLE, DISABLE, GPIO_OUTPUT, GPIO_HIGH, OPEN_DRAIN, GPIO_INT_DISABLE,
-	  NULL },
+	{ CHIP_GPIO, 24, ENABLE, DISABLE, GPIO_INPUT, GPIO_HIGH, OPEN_DRAIN, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 25, ENABLE, DISABLE, GPIO_OUTPUT, GPIO_HIGH, OPEN_DRAIN, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 26, ENABLE, DISABLE, GPIO_OUTPUT, GPIO_HIGH, OPEN_DRAIN, GPIO_INT_DISABLE, NULL },
 	{ CHIP_GPIO, 27, ENABLE, ENABLE, GPIO_OUTPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
-	{ CHIP_GPIO, 28, ENABLE, DISABLE, GPIO_OUTPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 29, ENABLE, DISABLE, GPIO_OUTPUT, GPIO_HIGH, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 30, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 31, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
+	{ CHIP_GPIO, 28, ENABLE, DISABLE, GPIO_OUTPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 29, ENABLE, DISABLE, GPIO_OUTPUT, GPIO_HIGH, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 30, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 31, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
 
 	/** Group E: 32-39 **/
-	{ CHIP_GPIO, 32, ENABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_EDGE_BOTH,
-	  ISR_DC_ON },
-	{ CHIP_GPIO, 33, ENABLE, DISABLE, GPIO_INPUT, GPIO_HIGH, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 34, ENABLE, DISABLE, GPIO_INPUT, GPIO_HIGH, OPEN_DRAIN, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 35, ENABLE, DISABLE, GPIO_INPUT, GPIO_HIGH, OPEN_DRAIN, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 36, ENABLE, DISABLE, GPIO_INPUT, GPIO_HIGH, OPEN_DRAIN, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 37, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 38, ENABLE, DISABLE, GPIO_INPUT, GPIO_HIGH, OPEN_DRAIN, GPIO_INT_DISABLE,
-	  NULL },
+	{ CHIP_GPIO, 32, ENABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_EDGE_BOTH, ISR_DC_ON },
+	{ CHIP_GPIO, 33, ENABLE, DISABLE, GPIO_INPUT, GPIO_HIGH, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 34, ENABLE, DISABLE, GPIO_INPUT, GPIO_HIGH, OPEN_DRAIN, GPIO_INT_EDGE_BOTH, ISR_PVDD11_S3_PMALERT },
+	{ CHIP_GPIO, 35, ENABLE, DISABLE, GPIO_INPUT, GPIO_HIGH, OPEN_DRAIN, GPIO_INT_EDGE_BOTH, ISR_HSC_THROTTLE },
+	{ CHIP_GPIO, 36, ENABLE, DISABLE, GPIO_INPUT, GPIO_HIGH, OPEN_DRAIN, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 37, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 38, ENABLE, DISABLE, GPIO_INPUT, GPIO_HIGH, OPEN_DRAIN, GPIO_INT_DISABLE, NULL },
 	{ CHIP_GPIO, 39, ENABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+
 	/** Group F: 40-47 **/
-	{ CHIP_GPIO, 40, ENABLE, DISABLE, GPIO_INPUT, GPIO_HIGH, OPEN_DRAIN, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 41, ENABLE, DISABLE, GPIO_INPUT, GPIO_HIGH, OPEN_DRAIN, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 42, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 43, ENABLE, DISABLE, GPIO_OUTPUT, GPIO_HIGH, OPEN_DRAIN, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 44, ENABLE, DISABLE, GPIO_INPUT, GPIO_HIGH, OPEN_DRAIN, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 45, ENABLE, DISABLE, GPIO_OUTPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 46, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 47, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
+	{ CHIP_GPIO, 40, ENABLE, DISABLE, GPIO_INPUT, GPIO_HIGH, OPEN_DRAIN, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 41, ENABLE, DISABLE, GPIO_INPUT, GPIO_HIGH, OPEN_DRAIN, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 42, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 43, ENABLE, DISABLE, GPIO_OUTPUT, GPIO_HIGH, OPEN_DRAIN, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 44, ENABLE, DISABLE, GPIO_INPUT, GPIO_HIGH, OPEN_DRAIN, GPIO_INT_EDGE_BOTH, ISR_DBP_PRSNT },
+	{ CHIP_GPIO, 45, ENABLE, DISABLE, GPIO_OUTPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 46, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 47, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
 
 	/** Group G: 48-55 **/
-	{ CHIP_GPIO, 48, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 49, ENABLE, DISABLE, GPIO_OUTPUT, GPIO_HIGH, OPEN_DRAIN, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 50, ENABLE, DISABLE, GPIO_INPUT, GPIO_HIGH, OPEN_DRAIN, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 51, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 52, ENABLE, DISABLE, GPIO_OUTPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 53, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 54, ENABLE, DISABLE, GPIO_OUTPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 55, ENABLE, DISABLE, GPIO_OUTPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
+	{ CHIP_GPIO, 48, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 49, ENABLE, DISABLE, GPIO_OUTPUT, GPIO_HIGH, OPEN_DRAIN, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 50, ENABLE, DISABLE, GPIO_INPUT, GPIO_HIGH, OPEN_DRAIN, GPIO_INT_EDGE_BOTH, ISR_MB_THROTTLE },
+	{ CHIP_GPIO, 51, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 52, ENABLE, DISABLE, GPIO_OUTPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 53, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 54, ENABLE, DISABLE, GPIO_OUTPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 55, ENABLE, DISABLE, GPIO_OUTPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
 
 	/** Group H: 56-63 **/
 	{ CHIP_GPIO, 56, ENABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
-	{ CHIP_GPIO, 57, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 58, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 59, ENABLE, DISABLE, GPIO_INPUT, GPIO_HIGH, OPEN_DRAIN, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 60, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 61, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 62, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 63, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
+	{ CHIP_GPIO, 57, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 58, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 59, ENABLE, DISABLE, GPIO_INPUT, GPIO_HIGH, OPEN_DRAIN, GPIO_INT_EDGE_BOTH, ISR_SYS_THROTTLE },
+	{ CHIP_GPIO, 60, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 61, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 62, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 63, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
 
 	/** Group I: 64-71 **/
-	{ CHIP_GPIO, 64, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 65, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 66, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 67, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 68, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 69, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 70, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 71, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
+	{ CHIP_GPIO, 64, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 65, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 66, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 67, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 68, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 69, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 70, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 71, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
 
 	/** Group J: 72-79 **/
-	{ CHIP_GPIO, 72, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 73, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 74, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 75, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 76, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 77, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 78, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 79, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
+	{ CHIP_GPIO, 72, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 73, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 74, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 75, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 76, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 77, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 78, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 79, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
 
 	/** Group K: 80-87 **/
-	{ CHIP_GPIO, 80, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 81, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 82, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 83, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 84, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 85, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 86, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 87, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
+	{ CHIP_GPIO, 80, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 81, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 82, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 83, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 84, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 85, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 86, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 87, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
 
 	/** Group L: 88-95 **/
-	{ CHIP_GPIO, 88, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 89, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 90, ENABLE, DISABLE, GPIO_OUTPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
+	{ CHIP_GPIO, 88, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 89, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 90, ENABLE, DISABLE, GPIO_OUTPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
 	{ CHIP_GPIO, 91, ENABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
-	{ CHIP_GPIO, 92, ENABLE, DISABLE, GPIO_INPUT, GPIO_HIGH, OPEN_DRAIN, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 93, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
+	{ CHIP_GPIO, 92, ENABLE, DISABLE, GPIO_INPUT, GPIO_HIGH, OPEN_DRAIN, GPIO_INT_EDGE_BOTH, ISR_PVDDCR_CPU0_PMALERT },
+	{ CHIP_GPIO, 93, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
 	{ CHIP_GPIO, 94, ENABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
 	{ CHIP_GPIO, 95, ENABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
 
 	/** Group M: 96-103 **/
-	{ CHIP_GPIO, 96, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
+	{ CHIP_GPIO, 96, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
 	{ CHIP_GPIO, 97, ENABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
-	{ CHIP_GPIO, 98, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 99, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 100, ENABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 101, ENABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 102, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 103, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
+	{ CHIP_GPIO, 98, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 99, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 100, ENABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 101, ENABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 102, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 103, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
 
 	/** Group N: 104-111 **/
-	{ CHIP_GPIO, 104, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 105, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 106, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 107, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 108, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 109, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 110, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 111, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
+	{ CHIP_GPIO, 104, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 105, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 106, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 107, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 108, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 109, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 110, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 111, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
 
 	/** Group O: 112-119 **/
-	{ CHIP_GPIO, 112, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 113, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 114, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 115, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 116, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 117, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 118, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 119, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
+	{ CHIP_GPIO, 112, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 113, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 114, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 115, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 116, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 117, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 118, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 119, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
 
 	/** Group P: 120-127 **/
-	{ CHIP_GPIO, 120, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 121, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 122, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 123, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 124, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 125, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 126, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 127, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
+	{ CHIP_GPIO, 120, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 121, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 122, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 123, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 124, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 125, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 126, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 127, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
 
 	/** Group Q: 128-135 **/
-	{ CHIP_GPIO, 128, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 129, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 130, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 131, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 132, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 133, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 134, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 135, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
+	{ CHIP_GPIO, 128, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 129, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 130, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 131, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 132, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 133, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 134, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 135, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
 
 	/** Group R: 136-143 **/
-	{ CHIP_GPIO, 136, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 137, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 138, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 139, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 140, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 141, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 142, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 143, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
+	{ CHIP_GPIO, 136, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 137, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 138, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 139, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 140, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 141, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 142, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 143, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
 
 	/** Group S: 144-151 **/
-	{ CHIP_GPIO, 144, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 145, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 146, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 147, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 148, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 149, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 150, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 151, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
+	{ CHIP_GPIO, 144, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 145, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 146, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 147, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 148, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 149, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 150, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 151, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
 
 	/** Group T: 152-159 **/
-	{ CHIP_GPIO, 152, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 153, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 154, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 155, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 156, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 157, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 158, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 159, ENABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
+	{ CHIP_GPIO, 152, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 153, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 154, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 155, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 156, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 157, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 158, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 159, ENABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
 
 	/** Group U: 160-167 **/
-	{ CHIP_GPIO, 160, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 161, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 162, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 163, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 164, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 165, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 166, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
-	{ CHIP_GPIO, 167, ENABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE,
-	  NULL },
+	{ CHIP_GPIO, 160, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 161, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 162, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 163, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 164, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 165, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 166, DISABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
+	{ CHIP_GPIO, 167, ENABLE, DISABLE, GPIO_INPUT, GPIO_LOW, PUSH_PULL, GPIO_INT_DISABLE, NULL },
 };
 
+// clang-format on
+
 bool pal_load_gpio_config(void)
 {
 	memcpy(&gpio_cfg[0], &plat_gpio_cfg[0], sizeof(plat_gpio_cfg));
diff --git a/meta-facebook/yv35-hd/src/platform/plat_init.c b/meta-facebook/yv35-hd/src/platform/plat_init.c
index 84616674c4..43e025db76 100644
--- a/meta-facebook/yv35-hd/src/platform/plat_init.c
+++ b/meta-facebook/yv35-hd/src/platform/plat_init.c
@@ -25,6 +25,7 @@ void pal_set_sys_status()
 {
 	set_DC_status(PWRGD_CPU_LVC3);
 	set_DC_on_delayed_status();
+	set_DC_off_delayed_status();
 	set_post_status(FM_BIOS_POST_CMPLT_BIC_N);
 	set_CPU_power_status(PWRGD_CPU_LVC3);
 	set_sys_ready_pin(BIC_READY);
diff --git a/meta-facebook/yv35-hd/src/platform/plat_isr.c b/meta-facebook/yv35-hd/src/platform/plat_isr.c
index d89b1996d1..6ef2b97aeb 100644
--- a/meta-facebook/yv35-hd/src/platform/plat_isr.c
+++ b/meta-facebook/yv35-hd/src/platform/plat_isr.c
@@ -1,9 +1,13 @@
+#include <stdlib.h>
 #include "plat_isr.h"
 #include "plat_gpio.h"
 #include "plat_sensor_table.h"
 #include "libipmi.h"
 #include "power_status.h"
 #include "ipmi.h"
+#include "plat_class.h"
+#include "plat_i2c.h"
+#include "pmbus.h"
 
 void ISR_POST_COMPLETE()
 {
@@ -11,13 +15,335 @@ void ISR_POST_COMPLETE()
 }
 
 K_WORK_DELAYABLE_DEFINE(set_DC_on_5s_work, set_DC_on_delayed_status);
+K_WORK_DELAYABLE_DEFINE(set_DC_off_10s_work, set_DC_off_delayed_status);
 #define DC_ON_5_SECOND 5
+#define DC_OFF_10_SECOND 10
 void ISR_DC_ON()
 {
 	set_DC_status(PWRGD_CPU_LVC3);
 	if (get_DC_status() == true) {
 		k_work_schedule(&set_DC_on_5s_work, K_SECONDS(DC_ON_5_SECOND));
+		if (k_work_cancel_delayable(&set_DC_off_10s_work) != 0) {
+			printf("[%s] Failed to cancel set dc off delay work.\n", __func__);
+		}
+		set_DC_off_delayed_status();
 	} else {
+		k_work_schedule(&set_DC_off_10s_work, K_SECONDS(DC_OFF_10_SECOND));
+		if (k_work_cancel_delayable(&set_DC_on_5s_work) != 0) {
+			printf("[%s] Failed to cancel set dc on delay work.\n", __func__);
+		}
 		set_DC_on_delayed_status();
+
+		if ((gpio_get(FM_CPU_BIC_SLP_S3_N) == GPIO_HIGH) &&
+		    (gpio_get(RST_RSMRST_BMC_N) == GPIO_HIGH)) {
+			common_addsel_msg_t sel_msg;
+			sel_msg.InF_target = BMC_IPMB;
+			sel_msg.sensor_type = IPMI_OEM_SENSOR_TYPE_OEM_C3;
+			sel_msg.event_type = IPMI_EVENT_TYPE_SENSOR_SPECIFIC;
+			sel_msg.sensor_number = SENSOR_NUM_POWER_ERROR;
+			sel_msg.event_data1 = IPMI_OEM_EVENT_OFFSET_SYS_PWROK_FAIL;
+			sel_msg.event_data2 = 0xFF;
+			sel_msg.event_data3 = 0xFF;
+			if (!common_add_sel_evt_record(&sel_msg)) {
+				printf("[%s] Failed to add system PWROK failure sel.\n", __func__);
+			}
+		}
+	}
+}
+
+static void SLP3_handler()
+{
+	common_addsel_msg_t sel_msg;
+	if ((gpio_get(FM_CPU_BIC_SLP_S3_N) == GPIO_HIGH) &&
+	    (gpio_get(PWRGD_CPU_LVC3) == GPIO_LOW)) {
+		sel_msg.InF_target = BMC_IPMB;
+		sel_msg.sensor_type = IPMI_OEM_SENSOR_TYPE_SYS_STA;
+		sel_msg.event_type = IPMI_EVENT_TYPE_SENSOR_SPECIFIC;
+		sel_msg.sensor_number = SENSOR_NUM_SYSTEM_STATUS;
+		sel_msg.event_data1 = IPMI_OEM_EVENT_OFFSET_SYS_VRWATCHDOG;
+		sel_msg.event_data2 = 0xFF;
+		sel_msg.event_data3 = 0xFF;
+		if (!common_add_sel_evt_record(&sel_msg)) {
+			printf("[%s] Failed to add VR watchdog timeout sel.\n", __func__);
+		}
+	}
+}
+
+K_WORK_DELAYABLE_DEFINE(SLP3_work, SLP3_handler);
+void ISR_SLP3()
+{
+	if (gpio_get(FM_CPU_BIC_SLP_S3_N) == GPIO_HIGH) {
+		printf("slp3\n");
+		k_work_schedule(&SLP3_work, K_MSEC(10000));
+		return;
+	} else {
+		if (k_work_cancel_delayable(&SLP3_work) != 0) {
+			printf("[%s] Failed to cancel delayable work.\n", __func__);
+		}
+	}
+}
+
+void ISR_DBP_PRSNT()
+{
+	common_addsel_msg_t sel_msg;
+	if ((gpio_get(FM_DBP_PRESENT_N) == GPIO_HIGH)) {
+		sel_msg.event_type = IPMI_OEM_EVENT_TYPE_DEASSART;
+	} else {
+		sel_msg.event_type = IPMI_EVENT_TYPE_SENSOR_SPECIFIC;
+	}
+	sel_msg.InF_target = BMC_IPMB;
+	sel_msg.sensor_type = IPMI_OEM_SENSOR_TYPE_HDT;
+	sel_msg.sensor_number = SENSOR_NUM_HDT_PRESENT;
+	sel_msg.event_data1 = 0xFF;
+	sel_msg.event_data2 = 0xFF;
+	sel_msg.event_data3 = 0xFF;
+	if (!common_add_sel_evt_record(&sel_msg)) {
+		printf("[%s] Failed to add HDT present sel.\n", __func__);
+	}
+}
+
+void ISR_HSC_THROTTLE()
+{
+	common_addsel_msg_t sel_msg;
+	static bool is_hsc_throttle_assert = false; // Flag for filt out fake alert
+	if (gpio_get(RST_RSMRST_BMC_N) == GPIO_HIGH) {
+		if ((gpio_get(PWRGD_CPU_LVC3) == GPIO_LOW) &&
+		    (get_DC_off_delayed_status() == false)) {
+			return;
+		} else {
+			if ((gpio_get(IRQ_HSC_ALERT1_N) == GPIO_HIGH) &&
+			    (is_hsc_throttle_assert == true)) {
+				sel_msg.event_type = IPMI_OEM_EVENT_TYPE_DEASSART;
+				is_hsc_throttle_assert = false;
+			} else if ((gpio_get(IRQ_HSC_ALERT1_N) == GPIO_LOW) &&
+				   (is_hsc_throttle_assert == false)) {
+				sel_msg.event_type = IPMI_EVENT_TYPE_SENSOR_SPECIFIC;
+				is_hsc_throttle_assert = true;
+			} else { // Fake alert
+				return;
+			}
+
+			sel_msg.InF_target = BMC_IPMB;
+			sel_msg.sensor_type = IPMI_OEM_SENSOR_TYPE_SYS_STA;
+			sel_msg.sensor_number = SENSOR_NUM_SYSTEM_STATUS;
+			sel_msg.event_data1 = IPMI_OEM_EVENT_OFFSET_SYS_PMBUSALERT;
+			sel_msg.event_data2 = 0xFF;
+			sel_msg.event_data3 = 0xFF;
+			if (!common_add_sel_evt_record(&sel_msg)) {
+				printf("[%s] Failed to add HSC Throttle sel.\n", __func__);
+			}
+		}
+	}
+}
+
+void ISR_MB_THROTTLE()
+{
+	common_addsel_msg_t sel_msg;
+	if (gpio_get(RST_RSMRST_BMC_N) == GPIO_HIGH) {
+		if (gpio_get(FAST_PROCHOT_N) == GPIO_HIGH) {
+			sel_msg.event_type = IPMI_OEM_EVENT_TYPE_DEASSART;
+		} else {
+			sel_msg.event_type = IPMI_EVENT_TYPE_SENSOR_SPECIFIC;
+		}
+		sel_msg.InF_target = BMC_IPMB;
+		sel_msg.sensor_type = IPMI_OEM_SENSOR_TYPE_SYS_STA;
+		sel_msg.sensor_number = SENSOR_NUM_SYSTEM_STATUS;
+		sel_msg.event_data1 = IPMI_OEM_EVENT_OFFSET_SYS_FIRMWAREASSERT;
+		sel_msg.event_data2 = 0xFF;
+		sel_msg.event_data3 = 0xFF;
+		if (!common_add_sel_evt_record(&sel_msg)) {
+			printf("[%s] Failed to add MB Throttle sel.\n", __func__);
+		}
+	}
+}
+
+void ISR_SOC_THMALTRIP()
+{
+	common_addsel_msg_t sel_msg;
+	if (gpio_get(RST_PLTRST_BIC_N) == GPIO_HIGH) {
+		sel_msg.InF_target = BMC_IPMB;
+		sel_msg.event_type = IPMI_EVENT_TYPE_SENSOR_SPECIFIC;
+		sel_msg.sensor_type = IPMI_OEM_SENSOR_TYPE_SYS_STA;
+		sel_msg.sensor_number = SENSOR_NUM_SYSTEM_STATUS;
+		sel_msg.event_data1 = IPMI_OEM_EVENT_OFFSET_SYS_THERMAL_TRIP;
+		sel_msg.event_data2 = 0xFF;
+		sel_msg.event_data3 = 0xFF;
+		if (!common_add_sel_evt_record(&sel_msg)) {
+			printf("[%s] Failed to add SOC Thermal trip sel.\n", __func__);
+		}
+	}
+}
+
+void ISR_SYS_THROTTLE()
+{
+	common_addsel_msg_t sel_msg;
+	if ((gpio_get(RST_PLTRST_BIC_N) == GPIO_HIGH) && (gpio_get(PWRGD_CPU_LVC3) == GPIO_HIGH)) {
+		if (gpio_get(FM_CPU_BIC_PROCHOT_LVT3_N) == GPIO_HIGH) {
+			sel_msg.event_type = IPMI_OEM_EVENT_TYPE_DEASSART;
+		} else {
+			sel_msg.event_type = IPMI_EVENT_TYPE_SENSOR_SPECIFIC;
+		}
+		sel_msg.InF_target = BMC_IPMB;
+		sel_msg.sensor_type = IPMI_OEM_SENSOR_TYPE_SYS_STA;
+		sel_msg.sensor_number = SENSOR_NUM_SYSTEM_STATUS;
+		sel_msg.event_data1 = IPMI_OEM_EVENT_OFFSET_SYS_THROTTLE;
+		sel_msg.event_data2 = 0xFF;
+		sel_msg.event_data3 = 0xFF;
+		if (!common_add_sel_evt_record(&sel_msg)) {
+			printf("[%s] Failed to add System Throttle sel.\n", __func__);
+		}
+	}
+}
+
+void ISR_HSC_OC()
+{
+	common_addsel_msg_t sel_msg;
+	if (gpio_get(RST_RSMRST_BMC_N) == GPIO_HIGH) {
+		if (gpio_get(FM_HSC_TIMER) == GPIO_LOW) {
+			sel_msg.event_type = IPMI_OEM_EVENT_TYPE_DEASSART;
+		} else {
+			sel_msg.event_type = IPMI_EVENT_TYPE_SENSOR_SPECIFIC;
+		}
+		sel_msg.InF_target = BMC_IPMB;
+		sel_msg.sensor_type = IPMI_OEM_SENSOR_TYPE_SYS_STA;
+		sel_msg.sensor_number = SENSOR_NUM_SYSTEM_STATUS;
+		sel_msg.event_data1 = IPMI_OEM_EVENT_OFFSET_SYS_HSCTIMER;
+		sel_msg.event_data2 = 0xFF;
+		sel_msg.event_data3 = 0xFF;
+		if (!common_add_sel_evt_record(&sel_msg)) {
+			printf("[%s] Failed to add HSC OC sel.\n", __func__);
+		}
+	}
+}
+
+static void add_vr_ocp_sel(uint8_t gpio_num, uint8_t vr_num)
+{
+	common_addsel_msg_t sel_msg;
+	if (gpio_get(gpio_num) == GPIO_HIGH) {
+		sel_msg.event_type = IPMI_OEM_EVENT_TYPE_DEASSART;
+	} else {
+		sel_msg.event_type = IPMI_EVENT_TYPE_SENSOR_SPECIFIC;
+	}
+	sel_msg.InF_target = BMC_IPMB;
+	sel_msg.sensor_type = IPMI_OEM_SENSOR_TYPE_VR;
+	sel_msg.sensor_number = SENSOR_NUM_VR_OCP;
+	sel_msg.event_data1 = vr_num;
+	sel_msg.event_data2 = 0xFF;
+	sel_msg.event_data3 = 0xFF;
+	if (!common_add_sel_evt_record(&sel_msg)) {
+		printf("[%s] Failed to add VR OCP sel.\n", __func__);
+	}
+}
+
+void ISR_PVDDCR_CPU0_OCP()
+{
+	if (get_DC_status() == true) {
+		add_vr_ocp_sel(PVDDCR_CPU0_BIC_OCP_N, 0);
+	}
+}
+
+void ISR_PVDDCR_CPU1_OCP()
+{
+	if (get_DC_status() == true) {
+		add_vr_ocp_sel(PVDDCR_CPU1_BIC_OCP_N, 1);
+	}
+}
+
+void ISR_PVDD11_S3_OCP()
+{
+	if (get_DC_status() == true) {
+		add_vr_ocp_sel(PVDD11_S3_BIC_OCP_N, 2);
+	}
+}
+
+static void add_vr_pmalert_sel(uint8_t gpio_num, uint8_t vr_addr, uint8_t vr_num)
+{
+	uint8_t retry = 5;
+	I2C_MSG *msg = (I2C_MSG *)malloc(sizeof(I2C_MSG));
+	if (msg == NULL) {
+		printf("[%s] Failed to allocate I2C_MSG.\n", __func__);
+		return;
+	}
+
+	for (int page = 0; page < 2; page++) {
+		msg->bus = I2C_BUS5;
+		msg->target_addr = vr_addr;
+		msg->tx_len = 2;
+		msg->data[0] = PMBUS_PAGE;
+		msg->data[1] = page;
+
+		if (i2c_master_write(msg, retry)) {
+			printf("[%s] Failed to write page.\n", __func__);
+			return;
+		}
+
+		msg->bus = I2C_BUS5;
+		msg->target_addr = vr_addr;
+		msg->tx_len = 1;
+		msg->rx_len = 2;
+		msg->data[0] = PMBUS_STATUS_WORD;
+
+		if (i2c_master_read(msg, retry)) {
+			printf("[%s] Failed to read PMBUS_STATUS_WORD.\n", __func__);
+			return;
+		}
+
+		common_addsel_msg_t sel_msg;
+		if (gpio_get(gpio_num) == GPIO_HIGH) {
+			sel_msg.event_type = IPMI_OEM_EVENT_TYPE_DEASSART;
+		} else {
+			sel_msg.event_type = IPMI_EVENT_TYPE_SENSOR_SPECIFIC;
+		}
+		sel_msg.InF_target = BMC_IPMB;
+		sel_msg.sensor_type = IPMI_OEM_SENSOR_TYPE_VR;
+		sel_msg.sensor_number = SENSOR_NUM_VR_ALERT;
+		sel_msg.event_data1 = (vr_num << 1) | (page & 0x01);
+		sel_msg.event_data2 = msg->data[0];
+		sel_msg.event_data3 = msg->data[1];
+		if (!common_add_sel_evt_record(&sel_msg)) {
+			printf("[%s] Failed to add VR PMALERT sel.\n", __func__);
+		}
+	}
+}
+
+void ISR_PVDDCR_CPU0_PMALERT()
+{
+	if (get_DC_status() == true) {
+		uint8_t board_rev = get_board_revision();
+		if (board_rev == SYS_BOARD_EVT_BOM2) {
+			add_vr_pmalert_sel(PVDDCR_CPU0_PMALERT_N, XDPE19283B_PVDDCR_CPU0_ADDR, 0);
+		} else if (board_rev == SYS_BOARD_EVT_BOM3) {
+			add_vr_pmalert_sel(PVDDCR_CPU0_PMALERT_N, MP2856GUT_PVDDCR_CPU0_ADDR, 0);
+		} else {
+			add_vr_pmalert_sel(PVDDCR_CPU0_PMALERT_N, RAA229621_PVDDCR_CPU0_ADDR, 0);
+		}
+	}
+}
+
+void ISR_PVDDCR_CPU1_PMALERT()
+{
+	if (get_DC_status() == true) {
+		uint8_t board_rev = get_board_revision();
+		if (board_rev == SYS_BOARD_EVT_BOM2) {
+			add_vr_pmalert_sel(PVDDCR_CPU1_PMALERT_N, XDPE19283B_PVDDCR_CPU1_ADDR, 1);
+		} else if (board_rev == SYS_BOARD_EVT_BOM3) {
+			add_vr_pmalert_sel(PVDDCR_CPU1_PMALERT_N, MP2856GUT_PVDDCR_CPU1_ADDR, 1);
+		} else {
+			add_vr_pmalert_sel(PVDDCR_CPU1_PMALERT_N, RAA229621_PVDDCR_CPU1_ADDR, 1);
+		}
+	}
+}
+
+void ISR_PVDD11_S3_PMALERT()
+{
+	if (get_DC_status() == true) {
+		uint8_t board_rev = get_board_revision();
+		if (board_rev == SYS_BOARD_EVT_BOM2) {
+			add_vr_pmalert_sel(PVDD11_S3_PMALERT_N, XDPE19283B_PVDD11_S3_ADDR, 2);
+		} else if (board_rev == SYS_BOARD_EVT_BOM3) {
+			add_vr_pmalert_sel(PVDD11_S3_PMALERT_N, MP2856GUT_PVDD11_S3_ADDR, 2);
+		} else {
+			add_vr_pmalert_sel(PVDD11_S3_PMALERT_N, RAA229621_PVDD11_S3_ADDR, 2);
+		}
 	}
 }
diff --git a/meta-facebook/yv35-hd/src/platform/plat_isr.h b/meta-facebook/yv35-hd/src/platform/plat_isr.h
index cc56950537..5b2a84c2d0 100644
--- a/meta-facebook/yv35-hd/src/platform/plat_isr.h
+++ b/meta-facebook/yv35-hd/src/platform/plat_isr.h
@@ -3,5 +3,18 @@
 
 void ISR_POST_COMPLETE();
 void ISR_DC_ON();
+void ISR_SLP3();
+void ISR_DBP_PRSNT();
+void ISR_HSC_THROTTLE();
+void ISR_MB_THROTTLE();
+void ISR_SOC_THMALTRIP();
+void ISR_SYS_THROTTLE();
+void ISR_HSC_OC();
+void ISR_PVDDCR_CPU1_OCP();
+void ISR_PVDDCR_CPU0_OCP();
+void ISR_PVDD11_S3_OCP();
+void ISR_PVDDCR_CPU1_PMALERT();
+void ISR_PVDDCR_CPU0_PMALERT();
+void ISR_PVDD11_S3_PMALERT();
 
 #endif
diff --git a/meta-facebook/yv35-hd/src/platform/plat_sensor_table.h b/meta-facebook/yv35-hd/src/platform/plat_sensor_table.h
index 48aa17274f..1029b7a77b 100644
--- a/meta-facebook/yv35-hd/src/platform/plat_sensor_table.h
+++ b/meta-facebook/yv35-hd/src/platform/plat_sensor_table.h
@@ -100,6 +100,12 @@
 
 #define POLL_TIME_BAT3V 3600 // second
 
+#define SENSOR_NUM_SYSTEM_STATUS 0x10
+#define SENSOR_NUM_POWER_ERROR 0x56
+#define SENSOR_NUM_VR_OCP 0x71
+#define SENSOR_NUM_VR_ALERT 0x72
+#define SENSOR_NUM_HDT_PRESENT 0xBD
+
 uint8_t plat_get_config_size();
 void load_sensor_config(void);