From 967d3eeb54aa9c5e3f4f6f850b159b3aaf9c5fc6 Mon Sep 17 00:00:00 2001 From: Scron Chang Date: Fri, 5 Aug 2022 15:19:09 +0800 Subject: [PATCH 1/4] fby3.5: rf: Enable USB feature. Modify the kernel config file to enable the USB feature. Signed-off-by: Scron Chang --- meta-facebook/yv35-rf/boards/ast1030_evb.conf | 2 +- meta-facebook/yv35-rf/prj.conf | 6 +++--- meta-facebook/yv35-rf/src/platform/plat_def.h | 2 ++ 3 files changed, 6 insertions(+), 4 deletions(-) diff --git a/meta-facebook/yv35-rf/boards/ast1030_evb.conf b/meta-facebook/yv35-rf/boards/ast1030_evb.conf index dac08bda3b..eef277bc12 100644 --- a/meta-facebook/yv35-rf/boards/ast1030_evb.conf +++ b/meta-facebook/yv35-rf/boards/ast1030_evb.conf @@ -9,7 +9,7 @@ CONFIG_TACH_ASPEED=n CONFIG_ESPI_ASPEED=n CONFIG_PECI_ASPEED=n CONFIG_PECI_ASPEED_INTERRUPT_DRIVEN=n -CONFIG_USB_ASPEED=n +CONFIG_USB_ASPEED=y CONFIG_I3C_ASPEED=n CONFIG_CRYPTO=n CONFIG_CRYPTO_ASPEED=n diff --git a/meta-facebook/yv35-rf/prj.conf b/meta-facebook/yv35-rf/prj.conf index ffe5eefc9f..3b6deb198e 100644 --- a/meta-facebook/yv35-rf/prj.conf +++ b/meta-facebook/yv35-rf/prj.conf @@ -53,10 +53,10 @@ CONFIG_I3C_SLAVE=n CONFIG_I3C_SLAVE_MQUEUE=n CONFIG_WATCHDOG=y #USB -CONFIG_USB=n -CONFIG_USB_DEVICE_STACK=n +CONFIG_USB=y +CONFIG_USB_DEVICE_STACK=y CONFIG_USB_DEVICE_PRODUCT="Zephyr CDC ACM" -CONFIG_USB_CDC_ACM=n +CONFIG_USB_CDC_ACM=y CONFIG_USB_CDC_ACM_RINGBUF_SIZE=576 CONFIG_USB_DEVICE_VID=0x1d6b CONFIG_USB_DEVICE_PID=0x0104 diff --git a/meta-facebook/yv35-rf/src/platform/plat_def.h b/meta-facebook/yv35-rf/src/platform/plat_def.h index b3dd565e2b..dfddebf5c1 100644 --- a/meta-facebook/yv35-rf/src/platform/plat_def.h +++ b/meta-facebook/yv35-rf/src/platform/plat_def.h @@ -1,4 +1,6 @@ #ifndef PLAT_DEF_H #define PLAT_DEF_H +#define BMC_USB_PORT "CDC_ACM_0" + #endif From 5d03ded237e91fdbb1f348dda0653b63a18a3d78 Mon Sep 17 00:00:00 2001 From: Scron Chang Date: Tue, 23 Aug 2022 18:54:58 +0800 Subject: [PATCH 2/4] fby3.5: rf: Impl CXL FW update Implement CXL conttroller FW update to RF BIC. The image to update is 32MB. The RF BIC checks the standby power, P1V8_ASIC, and the direction of the SPI switch and then writes data. Tested: Write different images for 20 times, and they are all successful. Signed-off-by: Scron Chang --- common/lib/util_spi.c | 23 +------ common/lib/util_spi.h | 4 +- common/service/ipmi/oem_1s_handler.c | 22 ++---- meta-facebook/yv35-rf/src/lib/plat_spi.c | 85 +++++++++++++++++++++--- 4 files changed, 87 insertions(+), 47 deletions(-) diff --git a/common/lib/util_spi.c b/common/lib/util_spi.c index a7095d29ca..2b8deee1a6 100644 --- a/common/lib/util_spi.c +++ b/common/lib/util_spi.c @@ -351,18 +351,9 @@ uint8_t fw_update(uint32_t offset, uint16_t msg_len, uint8_t *msg_buf, bool sect return FWUPDATE_SUCCESS; } -uint8_t fw_update_cxl(uint8_t flash_position) +__weak uint8_t fw_update_cxl(uint32_t offset, uint16_t msg_len, uint8_t *msg_buf, bool sector_end) { - int ret = 0; - const struct device *flash_dev; - - flash_dev = device_get_binding(flash_device[flash_position]); - ret = spi_nor_re_init(flash_dev); - if (ret != 0) { - return FWUPDATE_UPDATE_FAIL; - } - //TODO: do real update until know CXL fw update format and progress - return FWUPDATE_SUCCESS; + return FWUPDATE_NOT_SUPPORT; } __weak int pal_get_bios_flash_position() @@ -374,13 +365,3 @@ __weak bool pal_switch_bios_spi_mux(int gpio_status) { return true; } - -__weak int pal_get_cxl_flash_position() -{ - return -1; -} - -__weak bool pal_switch_cxl_spi_mux() -{ - return false; -} diff --git a/common/lib/util_spi.h b/common/lib/util_spi.h index 3174feab34..8efc3a70ed 100644 --- a/common/lib/util_spi.h +++ b/common/lib/util_spi.h @@ -26,14 +26,13 @@ enum DEVICE_POSITIONS { uint8_t fw_update(uint32_t offset, uint16_t msg_len, uint8_t *msg_buf, bool sector_end, uint8_t flash_position); -uint8_t fw_update_cxl(uint8_t flash_position); +uint8_t fw_update_cxl(uint32_t offset, uint16_t msg_len, uint8_t *msg_buf, bool sector_end); uint8_t get_fw_sha256(uint8_t *msg_buf, uint32_t offset, uint32_t length, uint8_t flash_position); int pal_get_bios_flash_position(); bool pal_switch_bios_spi_mux(int gpio_status); int pal_get_cxl_flash_position(); -bool pal_switch_cxl_spi_mux(); enum FIRMWARE_UPDATE_RETURN_CODE { FWUPDATE_SUCCESS, @@ -42,6 +41,7 @@ enum FIRMWARE_UPDATE_RETURN_CODE { FWUPDATE_REPEATED_UPDATED, FWUPDATE_UPDATE_FAIL, FWUPDATE_ERROR_OFFSET, + FWUPDATE_NOT_SUPPORT, }; #if DT_NODE_HAS_STATUS(DT_PATH(soc, spi_7e620000), okay) diff --git a/common/service/ipmi/oem_1s_handler.c b/common/service/ipmi/oem_1s_handler.c index c64cf91051..e016dc4c73 100644 --- a/common/service/ipmi/oem_1s_handler.c +++ b/common/service/ipmi/oem_1s_handler.c @@ -231,20 +231,9 @@ __weak void OEM_1S_FW_UPDATE(ipmi_msg *msg) } else if ((target == CPLD_UPDATE) || (target == (CPLD_UPDATE | IS_SECTOR_END_MASK))) { status = cpld_altera_max10_fw_update(offset, length, &msg->data[7]); - } else if (target == CXL_UPDATE) { - int pos = pal_get_cxl_flash_position(); - if (pos == -1) { - msg->completion_code = CC_INVALID_PARAM; - return; - } - - bool ret = pal_switch_cxl_spi_mux(); - if (ret == false) { - msg->completion_code = CC_UNSPECIFIED_ERROR; - return; - } - - status = fw_update_cxl(pos); + } else if (target == CXL_UPDATE || (target == (CXL_UPDATE | IS_SECTOR_END_MASK))) { + status = + fw_update_cxl(offset, length, &msg->data[7], (target & IS_SECTOR_END_MASK)); } else { msg->completion_code = CC_INVALID_DATA_FIELD; @@ -272,6 +261,9 @@ __weak void OEM_1S_FW_UPDATE(ipmi_msg *msg) case FWUPDATE_ERROR_OFFSET: msg->completion_code = CC_PARAM_OUT_OF_RANGE; break; + case FWUPDATE_NOT_SUPPORT: + msg->completion_code = CC_INVALID_PARAM; + break; default: msg->completion_code = CC_UNSPECIFIED_ERROR; break; @@ -977,7 +969,7 @@ __weak void OEM_1S_CONTROL_SENSOR_POLLING(ipmi_msg *msg) // Enable or Disable sensor polling sensor_config[control_sensor_index].is_enable_polling = ((operation == DISABLE_SENSOR_POLLING) ? DISABLE_SENSOR_POLLING : - ENABLE_SENSOR_POLLING); + ENABLE_SENSOR_POLLING); msg->data[return_data_index + 1] = sensor_config[control_sensor_index].is_enable_polling; } else { diff --git a/meta-facebook/yv35-rf/src/lib/plat_spi.c b/meta-facebook/yv35-rf/src/lib/plat_spi.c index 42e69aab55..8f788f7421 100644 --- a/meta-facebook/yv35-rf/src/lib/plat_spi.c +++ b/meta-facebook/yv35-rf/src/lib/plat_spi.c @@ -1,24 +1,91 @@ +#include +#include + #include "hal_gpio.h" #include "util_spi.h" +#include "util_sys.h" #include "plat_gpio.h" -bool pal_switch_cxl_spi_mux() +#define CXL_FLASH_TO_BIC 1 +#define CXL_FLASH_TO_CXL 0 + +#define CXL_UPDATE_MAX_OFFSET 0x2000000 + +static bool switch_cxl_spi_mux(int gpio_status) { - // Switch CXL MUX selection pin to BIC - int ret = gpio_set(SPI_MASTER_SEL, GPIO_HIGH); - if (ret != 0) { + if (gpio_status != CXL_FLASH_TO_BIC && gpio_status != CXL_FLASH_TO_CXL) { + printf("[%s] Invalid argument\n", __func__); return false; } - // Enable CXL MUX - ret = gpio_set(FM_SPI_MUX_OE_CTL_N, GPIO_LOW); - if (ret != 0) { + if (gpio_set(SPI_MASTER_SEL, gpio_status)) { + printf("Fail to switch the flash to %s\n", + (gpio_status == CXL_FLASH_TO_BIC) ? "BIC" : "PIONEER"); return false; } + return true; } -int pal_get_cxl_flash_position() +static bool control_flash_power(int power_state) +{ + int control_mode = 0; + + switch (power_state) { + case POWER_OFF: + control_mode = DISABLE_POWER_MODE; + break; + case POWER_ON: + control_mode = ENABLE_POWER_MODE; + break; + default: + return false; + } + + for (int retry = 3;; retry--) { + if (gpio_get(P1V8_ASIC_PG_R) == power_state) { + return true; + } + + if (!retry) { + break; + } + + control_power_stage(control_mode, P1V8_ASIC_EN_R); + k_msleep(CHKPWR_DELAY_MSEC); + } + + printf("Fail to %s the ASIC_1V8\n", (power_state == POWER_OFF) ? "disable" : "enable"); + + return false; +} + +uint8_t fw_update_cxl(uint32_t offset, uint16_t msg_len, uint8_t *msg_buf, bool sector_end) { - return DEVSPI_SPI1_CS0; + uint8_t ret = FWUPDATE_UPDATE_FAIL; + bool last = ((offset + msg_len) == CXL_UPDATE_MAX_OFFSET); + + if (offset > CXL_UPDATE_MAX_OFFSET) { + return FWUPDATE_OVER_LENGTH; + } + + // Enable the P1V8_ASCI to power the flash + if (control_flash_power(POWER_ON) == false) { + return FWUPDATE_UPDATE_FAIL; + } + + // Set high to choose the BIC as the host + if (switch_cxl_spi_mux(CXL_FLASH_TO_BIC) == false) { + printf("Fail to switch PIONEER flash to BIC\n"); + return FWUPDATE_UPDATE_FAIL; + } + + ret = fw_update(offset, msg_len, msg_buf, sector_end, DEVSPI_SPI1_CS0); + + if (last || ret != FWUPDATE_SUCCESS) { + control_flash_power(POWER_OFF); + switch_cxl_spi_mux(CXL_FLASH_TO_CXL); + } + + return ret; } From dc48a9b14dbf6c35c638910e960770cb67329b6e Mon Sep 17 00:00:00 2001 From: Scron Chang Date: Tue, 30 Aug 2022 09:23:45 +0800 Subject: [PATCH 3/4] fby3.5: rf: Change the SPI clock to 3.125MHz In the EVT stage, RF needs this patch because of the SPI buffer limitation. It will be fixed in the DVT stage, and this patch can be reverted. Tested: The SPI reading and writing both work well. uart:~$ flash update_test spi1_cs0 0 Writing 4092 bytes to spi1_cs0 (offset: 0x00000000)... Update done. RW test pass uart:~$ flash read spi1_cs0 0 100 00000000: 7a 79 78 77 76 75 74 73 72 71 70 6f 6e 6d 6c 6b |zyxwvuts rqponmlk| 00000010: 6a 69 68 67 66 65 64 63 62 61 7a 79 78 77 76 75 |jihgfedc bazyxwvu| 00000020: 74 73 72 71 70 6f 6e 6d 6c 6b 6a 69 68 67 66 65 |tsrqponm lkjihgfe| 00000030: 64 63 62 61 7a 79 78 77 76 75 74 73 72 71 70 6f |dcbazyxw vutsrqpo| 00000040: 6e 6d 6c 6b 6a 69 68 67 66 65 64 63 62 61 7a 79 |nmlkjihg fedcbazy| 00000050: 78 77 76 75 74 73 72 71 70 6f 6e 6d 6c 6b 6a 69 |xwvutsrq ponmlkji| 00000060: 68 67 66 65 64 63 62 61 7a 79 78 77 76 75 74 73 |hgfedcba zyxwvuts| 00000070: 72 71 70 6f 6e 6d 6c 6b 6a 69 68 67 66 65 64 63 |rqponmlk jihgfedc| 00000080: 62 61 7a 79 78 77 76 75 74 73 72 71 70 6f 6e 6d |bazyxwvu tsrqponm| 00000090: 6c 6b 6a 69 68 67 66 65 64 63 62 61 7a 79 78 77 |lkjihgfe dcbazyxw| 000000A0: 76 75 74 73 72 71 70 6f 6e 6d 6c 6b 6a 69 68 67 |vutsrqpo nmlkjihg| 000000B0: 66 65 64 63 62 61 7a 79 78 77 76 75 74 73 72 71 |fedcbazy xwvutsrq| 000000C0: 70 6f 6e 6d 6c 6b 6a 69 68 67 66 65 64 63 62 61 |ponmlkji hgfedcba| 000000D0: 7a 79 78 77 76 75 74 73 72 71 70 6f 6e 6d 6c 6b |zyxwvuts rqponmlk| 000000E0: 6a 69 68 67 66 65 64 63 62 61 7a 79 78 77 76 75 |jihgfedc bazyxwvu| 000000F0: 74 73 72 71 70 6f 6e 6d 6c 6b 6a 69 68 67 66 65 |tsrqponm lkjihgfe| uart:~$ Signed-off-by: Scron Chang --- meta-facebook/yv35-rf/boards/ast1030_evb.overlay | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-facebook/yv35-rf/boards/ast1030_evb.overlay b/meta-facebook/yv35-rf/boards/ast1030_evb.overlay index 7afc918d1c..23d62028db 100644 --- a/meta-facebook/yv35-rf/boards/ast1030_evb.overlay +++ b/meta-facebook/yv35-rf/boards/ast1030_evb.overlay @@ -94,7 +94,7 @@ &spi1_cs0 { status = "okay"; spi-max-buswidth = <4>; - spi-max-frequency = <50000000>; + spi-max-frequency = <3125000>; re-init-support; }; From 8a0786d69791a30b6fbd1a01db74bb81409301c0 Mon Sep 17 00:00:00 2001 From: Scron Chang Date: Tue, 30 Aug 2022 10:54:42 +0800 Subject: [PATCH 4/4] common: util_spi: Correct the printf specifier. The run-cppcheck blocks the pull-request and shows the following error information: ``` Errors Found: common/lib/util_spi.c:279:3:%d in format string (no. 2) requires 'int' but the argument type is 'unsigned int'. ``` This patch corrects the specifier and passes the run-cppcheck. Signed-off-by: Scron Chang --- common/lib/util_spi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/common/lib/util_spi.c b/common/lib/util_spi.c index 2b8deee1a6..d4fb3b7a70 100644 --- a/common/lib/util_spi.c +++ b/common/lib/util_spi.c @@ -276,7 +276,7 @@ uint8_t fw_update(uint32_t offset, uint16_t msg_len, uint8_t *msg_buf, bool sect } if ((buf_offset + msg_len) > SECTOR_SZ_64K) { - printf("spi bus%x recv data %d over sector size %d\n", flash_position, + printf("spi bus%x recv data %u over sector size %d\n", flash_position, buf_offset + msg_len, SECTOR_SZ_64K); SAFE_FREE(txbuf); k_msleep(10);