diff --git a/README.md b/README.md index 85af2dd6a6..36dab505d7 100644 --- a/README.md +++ b/README.md @@ -113,6 +113,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d | :green_heart: | STM32H723ZG | [Nucleo H723ZG](https://www.st.com/en/evaluation-tools/nucleo-h723zg.html) | *2.4.0* | | | :green_heart: | STM32H743ZI | [Nucleo H743ZI(2)](https://www.st.com/en/evaluation-tools/nucleo-h743zi.html) | *1.5.0* | Nucleo H743ZI2 since 1.6.0 | | :green_heart: | STM32H753ZI | [Nucleo H753ZI](https://www.st.com/en/evaluation-tools/nucleo-h753zi.html) | *2.7.0* | | +| :yellow_heart: | STM32H7A3ZITxQ | [NNUCLEO-H7A3ZI-Q](https://www.st.com/en/evaluation-tools/nucleo-h7a3zi-q.html) | **2.10.0** | | | :green_heart: | STM32L496ZG | [Nucleo L496ZG](http://www.st.com/en/evaluation-tools/nucleo-l496zg.html) | *1.3.0* | | | :green_heart: | STM32L496ZG-P | [Nucleo L496ZG-P](http://www.st.com/en/evaluation-tools/nucleo-l496zg-p.html) | *1.3.0* | | | :green_heart: | STM32L4R5ZI | [Nucleo L4R5ZI](http://www.st.com/en/evaluation-tools/nucleo-l4r5zi.html) | *1.4.0* | | @@ -604,8 +605,10 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d | :green_heart: | STM32H757XI | Generic Board | *2.7.0* | | | :green_heart: | STM32H7A3VGHX
STM32H7A3VGTX | Generic Board | *2.8.0* | | | :green_heart: | STM32H7A3VIHX
STM32H7A3VITX | Generic Board | *2.8.0* | | +| :yellow_heart: | STM32H7A3ZGTxQ
STM32H7A3ZITxQ | Generic Board | **2.10.0** | | | :green_heart: | STM32H7B0VBTX | Generic Board | *2.8.0* | | | :green_heart: | STM32H7B3VIHX
STM32H7B3VITX | Generic Board | *2.8.0* | | +| :yellow_heart: | STM32H7B3ZITxQ | Generic Board | **2.10.0** | | ### Generic STM32L0 boards diff --git a/boards.txt b/boards.txt index cd03bbedae..0aee1594ac 100644 --- a/boards.txt +++ b/boards.txt @@ -273,6 +273,22 @@ Nucleo_144.menu.pnum.NUCLEO_H753ZI.build.variant_h=variant_NUCLEO_H753ZI.h Nucleo_144.menu.pnum.NUCLEO_H753ZI.openocd.target=stm32h7x Nucleo_144.menu.pnum.NUCLEO_H753ZI.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H753.svd +# NUCLEO_H7A3ZI_Q +Nucleo_144.menu.pnum.NUCLEO_H7A3ZI_Q=Nucleo H7A3ZI-Q +Nucleo_144.menu.pnum.NUCLEO_H7A3ZI_Q.node=NOD_H7A3ZIQ +Nucleo_144.menu.pnum.NUCLEO_H7A3ZI_Q.upload.maximum_size=2097152 +Nucleo_144.menu.pnum.NUCLEO_H7A3ZI_Q.upload.maximum_data_size=1048576 +Nucleo_144.menu.pnum.NUCLEO_H7A3ZI_Q.build.mcu=cortex-m7 +Nucleo_144.menu.pnum.NUCLEO_H7A3ZI_Q.build.fpu=-mfpu=fpv4-sp-d16 +Nucleo_144.menu.pnum.NUCLEO_H7A3ZI_Q.build.float-abi=-mfloat-abi=hard +Nucleo_144.menu.pnum.NUCLEO_H7A3ZI_Q.build.board=NUCLEO_H7A3ZI_Q +Nucleo_144.menu.pnum.NUCLEO_H7A3ZI_Q.build.series=STM32H7xx +Nucleo_144.menu.pnum.NUCLEO_H7A3ZI_Q.build.product_line=STM32H7A3xxQ +Nucleo_144.menu.pnum.NUCLEO_H7A3ZI_Q.build.variant=STM32H7xx/H7A3Z(G-I)TxQ_H7B3ZITxQ +Nucleo_144.menu.pnum.NUCLEO_H7A3ZI_Q.build.variant_h=variant_NUCLEO_H7A3ZI_Q.h +Nucleo_144.menu.pnum.NUCLEO_H7A3ZI_Q.openocd.target=stm32h7x +Nucleo_144.menu.pnum.NUCLEO_H7A3ZI_Q.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H7A3.svd + # NUCLEO_L496ZG board Nucleo_144.menu.pnum.NUCLEO_L496ZG=Nucleo L496ZG Nucleo_144.menu.pnum.NUCLEO_L496ZG.node=NODE_L496ZG @@ -9550,6 +9566,24 @@ GenH7.menu.pnum.GENERIC_H7A3VITX.build.product_line=STM32H7A3xx GenH7.menu.pnum.GENERIC_H7A3VITX.build.variant=STM32H7xx/H7A3V(G-I)(H-T)_H7B0VBT_H7B3VI(H-T) GenH7.menu.pnum.GENERIC_H7A3VITX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H7A3.svd +# Generic H7A3ZGTxQ +GenH7.menu.pnum.GENERIC_H7A3ZGTXQ=Generic H7A3ZGTxQ +GenH7.menu.pnum.GENERIC_H7A3ZGTXQ.upload.maximum_size=1048576 +GenH7.menu.pnum.GENERIC_H7A3ZGTXQ.upload.maximum_data_size=1048576 +GenH7.menu.pnum.GENERIC_H7A3ZGTXQ.build.board=GENERIC_H7A3ZGTXQ +GenH7.menu.pnum.GENERIC_H7A3ZGTXQ.build.product_line=STM32H7A3xxQ +GenH7.menu.pnum.GENERIC_H7A3ZGTXQ.build.variant=STM32H7xx/H7A3Z(G-I)TxQ_H7B3ZITxQ +GenH7.menu.pnum.GENERIC_H7A3ZGTXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H7A3.svd + +# Generic H7A3ZITxQ +GenH7.menu.pnum.GENERIC_H7A3ZITXQ=Generic H7A3ZITxQ +GenH7.menu.pnum.GENERIC_H7A3ZITXQ.upload.maximum_size=2097152 +GenH7.menu.pnum.GENERIC_H7A3ZITXQ.upload.maximum_data_size=1048576 +GenH7.menu.pnum.GENERIC_H7A3ZITXQ.build.board=GENERIC_H7A3ZITXQ +GenH7.menu.pnum.GENERIC_H7A3ZITXQ.build.product_line=STM32H7A3xxQ +GenH7.menu.pnum.GENERIC_H7A3ZITXQ.build.variant=STM32H7xx/H7A3Z(G-I)TxQ_H7B3ZITxQ +GenH7.menu.pnum.GENERIC_H7A3ZITXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H7A3.svd + # Generic H7B0VBTx GenH7.menu.pnum.GENERIC_H7B0VBTX=Generic H7B0VBTx GenH7.menu.pnum.GENERIC_H7B0VBTX.upload.maximum_size=131072 @@ -9577,6 +9611,15 @@ GenH7.menu.pnum.GENERIC_H7B3VITX.build.product_line=STM32H7B3xx GenH7.menu.pnum.GENERIC_H7B3VITX.build.variant=STM32H7xx/H7A3V(G-I)(H-T)_H7B0VBT_H7B3VI(H-T) GenH7.menu.pnum.GENERIC_H7B3VITX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H7B3.svd +# Generic H7B3ZITxQ +GenH7.menu.pnum.GENERIC_H7B3ZITXQ=Generic H7B3ZITxQ +GenH7.menu.pnum.GENERIC_H7B3ZITXQ.upload.maximum_size=2097152 +GenH7.menu.pnum.GENERIC_H7B3ZITXQ.upload.maximum_data_size=1048576 +GenH7.menu.pnum.GENERIC_H7B3ZITXQ.build.board=GENERIC_H7B3ZITXQ +GenH7.menu.pnum.GENERIC_H7B3ZITXQ.build.product_line=STM32H7B3xxQ +GenH7.menu.pnum.GENERIC_H7B3ZITXQ.build.variant=STM32H7xx/H7A3Z(G-I)TxQ_H7B3ZITxQ +GenH7.menu.pnum.GENERIC_H7B3ZITXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H7B3.svd + # Upload menu GenH7.menu.upload_method.swdMethod=STM32CubeProgrammer (SWD) GenH7.menu.upload_method.swdMethod.upload.protocol=swd diff --git a/cmake/boards_db.cmake b/cmake/boards_db.cmake index 2c5a97e85e..4db190a96b 100644 --- a/cmake/boards_db.cmake +++ b/cmake/boards_db.cmake @@ -79836,6 +79836,170 @@ target_compile_options(GENERIC_H7A3VITX_xusb_HSFS INTERFACE "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" ) +# GENERIC_H7A3ZGTXQ +# ----------------------------------------------------------------------------- + +set(GENERIC_H7A3ZGTXQ_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H7xx/H7A3Z(G-I)TxQ_H7B3ZITxQ") +set(GENERIC_H7A3ZGTXQ_MAXSIZE 1048576) +set(GENERIC_H7A3ZGTXQ_MAXDATASIZE 1048576) +set(GENERIC_H7A3ZGTXQ_MCU cortex-m7) +set(GENERIC_H7A3ZGTXQ_FPCONF "-") +add_library(GENERIC_H7A3ZGTXQ INTERFACE) +target_compile_options(GENERIC_H7A3ZGTXQ INTERFACE + "SHELL:-DCORE_CM7 -DSTM32H7A3xxQ " + "SHELL:" + "SHELL:" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_H7A3ZGTXQ_MCU} +) +target_compile_definitions(GENERIC_H7A3ZGTXQ INTERFACE + "STM32H7xx" + "ARDUINO_GENERIC_H7A3ZGTXQ" + "BOARD_NAME=\"GENERIC_H7A3ZGTXQ\"" + "BOARD_ID=GENERIC_H7A3ZGTXQ" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_H7A3ZGTXQ INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32H7xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ + ${GENERIC_H7A3ZGTXQ_VARIANT_PATH} +) + +target_link_options(GENERIC_H7A3ZGTXQ INTERFACE + "LINKER:--default-script=${GENERIC_H7A3ZGTXQ_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=1048576" + "LINKER:--defsym=LD_MAX_DATA_SIZE=1048576" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_H7A3ZGTXQ_MCU} +) + +add_library(GENERIC_H7A3ZGTXQ_serial_disabled INTERFACE) +target_compile_options(GENERIC_H7A3ZGTXQ_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_H7A3ZGTXQ_serial_generic INTERFACE) +target_compile_options(GENERIC_H7A3ZGTXQ_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_H7A3ZGTXQ_serial_none INTERFACE) +target_compile_options(GENERIC_H7A3ZGTXQ_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_H7A3ZGTXQ_usb_CDC INTERFACE) +target_compile_options(GENERIC_H7A3ZGTXQ_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_H7A3ZGTXQ_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_H7A3ZGTXQ_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_H7A3ZGTXQ_usb_HID INTERFACE) +target_compile_options(GENERIC_H7A3ZGTXQ_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_H7A3ZGTXQ_usb_none INTERFACE) +target_compile_options(GENERIC_H7A3ZGTXQ_usb_none INTERFACE + "SHELL:" +) +add_library(GENERIC_H7A3ZGTXQ_xusb_FS INTERFACE) +target_compile_options(GENERIC_H7A3ZGTXQ_xusb_FS INTERFACE + "SHELL:" +) +add_library(GENERIC_H7A3ZGTXQ_xusb_HS INTERFACE) +target_compile_options(GENERIC_H7A3ZGTXQ_xusb_HS INTERFACE + "SHELL:-DUSE_USB_HS" +) +add_library(GENERIC_H7A3ZGTXQ_xusb_HSFS INTERFACE) +target_compile_options(GENERIC_H7A3ZGTXQ_xusb_HSFS INTERFACE + "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" +) + +# GENERIC_H7A3ZITXQ +# ----------------------------------------------------------------------------- + +set(GENERIC_H7A3ZITXQ_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H7xx/H7A3Z(G-I)TxQ_H7B3ZITxQ") +set(GENERIC_H7A3ZITXQ_MAXSIZE 2097152) +set(GENERIC_H7A3ZITXQ_MAXDATASIZE 1048576) +set(GENERIC_H7A3ZITXQ_MCU cortex-m7) +set(GENERIC_H7A3ZITXQ_FPCONF "-") +add_library(GENERIC_H7A3ZITXQ INTERFACE) +target_compile_options(GENERIC_H7A3ZITXQ INTERFACE + "SHELL:-DCORE_CM7 -DSTM32H7A3xxQ " + "SHELL:" + "SHELL:" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_H7A3ZITXQ_MCU} +) +target_compile_definitions(GENERIC_H7A3ZITXQ INTERFACE + "STM32H7xx" + "ARDUINO_GENERIC_H7A3ZITXQ" + "BOARD_NAME=\"GENERIC_H7A3ZITXQ\"" + "BOARD_ID=GENERIC_H7A3ZITXQ" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_H7A3ZITXQ INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32H7xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ + ${GENERIC_H7A3ZITXQ_VARIANT_PATH} +) + +target_link_options(GENERIC_H7A3ZITXQ INTERFACE + "LINKER:--default-script=${GENERIC_H7A3ZITXQ_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=2097152" + "LINKER:--defsym=LD_MAX_DATA_SIZE=1048576" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_H7A3ZITXQ_MCU} +) + +add_library(GENERIC_H7A3ZITXQ_serial_disabled INTERFACE) +target_compile_options(GENERIC_H7A3ZITXQ_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_H7A3ZITXQ_serial_generic INTERFACE) +target_compile_options(GENERIC_H7A3ZITXQ_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_H7A3ZITXQ_serial_none INTERFACE) +target_compile_options(GENERIC_H7A3ZITXQ_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_H7A3ZITXQ_usb_CDC INTERFACE) +target_compile_options(GENERIC_H7A3ZITXQ_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_H7A3ZITXQ_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_H7A3ZITXQ_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_H7A3ZITXQ_usb_HID INTERFACE) +target_compile_options(GENERIC_H7A3ZITXQ_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_H7A3ZITXQ_usb_none INTERFACE) +target_compile_options(GENERIC_H7A3ZITXQ_usb_none INTERFACE + "SHELL:" +) +add_library(GENERIC_H7A3ZITXQ_xusb_FS INTERFACE) +target_compile_options(GENERIC_H7A3ZITXQ_xusb_FS INTERFACE + "SHELL:" +) +add_library(GENERIC_H7A3ZITXQ_xusb_HS INTERFACE) +target_compile_options(GENERIC_H7A3ZITXQ_xusb_HS INTERFACE + "SHELL:-DUSE_USB_HS" +) +add_library(GENERIC_H7A3ZITXQ_xusb_HSFS INTERFACE) +target_compile_options(GENERIC_H7A3ZITXQ_xusb_HSFS INTERFACE + "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" +) + # GENERIC_H7B0VBTX # ----------------------------------------------------------------------------- @@ -80082,6 +80246,88 @@ target_compile_options(GENERIC_H7B3VITX_xusb_HSFS INTERFACE "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" ) +# GENERIC_H7B3ZITXQ +# ----------------------------------------------------------------------------- + +set(GENERIC_H7B3ZITXQ_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H7xx/H7A3Z(G-I)TxQ_H7B3ZITxQ") +set(GENERIC_H7B3ZITXQ_MAXSIZE 2097152) +set(GENERIC_H7B3ZITXQ_MAXDATASIZE 1048576) +set(GENERIC_H7B3ZITXQ_MCU cortex-m7) +set(GENERIC_H7B3ZITXQ_FPCONF "-") +add_library(GENERIC_H7B3ZITXQ INTERFACE) +target_compile_options(GENERIC_H7B3ZITXQ INTERFACE + "SHELL:-DCORE_CM7 -DSTM32H7B3xxQ " + "SHELL:" + "SHELL:" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_H7B3ZITXQ_MCU} +) +target_compile_definitions(GENERIC_H7B3ZITXQ INTERFACE + "STM32H7xx" + "ARDUINO_GENERIC_H7B3ZITXQ" + "BOARD_NAME=\"GENERIC_H7B3ZITXQ\"" + "BOARD_ID=GENERIC_H7B3ZITXQ" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_H7B3ZITXQ INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32H7xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ + ${GENERIC_H7B3ZITXQ_VARIANT_PATH} +) + +target_link_options(GENERIC_H7B3ZITXQ INTERFACE + "LINKER:--default-script=${GENERIC_H7B3ZITXQ_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=2097152" + "LINKER:--defsym=LD_MAX_DATA_SIZE=1048576" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_H7B3ZITXQ_MCU} +) + +add_library(GENERIC_H7B3ZITXQ_serial_disabled INTERFACE) +target_compile_options(GENERIC_H7B3ZITXQ_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_H7B3ZITXQ_serial_generic INTERFACE) +target_compile_options(GENERIC_H7B3ZITXQ_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_H7B3ZITXQ_serial_none INTERFACE) +target_compile_options(GENERIC_H7B3ZITXQ_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_H7B3ZITXQ_usb_CDC INTERFACE) +target_compile_options(GENERIC_H7B3ZITXQ_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_H7B3ZITXQ_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_H7B3ZITXQ_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_H7B3ZITXQ_usb_HID INTERFACE) +target_compile_options(GENERIC_H7B3ZITXQ_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_H7B3ZITXQ_usb_none INTERFACE) +target_compile_options(GENERIC_H7B3ZITXQ_usb_none INTERFACE + "SHELL:" +) +add_library(GENERIC_H7B3ZITXQ_xusb_FS INTERFACE) +target_compile_options(GENERIC_H7B3ZITXQ_xusb_FS INTERFACE + "SHELL:" +) +add_library(GENERIC_H7B3ZITXQ_xusb_HS INTERFACE) +target_compile_options(GENERIC_H7B3ZITXQ_xusb_HS INTERFACE + "SHELL:-DUSE_USB_HS" +) +add_library(GENERIC_H7B3ZITXQ_xusb_HSFS INTERFACE) +target_compile_options(GENERIC_H7B3ZITXQ_xusb_HSFS INTERFACE + "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" +) + # GENERIC_L010C6TX # ----------------------------------------------------------------------------- diff --git a/variants/STM32H7xx/H7A3Z(G-I)TxQ_H7B3ZITxQ/generic_clock.c b/variants/STM32H7xx/H7A3Z(G-I)TxQ_H7B3ZITxQ/generic_clock.c index 9fd6c852a1..668f3dddf0 100644 --- a/variants/STM32H7xx/H7A3Z(G-I)TxQ_H7B3ZITxQ/generic_clock.c +++ b/variants/STM32H7xx/H7A3Z(G-I)TxQ_H7B3ZITxQ/generic_clock.c @@ -21,8 +21,86 @@ */ WEAK void SystemClock_Config(void) { - /* SystemClock_Config can be generated by STM32CubeMX */ -#warning "SystemClock_Config() is empty. Default clock at reset is used." + RCC_OscInitTypeDef RCC_OscInitStruct = {}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {}; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {}; + + /*AXI clock gating */ + RCC->CKGAENR = 0xFFFFFFFF; + + /** Supply configuration update enable + */ + HAL_PWREx_ConfigSupply(PWR_DIRECT_SMPS_SUPPLY); + + /** Configure the main internal regulator output voltage + */ + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0); + + while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} + + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_HSI; + RCC_OscInitStruct.HSIState = RCC_HSI_DIV1; + RCC_OscInitStruct.HSICalibrationValue = 64; + RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; + RCC_OscInitStruct.PLL.PLLM = 4; + RCC_OscInitStruct.PLL.PLLN = 35; + RCC_OscInitStruct.PLL.PLLP = 2; + RCC_OscInitStruct.PLL.PLLQ = 2; + RCC_OscInitStruct.PLL.PLLR = 2; + RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_3; + RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE; + RCC_OscInitStruct.PLL.PLLFRACN = 0; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + Error_Handler(); + } + + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK + | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 + | RCC_CLOCKTYPE_D3PCLK1 | RCC_CLOCKTYPE_D1PCLK1; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2; + RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2; + RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2; + RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_6) != HAL_OK) { + Error_Handler(); + } + /** Initializes the peripherals clock + */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_USB; + PeriphClkInitStruct.PLL3.PLL3M = 4; + PeriphClkInitStruct.PLL3.PLL3N = 8; + PeriphClkInitStruct.PLL3.PLL3P = 2; + PeriphClkInitStruct.PLL3.PLL3Q = 4; + PeriphClkInitStruct.PLL3.PLL3R = 2; + PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL3VCIRANGE_3; + PeriphClkInitStruct.PLL3.PLL3VCOSEL = RCC_PLL3VCOWIDE; + PeriphClkInitStruct.PLL3.PLL3FRACN = 0; + PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PLL3; + PeriphClkInitStruct.PLL2.PLL2M = 4; + PeriphClkInitStruct.PLL2.PLL2N = 10; + PeriphClkInitStruct.PLL2.PLL2P = 2; + PeriphClkInitStruct.PLL2.PLL2Q = 2; + PeriphClkInitStruct.PLL2.PLL2R = 2; + PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2VCIRANGE_3; + PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2VCOWIDE; + PeriphClkInitStruct.PLL2.PLL2FRACN = 0; + PeriphClkInitStruct.Spi123ClockSelection = RCC_SPI123CLKSOURCE_PLL2; + PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; + + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { + Error_Handler(); + } } #endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32H7xx/H7A3Z(G-I)TxQ_H7B3ZITxQ/ldscript.ld b/variants/STM32H7xx/H7A3Z(G-I)TxQ_H7B3ZITxQ/ldscript.ld new file mode 100644 index 0000000000..c1f8244ffa --- /dev/null +++ b/variants/STM32H7xx/H7A3Z(G-I)TxQ_H7B3ZITxQ/ldscript.ld @@ -0,0 +1,179 @@ +/* +****************************************************************************** +** +** File : LinkerScript.ld +** +** Author : STM32CubeIDE +** +** Abstract : Linker script for STM32H7 series +** 2048Kbytes FLASH and 1376Kbytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +***************************************************************************** +** @attention +** +** Copyright (c) 2024 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +**************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ + ITCMRAM (xrw) : ORIGIN = 0x00000000, LENGTH = 64K + FLASH (rx) : ORIGIN = 0x08000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET + DTCMRAM1 (xrw) : ORIGIN = 0x20000000, LENGTH = 64K + DTCMRAM2 (xrw) : ORIGIN = 0x20010000, LENGTH = 64K + RAM (xrw) : ORIGIN = 0x24000000, LENGTH = LD_MAX_DATA_SIZE + RAM_CD (xrw) : ORIGIN = 0x30000000, LENGTH = 128K + RAM_SRD (xrw) : ORIGIN = 0x38000000, LENGTH = 32K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } >FLASH + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/variants/STM32H7xx/H7A3Z(G-I)TxQ_H7B3ZITxQ/variant_NUCLEO_H7A3ZI_Q.cpp b/variants/STM32H7xx/H7A3Z(G-I)TxQ_H7B3ZITxQ/variant_NUCLEO_H7A3ZI_Q.cpp new file mode 100644 index 0000000000..91bc1e4ca8 --- /dev/null +++ b/variants/STM32H7xx/H7A3Z(G-I)TxQ_H7B3ZITxQ/variant_NUCLEO_H7A3ZI_Q.cpp @@ -0,0 +1,235 @@ +/* + ******************************************************************************* + * Copyright (c) 2022, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_NUCLEO_H7A3ZI_Q) +#include "pins_arduino.h" + +// Pin number +const PinName digitalPin[] = { + PB_7, + PB_6, + PG_14, + PE_13, + PE_14, + PE_11, + PA_8, + PG_12, + PG_9, + PD_15, + PD_14, + PA_7, + PA_6, + PA_5, + PB_9, + PB_8, + PC_6, + PB_15, + PB_13, + PB_12, + PA_15, + PC_7, + PB_5, + PB_3, + PA_4, + PB_4, + PG_6, + PB_2, + PD_13, + PD_12, + PD_11, + PE_2, + PA_0, + PB_0, + PE_0, + PB_11, + PB_10, + PE_15, + PE_6, + PE_12, + PE_10, + PE_7, + PE_8, + PC_8, + PC_9, + PC_10, + PC_11, + PC_12, + PD_2, + PG_10, + PG_8, + PD_7, + PD_6, + PD_5, + PD_4, + PD_3, + PE_2, + PE_4, + PE_5, + PE_6, + PE_3, + PF_8, + PF_7, + PF_9, + PD_10, + PB_14, + PD_1, + PD_0, + PF_15, + PF_14, + PB_5, + PE_9, + PB_2, + PA_3, + PC_0, + PC_3_C, + PB_1, + PC_2_C, + PF_11, + PC_1, + PC_5, + PA_2, + PA_1, + PA_9, + PA_10, + PA_11, + PA_12, + PA_13, + PA_14, + PC_4, + PC_13, + PC_14, + PC_15, + PD_8, + PD_9, + PE_1, + PF_6, + PF_10, + PG_7, + PG_11, + PG_13, + PH_0, + PH_1 +}; + +// Analog (Ax) pin number array +const uint32_t analogInputPin[] = { + 73, // A0 + 74, // A1 + 75, // A2 + 76, // A3 + 77, // A4 + 78, // A5 + 79, // A6 + 80, // A7 + 81, // A8 + 82, // A9 + 89, // A10 + 11, // A11 + 12, // A12 + 13, // A13 + 24, // A14 + 32, // A15 + 33, // A16 + 69 // A17 +}; + +// ---------------------------------------------------------------------------- + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {}; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {}; + + /*AXI clock gating */ + RCC->CKGAENR = 0xFFFFFFFF; + + /** Supply configuration update enable + */ + HAL_PWREx_ConfigSupply(PWR_DIRECT_SMPS_SUPPLY); + + /** Configure the main internal regulator output voltage + */ + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0); + + while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} + + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; + RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PLLM = 1; + RCC_OscInitStruct.PLL.PLLN = 70; + RCC_OscInitStruct.PLL.PLLP = 2; + RCC_OscInitStruct.PLL.PLLQ = 4; + RCC_OscInitStruct.PLL.PLLR = 2; + RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_3; + RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE; + RCC_OscInitStruct.PLL.PLLFRACN = 0; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + Error_Handler(); + } + + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK + | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 + | RCC_CLOCKTYPE_D3PCLK1 | RCC_CLOCKTYPE_D1PCLK1; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2; + RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2; + RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2; + RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_6) != HAL_OK) { + Error_Handler(); + } + + /** Initializes the peripherals clock + */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_USB; + PeriphClkInitStruct.PLL3.PLL3M = 1; + PeriphClkInitStruct.PLL3.PLL3N = 24; + PeriphClkInitStruct.PLL3.PLL3P = 2; + PeriphClkInitStruct.PLL3.PLL3Q = 6; + PeriphClkInitStruct.PLL3.PLL3R = 2; + PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL3VCIRANGE_3; + PeriphClkInitStruct.PLL3.PLL3VCOSEL = RCC_PLL3VCOWIDE; + PeriphClkInitStruct.PLL3.PLL3FRACN = 0; + PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PLL3; + PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; + + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { + Error_Handler(); + } + +} + +#ifdef __cplusplus +} +#endif +#endif /* ARDUINO_H7A3ZI_Q */ diff --git a/variants/STM32H7xx/H7A3Z(G-I)TxQ_H7B3ZITxQ/variant_NUCLEO_H7A3ZI_Q.h b/variants/STM32H7xx/H7A3Z(G-I)TxQ_H7B3ZITxQ/variant_NUCLEO_H7A3ZI_Q.h new file mode 100644 index 0000000000..e7cb370ae4 --- /dev/null +++ b/variants/STM32H7xx/H7A3Z(G-I)TxQ_H7B3ZITxQ/variant_NUCLEO_H7A3ZI_Q.h @@ -0,0 +1,269 @@ +/* + ******************************************************************************* + * Copyright (c) 2022, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +// See UM2408, Figure 18. NUCLEO-H7A3ZI-Q extension connectors +// CN10 right Arduino Uno connector +#define PB7 0 +#define PB6 1 +#define PG14 2 +#define PE13 3 +#define PE14 4 +#define PE11 5 +#define PA8 6 +#define PG12 7 +// CN7 right Arduino Uno connector +#define PG9 8 +#define PD15 9 +#define PD14 10 +#define PA7 PIN_A11 +#define PA6 PIN_A12 +#define PA5 PIN_A13 +#define PB9 14 +#define PB8 15 +// CN7 left +#define PC6 16 +#define PB15 17 +#define PB13 18 +#define PB12 19 +#define PA15 20 +#define PC7 21 +#define PB5 22 +#define PB3 23 +#define PA4 PIN_A14 +#define PB4 25 +// CN10 Left +#define PG6 26 +#define PB2 27 +#define PD13 28 +#define PD12 29 +#define PD11 30 +#define PE2 31 +#define PA0 PIN_A15 +#define PB0 PIN_A16 +#define PE0 34 +// CN10 Right +#define PB11 35 +#define PB10 36 +#define PE15 37 +#define PE6 38 +#define PE12 39 +#define PE10 40 +#define PE7 41 +#define PE8 42 +// CN8 Left +#define PC8 43 +#define PC9 44 +#define PC10 45 +#define PC11 46 +#define PC12 47 +#define PD2 48 +#define PG10 49 +#define PG8 50 +// CN9 Left +#define PD7 51 +#define PD6 52 +#define PD5 53 +#define PD4 54 +#define PD3 55 +// 56 is PE2 (31) +#define PE4 57 +#define PE5 58 +// 59 is PE6 (38) +#define PE3 60 +#define PF8 61 +#define PF7 62 +#define PF9 63 +#define PD10 64 +// CN9 Right +#define PB14 65 +#define PD1 66 +#define PD0 67 +#define PF15 68 +#define PF14 PIN_A17 +// 70 is PB5 (22) +#define PE9 71 +// 72 is PB2 (27) +#define PA3 PIN_A0 +#define PC0 PIN_A1 +#define PC3_C PIN_A2 +#define PB1 PIN_A3 +#define PC2_C PIN_A4 +#define PF11 PIN_A5 +// CN7 left (analog part) +#define PC1 PIN_A6 +#define PC5 PIN_A7 +#define PA2 PIN_A8 +// ST morpho +#define PA1 PIN_A9 +#define PA9 83 +#define PA10 84 +#define PA11 85 +#define PA12 86 +#define PA13 87 +#define PA14 88 +#define PC4 PIN_A10 +#define PC13 90 +#define PC14 91 +#define PC15 92 +#define PD8 93 +#define PD9 94 +#define PE1 95 +#define PF6 96 +#define PF10 97 +#define PG7 98 +#define PG11 99 +#define PG13 100 +#define PH0 101 +#define PH1 102 + +// Alternate pins number +#define PA0_ALT1 (PA0 | ALT1) +#define PA1_ALT1 (PA1 | ALT1) +#define PA1_ALT2 (PA1 | ALT2) +#define PA2_ALT1 (PA2 | ALT1) +#define PA2_ALT2 (PA2 | ALT2) +#define PA3_ALT1 (PA3 | ALT1) +#define PA3_ALT2 (PA3 | ALT2) +#define PA4_ALT1 (PA4 | ALT1) +#define PA4_ALT2 (PA4 | ALT2) +#define PA5_ALT1 (PA5 | ALT1) +#define PA6_ALT1 (PA6 | ALT1) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA7_ALT3 (PA7 | ALT3) +#define PA9_ALT1 (PA9 | ALT1) +#define PA10_ALT1 (PA10 | ALT1) +#define PA11_ALT1 (PA11 | ALT1) +#define PA12_ALT1 (PA12 | ALT1) +#define PA15_ALT1 (PA15 | ALT1) +#define PA15_ALT2 (PA15 | ALT2) +#define PB0_ALT1 (PB0 | ALT1) +#define PB0_ALT2 (PB0 | ALT2) +#define PB1_ALT1 (PB1 | ALT1) +#define PB1_ALT2 (PB1 | ALT2) +#define PB3_ALT1 (PB3 | ALT1) +#define PB3_ALT2 (PB3 | ALT2) +#define PB4_ALT1 (PB4 | ALT1) +#define PB4_ALT2 (PB4 | ALT2) +#define PB5_ALT1 (PB5 | ALT1) +#define PB5_ALT2 (PB5 | ALT2) +#define PB6_ALT1 (PB6 | ALT1) +#define PB6_ALT2 (PB6 | ALT2) +#define PB7_ALT1 (PB7 | ALT1) +#define PB8_ALT1 (PB8 | ALT1) +#define PB9_ALT1 (PB9 | ALT1) +#define PB14_ALT1 (PB14 | ALT1) +#define PB14_ALT2 (PB14 | ALT2) +#define PB15_ALT1 (PB15 | ALT1) +#define PB15_ALT2 (PB15 | ALT2) +#define PC0_ALT1 (PC0 | ALT1) +#define PC1_ALT1 (PC1 | ALT1) +#define PC4_ALT1 (PC4 | ALT1) +#define PC5_ALT1 (PC5 | ALT1) +#define PC6_ALT1 (PC6 | ALT1) +#define PC7_ALT1 (PC7 | ALT1) +#define PC8_ALT1 (PC8 | ALT1) +#define PC9_ALT1 (PC9 | ALT1) +#define PC10_ALT1 (PC10 | ALT1) +#define PC11_ALT1 (PC11 | ALT1) +#define PF8_ALT1 (PF8 | ALT1) +#define PF9_ALT1 (PF9 | ALT1) +#define PG13_ALT1 (PG13 | ALT1) + +#define NUM_DIGITAL_PINS 103 +#define NUM_DUALPAD_PINS 2 +#define NUM_ANALOG_INPUTS 18 + +// On-board LED pin number +#define LED_GREEN PB0 // LD1 +#define LED_YELLOW PE1 // LD2 +#define LED_RED PB14 // LD3 +#ifndef LED_BUILTIN + #define LED_BUILTIN LED_GREEN +#endif + + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PC13 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM6 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM7 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 3 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PD9 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PD8 +#endif + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define HAL_DAC_MODULE_ENABLED +#endif +#if !defined(HAL_OSPI_MODULE_DISABLED) + #define HAL_OSPI_MODULE_ENABLED +#endif +#if !defined(HAL_SD_MODULE_DISABLED) + #define HAL_SD_MODULE_ENABLED +#endif + +// HSE default value is 25MHz in HAL +// By default HSE_BYPASS is based on HSI/2 from STLink +#ifndef HSE_BYPASS_NOT_USED + #define HSE_VALUE 8000000 +#endif + +#define USE_PWR_DIRECT_SMPS_SUPPLY + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #define SERIAL_PORT_MONITOR Serial + #define SERIAL_PORT_HARDWARE Serial +#endif