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<title>fritzm.github.io - PDP-11/45: Diagnostics XI - FP11 FPU, cont.</title>
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<h1>PDP-11/45: Diagnostics XI - FP11 FPU, cont.</h1>
Sun 23 October 2016
by <a class="url fn" href="https://fritzm.github.io/author/fritz-mueller.html">Fritz Mueller</a>
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<div><p>Wrote some small test programs to investigate FP add/subtract. Turns out that single-precision add/subtract
works fine, but double-precision results come back with some erroneous bits set in the fraction.
Here's the test code I ended up using for troublshooting -- when executed on my machine, bits 24 and 25
end up incorrectly set in the result at D3:</p>
<table class="highlighttable"><tr><td class="linenos"><div class="linenodiv"><pre> 1
2
3
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17</pre></div></td><td class="code"><div class="highlight"><pre><span></span> <span class="nt">000000</span> <span class="nt">AC0</span><span class="o">=%</span><span class="nt">0</span>
<span class="nt">000001</span> <span class="nt">AC1</span><span class="o">=%</span><span class="nt">1</span>
<span class="nt">000000</span> <span class="p">.</span><span class="nc">ASECT</span>
<span class="nt">001000</span> <span class="o">.=</span><span class="nt">1000</span>
<span class="nt">001000</span> <span class="nt">170011</span> <span class="nt">START</span><span class="o">:</span> <span class="nt">SETD</span> <span class="o">;</span><span class="nt">SET</span> <span class="nt">DOUBLE</span> <span class="nt">PRECISION</span> <span class="nt">MODE</span>
<span class="nt">001002</span> <span class="nt">172467</span> <span class="nt">000014</span> <span class="nt">LDD</span> <span class="nt">D1</span><span class="o">,</span><span class="nt">AC0</span> <span class="o">;</span><span class="nt">FETCH</span> <span class="nt">FIRST</span> <span class="nt">ADDEND</span> <span class="nt">FROM</span> <span class="nt">D1</span>
<span class="nt">001006</span> <span class="nt">172567</span> <span class="nt">000020</span> <span class="nt">LDD</span> <span class="nt">D2</span><span class="o">,</span><span class="nt">AC1</span> <span class="o">;</span><span class="nt">FETCH</span> <span class="nt">SECOND</span> <span class="nt">ADDEND</span> <span class="nt">FROM</span> <span class="nt">D2</span>
<span class="nt">001012</span> <span class="nt">172100</span> <span class="nt">ADDD</span> <span class="nt">AC0</span><span class="o">,</span><span class="nt">AC1</span> <span class="o">;</span><span class="nt">ADD</span> <span class="nt">THEM</span> <span class="o">(</span><span class="nt">RESULT</span> <span class="nt">IN</span> <span class="nt">AC1</span><span class="o">)</span>
<span class="nt">001014</span> <span class="nt">174167</span> <span class="nt">000022</span> <span class="nt">STD</span> <span class="nt">AC1</span><span class="o">,</span><span class="nt">D3</span> <span class="o">;</span><span class="nt">STORE</span> <span class="nt">RESULT</span> <span class="nt">TO</span> <span class="nt">D3</span>
<span class="nt">001020</span> <span class="nt">000000</span> <span class="nt">HALT</span>
<span class="nt">001022</span> <span class="nt">040200</span> <span class="nt">000000</span> <span class="nt">000000</span> <span class="nt">D1</span><span class="o">:</span> <span class="p">.</span><span class="nc">WORD</span> <span class="nt">040000</span><span class="o">,</span><span class="nt">000000</span><span class="o">,</span><span class="nt">000000</span><span class="o">,</span><span class="nt">000000</span> <span class="o">;</span><span class="nt">0</span><span class="p">.</span><span class="nc">5</span>
<span class="nt">001030</span> <span class="nt">000000</span>
<span class="nt">001032</span> <span class="nt">040200</span> <span class="nt">000000</span> <span class="nt">000000</span> <span class="nt">D2</span><span class="o">:</span> <span class="p">.</span><span class="nc">WORD</span> <span class="nt">040000</span><span class="o">,</span><span class="nt">000000</span><span class="o">,</span><span class="nt">000000</span><span class="o">,</span><span class="nt">000000</span> <span class="o">;</span><span class="nt">0</span><span class="p">.</span><span class="nc">5</span>
<span class="nt">001040</span> <span class="nt">000000</span>
<span class="nt">001042</span> <span class="nt">000000</span> <span class="nt">000000</span> <span class="nt">000000</span> <span class="nt">D3</span><span class="o">:</span> <span class="p">.</span><span class="nc">WORD</span> <span class="nt">000000</span><span class="o">,</span><span class="nt">000000</span><span class="o">,</span><span class="nt">000000</span><span class="o">,</span><span class="nt">000000</span>
<span class="nt">001050</span> <span class="nt">000000</span>
<span class="nt">001000</span> <span class="p">.</span><span class="nc">END</span> <span class="nt">START</span>
</pre></div>
</td></tr></table>
<p>So, the usual procedure: KM11 in the floating point slot, and FRL (where these bits are handled) out on
extenders. First step is to verify the microcode sequencing with the KM11 and front panel, and it looks good.
In particular, the FPU is sequencing through states ADD.04 and ADD.06 per expectation for double-precision,
branching correctly for non-zero operands, and taking the equal exponents branch through ADD.24 (refer to
page FLOWS 8 of the FP11 engineering drawings).</p>
<p>Next, stopped in state ADD.38, where the fraction addition occurs, and scanned the inputs and outputs of
all the 74181 bitslice ALUs with a logic probe. Bit 28 of the A input to the FALU (E16 pin 2, refer to page
FRLJ of the FP11 engineering drawings) is incorrectly set. This is arriving via the AR register.</p>
<p>The value in the AR register is originally fetched from the register scratchpad, then flows through QR, BR,
and the FALU during microstates ADD.04, ADD.06, and ADD.02. Some more stepping and logic probe work showed
that the fraction values are correct along these paths through these states. So it looks like AR itself
may be at fault.</p>
<p>Set up the logic analyzer on E15, which is a 74194 shift-register that holds bits 28-31 of AR. It looks
like it is indeed faulty:</p>
<p><img src='/images/pdp11/bad-ar.jpg'/></p>
<p>Here we can see what should be a broadside load: positive CLK edge, S0 and S1 both asserted, and inputs of
all zeros. But the output sticks brokenly at 8. Pulled this shift register, soldered in a socket, and put
a replacement and a couple of spares on order. All for now, until the parts arrive.</p></div>
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