mspm0l134x.mmap

0x40004000 A PERIPHERAL ADC0
0x40004400 B  REGISTER FSUB_0 (rw): Subscriber Configuration Register.
0x40004400 C   FIELD 00w02 FSUB_0_CHANID: 0 = disconnected. 1-15 = connected to channelID = CHANID.
0x40004444 B  REGISTER FPUB_1 (rw): Publisher Configuration Register.
0x40004444 C   FIELD 00w02 FPUB_1_CHANID: 0 = disconnected. 1-15 = connected to channelID = CHANID.
0x40004800 B  REGISTER PWREN (rw): Power enable
0x40004800 C   FIELD 00w01 PWREN_ENABLE (rw): Enable the power
0x40004800 C   FIELD 24w08 PWREN_KEY (wo): KEY to allow Power State Change
0x40004804 B  REGISTER RSTCTL (wo): Reset Control
0x40004804 C   FIELD 00w01 RSTCTL_RESETASSERT (wo): Assert reset to the peripheral
0x40004804 C   FIELD 01w01 RSTCTL_RESETSTKYCLR (wo): Clear the RESETSTKY bit in the STAT register
0x40004804 C   FIELD 24w08 RSTCTL_KEY (wo): Unlock key
0x40004808 B  REGISTER CLKCFG (rw): ADC clock configuration Register
0x40004808 C   FIELD 00w02 CLKCFG_SAMPCLK: ADC sample clock source selection.
0x40004808 C   FIELD 04w01 CLKCFG_CCONRUN: CCONRUN: Forces SYSOSC to run at base frequency when device is in RUN mode which can be used as ADC sample or conversion clock source.
0x40004808 C   FIELD 05w01 CLKCFG_CCONSTOP: CCONSTOP: Forces SYSOSC to run at base frequency when device is in STOP mode which can be used as ADC sample or conversion clock source.
0x40004808 C   FIELD 24w08 CLKCFG_KEY (wo): Unlock key
0x40004814 B  REGISTER STAT (ro): Status Register
0x40004814 C   FIELD 16w01 STAT_RESETSTKY (ro): This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register
0x40005020 B  REGISTER INT_EVENT0_IIDX (ro): Interrupt index
0x40005020 C   FIELD 00w10 INT_EVENT0_IIDX_STAT (ro): Interrupt index status
0x40005028 B  REGISTER INT_EVENT0_IMASK (rw): Interrupt mask
0x40005028 C   FIELD 00w01 INT_EVENT0_IMASK_OVIFG: Raw interrupt flag for MEMRESx overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
0x40005028 C   FIELD 01w01 INT_EVENT0_IMASK_TOVIFG: Raw interrupt flag for sequence conversion timeout overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
0x40005028 C   FIELD 02w01 INT_EVENT0_IMASK_HIGHIFG: Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
0x40005028 C   FIELD 03w01 INT_EVENT0_IMASK_LOWIFG: Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
0x40005028 C   FIELD 04w01 INT_EVENT0_IMASK_INIFG: Mask INIFG in MIS_EX register.
0x40005028 C   FIELD 05w01 INT_EVENT0_IMASK_DMADONE: Raw interrupt flag for DMADONE. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
0x40005028 C   FIELD 06w01 INT_EVENT0_IMASK_UVIFG: Raw interrupt flag for MEMRESx underflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR is set to 1.
0x40005028 C   FIELD 08w01 INT_EVENT0_IMASK_MEMRESIFG0: Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1
0x40005028 C   FIELD 09w01 INT_EVENT0_IMASK_MEMRESIFG1: Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. Reading MEMRES1 register will clear this bit, or when the corresponding bit in ICLR is set to 1
0x40005028 C   FIELD 10w01 INT_EVENT0_IMASK_MEMRESIFG2: Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. Reading MEMRES2 register will clear this bit, or when the corresponding bit in ICLR is set to 1
0x40005028 C   FIELD 11w01 INT_EVENT0_IMASK_MEMRESIFG3: Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. Reading MEMRES3 register will clear this bit, or when the corresponding bit in ICLR is set to 1
0x40005030 B  REGISTER INT_EVENT0_RIS (ro): Raw interrupt status
0x40005030 C   FIELD 00w01 INT_EVENT0_RIS_OVIFG: Raw interrupt flag for MEMRESx overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
0x40005030 C   FIELD 01w01 INT_EVENT0_RIS_TOVIFG: Raw interrupt flag for sequence conversion trigger overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
0x40005030 C   FIELD 02w01 INT_EVENT0_RIS_HIGHIFG: Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
0x40005030 C   FIELD 03w01 INT_EVENT0_RIS_LOWIFG: Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
0x40005030 C   FIELD 04w01 INT_EVENT0_RIS_INIFG: Mask INIFG in MIS_EX register.
0x40005030 C   FIELD 05w01 INT_EVENT0_RIS_DMADONE: Raw interrupt flag for DMADONE. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
0x40005030 C   FIELD 06w01 INT_EVENT0_RIS_UVIFG: Raw interrupt flag for MEMRESx underflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR is set to 1.
0x40005030 C   FIELD 08w01 INT_EVENT0_RIS_MEMRESIFG0: Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1
0x40005030 C   FIELD 09w01 INT_EVENT0_RIS_MEMRESIFG1: Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. Reading MEMRES1 register will clear this bit, or when the corresponding bit in ICLR is set to 1
0x40005030 C   FIELD 10w01 INT_EVENT0_RIS_MEMRESIFG2: Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. Reading MEMRES2 register will clear this bit, or when the corresponding bit in ICLR is set to 1
0x40005030 C   FIELD 11w01 INT_EVENT0_RIS_MEMRESIFG3: Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. Reading MEMRES3 register will clear this bit, or when the corresponding bit in ICLR is set to 1
0x40005038 B  REGISTER INT_EVENT0_MIS (ro): Masked interrupt status
0x40005038 C   FIELD 00w01 INT_EVENT0_MIS_OVIFG: Raw interrupt flag for MEMRESx overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
0x40005038 C   FIELD 01w01 INT_EVENT0_MIS_TOVIFG: Raw interrupt flag for sequence conversion timeout overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
0x40005038 C   FIELD 02w01 INT_EVENT0_MIS_HIGHIFG: Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
0x40005038 C   FIELD 03w01 INT_EVENT0_MIS_LOWIFG: Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
0x40005038 C   FIELD 04w01 INT_EVENT0_MIS_INIFG: Mask INIFG in MIS_EX register.
0x40005038 C   FIELD 05w01 INT_EVENT0_MIS_DMADONE: Raw interrupt flag for DMADONE. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
0x40005038 C   FIELD 06w01 INT_EVENT0_MIS_UVIFG: Raw interrupt flag for MEMRESx underflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR is set to 1.
0x40005038 C   FIELD 08w01 INT_EVENT0_MIS_MEMRESIFG0: Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1
0x40005038 C   FIELD 09w01 INT_EVENT0_MIS_MEMRESIFG1: Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. Reading MEMRES1 register will clear this bit, or when the corresponding bit in ICLR is set to 1
0x40005038 C   FIELD 10w01 INT_EVENT0_MIS_MEMRESIFG2: Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. Reading MEMRES2 register will clear this bit, or when the corresponding bit in ICLR is set to 1
0x40005038 C   FIELD 11w01 INT_EVENT0_MIS_MEMRESIFG3: Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. Reading MEMRES3 register will clear this bit, or when the corresponding bit in ICLR is set to 1
0x40005040 B  REGISTER INT_EVENT0_ISET (wo): Interrupt set
0x40005040 C   FIELD 00w01 INT_EVENT0_ISET_OVIFG: Raw interrupt flag for MEMRESx overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
0x40005040 C   FIELD 01w01 INT_EVENT0_ISET_TOVIFG: Raw interrupt flag for sequence conversion timeout overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
0x40005040 C   FIELD 02w01 INT_EVENT0_ISET_HIGHIFG: Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
0x40005040 C   FIELD 03w01 INT_EVENT0_ISET_LOWIFG: Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
0x40005040 C   FIELD 04w01 INT_EVENT0_ISET_INIFG: Mask INIFG in MIS_EX register.
0x40005040 C   FIELD 05w01 INT_EVENT0_ISET_DMADONE: Raw interrupt flag for DMADONE. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
0x40005040 C   FIELD 06w01 INT_EVENT0_ISET_UVIFG: Raw interrupt flag for MEMRESx underflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
0x40005040 C   FIELD 08w01 INT_EVENT0_ISET_MEMRESIFG0: Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1
0x40005040 C   FIELD 09w01 INT_EVENT0_ISET_MEMRESIFG1: Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. Reading MEMRES1 register will clear this bit, or when the corresponding bit in ICLR is set to 1
0x40005040 C   FIELD 10w01 INT_EVENT0_ISET_MEMRESIFG2: Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. Reading MEMRES2 register will clear this bit, or when the corresponding bit in ICLR is set to 1
0x40005040 C   FIELD 11w01 INT_EVENT0_ISET_MEMRESIFG3: Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. Reading MEMRES3 register will clear this bit, or when the corresponding bit in ICLR is set to 1
0x40005048 B  REGISTER INT_EVENT0_ICLR (wo): Interrupt clear
0x40005048 C   FIELD 00w01 INT_EVENT0_ICLR_OVIFG: Raw interrupt flag for MEMRESx overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
0x40005048 C   FIELD 01w01 INT_EVENT0_ICLR_TOVIFG: Raw interrupt flag for sequence conversion timeout overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
0x40005048 C   FIELD 02w01 INT_EVENT0_ICLR_HIGHIFG: Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
0x40005048 C   FIELD 03w01 INT_EVENT0_ICLR_LOWIFG: Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
0x40005048 C   FIELD 04w01 INT_EVENT0_ICLR_INIFG: Mask INIFG in MIS_EX register.
0x40005048 C   FIELD 05w01 INT_EVENT0_ICLR_DMADONE: Raw interrupt flag for DMADONE. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
0x40005048 C   FIELD 06w01 INT_EVENT0_ICLR_UVIFG: Raw interrupt flag for MEMRESx underflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
0x40005048 C   FIELD 08w01 INT_EVENT0_ICLR_MEMRESIFG0: Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1
0x40005048 C   FIELD 09w01 INT_EVENT0_ICLR_MEMRESIFG1: Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. Reading MEMRES1 register will clear this bit, or when the corresponding bit in ICLR is set to 1
0x40005048 C   FIELD 10w01 INT_EVENT0_ICLR_MEMRESIFG2: Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. Reading MEMRES2 register will clear this bit, or when the corresponding bit in ICLR is set to 1
0x40005048 C   FIELD 11w01 INT_EVENT0_ICLR_MEMRESIFG3: Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. Reading MEMRES3 register will clear this bit, or when the corresponding bit in ICLR is set to 1
0x40005050 B  REGISTER INT_EVENT1_IIDX (ro): Interrupt index
0x40005050 C   FIELD 00w10 INT_EVENT1_IIDX_STAT (ro): Interrupt index status
0x40005058 B  REGISTER INT_EVENT1_IMASK (rw): Interrupt mask
0x40005058 C   FIELD 02w01 INT_EVENT1_IMASK_HIGHIFG: Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
0x40005058 C   FIELD 03w01 INT_EVENT1_IMASK_LOWIFG: Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
0x40005058 C   FIELD 04w01 INT_EVENT1_IMASK_INIFG: Mask INIFG in MIS_EX register.
0x40005058 C   FIELD 08w01 INT_EVENT1_IMASK_MEMRESIFG0: Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1
0x40005060 B  REGISTER INT_EVENT1_RIS (ro): Raw interrupt status
0x40005060 C   FIELD 02w01 INT_EVENT1_RIS_HIGHIFG: Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
0x40005060 C   FIELD 03w01 INT_EVENT1_RIS_LOWIFG: Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
0x40005060 C   FIELD 04w01 INT_EVENT1_RIS_INIFG: Mask INIFG in MIS_EX register.
0x40005060 C   FIELD 08w01 INT_EVENT1_RIS_MEMRESIFG0: Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1
0x40005068 B  REGISTER INT_EVENT1_MIS (ro): Masked interrupt status
0x40005068 C   FIELD 02w01 INT_EVENT1_MIS_HIGHIFG: Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
0x40005068 C   FIELD 03w01 INT_EVENT1_MIS_LOWIFG: Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
0x40005068 C   FIELD 04w01 INT_EVENT1_MIS_INIFG: Mask INIFG in MIS_EX register.
0x40005068 C   FIELD 08w01 INT_EVENT1_MIS_MEMRESIFG0: Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1
0x40005070 B  REGISTER INT_EVENT1_ISET (wo): Interrupt set
0x40005070 C   FIELD 02w01 INT_EVENT1_ISET_HIGHIFG: Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
0x40005070 C   FIELD 03w01 INT_EVENT1_ISET_LOWIFG: Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
0x40005070 C   FIELD 04w01 INT_EVENT1_ISET_INIFG: Mask INIFG in MIS_EX register.
0x40005070 C   FIELD 08w01 INT_EVENT1_ISET_MEMRESIFG0: Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1
0x40005078 B  REGISTER INT_EVENT1_ICLR (wo): Interrupt clear
0x40005078 C   FIELD 02w01 INT_EVENT1_ICLR_HIGHIFG: Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
0x40005078 C   FIELD 03w01 INT_EVENT1_ICLR_LOWIFG: Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
0x40005078 C   FIELD 04w01 INT_EVENT1_ICLR_INIFG: Mask INIFG in MIS_EX register.
0x40005078 C   FIELD 08w01 INT_EVENT1_ICLR_MEMRESIFG0: Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1
0x40005080 B  REGISTER INT_EVENT2_IIDX (ro): Interrupt index
0x40005080 C   FIELD 00w10 INT_EVENT2_IIDX_STAT (ro): Interrupt index status
0x40005088 B  REGISTER INT_EVENT2_IMASK (rw): Interrupt mask extension
0x40005088 C   FIELD 08w01 INT_EVENT2_IMASK_MEMRESIFG0: Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1
0x40005088 C   FIELD 09w01 INT_EVENT2_IMASK_MEMRESIFG1: Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. Reading MEMRES1 register will clear this bit, or when the corresponding bit in ICLR is set to 1
0x40005088 C   FIELD 10w01 INT_EVENT2_IMASK_MEMRESIFG2: Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. Reading MEMRES2 register will clear this bit, or when the corresponding bit in ICLR is set to 1
0x40005088 C   FIELD 11w01 INT_EVENT2_IMASK_MEMRESIFG3: Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. Reading MEMRES3 register will clear this bit, or when the corresponding bit in ICLR is set to 1
0x40005090 B  REGISTER INT_EVENT2_RIS (ro): Raw interrupt status extension
0x40005090 C   FIELD 08w01 INT_EVENT2_RIS_MEMRESIFG0: Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1
0x40005090 C   FIELD 09w01 INT_EVENT2_RIS_MEMRESIFG1: Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. Reading MEMRES1 register will clear this bit, or when the corresponding bit in ICLR is set to 1
0x40005090 C   FIELD 10w01 INT_EVENT2_RIS_MEMRESIFG2: Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. Reading MEMRES2 register will clear this bit, or when the corresponding bit in ICLR is set to 1
0x40005090 C   FIELD 11w01 INT_EVENT2_RIS_MEMRESIFG3: Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. Reading MEMRES3 register will clear this bit, or when the corresponding bit in ICLR is set to 1
0x40005098 B  REGISTER INT_EVENT2_MIS (ro): Masked interrupt status extension
0x40005098 C   FIELD 08w01 INT_EVENT2_MIS_MEMRESIFG0: Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1
0x40005098 C   FIELD 09w01 INT_EVENT2_MIS_MEMRESIFG1: Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. Reading MEMRES1 register will clear this bit, or when the corresponding bit in ICLR is set to 1
0x40005098 C   FIELD 10w01 INT_EVENT2_MIS_MEMRESIFG2: Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. Reading MEMRES2 register will clear this bit, or when the corresponding bit in ICLR is set to 1
0x40005098 C   FIELD 11w01 INT_EVENT2_MIS_MEMRESIFG3: Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. Reading MEMRES3 register will clear this bit, or when the corresponding bit in ICLR is set to 1
0x400050A0 B  REGISTER INT_EVENT2_ISET (wo): Interrupt set extension
0x400050A0 C   FIELD 08w01 INT_EVENT2_ISET_MEMRESIFG0: Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1
0x400050A0 C   FIELD 09w01 INT_EVENT2_ISET_MEMRESIFG1: Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. Reading MEMRES1 register will clear this bit, or when the corresponding bit in ICLR is set to 1
0x400050A0 C   FIELD 10w01 INT_EVENT2_ISET_MEMRESIFG2: Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. Reading MEMRES2 register will clear this bit, or when the corresponding bit in ICLR is set to 1
0x400050A0 C   FIELD 11w01 INT_EVENT2_ISET_MEMRESIFG3: Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. Reading MEMRES3 register will clear this bit, or when the corresponding bit in ICLR is set to 1
0x400050A8 B  REGISTER INT_EVENT2_ICLR (wo): Interrupt clear extension
0x400050A8 C   FIELD 08w01 INT_EVENT2_ICLR_MEMRESIFG0: Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1
0x400050A8 C   FIELD 09w01 INT_EVENT2_ICLR_MEMRESIFG1: Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. Reading MEMRES1 register will clear this bit, or when the corresponding bit in ICLR is set to 1
0x400050A8 C   FIELD 10w01 INT_EVENT2_ICLR_MEMRESIFG2: Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. Reading MEMRES2 register will clear this bit, or when the corresponding bit in ICLR is set to 1
0x400050A8 C   FIELD 11w01 INT_EVENT2_ICLR_MEMRESIFG3: Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. Reading MEMRES3 register will clear this bit, or when the corresponding bit in ICLR is set to 1
0x400050E0 B  REGISTER EVT_MODE (ro): Event Mode
0x400050E0 C   FIELD 00w02 EVT_MODE_INT0_CFG (ro): Event line mode select for event corresponding to IPSTANDARD.INT_EVENT0
0x400050E0 C   FIELD 02w02 EVT_MODE_EVT1_CFG (ro): Event line mode select for event corresponding to IPSTANDARD.INT_EVENT1
0x400050FC B  REGISTER DESC (ro): Module Description
0x400050FC C   FIELD 00w04 DESC_MINREV (ro): Minor rev of the IP
0x400050FC C   FIELD 04w04 DESC_MAJREV (ro): Major rev of the IP
0x400050FC C   FIELD 08w04 DESC_INSTNUM (ro): Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances
0x400050FC C   FIELD 12w04 DESC_FEATUREVER (ro): Feature Set for the module *instance*
0x400050FC C   FIELD 16w16 DESC_MODULEID (ro): Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness.
0x40005100 B  REGISTER CTL0 (rw): Control Register 0
0x40005100 C   FIELD 00w01 CTL0_ENC (rw): Enable conversion
0x40005100 C   FIELD 16w01 CTL0_PWRDN (rw): Power down policy
0x40005100 C   FIELD 24w03 CTL0_SCLKDIV: Sample clock divider
0x40005104 B  REGISTER CTL1 (rw): Control Register 1
0x40005104 C   FIELD 00w01 CTL1_TRIGSRC (rw): Sample trigger source
0x40005104 C   FIELD 08w01 CTL1_SC (rw): Start of conversion
0x40005104 C   FIELD 16w02 CTL1_CONSEQ (rw): Conversion sequence mode
0x40005104 C   FIELD 20w01 CTL1_SAMPMODE (rw): Sample mode. This bit selects the source of the sampling signal. MANUAL option is not valid when TRIGSRC is selected as hardware event trigger.
0x40005104 C   FIELD 24w03 CTL1_AVGN (rw): Hardware averager numerator. Selects number of conversions to accumulate for current MEMCTLx and then it is divided by AVGD. Result will be stored in MEMRESx.
0x40005104 C   FIELD 28w03 CTL1_AVGD (rw): Hardware averager denominator. The number to divide the accumulated value by (this is a shift). Note result register is maximum of 16-bits long so if not shifted appropirately result will be truncated.
0x40005108 B  REGISTER CTL2 (rw): Control Register 2
0x40005108 C   FIELD 00w01 CTL2_DF (rw): Data read-back format. Data is always stored in binary unsigned format.
0x40005108 C   FIELD 01w02 CTL2_RES (rw): Resolution. These bits define the resolutoin of ADC conversion result. Note : A value of 3 defaults to 12-bits resolution.
0x40005108 C   FIELD 08w01 CTL2_DMAEN (rw): Enable DMA trigger for data transfer. Note: DMAEN bit is cleared by hardware based on DMA done signal at the end of data transfer. Software has to re-enable DMAEN bit for ADC to generate DMA triggers.
0x40005108 C   FIELD 10w01 CTL2_FIFOEN: Enable FIFO based operation
0x40005108 C   FIELD 11w05 CTL2_SAMPCNT (rw): Number of ADC converted samples to be transferred on a DMA trigger
0x40005108 C   FIELD 16w05 CTL2_STARTADD (rw): Sequencer start address. These bits select which MEMCTLx is used for single conversion or as first MEMCTL for sequence mode. The value of STARTADD is 0x00 to 0x17, corresponding to MEMRES0 to MEMRES23.
0x40005108 C   FIELD 24w05 CTL2_ENDADD (rw): Sequence end address. These bits select which MEMCTLx is the last one for the sequence mode. The value of ENDADD is 0x00 to 0x17, corresponding to MEMRES0 to MEMRES23.
0x40005110 B  REGISTER CLKFREQ (rw): Sample Clock Frequency Range Register
0x40005110 C   FIELD 00w03 CLKFREQ_FRANGE: Frequency Range.
0x40005114 B  REGISTER SCOMP0 (rw): Sample Time Compare 0 Register
0x40005114 C   FIELD 00w10 SCOMP0_VAL (rw): Specifies the number of sample clocks. When VAL = 0 or 1, number of sample clocks = Sample clock divide value. When VAL > 1, number of sample clocks = VAL x Sample clock divide value. Note: Sample clock divide value is not the value written to SCLKDIV but the actual divide value (SCLKDIV = 2 implies divide value is 4). Example: VAL = 4, SCLKDIV = 3 implies 32 sample clock cycles.
0x40005118 B  REGISTER SCOMP1 (rw): Sample Time Compare 1 Register
0x40005118 C   FIELD 00w10 SCOMP1_VAL (rw): Specifies the number of sample clocks. When VAL = 0 or 1, number of sample clocks = Sample clock divide value. When VAL > 1, number of sample clocks = VAL x Sample clock divide value. Note: Sample clock divide value is not the value written to SCLKDIV but the actual divide value (SCLKDIV = 2 implies divide value is 4). Example: VAL = 4, SCLKDIV = 3 implies 32 sample clock cycles.
0x40005148 B  REGISTER WCLOW (rw): Window Comparator Low Threshold Register
0x40005148 C   FIELD 00w16 WCLOW_DATA (rw): If DF = 0, unsigned binary format has to be used. The value based on the resolution has to be right aligned with the MSB on the left. For 10-bits and 8-bits resolution, unused bits have to be 0s. If DF = 1, 2s-complement format has to be used. The value based on the resolution has to be left aligned with the LSB on the right. For 10-bits and 8-bits resolution, unused bits have to be 0s.
0x40005150 B  REGISTER WCHIGH (rw): Window Comparator High Threshold Register
0x40005150 C   FIELD 00w16 WCHIGH_DATA (rw): If DF = 0, unsigned binary format has to be used. The threshold value has to be right aligned, with the MSB on the left. For 10-bits and 8-bits resolution, unused bit have to be 0s. If DF = 1, 2s-complement format has to be used. The value based on the resolution has to be left aligned with the LSB on the right. For 10-bits and 8-bits resolution, unused bit have to be 0s.
0x40005180 B  REGISTER MEMCTL[0] (rw): Conversion Memory Control Register
0x40005180 C   FIELD 00w05 MEMCTL_CHANSEL (rw): Input channel select.
0x40005180 C   FIELD 08w02 MEMCTL_VRSEL (rw): Voltage reference selection. VEREFM must be connected to on-board ground when external reference option is selected. Note: Writing value 0x3 defaults to INTREF.
0x40005180 C   FIELD 12w01 MEMCTL_STIME: Selects the source of sample timer period between SCOMP0 and SCOMP1.
0x40005180 C   FIELD 16w01 MEMCTL_AVGEN (rw): Enable hardware averaging.
0x40005180 C   FIELD 20w01 MEMCTL_BCSEN (rw): Enable burn out current source.
0x40005180 C   FIELD 24w01 MEMCTL_TRIG (rw): Trigger policy. Indicates if a trigger will be needed to step to the next MEMCTL in the sequence or to perform next conversion in the case of repeat single channel conversions.
0x40005180 C   FIELD 28w01 MEMCTL_WINCOMP (rw): Enable window comparator.
0x40005184 B  REGISTER MEMCTL[1] (rw): Conversion Memory Control Register
0x40005184 C   FIELD 00w05 MEMCTL_CHANSEL (rw): Input channel select.
0x40005184 C   FIELD 08w02 MEMCTL_VRSEL (rw): Voltage reference selection. VEREFM must be connected to on-board ground when external reference option is selected. Note: Writing value 0x3 defaults to INTREF.
0x40005184 C   FIELD 12w01 MEMCTL_STIME: Selects the source of sample timer period between SCOMP0 and SCOMP1.
0x40005184 C   FIELD 16w01 MEMCTL_AVGEN (rw): Enable hardware averaging.
0x40005184 C   FIELD 20w01 MEMCTL_BCSEN (rw): Enable burn out current source.
0x40005184 C   FIELD 24w01 MEMCTL_TRIG (rw): Trigger policy. Indicates if a trigger will be needed to step to the next MEMCTL in the sequence or to perform next conversion in the case of repeat single channel conversions.
0x40005184 C   FIELD 28w01 MEMCTL_WINCOMP (rw): Enable window comparator.
0x40005188 B  REGISTER MEMCTL[2] (rw): Conversion Memory Control Register
0x40005188 C   FIELD 00w05 MEMCTL_CHANSEL (rw): Input channel select.
0x40005188 C   FIELD 08w02 MEMCTL_VRSEL (rw): Voltage reference selection. VEREFM must be connected to on-board ground when external reference option is selected. Note: Writing value 0x3 defaults to INTREF.
0x40005188 C   FIELD 12w01 MEMCTL_STIME: Selects the source of sample timer period between SCOMP0 and SCOMP1.
0x40005188 C   FIELD 16w01 MEMCTL_AVGEN (rw): Enable hardware averaging.
0x40005188 C   FIELD 20w01 MEMCTL_BCSEN (rw): Enable burn out current source.
0x40005188 C   FIELD 24w01 MEMCTL_TRIG (rw): Trigger policy. Indicates if a trigger will be needed to step to the next MEMCTL in the sequence or to perform next conversion in the case of repeat single channel conversions.
0x40005188 C   FIELD 28w01 MEMCTL_WINCOMP (rw): Enable window comparator.
0x4000518C B  REGISTER MEMCTL[3] (rw): Conversion Memory Control Register
0x4000518C C   FIELD 00w05 MEMCTL_CHANSEL (rw): Input channel select.
0x4000518C C   FIELD 08w02 MEMCTL_VRSEL (rw): Voltage reference selection. VEREFM must be connected to on-board ground when external reference option is selected. Note: Writing value 0x3 defaults to INTREF.
0x4000518C C   FIELD 12w01 MEMCTL_STIME: Selects the source of sample timer period between SCOMP0 and SCOMP1.
0x4000518C C   FIELD 16w01 MEMCTL_AVGEN (rw): Enable hardware averaging.
0x4000518C C   FIELD 20w01 MEMCTL_BCSEN (rw): Enable burn out current source.
0x4000518C C   FIELD 24w01 MEMCTL_TRIG (rw): Trigger policy. Indicates if a trigger will be needed to step to the next MEMCTL in the sequence or to perform next conversion in the case of repeat single channel conversions.
0x4000518C C   FIELD 28w01 MEMCTL_WINCOMP (rw): Enable window comparator.
0x40005340 B  REGISTER STATUS (ro): Status Register
0x40005340 C   FIELD 00w01 STATUS_BUSY (ro): Busy. This bit indicates that an active ADC sample or conversion operation is in progress.
0x40005340 C   FIELD 01w01 STATUS_REFBUFRDY: Indicates reference buffer is powered up and ready.
0x40008000 A PERIPHERAL COMP0
0x40008400 B  REGISTER FSUB_0 (rw): Subscriber Port 0
0x40008400 C   FIELD 00w02 FSUB_0_CHANID: 0 = disconnected. 1-15 = connected to channelID = CHANID.
0x40008404 B  REGISTER FSUB_1 (rw): Subscriber Port 1
0x40008404 C   FIELD 00w02 FSUB_1_CHANID: 0 = disconnected. 1-15 = connected to channelID = CHANID.
0x40008444 B  REGISTER FPUB_1 (rw): Publisher port 1
0x40008444 C   FIELD 00w02 FPUB_1_CHANID: 0 = disconnected. 1-15 = connected to channelID = CHANID.
0x40008800 B  REGISTER PWREN (rw): Power enable
0x40008800 C   FIELD 00w01 PWREN_ENABLE: Enable the power
0x40008800 C   FIELD 24w08 PWREN_KEY (wo): KEY to allow Power State Change
0x40008804 B  REGISTER RSTCTL (wo): Reset Control
0x40008804 C   FIELD 00w01 RSTCTL_RESETASSERT (wo): Assert reset to the peripheral
0x40008804 C   FIELD 01w01 RSTCTL_RESETSTKYCLR (wo): Clear the RESETSTKY bit in the STAT register
0x40008804 C   FIELD 24w08 RSTCTL_KEY (wo): Unlock key
0x40008808 B  REGISTER CLKCFG (rw): Peripheral Clock Configuration Register
0x40008808 C   FIELD 08w01 CLKCFG_BLOCKASYNC (rw): Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz
0x40008808 C   FIELD 24w08 CLKCFG_KEY (wo): KEY to Allow State Change -- 0xA9
0x40008814 B  REGISTER GPRCM_STAT (ro): Status Register
0x40008814 C   FIELD 16w01 GPRCM_STAT_RESETSTKY (ro): This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register
0x40009020 B  REGISTER IIDX (ro): Interrupt index
0x40009020 C   FIELD 00w02 IIDX_STAT (ro): Interrupt index status
0x40009028 B  REGISTER IMASK (rw): Interrupt mask
0x40009028 C   FIELD 01w01 IMASK_COMPIFG: Masks COMPIFG
0x40009028 C   FIELD 02w01 IMASK_COMPINVIFG: Masks COMPINVIFG
0x40009028 C   FIELD 03w01 IMASK_OUTRDYIFG: Masks OUTRDYIFG
0x40009030 B  REGISTER RIS (ro): Raw interrupt status
0x40009030 C   FIELD 01w01 RIS_COMPIFG: Raw interrupt status for comparator output interrupt flag. The IES bit defines the transition of the comparator output setting this bit.
0x40009030 C   FIELD 02w01 RIS_COMPINVIFG: Raw interrupt status for comparator output inverted interrupt flag. The IES bit defines the transition of the comparator output setting this bit.
0x40009030 C   FIELD 03w01 RIS_OUTRDYIFG: Raw interrupt status for comparator output ready interrupt flag. This bit is set when the comparator output is valid.
0x40009038 B  REGISTER MIS (ro): Masked interrupt status
0x40009038 C   FIELD 01w01 MIS_COMPIFG: Masked interrupt status for COMPIFG
0x40009038 C   FIELD 02w01 MIS_COMPINVIFG: Masked interrupt status for COMPINVIFG
0x40009038 C   FIELD 03w01 MIS_OUTRDYIFG: Masked interrupt status for OUTRDYIFG
0x40009040 B  REGISTER ISET (wo): Interrupt set
0x40009040 C   FIELD 01w01 ISET_COMPIFG: Sets COMPIFG in RIS register
0x40009040 C   FIELD 02w01 ISET_COMPINVIFG: Sets COMPINVIFG in RIS register
0x40009040 C   FIELD 03w01 ISET_OUTRDYIFG: Sets OUTRDYIFG in RIS register
0x40009048 B  REGISTER ICLR (wo): Interrupt clear
0x40009048 C   FIELD 01w01 ICLR_COMPIFG: Clears COMPIFG in RIS register
0x40009048 C   FIELD 02w01 ICLR_COMPINVIFG: Clears COMPINVIFG in RIS register
0x40009048 C   FIELD 03w01 ICLR_OUTRDYIFG: Clears OUTRDYIFG in RIS register
0x400090E0 B  REGISTER EVT_MODE (rw): Event Mode
0x400090E0 C   FIELD 00w02 EVT_MODE_INT0_CFG (ro): Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]
0x400090E0 C   FIELD 02w02 EVT_MODE_EVT1_CFG (ro): Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]
0x400090FC B  REGISTER DESC (ro): Module Description
0x400090FC C   FIELD 00w04 DESC_MINREV (ro): Minor rev of the IP
0x400090FC C   FIELD 04w04 DESC_MAJREV (ro): Major rev of the IP
0x400090FC C   FIELD 12w04 DESC_FEATUREVER (ro): Feature Set for the module *instance*
0x400090FC C   FIELD 16w16 DESC_MODULEID (ro): Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness.
0x40009100 B  REGISTER CTL0 (rw): Control 0
0x40009100 C   FIELD 00w03 CTL0_IPSEL (rw): Channel input selected for the positive terminal of the comparator if IPEN is set to 1.
0x40009100 C   FIELD 15w01 CTL0_IPEN (rw): Channel input enable for the positive terminal of the comparator.
0x40009100 C   FIELD 16w03 CTL0_IMSEL (rw): Channel input selected for the negative terminal of the comparator if IMEN is set to 1.
0x40009100 C   FIELD 31w01 CTL0_IMEN (rw): Channel input enable for the negative terminal of the comparator.
0x40009104 B  REGISTER CTL1 (rw): Control 1
0x40009104 C   FIELD 00w01 CTL1_ENABLE (rw): This bit turns on the comparator. When the comparator is turned off it consumes no power.
0x40009104 C   FIELD 01w01 CTL1_MODE (rw): This bit selects the comparator operating mode.
0x40009104 C   FIELD 02w01 CTL1_EXCH (rw): This bit exchanges the comparator inputs and inverts the comparator output.
0x40009104 C   FIELD 03w01 CTL1_SHORT (rw): This bit shorts the positive and negative input terminals of the comparator.
0x40009104 C   FIELD 04w01 CTL1_IES (rw): This bit selected the interrupt edge for COMPIFG and COMPINVIFG.
0x40009104 C   FIELD 05w02 CTL1_HYST (rw): These bits select the hysteresis setting of the comparator.
0x40009104 C   FIELD 07w01 CTL1_OUTPOL (rw): This bit selects the comparator output polarity.
0x40009104 C   FIELD 08w01 CTL1_FLTEN (rw): This bit enables the analog filter at comparator output.
0x40009104 C   FIELD 09w02 CTL1_FLTDLY (rw): These bits select the comparator output filter delay. See the device-specific data sheet for specific values on comparator propagation delay for different filter delay settings.
0x40009104 C   FIELD 12w01 CTL1_WINCOMPEN (rw): This bit enables window comparator operation of comparator.
0x40009108 B  REGISTER CTL2 (rw): Control 2
0x40009108 C   FIELD 00w01 CTL2_REFMODE (rw): This bit requests ULP_REF bandgap operation in static mode or sampled mode. The local reference buffer and 8-bit DAC inside comparator module are also configured accordingly. Static mode operation offers higher accuracy but consumes higher current. Sampled mode operation consumes lower current but with relaxed reference voltage accuracy. Comparator requests for reference voltage from ULP_REF only when REFLVL > 0.
0x40009108 C   FIELD 03w02 CTL2_REFSRC (rw): These bits select the reference source for the comparator.
0x40009108 C   FIELD 07w01 CTL2_REFSEL (rw): This bit selects if the selected reference voltage is applied to positive or negative terminal of the comparator.
0x40009108 C   FIELD 08w03 CTL2_BLANKSRC (rw): These bits select the blanking source for the comparator.
0x40009108 C   FIELD 16w01 CTL2_DACCTL (rw): This bit determines if the comparator output or DACSW bit controls the selection between DACCODE0 and DACCODE1.
0x40009108 C   FIELD 17w01 CTL2_DACSW (rw): This bit selects between DACCODE0 and DACCODE1 to 8-bit DAC when DACCTL bit is 1.
0x40009108 C   FIELD 24w01 CTL2_SAMPMODE (rw): Enable sampled mode of comparator.
0x4000910C B  REGISTER CTL3 (rw): Control 3
0x4000910C C   FIELD 00w08 CTL3_DACCODE0 (rw): This is the first 8-bit DAC code. When the DAC code is 0x0 the DAC output will be 0 V. When the DAC code is 0xFF the DAC output will be selected reference voltage x 255/256.
0x4000910C C   FIELD 16w08 CTL3_DACCODE1 (rw): This is the second 8-bit DAC code. When the DAC code is 0x0 the DAC output will be 0 V. When the DAC code is 0xFF the DAC output will be selected reference voltage x 255/256.
0x40009120 B  REGISTER STAT (ro): Status
0x40009120 C   FIELD 00w01 STAT_OUT (ro): This bit reflects the value of the comparator output. Writing to this bit has no effect on the comparator output.
0x40020000 A PERIPHERAL OPA0
0x40020800 B  REGISTER PWREN (rw): Power enable
0x40020800 C   FIELD 00w01 PWREN_ENABLE (rw): Enable the power
0x40020800 C   FIELD 24w08 PWREN_KEY (wo): KEY to allow Power State Change
0x40020804 B  REGISTER RSTCTL (wo): Reset Control
0x40020804 C   FIELD 00w01 RSTCTL_RESETASSERT (wo): Assert reset to the peripheral
0x40020804 C   FIELD 01w01 RSTCTL_RESETSTKYCLR (wo): Clear the RESETSTKY bit in the STAT register
0x40020804 C   FIELD 24w08 RSTCTL_KEY (wo): Unlock key
0x40020814 B  REGISTER GPRCM_STAT (ro): Status Register
0x40020814 C   FIELD 16w01 GPRCM_STAT_RESETSTKY (ro): This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register
0x40021010 B  REGISTER CLKOVR (rw): Clock Override
0x40021010 C   FIELD 00w01 CLKOVR_OVERRIDE (rw): Unlocks the functionality of [RUN_STOP] to override the automatic peripheral clock request
0x40021010 C   FIELD 01w01 CLKOVR_RUN_STOP (rw): If [OVERRIDE] is enabled, this register is used to manually control the peripheral's clock request to the system
0x4002101C B  REGISTER PWRCTL (rw): Power Control
0x4002101C C   FIELD 00w01 PWRCTL_AUTO_OFF (rw): When set the peripheral will remove its local IP request for enable so that it can be disabled if no other entities in the system are requesting it to be enabled.
0x40021100 B  REGISTER CTL (rw): Control Register
0x40021100 C   FIELD 00w01 CTL_ENABLE (rw): OAxn Enable.
0x40021104 B  REGISTER CFGBASE (rw): Configuration Base Register
0x40021104 C   FIELD 00w01 CFGBASE_GBW (rw): Select gain bandwidth which affects current as well the gain bandwidth. The lower gain bandwidth has lower current. See device specific datasheet for values. Can only be modified when STAT.BUSY=0.
0x40021104 C   FIELD 02w01 CFGBASE_RRI (rw): Rail-to-rail input enable. Can only be modified when STAT.BUSY=0
0x40021108 B  REGISTER CFG (rw): Configuration Register
0x40021108 C   FIELD 00w02 CFG_CHOP (rw): Chopping enable.
0x40021108 C   FIELD 02w01 CFG_OUTPIN (rw): Enable output pin
0x40021108 C   FIELD 03w04 CFG_PSEL (rw): Positive OA input selection. Please refer to the device specific datasheet for exact channels available.
0x40021108 C   FIELD 07w03 CFG_NSEL (rw): Negative OA input selection. Please refer to the device specific datasheet for exact channels available.
0x40021108 C   FIELD 10w03 CFG_MSEL (rw): MSEL Mux selection. Please refer to the device specific datasheet for exact channels available.
0x40021108 C   FIELD 13w03 CFG_GAIN (rw): Gain setting. Refer to TRM for enumeration information.
0x40021118 B  REGISTER STAT (ro): Status Register
0x40021118 C   FIELD 00w01 STAT_RDY (ro): OA ready status.
0x40022000 A PERIPHERAL OPA1
0x40022800 B  REGISTER PWREN (rw): Power enable
0x40022800 C   FIELD 00w01 PWREN_ENABLE (rw): Enable the power
0x40022800 C   FIELD 24w08 PWREN_KEY (wo): KEY to allow Power State Change
0x40022804 B  REGISTER RSTCTL (wo): Reset Control
0x40022804 C   FIELD 00w01 RSTCTL_RESETASSERT (wo): Assert reset to the peripheral
0x40022804 C   FIELD 01w01 RSTCTL_RESETSTKYCLR (wo): Clear the RESETSTKY bit in the STAT register
0x40022804 C   FIELD 24w08 RSTCTL_KEY (wo): Unlock key
0x40022814 B  REGISTER GPRCM_STAT (ro): Status Register
0x40022814 C   FIELD 16w01 GPRCM_STAT_RESETSTKY (ro): This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register
0x40023010 B  REGISTER CLKOVR (rw): Clock Override
0x40023010 C   FIELD 00w01 CLKOVR_OVERRIDE (rw): Unlocks the functionality of [RUN_STOP] to override the automatic peripheral clock request
0x40023010 C   FIELD 01w01 CLKOVR_RUN_STOP (rw): If [OVERRIDE] is enabled, this register is used to manually control the peripheral's clock request to the system
0x4002301C B  REGISTER PWRCTL (rw): Power Control
0x4002301C C   FIELD 00w01 PWRCTL_AUTO_OFF (rw): When set the peripheral will remove its local IP request for enable so that it can be disabled if no other entities in the system are requesting it to be enabled.
0x40023100 B  REGISTER CTL (rw): Control Register
0x40023100 C   FIELD 00w01 CTL_ENABLE (rw): OAxn Enable.
0x40023104 B  REGISTER CFGBASE (rw): Configuration Base Register
0x40023104 C   FIELD 00w01 CFGBASE_GBW (rw): Select gain bandwidth which affects current as well the gain bandwidth. The lower gain bandwidth has lower current. See device specific datasheet for values. Can only be modified when STAT.BUSY=0.
0x40023104 C   FIELD 02w01 CFGBASE_RRI (rw): Rail-to-rail input enable. Can only be modified when STAT.BUSY=0
0x40023108 B  REGISTER CFG (rw): Configuration Register
0x40023108 C   FIELD 00w02 CFG_CHOP (rw): Chopping enable.
0x40023108 C   FIELD 02w01 CFG_OUTPIN (rw): Enable output pin
0x40023108 C   FIELD 03w04 CFG_PSEL (rw): Positive OA input selection. Please refer to the device specific datasheet for exact channels available.
0x40023108 C   FIELD 07w03 CFG_NSEL (rw): Negative OA input selection. Please refer to the device specific datasheet for exact channels available.
0x40023108 C   FIELD 10w03 CFG_MSEL (rw): MSEL Mux selection. Please refer to the device specific datasheet for exact channels available.
0x40023108 C   FIELD 13w03 CFG_GAIN (rw): Gain setting. Refer to TRM for enumeration information.
0x40023118 B  REGISTER STAT (ro): Status Register
0x40023118 C   FIELD 00w01 STAT_RDY (ro): OA ready status.
0x40030000 A PERIPHERAL VREF
0x40030800 B  REGISTER PWREN (rw): Power enable
0x40030800 C   FIELD 00w01 PWREN_ENABLE: Enable the power
0x40030800 C   FIELD 24w08 PWREN_KEY (wo): KEY to allow Power State Change
0x40030804 B  REGISTER RSTCTL (wo): Reset Control
0x40030804 C   FIELD 00w01 RSTCTL_RESETASSERT (wo): Assert reset to the peripheral
0x40030804 C   FIELD 01w01 RSTCTL_RESETSTKYCLR (wo): Clear the RESETSTKY bit in the STAT register
0x40030804 C   FIELD 24w08 RSTCTL_KEY (wo): Unlock key
0x40030814 B  REGISTER STAT (ro): Status Register
0x40030814 C   FIELD 16w01 STAT_RESETSTKY (ro): This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register
0x40031000 B  REGISTER CLKDIV (rw): Clock Divider
0x40031000 C   FIELD 00w03 CLKDIV_RATIO (rw): Selects divide ratio of module clock
0x40031008 B  REGISTER CLKSEL (rw): Clock Selection
0x40031008 C   FIELD 01w01 CLKSEL_LFCLK_SEL (rw): Selects LFCLK as clock source if enabled
0x40031008 C   FIELD 02w01 CLKSEL_MFCLK_SEL (rw): Selects MFCLK as clock source if enabled
0x40031008 C   FIELD 03w01 CLKSEL_BUSCLK_SEL (rw): Selects BUSCLK as clock source if enabled
0x400310FC B  REGISTER DESC (ro): Module Description
0x400310FC C   FIELD 00w04 DESC_MINREV (ro): Minor rev of the IP
0x400310FC C   FIELD 04w04 DESC_MAJREV (ro): Major rev of the IP
0x400310FC C   FIELD 12w04 DESC_FEATUREVER (ro): Feature Set for the module *instance*
0x400310FC C   FIELD 16w16 DESC_MODULEID (ro): Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness.
0x40031100 B  REGISTER CTL0 (rw): Control 0
0x40031100 C   FIELD 00w01 CTL0_ENABLE (rw): This bit enables the VREF module.
0x40031100 C   FIELD 01w01 CTL0_ENABLEBIAS (rw): This bit enables the VREF Bias.
0x40031100 C   FIELD 02w02 CTL0_IBPROG (rw): There bits configure current bias.
0x40031100 C   FIELD 07w01 CTL0_BUFCONFIG (rw): These bits configure output buffer.
0x40031100 C   FIELD 08w01 CTL0_SHMODE (rw): This bit enable sample and hold mode
0x40031100 C   FIELD 09w04 CTL0_SPARE (rw): These bits are reserved
0x40031104 B  REGISTER CTL1 (rw): Control 1
0x40031104 C   FIELD 00w01 CTL1_READY (ro): These bits defines status of VREF
0x40031104 C   FIELD 01w01 CTL1_VREFLOSEL (rw): This bit select VREFLO pin
0x40031108 B  REGISTER CTL2 (rw): Control 2
0x40031108 C   FIELD 00w16 CTL2_SHCYCLE (rw): Sample and hold cycle count
0x40031108 C   FIELD 16w16 CTL2_HCYCLE (rw): Hold cycle count
0x40080000 A PERIPHERAL WWDT0
0x40080800 B  REGISTER PWREN (rw): Power enable
0x40080800 C   FIELD 00w01 PWREN_ENABLE: Enable the power Note: For safety devices the power cannot be disabled once enabled.
0x40080800 C   FIELD 24w08 PWREN_KEY (wo): KEY to allow Power State Change
0x40080804 B  REGISTER RSTCTL (wo): Reset Control
0x40080804 C   FIELD 00w01 RSTCTL_RESETASSERT (wo): Assert reset to the peripheral Note: For safety devices a watchdog reset by software is not possible.
0x40080804 C   FIELD 01w01 RSTCTL_RESETSTKYCLR (wo): Clear [GPRCM.STAT.RESETSTKY]
0x40080804 C   FIELD 24w08 RSTCTL_KEY (wo): Unlock key
0x40080814 B  REGISTER STAT (ro): Status Register
0x40080814 C   FIELD 16w01 STAT_RESETSTKY (ro): This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register
0x40081018 B  REGISTER PDBGCTL (rw): Peripheral Debug Control
0x40081018 C   FIELD 00w01 PDBGCTL_FREE (rw): Free run control
0x40081020 B  REGISTER IIDX (ro): Interrupt index
0x40081020 C   FIELD 00w05 IIDX_STAT (ro): Module Interrupt Vector Value. This register provides the highest priority interrupt index. A read clears the corresponding interrupt flag in RIS and MISC.
0x40081028 B  REGISTER IMASK (rw): Interrupt mask
0x40081028 C   FIELD 00w01 IMASK_INTTIM: Interval Timer Interrupt.
0x40081030 B  REGISTER RIS (ro): Raw interrupt status
0x40081030 C   FIELD 00w01 RIS_INTTIM: Interval Timer Interrupt.
0x40081038 B  REGISTER MIS (ro): Masked interrupt status
0x40081038 C   FIELD 00w01 MIS_INTTIM: Interval Timer Interrupt.
0x40081040 B  REGISTER ISET (wo): Interrupt set
0x40081040 C   FIELD 00w01 ISET_INTTIM: Interval Timer Interrupt.
0x40081048 B  REGISTER ICLR (wo): Interrupt clear
0x40081048 C   FIELD 00w01 ICLR_INTTIM: Interval Timer Interrupt.
0x400810E0 B  REGISTER EVT_MODE (rw): Event Mode
0x400810E0 C   FIELD 00w02 EVT_MODE_INT0_CFG (ro): Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]
0x400810FC B  REGISTER DESC (ro): Module Description
0x400810FC C   FIELD 00w04 DESC_MINREV: Minor rev of the IP
0x400810FC C   FIELD 04w04 DESC_MAJREV: Major rev of the IP
0x400810FC C   FIELD 08w04 DESC_INSTNUM: Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances
0x400810FC C   FIELD 12w04 DESC_FEATUREVER: Feature Set for the module *instance*
0x400810FC C   FIELD 16w16 DESC_MODULEID: Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness.
0x40081100 B  REGISTER WWDTCTL0 (read-writeOnce): Window Watchdog Timer Control Register 0
0x40081100 C   FIELD 00w03 WWDTCTL0_CLKDIV (read-writeOnce): Module Clock Divider, Divide the clock source by CLKDIV+1. Divider values from /1 to /8 are possible. The clock divider is currently 4 bits. Bit 4 has no effect and should always be written with 0.
0x40081100 C   FIELD 04w03 WWDTCTL0_PER (read-writeOnce): Timer Period of the WWDT. These bits select the total watchdog timer count.
0x40081100 C   FIELD 08w03 WWDTCTL0_WINDOW0 (read-writeOnce): Closed window period in percentage of the timer interval. WWDTCTL1.WINSEL determines the active window setting (WWDTCTL0.WINDOW0 or WWDTCTL0.WINDOW1).
0x40081100 C   FIELD 12w03 WWDTCTL0_WINDOW1 (read-writeOnce): Closed window period in percentage of the timer interval. WWDTCTL1.WINSEL determines the active window setting (WWDTCTL0.WINDOW0 or WWDTCTL0.WINDOW1).
0x40081100 C   FIELD 16w01 WWDTCTL0_MODE (read-writeOnce): Window Watchdog Timer Mode
0x40081100 C   FIELD 17w01 WWDTCTL0_STISM (read-writeOnce): Stop In Sleep Mode. The functionality of this bit requires that POLICY.HWCEN = 0. If POLICY.HWCEN = 1 the WWDT resets during sleep and needs re-configuration. Note: This bit has no effect for the global Window Watchdog as Sleep Mode is not supported.
0x40081100 C   FIELD 24w08 WWDTCTL0_KEY (read-writeOnce): KEY to allow write access to this register. Writing to this register with an incorrect key activates the WWDT error signal to the ESM. Read as 0.
0x40081104 B  REGISTER WWDTCTL1 (rw): Window Watchdog Timer Control Register 0
0x40081104 C   FIELD 00w01 WWDTCTL1_WINSEL (rw): Close Window Select
0x40081104 C   FIELD 24w08 WWDTCTL1_KEY (wo): KEY to allow write access to this register. Writing to this register with an incorrect key activates the WWDT error signal to the ESM. Read as 0.
0x40081108 B  REGISTER WWDTCNTRST (rw): Window Watchdog Timer Counter Reset Register
0x40081108 C   FIELD 00w32 WWDTCNTRST_RESTART (rw): Window Watchdog Timer Counter Restart Writing 00A7h to this register restarts the WWDT Counter. Writing any other value causes an error generation to the ESM. Read as 0.
0x4008110C B  REGISTER WWDTSTAT (ro): Window Watchdog Timer Status Register
0x4008110C C   FIELD 00w01 WWDTSTAT_RUN (ro): Watchdog running status flag.
0x40084000 A PERIPHERAL TIMG0
0x40084400 B  REGISTER FSUB_0 (rw): Subsciber Port 0
0x40084400 C   FIELD 00w02 FSUB_0_CHANID: 0 = disconnected. 1-15 = connected to channelID = CHANID.
0x40084404 B  REGISTER FSUB_1 (rw): Subscriber Port 1
0x40084404 C   FIELD 00w02 FSUB_1_CHANID: 0 = disconnected. 1-15 = connected to channelID = CHANID.
0x40084444 B  REGISTER FPUB_0 (rw): Publisher Port 0
0x40084444 C   FIELD 00w02 FPUB_0_CHANID: 0 = disconnected. 1-15 = connected to channelID = CHANID.
0x40084448 B  REGISTER FPUB_1 (rw): Publisher Port 1
0x40084448 C   FIELD 00w02 FPUB_1_CHANID: 0 = disconnected. 1-15 = connected to channelID = CHANID.
0x40084800 B  REGISTER PWREN (rw): Power enable
0x40084800 C   FIELD 00w01 PWREN_ENABLE: Enable the power
0x40084800 C   FIELD 24w08 PWREN_KEY (wo): KEY to allow Power State Change
0x40084804 B  REGISTER RSTCTL (wo): Reset Control
0x40084804 C   FIELD 00w01 RSTCTL_RESETASSERT (wo): Assert reset to the peripheral
0x40084804 C   FIELD 01w01 RSTCTL_RESETSTKYCLR (wo): Clear the RESETSTKY bit in the STAT register
0x40084804 C   FIELD 24w08 RSTCTL_KEY (wo): Unlock key
0x40084814 B  REGISTER STAT (ro): Status Register
0x40084814 C   FIELD 16w01 STAT_RESETSTKY (ro): This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register
0x40085000 B  REGISTER CLKDIV (rw): Clock Divider
0x40085000 C   FIELD 00w03 CLKDIV_RATIO: Selects divide ratio of module clock
0x40085008 B  REGISTER CLKSEL (rw): Clock Select for Ultra Low Power peripherals
0x40085008 C   FIELD 01w01 CLKSEL_LFCLK_SEL (rw): Selects LFCLK as clock source if enabled
0x40085008 C   FIELD 02w01 CLKSEL_MFCLK_SEL (rw): Selects MFCLK as clock source if enabled
0x40085008 C   FIELD 03w01 CLKSEL_BUSCLK_SEL (rw): Selects BUSCLK as clock source if enabled
0x40085018 B  REGISTER PDBGCTL (rw): Peripheral Debug Control
0x40085018 C   FIELD 00w01 PDBGCTL_FREE (rw): Free run control
0x40085018 C   FIELD 01w01 PDBGCTL_SOFT (rw): Soft halt boundary control. This function is only available, if [FREE] is set to 'STOP'
0x40085020 B  REGISTER IIDX (ro): Interrupt index
0x40085020 C   FIELD 00w08 IIDX_STAT (ro): Interrupt index status
0x40085028 B  REGISTER IMASK (rw): Interrupt mask
0x40085028 C   FIELD 00w01 IMASK_Z: Zero Event mask
0x40085028 C   FIELD 01w01 IMASK_L: Load Event mask
0x40085028 C   FIELD 04w01 IMASK_CCD0: Capture or Compare DN event mask CCP0
0x40085028 C   FIELD 05w01 IMASK_CCD1: Capture or Compare DN event mask CCP1
0x40085028 C   FIELD 08w01 IMASK_CCU0: Capture or Compare UP event mask CCP0
0x40085028 C   FIELD 09w01 IMASK_CCU1: Capture or Compare UP event mask CCP1
0x40085028 C   FIELD 25w01 IMASK_TOV: Trigger Overflow Event mask
0x40085030 B  REGISTER RIS (ro): Raw interrupt status
0x40085030 C   FIELD 00w01 RIS_Z: Zero event generated an interrupt.
0x40085030 C   FIELD 01w01 RIS_L: Load event generated an interrupt.
0x40085030 C   FIELD 04w01 RIS_CCD0: Capture or compare down event generated an interrupt CCP0
0x40085030 C   FIELD 05w01 RIS_CCD1: Capture or compare down event generated an interrupt CCP1
0x40085030 C   FIELD 08w01 RIS_CCU0: Capture or compare up event generated an interrupt CCP0
0x40085030 C   FIELD 09w01 RIS_CCU1: Capture or compare up event generated an interrupt CCP1
0x40085030 C   FIELD 25w01 RIS_TOV: Trigger overflow
0x40085038 B  REGISTER MIS (ro): Masked interrupt status
0x40085038 C   FIELD 00w01 MIS_Z: Zero event generated an interrupt.
0x40085038 C   FIELD 01w01 MIS_L: Load event generated an interrupt.
0x40085038 C   FIELD 04w01 MIS_CCD0: Capture or compare down event generated an interrupt CCP0
0x40085038 C   FIELD 05w01 MIS_CCD1: Capture or compare down event generated an interrupt CCP1
0x40085038 C   FIELD 08w01 MIS_CCU0: Capture or compare up event generated an interrupt CCP0
0x40085038 C   FIELD 09w01 MIS_CCU1: Capture or compare up event generated an interrupt CCP1
0x40085038 C   FIELD 25w01 MIS_TOV: Trigger overflow
0x40085040 B  REGISTER ISET (wo): Interrupt set
0x40085040 C   FIELD 00w01 ISET_Z: Zero event SET
0x40085040 C   FIELD 01w01 ISET_L: Load event SET
0x40085040 C   FIELD 04w01 ISET_CCD0: Capture or compare down event SET
0x40085040 C   FIELD 05w01 ISET_CCD1: Capture or compare down event SET
0x40085040 C   FIELD 08w01 ISET_CCU0: Capture or compare up event SET
0x40085040 C   FIELD 09w01 ISET_CCU1: Capture or compare up event SET
0x40085040 C   FIELD 25w01 ISET_TOV: Trigger Overflow event SET
0x40085048 B  REGISTER ICLR (wo): Interrupt clear
0x40085048 C   FIELD 00w01 ICLR_Z: Zero event CLEAR
0x40085048 C   FIELD 01w01 ICLR_L: Load event CLEAR
0x40085048 C   FIELD 04w01 ICLR_CCD0: Capture or compare down event CLEAR
0x40085048 C   FIELD 05w01 ICLR_CCD1: Capture or compare down event CLEAR
0x40085048 C   FIELD 08w01 ICLR_CCU0: Capture or compare up event CLEAR
0x40085048 C   FIELD 09w01 ICLR_CCU1: Capture or compare up event CLEAR
0x40085048 C   FIELD 25w01 ICLR_TOV: Trigger Overflow event CLEAR
0x400850E0 B  REGISTER EVT_MODE (rw): Event Mode
0x400850E0 C   FIELD 00w02 EVT_MODE_EVT0_CFG (ro): Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]
0x400850E0 C   FIELD 02w02 EVT_MODE_EVT1_CFG (ro): Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]
0x400850E0 C   FIELD 04w02 EVT_MODE_EVT2_CFG (ro): Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]
0x400850FC B  REGISTER DESC (ro): Module Description
0x400850FC C   FIELD 00w04 DESC_MINREV: Minor rev of the IP
0x400850FC C   FIELD 04w04 DESC_MAJREV: Major rev of the IP
0x400850FC C   FIELD 08w04 DESC_INSTNUM: Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances
0x400850FC C   FIELD 12w04 DESC_FEATUREVER: Feature Set for the module *instance*
0x400850FC C   FIELD 16w16 DESC_MODULEID: Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness.
0x40085100 B  REGISTER CCPD (rw): CCP Direction
0x40085100 C   FIELD 00w01 CCPD_C0CCP0: Counter CCP0
0x40085100 C   FIELD 01w01 CCPD_C0CCP1: Counter CCP1
0x40085104 B  REGISTER ODIS (rw): Output Disable
0x40085104 C   FIELD 00w01 ODIS_C0CCP0 (rw): Counter CCP0 Disable Mask Defines whether CCP0 of Counter n is forced low or not
0x40085104 C   FIELD 01w01 ODIS_C0CCP1 (rw): Counter CCP1 Disable Mask Defines whether CCP0 of Counter n is forced low or not
0x40085108 B  REGISTER CCLKCTL (rw): Counter Clock Control Register
0x40085108 C   FIELD 00w01 CCLKCTL_CLKEN (rw): Clock Enable Disables the clock gating to the module. SW has to explicitly program the value to 0 to gate the clock.
0x4008510C B  REGISTER CPS (rw): Clock Prescale Register
0x4008510C C   FIELD 00w08 CPS_PCNT (rw): Pre-Scale Count This field specifies the pre-scale count value. The selected TIMCLK source is divided by a value of (PCNT+1). A PCNT value of 0 divides TIMCLK by 1, effectively bypassing the divider. A PCNT value of greater than 0 divides the TIMCLK source generating a slower clock
0x40085110 B  REGISTER CPSV (ro): Clock prescale count status register
0x40085110 C   FIELD 00w08 CPSV_CPSVAL (ro): Current Prescale Count Value
0x40085114 B  REGISTER CTTRIGCTL (rw): Timer Cross Trigger Control Register
0x40085114 C   FIELD 00w01 CTTRIGCTL_CTEN (rw): Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system. These cross triggers are connected to the respective timer trigger in of the other timer IPs in the SOC power domain. The timer cross trigger is essentially the combined logic of the HW and SW conditions controlling EN bit in the CTRCTL register.
0x40085114 C   FIELD 01w01 CTTRIGCTL_EVTCTEN (rw): Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path
0x40085114 C   FIELD 16w04 CTTRIGCTL_EVTCTTRIGSEL (rw): Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path
0x4008511C B  REGISTER CTTRIG (wo): Timer Cross Trigger Register
0x4008511C C   FIELD 00w01 CTTRIG_TRIG (wo): Generate Cross Trigger This bit when programmed will generate a synchronized trigger condition all the cross trigger enabled Timer instances including current timer instance.
0x40085800 B  REGISTER CTR (rw): Counter Register
0x40085800 C   FIELD 00w16 CTR_CCTR (rw): Current Counter value
0x40085804 B  REGISTER CTRCTL (rw): Counter Control Register
0x40085804 C   FIELD 00w01 CTRCTL_EN (rw): Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit, the counter value is set per the CVAE value. Hardware: This bit may also be set as the result of an LCOND or ZCOND condition being met and the counter value changed to the load value or zero value, respectively.
0x40085804 C   FIELD 01w03 CTRCTL_REPEAT (rw): Repeat. The repeat bit controls whether the counter continues to advance following a zero event, or the exiting of a debug or fault condition. If counting down, a zero event is followed by a load at the next advance condition. If counting up-down, a zero event is followed by an advance event (+1). The intent of encoding 3 is that if the debug condition is in effect, the generation of the load pulse is deferred until the debug condition is over. This allows the counter to reach zero before counting is suspended.
0x40085804 C   FIELD 04w02 CTRCTL_CM (rw): Count Mode
0x40085804 C   FIELD 07w03 CTRCTL_CLC (rw): Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved.
0x40085804 C   FIELD 10w03 CTRCTL_CAC (rw): Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved.
0x40085804 C   FIELD 13w03 CTRCTL_CZC (rw): Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved.
0x40085804 C   FIELD 17w01 CTRCTL_DRB (rw): Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode.
0x40085804 C   FIELD 28w02 CTRCTL_CVAE (rw): Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active.
0x40085808 B  REGISTER LOAD (rw): Load Register
0x40085808 C   FIELD 00w16 LOAD_LD (rw): Load Value
0x40085810 B  REGISTER CC_01[0] (rw): Capture or Compare Register 0 to Capture or Compare Register 1
0x40085810 C   FIELD 00w16 CC_01_CCVAL (rw): Capture or compare value
0x40085814 B  REGISTER CC_01[1] (rw): Capture or Compare Register 0 to Capture or Compare Register 1
0x40085814 C   FIELD 00w16 CC_01_CCVAL (rw): Capture or compare value
0x40085830 B  REGISTER CCCTL_01[0] (rw): Capture or Compare Control Registers
0x40085830 C   FIELD 00w03 CCCTL_01_CCOND (rw): Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved
0x40085830 C   FIELD 04w03 CCCTL_01_ACOND (rw): Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved
0x40085830 C   FIELD 08w03 CCCTL_01_LCOND (rw): Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved
0x40085830 C   FIELD 12w03 CCCTL_01_ZCOND (rw): Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved
0x40085830 C   FIELD 17w01 CCCTL_01_COC (rw): Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both).
0x40085830 C   FIELD 22w03 CCCTL_01_CC2SELU: Selects the source second CCU event.
0x40085830 C   FIELD 26w03 CCCTL_01_CCACTUPD (rw): CCACT shadow register Update Method This field controls how updates to the CCCACT shadow register are performed
0x40085830 C   FIELD 29w03 CCCTL_01_CC2SELD: Selects the source second CCD event.
0x40085834 B  REGISTER CCCTL_01[1] (rw): Capture or Compare Control Registers
0x40085834 C   FIELD 00w03 CCCTL_01_CCOND (rw): Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved
0x40085834 C   FIELD 04w03 CCCTL_01_ACOND (rw): Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved
0x40085834 C   FIELD 08w03 CCCTL_01_LCOND (rw): Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved
0x40085834 C   FIELD 12w03 CCCTL_01_ZCOND (rw): Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved
0x40085834 C   FIELD 17w01 CCCTL_01_COC (rw): Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both).
0x40085834 C   FIELD 22w03 CCCTL_01_CC2SELU: Selects the source second CCU event.
0x40085834 C   FIELD 26w03 CCCTL_01_CCACTUPD (rw): CCACT shadow register Update Method This field controls how updates to the CCCACT shadow register are performed
0x40085834 C   FIELD 29w03 CCCTL_01_CC2SELD: Selects the source second CCD event.
0x40085850 B  REGISTER OCTL_01[0] (rw): CCP Output Control Registers
0x40085850 C   FIELD 00w04 OCTL_01_CCPO (rw): CCP Output Source
0x40085850 C   FIELD 04w01 OCTL_01_CCPOINV (rw): CCP Output Invert The output as selected by CCPO is conditionally inverted.
0x40085850 C   FIELD 05w01 OCTL_01_CCPIV (rw): CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0).
0x40085854 B  REGISTER OCTL_01[1] (rw): CCP Output Control Registers
0x40085854 C   FIELD 00w04 OCTL_01_CCPO (rw): CCP Output Source
0x40085854 C   FIELD 04w01 OCTL_01_CCPOINV (rw): CCP Output Invert The output as selected by CCPO is conditionally inverted.
0x40085854 C   FIELD 05w01 OCTL_01_CCPIV (rw): CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0).
0x40085870 B  REGISTER CCACT_01[0] (rw): Capture or Compare Action Registers
0x40085870 C   FIELD 00w02 CCACT_01_ZACT (rw): CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event.
0x40085870 C   FIELD 03w02 CCACT_01_LACT (rw): CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event.
0x40085870 C   FIELD 06w02 CCACT_01_CDACT (rw): CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down.
0x40085870 C   FIELD 09w02 CCACT_01_CUACT (rw): CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up.
0x40085870 C   FIELD 12w02 CCACT_01_CC2DACT (rw): CCP Output Action on CC2D event.
0x40085870 C   FIELD 15w02 CCACT_01_CC2UACT (rw): CCP Output Action on CC2U event.
0x40085870 C   FIELD 28w02 CCACT_01_SWFRCACT (rw): CCP Output Action on Software Froce Output This field describes the resulting action of software force. This action has a shadow register, which will be updated under specific condition. So that this register cannot take into effect immediately.
0x40085874 B  REGISTER CCACT_01[1] (rw): Capture or Compare Action Registers
0x40085874 C   FIELD 00w02 CCACT_01_ZACT (rw): CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event.
0x40085874 C   FIELD 03w02 CCACT_01_LACT (rw): CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event.
0x40085874 C   FIELD 06w02 CCACT_01_CDACT (rw): CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down.
0x40085874 C   FIELD 09w02 CCACT_01_CUACT (rw): CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up.
0x40085874 C   FIELD 12w02 CCACT_01_CC2DACT (rw): CCP Output Action on CC2D event.
0x40085874 C   FIELD 15w02 CCACT_01_CC2UACT (rw): CCP Output Action on CC2U event.
0x40085874 C   FIELD 28w02 CCACT_01_SWFRCACT (rw): CCP Output Action on Software Froce Output This field describes the resulting action of software force. This action has a shadow register, which will be updated under specific condition. So that this register cannot take into effect immediately.
0x40085880 B  REGISTER IFCTL_01[0] (rw): Input Filter Control Register
0x40085880 C   FIELD 00w04 IFCTL_01_ISEL (rw): Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved
0x40085880 C   FIELD 07w01 IFCTL_01_INV (rw): Input Inversion This bit controls whether the selected input is inverted.
0x40085880 C   FIELD 08w02 IFCTL_01_FP (rw): Filter Period. This field specifies the sample period for the input filter. I.e. The input is sampled for FP timer clocks during filtering.
0x40085880 C   FIELD 11w01 IFCTL_01_CPV (rw): Consecutive Period/Voting Select This bit controls whether the input filter uses a stricter consecutive period count or majority voting.
0x40085880 C   FIELD 12w01 IFCTL_01_FE (rw): Filter Enable This bit controls whether the input is filtered by the input filter or bypasses to the edge detect.
0x40085884 B  REGISTER IFCTL_01[1] (rw): Input Filter Control Register
0x40085884 C   FIELD 00w04 IFCTL_01_ISEL (rw): Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved
0x40085884 C   FIELD 07w01 IFCTL_01_INV (rw): Input Inversion This bit controls whether the selected input is inverted.
0x40085884 C   FIELD 08w02 IFCTL_01_FP (rw): Filter Period. This field specifies the sample period for the input filter. I.e. The input is sampled for FP timer clocks during filtering.
0x40085884 C   FIELD 11w01 IFCTL_01_CPV (rw): Consecutive Period/Voting Select This bit controls whether the input filter uses a stricter consecutive period count or majority voting.
0x40085884 C   FIELD 12w01 IFCTL_01_FE (rw): Filter Enable This bit controls whether the input is filtered by the input filter or bypasses to the edge detect.
0x400858B0 B  REGISTER TSEL (rw): Trigger Select
0x400858B0 C   FIELD 00w05 TSEL_ETSEL (rw): External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger. Triggers 0-15 are used to connect triggers generated by other timer modules in the same power domain. Refer to the SoC datasheet to get details. Triggers 16 and 17 are connected to event manager subscriber ports. Event lines 18-31 are reserved for future use.
0x400858B0 C   FIELD 09w01 TSEL_TE (rw): Trigger Enable. This selects whether a trigger is enabled or not for this counter 0x0 = Triggers are not used 0x1 = Triggers are used as selected by the ETSEL field
0x40086000 A PERIPHERAL TIMG1
0x40086400 B  REGISTER FSUB_0 (rw): Subsciber Port 0
0x40086400 C   FIELD 00w02 FSUB_0_CHANID: 0 = disconnected. 1-15 = connected to channelID = CHANID.
0x40086404 B  REGISTER FSUB_1 (rw): Subscriber Port 1
0x40086404 C   FIELD 00w02 FSUB_1_CHANID: 0 = disconnected. 1-15 = connected to channelID = CHANID.
0x40086444 B  REGISTER FPUB_0 (rw): Publisher Port 0
0x40086444 C   FIELD 00w02 FPUB_0_CHANID: 0 = disconnected. 1-15 = connected to channelID = CHANID.
0x40086448 B  REGISTER FPUB_1 (rw): Publisher Port 1
0x40086448 C   FIELD 00w02 FPUB_1_CHANID: 0 = disconnected. 1-15 = connected to channelID = CHANID.
0x40086800 B  REGISTER PWREN (rw): Power enable
0x40086800 C   FIELD 00w01 PWREN_ENABLE: Enable the power
0x40086800 C   FIELD 24w08 PWREN_KEY (wo): KEY to allow Power State Change
0x40086804 B  REGISTER RSTCTL (wo): Reset Control
0x40086804 C   FIELD 00w01 RSTCTL_RESETASSERT (wo): Assert reset to the peripheral
0x40086804 C   FIELD 01w01 RSTCTL_RESETSTKYCLR (wo): Clear the RESETSTKY bit in the STAT register
0x40086804 C   FIELD 24w08 RSTCTL_KEY (wo): Unlock key
0x40086814 B  REGISTER STAT (ro): Status Register
0x40086814 C   FIELD 16w01 STAT_RESETSTKY (ro): This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register
0x40087000 B  REGISTER CLKDIV (rw): Clock Divider
0x40087000 C   FIELD 00w03 CLKDIV_RATIO: Selects divide ratio of module clock
0x40087008 B  REGISTER CLKSEL (rw): Clock Select for Ultra Low Power peripherals
0x40087008 C   FIELD 01w01 CLKSEL_LFCLK_SEL (rw): Selects LFCLK as clock source if enabled
0x40087008 C   FIELD 02w01 CLKSEL_MFCLK_SEL (rw): Selects MFCLK as clock source if enabled
0x40087008 C   FIELD 03w01 CLKSEL_BUSCLK_SEL (rw): Selects BUSCLK as clock source if enabled
0x40087018 B  REGISTER PDBGCTL (rw): Peripheral Debug Control
0x40087018 C   FIELD 00w01 PDBGCTL_FREE (rw): Free run control
0x40087018 C   FIELD 01w01 PDBGCTL_SOFT (rw): Soft halt boundary control. This function is only available, if [FREE] is set to 'STOP'
0x40087020 B  REGISTER IIDX (ro): Interrupt index
0x40087020 C   FIELD 00w08 IIDX_STAT (ro): Interrupt index status
0x40087028 B  REGISTER IMASK (rw): Interrupt mask
0x40087028 C   FIELD 00w01 IMASK_Z: Zero Event mask
0x40087028 C   FIELD 01w01 IMASK_L: Load Event mask
0x40087028 C   FIELD 04w01 IMASK_CCD0: Capture or Compare DN event mask CCP0
0x40087028 C   FIELD 05w01 IMASK_CCD1: Capture or Compare DN event mask CCP1
0x40087028 C   FIELD 08w01 IMASK_CCU0: Capture or Compare UP event mask CCP0
0x40087028 C   FIELD 09w01 IMASK_CCU1: Capture or Compare UP event mask CCP1
0x40087028 C   FIELD 25w01 IMASK_TOV: Trigger Overflow Event mask
0x40087030 B  REGISTER RIS (ro): Raw interrupt status
0x40087030 C   FIELD 00w01 RIS_Z: Zero event generated an interrupt.
0x40087030 C   FIELD 01w01 RIS_L: Load event generated an interrupt.
0x40087030 C   FIELD 04w01 RIS_CCD0: Capture or compare down event generated an interrupt CCP0
0x40087030 C   FIELD 05w01 RIS_CCD1: Capture or compare down event generated an interrupt CCP1
0x40087030 C   FIELD 08w01 RIS_CCU0: Capture or compare up event generated an interrupt CCP0
0x40087030 C   FIELD 09w01 RIS_CCU1: Capture or compare up event generated an interrupt CCP1
0x40087030 C   FIELD 25w01 RIS_TOV: Trigger overflow
0x40087038 B  REGISTER MIS (ro): Masked interrupt status
0x40087038 C   FIELD 00w01 MIS_Z: Zero event generated an interrupt.
0x40087038 C   FIELD 01w01 MIS_L: Load event generated an interrupt.
0x40087038 C   FIELD 04w01 MIS_CCD0: Capture or compare down event generated an interrupt CCP0
0x40087038 C   FIELD 05w01 MIS_CCD1: Capture or compare down event generated an interrupt CCP1
0x40087038 C   FIELD 08w01 MIS_CCU0: Capture or compare up event generated an interrupt CCP0
0x40087038 C   FIELD 09w01 MIS_CCU1: Capture or compare up event generated an interrupt CCP1
0x40087038 C   FIELD 25w01 MIS_TOV: Trigger overflow
0x40087040 B  REGISTER ISET (wo): Interrupt set
0x40087040 C   FIELD 00w01 ISET_Z: Zero event SET
0x40087040 C   FIELD 01w01 ISET_L: Load event SET
0x40087040 C   FIELD 04w01 ISET_CCD0: Capture or compare down event SET
0x40087040 C   FIELD 05w01 ISET_CCD1: Capture or compare down event SET
0x40087040 C   FIELD 08w01 ISET_CCU0: Capture or compare up event SET
0x40087040 C   FIELD 09w01 ISET_CCU1: Capture or compare up event SET
0x40087040 C   FIELD 25w01 ISET_TOV: Trigger Overflow event SET
0x40087048 B  REGISTER ICLR (wo): Interrupt clear
0x40087048 C   FIELD 00w01 ICLR_Z: Zero event CLEAR
0x40087048 C   FIELD 01w01 ICLR_L: Load event CLEAR
0x40087048 C   FIELD 04w01 ICLR_CCD0: Capture or compare down event CLEAR
0x40087048 C   FIELD 05w01 ICLR_CCD1: Capture or compare down event CLEAR
0x40087048 C   FIELD 08w01 ICLR_CCU0: Capture or compare up event CLEAR
0x40087048 C   FIELD 09w01 ICLR_CCU1: Capture or compare up event CLEAR
0x40087048 C   FIELD 25w01 ICLR_TOV: Trigger Overflow event CLEAR
0x400870E0 B  REGISTER EVT_MODE (rw): Event Mode
0x400870E0 C   FIELD 00w02 EVT_MODE_EVT0_CFG (ro): Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]
0x400870E0 C   FIELD 02w02 EVT_MODE_EVT1_CFG (ro): Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]
0x400870E0 C   FIELD 04w02 EVT_MODE_EVT2_CFG (ro): Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]
0x400870FC B  REGISTER DESC (ro): Module Description
0x400870FC C   FIELD 00w04 DESC_MINREV: Minor rev of the IP
0x400870FC C   FIELD 04w04 DESC_MAJREV: Major rev of the IP
0x400870FC C   FIELD 08w04 DESC_INSTNUM: Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances
0x400870FC C   FIELD 12w04 DESC_FEATUREVER: Feature Set for the module *instance*
0x400870FC C   FIELD 16w16 DESC_MODULEID: Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness.
0x40087100 B  REGISTER CCPD (rw): CCP Direction
0x40087100 C   FIELD 00w01 CCPD_C0CCP0: Counter CCP0
0x40087100 C   FIELD 01w01 CCPD_C0CCP1: Counter CCP1
0x40087104 B  REGISTER ODIS (rw): Output Disable
0x40087104 C   FIELD 00w01 ODIS_C0CCP0 (rw): Counter CCP0 Disable Mask Defines whether CCP0 of Counter n is forced low or not
0x40087104 C   FIELD 01w01 ODIS_C0CCP1 (rw): Counter CCP1 Disable Mask Defines whether CCP0 of Counter n is forced low or not
0x40087108 B  REGISTER CCLKCTL (rw): Counter Clock Control Register
0x40087108 C   FIELD 00w01 CCLKCTL_CLKEN (rw): Clock Enable Disables the clock gating to the module. SW has to explicitly program the value to 0 to gate the clock.
0x4008710C B  REGISTER CPS (rw): Clock Prescale Register
0x4008710C C   FIELD 00w08 CPS_PCNT (rw): Pre-Scale Count This field specifies the pre-scale count value. The selected TIMCLK source is divided by a value of (PCNT+1). A PCNT value of 0 divides TIMCLK by 1, effectively bypassing the divider. A PCNT value of greater than 0 divides the TIMCLK source generating a slower clock
0x40087110 B  REGISTER CPSV (ro): Clock prescale count status register
0x40087110 C   FIELD 00w08 CPSV_CPSVAL (ro): Current Prescale Count Value
0x40087114 B  REGISTER CTTRIGCTL (rw): Timer Cross Trigger Control Register
0x40087114 C   FIELD 00w01 CTTRIGCTL_CTEN (rw): Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system. These cross triggers are connected to the respective timer trigger in of the other timer IPs in the SOC power domain. The timer cross trigger is essentially the combined logic of the HW and SW conditions controlling EN bit in the CTRCTL register.
0x40087114 C   FIELD 01w01 CTTRIGCTL_EVTCTEN (rw): Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path
0x40087114 C   FIELD 16w04 CTTRIGCTL_EVTCTTRIGSEL (rw): Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path
0x4008711C B  REGISTER CTTRIG (wo): Timer Cross Trigger Register
0x4008711C C   FIELD 00w01 CTTRIG_TRIG (wo): Generate Cross Trigger This bit when programmed will generate a synchronized trigger condition all the cross trigger enabled Timer instances including current timer instance.
0x40087800 B  REGISTER CTR (rw): Counter Register
0x40087800 C   FIELD 00w16 CTR_CCTR (rw): Current Counter value
0x40087804 B  REGISTER CTRCTL (rw): Counter Control Register
0x40087804 C   FIELD 00w01 CTRCTL_EN (rw): Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit, the counter value is set per the CVAE value. Hardware: This bit may also be set as the result of an LCOND or ZCOND condition being met and the counter value changed to the load value or zero value, respectively.
0x40087804 C   FIELD 01w03 CTRCTL_REPEAT (rw): Repeat. The repeat bit controls whether the counter continues to advance following a zero event, or the exiting of a debug or fault condition. If counting down, a zero event is followed by a load at the next advance condition. If counting up-down, a zero event is followed by an advance event (+1). The intent of encoding 3 is that if the debug condition is in effect, the generation of the load pulse is deferred until the debug condition is over. This allows the counter to reach zero before counting is suspended.
0x40087804 C   FIELD 04w02 CTRCTL_CM (rw): Count Mode
0x40087804 C   FIELD 07w03 CTRCTL_CLC (rw): Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved.
0x40087804 C   FIELD 10w03 CTRCTL_CAC (rw): Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved.
0x40087804 C   FIELD 13w03 CTRCTL_CZC (rw): Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved.
0x40087804 C   FIELD 17w01 CTRCTL_DRB (rw): Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode.
0x40087804 C   FIELD 28w02 CTRCTL_CVAE (rw): Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active.
0x40087808 B  REGISTER LOAD (rw): Load Register
0x40087808 C   FIELD 00w16 LOAD_LD (rw): Load Value
0x40087810 B  REGISTER CC_01[0] (rw): Capture or Compare Register 0 to Capture or Compare Register 1
0x40087810 C   FIELD 00w16 CC_01_CCVAL (rw): Capture or compare value
0x40087814 B  REGISTER CC_01[1] (rw): Capture or Compare Register 0 to Capture or Compare Register 1
0x40087814 C   FIELD 00w16 CC_01_CCVAL (rw): Capture or compare value
0x40087830 B  REGISTER CCCTL_01[0] (rw): Capture or Compare Control Registers
0x40087830 C   FIELD 00w03 CCCTL_01_CCOND (rw): Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved
0x40087830 C   FIELD 04w03 CCCTL_01_ACOND (rw): Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved
0x40087830 C   FIELD 08w03 CCCTL_01_LCOND (rw): Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved
0x40087830 C   FIELD 12w03 CCCTL_01_ZCOND (rw): Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved
0x40087830 C   FIELD 17w01 CCCTL_01_COC (rw): Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both).
0x40087830 C   FIELD 22w03 CCCTL_01_CC2SELU: Selects the source second CCU event.
0x40087830 C   FIELD 26w03 CCCTL_01_CCACTUPD (rw): CCACT shadow register Update Method This field controls how updates to the CCCACT shadow register are performed
0x40087830 C   FIELD 29w03 CCCTL_01_CC2SELD: Selects the source second CCD event.
0x40087834 B  REGISTER CCCTL_01[1] (rw): Capture or Compare Control Registers
0x40087834 C   FIELD 00w03 CCCTL_01_CCOND (rw): Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved
0x40087834 C   FIELD 04w03 CCCTL_01_ACOND (rw): Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved
0x40087834 C   FIELD 08w03 CCCTL_01_LCOND (rw): Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved
0x40087834 C   FIELD 12w03 CCCTL_01_ZCOND (rw): Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved
0x40087834 C   FIELD 17w01 CCCTL_01_COC (rw): Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both).
0x40087834 C   FIELD 22w03 CCCTL_01_CC2SELU: Selects the source second CCU event.
0x40087834 C   FIELD 26w03 CCCTL_01_CCACTUPD (rw): CCACT shadow register Update Method This field controls how updates to the CCCACT shadow register are performed
0x40087834 C   FIELD 29w03 CCCTL_01_CC2SELD: Selects the source second CCD event.
0x40087850 B  REGISTER OCTL_01[0] (rw): CCP Output Control Registers
0x40087850 C   FIELD 00w04 OCTL_01_CCPO (rw): CCP Output Source
0x40087850 C   FIELD 04w01 OCTL_01_CCPOINV (rw): CCP Output Invert The output as selected by CCPO is conditionally inverted.
0x40087850 C   FIELD 05w01 OCTL_01_CCPIV (rw): CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0).
0x40087854 B  REGISTER OCTL_01[1] (rw): CCP Output Control Registers
0x40087854 C   FIELD 00w04 OCTL_01_CCPO (rw): CCP Output Source
0x40087854 C   FIELD 04w01 OCTL_01_CCPOINV (rw): CCP Output Invert The output as selected by CCPO is conditionally inverted.
0x40087854 C   FIELD 05w01 OCTL_01_CCPIV (rw): CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0).
0x40087870 B  REGISTER CCACT_01[0] (rw): Capture or Compare Action Registers
0x40087870 C   FIELD 00w02 CCACT_01_ZACT (rw): CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event.
0x40087870 C   FIELD 03w02 CCACT_01_LACT (rw): CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event.
0x40087870 C   FIELD 06w02 CCACT_01_CDACT (rw): CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down.
0x40087870 C   FIELD 09w02 CCACT_01_CUACT (rw): CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up.
0x40087870 C   FIELD 12w02 CCACT_01_CC2DACT (rw): CCP Output Action on CC2D event.
0x40087870 C   FIELD 15w02 CCACT_01_CC2UACT (rw): CCP Output Action on CC2U event.
0x40087870 C   FIELD 28w02 CCACT_01_SWFRCACT (rw): CCP Output Action on Software Froce Output This field describes the resulting action of software force. This action has a shadow register, which will be updated under specific condition. So that this register cannot take into effect immediately.
0x40087874 B  REGISTER CCACT_01[1] (rw): Capture or Compare Action Registers
0x40087874 C   FIELD 00w02 CCACT_01_ZACT (rw): CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event.
0x40087874 C   FIELD 03w02 CCACT_01_LACT (rw): CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event.
0x40087874 C   FIELD 06w02 CCACT_01_CDACT (rw): CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down.
0x40087874 C   FIELD 09w02 CCACT_01_CUACT (rw): CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up.
0x40087874 C   FIELD 12w02 CCACT_01_CC2DACT (rw): CCP Output Action on CC2D event.
0x40087874 C   FIELD 15w02 CCACT_01_CC2UACT (rw): CCP Output Action on CC2U event.
0x40087874 C   FIELD 28w02 CCACT_01_SWFRCACT (rw): CCP Output Action on Software Froce Output This field describes the resulting action of software force. This action has a shadow register, which will be updated under specific condition. So that this register cannot take into effect immediately.
0x40087880 B  REGISTER IFCTL_01[0] (rw): Input Filter Control Register
0x40087880 C   FIELD 00w04 IFCTL_01_ISEL (rw): Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved
0x40087880 C   FIELD 07w01 IFCTL_01_INV (rw): Input Inversion This bit controls whether the selected input is inverted.
0x40087880 C   FIELD 08w02 IFCTL_01_FP (rw): Filter Period. This field specifies the sample period for the input filter. I.e. The input is sampled for FP timer clocks during filtering.
0x40087880 C   FIELD 11w01 IFCTL_01_CPV (rw): Consecutive Period/Voting Select This bit controls whether the input filter uses a stricter consecutive period count or majority voting.
0x40087880 C   FIELD 12w01 IFCTL_01_FE (rw): Filter Enable This bit controls whether the input is filtered by the input filter or bypasses to the edge detect.
0x40087884 B  REGISTER IFCTL_01[1] (rw): Input Filter Control Register
0x40087884 C   FIELD 00w04 IFCTL_01_ISEL (rw): Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved
0x40087884 C   FIELD 07w01 IFCTL_01_INV (rw): Input Inversion This bit controls whether the selected input is inverted.
0x40087884 C   FIELD 08w02 IFCTL_01_FP (rw): Filter Period. This field specifies the sample period for the input filter. I.e. The input is sampled for FP timer clocks during filtering.
0x40087884 C   FIELD 11w01 IFCTL_01_CPV (rw): Consecutive Period/Voting Select This bit controls whether the input filter uses a stricter consecutive period count or majority voting.
0x40087884 C   FIELD 12w01 IFCTL_01_FE (rw): Filter Enable This bit controls whether the input is filtered by the input filter or bypasses to the edge detect.
0x400878B0 B  REGISTER TSEL (rw): Trigger Select
0x400878B0 C   FIELD 00w05 TSEL_ETSEL (rw): External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger. Triggers 0-15 are used to connect triggers generated by other timer modules in the same power domain. Refer to the SoC datasheet to get details. Triggers 16 and 17 are connected to event manager subscriber ports. Event lines 18-31 are reserved for future use.
0x400878B0 C   FIELD 09w01 TSEL_TE (rw): Trigger Enable. This selects whether a trigger is enabled or not for this counter 0x0 = Triggers are not used 0x1 = Triggers are used as selected by the ETSEL field
0x40088000 A PERIPHERAL TIMG2
0x40088400 B  REGISTER FSUB_0 (rw): Subsciber Port 0
0x40088400 C   FIELD 00w02 FSUB_0_CHANID: 0 = disconnected. 1-15 = connected to channelID = CHANID.
0x40088404 B  REGISTER FSUB_1 (rw): Subscriber Port 1
0x40088404 C   FIELD 00w02 FSUB_1_CHANID: 0 = disconnected. 1-15 = connected to channelID = CHANID.
0x40088444 B  REGISTER FPUB_0 (rw): Publisher Port 0
0x40088444 C   FIELD 00w02 FPUB_0_CHANID: 0 = disconnected. 1-15 = connected to channelID = CHANID.
0x40088448 B  REGISTER FPUB_1 (rw): Publisher Port 1
0x40088448 C   FIELD 00w02 FPUB_1_CHANID: 0 = disconnected. 1-15 = connected to channelID = CHANID.
0x40088800 B  REGISTER PWREN (rw): Power enable
0x40088800 C   FIELD 00w01 PWREN_ENABLE: Enable the power
0x40088800 C   FIELD 24w08 PWREN_KEY (wo): KEY to allow Power State Change
0x40088804 B  REGISTER RSTCTL (wo): Reset Control
0x40088804 C   FIELD 00w01 RSTCTL_RESETASSERT (wo): Assert reset to the peripheral
0x40088804 C   FIELD 01w01 RSTCTL_RESETSTKYCLR (wo): Clear the RESETSTKY bit in the STAT register
0x40088804 C   FIELD 24w08 RSTCTL_KEY (wo): Unlock key
0x40088814 B  REGISTER STAT (ro): Status Register
0x40088814 C   FIELD 16w01 STAT_RESETSTKY (ro): This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register
0x40089000 B  REGISTER CLKDIV (rw): Clock Divider
0x40089000 C   FIELD 00w03 CLKDIV_RATIO: Selects divide ratio of module clock
0x40089008 B  REGISTER CLKSEL (rw): Clock Select for Ultra Low Power peripherals
0x40089008 C   FIELD 01w01 CLKSEL_LFCLK_SEL (rw): Selects LFCLK as clock source if enabled
0x40089008 C   FIELD 02w01 CLKSEL_MFCLK_SEL (rw): Selects MFCLK as clock source if enabled
0x40089008 C   FIELD 03w01 CLKSEL_BUSCLK_SEL (rw): Selects BUSCLK as clock source if enabled
0x40089018 B  REGISTER PDBGCTL (rw): Peripheral Debug Control
0x40089018 C   FIELD 00w01 PDBGCTL_FREE (rw): Free run control
0x40089018 C   FIELD 01w01 PDBGCTL_SOFT (rw): Soft halt boundary control. This function is only available, if [FREE] is set to 'STOP'
0x40089020 B  REGISTER IIDX (ro): Interrupt index
0x40089020 C   FIELD 00w08 IIDX_STAT (ro): Interrupt index status
0x40089028 B  REGISTER IMASK (rw): Interrupt mask
0x40089028 C   FIELD 00w01 IMASK_Z: Zero Event mask
0x40089028 C   FIELD 01w01 IMASK_L: Load Event mask
0x40089028 C   FIELD 04w01 IMASK_CCD0: Capture or Compare DN event mask CCP0
0x40089028 C   FIELD 05w01 IMASK_CCD1: Capture or Compare DN event mask CCP1
0x40089028 C   FIELD 08w01 IMASK_CCU0: Capture or Compare UP event mask CCP0
0x40089028 C   FIELD 09w01 IMASK_CCU1: Capture or Compare UP event mask CCP1
0x40089028 C   FIELD 25w01 IMASK_TOV: Trigger Overflow Event mask
0x40089030 B  REGISTER RIS (ro): Raw interrupt status
0x40089030 C   FIELD 00w01 RIS_Z: Zero event generated an interrupt.
0x40089030 C   FIELD 01w01 RIS_L: Load event generated an interrupt.
0x40089030 C   FIELD 04w01 RIS_CCD0: Capture or compare down event generated an interrupt CCP0
0x40089030 C   FIELD 05w01 RIS_CCD1: Capture or compare down event generated an interrupt CCP1
0x40089030 C   FIELD 08w01 RIS_CCU0: Capture or compare up event generated an interrupt CCP0
0x40089030 C   FIELD 09w01 RIS_CCU1: Capture or compare up event generated an interrupt CCP1
0x40089030 C   FIELD 25w01 RIS_TOV: Trigger overflow
0x40089038 B  REGISTER MIS (ro): Masked interrupt status
0x40089038 C   FIELD 00w01 MIS_Z: Zero event generated an interrupt.
0x40089038 C   FIELD 01w01 MIS_L: Load event generated an interrupt.
0x40089038 C   FIELD 04w01 MIS_CCD0: Capture or compare down event generated an interrupt CCP0
0x40089038 C   FIELD 05w01 MIS_CCD1: Capture or compare down event generated an interrupt CCP1
0x40089038 C   FIELD 08w01 MIS_CCU0: Capture or compare up event generated an interrupt CCP0
0x40089038 C   FIELD 09w01 MIS_CCU1: Capture or compare up event generated an interrupt CCP1
0x40089038 C   FIELD 25w01 MIS_TOV: Trigger overflow
0x40089040 B  REGISTER ISET (wo): Interrupt set
0x40089040 C   FIELD 00w01 ISET_Z: Zero event SET
0x40089040 C   FIELD 01w01 ISET_L: Load event SET
0x40089040 C   FIELD 04w01 ISET_CCD0: Capture or compare down event SET
0x40089040 C   FIELD 05w01 ISET_CCD1: Capture or compare down event SET
0x40089040 C   FIELD 08w01 ISET_CCU0: Capture or compare up event SET
0x40089040 C   FIELD 09w01 ISET_CCU1: Capture or compare up event SET
0x40089040 C   FIELD 25w01 ISET_TOV: Trigger Overflow event SET
0x40089048 B  REGISTER ICLR (wo): Interrupt clear
0x40089048 C   FIELD 00w01 ICLR_Z: Zero event CLEAR
0x40089048 C   FIELD 01w01 ICLR_L: Load event CLEAR
0x40089048 C   FIELD 04w01 ICLR_CCD0: Capture or compare down event CLEAR
0x40089048 C   FIELD 05w01 ICLR_CCD1: Capture or compare down event CLEAR
0x40089048 C   FIELD 08w01 ICLR_CCU0: Capture or compare up event CLEAR
0x40089048 C   FIELD 09w01 ICLR_CCU1: Capture or compare up event CLEAR
0x40089048 C   FIELD 25w01 ICLR_TOV: Trigger Overflow event CLEAR
0x400890E0 B  REGISTER EVT_MODE (rw): Event Mode
0x400890E0 C   FIELD 00w02 EVT_MODE_EVT0_CFG (ro): Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]
0x400890E0 C   FIELD 02w02 EVT_MODE_EVT1_CFG (ro): Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]
0x400890E0 C   FIELD 04w02 EVT_MODE_EVT2_CFG (ro): Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]
0x400890FC B  REGISTER DESC (ro): Module Description
0x400890FC C   FIELD 00w04 DESC_MINREV: Minor rev of the IP
0x400890FC C   FIELD 04w04 DESC_MAJREV: Major rev of the IP
0x400890FC C   FIELD 08w04 DESC_INSTNUM: Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances
0x400890FC C   FIELD 12w04 DESC_FEATUREVER: Feature Set for the module *instance*
0x400890FC C   FIELD 16w16 DESC_MODULEID: Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness.
0x40089100 B  REGISTER CCPD (rw): CCP Direction
0x40089100 C   FIELD 00w01 CCPD_C0CCP0: Counter CCP0
0x40089100 C   FIELD 01w01 CCPD_C0CCP1: Counter CCP1
0x40089104 B  REGISTER ODIS (rw): Output Disable
0x40089104 C   FIELD 00w01 ODIS_C0CCP0 (rw): Counter CCP0 Disable Mask Defines whether CCP0 of Counter n is forced low or not
0x40089104 C   FIELD 01w01 ODIS_C0CCP1 (rw): Counter CCP1 Disable Mask Defines whether CCP0 of Counter n is forced low or not
0x40089108 B  REGISTER CCLKCTL (rw): Counter Clock Control Register
0x40089108 C   FIELD 00w01 CCLKCTL_CLKEN (rw): Clock Enable Disables the clock gating to the module. SW has to explicitly program the value to 0 to gate the clock.
0x4008910C B  REGISTER CPS (rw): Clock Prescale Register
0x4008910C C   FIELD 00w08 CPS_PCNT (rw): Pre-Scale Count This field specifies the pre-scale count value. The selected TIMCLK source is divided by a value of (PCNT+1). A PCNT value of 0 divides TIMCLK by 1, effectively bypassing the divider. A PCNT value of greater than 0 divides the TIMCLK source generating a slower clock
0x40089110 B  REGISTER CPSV (ro): Clock prescale count status register
0x40089110 C   FIELD 00w08 CPSV_CPSVAL (ro): Current Prescale Count Value
0x40089114 B  REGISTER CTTRIGCTL (rw): Timer Cross Trigger Control Register
0x40089114 C   FIELD 00w01 CTTRIGCTL_CTEN (rw): Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system. These cross triggers are connected to the respective timer trigger in of the other timer IPs in the SOC power domain. The timer cross trigger is essentially the combined logic of the HW and SW conditions controlling EN bit in the CTRCTL register.
0x40089114 C   FIELD 01w01 CTTRIGCTL_EVTCTEN (rw): Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path
0x40089114 C   FIELD 16w04 CTTRIGCTL_EVTCTTRIGSEL (rw): Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path
0x4008911C B  REGISTER CTTRIG (wo): Timer Cross Trigger Register
0x4008911C C   FIELD 00w01 CTTRIG_TRIG (wo): Generate Cross Trigger This bit when programmed will generate a synchronized trigger condition all the cross trigger enabled Timer instances including current timer instance.
0x40089800 B  REGISTER CTR (rw): Counter Register
0x40089800 C   FIELD 00w16 CTR_CCTR (rw): Current Counter value
0x40089804 B  REGISTER CTRCTL (rw): Counter Control Register
0x40089804 C   FIELD 00w01 CTRCTL_EN (rw): Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit, the counter value is set per the CVAE value. Hardware: This bit may also be set as the result of an LCOND or ZCOND condition being met and the counter value changed to the load value or zero value, respectively.
0x40089804 C   FIELD 01w03 CTRCTL_REPEAT (rw): Repeat. The repeat bit controls whether the counter continues to advance following a zero event, or the exiting of a debug or fault condition. If counting down, a zero event is followed by a load at the next advance condition. If counting up-down, a zero event is followed by an advance event (+1). The intent of encoding 3 is that if the debug condition is in effect, the generation of the load pulse is deferred until the debug condition is over. This allows the counter to reach zero before counting is suspended.
0x40089804 C   FIELD 04w02 CTRCTL_CM (rw): Count Mode
0x40089804 C   FIELD 07w03 CTRCTL_CLC (rw): Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved.
0x40089804 C   FIELD 10w03 CTRCTL_CAC (rw): Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved.
0x40089804 C   FIELD 13w03 CTRCTL_CZC (rw): Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved.
0x40089804 C   FIELD 17w01 CTRCTL_DRB (rw): Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode.
0x40089804 C   FIELD 28w02 CTRCTL_CVAE (rw): Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active.
0x40089808 B  REGISTER LOAD (rw): Load Register
0x40089808 C   FIELD 00w16 LOAD_LD (rw): Load Value
0x40089810 B  REGISTER CC_01[0] (rw): Capture or Compare Register 0 to Capture or Compare Register 1
0x40089810 C   FIELD 00w16 CC_01_CCVAL (rw): Capture or compare value
0x40089814 B  REGISTER CC_01[1] (rw): Capture or Compare Register 0 to Capture or Compare Register 1
0x40089814 C   FIELD 00w16 CC_01_CCVAL (rw): Capture or compare value
0x40089830 B  REGISTER CCCTL_01[0] (rw): Capture or Compare Control Registers
0x40089830 C   FIELD 00w03 CCCTL_01_CCOND (rw): Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved
0x40089830 C   FIELD 04w03 CCCTL_01_ACOND (rw): Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved
0x40089830 C   FIELD 08w03 CCCTL_01_LCOND (rw): Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved
0x40089830 C   FIELD 12w03 CCCTL_01_ZCOND (rw): Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved
0x40089830 C   FIELD 17w01 CCCTL_01_COC (rw): Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both).
0x40089830 C   FIELD 22w03 CCCTL_01_CC2SELU: Selects the source second CCU event.
0x40089830 C   FIELD 26w03 CCCTL_01_CCACTUPD (rw): CCACT shadow register Update Method This field controls how updates to the CCCACT shadow register are performed
0x40089830 C   FIELD 29w03 CCCTL_01_CC2SELD: Selects the source second CCD event.
0x40089834 B  REGISTER CCCTL_01[1] (rw): Capture or Compare Control Registers
0x40089834 C   FIELD 00w03 CCCTL_01_CCOND (rw): Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved
0x40089834 C   FIELD 04w03 CCCTL_01_ACOND (rw): Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved
0x40089834 C   FIELD 08w03 CCCTL_01_LCOND (rw): Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved
0x40089834 C   FIELD 12w03 CCCTL_01_ZCOND (rw): Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved
0x40089834 C   FIELD 17w01 CCCTL_01_COC (rw): Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both).
0x40089834 C   FIELD 22w03 CCCTL_01_CC2SELU: Selects the source second CCU event.
0x40089834 C   FIELD 26w03 CCCTL_01_CCACTUPD (rw): CCACT shadow register Update Method This field controls how updates to the CCCACT shadow register are performed
0x40089834 C   FIELD 29w03 CCCTL_01_CC2SELD: Selects the source second CCD event.
0x40089850 B  REGISTER OCTL_01[0] (rw): CCP Output Control Registers
0x40089850 C   FIELD 00w04 OCTL_01_CCPO (rw): CCP Output Source
0x40089850 C   FIELD 04w01 OCTL_01_CCPOINV (rw): CCP Output Invert The output as selected by CCPO is conditionally inverted.
0x40089850 C   FIELD 05w01 OCTL_01_CCPIV (rw): CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0).
0x40089854 B  REGISTER OCTL_01[1] (rw): CCP Output Control Registers
0x40089854 C   FIELD 00w04 OCTL_01_CCPO (rw): CCP Output Source
0x40089854 C   FIELD 04w01 OCTL_01_CCPOINV (rw): CCP Output Invert The output as selected by CCPO is conditionally inverted.
0x40089854 C   FIELD 05w01 OCTL_01_CCPIV (rw): CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0).
0x40089870 B  REGISTER CCACT_01[0] (rw): Capture or Compare Action Registers
0x40089870 C   FIELD 00w02 CCACT_01_ZACT (rw): CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event.
0x40089870 C   FIELD 03w02 CCACT_01_LACT (rw): CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event.
0x40089870 C   FIELD 06w02 CCACT_01_CDACT (rw): CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down.
0x40089870 C   FIELD 09w02 CCACT_01_CUACT (rw): CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up.
0x40089870 C   FIELD 12w02 CCACT_01_CC2DACT (rw): CCP Output Action on CC2D event.
0x40089870 C   FIELD 15w02 CCACT_01_CC2UACT (rw): CCP Output Action on CC2U event.
0x40089870 C   FIELD 28w02 CCACT_01_SWFRCACT (rw): CCP Output Action on Software Froce Output This field describes the resulting action of software force. This action has a shadow register, which will be updated under specific condition. So that this register cannot take into effect immediately.
0x40089874 B  REGISTER CCACT_01[1] (rw): Capture or Compare Action Registers
0x40089874 C   FIELD 00w02 CCACT_01_ZACT (rw): CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event.
0x40089874 C   FIELD 03w02 CCACT_01_LACT (rw): CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event.
0x40089874 C   FIELD 06w02 CCACT_01_CDACT (rw): CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down.
0x40089874 C   FIELD 09w02 CCACT_01_CUACT (rw): CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up.
0x40089874 C   FIELD 12w02 CCACT_01_CC2DACT (rw): CCP Output Action on CC2D event.
0x40089874 C   FIELD 15w02 CCACT_01_CC2UACT (rw): CCP Output Action on CC2U event.
0x40089874 C   FIELD 28w02 CCACT_01_SWFRCACT (rw): CCP Output Action on Software Froce Output This field describes the resulting action of software force. This action has a shadow register, which will be updated under specific condition. So that this register cannot take into effect immediately.
0x40089880 B  REGISTER IFCTL_01[0] (rw): Input Filter Control Register
0x40089880 C   FIELD 00w04 IFCTL_01_ISEL (rw): Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved
0x40089880 C   FIELD 07w01 IFCTL_01_INV (rw): Input Inversion This bit controls whether the selected input is inverted.
0x40089880 C   FIELD 08w02 IFCTL_01_FP (rw): Filter Period. This field specifies the sample period for the input filter. I.e. The input is sampled for FP timer clocks during filtering.
0x40089880 C   FIELD 11w01 IFCTL_01_CPV (rw): Consecutive Period/Voting Select This bit controls whether the input filter uses a stricter consecutive period count or majority voting.
0x40089880 C   FIELD 12w01 IFCTL_01_FE (rw): Filter Enable This bit controls whether the input is filtered by the input filter or bypasses to the edge detect.
0x40089884 B  REGISTER IFCTL_01[1] (rw): Input Filter Control Register
0x40089884 C   FIELD 00w04 IFCTL_01_ISEL (rw): Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved
0x40089884 C   FIELD 07w01 IFCTL_01_INV (rw): Input Inversion This bit controls whether the selected input is inverted.
0x40089884 C   FIELD 08w02 IFCTL_01_FP (rw): Filter Period. This field specifies the sample period for the input filter. I.e. The input is sampled for FP timer clocks during filtering.
0x40089884 C   FIELD 11w01 IFCTL_01_CPV (rw): Consecutive Period/Voting Select This bit controls whether the input filter uses a stricter consecutive period count or majority voting.
0x40089884 C   FIELD 12w01 IFCTL_01_FE (rw): Filter Enable This bit controls whether the input is filtered by the input filter or bypasses to the edge detect.
0x400898B0 B  REGISTER TSEL (rw): Trigger Select
0x400898B0 C   FIELD 00w05 TSEL_ETSEL (rw): External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger. Triggers 0-15 are used to connect triggers generated by other timer modules in the same power domain. Refer to the SoC datasheet to get details. Triggers 16 and 17 are connected to event manager subscriber ports. Event lines 18-31 are reserved for future use.
0x400898B0 C   FIELD 09w01 TSEL_TE (rw): Trigger Enable. This selects whether a trigger is enabled or not for this counter 0x0 = Triggers are not used 0x1 = Triggers are used as selected by the ETSEL field
0x4008C000 A PERIPHERAL TIMG4
0x4008C400 B  REGISTER FSUB_0 (rw): Subsciber Port 0
0x4008C400 C   FIELD 00w02 FSUB_0_CHANID: 0 = disconnected. 1-15 = connected to channelID = CHANID.
0x4008C404 B  REGISTER FSUB_1 (rw): Subscriber Port 1
0x4008C404 C   FIELD 00w02 FSUB_1_CHANID: 0 = disconnected. 1-15 = connected to channelID = CHANID.
0x4008C444 B  REGISTER FPUB_0 (rw): Publisher Port 0
0x4008C444 C   FIELD 00w02 FPUB_0_CHANID: 0 = disconnected. 1-15 = connected to channelID = CHANID.
0x4008C448 B  REGISTER FPUB_1 (rw): Publisher Port 1
0x4008C448 C   FIELD 00w02 FPUB_1_CHANID: 0 = disconnected. 1-15 = connected to channelID = CHANID.
0x4008C800 B  REGISTER PWREN (rw): Power enable
0x4008C800 C   FIELD 00w01 PWREN_ENABLE: Enable the power
0x4008C800 C   FIELD 24w08 PWREN_KEY (wo): KEY to allow Power State Change
0x4008C804 B  REGISTER RSTCTL (wo): Reset Control
0x4008C804 C   FIELD 00w01 RSTCTL_RESETASSERT (wo): Assert reset to the peripheral
0x4008C804 C   FIELD 01w01 RSTCTL_RESETSTKYCLR (wo): Clear the RESETSTKY bit in the STAT register
0x4008C804 C   FIELD 24w08 RSTCTL_KEY (wo): Unlock key
0x4008C814 B  REGISTER STAT (ro): Status Register
0x4008C814 C   FIELD 16w01 STAT_RESETSTKY (ro): This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register
0x4008D000 B  REGISTER CLKDIV (rw): Clock Divider
0x4008D000 C   FIELD 00w03 CLKDIV_RATIO: Selects divide ratio of module clock
0x4008D008 B  REGISTER CLKSEL (rw): Clock Select for Ultra Low Power peripherals
0x4008D008 C   FIELD 01w01 CLKSEL_LFCLK_SEL (rw): Selects LFCLK as clock source if enabled
0x4008D008 C   FIELD 02w01 CLKSEL_MFCLK_SEL (rw): Selects MFCLK as clock source if enabled
0x4008D008 C   FIELD 03w01 CLKSEL_BUSCLK_SEL (rw): Selects BUSCLK as clock source if enabled
0x4008D018 B  REGISTER PDBGCTL (rw): Peripheral Debug Control
0x4008D018 C   FIELD 00w01 PDBGCTL_FREE (rw): Free run control
0x4008D018 C   FIELD 01w01 PDBGCTL_SOFT (rw): Soft halt boundary control. This function is only available, if [FREE] is set to 'STOP'
0x4008D020 B  REGISTER IIDX (ro): Interrupt index
0x4008D020 C   FIELD 00w08 IIDX_STAT (ro): Interrupt index status
0x4008D028 B  REGISTER IMASK (rw): Interrupt mask
0x4008D028 C   FIELD 00w01 IMASK_Z: Zero Event mask
0x4008D028 C   FIELD 01w01 IMASK_L: Load Event mask
0x4008D028 C   FIELD 04w01 IMASK_CCD0: Capture or Compare DN event mask CCP0
0x4008D028 C   FIELD 05w01 IMASK_CCD1: Capture or Compare DN event mask CCP1
0x4008D028 C   FIELD 08w01 IMASK_CCU0: Capture or Compare UP event mask CCP0
0x4008D028 C   FIELD 09w01 IMASK_CCU1: Capture or Compare UP event mask CCP1
0x4008D028 C   FIELD 25w01 IMASK_TOV: Trigger Overflow Event mask
0x4008D030 B  REGISTER RIS (ro): Raw interrupt status
0x4008D030 C   FIELD 00w01 RIS_Z: Zero event generated an interrupt.
0x4008D030 C   FIELD 01w01 RIS_L: Load event generated an interrupt.
0x4008D030 C   FIELD 04w01 RIS_CCD0: Capture or compare down event generated an interrupt CCP0
0x4008D030 C   FIELD 05w01 RIS_CCD1: Capture or compare down event generated an interrupt CCP1
0x4008D030 C   FIELD 08w01 RIS_CCU0: Capture or compare up event generated an interrupt CCP0
0x4008D030 C   FIELD 09w01 RIS_CCU1: Capture or compare up event generated an interrupt CCP1
0x4008D030 C   FIELD 25w01 RIS_TOV: Trigger overflow
0x4008D038 B  REGISTER MIS (ro): Masked interrupt status
0x4008D038 C   FIELD 00w01 MIS_Z: Zero event generated an interrupt.
0x4008D038 C   FIELD 01w01 MIS_L: Load event generated an interrupt.
0x4008D038 C   FIELD 04w01 MIS_CCD0: Capture or compare down event generated an interrupt CCP0
0x4008D038 C   FIELD 05w01 MIS_CCD1: Capture or compare down event generated an interrupt CCP1
0x4008D038 C   FIELD 08w01 MIS_CCU0: Capture or compare up event generated an interrupt CCP0
0x4008D038 C   FIELD 09w01 MIS_CCU1: Capture or compare up event generated an interrupt CCP1
0x4008D038 C   FIELD 12w01 MIS_CCD4: Compare down event generated an interrupt CCP4
0x4008D038 C   FIELD 13w01 MIS_CCD5: Compare down event generated an interrupt CCP5
0x4008D038 C   FIELD 14w01 MIS_CCU4: Compare up event generated an interrupt CCP4
0x4008D038 C   FIELD 15w01 MIS_CCU5: Compare up event generated an interrupt CCP5
0x4008D038 C   FIELD 25w01 MIS_TOV: Trigger overflow
0x4008D040 B  REGISTER ISET (wo): Interrupt set
0x4008D040 C   FIELD 00w01 ISET_Z: Zero event SET
0x4008D040 C   FIELD 01w01 ISET_L: Load event SET
0x4008D040 C   FIELD 04w01 ISET_CCD0: Capture or compare down event SET
0x4008D040 C   FIELD 05w01 ISET_CCD1: Capture or compare down event SET
0x4008D040 C   FIELD 08w01 ISET_CCU0: Capture or compare up event SET
0x4008D040 C   FIELD 09w01 ISET_CCU1: Capture or compare up event SET
0x4008D040 C   FIELD 25w01 ISET_TOV: Trigger Overflow event SET
0x4008D048 B  REGISTER ICLR (wo): Interrupt clear
0x4008D048 C   FIELD 00w01 ICLR_Z: Zero event CLEAR
0x4008D048 C   FIELD 01w01 ICLR_L: Load event CLEAR
0x4008D048 C   FIELD 04w01 ICLR_CCD0: Capture or compare down event CLEAR
0x4008D048 C   FIELD 05w01 ICLR_CCD1: Capture or compare down event CLEAR
0x4008D048 C   FIELD 08w01 ICLR_CCU0: Capture or compare up event CLEAR
0x4008D048 C   FIELD 09w01 ICLR_CCU1: Capture or compare up event CLEAR
0x4008D048 C   FIELD 25w01 ICLR_TOV: Trigger Overflow event CLEAR
0x4008D0E0 B  REGISTER EVT_MODE (rw): Event Mode
0x4008D0E0 C   FIELD 00w02 EVT_MODE_EVT0_CFG (ro): Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]
0x4008D0E0 C   FIELD 02w02 EVT_MODE_EVT1_CFG (ro): Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]
0x4008D0E0 C   FIELD 04w02 EVT_MODE_EVT2_CFG (ro): Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]
0x4008D0FC B  REGISTER DESC (ro): Module Description
0x4008D0FC C   FIELD 00w04 DESC_MINREV: Minor rev of the IP
0x4008D0FC C   FIELD 04w04 DESC_MAJREV: Major rev of the IP
0x4008D0FC C   FIELD 08w04 DESC_INSTNUM: Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances
0x4008D0FC C   FIELD 12w04 DESC_FEATUREVER: Feature Set for the module *instance*
0x4008D0FC C   FIELD 16w16 DESC_MODULEID: Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness.
0x4008D100 B  REGISTER CCPD (rw): CCP Direction
0x4008D100 C   FIELD 00w01 CCPD_C0CCP0: Counter CCP0
0x4008D100 C   FIELD 01w01 CCPD_C0CCP1: Counter CCP1
0x4008D104 B  REGISTER ODIS (rw): Output Disable
0x4008D104 C   FIELD 00w01 ODIS_C0CCP0 (rw): Counter CCP0 Disable Mask Defines whether CCP0 of Counter n is forced low or not
0x4008D104 C   FIELD 01w01 ODIS_C0CCP1 (rw): Counter CCP1 Disable Mask Defines whether CCP0 of Counter n is forced low or not
0x4008D108 B  REGISTER CCLKCTL (rw): Counter Clock Control Register
0x4008D108 C   FIELD 00w01 CCLKCTL_CLKEN (rw): Clock Enable Disables the clock gating to the module. SW has to explicitly program the value to 0 to gate the clock.
0x4008D10C B  REGISTER CPS (rw): Clock Prescale Register
0x4008D10C C   FIELD 00w08 CPS_PCNT (rw): Pre-Scale Count This field specifies the pre-scale count value. The selected TIMCLK source is divided by a value of (PCNT+1). A PCNT value of 0 divides TIMCLK by 1, effectively bypassing the divider. A PCNT value of greater than 0 divides the TIMCLK source generating a slower clock
0x4008D110 B  REGISTER CPSV (ro): Clock prescale count status register
0x4008D110 C   FIELD 00w08 CPSV_CPSVAL (ro): Current Prescale Count Value
0x4008D114 B  REGISTER CTTRIGCTL (rw): Timer Cross Trigger Control Register
0x4008D114 C   FIELD 00w01 CTTRIGCTL_CTEN (rw): Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system. These cross triggers are connected to the respective timer trigger in of the other timer IPs in the SOC power domain. The timer cross trigger is essentially the combined logic of the HW and SW conditions controlling EN bit in the CTRCTL register.
0x4008D114 C   FIELD 01w01 CTTRIGCTL_EVTCTEN (rw): Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path
0x4008D114 C   FIELD 16w04 CTTRIGCTL_EVTCTTRIGSEL (rw): Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path
0x4008D11C B  REGISTER CTTRIG (wo): Timer Cross Trigger Register
0x4008D11C C   FIELD 00w01 CTTRIG_TRIG (wo): Generate Cross Trigger This bit when programmed will generate a synchronized trigger condition all the cross trigger enabled Timer instances including current timer instance.
0x4008D124 B  REGISTER GCTL (rw): Shadow to active load mask
0x4008D124 C   FIELD 00w01 GCTL_SHDWLDEN (rw): Enables shadow to active load of bufferred registers and register fields.
0x4008D800 B  REGISTER CTR (rw): Counter Register
0x4008D800 C   FIELD 00w16 CTR_CCTR (rw): Current Counter value
0x4008D804 B  REGISTER CTRCTL (rw): Counter Control Register
0x4008D804 C   FIELD 00w01 CTRCTL_EN (rw): Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit, the counter value is set per the CVAE value. Hardware: This bit may also be set as the result of an LCOND or ZCOND condition being met and the counter value changed to the load value or zero value, respectively.
0x4008D804 C   FIELD 01w03 CTRCTL_REPEAT (rw): Repeat. The repeat bit controls whether the counter continues to advance following a zero event, or the exiting of a debug or fault condition. If counting down, a zero event is followed by a load at the next advance condition. If counting up-down, a zero event is followed by an advance event (+1). The intent of encoding 3 is that if the debug condition is in effect, the generation of the load pulse is deferred until the debug condition is over. This allows the counter to reach zero before counting is suspended.
0x4008D804 C   FIELD 04w02 CTRCTL_CM (rw): Count Mode
0x4008D804 C   FIELD 07w03 CTRCTL_CLC (rw): Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved.
0x4008D804 C   FIELD 10w03 CTRCTL_CAC (rw): Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved.
0x4008D804 C   FIELD 13w03 CTRCTL_CZC (rw): Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved.
0x4008D804 C   FIELD 17w01 CTRCTL_DRB (rw): Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode.
0x4008D804 C   FIELD 28w02 CTRCTL_CVAE (rw): Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active.
0x4008D808 B  REGISTER LOAD (rw): Load Register
0x4008D808 C   FIELD 00w16 LOAD_LD (rw): Load Value
0x4008D810 B  REGISTER CC_01[0] (rw): Capture or Compare Register 0 to Capture or Compare Register 1
0x4008D810 C   FIELD 00w16 CC_01_CCVAL (rw): Capture or compare value
0x4008D814 B  REGISTER CC_01[1] (rw): Capture or Compare Register 0 to Capture or Compare Register 1
0x4008D814 C   FIELD 00w16 CC_01_CCVAL (rw): Capture or compare value
0x4008D830 B  REGISTER CCCTL_01[0] (rw): Capture or Compare Control Registers
0x4008D830 C   FIELD 00w03 CCCTL_01_CCOND (rw): Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved
0x4008D830 C   FIELD 04w03 CCCTL_01_ACOND (rw): Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved
0x4008D830 C   FIELD 08w03 CCCTL_01_LCOND (rw): Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved
0x4008D830 C   FIELD 12w03 CCCTL_01_ZCOND (rw): Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved
0x4008D830 C   FIELD 17w01 CCCTL_01_COC (rw): Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both).
0x4008D830 C   FIELD 18w03 CCCTL_01_CCUPD (rw): Capture and Compare Update Method This field controls how updates to the pipelined capture and compare register are performed (when operating in compare mode, COC=0).
0x4008D830 C   FIELD 22w03 CCCTL_01_CC2SELU: Selects the source second CCU event.
0x4008D830 C   FIELD 26w03 CCCTL_01_CCACTUPD (rw): CCACT shadow register Update Method This field controls how updates to the CCCACT shadow register are performed
0x4008D830 C   FIELD 29w03 CCCTL_01_CC2SELD: Selects the source second CCD event.
0x4008D834 B  REGISTER CCCTL_01[1] (rw): Capture or Compare Control Registers
0x4008D834 C   FIELD 00w03 CCCTL_01_CCOND (rw): Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved
0x4008D834 C   FIELD 04w03 CCCTL_01_ACOND (rw): Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved
0x4008D834 C   FIELD 08w03 CCCTL_01_LCOND (rw): Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved
0x4008D834 C   FIELD 12w03 CCCTL_01_ZCOND (rw): Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved
0x4008D834 C   FIELD 17w01 CCCTL_01_COC (rw): Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both).
0x4008D834 C   FIELD 18w03 CCCTL_01_CCUPD (rw): Capture and Compare Update Method This field controls how updates to the pipelined capture and compare register are performed (when operating in compare mode, COC=0).
0x4008D834 C   FIELD 22w03 CCCTL_01_CC2SELU: Selects the source second CCU event.
0x4008D834 C   FIELD 26w03 CCCTL_01_CCACTUPD (rw): CCACT shadow register Update Method This field controls how updates to the CCCACT shadow register are performed
0x4008D834 C   FIELD 29w03 CCCTL_01_CC2SELD: Selects the source second CCD event.
0x4008D850 B  REGISTER OCTL_01[0] (rw): CCP Output Control Registers
0x4008D850 C   FIELD 00w04 OCTL_01_CCPO (rw): CCP Output Source
0x4008D850 C   FIELD 04w01 OCTL_01_CCPOINV (rw): CCP Output Invert The output as selected by CCPO is conditionally inverted.
0x4008D850 C   FIELD 05w01 OCTL_01_CCPIV (rw): CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0).
0x4008D854 B  REGISTER OCTL_01[1] (rw): CCP Output Control Registers
0x4008D854 C   FIELD 00w04 OCTL_01_CCPO (rw): CCP Output Source
0x4008D854 C   FIELD 04w01 OCTL_01_CCPOINV (rw): CCP Output Invert The output as selected by CCPO is conditionally inverted.
0x4008D854 C   FIELD 05w01 OCTL_01_CCPIV (rw): CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0).
0x4008D870 B  REGISTER CCACT_01[0] (rw): Capture or Compare Action Registers
0x4008D870 C   FIELD 00w02 CCACT_01_ZACT (rw): CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event.
0x4008D870 C   FIELD 03w02 CCACT_01_LACT (rw): CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event.
0x4008D870 C   FIELD 06w02 CCACT_01_CDACT (rw): CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down.
0x4008D870 C   FIELD 09w02 CCACT_01_CUACT (rw): CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up.
0x4008D870 C   FIELD 12w02 CCACT_01_CC2DACT (rw): CCP Output Action on CC2D event.
0x4008D870 C   FIELD 15w02 CCACT_01_CC2UACT (rw): CCP Output Action on CC2U event.
0x4008D870 C   FIELD 28w02 CCACT_01_SWFRCACT (rw): CCP Output Action on Software Froce Output This field describes the resulting action of software force. This action has a shadow register, which will be updated under specific condition. So that this register cannot take into effect immediately.
0x4008D874 B  REGISTER CCACT_01[1] (rw): Capture or Compare Action Registers
0x4008D874 C   FIELD 00w02 CCACT_01_ZACT (rw): CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event.
0x4008D874 C   FIELD 03w02 CCACT_01_LACT (rw): CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event.
0x4008D874 C   FIELD 06w02 CCACT_01_CDACT (rw): CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down.
0x4008D874 C   FIELD 09w02 CCACT_01_CUACT (rw): CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up.
0x4008D874 C   FIELD 12w02 CCACT_01_CC2DACT (rw): CCP Output Action on CC2D event.
0x4008D874 C   FIELD 15w02 CCACT_01_CC2UACT (rw): CCP Output Action on CC2U event.
0x4008D874 C   FIELD 28w02 CCACT_01_SWFRCACT (rw): CCP Output Action on Software Froce Output This field describes the resulting action of software force. This action has a shadow register, which will be updated under specific condition. So that this register cannot take into effect immediately.
0x4008D880 B  REGISTER IFCTL_01[0] (rw): Input Filter Control Register
0x4008D880 C   FIELD 00w04 IFCTL_01_ISEL (rw): Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved
0x4008D880 C   FIELD 07w01 IFCTL_01_INV (rw): Input Inversion This bit controls whether the selected input is inverted.
0x4008D880 C   FIELD 08w02 IFCTL_01_FP (rw): Filter Period. This field specifies the sample period for the input filter. I.e. The input is sampled for FP timer clocks during filtering.
0x4008D880 C   FIELD 11w01 IFCTL_01_CPV (rw): Consecutive Period/Voting Select This bit controls whether the input filter uses a stricter consecutive period count or majority voting.
0x4008D880 C   FIELD 12w01 IFCTL_01_FE (rw): Filter Enable This bit controls whether the input is filtered by the input filter or bypasses to the edge detect.
0x4008D884 B  REGISTER IFCTL_01[1] (rw): Input Filter Control Register
0x4008D884 C   FIELD 00w04 IFCTL_01_ISEL (rw): Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved
0x4008D884 C   FIELD 07w01 IFCTL_01_INV (rw): Input Inversion This bit controls whether the selected input is inverted.
0x4008D884 C   FIELD 08w02 IFCTL_01_FP (rw): Filter Period. This field specifies the sample period for the input filter. I.e. The input is sampled for FP timer clocks during filtering.
0x4008D884 C   FIELD 11w01 IFCTL_01_CPV (rw): Consecutive Period/Voting Select This bit controls whether the input filter uses a stricter consecutive period count or majority voting.
0x4008D884 C   FIELD 12w01 IFCTL_01_FE (rw): Filter Enable This bit controls whether the input is filtered by the input filter or bypasses to the edge detect.
0x4008D8B0 B  REGISTER TSEL (rw): Trigger Select
0x4008D8B0 C   FIELD 00w05 TSEL_ETSEL (rw): External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger. Triggers 0-15 are used to connect triggers generated by other timer modules in the same power domain. Refer to the SoC datasheet to get details. Triggers 16 and 17 are connected to event manager subscriber ports. Event lines 18-31 are reserved for future use.
0x4008D8B0 C   FIELD 09w01 TSEL_TE (rw): Trigger Enable. This selects whether a trigger is enabled or not for this counter 0x0 = Triggers are not used 0x1 = Triggers are used as selected by the ETSEL field
0x400A0000 A PERIPHERAL GPIOA
0x400A0400 B  REGISTER FSUB_0 (rw): Subsciber Port 0
0x400A0400 C   FIELD 00w02 FSUB_0_CHANID: 0 = disconnected. 1-15 = connected to channelID = CHANID.
0x400A0404 B  REGISTER FSUB_1 (rw): Subscriber Port 1
0x400A0404 C   FIELD 00w02 FSUB_1_CHANID: 0 = disconnected. 1-15 = connected to channelID = CHANID.
0x400A0444 B  REGISTER FPUB_0 (rw): Publisher Port 0
0x400A0444 C   FIELD 00w02 FPUB_0_CHANID: 0 = disconnected. 1-15 = connected to channelID = CHANID.
0x400A0448 B  REGISTER FPUB_1 (rw): Publisher Port 1
0x400A0448 C   FIELD 00w02 FPUB_1_CHANID: 0 = disconnected. 1-15 = connected to channelID = CHANID.
0x400A0800 B  REGISTER PWREN (rw): Power enable
0x400A0800 C   FIELD 00w01 PWREN_ENABLE: Enable the power
0x400A0800 C   FIELD 24w08 PWREN_KEY (wo): KEY to allow Power State Change
0x400A0804 B  REGISTER RSTCTL (wo): Reset Control
0x400A0804 C   FIELD 00w01 RSTCTL_RESETASSERT (wo): Assert reset to the peripheral
0x400A0804 C   FIELD 01w01 RSTCTL_RESETSTKYCLR (wo): Clear the RESETSTKY bit in the STAT register
0x400A0804 C   FIELD 24w08 RSTCTL_KEY (wo): Unlock key
0x400A0814 B  REGISTER STAT (ro): Status Register
0x400A0814 C   FIELD 16w01 STAT_RESETSTKY (ro): This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register
0x400A1010 B  REGISTER CLKOVR (rw): Clock Override
0x400A1010 C   FIELD 00w01 CLKOVR_OVERRIDE (rw): Unlocks the functionality of [RUN_STOP] to override the automatic peripheral clock request
0x400A1010 C   FIELD 01w01 CLKOVR_RUN_STOP (rw): If [OVERRIDE] is enabled, this register is used to manually control the peripheral's clock request to the system
0x400A1018 B  REGISTER PDBGCTL (rw): Peripheral Debug Control
0x400A1018 C   FIELD 00w01 PDBGCTL_FREE (rw): Free run control
0x400A1020 B  REGISTER INT_EVENT0_IIDX (ro): Interrupt index
0x400A1020 C   FIELD 00w08 INT_EVENT0_IIDX_STAT (ro): Interrupt index status
0x400A1028 B  REGISTER INT_EVENT0_IMASK (rw): Interrupt mask
0x400A1028 C   FIELD 00w01 INT_EVENT0_IMASK_DIO0: DIO0 event mask
0x400A1028 C   FIELD 01w01 INT_EVENT0_IMASK_DIO1: DIO1 event mask
0x400A1028 C   FIELD 02w01 INT_EVENT0_IMASK_DIO2: DIO2 event mask
0x400A1028 C   FIELD 03w01 INT_EVENT0_IMASK_DIO3: DIO3 event mask
0x400A1028 C   FIELD 04w01 INT_EVENT0_IMASK_DIO4: DIO4 event mask
0x400A1028 C   FIELD 05w01 INT_EVENT0_IMASK_DIO5: DIO5 event mask
0x400A1028 C   FIELD 06w01 INT_EVENT0_IMASK_DIO6: DIO6 event mask
0x400A1028 C   FIELD 07w01 INT_EVENT0_IMASK_DIO7: DIO7 event mask
0x400A1028 C   FIELD 08w01 INT_EVENT0_IMASK_DIO8: DIO8 event mask
0x400A1028 C   FIELD 09w01 INT_EVENT0_IMASK_DIO9: DIO9 event mask
0x400A1028 C   FIELD 10w01 INT_EVENT0_IMASK_DIO10: DIO10 event mask
0x400A1028 C   FIELD 11w01 INT_EVENT0_IMASK_DIO11: DIO11 event mask
0x400A1028 C   FIELD 12w01 INT_EVENT0_IMASK_DIO12: DIO12 event mask
0x400A1028 C   FIELD 13w01 INT_EVENT0_IMASK_DIO13: DIO13 event mask
0x400A1028 C   FIELD 14w01 INT_EVENT0_IMASK_DIO14: DIO14 event mask
0x400A1028 C   FIELD 15w01 INT_EVENT0_IMASK_DIO15: DIO15 event mask
0x400A1028 C   FIELD 16w01 INT_EVENT0_IMASK_DIO16: DIO16 event mask
0x400A1028 C   FIELD 17w01 INT_EVENT0_IMASK_DIO17: DIO17 event mask
0x400A1028 C   FIELD 18w01 INT_EVENT0_IMASK_DIO18: DIO18 event mask
0x400A1028 C   FIELD 19w01 INT_EVENT0_IMASK_DIO19: DIO19 event mask
0x400A1028 C   FIELD 20w01 INT_EVENT0_IMASK_DIO20: DIO20 event mask
0x400A1028 C   FIELD 21w01 INT_EVENT0_IMASK_DIO21: DIO21 event mask
0x400A1028 C   FIELD 22w01 INT_EVENT0_IMASK_DIO22: DIO22 event mask
0x400A1028 C   FIELD 23w01 INT_EVENT0_IMASK_DIO23: DIO23 event mask
0x400A1028 C   FIELD 24w01 INT_EVENT0_IMASK_DIO24: DIO24 event mask
0x400A1028 C   FIELD 25w01 INT_EVENT0_IMASK_DIO25: DIO25 event mask
0x400A1028 C   FIELD 26w01 INT_EVENT0_IMASK_DIO26: DIO26 event mask
0x400A1028 C   FIELD 27w01 INT_EVENT0_IMASK_DIO27: DIO27 event mask
0x400A1028 C   FIELD 28w01 INT_EVENT0_IMASK_DIO28: DIO28 event mask
0x400A1028 C   FIELD 29w01 INT_EVENT0_IMASK_DIO29: DIO29 event mask
0x400A1028 C   FIELD 30w01 INT_EVENT0_IMASK_DIO30: DIO30 event mask
0x400A1028 C   FIELD 31w01 INT_EVENT0_IMASK_DIO31: DIO31 event mask
0x400A1030 B  REGISTER INT_EVENT0_RIS (ro): Raw interrupt status
0x400A1030 C   FIELD 00w01 INT_EVENT0_RIS_DIO0: DIO0 event
0x400A1030 C   FIELD 01w01 INT_EVENT0_RIS_DIO1: DIO1 event
0x400A1030 C   FIELD 02w01 INT_EVENT0_RIS_DIO2: DIO2 event
0x400A1030 C   FIELD 03w01 INT_EVENT0_RIS_DIO3: DIO3 event
0x400A1030 C   FIELD 04w01 INT_EVENT0_RIS_DIO4: DIO4 event
0x400A1030 C   FIELD 05w01 INT_EVENT0_RIS_DIO5: DIO5 event
0x400A1030 C   FIELD 06w01 INT_EVENT0_RIS_DIO6: DIO6 event
0x400A1030 C   FIELD 07w01 INT_EVENT0_RIS_DIO7: DIO7 event
0x400A1030 C   FIELD 08w01 INT_EVENT0_RIS_DIO8: DIO8 event
0x400A1030 C   FIELD 09w01 INT_EVENT0_RIS_DIO9: DIO9 event
0x400A1030 C   FIELD 10w01 INT_EVENT0_RIS_DIO10: DIO10 event
0x400A1030 C   FIELD 11w01 INT_EVENT0_RIS_DIO11: DIO11 event
0x400A1030 C   FIELD 12w01 INT_EVENT0_RIS_DIO12: DIO12 event
0x400A1030 C   FIELD 13w01 INT_EVENT0_RIS_DIO13: DIO13 event
0x400A1030 C   FIELD 14w01 INT_EVENT0_RIS_DIO14: DIO14 event
0x400A1030 C   FIELD 15w01 INT_EVENT0_RIS_DIO15: DIO15 event
0x400A1030 C   FIELD 16w01 INT_EVENT0_RIS_DIO16: DIO16 event
0x400A1030 C   FIELD 17w01 INT_EVENT0_RIS_DIO17: DIO17 event
0x400A1030 C   FIELD 18w01 INT_EVENT0_RIS_DIO18: DIO18 event
0x400A1030 C   FIELD 19w01 INT_EVENT0_RIS_DIO19: DIO19 event
0x400A1030 C   FIELD 20w01 INT_EVENT0_RIS_DIO20: DIO20 event
0x400A1030 C   FIELD 21w01 INT_EVENT0_RIS_DIO21: DIO21 event
0x400A1030 C   FIELD 22w01 INT_EVENT0_RIS_DIO22: DIO22 event
0x400A1030 C   FIELD 23w01 INT_EVENT0_RIS_DIO23: DIO23 event
0x400A1030 C   FIELD 24w01 INT_EVENT0_RIS_DIO24: DIO24 event
0x400A1030 C   FIELD 25w01 INT_EVENT0_RIS_DIO25: DIO25 event
0x400A1030 C   FIELD 26w01 INT_EVENT0_RIS_DIO26: DIO26 event
0x400A1030 C   FIELD 27w01 INT_EVENT0_RIS_DIO27: DIO27 event
0x400A1030 C   FIELD 28w01 INT_EVENT0_RIS_DIO28: DIO28 event
0x400A1030 C   FIELD 29w01 INT_EVENT0_RIS_DIO29: DIO29 event
0x400A1030 C   FIELD 30w01 INT_EVENT0_RIS_DIO30: DIO30 event
0x400A1030 C   FIELD 31w01 INT_EVENT0_RIS_DIO31: DIO31 event
0x400A1038 B  REGISTER INT_EVENT0_MIS (ro): Masked interrupt status
0x400A1038 C   FIELD 00w01 INT_EVENT0_MIS_DIO0: DIO0 event
0x400A1038 C   FIELD 01w01 INT_EVENT0_MIS_DIO1: DIO1 event
0x400A1038 C   FIELD 02w01 INT_EVENT0_MIS_DIO2: DIO2 event
0x400A1038 C   FIELD 03w01 INT_EVENT0_MIS_DIO3: DIO3 event
0x400A1038 C   FIELD 04w01 INT_EVENT0_MIS_DIO4: DIO4 event
0x400A1038 C   FIELD 05w01 INT_EVENT0_MIS_DIO5: DIO5 event
0x400A1038 C   FIELD 06w01 INT_EVENT0_MIS_DIO6: DIO6 event
0x400A1038 C   FIELD 07w01 INT_EVENT0_MIS_DIO7: DIO7 event
0x400A1038 C   FIELD 08w01 INT_EVENT0_MIS_DIO8: DIO8 event
0x400A1038 C   FIELD 09w01 INT_EVENT0_MIS_DIO9: DIO9 event
0x400A1038 C   FIELD 10w01 INT_EVENT0_MIS_DIO10: DIO10 event
0x400A1038 C   FIELD 11w01 INT_EVENT0_MIS_DIO11: DIO11 event
0x400A1038 C   FIELD 12w01 INT_EVENT0_MIS_DIO12: DIO12 event
0x400A1038 C   FIELD 13w01 INT_EVENT0_MIS_DIO13: DIO13 event
0x400A1038 C   FIELD 14w01 INT_EVENT0_MIS_DIO14: DIO14 event
0x400A1038 C   FIELD 15w01 INT_EVENT0_MIS_DIO15: DIO15 event
0x400A1038 C   FIELD 16w01 INT_EVENT0_MIS_DIO16: DIO16 event
0x400A1038 C   FIELD 17w01 INT_EVENT0_MIS_DIO17: DIO17 event
0x400A1038 C   FIELD 18w01 INT_EVENT0_MIS_DIO18: DIO18 event
0x400A1038 C   FIELD 19w01 INT_EVENT0_MIS_DIO19: DIO19 event
0x400A1038 C   FIELD 20w01 INT_EVENT0_MIS_DIO20: DIO20 event
0x400A1038 C   FIELD 21w01 INT_EVENT0_MIS_DIO21: DIO21 event
0x400A1038 C   FIELD 22w01 INT_EVENT0_MIS_DIO22: DIO22 event
0x400A1038 C   FIELD 23w01 INT_EVENT0_MIS_DIO23: DIO23 event
0x400A1038 C   FIELD 24w01 INT_EVENT0_MIS_DIO24: DIO24 event
0x400A1038 C   FIELD 25w01 INT_EVENT0_MIS_DIO25: DIO25 event
0x400A1038 C   FIELD 26w01 INT_EVENT0_MIS_DIO26: DIO26 event
0x400A1038 C   FIELD 27w01 INT_EVENT0_MIS_DIO27: DIO27 event
0x400A1038 C   FIELD 28w01 INT_EVENT0_MIS_DIO28: DIO28 event
0x400A1038 C   FIELD 29w01 INT_EVENT0_MIS_DIO29: DIO29 event
0x400A1038 C   FIELD 30w01 INT_EVENT0_MIS_DIO30: DIO30 event
0x400A1038 C   FIELD 31w01 INT_EVENT0_MIS_DIO31: DIO31 event
0x400A1040 B  REGISTER INT_EVENT0_ISET (wo): Interrupt set
0x400A1040 C   FIELD 00w01 INT_EVENT0_ISET_DIO0: DIO0 event
0x400A1040 C   FIELD 01w01 INT_EVENT0_ISET_DIO1: DIO1 event
0x400A1040 C   FIELD 02w01 INT_EVENT0_ISET_DIO2: DIO2 event
0x400A1040 C   FIELD 03w01 INT_EVENT0_ISET_DIO3: DIO3 event
0x400A1040 C   FIELD 04w01 INT_EVENT0_ISET_DIO4: DIO4 event
0x400A1040 C   FIELD 05w01 INT_EVENT0_ISET_DIO5: DIO5 event
0x400A1040 C   FIELD 06w01 INT_EVENT0_ISET_DIO6: DIO6 event
0x400A1040 C   FIELD 07w01 INT_EVENT0_ISET_DIO7: DIO7 event
0x400A1040 C   FIELD 08w01 INT_EVENT0_ISET_DIO8: DIO8 event
0x400A1040 C   FIELD 09w01 INT_EVENT0_ISET_DIO9: DIO9 event
0x400A1040 C   FIELD 10w01 INT_EVENT0_ISET_DIO10: DIO10 event
0x400A1040 C   FIELD 11w01 INT_EVENT0_ISET_DIO11: DIO11 event
0x400A1040 C   FIELD 12w01 INT_EVENT0_ISET_DIO12: DIO12 event
0x400A1040 C   FIELD 13w01 INT_EVENT0_ISET_DIO13: DIO13 event
0x400A1040 C   FIELD 14w01 INT_EVENT0_ISET_DIO14: DIO14 event
0x400A1040 C   FIELD 15w01 INT_EVENT0_ISET_DIO15: DIO15 event
0x400A1040 C   FIELD 16w01 INT_EVENT0_ISET_DIO16: DIO16 event
0x400A1040 C   FIELD 17w01 INT_EVENT0_ISET_DIO17: DIO17 event
0x400A1040 C   FIELD 18w01 INT_EVENT0_ISET_DIO18: DIO18 event
0x400A1040 C   FIELD 19w01 INT_EVENT0_ISET_DIO19: DIO19 event
0x400A1040 C   FIELD 20w01 INT_EVENT0_ISET_DIO20: DIO20 event
0x400A1040 C   FIELD 21w01 INT_EVENT0_ISET_DIO21: DIO21 event
0x400A1040 C   FIELD 22w01 INT_EVENT0_ISET_DIO22: DIO22 event
0x400A1040 C   FIELD 23w01 INT_EVENT0_ISET_DIO23: DIO23 event
0x400A1040 C   FIELD 24w01 INT_EVENT0_ISET_DIO24: DIO24 event
0x400A1040 C   FIELD 25w01 INT_EVENT0_ISET_DIO25: DIO25 event
0x400A1040 C   FIELD 26w01 INT_EVENT0_ISET_DIO26: DIO26 event
0x400A1040 C   FIELD 27w01 INT_EVENT0_ISET_DIO27: DIO27 event
0x400A1040 C   FIELD 28w01 INT_EVENT0_ISET_DIO28: DIO28 event
0x400A1040 C   FIELD 29w01 INT_EVENT0_ISET_DIO29: DIO29 event
0x400A1040 C   FIELD 30w01 INT_EVENT0_ISET_DIO30: DIO30 event
0x400A1040 C   FIELD 31w01 INT_EVENT0_ISET_DIO31: DIO31 event
0x400A1048 B  REGISTER INT_EVENT0_ICLR (wo): Interrupt clear
0x400A1048 C   FIELD 00w01 INT_EVENT0_ICLR_DIO0: DIO0 event
0x400A1048 C   FIELD 01w01 INT_EVENT0_ICLR_DIO1: DIO1 event
0x400A1048 C   FIELD 02w01 INT_EVENT0_ICLR_DIO2: DIO2 event
0x400A1048 C   FIELD 03w01 INT_EVENT0_ICLR_DIO3: DIO3 event
0x400A1048 C   FIELD 04w01 INT_EVENT0_ICLR_DIO4: DIO4 event
0x400A1048 C   FIELD 05w01 INT_EVENT0_ICLR_DIO5: DIO5 event
0x400A1048 C   FIELD 06w01 INT_EVENT0_ICLR_DIO6: DIO6 event
0x400A1048 C   FIELD 07w01 INT_EVENT0_ICLR_DIO7: DIO7 event
0x400A1048 C   FIELD 08w01 INT_EVENT0_ICLR_DIO8: DIO8 event
0x400A1048 C   FIELD 09w01 INT_EVENT0_ICLR_DIO9: DIO9 event
0x400A1048 C   FIELD 10w01 INT_EVENT0_ICLR_DIO10: DIO10 event
0x400A1048 C   FIELD 11w01 INT_EVENT0_ICLR_DIO11: DIO11 event
0x400A1048 C   FIELD 12w01 INT_EVENT0_ICLR_DIO12: DIO12 event
0x400A1048 C   FIELD 13w01 INT_EVENT0_ICLR_DIO13: DIO13 event
0x400A1048 C   FIELD 14w01 INT_EVENT0_ICLR_DIO14: DIO14 event
0x400A1048 C   FIELD 15w01 INT_EVENT0_ICLR_DIO15: DIO15 event
0x400A1048 C   FIELD 16w01 INT_EVENT0_ICLR_DIO16: DIO16 event
0x400A1048 C   FIELD 17w01 INT_EVENT0_ICLR_DIO17: DIO17 event
0x400A1048 C   FIELD 18w01 INT_EVENT0_ICLR_DIO18: DIO18 event
0x400A1048 C   FIELD 19w01 INT_EVENT0_ICLR_DIO19: DIO19 event
0x400A1048 C   FIELD 20w01 INT_EVENT0_ICLR_DIO20: DIO20 event
0x400A1048 C   FIELD 21w01 INT_EVENT0_ICLR_DIO21: DIO21 event
0x400A1048 C   FIELD 22w01 INT_EVENT0_ICLR_DIO22: DIO22 event
0x400A1048 C   FIELD 23w01 INT_EVENT0_ICLR_DIO23: DIO23 event
0x400A1048 C   FIELD 24w01 INT_EVENT0_ICLR_DIO24: DIO24 event
0x400A1048 C   FIELD 25w01 INT_EVENT0_ICLR_DIO25: DIO25 event
0x400A1048 C   FIELD 26w01 INT_EVENT0_ICLR_DIO26: DIO26 event
0x400A1048 C   FIELD 27w01 INT_EVENT0_ICLR_DIO27: DIO27 event
0x400A1048 C   FIELD 28w01 INT_EVENT0_ICLR_DIO28: DIO28 event
0x400A1048 C   FIELD 29w01 INT_EVENT0_ICLR_DIO29: DIO29 event
0x400A1048 C   FIELD 30w01 INT_EVENT0_ICLR_DIO30: DIO30 event
0x400A1048 C   FIELD 31w01 INT_EVENT0_ICLR_DIO31: DIO31 event
0x400A1050 B  REGISTER INT_EVENT1_IIDX (ro): Interrupt index
0x400A1050 C   FIELD 00w08 INT_EVENT1_IIDX_STAT (ro): Interrupt index status
0x400A1058 B  REGISTER INT_EVENT1_IMASK (rw): Interrupt mask
0x400A1058 C   FIELD 00w01 INT_EVENT1_IMASK_DIO0: DIO0 event mask
0x400A1058 C   FIELD 01w01 INT_EVENT1_IMASK_DIO1: DIO1 event mask
0x400A1058 C   FIELD 02w01 INT_EVENT1_IMASK_DIO2: DIO2 event mask
0x400A1058 C   FIELD 03w01 INT_EVENT1_IMASK_DIO3: DIO3 event mask
0x400A1058 C   FIELD 04w01 INT_EVENT1_IMASK_DIO4: DIO4 event mask
0x400A1058 C   FIELD 05w01 INT_EVENT1_IMASK_DIO5: DIO5 event mask
0x400A1058 C   FIELD 06w01 INT_EVENT1_IMASK_DIO6: DIO6 event mask
0x400A1058 C   FIELD 07w01 INT_EVENT1_IMASK_DIO7: DIO7 event mask
0x400A1058 C   FIELD 08w01 INT_EVENT1_IMASK_DIO8: DIO8 event mask
0x400A1058 C   FIELD 09w01 INT_EVENT1_IMASK_DIO9: DIO9 event mask
0x400A1058 C   FIELD 10w01 INT_EVENT1_IMASK_DIO10: DIO10 event mask
0x400A1058 C   FIELD 11w01 INT_EVENT1_IMASK_DIO11: DIO11 event mask
0x400A1058 C   FIELD 12w01 INT_EVENT1_IMASK_DIO12: DIO12 event mask
0x400A1058 C   FIELD 13w01 INT_EVENT1_IMASK_DIO13: DIO13 event mask
0x400A1058 C   FIELD 14w01 INT_EVENT1_IMASK_DIO14: DIO14 event mask
0x400A1058 C   FIELD 15w01 INT_EVENT1_IMASK_DIO15: DIO15 event mask
0x400A1060 B  REGISTER INT_EVENT1_RIS (ro): Raw interrupt status
0x400A1060 C   FIELD 00w01 INT_EVENT1_RIS_DIO0: DIO0 event
0x400A1060 C   FIELD 01w01 INT_EVENT1_RIS_DIO1: DIO1 event
0x400A1060 C   FIELD 02w01 INT_EVENT1_RIS_DIO2: DIO2 event
0x400A1060 C   FIELD 03w01 INT_EVENT1_RIS_DIO3: DIO3 event
0x400A1060 C   FIELD 04w01 INT_EVENT1_RIS_DIO4: DIO4 event
0x400A1060 C   FIELD 05w01 INT_EVENT1_RIS_DIO5: DIO5 event
0x400A1060 C   FIELD 06w01 INT_EVENT1_RIS_DIO6: DIO6 event
0x400A1060 C   FIELD 07w01 INT_EVENT1_RIS_DIO7: DIO7 event
0x400A1060 C   FIELD 08w01 INT_EVENT1_RIS_DIO8: DIO8 event
0x400A1060 C   FIELD 09w01 INT_EVENT1_RIS_DIO9: DIO9 event
0x400A1060 C   FIELD 10w01 INT_EVENT1_RIS_DIO10: DIO10 event
0x400A1060 C   FIELD 11w01 INT_EVENT1_RIS_DIO11: DIO11 event
0x400A1060 C   FIELD 12w01 INT_EVENT1_RIS_DIO12: DIO12 event
0x400A1060 C   FIELD 13w01 INT_EVENT1_RIS_DIO13: DIO13 event
0x400A1060 C   FIELD 14w01 INT_EVENT1_RIS_DIO14: DIO14 event
0x400A1060 C   FIELD 15w01 INT_EVENT1_RIS_DIO15: DIO15 event
0x400A1068 B  REGISTER INT_EVENT1_MIS (ro): Masked interrupt status
0x400A1068 C   FIELD 00w01 INT_EVENT1_MIS_DIO0: DIO0 event
0x400A1068 C   FIELD 01w01 INT_EVENT1_MIS_DIO1: DIO1 event
0x400A1068 C   FIELD 02w01 INT_EVENT1_MIS_DIO2: DIO2 event
0x400A1068 C   FIELD 03w01 INT_EVENT1_MIS_DIO3: DIO3 event
0x400A1068 C   FIELD 04w01 INT_EVENT1_MIS_DIO4: DIO4 event
0x400A1068 C   FIELD 05w01 INT_EVENT1_MIS_DIO5: DIO5 event
0x400A1068 C   FIELD 06w01 INT_EVENT1_MIS_DIO6: DIO6 event
0x400A1068 C   FIELD 07w01 INT_EVENT1_MIS_DIO7: DIO7 event
0x400A1068 C   FIELD 08w01 INT_EVENT1_MIS_DIO8: DIO8 event
0x400A1068 C   FIELD 09w01 INT_EVENT1_MIS_DIO9: DIO9 event
0x400A1068 C   FIELD 10w01 INT_EVENT1_MIS_DIO10: DIO10 event
0x400A1068 C   FIELD 11w01 INT_EVENT1_MIS_DIO11: DIO11 event
0x400A1068 C   FIELD 12w01 INT_EVENT1_MIS_DIO12: DIO12 event
0x400A1068 C   FIELD 13w01 INT_EVENT1_MIS_DIO13: DIO13 event
0x400A1068 C   FIELD 14w01 INT_EVENT1_MIS_DIO14: DIO14 event
0x400A1068 C   FIELD 15w01 INT_EVENT1_MIS_DIO15: DIO15 event
0x400A1070 B  REGISTER INT_EVENT1_ISET (wo): Interrupt set
0x400A1070 C   FIELD 00w01 INT_EVENT1_ISET_DIO0: DIO0 event
0x400A1070 C   FIELD 01w01 INT_EVENT1_ISET_DIO1: DIO1 event
0x400A1070 C   FIELD 02w01 INT_EVENT1_ISET_DIO2: DIO2 event
0x400A1070 C   FIELD 03w01 INT_EVENT1_ISET_DIO3: DIO3 event
0x400A1070 C   FIELD 04w01 INT_EVENT1_ISET_DIO4: DIO4 event
0x400A1070 C   FIELD 05w01 INT_EVENT1_ISET_DIO5: DIO5 event
0x400A1070 C   FIELD 06w01 INT_EVENT1_ISET_DIO6: DIO6 event
0x400A1070 C   FIELD 07w01 INT_EVENT1_ISET_DIO7: DIO7 event
0x400A1070 C   FIELD 08w01 INT_EVENT1_ISET_DIO8: DIO8 event
0x400A1070 C   FIELD 09w01 INT_EVENT1_ISET_DIO9: DIO9 event
0x400A1070 C   FIELD 10w01 INT_EVENT1_ISET_DIO10: DIO10 event
0x400A1070 C   FIELD 11w01 INT_EVENT1_ISET_DIO11: DIO11 event
0x400A1070 C   FIELD 12w01 INT_EVENT1_ISET_DIO12: DIO12 event
0x400A1070 C   FIELD 13w01 INT_EVENT1_ISET_DIO13: DIO13 event
0x400A1070 C   FIELD 14w01 INT_EVENT1_ISET_DIO14: DIO14 event
0x400A1070 C   FIELD 15w01 INT_EVENT1_ISET_DIO15: DIO15 event
0x400A1078 B  REGISTER INT_EVENT1_ICLR (wo): Interrupt clear
0x400A1078 C   FIELD 00w01 INT_EVENT1_ICLR_DIO0: DIO0 event
0x400A1078 C   FIELD 01w01 INT_EVENT1_ICLR_DIO1: DIO1 event
0x400A1078 C   FIELD 02w01 INT_EVENT1_ICLR_DIO2: DIO2 event
0x400A1078 C   FIELD 03w01 INT_EVENT1_ICLR_DIO3: DIO3 event
0x400A1078 C   FIELD 04w01 INT_EVENT1_ICLR_DIO4: DIO4 event
0x400A1078 C   FIELD 05w01 INT_EVENT1_ICLR_DIO5: DIO5 event
0x400A1078 C   FIELD 06w01 INT_EVENT1_ICLR_DIO6: DIO6 event
0x400A1078 C   FIELD 07w01 INT_EVENT1_ICLR_DIO7: DIO7 event
0x400A1078 C   FIELD 08w01 INT_EVENT1_ICLR_DIO8: DIO8 event
0x400A1078 C   FIELD 09w01 INT_EVENT1_ICLR_DIO9: DIO9 event
0x400A1078 C   FIELD 10w01 INT_EVENT1_ICLR_DIO10: DIO10 event
0x400A1078 C   FIELD 11w01 INT_EVENT1_ICLR_DIO11: DIO11 event
0x400A1078 C   FIELD 12w01 INT_EVENT1_ICLR_DIO12: DIO12 event
0x400A1078 C   FIELD 13w01 INT_EVENT1_ICLR_DIO13: DIO13 event
0x400A1078 C   FIELD 14w01 INT_EVENT1_ICLR_DIO14: DIO14 event
0x400A1078 C   FIELD 15w01 INT_EVENT1_ICLR_DIO15: DIO15 event
0x400A1080 B  REGISTER INT_EVENT2_IIDX (ro): Interrupt index
0x400A1080 C   FIELD 00w08 INT_EVENT2_IIDX_STAT (ro): Interrupt index status
0x400A1088 B  REGISTER INT_EVENT2_IMASK (rw): Interrupt mask
0x400A1088 C   FIELD 16w01 INT_EVENT2_IMASK_DIO16: DIO16 event mask
0x400A1088 C   FIELD 17w01 INT_EVENT2_IMASK_DIO17: DIO17 event mask
0x400A1088 C   FIELD 18w01 INT_EVENT2_IMASK_DIO18: DIO18 event mask
0x400A1088 C   FIELD 19w01 INT_EVENT2_IMASK_DIO19: DIO19 event mask
0x400A1088 C   FIELD 20w01 INT_EVENT2_IMASK_DIO20: DIO20 event mask
0x400A1088 C   FIELD 21w01 INT_EVENT2_IMASK_DIO21: DIO21 event mask
0x400A1088 C   FIELD 22w01 INT_EVENT2_IMASK_DIO22: DIO22 event mask
0x400A1088 C   FIELD 23w01 INT_EVENT2_IMASK_DIO23: DIO23 event mask
0x400A1088 C   FIELD 24w01 INT_EVENT2_IMASK_DIO24: DIO24 event mask
0x400A1088 C   FIELD 25w01 INT_EVENT2_IMASK_DIO25: DIO25 event mask
0x400A1088 C   FIELD 26w01 INT_EVENT2_IMASK_DIO26: DIO26 event mask
0x400A1088 C   FIELD 27w01 INT_EVENT2_IMASK_DIO27: DIO27 event mask
0x400A1088 C   FIELD 28w01 INT_EVENT2_IMASK_DIO28: DIO28 event mask
0x400A1088 C   FIELD 29w01 INT_EVENT2_IMASK_DIO29: DIO29 event mask
0x400A1088 C   FIELD 30w01 INT_EVENT2_IMASK_DIO30: DIO30 event mask
0x400A1088 C   FIELD 31w01 INT_EVENT2_IMASK_DIO31: DIO31 event mask
0x400A1090 B  REGISTER INT_EVENT2_RIS (ro): Raw interrupt status
0x400A1090 C   FIELD 16w01 INT_EVENT2_RIS_DIO16: DIO16 event
0x400A1090 C   FIELD 17w01 INT_EVENT2_RIS_DIO17: DIO17 event
0x400A1090 C   FIELD 18w01 INT_EVENT2_RIS_DIO18: DIO18 event
0x400A1090 C   FIELD 19w01 INT_EVENT2_RIS_DIO19: DIO19 event
0x400A1090 C   FIELD 20w01 INT_EVENT2_RIS_DIO20: DIO20 event
0x400A1090 C   FIELD 21w01 INT_EVENT2_RIS_DIO21: DIO21 event
0x400A1090 C   FIELD 22w01 INT_EVENT2_RIS_DIO22: DIO22 event
0x400A1090 C   FIELD 23w01 INT_EVENT2_RIS_DIO23: DIO23 event
0x400A1090 C   FIELD 24w01 INT_EVENT2_RIS_DIO24: DIO24 event
0x400A1090 C   FIELD 25w01 INT_EVENT2_RIS_DIO25: DIO25 event
0x400A1090 C   FIELD 26w01 INT_EVENT2_RIS_DIO26: DIO26 event
0x400A1090 C   FIELD 27w01 INT_EVENT2_RIS_DIO27: DIO27 event
0x400A1090 C   FIELD 28w01 INT_EVENT2_RIS_DIO28: DIO28 event
0x400A1090 C   FIELD 29w01 INT_EVENT2_RIS_DIO29: DIO29 event
0x400A1090 C   FIELD 30w01 INT_EVENT2_RIS_DIO30: DIO30 event
0x400A1090 C   FIELD 31w01 INT_EVENT2_RIS_DIO31: DIO31 event
0x400A1098 B  REGISTER INT_EVENT2_MIS (ro): Masked interrupt status
0x400A1098 C   FIELD 16w01 INT_EVENT2_MIS_DIO16: DIO16 event
0x400A1098 C   FIELD 17w01 INT_EVENT2_MIS_DIO17: DIO17 event
0x400A1098 C   FIELD 18w01 INT_EVENT2_MIS_DIO18: DIO18 event
0x400A1098 C   FIELD 19w01 INT_EVENT2_MIS_DIO19: DIO19 event
0x400A1098 C   FIELD 20w01 INT_EVENT2_MIS_DIO20: DIO20 event
0x400A1098 C   FIELD 21w01 INT_EVENT2_MIS_DIO21: DIO21 event
0x400A1098 C   FIELD 22w01 INT_EVENT2_MIS_DIO22: DIO22 event
0x400A1098 C   FIELD 23w01 INT_EVENT2_MIS_DIO23: DIO23 event
0x400A1098 C   FIELD 24w01 INT_EVENT2_MIS_DIO24: DIO24 event
0x400A1098 C   FIELD 25w01 INT_EVENT2_MIS_DIO25: DIO25 event
0x400A1098 C   FIELD 26w01 INT_EVENT2_MIS_DIO26: DIO26 event
0x400A1098 C   FIELD 27w01 INT_EVENT2_MIS_DIO27: DIO27 event
0x400A1098 C   FIELD 28w01 INT_EVENT2_MIS_DIO28: DIO28 event
0x400A1098 C   FIELD 29w01 INT_EVENT2_MIS_DIO29: DIO29 event
0x400A1098 C   FIELD 30w01 INT_EVENT2_MIS_DIO30: DIO30 event
0x400A1098 C   FIELD 31w01 INT_EVENT2_MIS_DIO31: DIO31 event
0x400A10A0 B  REGISTER INT_EVENT2_ISET (wo): Interrupt set
0x400A10A0 C   FIELD 16w01 INT_EVENT2_ISET_DIO16: DIO16 event
0x400A10A0 C   FIELD 17w01 INT_EVENT2_ISET_DIO17: DIO17 event
0x400A10A0 C   FIELD 18w01 INT_EVENT2_ISET_DIO18: DIO18 event
0x400A10A0 C   FIELD 19w01 INT_EVENT2_ISET_DIO19: DIO19 event
0x400A10A0 C   FIELD 20w01 INT_EVENT2_ISET_DIO20: DIO20 event
0x400A10A0 C   FIELD 21w01 INT_EVENT2_ISET_DIO21: DIO21 event
0x400A10A0 C   FIELD 22w01 INT_EVENT2_ISET_DIO22: DIO22 event
0x400A10A0 C   FIELD 23w01 INT_EVENT2_ISET_DIO23: DIO23 event
0x400A10A0 C   FIELD 24w01 INT_EVENT2_ISET_DIO24: DIO24 event
0x400A10A0 C   FIELD 25w01 INT_EVENT2_ISET_DIO25: DIO25 event
0x400A10A0 C   FIELD 26w01 INT_EVENT2_ISET_DIO26: DIO26 event
0x400A10A0 C   FIELD 27w01 INT_EVENT2_ISET_DIO27: DIO27 event
0x400A10A0 C   FIELD 28w01 INT_EVENT2_ISET_DIO28: DIO28 event
0x400A10A0 C   FIELD 29w01 INT_EVENT2_ISET_DIO29: DIO29 event
0x400A10A0 C   FIELD 30w01 INT_EVENT2_ISET_DIO30: DIO30 event
0x400A10A0 C   FIELD 31w01 INT_EVENT2_ISET_DIO31: DIO31 event
0x400A10A8 B  REGISTER INT_EVENT2_ICLR (wo): Interrupt clear
0x400A10A8 C   FIELD 16w01 INT_EVENT2_ICLR_DIO16: DIO16 event
0x400A10A8 C   FIELD 17w01 INT_EVENT2_ICLR_DIO17: DIO17 event
0x400A10A8 C   FIELD 18w01 INT_EVENT2_ICLR_DIO18: DIO18 event
0x400A10A8 C   FIELD 19w01 INT_EVENT2_ICLR_DIO19: DIO19 event
0x400A10A8 C   FIELD 20w01 INT_EVENT2_ICLR_DIO20: DIO20 event
0x400A10A8 C   FIELD 21w01 INT_EVENT2_ICLR_DIO21: DIO21 event
0x400A10A8 C   FIELD 22w01 INT_EVENT2_ICLR_DIO22: DIO22 event
0x400A10A8 C   FIELD 23w01 INT_EVENT2_ICLR_DIO23: DIO23 event
0x400A10A8 C   FIELD 24w01 INT_EVENT2_ICLR_DIO24: DIO24 event
0x400A10A8 C   FIELD 25w01 INT_EVENT2_ICLR_DIO25: DIO25 event
0x400A10A8 C   FIELD 26w01 INT_EVENT2_ICLR_DIO26: DIO26 event
0x400A10A8 C   FIELD 27w01 INT_EVENT2_ICLR_DIO27: DIO27 event
0x400A10A8 C   FIELD 28w01 INT_EVENT2_ICLR_DIO28: DIO28 event
0x400A10A8 C   FIELD 29w01 INT_EVENT2_ICLR_DIO29: DIO29 event
0x400A10A8 C   FIELD 30w01 INT_EVENT2_ICLR_DIO30: DIO30 event
0x400A10A8 C   FIELD 31w01 INT_EVENT2_ICLR_DIO31: DIO31 event
0x400A10E0 B  REGISTER EVT_MODE (rw): Event Mode
0x400A10E0 C   FIELD 00w02 EVT_MODE_INT0_CFG (ro): Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT0]
0x400A10E0 C   FIELD 02w02 EVT_MODE_EVT1_CFG (ro): Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT1]
0x400A10E0 C   FIELD 04w02 EVT_MODE_EVT2_CFG (ro): Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT2]
0x400A10FC B  REGISTER DESC (ro): Module Description
0x400A10FC C   FIELD 00w04 DESC_MINREV: Minor rev of the IP
0x400A10FC C   FIELD 04w04 DESC_MAJREV: Major rev of the IP
0x400A10FC C   FIELD 12w04 DESC_FEATUREVER: Feature Set for the module *instance*
0x400A10FC C   FIELD 16w16 DESC_MODULEID: Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness.
0x400A1200 B  REGISTER DOUT3_0 (wo): Data output 3 to 0
0x400A1200 C   FIELD 00w01 DOUT3_0_DIO0 (wo): This bit sets the value of the pin configured as DIO0 when the output is enabled through DOE31_0 register.
0x400A1200 C   FIELD 08w01 DOUT3_0_DIO1 (wo): This bit sets the value of the pin configured as DIO1 when the output is enabled through DOE31_0 register.
0x400A1200 C   FIELD 16w01 DOUT3_0_DIO2 (wo): This bit sets the value of the pin configured as DIO2 when the output is enabled through DOE31_0 register.
0x400A1200 C   FIELD 24w01 DOUT3_0_DIO3 (wo): This bit sets the value of the pin configured as DIO3 when the output is enabled through DOE31_0 register.
0x400A1204 B  REGISTER DOUT7_4 (wo): Data output 7 to 4
0x400A1204 C   FIELD 00w01 DOUT7_4_DIO4 (wo): This bit sets the value of the pin configured as DIO4 when the output is enabled through DOE31_0 register.
0x400A1204 C   FIELD 08w01 DOUT7_4_DIO5 (wo): This bit sets the value of the pin configured as DIO5 when the output is enabled through DOE31_0 register.
0x400A1204 C   FIELD 16w01 DOUT7_4_DIO6 (wo): This bit sets the value of the pin configured as DIO6 when the output is enabled through DOE31_0 register.
0x400A1204 C   FIELD 24w01 DOUT7_4_DIO7 (wo): This bit sets the value of the pin configured as DIO7 when the output is enabled through DOE31_0 register.
0x400A1208 B  REGISTER DOUT11_8 (wo): Data output 11 to 8
0x400A1208 C   FIELD 00w01 DOUT11_8_DIO8 (wo): This bit sets the value of the pin configured as DIO8 when the output is enabled through DOE31_0 register.
0x400A1208 C   FIELD 08w01 DOUT11_8_DIO9 (wo): This bit sets the value of the pin configured as DIO9 when the output is enabled through DOE31_0 register.
0x400A1208 C   FIELD 16w01 DOUT11_8_DIO10 (wo): This bit sets the value of the pin configured as DIO10 when the output is enabled through DOE31_0 register.
0x400A1208 C   FIELD 24w01 DOUT11_8_DIO11 (wo): This bit sets the value of the pin configured as DIO11 when the output is enabled through DOE31_0 register.
0x400A120C B  REGISTER DOUT15_12 (wo): Data output 15 to 12
0x400A120C C   FIELD 00w01 DOUT15_12_DIO12 (wo): This bit sets the value of the pin configured as DIO12 when the output is enabled through DOE31_0 register.
0x400A120C C   FIELD 08w01 DOUT15_12_DIO13 (wo): This bit sets the value of the pin configured as DIO13 when the output is enabled through DOE31_0 register.
0x400A120C C   FIELD 16w01 DOUT15_12_DIO14 (wo): This bit sets the value of the pin configured as DIO14 when the output is enabled through DOE31_0 register.
0x400A120C C   FIELD 24w01 DOUT15_12_DIO15 (wo): This bit sets the value of the pin configured as DIO15 when the output is enabled through DOE31_0 register.
0x400A1210 B  REGISTER DOUT19_16 (wo): Data output 19 to 16
0x400A1210 C   FIELD 00w01 DOUT19_16_DIO16 (wo): This bit sets the value of the pin configured as DIO16 when the output is enabled through DOE31_0 register.
0x400A1210 C   FIELD 08w01 DOUT19_16_DIO17 (wo): This bit sets the value of the pin configured as DIO17 when the output is enabled through DOE31_0 register.
0x400A1210 C   FIELD 16w01 DOUT19_16_DIO18 (wo): This bit sets the value of the pin configured as DIO18 when the output is enabled through DOE31_0 register.
0x400A1210 C   FIELD 24w01 DOUT19_16_DIO19 (wo): This bit sets the value of the pin configured as DIO19 when the output is enabled through DOE31_0 register.
0x400A1214 B  REGISTER DOUT23_20 (wo): Data output 23 to 20
0x400A1214 C   FIELD 00w01 DOUT23_20_DIO20 (wo): This bit sets the value of the pin configured as DIO20 when the output is enabled through DOE31_0 register.
0x400A1214 C   FIELD 08w01 DOUT23_20_DIO21 (wo): This bit sets the value of the pin configured as DIO21 when the output is enabled through DOE31_0 register.
0x400A1214 C   FIELD 16w01 DOUT23_20_DIO22 (wo): This bit sets the value of the pin configured as DIO22 when the output is enabled through DOE31_0 register.
0x400A1214 C   FIELD 24w01 DOUT23_20_DIO23 (wo): This bit sets the value of the pin configured as DIO23 when the output is enabled through DOE31_0 register.
0x400A1218 B  REGISTER DOUT27_24 (wo): Data output 27 to 24
0x400A1218 C   FIELD 00w01 DOUT27_24_DIO24 (wo): This bit sets the value of the pin configured as DIO24 when the output is enabled through DOE31_0 register.
0x400A1218 C   FIELD 08w01 DOUT27_24_DIO25 (wo): This bit sets the value of the pin configured as DIO25 when the output is enabled through DOE31_0 register.
0x400A1218 C   FIELD 16w01 DOUT27_24_DIO26 (wo): This bit sets the value of the pin configured as DIO26 when the output is enabled through DOE31_0 register.
0x400A1218 C   FIELD 24w01 DOUT27_24_DIO27 (wo): This bit sets the value of the pin configured as DIO27 when the output is enabled through DOE31_0 register.
0x400A121C B  REGISTER DOUT31_28 (wo): Data output 31 to 28
0x400A121C C   FIELD 00w01 DOUT31_28_DIO28 (wo): This bit sets the value of the pin configured as DIO28 when the output is enabled through DOE31_0 register.
0x400A121C C   FIELD 08w01 DOUT31_28_DIO29 (wo): This bit sets the value of the pin configured as DIO29 when the output is enabled through DOE31_0 register.
0x400A121C C   FIELD 16w01 DOUT31_28_DIO30 (wo): This bit sets the value of the pin configured as DIO30 when the output is enabled through DOE31_0 register.
0x400A121C C   FIELD 24w01 DOUT31_28_DIO31 (wo): This bit sets the value of the pin configured as DIO31 when the output is enabled through DOE31_0 register.
0x400A1280 B  REGISTER DOUT31_0 (rw): Data output 31 to 0
0x400A1280 C   FIELD 00w01 DOUT31_0_DIO0 (rw): This bit sets the value of the pin configured as DIO0 when the output is enabled through DOE31_0 register.
0x400A1280 C   FIELD 01w01 DOUT31_0_DIO1 (rw): This bit sets the value of the pin configured as DIO1 when the output is enabled through DOE31_0 register.
0x400A1280 C   FIELD 02w01 DOUT31_0_DIO2 (rw): This bit sets the value of the pin configured as DIO2 when the output is enabled through DOE31_0 register.
0x400A1280 C   FIELD 03w01 DOUT31_0_DIO3 (rw): This bit sets the value of the pin configured as DIO3 when the output is enabled through DOE31_0 register.
0x400A1280 C   FIELD 04w01 DOUT31_0_DIO4 (rw): This bit sets the value of the pin configured as DIO4 when the output is enabled through DOE31_0 register.
0x400A1280 C   FIELD 05w01 DOUT31_0_DIO5 (rw): This bit sets the value of the pin configured as DIO5 when the output is enabled through DOE31_0 register.
0x400A1280 C   FIELD 06w01 DOUT31_0_DIO6 (rw): This bit sets the value of the pin configured as DIO6 when the output is enabled through DOE31_0 register.
0x400A1280 C   FIELD 07w01 DOUT31_0_DIO7 (rw): This bit sets the value of the pin configured as DIO7 when the output is enabled through DOE31_0 register.
0x400A1280 C   FIELD 08w01 DOUT31_0_DIO8 (rw): This bit sets the value of the pin configured as DIO8 when the output is enabled through DOE31_0 register.
0x400A1280 C   FIELD 09w01 DOUT31_0_DIO9 (rw): This bit sets the value of the pin configured as DIO9 when the output is enabled through DOE31_0 register.
0x400A1280 C   FIELD 10w01 DOUT31_0_DIO10 (rw): This bit sets the value of the pin configured as DIO10 when the output is enabled through DOE31_0 register.
0x400A1280 C   FIELD 11w01 DOUT31_0_DIO11 (rw): This bit sets the value of the pin configured as DIO11 when the output is enabled through DOE31_0 register.
0x400A1280 C   FIELD 12w01 DOUT31_0_DIO12 (rw): This bit sets the value of the pin configured as DIO12 when the output is enabled through DOE31_0 register.
0x400A1280 C   FIELD 13w01 DOUT31_0_DIO13 (rw): This bit sets the value of the pin configured as DIO13 when the output is enabled through DOE31_0 register.
0x400A1280 C   FIELD 14w01 DOUT31_0_DIO14 (rw): This bit sets the value of the pin configured as DIO14 when the output is enabled through DOE31_0 register.
0x400A1280 C   FIELD 15w01 DOUT31_0_DIO15 (rw): This bit sets the value of the pin configured as DIO15 when the output is enabled through DOE31_0 register.
0x400A1280 C   FIELD 16w01 DOUT31_0_DIO16 (rw): This bit sets the value of the pin configured as DIO16 when the output is enabled through DOE31_0 register.
0x400A1280 C   FIELD 17w01 DOUT31_0_DIO17 (rw): This bit sets the value of the pin configured as DIO17 when the output is enabled through DOE31_0 register.
0x400A1280 C   FIELD 18w01 DOUT31_0_DIO18 (rw): This bit sets the value of the pin configured as DIO18 when the output is enabled through DOE31_0 register.
0x400A1280 C   FIELD 19w01 DOUT31_0_DIO19 (rw): This bit sets the value of the pin configured as DIO19 when the output is enabled through DOE31_0 register.
0x400A1280 C   FIELD 20w01 DOUT31_0_DIO20 (rw): This bit sets the value of the pin configured as DIO20 when the output is enabled through DOE31_0 register.
0x400A1280 C   FIELD 21w01 DOUT31_0_DIO21 (rw): This bit sets the value of the pin configured as DIO21 when the output is enabled through DOE31_0 register.
0x400A1280 C   FIELD 22w01 DOUT31_0_DIO22 (rw): This bit sets the value of the pin configured as DIO22 when the output is enabled through DOE31_0 register.
0x400A1280 C   FIELD 23w01 DOUT31_0_DIO23 (rw): This bit sets the value of the pin configured as DIO23 when the output is enabled through DOE31_0 register.
0x400A1280 C   FIELD 24w01 DOUT31_0_DIO24 (rw): This bit sets the value of the pin configured as DIO24 when the output is enabled through DOE31_0 register.
0x400A1280 C   FIELD 25w01 DOUT31_0_DIO25 (rw): This bit sets the value of the pin configured as DIO25 when the output is enabled through DOE31_0 register.
0x400A1280 C   FIELD 26w01 DOUT31_0_DIO26 (rw): This bit sets the value of the pin configured as DIO26 when the output is enabled through DOE31_0 register.
0x400A1280 C   FIELD 27w01 DOUT31_0_DIO27 (rw): This bit sets the value of the pin configured as DIO27 when the output is enabled through DOE31_0 register.
0x400A1280 C   FIELD 28w01 DOUT31_0_DIO28 (rw): This bit sets the value of the pin configured as DIO28 when the output is enabled through DOE31_0 register.
0x400A1280 C   FIELD 29w01 DOUT31_0_DIO29 (rw): This bit sets the value of the pin configured as DIO29 when the output is enabled through DOE31_0 register.
0x400A1280 C   FIELD 30w01 DOUT31_0_DIO30 (rw): This bit sets the value of the pin configured as DIO30 when the output is enabled through DOE31_0 register.
0x400A1280 C   FIELD 31w01 DOUT31_0_DIO31 (rw): This bit sets the value of the pin configured as DIO31 when the output is enabled through DOE31_0 register.
0x400A1290 B  REGISTER DOUTSET31_0 (wo): Data output set 31 to 0
0x400A1290 C   FIELD 00w01 DOUTSET31_0_DIO0 (wo): Writing 1 to this bit sets the DIO0 bit in the DOUT31_0 register. Writing 0 has no effect.
0x400A1290 C   FIELD 01w01 DOUTSET31_0_DIO1 (wo): Writing 1 to this bit sets the DIO1 bit in the DOUT31_0 register. Writing 0 has no effect.
0x400A1290 C   FIELD 02w01 DOUTSET31_0_DIO2 (wo): Writing 1 to this bit sets the DIO2 bit in the DOUT31_0 register. Writing 0 has no effect.
0x400A1290 C   FIELD 03w01 DOUTSET31_0_DIO3 (wo): Writing 1 to this bit sets the DIO3 bit in the DOUT31_0 register. Writing 0 has no effect.
0x400A1290 C   FIELD 04w01 DOUTSET31_0_DIO4 (wo): Writing 1 to this bit sets the DIO4 bit in the DOUT31_0 register. Writing 0 has no effect.
0x400A1290 C   FIELD 05w01 DOUTSET31_0_DIO5 (wo): Writing 1 to this bit sets the DIO5 bit in the DOUT31_0 register. Writing 0 has no effect.
0x400A1290 C   FIELD 06w01 DOUTSET31_0_DIO6 (wo): Writing 1 to this bit sets the DIO6 bit in the DOUT31_0 register. Writing 0 has no effect.
0x400A1290 C   FIELD 07w01 DOUTSET31_0_DIO7 (wo): Writing 1 to this bit sets the DIO7 bit in the DOUT31_0 register. Writing 0 has no effect.
0x400A1290 C   FIELD 08w01 DOUTSET31_0_DIO8 (wo): Writing 1 to this bit sets the DIO8 bit in the DOUT31_0 register. Writing 0 has no effect.
0x400A1290 C   FIELD 09w01 DOUTSET31_0_DIO9 (wo): Writing 1 to this bit sets the DIO9 bit in the DOUT31_0 register. Writing 0 has no effect.
0x400A1290 C   FIELD 10w01 DOUTSET31_0_DIO10 (wo): Writing 1 to this bit sets the DIO10 bit in the DOUT31_0 register. Writing 0 has no effect.
0x400A1290 C   FIELD 11w01 DOUTSET31_0_DIO11 (wo): Writing 1 to this bit sets the DIO11 bit in the DOUT31_0 register. Writing 0 has no effect.
0x400A1290 C   FIELD 12w01 DOUTSET31_0_DIO12 (wo): Writing 1 to this bit sets the DIO12 bit in the DOUT31_0 register. Writing 0 has no effect.
0x400A1290 C   FIELD 13w01 DOUTSET31_0_DIO13 (wo): Writing 1 to this bit sets the DIO13 bit in the DOUT31_0 register. Writing 0 has no effect.
0x400A1290 C   FIELD 14w01 DOUTSET31_0_DIO14 (wo): Writing 1 to this bit sets the DIO14 bit in the DOUT31_0 register. Writing 0 has no effect.
0x400A1290 C   FIELD 15w01 DOUTSET31_0_DIO15 (wo): Writing 1 to this bit sets the DIO15 bit in the DOUT31_0 register. Writing 0 has no effect.
0x400A1290 C   FIELD 16w01 DOUTSET31_0_DIO16 (wo): Writing 1 to this bit sets the DIO16 bit in the DOUT31_0 register. Writing 0 has no effect.
0x400A1290 C   FIELD 17w01 DOUTSET31_0_DIO17 (wo): Writing 1 to this bit sets the DIO17 bit in the DOUT31_0 register. Writing 0 has no effect.
0x400A1290 C   FIELD 18w01 DOUTSET31_0_DIO18 (wo): Writing 1 to this bit sets the DIO18 bit in the DOUT31_0 register. Writing 0 has no effect.
0x400A1290 C   FIELD 19w01 DOUTSET31_0_DIO19 (wo): Writing 1 to this bit sets the DIO19 bit in the DOUT31_0 register. Writing 0 has no effect.
0x400A1290 C   FIELD 20w01 DOUTSET31_0_DIO20 (wo): Writing 1 to this bit sets the DIO20 bit in the DOUT31_0 register. Writing 0 has no effect.
0x400A1290 C   FIELD 21w01 DOUTSET31_0_DIO21 (wo): Writing 1 to this bit sets the DIO21 bit in the DOUT31_0 register. Writing 0 has no effect.
0x400A1290 C   FIELD 22w01 DOUTSET31_0_DIO22 (wo): Writing 1 to this bit sets the DIO22 bit in the DOUT31_0 register. Writing 0 has no effect.
0x400A1290 C   FIELD 23w01 DOUTSET31_0_DIO23 (wo): Writing 1 to this bit sets the DIO23 bit in the DOUT31_0 register. Writing 0 has no effect.
0x400A1290 C   FIELD 24w01 DOUTSET31_0_DIO24 (wo): Writing 1 to this bit sets the DIO24 bit in the DOUT31_0 register. Writing 0 has no effect.
0x400A1290 C   FIELD 25w01 DOUTSET31_0_DIO25 (wo): Writing 1 to this bit sets the DIO25 bit in the DOUT31_0 register. Writing 0 has no effect.
0x400A1290 C   FIELD 26w01 DOUTSET31_0_DIO26 (wo): Writing 1 to this bit sets the DIO26 bit in the DOUT31_0 register. Writing 0 has no effect.
0x400A1290 C   FIELD 27w01 DOUTSET31_0_DIO27 (wo): Writing 1 to this bit sets the DIO27 bit in the DOUT31_0 register. Writing 0 has no effect.
0x400A1290 C   FIELD 28w01 DOUTSET31_0_DIO28 (wo): Writing 1 to this bit sets the DIO28 bit in the DOUT31_0 register. Writing 0 has no effect.
0x400A1290 C   FIELD 29w01 DOUTSET31_0_DIO29 (wo): Writing 1 to this bit sets the DIO29 bit in the DOUT31_0 register. Writing 0 has no effect.
0x400A1290 C   FIELD 30w01 DOUTSET31_0_DIO30 (wo): Writing 1 to this bit sets the DIO30 bit in the DOUT31_0 register. Writing 0 has no effect.
0x400A1290 C   FIELD 31w01 DOUTSET31_0_DIO31 (wo): Writing 1 to this bit sets the DIO31 bit in the DOUT31_0 register. Writing 0 has no effect.
0x400A12A0 B  REGISTER DOUTCLR31_0 (wo): Data output clear 31 to 0
0x400A12A0 C   FIELD 00w01 DOUTCLR31_0_DIO0 (wo): Writing 1 to this bit clears the DIO0 bit in the DOUT31_0 register. Writing 0 has no effect.
0x400A12A0 C   FIELD 01w01 DOUTCLR31_0_DIO1 (wo): Writing 1 to this bit clears the DIO1 bit in the DOUT31_0 register. Writing 0 has no effect.
0x400A12A0 C   FIELD 02w01 DOUTCLR31_0_DIO2 (wo): Writing 1 to this bit clears the DIO2 bit in the DOUT31_0 register. Writing 0 has no effect.
0x400A12A0 C   FIELD 03w01 DOUTCLR31_0_DIO3 (wo): Writing 1 to this bit clears the DIO3 bit in the DOUT31_0 register. Writing 0 has no effect.
0x400A12A0 C   FIELD 04w01 DOUTCLR31_0_DIO4 (wo): Writing 1 to this bit clears the DIO4 bit in the DOUT31_0 register. Writing 0 has no effect.
0x400A12A0 C   FIELD 05w01 DOUTCLR31_0_DIO5 (wo): Writing 1 to this bit clears the DIO5 bit in the DOUT31_0 register. Writing 0 has no effect.
0x400A12A0 C   FIELD 06w01 DOUTCLR31_0_DIO6 (wo): Writing 1 to this bit clears the DIO6 bit in the DOUT31_0 register. Writing 0 has no effect.
0x400A12A0 C   FIELD 07w01 DOUTCLR31_0_DIO7 (wo): Writing 1 to this bit clears the DIO7 bit in the DOUT31_0 register. Writing 0 has no effect.
0x400A12A0 C   FIELD 08w01 DOUTCLR31_0_DIO8 (wo): Writing 1 to this bit clears the DIO8 bit in the DOUT31_0 register. Writing 0 has no effect.
0x400A12A0 C   FIELD 09w01 DOUTCLR31_0_DIO9 (wo): Writing 1 to this bit clears the DIO9 bit in the DOUT31_0 register. Writing 0 has no effect.
0x400A12A0 C   FIELD 10w01 DOUTCLR31_0_DIO10 (wo): Writing 1 to this bit clears the DIO10 bit in the DOUT31_0 register. Writing 0 has no effect.
0x400A12A0 C   FIELD 11w01 DOUTCLR31_0_DIO11 (wo): Writing 1 to this bit clears the DIO11 bit in the DOUT31_0 register. Writing 0 has no effect.
0x400A12A0 C   FIELD 12w01 DOUTCLR31_0_DIO12 (wo): Writing 1 to this bit clears the DIO12 bit in the DOUT31_0 register. Writing 0 has no effect.
0x400A12A0 C   FIELD 13w01 DOUTCLR31_0_DIO13 (wo): Writing 1 to this bit clears the DIO13 bit in the DOUT31_0 register. Writing 0 has no effect.
0x400A12A0 C   FIELD 14w01 DOUTCLR31_0_DIO14 (wo): Writing 1 to this bit clears the DIO14 bit in the DOUT31_0 register. Writing 0 has no effect.
0x400A12A0 C   FIELD 15w01 DOUTCLR31_0_DIO15 (wo): Writing 1 to this bit clears the DIO15 bit in the DOUT31_0 register. Writing 0 has no effect.
0x400A12A0 C   FIELD 16w01 DOUTCLR31_0_DIO16 (wo): Writing 1 to this bit clears the DIO16 bit in the DOUT31_0 register. Writing 0 has no effect.
0x400A12A0 C   FIELD 17w01 DOUTCLR31_0_DIO17 (wo): Writing 1 to this bit clears the DIO17 bit in the DOUT31_0 register. Writing 0 has no effect.
0x400A12A0 C   FIELD 18w01 DOUTCLR31_0_DIO18 (wo): Writing 1 to this bit clears the DIO18 bit in the DOUT31_0 register. Writing 0 has no effect.
0x400A12A0 C   FIELD 19w01 DOUTCLR31_0_DIO19 (wo): Writing 1 to this bit clears the DIO19 bit in the DOUT31_0 register. Writing 0 has no effect.
0x400A12A0 C   FIELD 20w01 DOUTCLR31_0_DIO20 (wo): Writing 1 to this bit clears the DIO20 bit in the DOUT31_0 register. Writing 0 has no effect.
0x400A12A0 C   FIELD 21w01 DOUTCLR31_0_DIO21 (wo): Writing 1 to this bit clears the DIO21 bit in the DOUT31_0 register. Writing 0 has no effect.
0x400A12A0 C   FIELD 22w01 DOUTCLR31_0_DIO22 (wo): Writing 1 to this bit clears the DIO22 bit in the DOUT31_0 register. Writing 0 has no effect.
0x400A12A0 C   FIELD 23w01 DOUTCLR31_0_DIO23 (wo): Writing 1 to this bit clears the DIO23 bit in the DOUT31_0 register. Writing 0 has no effect.
0x400A12A0 C   FIELD 24w01 DOUTCLR31_0_DIO24 (wo): Writing 1 to this bit clears the DIO24 bit in the DOUT31_0 register. Writing 0 has no effect.
0x400A12A0 C   FIELD 25w01 DOUTCLR31_0_DIO25 (wo): Writing 1 to this bit clears the DIO25 bit in the DOUT31_0 register. Writing 0 has no effect.
0x400A12A0 C   FIELD 26w01 DOUTCLR31_0_DIO26 (wo): Writing 1 to this bit clears the DIO26 bit in the DOUT31_0 register. Writing 0 has no effect.
0x400A12A0 C   FIELD 27w01 DOUTCLR31_0_DIO27 (wo): Writing 1 to this bit clears the DIO27 bit in the DOUT31_0 register. Writing 0 has no effect.
0x400A12A0 C   FIELD 28w01 DOUTCLR31_0_DIO28 (wo): Writing 1 to this bit clears the DIO28 bit in the DOUT31_0 register. Writing 0 has no effect.
0x400A12A0 C   FIELD 29w01 DOUTCLR31_0_DIO29 (wo): Writing 1 to this bit clears the DIO29 bit in the DOUT31_0 register. Writing 0 has no effect.
0x400A12A0 C   FIELD 30w01 DOUTCLR31_0_DIO30 (wo): Writing 1 to this bit clears the DIO30 bit in the DOUT31_0 register. Writing 0 has no effect.
0x400A12A0 C   FIELD 31w01 DOUTCLR31_0_DIO31 (wo): Writing 1 to this bit clears the DIO31 bit in the DOUT31_0 register. Writing 0 has no effect.
0x400A12B0 B  REGISTER DOUTTGL31_0 (wo): Data output toggle 31 to 0
0x400A12B0 C   FIELD 00w01 DOUTTGL31_0_DIO0 (wo): This bit is used to toggle DIO0 output.
0x400A12B0 C   FIELD 01w01 DOUTTGL31_0_DIO1 (wo): This bit is used to toggle DIO1 output.
0x400A12B0 C   FIELD 02w01 DOUTTGL31_0_DIO2 (wo): This bit is used to toggle DIO2 output.
0x400A12B0 C   FIELD 03w01 DOUTTGL31_0_DIO3 (wo): This bit is used to toggle DIO3 output.
0x400A12B0 C   FIELD 04w01 DOUTTGL31_0_DIO4 (wo): This bit is used to toggle DIO4 output.
0x400A12B0 C   FIELD 05w01 DOUTTGL31_0_DIO5 (wo): This bit is used to toggle DIO5 output.
0x400A12B0 C   FIELD 06w01 DOUTTGL31_0_DIO6 (wo): This bit is used to toggle DIO6 output.
0x400A12B0 C   FIELD 07w01 DOUTTGL31_0_DIO7 (wo): This bit is used to toggle DIO7 output.
0x400A12B0 C   FIELD 08w01 DOUTTGL31_0_DIO8 (wo): This bit is used to toggle DIO8 output.
0x400A12B0 C   FIELD 09w01 DOUTTGL31_0_DIO9 (wo): This bit is used to toggle DIO9 output.
0x400A12B0 C   FIELD 10w01 DOUTTGL31_0_DIO10 (wo): This bit is used to toggle DIO10 output.
0x400A12B0 C   FIELD 11w01 DOUTTGL31_0_DIO11 (wo): This bit is used to toggle DIO11 output.
0x400A12B0 C   FIELD 12w01 DOUTTGL31_0_DIO12 (wo): This bit is used to toggle DIO12 output.
0x400A12B0 C   FIELD 13w01 DOUTTGL31_0_DIO13 (wo): This bit is used to toggle DIO13 output.
0x400A12B0 C   FIELD 14w01 DOUTTGL31_0_DIO14 (wo): This bit is used to toggle DIO14 output.
0x400A12B0 C   FIELD 15w01 DOUTTGL31_0_DIO15 (wo): This bit is used to toggle DIO15 output.
0x400A12B0 C   FIELD 16w01 DOUTTGL31_0_DIO16 (wo): This bit is used to toggle DIO16 output.
0x400A12B0 C   FIELD 17w01 DOUTTGL31_0_DIO17 (wo): This bit is used to toggle DIO17 output.
0x400A12B0 C   FIELD 18w01 DOUTTGL31_0_DIO18 (wo): This bit is used to toggle DIO18 output.
0x400A12B0 C   FIELD 19w01 DOUTTGL31_0_DIO19 (wo): This bit is used to toggle DIO19 output.
0x400A12B0 C   FIELD 20w01 DOUTTGL31_0_DIO20 (wo): This bit is used to toggle DIO20 output.
0x400A12B0 C   FIELD 21w01 DOUTTGL31_0_DIO21 (wo): This bit is used to toggle DIO21 output.
0x400A12B0 C   FIELD 22w01 DOUTTGL31_0_DIO22 (wo): This bit is used to toggle DIO22 output.
0x400A12B0 C   FIELD 23w01 DOUTTGL31_0_DIO23 (wo): This bit is used to toggle DIO23 output.
0x400A12B0 C   FIELD 24w01 DOUTTGL31_0_DIO24 (wo): This bit is used to toggle DIO24 output.
0x400A12B0 C   FIELD 25w01 DOUTTGL31_0_DIO25 (wo): This bit is used to toggle DIO25 output.
0x400A12B0 C   FIELD 26w01 DOUTTGL31_0_DIO26 (wo): This bit is used to toggle DIO26 output.
0x400A12B0 C   FIELD 27w01 DOUTTGL31_0_DIO27 (wo): This bit is used to toggle DIO27 output.
0x400A12B0 C   FIELD 28w01 DOUTTGL31_0_DIO28 (wo): This bit is used to toggle DIO28 output.
0x400A12B0 C   FIELD 29w01 DOUTTGL31_0_DIO29 (wo): This bit is used to toggle DIO29 output.
0x400A12B0 C   FIELD 30w01 DOUTTGL31_0_DIO30 (wo): This bit is used to toggle DIO30 output.
0x400A12B0 C   FIELD 31w01 DOUTTGL31_0_DIO31 (wo): This bit is used to toggle DIO31 output.
0x400A12C0 B  REGISTER DOE31_0 (rw): Data output enable 31 to 0
0x400A12C0 C   FIELD 00w01 DOE31_0_DIO0 (rw): Enables data output for DIO0.
0x400A12C0 C   FIELD 01w01 DOE31_0_DIO1 (rw): Enables data output for DIO1.
0x400A12C0 C   FIELD 02w01 DOE31_0_DIO2 (rw): Enables data output for DIO2.
0x400A12C0 C   FIELD 03w01 DOE31_0_DIO3 (rw): Enables data output for DIO3.
0x400A12C0 C   FIELD 04w01 DOE31_0_DIO4 (rw): Enables data output for DIO4.
0x400A12C0 C   FIELD 05w01 DOE31_0_DIO5 (rw): Enables data output for DIO5.
0x400A12C0 C   FIELD 06w01 DOE31_0_DIO6 (rw): Enables data output for DIO6.
0x400A12C0 C   FIELD 07w01 DOE31_0_DIO7 (rw): Enables data output for DIO7.
0x400A12C0 C   FIELD 08w01 DOE31_0_DIO8 (rw): Enables data output for DIO8.
0x400A12C0 C   FIELD 09w01 DOE31_0_DIO9 (rw): Enables data output for DIO9.
0x400A12C0 C   FIELD 10w01 DOE31_0_DIO10 (rw): Enables data output for DIO10.
0x400A12C0 C   FIELD 11w01 DOE31_0_DIO11 (rw): Enables data output for DIO11.
0x400A12C0 C   FIELD 12w01 DOE31_0_DIO12 (rw): Enables data output for DIO12.
0x400A12C0 C   FIELD 13w01 DOE31_0_DIO13 (rw): Enables data output for DIO13.
0x400A12C0 C   FIELD 14w01 DOE31_0_DIO14 (rw): Enables data output for DIO14.
0x400A12C0 C   FIELD 15w01 DOE31_0_DIO15 (rw): Enables data output for DIO15.
0x400A12C0 C   FIELD 16w01 DOE31_0_DIO16 (rw): Enables data output for DIO16.
0x400A12C0 C   FIELD 17w01 DOE31_0_DIO17 (rw): Enables data output for DIO17.
0x400A12C0 C   FIELD 18w01 DOE31_0_DIO18 (rw): Enables data output for DIO18.
0x400A12C0 C   FIELD 19w01 DOE31_0_DIO19 (rw): Enables data output for DIO19.
0x400A12C0 C   FIELD 20w01 DOE31_0_DIO20 (rw): Enables data output for DIO20.
0x400A12C0 C   FIELD 21w01 DOE31_0_DIO21 (rw): Enables data output for DIO21.
0x400A12C0 C   FIELD 22w01 DOE31_0_DIO22 (rw): Enables data output for DIO22.
0x400A12C0 C   FIELD 23w01 DOE31_0_DIO23 (rw): Enables data output for DIO23.
0x400A12C0 C   FIELD 24w01 DOE31_0_DIO24 (rw): Enables data output for DIO24.
0x400A12C0 C   FIELD 25w01 DOE31_0_DIO25 (rw): Enables data output for DIO25.
0x400A12C0 C   FIELD 26w01 DOE31_0_DIO26 (rw): Enables data output for DIO26.
0x400A12C0 C   FIELD 27w01 DOE31_0_DIO27 (rw): Enables data output for DIO27.
0x400A12C0 C   FIELD 28w01 DOE31_0_DIO28 (rw): Enables data output for DIO28.
0x400A12C0 C   FIELD 29w01 DOE31_0_DIO29 (rw): Enables data output for DIO29.
0x400A12C0 C   FIELD 30w01 DOE31_0_DIO30 (rw): Enables data output for DIO30.
0x400A12C0 C   FIELD 31w01 DOE31_0_DIO31 (rw): Enables data output for DIO31.
0x400A12D0 B  REGISTER DOESET31_0 (wo): Data output enable set 31 to 0
0x400A12D0 C   FIELD 00w01 DOESET31_0_DIO0 (wo): Writing 1 to this bit sets the DIO0 bit in the DOE31_0 register. Writing 0 has no effect.
0x400A12D0 C   FIELD 01w01 DOESET31_0_DIO1 (wo): Writing 1 to this bit sets the DIO1 bit in the DOE31_0 register. Writing 0 has no effect.
0x400A12D0 C   FIELD 02w01 DOESET31_0_DIO2 (wo): Writing 1 to this bit sets the DIO2 bit in the DOE31_0 register. Writing 0 has no effect.
0x400A12D0 C   FIELD 03w01 DOESET31_0_DIO3 (wo): Writing 1 to this bit sets the DIO3 bit in the DOE31_0 register. Writing 0 has no effect.
0x400A12D0 C   FIELD 04w01 DOESET31_0_DIO4 (wo): Writing 1 to this bit sets the DIO4 bit in the DOE31_0 register. Writing 0 has no effect.
0x400A12D0 C   FIELD 05w01 DOESET31_0_DIO5 (wo): Writing 1 to this bit sets the DIO5 bit in the DOE31_0 register. Writing 0 has no effect.
0x400A12D0 C   FIELD 06w01 DOESET31_0_DIO6 (wo): Writing 1 to this bit sets the DIO6 bit in the DOE31_0 register. Writing 0 has no effect.
0x400A12D0 C   FIELD 07w01 DOESET31_0_DIO7 (wo): Writing 1 to this bit sets the DIO7 bit in the DOE31_0 register. Writing 0 has no effect.
0x400A12D0 C   FIELD 08w01 DOESET31_0_DIO8 (wo): Writing 1 to this bit sets the DIO8 bit in the DOE31_0 register. Writing 0 has no effect.
0x400A12D0 C   FIELD 09w01 DOESET31_0_DIO9 (wo): Writing 1 to this bit sets the DIO9 bit in the DOE31_0 register. Writing 0 has no effect.
0x400A12D0 C   FIELD 10w01 DOESET31_0_DIO10 (wo): Writing 1 to this bit sets the DIO10 bit in the DOE31_0 register. Writing 0 has no effect.
0x400A12D0 C   FIELD 11w01 DOESET31_0_DIO11 (wo): Writing 1 to this bit sets the DIO11 bit in the DOE31_0 register. Writing 0 has no effect.
0x400A12D0 C   FIELD 12w01 DOESET31_0_DIO12 (wo): Writing 1 to this bit sets the DIO12 bit in the DOE31_0 register. Writing 0 has no effect.
0x400A12D0 C   FIELD 13w01 DOESET31_0_DIO13 (wo): Writing 1 to this bit sets the DIO13 bit in the DOE31_0 register. Writing 0 has no effect.
0x400A12D0 C   FIELD 14w01 DOESET31_0_DIO14 (wo): Writing 1 to this bit sets the DIO14 bit in the DOE31_0 register. Writing 0 has no effect.
0x400A12D0 C   FIELD 15w01 DOESET31_0_DIO15 (wo): Writing 1 to this bit sets the DIO15 bit in the DOE31_0 register. Writing 0 has no effect.
0x400A12D0 C   FIELD 16w01 DOESET31_0_DIO16 (wo): Writing 1 to this bit sets the DIO16 bit in the DOE31_0 register. Writing 0 has no effect.
0x400A12D0 C   FIELD 17w01 DOESET31_0_DIO17 (wo): Writing 1 to this bit sets the DIO17 bit in the DOE31_0 register. Writing 0 has no effect.
0x400A12D0 C   FIELD 18w01 DOESET31_0_DIO18 (wo): Writing 1 to this bit sets the DIO18 bit in the DOE31_0 register. Writing 0 has no effect.
0x400A12D0 C   FIELD 19w01 DOESET31_0_DIO19 (wo): Writing 1 to this bit sets the DIO19 bit in the DOE31_0 register. Writing 0 has no effect.
0x400A12D0 C   FIELD 20w01 DOESET31_0_DIO20 (wo): Writing 1 to this bit sets the DIO20 bit in the DOE31_0 register. Writing 0 has no effect.
0x400A12D0 C   FIELD 21w01 DOESET31_0_DIO21 (wo): Writing 1 to this bit sets the DIO21 bit in the DOE31_0 register. Writing 0 has no effect.
0x400A12D0 C   FIELD 22w01 DOESET31_0_DIO22 (wo): Writing 1 to this bit sets the DIO22 bit in the DOE31_0 register. Writing 0 has no effect.
0x400A12D0 C   FIELD 23w01 DOESET31_0_DIO23 (wo): Writing 1 to this bit sets the DIO23 bit in the DOE31_0 register. Writing 0 has no effect.
0x400A12D0 C   FIELD 24w01 DOESET31_0_DIO24 (wo): Writing 1 to this bit sets the DIO24 bit in the DOE31_0 register. Writing 0 has no effect.
0x400A12D0 C   FIELD 25w01 DOESET31_0_DIO25 (wo): Writing 1 to this bit sets the DIO25 bit in the DOE31_0 register. Writing 0 has no effect.
0x400A12D0 C   FIELD 26w01 DOESET31_0_DIO26 (wo): Writing 1 to this bit sets the DIO26 bit in the DOE31_0 register. Writing 0 has no effect.
0x400A12D0 C   FIELD 27w01 DOESET31_0_DIO27 (wo): Writing 1 to this bit sets the DIO27 bit in the DOE31_0 register. Writing 0 has no effect.
0x400A12D0 C   FIELD 28w01 DOESET31_0_DIO28 (wo): Writing 1 to this bit sets the DIO28 bit in the DOE31_0 register. Writing 0 has no effect.
0x400A12D0 C   FIELD 29w01 DOESET31_0_DIO29 (wo): Writing 1 to this bit sets the DIO29 bit in the DOE31_0 register. Writing 0 has no effect.
0x400A12D0 C   FIELD 30w01 DOESET31_0_DIO30 (wo): Writing 1 to this bit sets the DIO30 bit in the DOE31_0 register. Writing 0 has no effect.
0x400A12D0 C   FIELD 31w01 DOESET31_0_DIO31 (wo): Writing 1 to this bit sets the DIO31 bit in the DOE31_0 register. Writing 0 has no effect.
0x400A12E0 B  REGISTER DOECLR31_0 (wo): Data output enable clear 31 to 0
0x400A12E0 C   FIELD 00w01 DOECLR31_0_DIO0 (wo): Writing 1 to this bit clears the DIO0 bit in the DOE31_0 register. Writing 0 has no effect.
0x400A12E0 C   FIELD 01w01 DOECLR31_0_DIO1 (wo): Writing 1 to this bit clears the DIO1 bit in the DOE31_0 register. Writing 0 has no effect.
0x400A12E0 C   FIELD 02w01 DOECLR31_0_DIO2 (wo): Writing 1 to this bit clears the DIO2 bit in the DOE31_0 register. Writing 0 has no effect.
0x400A12E0 C   FIELD 03w01 DOECLR31_0_DIO3 (wo): Writing 1 to this bit clears the DIO3 bit in the DOE31_0 register. Writing 0 has no effect.
0x400A12E0 C   FIELD 04w01 DOECLR31_0_DIO4 (wo): Writing 1 to this bit clears the DIO4 bit in the DOE31_0 register. Writing 0 has no effect.
0x400A12E0 C   FIELD 05w01 DOECLR31_0_DIO5 (wo): Writing 1 to this bit clears the DIO5 bit in the DOE31_0 register. Writing 0 has no effect.
0x400A12E0 C   FIELD 06w01 DOECLR31_0_DIO6 (wo): Writing 1 to this bit clears the DIO6 bit in the DOE31_0 register. Writing 0 has no effect.
0x400A12E0 C   FIELD 07w01 DOECLR31_0_DIO7 (wo): Writing 1 to this bit clears the DIO7 bit in the DOE31_0 register. Writing 0 has no effect.
0x400A12E0 C   FIELD 08w01 DOECLR31_0_DIO8 (wo): Writing 1 to this bit clears the DIO8 bit in the DOE31_0 register. Writing 0 has no effect.
0x400A12E0 C   FIELD 09w01 DOECLR31_0_DIO9 (wo): Writing 1 to this bit clears the DIO9 bit in the DOE31_0 register. Writing 0 has no effect.
0x400A12E0 C   FIELD 10w01 DOECLR31_0_DIO10 (wo): Writing 1 to this bit clears the DIO10 bit in the DOE31_0 register. Writing 0 has no effect.
0x400A12E0 C   FIELD 11w01 DOECLR31_0_DIO11 (wo): Writing 1 to this bit clears the DIO11 bit in the DOE31_0 register. Writing 0 has no effect.
0x400A12E0 C   FIELD 12w01 DOECLR31_0_DIO12 (wo): Writing 1 to this bit clears the DIO12 bit in the DOE31_0 register. Writing 0 has no effect.
0x400A12E0 C   FIELD 13w01 DOECLR31_0_DIO13 (wo): Writing 1 to this bit clears the DIO13 bit in the DOE31_0 register. Writing 0 has no effect.
0x400A12E0 C   FIELD 14w01 DOECLR31_0_DIO14 (wo): Writing 1 to this bit clears the DIO14 bit in the DOE31_0 register. Writing 0 has no effect.
0x400A12E0 C   FIELD 15w01 DOECLR31_0_DIO15 (wo): Writing 1 to this bit clears the DIO15 bit in the DOE31_0 register. Writing 0 has no effect.
0x400A12E0 C   FIELD 16w01 DOECLR31_0_DIO16 (wo): Writing 1 to this bit clears the DIO16 bit in the DOE31_0 register. Writing 0 has no effect.
0x400A12E0 C   FIELD 17w01 DOECLR31_0_DIO17 (wo): Writing 1 to this bit clears the DIO17 bit in the DOE31_0 register. Writing 0 has no effect.
0x400A12E0 C   FIELD 18w01 DOECLR31_0_DIO18 (wo): Writing 1 to this bit clears the DIO18 bit in the DOE31_0 register. Writing 0 has no effect.
0x400A12E0 C   FIELD 19w01 DOECLR31_0_DIO19 (wo): Writing 1 to this bit clears the DIO19 bit in the DOE31_0 register. Writing 0 has no effect.
0x400A12E0 C   FIELD 20w01 DOECLR31_0_DIO20 (wo): Writing 1 to this bit clears the DIO20 bit in the DOE31_0 register. Writing 0 has no effect.
0x400A12E0 C   FIELD 21w01 DOECLR31_0_DIO21 (wo): Writing 1 to this bit clears the DIO21 bit in the DOE31_0 register. Writing 0 has no effect.
0x400A12E0 C   FIELD 22w01 DOECLR31_0_DIO22 (wo): Writing 1 to this bit clears the DIO22 bit in the DOE31_0 register. Writing 0 has no effect.
0x400A12E0 C   FIELD 23w01 DOECLR31_0_DIO23 (wo): Writing 1 to this bit clears the DIO23 bit in the DOE31_0 register. Writing 0 has no effect.
0x400A12E0 C   FIELD 24w01 DOECLR31_0_DIO24 (wo): Writing 1 to this bit clears the DIO24 bit in the DOE31_0 register. Writing 0 has no effect.
0x400A12E0 C   FIELD 25w01 DOECLR31_0_DIO25 (wo): Writing 1 to this bit clears the DIO25 bit in the DOE31_0 register. Writing 0 has no effect.
0x400A12E0 C   FIELD 26w01 DOECLR31_0_DIO26 (wo): Writing 1 to this bit clears the DIO26 bit in the DOE31_0 register. Writing 0 has no effect.
0x400A12E0 C   FIELD 27w01 DOECLR31_0_DIO27 (wo): Writing 1 to this bit clears the DIO27 bit in the DOE31_0 register. Writing 0 has no effect.
0x400A12E0 C   FIELD 28w01 DOECLR31_0_DIO28 (wo): Writing 1 to this bit clears the DIO28 bit in the DOE31_0 register. Writing 0 has no effect.
0x400A12E0 C   FIELD 29w01 DOECLR31_0_DIO29 (wo): Writing 1 to this bit clears the DIO29 bit in the DOE31_0 register. Writing 0 has no effect.
0x400A12E0 C   FIELD 30w01 DOECLR31_0_DIO30 (wo): Writing 1 to this bit clears the DIO30 bit in the DOE31_0 register. Writing 0 has no effect.
0x400A12E0 C   FIELD 31w01 DOECLR31_0_DIO31 (wo): Writing 1 to this bit clears the DIO31 bit in the DOE31_0 register. Writing 0 has no effect.
0x400A1300 B  REGISTER DIN3_0 (ro): Data input 3 to 0
0x400A1300 C   FIELD 00w01 DIN3_0_DIO0 (ro): This bit reads the data input value of DIO0.
0x400A1300 C   FIELD 08w01 DIN3_0_DIO1 (ro): This bit reads the data input value of DIO1.
0x400A1300 C   FIELD 16w01 DIN3_0_DIO2 (ro): This bit reads the data input value of DIO2.
0x400A1300 C   FIELD 24w01 DIN3_0_DIO3 (ro): This bit reads the data input value of DIO3.
0x400A1304 B  REGISTER DIN7_4 (ro): Data input 7 to 4
0x400A1304 C   FIELD 00w01 DIN7_4_DIO4 (ro): This bit reads the data input value of DIO4.
0x400A1304 C   FIELD 08w01 DIN7_4_DIO5 (ro): This bit reads the data input value of DIO5.
0x400A1304 C   FIELD 16w01 DIN7_4_DIO6 (ro): This bit reads the data input value of DIO6.
0x400A1304 C   FIELD 24w01 DIN7_4_DIO7 (ro): This bit reads the data input value of DIO7.
0x400A1308 B  REGISTER DIN11_8 (ro): Data input 11 to 8
0x400A1308 C   FIELD 00w01 DIN11_8_DIO8 (ro): This bit reads the data input value of DIO8.
0x400A1308 C   FIELD 08w01 DIN11_8_DIO9 (ro): This bit reads the data input value of DIO9.
0x400A1308 C   FIELD 16w01 DIN11_8_DIO10 (ro): This bit reads the data input value of DIO10.
0x400A1308 C   FIELD 24w01 DIN11_8_DIO11 (ro): This bit reads the data input value of DIO11.
0x400A130C B  REGISTER DIN15_12 (ro): Data input 15 to 12
0x400A130C C   FIELD 00w01 DIN15_12_DIO12 (ro): This bit reads the data input value of DIO12.
0x400A130C C   FIELD 08w01 DIN15_12_DIO13 (ro): This bit reads the data input value of DIO13.
0x400A130C C   FIELD 16w01 DIN15_12_DIO14 (ro): This bit reads the data input value of DIO14.
0x400A130C C   FIELD 24w01 DIN15_12_DIO15 (ro): This bit reads the data input value of DIO15.
0x400A1310 B  REGISTER DIN19_16 (ro): Data input 19 to 16
0x400A1310 C   FIELD 00w01 DIN19_16_DIO16 (ro): This bit reads the data input value of DIO16.
0x400A1310 C   FIELD 08w01 DIN19_16_DIO17 (ro): This bit reads the data input value of DIO17.
0x400A1310 C   FIELD 16w01 DIN19_16_DIO18 (ro): This bit reads the data input value of DIO18.
0x400A1310 C   FIELD 24w01 DIN19_16_DIO19 (ro): This bit reads the data input value of DIO19.
0x400A1314 B  REGISTER DIN23_20 (ro): Data input 23 to 20
0x400A1314 C   FIELD 00w01 DIN23_20_DIO20 (ro): This bit reads the data input value of DIO20.
0x400A1314 C   FIELD 08w01 DIN23_20_DIO21 (ro): This bit reads the data input value of DIO21.
0x400A1314 C   FIELD 16w01 DIN23_20_DIO22 (ro): This bit reads the data input value of DIO22.
0x400A1314 C   FIELD 24w01 DIN23_20_DIO23 (ro): This bit reads the data input value of DIO23.
0x400A1318 B  REGISTER DIN27_24 (ro): Data input 27 to 24
0x400A1318 C   FIELD 00w01 DIN27_24_DIO24 (ro): This bit reads the data input value of DIO24.
0x400A1318 C   FIELD 08w01 DIN27_24_DIO25 (ro): This bit reads the data input value of DIO25.
0x400A1318 C   FIELD 16w01 DIN27_24_DIO26 (ro): This bit reads the data input value of DIO26.
0x400A1318 C   FIELD 24w01 DIN27_24_DIO27 (ro): This bit reads the data input value of DIO27.
0x400A131C B  REGISTER DIN31_28 (ro): Data input 31 to 28
0x400A131C C   FIELD 00w01 DIN31_28_DIO28 (ro): This bit reads the data input value of DIO28.
0x400A131C C   FIELD 08w01 DIN31_28_DIO29 (ro): This bit reads the data input value of DIO29.
0x400A131C C   FIELD 16w01 DIN31_28_DIO30 (ro): This bit reads the data input value of DIO30.
0x400A131C C   FIELD 24w01 DIN31_28_DIO31 (ro): This bit reads the data input value of DIO31.
0x400A1380 B  REGISTER DIN31_0 (ro): Data input 31 to 0
0x400A1380 C   FIELD 00w01 DIN31_0_DIO0 (ro): This bit reads the data input value of DIO0.
0x400A1380 C   FIELD 01w01 DIN31_0_DIO1 (ro): This bit reads the data input value of DIO1.
0x400A1380 C   FIELD 02w01 DIN31_0_DIO2 (ro): This bit reads the data input value of DIO2.
0x400A1380 C   FIELD 03w01 DIN31_0_DIO3 (ro): This bit reads the data input value of DIO3.
0x400A1380 C   FIELD 04w01 DIN31_0_DIO4 (ro): This bit reads the data input value of DIO4.
0x400A1380 C   FIELD 05w01 DIN31_0_DIO5 (ro): This bit reads the data input value of DIO5.
0x400A1380 C   FIELD 06w01 DIN31_0_DIO6 (ro): This bit reads the data input value of DIO6.
0x400A1380 C   FIELD 07w01 DIN31_0_DIO7 (ro): This bit reads the data input value of DIO7.
0x400A1380 C   FIELD 08w01 DIN31_0_DIO8 (ro): This bit reads the data input value of DIO8.
0x400A1380 C   FIELD 09w01 DIN31_0_DIO9 (ro): This bit reads the data input value of DIO9.
0x400A1380 C   FIELD 10w01 DIN31_0_DIO10 (ro): This bit reads the data input value of DIO10.
0x400A1380 C   FIELD 11w01 DIN31_0_DIO11 (ro): This bit reads the data input value of DIO11.
0x400A1380 C   FIELD 12w01 DIN31_0_DIO12 (ro): This bit reads the data input value of DIO12.
0x400A1380 C   FIELD 13w01 DIN31_0_DIO13 (ro): This bit reads the data input value of DIO13.
0x400A1380 C   FIELD 14w01 DIN31_0_DIO14 (ro): This bit reads the data input value of DIO14.
0x400A1380 C   FIELD 15w01 DIN31_0_DIO15 (ro): This bit reads the data input value of DIO15.
0x400A1380 C   FIELD 16w01 DIN31_0_DIO16 (ro): This bit reads the data input value of DIO16.
0x400A1380 C   FIELD 17w01 DIN31_0_DIO17 (ro): This bit reads the data input value of DIO17.
0x400A1380 C   FIELD 18w01 DIN31_0_DIO18 (ro): This bit reads the data input value of DIO18.
0x400A1380 C   FIELD 19w01 DIN31_0_DIO19 (ro): This bit reads the data input value of DIO19.
0x400A1380 C   FIELD 20w01 DIN31_0_DIO20 (ro): This bit reads the data input value of DIO20.
0x400A1380 C   FIELD 21w01 DIN31_0_DIO21 (ro): This bit reads the data input value of DIO21.
0x400A1380 C   FIELD 22w01 DIN31_0_DIO22 (ro): This bit reads the data input value of DIO22.
0x400A1380 C   FIELD 23w01 DIN31_0_DIO23 (ro): This bit reads the data input value of DIO23.
0x400A1380 C   FIELD 24w01 DIN31_0_DIO24 (ro): This bit reads the data input value of DIO24.
0x400A1380 C   FIELD 25w01 DIN31_0_DIO25 (ro): This bit reads the data input value of DIO25.
0x400A1380 C   FIELD 26w01 DIN31_0_DIO26 (ro): This bit reads the data input value of DIO26.
0x400A1380 C   FIELD 27w01 DIN31_0_DIO27 (ro): This bit reads the data input value of DIO27.
0x400A1380 C   FIELD 28w01 DIN31_0_DIO28 (ro): This bit reads the data input value of DIO28.
0x400A1380 C   FIELD 29w01 DIN31_0_DIO29 (ro): This bit reads the data input value of DIO29.
0x400A1380 C   FIELD 30w01 DIN31_0_DIO30 (ro): This bit reads the data input value of DIO30.
0x400A1380 C   FIELD 31w01 DIN31_0_DIO31 (ro): This bit reads the data input value of DIO31.
0x400A1390 B  REGISTER POLARITY15_0 (rw): Polarity 15 to 0
0x400A1390 C   FIELD 00w02 POLARITY15_0_DIO0 (rw): Enables and configures edge detection polarity for DIO0.
0x400A1390 C   FIELD 02w02 POLARITY15_0_DIO1 (rw): Enables and configures edge detection polarity for DIO1.
0x400A1390 C   FIELD 04w02 POLARITY15_0_DIO2 (rw): Enables and configures edge detection polarity for DIO2.
0x400A1390 C   FIELD 06w02 POLARITY15_0_DIO3 (rw): Enables and configures edge detection polarity for DIO3.
0x400A1390 C   FIELD 08w02 POLARITY15_0_DIO4 (rw): Enables and configures edge detection polarity for DIO4.
0x400A1390 C   FIELD 10w02 POLARITY15_0_DIO5 (rw): Enables and configures edge detection polarity for DIO5.
0x400A1390 C   FIELD 12w02 POLARITY15_0_DIO6 (rw): Enables and configures edge detection polarity for DIO6.
0x400A1390 C   FIELD 14w02 POLARITY15_0_DIO7 (rw): Enables and configures edge detection polarity for DIO7.
0x400A1390 C   FIELD 16w02 POLARITY15_0_DIO8 (rw): Enables and configures edge detection polarity for DIO8.
0x400A1390 C   FIELD 18w02 POLARITY15_0_DIO9 (rw): Enables and configures edge detection polarity for DIO9.
0x400A1390 C   FIELD 20w02 POLARITY15_0_DIO10 (rw): Enables and configures edge detection polarity for DIO10.
0x400A1390 C   FIELD 22w02 POLARITY15_0_DIO11 (rw): Enables and configures edge detection polarity for DIO11.
0x400A1390 C   FIELD 24w02 POLARITY15_0_DIO12 (rw): Enables and configures edge detection polarity for DIO12.
0x400A1390 C   FIELD 26w02 POLARITY15_0_DIO13 (rw): Enables and configures edge detection polarity for DIO13.
0x400A1390 C   FIELD 28w02 POLARITY15_0_DIO14 (rw): Enables and configures edge detection polarity for DIO14.
0x400A1390 C   FIELD 30w02 POLARITY15_0_DIO15 (rw): Enables and configures edge detection polarity for DIO15.
0x400A13A0 B  REGISTER POLARITY31_16 (rw): Polarity 31 to 16
0x400A13A0 C   FIELD 00w02 POLARITY31_16_DIO16 (rw): Enables and configures edge detection polarity for DIO16.
0x400A13A0 C   FIELD 02w02 POLARITY31_16_DIO17 (rw): Enables and configures edge detection polarity for DIO17.
0x400A13A0 C   FIELD 04w02 POLARITY31_16_DIO18 (rw): Enables and configures edge detection polarity for DIO18.
0x400A13A0 C   FIELD 06w02 POLARITY31_16_DIO19 (rw): Enables and configures edge detection polarity for DIO19.
0x400A13A0 C   FIELD 08w02 POLARITY31_16_DIO20 (rw): Enables and configures edge detection polarity for DIO20.
0x400A13A0 C   FIELD 10w02 POLARITY31_16_DIO21 (rw): Enables and configures edge detection polarity for DIO21.
0x400A13A0 C   FIELD 12w02 POLARITY31_16_DIO22 (rw): Enables and configures edge detection polarity for DIO22.
0x400A13A0 C   FIELD 14w02 POLARITY31_16_DIO23 (rw): Enables and configures edge detection polarity for DIO23.
0x400A13A0 C   FIELD 16w02 POLARITY31_16_DIO24 (rw): Enables and configures edge detection polarity for DIO24.
0x400A13A0 C   FIELD 18w02 POLARITY31_16_DIO25 (rw): Enables and configures edge detection polarity for DIO25.
0x400A13A0 C   FIELD 20w02 POLARITY31_16_DIO26 (rw): Enables and configures edge detection polarity for DIO26.
0x400A13A0 C   FIELD 22w02 POLARITY31_16_DIO27 (rw): Enables and configures edge detection polarity for DIO27.
0x400A13A0 C   FIELD 24w02 POLARITY31_16_DIO28 (rw): Enables and configures edge detection polarity for DIO28.
0x400A13A0 C   FIELD 26w02 POLARITY31_16_DIO29 (rw): Enables and configures edge detection polarity for DIO29.
0x400A13A0 C   FIELD 28w02 POLARITY31_16_DIO30 (rw): Enables and configures edge detection polarity for DIO30.
0x400A13A0 C   FIELD 30w02 POLARITY31_16_DIO31 (rw): Enables and configures edge detection polarity for DIO31.
0x400A1400 B  REGISTER CTL (rw): FAST WAKE GLOBAL EN
0x400A1400 C   FIELD 00w01 CTL_FASTWAKEONLY (rw): FASTWAKEONLY for the global control of fastwake
0x400A1404 B  REGISTER FASTWAKE (rw): FAST WAKE ENABLE
0x400A1404 C   FIELD 00w01 FASTWAKE_DIN0: Enable fastwake feature for DIN0
0x400A1404 C   FIELD 01w01 FASTWAKE_DIN1: Enable fastwake feature for DIN1
0x400A1404 C   FIELD 02w01 FASTWAKE_DIN2: Enable fastwake feature for DIN2
0x400A1404 C   FIELD 03w01 FASTWAKE_DIN3: Enable fastwake feature for DIN3
0x400A1404 C   FIELD 04w01 FASTWAKE_DIN4: Enable fastwake feature for DIN4
0x400A1404 C   FIELD 05w01 FASTWAKE_DIN5: Enable fastwake feature for DIN5
0x400A1404 C   FIELD 06w01 FASTWAKE_DIN6: Enable fastwake feature for DIN6
0x400A1404 C   FIELD 07w01 FASTWAKE_DIN7: Enable fastwake feature for DIN7
0x400A1404 C   FIELD 08w01 FASTWAKE_DIN8: Enable fastwake feature for DIN8
0x400A1404 C   FIELD 09w01 FASTWAKE_DIN9: Enable fastwake feature for DIN9
0x400A1404 C   FIELD 10w01 FASTWAKE_DIN10: Enable fastwake feature for DIN10
0x400A1404 C   FIELD 11w01 FASTWAKE_DIN11: Enable fastwake feature for DIN11
0x400A1404 C   FIELD 12w01 FASTWAKE_DIN12: Enable fastwake feature for DIN12
0x400A1404 C   FIELD 13w01 FASTWAKE_DIN13: Enable fastwake feature for DIN13
0x400A1404 C   FIELD 14w01 FASTWAKE_DIN14: Enable fastwake feature for DIN14
0x400A1404 C   FIELD 15w01 FASTWAKE_DIN15: Enable fastwake feature for DIN15
0x400A1404 C   FIELD 16w01 FASTWAKE_DIN16: Enable fastwake feature for DIN16
0x400A1404 C   FIELD 17w01 FASTWAKE_DIN17: Enable fastwake feature for DIN17
0x400A1404 C   FIELD 18w01 FASTWAKE_DIN18: Enable fastwake feature for DIN18
0x400A1404 C   FIELD 19w01 FASTWAKE_DIN19: Enable fastwake feature for DIN19
0x400A1404 C   FIELD 20w01 FASTWAKE_DIN20: Enable fastwake feature for DIN20
0x400A1404 C   FIELD 21w01 FASTWAKE_DIN21: Enable fastwake feature for DIN21
0x400A1404 C   FIELD 22w01 FASTWAKE_DIN22: Enable fastwake feature for DIN22
0x400A1404 C   FIELD 23w01 FASTWAKE_DIN23: Enable fastwake feature for DIN23
0x400A1404 C   FIELD 24w01 FASTWAKE_DIN24: Enable fastwake feature for DIN24
0x400A1404 C   FIELD 25w01 FASTWAKE_DIN25: Enable fastwake feature for DIN25
0x400A1404 C   FIELD 26w01 FASTWAKE_DIN26: Enable fastwake feature for DIN26
0x400A1404 C   FIELD 27w01 FASTWAKE_DIN27: Enable fastwake feature for DIN27
0x400A1404 C   FIELD 28w01 FASTWAKE_DIN28: Enable fastwake feature for DIN29
0x400A1404 C   FIELD 29w01 FASTWAKE_DIN29: Enable fastwake feature for DIN29
0x400A1404 C   FIELD 30w01 FASTWAKE_DIN30: Enable fastwake feature for DIN30
0x400A1404 C   FIELD 31w01 FASTWAKE_DIN31: Enable fastwake feature for DIN31
0x400A1500 B  REGISTER SUB0CFG (rw): Subscriber 0 configuration
0x400A1500 C   FIELD 00w01 SUB0CFG_ENABLE (rw): This bit is used to enable subscriber 0 event.
0x400A1500 C   FIELD 08w02 SUB0CFG_OUTPOLICY (rw): These bits configure the output policy for subscriber 0 event.
0x400A1500 C   FIELD 16w04 SUB0CFG_INDEX (rw): Indicates the specific bit among lower 16 bits that is targeted by the subscriber action
0x400A1508 B  REGISTER FILTEREN15_0 (rw): Filter Enable 15 to 0
0x400A1508 C   FIELD 00w02 FILTEREN15_0_DIN0: Programmable counter length of digital glitch filter for DIN0
0x400A1508 C   FIELD 02w02 FILTEREN15_0_DIN1: Programmable counter length of digital glitch filter for DIN1
0x400A1508 C   FIELD 04w02 FILTEREN15_0_DIN2: Programmable counter length of digital glitch filter for DIN2
0x400A1508 C   FIELD 06w02 FILTEREN15_0_DIN3: Programmable counter length of digital glitch filter for DIN3
0x400A1508 C   FIELD 08w02 FILTEREN15_0_DIN4: Programmable counter length of digital glitch filter for DIN4
0x400A1508 C   FIELD 10w02 FILTEREN15_0_DIN5: Programmable counter length of digital glitch filter for DIN5
0x400A1508 C   FIELD 12w02 FILTEREN15_0_DIN6: Programmable counter length of digital glitch filter for DIN6
0x400A1508 C   FIELD 14w02 FILTEREN15_0_DIN7: Programmable counter length of digital glitch filter for DIN7
0x400A1508 C   FIELD 16w02 FILTEREN15_0_DIN8: Programmable counter length of digital glitch filter for DIN8
0x400A1508 C   FIELD 18w02 FILTEREN15_0_DIN9: Programmable counter length of digital glitch filter for DIN9
0x400A1508 C   FIELD 20w02 FILTEREN15_0_DIN10: Programmable counter length of digital glitch filter for DIN10
0x400A1508 C   FIELD 22w02 FILTEREN15_0_DIN11: Programmable counter length of digital glitch filter for DIN11
0x400A1508 C   FIELD 24w02 FILTEREN15_0_DIN12: Programmable counter length of digital glitch filter for DIN12
0x400A1508 C   FIELD 26w02 FILTEREN15_0_DIN13: Programmable counter length of digital glitch filter for DIN13
0x400A1508 C   FIELD 28w02 FILTEREN15_0_DIN14: Programmable counter length of digital glitch filter for DIN14
0x400A1508 C   FIELD 30w02 FILTEREN15_0_DIN15: Programmable counter length of digital glitch filter for DIN15
0x400A150C B  REGISTER FILTEREN31_16 (rw): Filter Enable 31 to 16
0x400A150C C   FIELD 00w02 FILTEREN31_16_DIN16: Programmable counter length of digital glitch filter for DIN16
0x400A150C C   FIELD 02w02 FILTEREN31_16_DIN17: Programmable counter length of digital glitch filter for DIN17
0x400A150C C   FIELD 04w02 FILTEREN31_16_DIN18: Programmable counter length of digital glitch filter for DIN18
0x400A150C C   FIELD 06w02 FILTEREN31_16_DIN19: Programmable counter length of digital glitch filter for DIN19
0x400A150C C   FIELD 08w02 FILTEREN31_16_DIN20: Programmable counter length of digital glitch filter for DIN20
0x400A150C C   FIELD 10w02 FILTEREN31_16_DIN21: Programmable counter length of digital glitch filter for DIN21
0x400A150C C   FIELD 12w02 FILTEREN31_16_DIN22: Programmable counter length of digital glitch filter for DIN22
0x400A150C C   FIELD 14w02 FILTEREN31_16_DIN23: Programmable counter length of digital glitch filter for DIN23
0x400A150C C   FIELD 16w02 FILTEREN31_16_DIN24: Programmable counter length of digital glitch filter for DIN24
0x400A150C C   FIELD 18w02 FILTEREN31_16_DIN25: Programmable counter length of digital glitch filter for DIN25
0x400A150C C   FIELD 20w02 FILTEREN31_16_DIN26: Programmable counter length of digital glitch filter for DIN26
0x400A150C C   FIELD 22w02 FILTEREN31_16_DIN27: Programmable counter length of digital glitch filter for DIN27
0x400A150C C   FIELD 24w02 FILTEREN31_16_DIN28: Programmable counter length of digital glitch filter for DIN28
0x400A150C C   FIELD 26w02 FILTEREN31_16_DIN29: Programmable counter length of digital glitch filter for DIN29
0x400A150C C   FIELD 28w02 FILTEREN31_16_DIN30: Programmable counter length of digital glitch filter for DIN30
0x400A150C C   FIELD 30w02 FILTEREN31_16_DIN31: Programmable counter length of digital glitch filter for DIN31
0x400A1510 B  REGISTER DMAMASK (rw): DMA Write MASK
0x400A1510 C   FIELD 00w01 DMAMASK_DOUT0: DMA is allowed to modify DOUT0
0x400A1510 C   FIELD 01w01 DMAMASK_DOUT1: DMA is allowed to modify DOUT1
0x400A1510 C   FIELD 02w01 DMAMASK_DOUT2: DMA is allowed to modify DOUT2
0x400A1510 C   FIELD 03w01 DMAMASK_DOUT3: DMA is allowed to modify DOUT3
0x400A1510 C   FIELD 04w01 DMAMASK_DOUT4: DMA is allowed to modify DOUT4
0x400A1510 C   FIELD 05w01 DMAMASK_DOUT5: DMA is allowed to modify DOUT5
0x400A1510 C   FIELD 06w01 DMAMASK_DOUT6: DMA is allowed to modify DOUT6
0x400A1510 C   FIELD 07w01 DMAMASK_DOUT7: DMA is allowed to modify DOUT7
0x400A1510 C   FIELD 08w01 DMAMASK_DOUT8: DMA is allowed to modify DOUT8
0x400A1510 C   FIELD 09w01 DMAMASK_DOUT9: DMA is allowed to modify DOUT9
0x400A1510 C   FIELD 10w01 DMAMASK_DOUT10: DMA is allowed to modify DOUT10
0x400A1510 C   FIELD 11w01 DMAMASK_DOUT11: DMA is allowed to modify DOUT11
0x400A1510 C   FIELD 12w01 DMAMASK_DOUT12: DMA is allowed to modify DOUT12
0x400A1510 C   FIELD 13w01 DMAMASK_DOUT13: DMA is allowed to modify DOUT13
0x400A1510 C   FIELD 14w01 DMAMASK_DOUT14: DMA is allowed to modify DOUT14
0x400A1510 C   FIELD 15w01 DMAMASK_DOUT15: DMA is allowed to modify DOUT15
0x400A1510 C   FIELD 16w01 DMAMASK_DOUT16: DMA is allowed to modify DOUT16
0x400A1510 C   FIELD 17w01 DMAMASK_DOUT17: DMA is allowed to modify DOUT17
0x400A1510 C   FIELD 18w01 DMAMASK_DOUT18: DMA is allowed to modify DOUT18
0x400A1510 C   FIELD 19w01 DMAMASK_DOUT19: DMA is allowed to modify DOUT19
0x400A1510 C   FIELD 20w01 DMAMASK_DOUT20: DMA is allowed to modify DOUT20
0x400A1510 C   FIELD 21w01 DMAMASK_DOUT21: DMA is allowed to modify DOUT21
0x400A1510 C   FIELD 22w01 DMAMASK_DOUT22: DMA is allowed to modify DOUT22
0x400A1510 C   FIELD 23w01 DMAMASK_DOUT23: DMA is allowed to modify DOUT23
0x400A1510 C   FIELD 24w01 DMAMASK_DOUT24: DMA is allowed to modify DOUT24
0x400A1510 C   FIELD 25w01 DMAMASK_DOUT25: DMA is allowed to modify DOUT25
0x400A1510 C   FIELD 26w01 DMAMASK_DOUT26: DMA is allowed to modify DOUT26
0x400A1510 C   FIELD 27w01 DMAMASK_DOUT27: DMA is allowed to modify DOUT27
0x400A1510 C   FIELD 28w01 DMAMASK_DOUT28: DMA is allowed to modify DOUT28
0x400A1510 C   FIELD 29w01 DMAMASK_DOUT29: DMA is allowed to modify DOUT29
0x400A1510 C   FIELD 30w01 DMAMASK_DOUT30: DMA is allowed to modify DOUT30
0x400A1510 C   FIELD 31w01 DMAMASK_DOUT31: DMA is allowed to modify DOUT31
0x400A1520 B  REGISTER SUB1CFG (rw): Subscriber 1 configuration
0x400A1520 C   FIELD 00w01 SUB1CFG_ENABLE (rw): This bit is used to enable subscriber 1 event.
0x400A1520 C   FIELD 08w02 SUB1CFG_OUTPOLICY (rw): These bits configure the output policy for subscriber 1 event.
0x400A1520 C   FIELD 16w04 SUB1CFG_INDEX (rw): indicates the specific bit in the upper 16 bits that is targeted by the subscriber action
0x400AF000 A PERIPHERAL SYSCTL
0x400B0020 B  REGISTER IIDX (ro): SYSCTL interrupt index
0x400B0020 C   FIELD 00w02 IIDX_STAT (ro): The SYSCTL interrupt index (IIDX) register generates a value corresponding to the highest priority pending interrupt source. This value may be used as an address offset for fast, deterministic handling in the interrupt service routine. A read of the IIDX register will clear the corresponding interrupt status in the RIS and MIS registers.
0x400B0028 B  REGISTER IMASK (rw): SYSCTL interrupt mask
0x400B0028 C   FIELD 00w01 IMASK_LFOSCGOOD (rw): Enable or disable the LFOSCGOOD interrupt. LFOSCGOOD indicates that the LFOSC has started successfully.
0x400B0028 C   FIELD 01w01 IMASK_ANACLKERR (rw): Analog Clocking Consistency Error
0x400B0030 B  REGISTER RIS (ro): SYSCTL raw interrupt status
0x400B0030 C   FIELD 00w01 RIS_LFOSCGOOD (ro): Raw status of the LFOSCGOOD interrupt.
0x400B0030 C   FIELD 01w01 RIS_ANACLKERR (ro): Analog Clocking Consistency Error
0x400B0038 B  REGISTER MIS (ro): SYSCTL masked interrupt status
0x400B0038 C   FIELD 00w01 MIS_LFOSCGOOD (ro): Masked status of the LFOSCGOOD interrupt.
0x400B0038 C   FIELD 01w01 MIS_ANACLKERR (ro): Analog Clocking Consistency Error
0x400B0040 B  REGISTER ISET (wo): SYSCTL interrupt set
0x400B0040 C   FIELD 00w01 ISET_LFOSCGOOD (wo): Set the LFOSCGOOD interrupt.
0x400B0040 C   FIELD 01w01 ISET_ANACLKERR (wo): Analog Clocking Consistency Error
0x400B0048 B  REGISTER ICLR (wo): SYSCTL interrupt clear
0x400B0048 C   FIELD 00w01 ICLR_LFOSCGOOD (wo): Clear the LFOSCGOOD interrupt.
0x400B0048 C   FIELD 01w01 ICLR_ANACLKERR (wo): Analog Clocking Consistency Error
0x400B0050 B  REGISTER NMIIIDX (ro): NMI interrupt index
0x400B0050 C   FIELD 00w02 NMIIIDX_STAT (ro): The NMI interrupt index (NMIIIDX) register generates a value corresponding to the highest priority pending NMI source. This value may be used as an address offset for fast, deterministic handling in the NMI service routine. A read of the NMIIIDX register will clear the corresponding interrupt status in the NMIRIS register.
0x400B0060 B  REGISTER NMIRIS (ro): NMI raw interrupt status
0x400B0060 C   FIELD 00w01 NMIRIS_BORLVL (ro): Raw status of the BORLVL NMI
0x400B0060 C   FIELD 01w01 NMIRIS_WWDT0 (ro): Watch Dog 0 Fault
0x400B0070 B  REGISTER NMIISET (wo): NMI interrupt set
0x400B0070 C   FIELD 00w01 NMIISET_BORLVL (wo): Set the BORLVL NMI
0x400B0070 C   FIELD 01w01 NMIISET_WWDT0 (wo): Watch Dog 0 Fault
0x400B0078 B  REGISTER NMIICLR (wo): NMI interrupt clear
0x400B0078 C   FIELD 00w01 NMIICLR_BORLVL (wo): Clr the BORLVL NMI
0x400B0078 C   FIELD 01w01 NMIICLR_WWDT0 (wo): Watch Dog 0 Fault
0x400B0100 B  REGISTER SYSOSCCFG (rw): SYSOSC configuration
0x400B0100 C   FIELD 00w02 SYSOSCCFG_FREQ (rw): Target operating frequency for the system oscillator (SYSOSC)
0x400B0100 C   FIELD 08w01 SYSOSCCFG_USE4MHZSTOP (rw): USE4MHZSTOP sets the SYSOSC stop mode frequency policy. When entering STOP mode, the SYSOSC frequency may be automatically switched to 4MHz to reduce SYSOSC power consumption.
0x400B0100 C   FIELD 09w01 SYSOSCCFG_DISABLESTOP (rw): DISABLESTOP sets the SYSOSC stop mode enable/disable policy. When operating in STOP mode, the SYSOSC may be automatically disabled. When set, ULPCLK will run from LFCLK in STOP mode and SYSOSC will be disabled to reduce power consumption.
0x400B0100 C   FIELD 10w01 SYSOSCCFG_DISABLE (rw): DISABLE sets the SYSOSC enable/disable policy. SYSOSC may be powered off in RUN, SLEEP, and STOP modes to reduce power consumption. When SYSOSC is disabled, MCLK and ULPCLK are sourced from LFCLK.
0x400B0100 C   FIELD 16w01 SYSOSCCFG_BLOCKASYNCALL (rw): BLOCKASYNCALL may be used to mask block all asynchronous fast clock requests, preventing hardware from dynamically changing the active clock configuration when operating in a given mode.
0x400B0100 C   FIELD 17w01 SYSOSCCFG_FASTCPUEVENT (rw): FASTCPUEVENT may be used to assert a fast clock request when an interrupt is asserted to the CPU, reducing interrupt latency.
0x400B013C B  REGISTER GENCLKEN (rw): General clock enable control
0x400B013C C   FIELD 00w01 GENCLKEN_EXCLKEN (rw): EXCLKEN enables the CLK_OUT external clock output block.
0x400B013C C   FIELD 04w01 GENCLKEN_MFPCLKEN (rw): MFPCLKEN enables the middle frequency precision clock (MFPCLK).
0x400B0140 B  REGISTER PMODECFG (rw): Power mode configuration
0x400B0140 C   FIELD 00w02 PMODECFG_DSLEEP (rw): DSLEEP selects the operating mode to enter upon a DEEPSLEEP request from the CPU.
0x400B0140 C   FIELD 05w01 PMODECFG_SYSSRAMONSTOP (rw): SYSSRAMONSTOP selects whether the SRAM controller is enabled or disabled in STOP mode.
0x400B0150 B  REGISTER FCC (ro): Frequency clock counter (FCC) count
0x400B0150 C   FIELD 00w22 FCC_DATA (ro): Frequency clock counter (FCC) count value.
0x400B0170 B  REGISTER SYSOSCTRIMUSER (rw): SYSOSC user-specified trim
0x400B0170 C   FIELD 00w02 SYSOSCTRIMUSER_FREQ (rw): FREQ specifies the target user-trimmed frequency for SYSOSC.
0x400B0170 C   FIELD 04w03 SYSOSCTRIMUSER_CAP (rw): CAP specifies the SYSOSC capacitor trim. This value changes with the target frequency.
0x400B0170 C   FIELD 08w06 SYSOSCTRIMUSER_RESCOARSE (rw): RESCOARSE specifies the resister coarse trim. This value changes with the target frequency.
0x400B0170 C   FIELD 16w04 SYSOSCTRIMUSER_RESFINE (rw): RESFINE specifies the resister fine trim. This value changes with the target frequency.
0x400B0170 C   FIELD 20w09 SYSOSCTRIMUSER_RDIV (rw): RDIV specifies the frequency correction loop (FCL) resistor trim. This value changes with the target frequency.
0x400B0178 B  REGISTER SRAMBOUNDARY (rw): SRAM Write Boundary
0x400B0178 C   FIELD 05w15 SRAMBOUNDARY_ADDR (rw): SRAM boundary configuration. The value configured into this acts such that: SRAM accesses to addresses less than or equal value will be RW only. SRAM accesses to addresses greater than value will be RX only. Value of 0 is not valid (system will have no stack). If set to 0, the system acts as if the entire SRAM is RWX. Any non-zero value can be configured, including a value = SRAM size.
0x400B0180 B  REGISTER SYSTEMCFG (rw): System configuration
0x400B0180 C   FIELD 00w01 SYSTEMCFG_WWDTLP0RSTDIS (rw): WWDTLP0RSTDIS specifies whether a WWDT Error Event will trigger a BOOTRST or an NMI.
0x400B0180 C   FIELD 24w08 SYSTEMCFG_KEY (wo): The key value of 1Bh (27) must be written to KEY together with contents to be updated. Reads as 0
0x400B0200 B  REGISTER WRITELOCK (rw): SYSCTL register write lockout
0x400B0200 C   FIELD 00w01 WRITELOCK_ACTIVE (rw): ACTIVE controls whether critical SYSCTL registers are write protected or not.
0x400B0220 B  REGISTER RSTCAUSE (ro): Reset cause
0x400B0220 C   FIELD 00w05 RSTCAUSE_ID (ro): ID is a read-to-clear field which indicates the lowest level reset cause since the last read.
0x400B0300 B  REGISTER RESETLEVEL (rw): Reset level for application-triggered reset command
0x400B0300 C   FIELD 00w03 RESETLEVEL_LEVEL (rw): LEVEL is used to specify the type of reset to be issued when RESETCMD is set to generate a software triggered reset.
0x400B0304 B  REGISTER RESETCMD (wo): Execute an application-triggered reset command
0x400B0304 C   FIELD 00w01 RESETCMD_GO (wo): Execute the reset specified in RESETLEVEL.LEVEL. Must be written together with the KEY.
0x400B0304 C   FIELD 24w08 RESETCMD_KEY (wo): The key value of E4h (228) must be written to KEY together with GO to trigger the reset.
0x400B0308 B  REGISTER BORTHRESHOLD (rw): BOR threshold selection
0x400B0308 C   FIELD 00w02 BORTHRESHOLD_LEVEL (rw): LEVEL specifies the desired BOR threshold and BOR mode.
0x400B030C B  REGISTER BORCLRCMD (wo): Set the BOR threshold
0x400B030C C   FIELD 00w01 BORCLRCMD_GO (wo): GO clears any prior BOR violation status indications and attempts to change the active BOR mode to that specified in the LEVEL field of the BORTHRESHOLD register.
0x400B030C C   FIELD 24w08 BORCLRCMD_KEY (wo): The key value of C7h (199) must be written to KEY together with GO to trigger the clear and BOR threshold change.
0x400B0310 B  REGISTER SYSOSCFCLCTL (wo): SYSOSC frequency correction loop (FCL) ROSC enable
0x400B0310 C   FIELD 00w01 SYSOSCFCLCTL_SETUSEFCL (wo): Set SETUSEFCL to enable the frequency correction loop in SYSOSC. Once enabled, this state is locked until the next BOOTRST.
0x400B0310 C   FIELD 24w08 SYSOSCFCLCTL_KEY (wo): The key value of 2Ah (42) must be written to KEY together with SETUSEFCL to enable the FCL.
0x400B031C B  REGISTER SHDNIOREL (wo): SHUTDOWN IO release control
0x400B031C C   FIELD 00w01 SHDNIOREL_RELEASE (wo): Set RELEASE to release the IO after a SHUTDOWN mode exit.
0x400B031C C   FIELD 24w08 SHDNIOREL_KEY (wo): The key value 91h must be written to KEY together with RELEASE to set RELEASE.
0x400B0320 B  REGISTER EXRSTPIN (wo): Disable the reset function of the NRST pin
0x400B0320 C   FIELD 00w01 EXRSTPIN_DISABLE (wo): Set DISABLE to disable the reset function of the NRST pin. Once set, this configuration is locked until the next POR.
0x400B0320 C   FIELD 24w08 EXRSTPIN_KEY (wo): The key value 1Eh must be written together with DISABLE to disable the reset function.
0x400B0328 B  REGISTER SWDCFG (wo): Disable the SWD function on the SWD pins
0x400B0328 C   FIELD 00w01 SWDCFG_DISABLE (wo): Set DISABLE to disable the SWD function on SWD pins, allowing the SWD pins to be used as GPIO.
0x400B0328 C   FIELD 24w08 SWDCFG_KEY (wo): The key value 62h (98) must be written to KEY together with DISBALE to disable the SWD functions.
0x400B032C B  REGISTER FCCCMD (wo): Frequency clock counter start capture
0x400B032C C   FIELD 00w01 FCCCMD_GO (wo): Set GO to start a capture with the frequency clock counter (FCC).
0x400B032C C   FIELD 24w08 FCCCMD_KEY (wo): The key value 0Eh (14) must be written with GO to start a capture.
0x400B0380 B  REGISTER PMUOPAMP (rw): GPAMP control
0x400B0380 C   FIELD 00w01 PMUOPAMP_ENABLE (rw): Set ENABLE to turn on the GPAMP.
0x400B0380 C   FIELD 01w01 PMUOPAMP_PCHENABLE (rw): Set PCHENABLE to enable the positive channel input.
0x400B0380 C   FIELD 02w02 PMUOPAMP_NSEL (rw): NSEL selects the GPAMP negative channel input.
0x400B0380 C   FIELD 04w02 PMUOPAMP_RRI (rw): RRI selects the rail-to-rail input mode.
0x400B0380 C   FIELD 06w01 PMUOPAMP_OUTENABLE (rw): Set OUTENABLE to connect the GPAMP output signal to the GPAMP_OUT pin
0x400B0380 C   FIELD 08w02 PMUOPAMP_CHOPCLKFREQ (rw): CHOPCLKFREQ selects the GPAMP chopping clock frequency
0x400B0380 C   FIELD 10w02 PMUOPAMP_CHOPCLKMODE (rw): CHOPCLKMODE selects the GPAMP chopping mode.
0x400B0400 B  REGISTER SHUTDNSTORE0 (rw): Shutdown storage memory (byte 0)
0x400B0400 C   FIELD 00w08 SHUTDNSTORE0_DATA (rw): Shutdown storage byte 0
0x400B0404 B  REGISTER SHUTDNSTORE1 (rw): Shutdown storage memory (byte 1)
0x400B0404 C   FIELD 00w08 SHUTDNSTORE1_DATA (rw): Shutdown storage byte 1
0x400B0408 B  REGISTER SHUTDNSTORE2 (rw): Shutdown storage memory (byte 2)
0x400B0408 C   FIELD 00w08 SHUTDNSTORE2_DATA (rw): Shutdown storage byte 2
0x400B040C B  REGISTER SHUTDNSTORE3 (rw): Shutdown storage memory (byte 3)
0x400B040C C   FIELD 00w08 SHUTDNSTORE3_DATA (rw): Shutdown storage byte 3
0x400C7000 A PERIPHERAL DEBUGSS
0x400C8020 B  REGISTER IIDX (ro): Interrupt index
0x400C8020 C   FIELD 00w08 IIDX_STAT: Interrupt index status
0x400C8028 B  REGISTER IMASK (rw): Interrupt mask
0x400C8028 C   FIELD 00w01 IMASK_TXIFG: Masks TXIFG in MIS register
0x400C8028 C   FIELD 01w01 IMASK_RXIFG: Masks RXIFG in MIS register
0x400C8028 C   FIELD 02w01 IMASK_PWRUPIFG: Masks PWRUPIFG in MIS register
0x400C8028 C   FIELD 03w01 IMASK_PWRDWNIFG: Masks PWRDWNIFG in MIS register
0x400C8030 B  REGISTER RIS (ro): Raw interrupt status
0x400C8030 C   FIELD 00w01 RIS_TXIFG: Raw interrupt status for TXIFG
0x400C8030 C   FIELD 01w01 RIS_RXIFG: Raw interrupt status for RXIFG
0x400C8030 C   FIELD 02w01 RIS_PWRUPIFG: Raw interrupt status for PWRUPIFG
0x400C8030 C   FIELD 03w01 RIS_PWRDWNIFG: Raw interrupt status for PWRDWNIFG
0x400C8038 B  REGISTER MIS (ro): Masked interrupt status
0x400C8038 C   FIELD 00w01 MIS_TXIFG: Masked interrupt status for TXIFG
0x400C8038 C   FIELD 01w01 MIS_RXIFG: Masked interrupt status for RXIFG
0x400C8038 C   FIELD 02w01 MIS_PWRUPIFG: Masked interrupt status for PWRUPIFG
0x400C8038 C   FIELD 03w01 MIS_PWRDWNIFG: Masked interrupt status for PWRDWNIFG
0x400C8040 B  REGISTER ISET (wo): Interrupt set
0x400C8040 C   FIELD 00w01 ISET_TXIFG: Sets TXIFG in RIS register
0x400C8040 C   FIELD 01w01 ISET_RXIFG: Sets RXIFG in RIS register
0x400C8040 C   FIELD 02w01 ISET_PWRUPIFG: Sets PWRUPIFG in RIS register
0x400C8040 C   FIELD 03w01 ISET_PWRDWNIFG: Sets PWRDWNIFG in RIS register
0x400C8048 B  REGISTER ICLR (wo): Interrupt clear
0x400C8048 C   FIELD 00w01 ICLR_TXIFG: Clears TXIFG in RIS register
0x400C8048 C   FIELD 01w01 ICLR_RXIFG: Clears RXIFG in RIS register
0x400C8048 C   FIELD 02w01 ICLR_PWRUPIFG: Clears PWRUPIFG in RIS register
0x400C8048 C   FIELD 03w01 ICLR_PWRDWNIFG: Clears PWRDWNIFG in RIS register
0x400C80E0 B  REGISTER EVT_MODE (ro): Event Mode
0x400C80E0 C   FIELD 00w02 EVT_MODE_INT0_CFG (ro): Event line mode select for peripheral events
0x400C80FC B  REGISTER DESC (ro): Module Description
0x400C80FC C   FIELD 00w04 DESC_MINREV: Minor rev of the IP
0x400C80FC C   FIELD 04w04 DESC_MAJREV: Major rev of the IP
0x400C80FC C   FIELD 08w04 DESC_INSTNUM: Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances
0x400C80FC C   FIELD 12w04 DESC_FEATUREVER: Feature Set for the module *instance*
0x400C80FC C   FIELD 16w16 DESC_MODULEID: Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness.
0x400C8100 B  REGISTER TXD (ro): Transmit data register
0x400C8100 C   FIELD 00w32 TXD_TX_DATA (ro): Contains data written by an external debug tool to the SEC-AP TXDATA register
0x400C8104 B  REGISTER TXCTL (ro): Transmit control register
0x400C8104 C   FIELD 00w01 TXCTL_TRANSMIT (ro): Indicates data request in DSSM.TXD, set on write via Debug AP to DSSM.TXD. A read of the DSSM.TXD register by SW will clear the TX field. The tool can check that TXD is empty by reading this field.
0x400C8104 C   FIELD 01w31 TXCTL_TRANSMIT_FLAGS (ro): Generic TX flags that can be set by external debug tool. Functionality is defined by SW.
0x400C8108 B  REGISTER RXD (rw): Receive data register
0x400C8108 C   FIELD 00w32 RXD_RX_DATA (rw): Contains data written by SM/OW.
0x400C810C B  REGISTER RXCTL (rw): Receive control register
0x400C810C C   FIELD 00w01 RXCTL_RECEIVE (ro): Indicates SW write to the DSSM.RXD register. A read of the DSSM.RXD register by SWD Access Port will clear the RX field.
0x400C810C C   FIELD 01w07 RXCTL_RECEIVE_FLAGS (rw): Generic RX flags that can be set by SW and read by external debug tool. Functionality is defined by SW.
0x400C8200 B  REGISTER SPECIAL_AUTH (ro): Special enable authorization register
0x400C8200 C   FIELD 00w01 SPECIAL_AUTH_SECAPEN (ro): An active high input. When asserted (and SWD access is also permitted), the debug tools can use the Security-AP to communicate with security control logic. When deasserted, a DAPBUS firewall will isolate the AP and prevent access to the Security-AP.
0x400C8200 C   FIELD 01w01 SPECIAL_AUTH_SWDPORTEN (ro): When asserted, the SW-DP functions normally. When deasserted, the SW-DP effectively disables all external debug access.
0x400C8200 C   FIELD 02w01 SPECIAL_AUTH_DFTAPEN (ro): An active high input. When asserted (and SWD access is also permitted), the debug tools can then access the DFT-AP external to the DebugSS lite. When deasserted, a DAPBUS firewall will isolate the AP and prevent access.
0x400C8200 C   FIELD 03w01 SPECIAL_AUTH_ETAPEN (ro): An active high input. When asserted (and SWD access is also permitted), the debug tools can then access an ET-AP external to the DebugSS lite. When deasserted, a DAPBUS firewall will isolate the AP and prevent access.
0x400C8200 C   FIELD 04w01 SPECIAL_AUTH_CFGAPEN (ro): An active high input. When asserted (and SWD access is also permitted), the debug tools can use the Config-AP to read device configuration information. When deasserted, a DAPBUS firewall will isolate the AP and prevent access to the Config-AP.
0x400C8200 C   FIELD 05w01 SPECIAL_AUTH_AHBAPEN (ro): Disabling / enabling debug access to the M0+ Core via the AHB-AP DAP bus isolation.
0x400C8200 C   FIELD 06w01 SPECIAL_AUTH_PWRAPEN (ro): An active high input. When asserted (and SWD access is also permitted), the debug tools can then access the PWR-AP to power and reset state of the CPU. When deasserted, a DAPBUS firewall will isolate the AP and prevent access.
0x400C8210 B  REGISTER APP_AUTH (ro): Application CPU0 authorization register
0x400C8210 C   FIELD 00w01 APP_AUTH_DBGEN (ro): Controls invasive debug enable.
0x400C8210 C   FIELD 01w01 APP_AUTH_NIDEN (ro): Controls non-invasive debug enable.
0x400C8210 C   FIELD 02w01 APP_AUTH_SPIDEN (ro): Secure invasive debug enable.
0x400C8210 C   FIELD 03w01 APP_AUTH_SPNIDEN (ro): Secure non-invasive debug enable.
0x400CD000 A PERIPHERAL FLASHCTL
0x400CE020 B  REGISTER IIDX (ro): Interrupt Index Register
0x400CE020 C   FIELD 00w01 IIDX_STAT (ro): Indicates which interrupt has fired. 0x0 means no event pending. The priority order is fixed. On each read, only one interrupt is indicated. On a read, the current interrupt (highest priority) is automatically cleared by the hardware and the corresponding interrupt flags in the RIS and MIS are cleared as well. After a read from the CPU (not from the debug interface), the register must be updated with the next highest priority interrupt.
0x400CE028 B  REGISTER IMASK (rw): Interrupt Mask Register
0x400CE028 C   FIELD 00w01 IMASK_DONE (rw): Interrupt mask for DONE: 0: Interrupt is disabled in MIS register 1: Interrupt is enabled in MIS register
0x400CE030 B  REGISTER RIS (ro): Raw Interrupt Status Register
0x400CE030 C   FIELD 00w01 RIS_DONE (ro): NoWrapper operation completed. This interrupt bit is set by firmware or the corresponding bit in the ISET register. It is cleared by the corresponding bit in in the ICLR register or reading the IIDX register when this interrupt is the highest priority.
0x400CE038 B  REGISTER MIS (ro): Masked Interrupt Status Register
0x400CE038 C   FIELD 00w01 MIS_DONE (ro): NoWrapper operation completed. This masked interrupt bit reflects the bitwise AND of the corresponding RIS and IMASK bits.
0x400CE040 B  REGISTER ISET (wo): Interrupt Set Register
0x400CE040 C   FIELD 00w01 ISET_DONE (wo): 0: No effect 1: Set the DONE interrupt in the RIS register
0x400CE048 B  REGISTER ICLR (wo): Interrupt Clear Register
0x400CE048 C   FIELD 00w01 ICLR_DONE (wo): 0: No effect 1: Clear the DONE interrupt in the RIS register
0x400CE0E0 B  REGISTER EVT_MODE (ro): Event Mode
0x400CE0E0 C   FIELD 00w02 EVT_MODE_INT0_CFG (ro): Event line mode select for peripheral event
0x400CE0FC B  REGISTER DESC (ro): Hardware Version Description Register
0x400CE0FC C   FIELD 00w04 DESC_MINREV (ro): Minor Revision
0x400CE0FC C   FIELD 04w04 DESC_MAJREV (ro): Major Revision
0x400CE0FC C   FIELD 08w04 DESC_INSTNUM (ro): Instance number
0x400CE0FC C   FIELD 12w04 DESC_FEATUREVER (ro): Feature set
0x400CE0FC C   FIELD 16w16 DESC_MODULEID (ro): Module ID
0x400CE100 B  REGISTER CMDEXEC (rw): Command Execute Register
0x400CE100 C   FIELD 00w01 CMDEXEC_VAL (rw): Command Execute value Initiates execution of the command specified in the CMDTYPE register.
0x400CE104 B  REGISTER CMDTYPE (rw): Command Type Register
0x400CE104 C   FIELD 00w03 CMDTYPE_COMMAND (rw): Command type
0x400CE104 C   FIELD 04w03 CMDTYPE_SIZE (rw): Command size
0x400CE108 B  REGISTER CMDCTL (rw): Command Control Register
0x400CE108 C   FIELD 00w04 CMDCTL_MODESEL (rw): Mode This field is only used for the Mode Change command type. Otherwise, bank and pump modes are set automaticlly via the NW hardware.
0x400CE108 C   FIELD 09w04 CMDCTL_REGIONSEL (rw): Bank Region A specific region ID can be written to this field to indicate to which region an operation should be applied if CMDCTL.ADDRXLATEOVR is set.
0x400CE108 C   FIELD 16w01 CMDCTL_ADDRXLATEOVR (rw): Override hardware address translation of address in CMDADDR from a system address to a bank address and bank ID. Use data written to CMDADDR directly as the bank address. Use the value written to CMDCTL.BANKSEL directly as the bank ID. Use the value written to CMDCTL.REGIONSEL directly as the region ID.
0x400CE108 C   FIELD 20w01 CMDCTL_SSERASEDIS (rw): Disable Stair-Step Erase. If set, the default VHV trim voltage setting will be used for all erase pulses. By default, this bit is reset, meaning that the VHV voltage will be stepped during successive erase pulses. The step count, step voltage, begin and end voltages are all hard-wired.
0x400CE108 C   FIELD 21w01 CMDCTL_DATAVEREN (rw): Enable invalid data verify. This checks for 0->1 transitions in the memory when a program operation is initiated. If such a transition is found, the program will fail with an error without doing any programming.
0x400CE120 B  REGISTER CMDADDR (rw): Command Address Register
0x400CE120 C   FIELD 00w32 CMDADDR_VAL (rw): Address value
0x400CE124 B  REGISTER CMDBYTEN (rw): Command Program Byte Enable Register
0x400CE124 C   FIELD 00w08 CMDBYTEN_VAL (rw): Command Byte Enable value. A 1-bit per flash word byte value is placed in this register.
0x400CE130 B  REGISTER CMDDATA0 (rw): Command Data Register 0
0x400CE130 C   FIELD 00w32 CMDDATA0_VAL (rw): A 32-bit data value is placed in this field.
0x400CE134 B  REGISTER CMDDATA1 (rw): Command Data Register 1
0x400CE134 C   FIELD 00w32 CMDDATA1_VAL (rw): A 32-bit data value is placed in this field.
0x400CE1D0 B  REGISTER CMDWEPROTA (rw): Command Write Erase Protect A Register
0x400CE1D0 C   FIELD 00w32 CMDWEPROTA_VAL (rw): Each bit protects 1 sector. bit [0]: When 1, sector 0 of the flash memory will be protected from program and erase. bit [1]: When 1, sector 1 of the flash memory will be protected from program and erase. : : bit [31]: When 1, sector 31 of the flash memory will be protected from program and erase.
0x400CE1D4 B  REGISTER CMDWEPROTB (rw): Command Write Erase Protect B Register
0x400CE1D4 C   FIELD 00w04 CMDWEPROTB_VAL (rw): Each bit protects a group of 8 sectors. When a bit is 1, the associated 8 sectors in the flash will be protected from program and erase. A maximum of 256 sectors can be protected with this register.
0x400CE1D8 B  REGISTER CMDWEPROTC (rw): Command Write Erase Protect C Register
0x400CE1D8 C   FIELD 00w00 CMDWEPROTC_VAL (rw): Each bit protects a group of 8 sectors. When a bit is 1, the associated 8 sectors in the flash will be protected from program and erase. Note that the sectors protected with this register start at sector 256 in the flash, where the sectors protected by the CMDWEPROTB register end.
0x400CE210 B  REGISTER CMDWEPROTNM (rw): Command Write Erase Protect Non-Main Register
0x400CE210 C   FIELD 00w01 CMDWEPROTNM_VAL (rw): Each bit protects 1 sector. bit [0]: When 1, sector 0 of the non-main region will be protected from program and erase. bit [1]: When 1, sector 1 of the non-main region will be protected from program and erase. : : bit [31]: When 1, sector 31 of the non-main will be protected from program and erase.
0x400CE214 B  REGISTER CMDWEPROTTR (rw): Command Write Erase Protect Trim Register
0x400CE214 C   FIELD 00w01 CMDWEPROTTR_VAL (rw): Each bit protects 1 sector. bit [0]: When 1, sector 0 of the engr region will be protected from program and erase. bit [1]: When 1, sector 1 of the engr region will be protected from program and erase. : : bit [31]: When 1, sector 31 of the engr region will be protected from program and erase.
0x400CE218 B  REGISTER CMDWEPROTEN (rw): Command Write Erase Protect Engr Register
0x400CE218 C   FIELD 00w02 CMDWEPROTEN_VAL (rw): Each bit protects 1 sector. bit [0]: When 1, sector 0 of the engr region will be protected from program and erase. bit [1]: When 1, sector 1 of the engr region will be protected from program and erase. : : bit [31]: When 1, sector 31 of the engr region will be protected from program and erase.
0x400CE3B0 B  REGISTER CFGCMD (rw): Command Configuration Register
0x400CE3B0 C   FIELD 00w04 CFGCMD_WAITSTATE (rw): Wait State setting for program verify, erase verify and read verify
0x400CE3B4 B  REGISTER CFGPCNT (rw): Pulse Counter Configuration Register
0x400CE3B4 C   FIELD 00w01 CFGPCNT_MAXPCNTOVR (rw): Override hard-wired maximum pulse count. If MAXERSPCNTOVR is not set, then setting this value alone will override the max pulse count for both program and erase. If MAXERSPCNTOVR is set, then this bit will only control the max pulse count setting for program. By default, this bit is 0, and a hard-wired max pulse count is used.
0x400CE3B4 C   FIELD 04w08 CFGPCNT_MAXPCNTVAL (rw): Override maximum pulse counter with this value. If MAXPCNTOVR = 0, then this field is ignored. If MAXPCNTOVR = 1 and MAXERSPCNTOVR = 0, then this value will be used to override the max pulse count for both program and erase. Full max value will be {4'h0, MAXPCNTVAL} . If MAXPCNTOVR = 1 and MAXERSPCNTOVR = 1, then this value will be used to override the max pulse count for program only. Full max value will be {4'h0, MAXPCNTVAL}.
0x400CE3D0 B  REGISTER STATCMD (ro): Command Status Register
0x400CE3D0 C   FIELD 00w01 STATCMD_CMDDONE (ro): Command Done
0x400CE3D0 C   FIELD 01w01 STATCMD_CMDPASS (ro): Command Pass - valid when CMD_DONE field is 1
0x400CE3D0 C   FIELD 02w01 STATCMD_CMDINPROGRESS (ro): Command In Progress
0x400CE3D0 C   FIELD 04w01 STATCMD_FAILWEPROT (ro): Command failed due to Write/Erase Protect Sector Violation
0x400CE3D0 C   FIELD 05w01 STATCMD_FAILVERIFY (ro): Command failed due to verify error
0x400CE3D0 C   FIELD 06w01 STATCMD_FAILILLADDR (ro): Command failed due to the use of an illegal address
0x400CE3D0 C   FIELD 07w01 STATCMD_FAILMODE (ro): Command failed because a bank has been set to a mode other than READ. Program and Erase commands cannot be initiated unless all banks are in READ mode.
0x400CE3D0 C   FIELD 08w01 STATCMD_FAILINVDATA (ro): Program command failed because an attempt was made to program a stored 0 value to a 1.
0x400CE3D0 C   FIELD 12w01 STATCMD_FAILMISC (ro): Command failed due to error other than write/erase protect violation or verify error. This is an extra bit in case a new failure mechanism is added which requires a status bit.
0x400CE3D4 B  REGISTER STATADDR (ro): Address Status Register
0x400CE3D4 C   FIELD 00w16 STATADDR_BANKADDR (ro): Current Bank Address A bank offset address is stored in this register.
0x400CE3D4 C   FIELD 16w05 STATADDR_REGIONID (ro): Current Region ID A region indicator is stored in this register which represents the current flash region on which the state machine is operating.
0x400CE3D4 C   FIELD 21w05 STATADDR_BANKID (ro): Current Bank ID A bank indicator is stored in this register which represents the current bank on which the state machine is operating. There is 1 bit per bank.
0x400CE3D8 B  REGISTER STATPCNT (ro): Pulse Count Status Register
0x400CE3D8 C   FIELD 00w12 STATPCNT_PULSECNT (ro): Current Pulse Counter Value
0x400CE3DC B  REGISTER STATMODE (ro): Mode Status Register
0x400CE3DC C   FIELD 00w01 STATMODE_BANKNOTINRD (ro): Bank not in read mode. Indicates which banks are not in READ mode. There is 1 bit per bank.
0x400CE3DC C   FIELD 08w04 STATMODE_BANKMODE (ro): Indicates mode of bank(s) that are not in READ mode
0x400CE3DC C   FIELD 16w01 STATMODE_BANK2TRDY (ro): Bank 2T Ready. Bank(s) are ready for 2T access. This is accomplished when the pump has fully driven power rails to the bank(s).
0x400CE3DC C   FIELD 17w01 STATMODE_BANK1TRDY (ro): Bank 1T Ready. Bank(s) are ready for 1T access. This is accomplished when the bank and pump have been trimmed.
0x400CE3F0 B  REGISTER GBLINFO0 (ro): Global Information Register 0
0x400CE3F0 C   FIELD 00w16 GBLINFO0_SECTORSIZE (ro): Sector size in bytes
0x400CE3F0 C   FIELD 16w03 GBLINFO0_NUMBANKS (ro): Number of banks instantiated Minimum: 1 Maximum: 5
0x400CE3F4 B  REGISTER GBLINFO1 (ro): Global Information Register 1
0x400CE3F4 C   FIELD 00w08 GBLINFO1_DATAWIDTH (ro): Data width in bits
0x400CE3F4 C   FIELD 08w05 GBLINFO1_ECCWIDTH (ro): ECC data width in bits
0x400CE3F4 C   FIELD 16w03 GBLINFO1_REDWIDTH (ro): Redundant data width in bits
0x400CE3F8 B  REGISTER GBLINFO2 (ro): Global Information Register 2
0x400CE3F8 C   FIELD 00w04 GBLINFO2_DATAREGISTERS (ro): Number of data registers present.
0x400CE400 B  REGISTER BANK0INFO0 (ro): Bank Information Register 0 for Bank 0
0x400CE400 C   FIELD 00w12 BANK0INFO0_MAINSIZE (ro): Main region size in sectors Minimum: 0x8 (8) Maximum: 0x200 (512)
0x400CE404 B  REGISTER BANK0INFO1 (ro): Bank Information Register 1 for Bank 0
0x400CE404 C   FIELD 00w08 BANK0INFO1_NONMAINSIZE (ro): Non-main region size in sectors Minimum: 0x0 (0) Maximum: 0x10 (16)
0x400CE404 C   FIELD 08w08 BANK0INFO1_TRIMSIZE (ro): Trim region size in sectors Minimum: 0x0 (0) Maximum: 0x10 (16)
0x400CE404 C   FIELD 16w08 BANK0INFO1_ENGRSIZE (ro): Engr region size in sectors Minimum: 0x0 (0) Maximum: 0x10 (16)
0x400F0000 A PERIPHERAL I2C0
0x400F0800 B  REGISTER PWREN (rw): Power enable
0x400F0800 C   FIELD 00w01 PWREN_ENABLE (rw): Enable the power
0x400F0800 C   FIELD 24w08 PWREN_KEY (wo): KEY to allow Power State Change
0x400F0804 B  REGISTER RSTCTL (wo): Reset Control
0x400F0804 C   FIELD 00w01 RSTCTL_RESETASSERT (wo): Assert reset to the peripheral
0x400F0804 C   FIELD 01w01 RSTCTL_RESETSTKYCLR (wo): Clear the RESETSTKY bit in the STAT register
0x400F0804 C   FIELD 24w08 RSTCTL_KEY (wo): Unlock key
0x400F0808 B  REGISTER CLKCFG (rw): Peripheral Clock Configuration Register
0x400F0808 C   FIELD 08w01 CLKCFG_BLOCKASYNC (rw): Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz
0x400F0808 C   FIELD 24w08 CLKCFG_KEY (wo): KEY to Allow State Change -- 0xA9
0x400F0814 B  REGISTER STAT (ro): Status Register
0x400F0814 C   FIELD 16w01 STAT_RESETSTKY (ro): This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register
0x400F1000 B  REGISTER CLKDIV (rw): Clock Divider
0x400F1000 C   FIELD 00w03 CLKDIV_RATIO: Selects divide ratio of module clock
0x400F1004 B  REGISTER CLKSEL (rw): Clock Select for Ultra Low Power peripherals
0x400F1004 C   FIELD 02w01 CLKSEL_MFCLK_SEL (rw): Selects MFCLK as clock source if enabled
0x400F1004 C   FIELD 03w01 CLKSEL_BUSCLK_SEL (rw): Selects BUSCLK as clock source if enabled
0x400F1018 B  REGISTER PDBGCTL (rw): Peripheral Debug Control
0x400F1018 C   FIELD 00w01 PDBGCTL_FREE (rw): Free run control
0x400F1018 C   FIELD 01w01 PDBGCTL_SOFT (rw): Soft halt boundary control. This function is only available, if [FREE] is set to 'STOP'
0x400F1020 B  REGISTER INT_EVENT0_IIDX (ro): Interrupt index
0x400F1020 C   FIELD 00w08 INT_EVENT0_IIDX_STAT (ro): I2C Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MISC. 15h-1Fh = Reserved
0x400F1028 B  REGISTER INT_EVENT0_IMASK (rw): Interrupt mask
0x400F1028 C   FIELD 00w01 INT_EVENT0_IMASK_MRXDONE: Master Receive Transaction completed Interrupt
0x400F1028 C   FIELD 01w01 INT_EVENT0_IMASK_MTXDONE: Master Transmit Transaction completed Interrupt
0x400F1028 C   FIELD 02w01 INT_EVENT0_IMASK_MRXFIFOTRG: Master Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes
0x400F1028 C   FIELD 03w01 INT_EVENT0_IMASK_MTXFIFOTRG: Master Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes
0x400F1028 C   FIELD 04w01 INT_EVENT0_IMASK_MRXFIFOFULL: RXFIFO full event. This interrupt is set if an RX FIFO is full.
0x400F1028 C   FIELD 05w01 INT_EVENT0_IMASK_MTXEMPTY: Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode.
0x400F1028 C   FIELD 07w01 INT_EVENT0_IMASK_MNACK: Address/Data NACK Interrupt
0x400F1028 C   FIELD 08w01 INT_EVENT0_IMASK_MSTART: START Detection Interrupt
0x400F1028 C   FIELD 09w01 INT_EVENT0_IMASK_MSTOP: STOP Detection Interrupt
0x400F1028 C   FIELD 10w01 INT_EVENT0_IMASK_MARBLOST: Arbitration Lost Interrupt
0x400F1028 C   FIELD 11w01 INT_EVENT0_IMASK_MDMA_DONE1_2: DMA Done 1 on Event Channel 2
0x400F1028 C   FIELD 12w01 INT_EVENT0_IMASK_MDMA_DONE1_3: DMA Done 1 on Event Channel 3
0x400F1028 C   FIELD 13w01 INT_EVENT0_IMASK_MPEC_RX_ERR: Master RX Pec Error Interrupt
0x400F1028 C   FIELD 14w01 INT_EVENT0_IMASK_TIMEOUTA: Timeout A Interrupt
0x400F1028 C   FIELD 15w01 INT_EVENT0_IMASK_TIMEOUTB: Timeout B Interrupt
0x400F1028 C   FIELD 16w01 INT_EVENT0_IMASK_SRXDONE: Slave Receive Data Interrupt Signals that a byte has been received
0x400F1028 C   FIELD 17w01 INT_EVENT0_IMASK_STXDONE: Slave Transmit Transaction completed Interrupt
0x400F1028 C   FIELD 18w01 INT_EVENT0_IMASK_SRXFIFOTRG: Slave Receive FIFO Trigger
0x400F1028 C   FIELD 19w01 INT_EVENT0_IMASK_STXFIFOTRG: Slave Transmit FIFO Trigger
0x400F1028 C   FIELD 20w01 INT_EVENT0_IMASK_SRXFIFOFULL: RXFIFO full event. This interrupt is set if an Slave RX FIFO is full.
0x400F1028 C   FIELD 21w01 INT_EVENT0_IMASK_STXEMPTY: Slave Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode.
0x400F1028 C   FIELD 22w01 INT_EVENT0_IMASK_SSTART: Start Condition Interrupt
0x400F1028 C   FIELD 23w01 INT_EVENT0_IMASK_SSTOP: Stop Condition Interrupt
0x400F1028 C   FIELD 24w01 INT_EVENT0_IMASK_SGENCALL: General Call Interrupt
0x400F1028 C   FIELD 25w01 INT_EVENT0_IMASK_SDMA_DONE1_2: Slave DMA Done 1 on Event Channel 2
0x400F1028 C   FIELD 26w01 INT_EVENT0_IMASK_SDMA_DONE1_3: Slave DMA Done 1 on Event Channel 3
0x400F1028 C   FIELD 27w01 INT_EVENT0_IMASK_SPEC_RX_ERR: Slave RX Pec Error Interrupt
0x400F1028 C   FIELD 28w01 INT_EVENT0_IMASK_STX_UNFL: Slave TX FIFO underflow
0x400F1028 C   FIELD 29w01 INT_EVENT0_IMASK_SRX_OVFL: Slave RX FIFO overflow
0x400F1028 C   FIELD 30w01 INT_EVENT0_IMASK_SARBLOST: Slave Arbitration Lost
0x400F1028 C   FIELD 31w01 INT_EVENT0_IMASK_INTR_OVFL: Interrupt Overflow Interrupt Mask
0x400F1030 B  REGISTER INT_EVENT0_RIS (ro): Raw interrupt status
0x400F1030 C   FIELD 00w01 INT_EVENT0_RIS_MRXDONE: Master Receive Transaction completed Interrupt
0x400F1030 C   FIELD 01w01 INT_EVENT0_RIS_MTXDONE: Master Transmit Transaction completed Interrupt
0x400F1030 C   FIELD 02w01 INT_EVENT0_RIS_MRXFIFOTRG: Master Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes
0x400F1030 C   FIELD 03w01 INT_EVENT0_RIS_MTXFIFOTRG: Master Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes
0x400F1030 C   FIELD 04w01 INT_EVENT0_RIS_MRXFIFOFULL: RXFIFO full event. This interrupt is set if an RX FIFO is full.
0x400F1030 C   FIELD 05w01 INT_EVENT0_RIS_MTXEMPTY: Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode.
0x400F1030 C   FIELD 07w01 INT_EVENT0_RIS_MNACK: Address/Data NACK Interrupt
0x400F1030 C   FIELD 08w01 INT_EVENT0_RIS_MSTART: START Detection Interrupt
0x400F1030 C   FIELD 09w01 INT_EVENT0_RIS_MSTOP: STOP Detection Interrupt
0x400F1030 C   FIELD 10w01 INT_EVENT0_RIS_MARBLOST: Arbitration Lost Interrupt
0x400F1030 C   FIELD 11w01 INT_EVENT0_RIS_MDMA_DONE1_2: DMA Done 1 on Event Channel 2
0x400F1030 C   FIELD 12w01 INT_EVENT0_RIS_MDMA_DONE1_3: DMA Done 1 on Event Channel 3
0x400F1030 C   FIELD 13w01 INT_EVENT0_RIS_MPEC_RX_ERR: Master RX Pec Error Interrupt
0x400F1030 C   FIELD 14w01 INT_EVENT0_RIS_TIMEOUTA: Timeout A Interrupt
0x400F1030 C   FIELD 15w01 INT_EVENT0_RIS_TIMEOUTB: Timeout B Interrupt
0x400F1030 C   FIELD 16w01 INT_EVENT0_RIS_SRXDONE: Slave Receive Data Interrupt Signals that a byte has been received
0x400F1030 C   FIELD 17w01 INT_EVENT0_RIS_STXDONE: Slave Transmit Transaction completed Interrupt
0x400F1030 C   FIELD 18w01 INT_EVENT0_RIS_SRXFIFOTRG: Slave Receive FIFO Trigger
0x400F1030 C   FIELD 19w01 INT_EVENT0_RIS_STXFIFOTRG: Slave Transmit FIFO Trigger
0x400F1030 C   FIELD 20w01 INT_EVENT0_RIS_SRXFIFOFULL: RXFIFO full event. This interrupt is set if an RX FIFO is full.
0x400F1030 C   FIELD 21w01 INT_EVENT0_RIS_STXEMPTY: Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode.
0x400F1030 C   FIELD 22w01 INT_EVENT0_RIS_SSTART: Start Condition Interrupt
0x400F1030 C   FIELD 23w01 INT_EVENT0_RIS_SSTOP: Stop Condition Interrupt
0x400F1030 C   FIELD 24w01 INT_EVENT0_RIS_SGENCALL: General Call Interrupt
0x400F1030 C   FIELD 25w01 INT_EVENT0_RIS_SDMA_DONE1_2: DMA Done 1 on Event Channel 2
0x400F1030 C   FIELD 26w01 INT_EVENT0_RIS_SDMA_DONE1_3: DMA Done 1 on Event Channel 3
0x400F1030 C   FIELD 27w01 INT_EVENT0_RIS_SPEC_RX_ERR: Slave RX Pec Error Interrupt
0x400F1030 C   FIELD 28w01 INT_EVENT0_RIS_STX_UNFL: Slave TX FIFO underflow
0x400F1030 C   FIELD 29w01 INT_EVENT0_RIS_SRX_OVFL: Slave RX FIFO overflow
0x400F1030 C   FIELD 30w01 INT_EVENT0_RIS_SARBLOST: Slave Arbitration Lost
0x400F1030 C   FIELD 31w01 INT_EVENT0_RIS_INTR_OVFL: Interrupt overflow interrupt It is set when SSTART or SSTOP interrupts overflow i.e. occur twice without being serviced
0x400F1038 B  REGISTER INT_EVENT0_MIS (ro): Masked interrupt status
0x400F1038 C   FIELD 00w01 INT_EVENT0_MIS_MRXDONE: Master Receive Data Interrupt
0x400F1038 C   FIELD 01w01 INT_EVENT0_MIS_MTXDONE: Master Transmit Transaction completed Interrupt
0x400F1038 C   FIELD 02w01 INT_EVENT0_MIS_MRXFIFOTRG: Master Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes
0x400F1038 C   FIELD 03w01 INT_EVENT0_MIS_MTXFIFOTRG: Master Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes
0x400F1038 C   FIELD 04w01 INT_EVENT0_MIS_MRXFIFOFULL: RXFIFO full event. This interrupt is set if the RX FIFO is full.
0x400F1038 C   FIELD 05w01 INT_EVENT0_MIS_MTXEMPTY: Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode.
0x400F1038 C   FIELD 07w01 INT_EVENT0_MIS_MNACK: Address/Data NACK Interrupt
0x400F1038 C   FIELD 08w01 INT_EVENT0_MIS_MSTART: START Detection Interrupt
0x400F1038 C   FIELD 09w01 INT_EVENT0_MIS_MSTOP: STOP Detection Interrupt
0x400F1038 C   FIELD 10w01 INT_EVENT0_MIS_MARBLOST: Arbitration Lost Interrupt
0x400F1038 C   FIELD 11w01 INT_EVENT0_MIS_MDMA_DONE1_2: DMA Done 1 on Event Channel 2
0x400F1038 C   FIELD 12w01 INT_EVENT0_MIS_MDMA_DONE1_3: DMA Done 1 on Event Channel 3
0x400F1038 C   FIELD 13w01 INT_EVENT0_MIS_MPEC_RX_ERR: Master RX Pec Error Interrupt
0x400F1038 C   FIELD 14w01 INT_EVENT0_MIS_TIMEOUTA: Timeout A Interrupt
0x400F1038 C   FIELD 15w01 INT_EVENT0_MIS_TIMEOUTB: Timeout B Interrupt
0x400F1038 C   FIELD 16w01 INT_EVENT0_MIS_SRXDONE: Slave Receive Data Interrupt Signals that a byte has been received
0x400F1038 C   FIELD 17w01 INT_EVENT0_MIS_STXDONE: Slave Transmit Transaction completed Interrupt
0x400F1038 C   FIELD 18w01 INT_EVENT0_MIS_SRXFIFOTRG: Slave Receive FIFO Trigger
0x400F1038 C   FIELD 19w01 INT_EVENT0_MIS_STXFIFOTRG: Slave Transmit FIFO Trigger
0x400F1038 C   FIELD 20w01 INT_EVENT0_MIS_SRXFIFOFULL: RXFIFO full event. This interrupt is set if an RX FIFO is full.
0x400F1038 C   FIELD 21w01 INT_EVENT0_MIS_STXEMPTY: Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode.
0x400F1038 C   FIELD 22w01 INT_EVENT0_MIS_SSTART: Slave START Detection Interrupt
0x400F1038 C   FIELD 23w01 INT_EVENT0_MIS_SSTOP: Slave STOP Detection Interrupt
0x400F1038 C   FIELD 24w01 INT_EVENT0_MIS_SGENCALL: General Call Interrupt
0x400F1038 C   FIELD 25w01 INT_EVENT0_MIS_SDMA_DONE1_2: DMA Done 1 on Event Channel 2
0x400F1038 C   FIELD 26w01 INT_EVENT0_MIS_SDMA_DONE1_3: DMA Done 1 on Event Channel 3
0x400F1038 C   FIELD 27w01 INT_EVENT0_MIS_SPEC_RX_ERR: Slave RX Pec Error Interrupt
0x400F1038 C   FIELD 28w01 INT_EVENT0_MIS_STX_UNFL: Slave TX FIFO underflow
0x400F1038 C   FIELD 29w01 INT_EVENT0_MIS_SRX_OVFL: Slave RX FIFO overflow
0x400F1038 C   FIELD 30w01 INT_EVENT0_MIS_SARBLOST: Slave Arbitration Lost
0x400F1038 C   FIELD 31w01 INT_EVENT0_MIS_INTR_OVFL: Interrupt overflow
0x400F1040 B  REGISTER INT_EVENT0_ISET (wo): Interrupt set
0x400F1040 C   FIELD 00w01 INT_EVENT0_ISET_MRXDONE: Master Receive Data Interrupt Signals that a byte has been received
0x400F1040 C   FIELD 01w01 INT_EVENT0_ISET_MTXDONE: Master Transmit Transaction completed Interrupt
0x400F1040 C   FIELD 02w01 INT_EVENT0_ISET_MRXFIFOTRG: Master Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes
0x400F1040 C   FIELD 03w01 INT_EVENT0_ISET_MTXFIFOTRG: Master Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes
0x400F1040 C   FIELD 04w01 INT_EVENT0_ISET_MRXFIFOFULL: RXFIFO full event.
0x400F1040 C   FIELD 05w01 INT_EVENT0_ISET_MTXEMPTY: Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode.
0x400F1040 C   FIELD 07w01 INT_EVENT0_ISET_MNACK: Address/Data NACK Interrupt
0x400F1040 C   FIELD 08w01 INT_EVENT0_ISET_MSTART: START Detection Interrupt
0x400F1040 C   FIELD 09w01 INT_EVENT0_ISET_MSTOP: STOP Detection Interrupt
0x400F1040 C   FIELD 10w01 INT_EVENT0_ISET_MARBLOST: Arbitration Lost Interrupt
0x400F1040 C   FIELD 11w01 INT_EVENT0_ISET_MDMA_DONE1_2: DMA Done 1 on Event Channel 2
0x400F1040 C   FIELD 12w01 INT_EVENT0_ISET_MDMA_DONE1_3: DMA Done 1 on Event Channel 3
0x400F1040 C   FIELD 13w01 INT_EVENT0_ISET_MPEC_RX_ERR: Master RX Pec Error Interrupt
0x400F1040 C   FIELD 14w01 INT_EVENT0_ISET_TIMEOUTA: Timeout A interrupt
0x400F1040 C   FIELD 15w01 INT_EVENT0_ISET_TIMEOUTB: Timeout B Interrupt
0x400F1040 C   FIELD 16w01 INT_EVENT0_ISET_SRXDONE: Slave Receive Data Interrupt Signals that a byte has been received
0x400F1040 C   FIELD 17w01 INT_EVENT0_ISET_STXDONE: Slave Transmit Transaction completed Interrupt
0x400F1040 C   FIELD 18w01 INT_EVENT0_ISET_SRXFIFOTRG: Slave Receive FIFO Trigger
0x400F1040 C   FIELD 19w01 INT_EVENT0_ISET_STXFIFOTRG: Slave Transmit FIFO Trigger
0x400F1040 C   FIELD 20w01 INT_EVENT0_ISET_SRXFIFOFULL: RXFIFO full event. This interrupt is set if an RX FIFO is full.
0x400F1040 C   FIELD 21w01 INT_EVENT0_ISET_STXEMPTY: Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode.
0x400F1040 C   FIELD 22w01 INT_EVENT0_ISET_SSTART: Start Condition Interrupt
0x400F1040 C   FIELD 23w01 INT_EVENT0_ISET_SSTOP: Stop Condition Interrupt
0x400F1040 C   FIELD 24w01 INT_EVENT0_ISET_SGENCALL: General Call Interrupt
0x400F1040 C   FIELD 25w01 INT_EVENT0_ISET_SDMA_DONE1_2: DMA Done 1 on Event Channel 2
0x400F1040 C   FIELD 26w01 INT_EVENT0_ISET_SDMA_DONE1_3: DMA Done 1 on Event Channel 3
0x400F1040 C   FIELD 27w01 INT_EVENT0_ISET_SPEC_RX_ERR: Slave RX Pec Error Interrupt
0x400F1040 C   FIELD 28w01 INT_EVENT0_ISET_STX_UNFL: Slave TX FIFO underflow
0x400F1040 C   FIELD 29w01 INT_EVENT0_ISET_SRX_OVFL: Slave RX FIFO overflow
0x400F1040 C   FIELD 30w01 INT_EVENT0_ISET_SARBLOST: Slave Arbitration Lost
0x400F1040 C   FIELD 31w01 INT_EVENT0_ISET_INTR_OVFL: Interrupt overflow
0x400F1048 B  REGISTER INT_EVENT0_ICLR (wo): Interrupt clear
0x400F1048 C   FIELD 00w01 INT_EVENT0_ICLR_MRXDONE: Master Receive Data Interrupt Signals that a byte has been received
0x400F1048 C   FIELD 01w01 INT_EVENT0_ICLR_MTXDONE: Master Transmit Transaction completed Interrupt
0x400F1048 C   FIELD 02w01 INT_EVENT0_ICLR_MRXFIFOTRG: Master Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes
0x400F1048 C   FIELD 03w01 INT_EVENT0_ICLR_MTXFIFOTRG: Master Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes
0x400F1048 C   FIELD 04w01 INT_EVENT0_ICLR_MRXFIFOFULL: RXFIFO full event.
0x400F1048 C   FIELD 05w01 INT_EVENT0_ICLR_MTXEMPTY: Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode.
0x400F1048 C   FIELD 07w01 INT_EVENT0_ICLR_MNACK: Address/Data NACK Interrupt
0x400F1048 C   FIELD 08w01 INT_EVENT0_ICLR_MSTART: START Detection Interrupt
0x400F1048 C   FIELD 09w01 INT_EVENT0_ICLR_MSTOP: STOP Detection Interrupt
0x400F1048 C   FIELD 10w01 INT_EVENT0_ICLR_MARBLOST: Arbitration Lost Interrupt
0x400F1048 C   FIELD 11w01 INT_EVENT0_ICLR_MDMA_DONE1_2: DMA Done 1 on Event Channel 2
0x400F1048 C   FIELD 12w01 INT_EVENT0_ICLR_MDMA_DONE1_3: DMA Done 1 on Event Channel 3
0x400F1048 C   FIELD 13w01 INT_EVENT0_ICLR_MPEC_RX_ERR: Master RX Pec Error Interrupt
0x400F1048 C   FIELD 14w01 INT_EVENT0_ICLR_TIMEOUTA: Timeout A interrupt
0x400F1048 C   FIELD 15w01 INT_EVENT0_ICLR_TIMEOUTB: Timeout B Interrupt
0x400F1048 C   FIELD 16w01 INT_EVENT0_ICLR_SRXDONE: Slave Receive Data Interrupt Signals that a byte has been received
0x400F1048 C   FIELD 17w01 INT_EVENT0_ICLR_STXDONE: Slave Transmit Transaction completed Interrupt
0x400F1048 C   FIELD 18w01 INT_EVENT0_ICLR_SRXFIFOTRG: Slave Receive FIFO Trigger
0x400F1048 C   FIELD 19w01 INT_EVENT0_ICLR_STXFIFOTRG: Slave Transmit FIFO Trigger
0x400F1048 C   FIELD 20w01 INT_EVENT0_ICLR_SRXFIFOFULL: RXFIFO full event. This interrupt is set if an RX FIFO is full.
0x400F1048 C   FIELD 21w01 INT_EVENT0_ICLR_STXEMPTY: Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode.
0x400F1048 C   FIELD 22w01 INT_EVENT0_ICLR_SSTART: Slave START Detection Interrupt
0x400F1048 C   FIELD 23w01 INT_EVENT0_ICLR_SSTOP: Slave STOP Detection Interrupt
0x400F1048 C   FIELD 24w01 INT_EVENT0_ICLR_SGENCALL: General Call Interrupt
0x400F1048 C   FIELD 25w01 INT_EVENT0_ICLR_SDMA_DONE1_2: DMA Done 1 on Event Channel 2
0x400F1048 C   FIELD 26w01 INT_EVENT0_ICLR_SDMA_DONE1_3: DMA Done 1 on Event Channel 3
0x400F1048 C   FIELD 27w01 INT_EVENT0_ICLR_SPEC_RX_ERR: Slave RX Pec Error Interrupt
0x400F1048 C   FIELD 28w01 INT_EVENT0_ICLR_STX_UNFL: Slave TX FIFO underflow
0x400F1048 C   FIELD 29w01 INT_EVENT0_ICLR_SRX_OVFL: Slave RX FIFO overflow
0x400F1048 C   FIELD 30w01 INT_EVENT0_ICLR_SARBLOST: Slave Arbitration Lost
0x400F1048 C   FIELD 31w01 INT_EVENT0_ICLR_INTR_OVFL: Interrupt overflow
0x400F1050 B  REGISTER INT_EVENT1_IIDX (ro): Interrupt index
0x400F1050 C   FIELD 00w08 INT_EVENT1_IIDX_STAT (ro): I2C Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MISC. 15h-1Fh = Reserved
0x400F1058 B  REGISTER INT_EVENT1_IMASK (rw): Interrupt mask
0x400F1058 C   FIELD 00w01 INT_EVENT1_IMASK_MRXFIFOTRG: Master Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes
0x400F1058 C   FIELD 01w01 INT_EVENT1_IMASK_MTXFIFOTRG: Master Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes
0x400F1058 C   FIELD 02w01 INT_EVENT1_IMASK_SRXFIFOTRG: Slave Receive FIFO Trigger
0x400F1058 C   FIELD 03w01 INT_EVENT1_IMASK_STXFIFOTRG: Slave Transmit FIFO Trigger
0x400F1060 B  REGISTER INT_EVENT1_RIS (ro): Raw interrupt status
0x400F1060 C   FIELD 00w01 INT_EVENT1_RIS_MRXFIFOTRG: Master Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes
0x400F1060 C   FIELD 01w01 INT_EVENT1_RIS_MTXFIFOTRG: Master Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes
0x400F1060 C   FIELD 02w01 INT_EVENT1_RIS_SRXFIFOTRG: Slave Receive FIFO Trigger
0x400F1060 C   FIELD 03w01 INT_EVENT1_RIS_STXFIFOTRG: Slave Transmit FIFO Trigger
0x400F1068 B  REGISTER INT_EVENT1_MIS (ro): Masked interrupt status
0x400F1068 C   FIELD 00w01 INT_EVENT1_MIS_MRXFIFOTRG: Master Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes
0x400F1068 C   FIELD 01w01 INT_EVENT1_MIS_MTXFIFOTRG: Master Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes
0x400F1068 C   FIELD 02w01 INT_EVENT1_MIS_SRXFIFOTRG: Slave Receive FIFO Trigger
0x400F1068 C   FIELD 03w01 INT_EVENT1_MIS_STXFIFOTRG: Slave Transmit FIFO Trigger
0x400F1070 B  REGISTER INT_EVENT1_ISET (wo): Interrupt set
0x400F1070 C   FIELD 00w01 INT_EVENT1_ISET_MRXFIFOTRG: Master Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes
0x400F1070 C   FIELD 01w01 INT_EVENT1_ISET_MTXFIFOTRG: Master Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes
0x400F1070 C   FIELD 02w01 INT_EVENT1_ISET_SRXFIFOTRG: Slave Receive FIFO Trigger
0x400F1070 C   FIELD 03w01 INT_EVENT1_ISET_STXFIFOTRG: Slave Transmit FIFO Trigger
0x400F1078 B  REGISTER INT_EVENT1_ICLR (wo): Interrupt clear
0x400F1078 C   FIELD 00w01 INT_EVENT1_ICLR_MRXFIFOTRG: Master Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes
0x400F1078 C   FIELD 01w01 INT_EVENT1_ICLR_MTXFIFOTRG: Master Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes
0x400F1078 C   FIELD 02w01 INT_EVENT1_ICLR_SRXFIFOTRG: Slave Receive FIFO Trigger
0x400F1078 C   FIELD 03w01 INT_EVENT1_ICLR_STXFIFOTRG: Slave Transmit FIFO Trigger
0x400F1080 B  REGISTER INT_EVENT2_IIDX (ro): Interrupt index
0x400F1080 C   FIELD 00w08 INT_EVENT2_IIDX_STAT (ro): I2C Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MISC. 15h-1Fh = Reserved
0x400F1088 B  REGISTER INT_EVENT2_IMASK (rw): Interrupt mask
0x400F1088 C   FIELD 00w01 INT_EVENT2_IMASK_MRXFIFOTRG: Master Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes
0x400F1088 C   FIELD 01w01 INT_EVENT2_IMASK_MTXFIFOTRG: Master Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes
0x400F1088 C   FIELD 02w01 INT_EVENT2_IMASK_SRXFIFOTRG: Slave Receive FIFO Trigger
0x400F1088 C   FIELD 03w01 INT_EVENT2_IMASK_STXFIFOTRG: Slave Transmit FIFO Trigger
0x400F1090 B  REGISTER INT_EVENT2_RIS (ro): Raw interrupt status
0x400F1090 C   FIELD 00w01 INT_EVENT2_RIS_MRXFIFOTRG: Master Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes
0x400F1090 C   FIELD 01w01 INT_EVENT2_RIS_MTXFIFOTRG: Master Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes
0x400F1090 C   FIELD 02w01 INT_EVENT2_RIS_SRXFIFOTRG: Slave Receive FIFO Trigger
0x400F1090 C   FIELD 03w01 INT_EVENT2_RIS_STXFIFOTRG: Slave Transmit FIFO Trigger
0x400F1098 B  REGISTER INT_EVENT2_MIS (ro): Masked interrupt status
0x400F1098 C   FIELD 00w01 INT_EVENT2_MIS_MRXFIFOTRG: Master Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes
0x400F1098 C   FIELD 01w01 INT_EVENT2_MIS_MTXFIFOTRG: Master Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes
0x400F1098 C   FIELD 02w01 INT_EVENT2_MIS_SRXFIFOTRG: Slave Receive FIFO Trigger
0x400F1098 C   FIELD 03w01 INT_EVENT2_MIS_STXFIFOTRG: Slave Transmit FIFO Trigger
0x400F10A0 B  REGISTER INT_EVENT2_ISET (wo): Interrupt set
0x400F10A0 C   FIELD 00w01 INT_EVENT2_ISET_MRXFIFOTRG: Master Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes
0x400F10A0 C   FIELD 01w01 INT_EVENT2_ISET_MTXFIFOTRG: Master Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes
0x400F10A0 C   FIELD 02w01 INT_EVENT2_ISET_SRXFIFOTRG: Slave Receive FIFO Trigger
0x400F10A0 C   FIELD 03w01 INT_EVENT2_ISET_STXFIFOTRG: Slave Transmit FIFO Trigger
0x400F10A8 B  REGISTER INT_EVENT2_ICLR (wo): Interrupt clear
0x400F10A8 C   FIELD 00w01 INT_EVENT2_ICLR_MRXFIFOTRG: Master Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes
0x400F10A8 C   FIELD 01w01 INT_EVENT2_ICLR_MTXFIFOTRG: Master Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes
0x400F10A8 C   FIELD 02w01 INT_EVENT2_ICLR_SRXFIFOTRG: Slave Receive FIFO Trigger
0x400F10A8 C   FIELD 03w01 INT_EVENT2_ICLR_STXFIFOTRG: Slave Transmit FIFO Trigger
0x400F10E0 B  REGISTER EVT_MODE (rw): Event Mode
0x400F10E0 C   FIELD 00w02 EVT_MODE_INT0_CFG (ro): Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT0]
0x400F10E0 C   FIELD 02w02 EVT_MODE_INT1_CFG (ro): Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT1]
0x400F10E0 C   FIELD 04w02 EVT_MODE_EVT2_CFG (ro): Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT2]
0x400F10FC B  REGISTER DESC (ro): Module Description
0x400F10FC C   FIELD 00w04 DESC_MINREV: Minor rev of the IP
0x400F10FC C   FIELD 04w04 DESC_MAJREV: Major rev of the IP
0x400F10FC C   FIELD 08w04 DESC_INSTNUM: Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances
0x400F10FC C   FIELD 12w04 DESC_FEATUREVER: Feature Set for the module *instance*
0x400F10FC C   FIELD 16w16 DESC_MODULEID: Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness.
0x400F1200 B  REGISTER GFCTL (rw): I2C Glitch Filter Control
0x400F1200 C   FIELD 00w03 GFCTL_DGFSEL (rw): Glitch Suppression Pulse Width This field controls the pulse width select for glitch suppression on the SCL and SDA lines. The following values are the glitch suppression values in terms of functional clocks. (Core Domain only)
0x400F1200 C   FIELD 08w01 GFCTL_AGFEN (rw): Analog Glitch Suppression Enable
0x400F1200 C   FIELD 09w02 GFCTL_AGFSEL (rw): Analog Glitch Suppression Pulse Width This field controls the pulse width select for the analog glitch suppression on SCL and SDA lines. See device datasheet for exact values. (ULP I2C only)
0x400F1200 C   FIELD 11w01 GFCTL_CHAIN: Analog and digital noise filters chaining enable.
0x400F1204 B  REGISTER TIMEOUT_CTL (rw): I2C Timeout Count Control Register
0x400F1204 C   FIELD 00w08 TIMEOUT_CTL_TCNTLA (rw): Timeout counter A load value Counter A is used for SCL low detection. This field contains the upper 8 bits of a 12-bit pre-load value for the Timeout A count. NOTE: The value of CNTLA must be greater than 1h. Each count is equal to 520 times the timeout period of functional clock. For example, with 8MHz functional clock and a 100KHz operating I2C clock, one timeout period will be equal to (1 / 8MHz) * 520 or 65 us.
0x400F1204 C   FIELD 15w01 TIMEOUT_CTL_TCNTAEN (rw): Timeout Counter A Enable
0x400F1204 C   FIELD 16w08 TIMEOUT_CTL_TCNTLB (rw): Timeout Count B Load: Counter B is used for SCL High Detection. This field contains the upper 8 bits of a 12-bit pre-load value for the Timeout B count. NOTE: The value of CNTLB must be greater than 1h. Each count is equal to 1* clock period. For example, with 10MHz functional clock one timeout period will be equal to1*100ns.
0x400F1204 C   FIELD 31w01 TIMEOUT_CTL_TCNTBEN (rw): Timeout Counter B Enable
0x400F1208 B  REGISTER TIMEOUT_CNT (ro): I2C Timeout Count Register
0x400F1208 C   FIELD 00w08 TIMEOUT_CNT_TCNTA (ro): Timeout Count A Current Count: This field contains the upper 8 bits of a 12-bit current counter for timeout counter A
0x400F1208 C   FIELD 16w08 TIMEOUT_CNT_TCNTB: Timeout Count B Current Count: This field contains the upper 8 bits of a 12-bit current counter for timeout counter B
0x400F1210 B  REGISTER MSA (rw): I2C Master Slave Address Register
0x400F1210 C   FIELD 00w01 MSA_DIR: Receive/Send The DIR bit specifies if the next master operation is a Receive (High) or Transmit (Low). 0h = Transmit 1h = Receive
0x400F1210 C   FIELD 01w10 MSA_SADDR: I2C Slave Address This field specifies bits A9 through A0 of the slave address. In 7-bit addressing mode as selected by MSA.MODE bit, the top 3 bits are don't care
0x400F1210 C   FIELD 15w01 MSA_MMODE: This bit selects the adressing mode to be used in master mode When 0, 7-bit addressing is used. When 1, 10-bit addressing is used.
0x400F1214 B  REGISTER MCTR (rw): I2C Master Control Register
0x400F1214 C   FIELD 00w01 MCTR_BURSTRUN (rw): I2C Master Enable and start transaction
0x400F1214 C   FIELD 01w01 MCTR_START (rw): Generate START
0x400F1214 C   FIELD 02w01 MCTR_STOP (rw): Generate STOP
0x400F1214 C   FIELD 03w01 MCTR_ACK (rw): Data Acknowledge Enable. Software needs to configure this bit to send the ACK or NACK. See field decoding in Table: MCTR Field decoding.
0x400F1214 C   FIELD 04w01 MCTR_MACKOEN: Master ACK overrride Enable
0x400F1214 C   FIELD 05w01 MCTR_RD_ON_TXEMPTY: Read on TX Empty
0x400F1214 C   FIELD 16w12 MCTR_MBLEN (rw): I2C transaction length This field contains the programmed length of bytes of the Transaction.
0x400F1218 B  REGISTER MSR (ro): I2C Master Status Register
0x400F1218 C   FIELD 00w01 MSR_BUSY (ro): I2C Master FSM Busy The BUSY bit is set during an ongoing transaction, so is set during the transmit/receive of the amount of data set in MBLEN including START, RESTART, Address and STOP signal generation when required for the current transaction.
0x400F1218 C   FIELD 01w01 MSR_ERR (ro): Error The error can be from the slave address not being acknowledged or the transmit data not being acknowledged.
0x400F1218 C   FIELD 02w01 MSR_ADRACK (ro): Acknowledge Address
0x400F1218 C   FIELD 03w01 MSR_DATACK (ro): Acknowledge Data
0x400F1218 C   FIELD 04w01 MSR_ARBLST (ro): Arbitration Lost
0x400F1218 C   FIELD 05w01 MSR_IDLE (ro): I2C Idle
0x400F1218 C   FIELD 06w01 MSR_BUSBSY (ro): I2C Bus is Busy Master State Machine will wait until this bit is cleared before starting a transaction. When first enabling the Master in multi master environments, FW should wait for one I2C clock period after setting ACTIVE high before writing to the MTCR register to start the transaction so that if SCL goes low it will trigger the BUSBSY.
0x400F1218 C   FIELD 16w12 MSR_MBCNT (ro): I2C Master Transaction Count This field contains the current count-down value of the transaction.
0x400F121C B  REGISTER MRXDATA (ro): I2C Master RXData
0x400F121C C   FIELD 00w08 MRXDATA_VALUE (ro): Received Data. This field contains the last received data.
0x400F1220 B  REGISTER MTXDATA (rw): I2C Master TXData
0x400F1220 C   FIELD 00w08 MTXDATA_VALUE (rw): Transmit Data This byte contains the data to be transferred during the next transaction.
0x400F1224 B  REGISTER MTPR (rw): I2C Master Timer Period
0x400F1224 C   FIELD 00w07 MTPR_TPR (rw): Timer Period This field is used in the equation to configure SCL_PERIOD : SCL_PERIOD = (1 + TPR ) * (SCL_LP + SCL_HP ) * INT_CLK_PRD where: SCL_PRD is the SCL line period (I2C clock). TPR is the Timer Period register value (range of 1 to 127). SCL_LP is the SCL Low period (fixed at 6). SCL_HP is the SCL High period (fixed at 4). CLK_PRD is the functional clock period in ns.
0x400F1228 B  REGISTER MCR (rw): I2C Master Configuration
0x400F1228 C   FIELD 00w01 MCR_ACTIVE (rw): Device Active After this bit has been set, it should not be set again unless it has been cleared by writing a 0 or by a reset, otherwise transfer failures may occur.
0x400F1228 C   FIELD 01w01 MCR_MMST (rw): Multimaster mode. In Multimaster mode the SCL high time counts once the SCL line has been detected high. If this is not enabled the high time counts as soon as the SCL line has been set high by the I2C controller.
0x400F1228 C   FIELD 02w01 MCR_CLKSTRETCH (rw): Clock Stretching. This bit controls the support for clock stretching of the I2C bus.
0x400F1228 C   FIELD 08w01 MCR_LPBK (rw): I2C Loopback
0x400F1234 B  REGISTER MBMON (ro): I2C Master Bus Monitor
0x400F1234 C   FIELD 00w01 MBMON_SCL (ro): I2C SCL Status
0x400F1234 C   FIELD 01w01 MBMON_SDA (ro): I2C SDA Status
0x400F1238 B  REGISTER MFIFOCTL (rw): I2C Master FIFO Control
0x400F1238 C   FIELD 00w03 MFIFOCTL_TXTRIG: TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated.
0x400F1238 C   FIELD 07w01 MFIFOCTL_TXFLUSH: TX FIFO Flush Setting this bit will Flush the TX FIFO. Before reseting this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed.
0x400F1238 C   FIELD 08w03 MFIFOCTL_RXTRIG: RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO.
0x400F1238 C   FIELD 15w01 MFIFOCTL_RXFLUSH: RX FIFO Flush Setting this bit will Flush the RX FIFO. Before reseting this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed.
0x400F123C B  REGISTER MFIFOSR (ro): I2C Master FIFO Status Register
0x400F123C C   FIELD 00w04 MFIFOSR_RXFIFOCNT (ro): Number of Bytes which could be read from the RX FIFO
0x400F123C C   FIELD 07w01 MFIFOSR_RXFLUSH: RX FIFO Flush When this bit is set a Flush operation for the RX FIFO is active. Clear the RXFLUSH bit in the control register to stop.
0x400F123C C   FIELD 08w04 MFIFOSR_TXFIFOCNT (ro): Number of Bytes which could be put into the TX FIFO
0x400F123C C   FIELD 15w01 MFIFOSR_TXFLUSH: TX FIFO Flush When this bit is set a Flush operation for the TX FIFO is active. Clear the TXFLUSH bit in the control register to stop.
0x400F1240 B  REGISTER MASTER_I2CPECCTL (rw): I2C master PEC control register
0x400F1240 C   FIELD 00w09 MASTER_I2CPECCTL_PECCNT: PEC Count When this field is non zero, the number of I2C bytes are counted (Note that although the PEC is calculated on the I2C address it is not counted at a byte). When the byte count = PECCNT and the state machine is transmitting, the contents of the LSFR is loaded into the shift register instead of the byte received from the Tx FIFO. When the state machine is receiving, after the last bit of this byte is received the LSFR is checked and if it is non-zero, a PEC RX Error interrupt is generated. The I2C packet must be padded to include the PEC byte for both transmit and receive. In transmit mode the FIFO must be loaded with a dummy PEC byte. In receive mode the PEC byte will be passed to the Rx FIFO. In the normal Master use case, FW would set PECEN=1 and PECCNT=SMB packet length (Not including Slave Address byte, but including the PEC byte). FW would then configure DMA to allow the packet to complete unassisted and write MCTR to initiate the transaction. Note that when the byte count = PEC CNT, the byte count is reset to 0 and multiple PEC calculation can automatically occur within a single I2C transaction. Note that any write to the MASTER_I2CPECCTL Register will clear the current PEC Byte Count in the Master State Machine.
0x400F1240 C   FIELD 12w01 MASTER_I2CPECCTL_PECEN: PEC Enable This bit enables the SMB Packet Error Checking (PEC). When enabled the PEC is calculated on all bits accept the Start, Stop, Ack and Nack. The PEC LSFR and the Byte Counter is set to 0 when the State Machine is in the IDLE state, which occur following a Stop or when a timeout occurs. The Counter is also set to 0 after the PEC byte is sent or received. Note that the NACK is automatically send following a PEC byte that results in a PEC error. The PEC Polynomial is x^8 + x^2 + x^1 + 1.
0x400F1244 B  REGISTER MASTER_PECSR (ro): I2C master PEC status register
0x400F1244 C   FIELD 00w09 MASTER_PECSR_PECBYTECNT: PEC Byte Count This is the current PEC Byte Count of the Master State Machine.
0x400F1244 C   FIELD 16w01 MASTER_PECSR_PECSTS_CHECK: This status bit indicates if the PEC was checked in the transaction that occurred before the last Stop. Latched on Stop.
0x400F1244 C   FIELD 17w01 MASTER_PECSR_PECSTS_ERROR: This status bit indicates if a PEC check error occurred in the transaction that occurred before the last Stop. Latched on Stop.
0x400F1250 B  REGISTER SOAR (rw): I2C Slave Own Address
0x400F1250 C   FIELD 00w10 SOAR_OAR (rw): I2C Slave Own Address: This field specifies bits A9 through A0 of the slave address. In 7-bit addressing mode as selected by I2CSOAR.MODE bit, the top 3 bits are don't care
0x400F1250 C   FIELD 14w01 SOAR_OAREN: I2C Slave Own Address Enable
0x400F1250 C   FIELD 15w01 SOAR_SMODE: This bit selects the adressing mode to be used in slave mode. When 0, 7-bit addressing is used. When 1, 10-bit addressing is used.
0x400F1254 B  REGISTER SOAR2 (rw): I2C Slave Own Address 2
0x400F1254 C   FIELD 00w07 SOAR2_OAR2 (rw): I2C Slave Own Address 2 This field specifies the alternate OAR2 address.
0x400F1254 C   FIELD 07w01 SOAR2_OAR2EN (rw): I2C Slave Own Address 2 Enable
0x400F1254 C   FIELD 16w07 SOAR2_OAR2_MASK: I2C Slave Own Address 2 Mask: This field specifies bits A6 through A0 of the slave address. The bits with value 1 in SOAR2.OAR2_MASK field will make the corresponding incoming address bits to match by default regardless of the value inside SOAR2.OAR2 i.e. corresponding SOAR2.OAR2 bit is a dont care.
0x400F1258 B  REGISTER SCTR (rw): I2C Slave Control Register
0x400F1258 C   FIELD 00w01 SCTR_ACTIVE (rw): Device Active. Setting this bit enables the slave functionality.
0x400F1258 C   FIELD 01w01 SCTR_GENCALL (rw): General call response enable. This bit is only available in UCBxI2COA0. Modify only when UCSWRST = 1. 0b = Do not respond to a general call 1b = Respond to a general call
0x400F1258 C   FIELD 02w01 SCTR_SCLKSTRETCH: Slave Clock Stretch Enable
0x400F1258 C   FIELD 03w01 SCTR_TXEMPTY_ON_TREQ: Tx Empty Interrupt on TREQ
0x400F1258 C   FIELD 04w01 SCTR_TXTRIG_TXMODE: Tx Trigger when slave FSM is in Tx Mode
0x400F1258 C   FIELD 05w01 SCTR_TXWAIT_STALE_TXFIFO: Tx transfer waits when stale data in Tx FIFO. This prevents stale bytes left in the TX FIFO from automatically being sent on the next I2C packet. Note: this should be used with TXEMPTY_ON_TREQ set to prevent the Slave State Machine from waiting for TX FIFO data without an interrupt notification when the FIFO data is stale.
0x400F1258 C   FIELD 06w01 SCTR_RXFULL_ON_RREQ: Rx full interrupt generated on RREQ condition as indicated in SSR
0x400F1258 C   FIELD 07w01 SCTR_EN_DEFHOSTADR: Enable Default Host Address
0x400F1258 C   FIELD 08w01 SCTR_EN_ALRESPADR: Enable Alert Response Address
0x400F1258 C   FIELD 09w01 SCTR_EN_DEFDEVADR: Enable Deault device address
0x400F1258 C   FIELD 10w01 SCTR_SWUEN: Slave Wakeup Enable
0x400F125C B  REGISTER SSR (ro): I2C Slave Status Register
0x400F125C C   FIELD 00w01 SSR_RREQ (ro): Receive Request
0x400F125C C   FIELD 01w01 SSR_TREQ (ro): Transmit Request
0x400F125C C   FIELD 02w01 SSR_RXMODE: Slave FSM is in Rx MODE
0x400F125C C   FIELD 03w01 SSR_OAR2SEL (ro): OAR2 Address Matched This bit gets reevaluated after every address comparison.
0x400F125C C   FIELD 04w01 SSR_QCMDST (ro): Quick Command Status Value Description: 0: The last transaction was a normal transaction or a transaction has not occurred. 1: The last transaction was a Quick Command transaction
0x400F125C C   FIELD 05w01 SSR_QCMDRW (ro): Quick Command Read / Write This bit only has meaning when the QCMDST bit is set. Value Description: 0: Quick command was a write 1: Quick command was a read
0x400F125C C   FIELD 06w01 SSR_BUSBSY: I2C bus is busy
0x400F125C C   FIELD 07w01 SSR_TXMODE: Slave FSM is in TX MODE
0x400F125C C   FIELD 08w01 SSR_STALE_TXFIFO: Stale Tx FIFO
0x400F125C C   FIELD 09w10 SSR_ADDRMATCH: Indicates the address for which slave address match happened
0x400F1260 B  REGISTER SRXDATA (ro): I2C Slave RXData
0x400F1260 C   FIELD 00w08 SRXDATA_VALUE (ro): Received Data. This field contains the last received data.
0x400F1264 B  REGISTER STXDATA (rw): I2C Slave TXData
0x400F1264 C   FIELD 00w08 STXDATA_VALUE (rw): Transmit Data This byte contains the data to be transferred during the next transaction.
0x400F1268 B  REGISTER SACKCTL (rw): I2C Slave ACK Control
0x400F1268 C   FIELD 00w01 SACKCTL_ACKOEN (rw): I2C Slave ACK Override Enable
0x400F1268 C   FIELD 01w01 SACKCTL_ACKOVAL (rw): I2C Slave ACK Override Value Note: for General Call this bit will be ignored if set to NACK and slave continues to receive data.
0x400F1268 C   FIELD 02w01 SACKCTL_ACKOEN_ON_START: When set this bit will automatically turn on the Slave ACKOEN field following a Start Condition.
0x400F1268 C   FIELD 03w01 SACKCTL_ACKOEN_ON_PECNEXT: When set this bit will automatically turn on the Slave ACKOEN field following the ACK/NACK of the byte received just prior to the PEC byte. Note that when ACKOEN is set the PEC byte will not automatically be ACKed/NACKed by the State Machine and FW must perform this function by writing SLAVE_SACKCTL.
0x400F1268 C   FIELD 04w01 SACKCTL_ACKOEN_ON_PECDONE: When set this bit will automatically turn on the Slave ACKOEN field following the ACK/NACK of the received PEC byte.
0x400F126C B  REGISTER SFIFOCTL (rw): I2C Slave FIFO Control
0x400F126C C   FIELD 00w03 SFIFOCTL_TXTRIG: TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated.
0x400F126C C   FIELD 07w01 SFIFOCTL_TXFLUSH: TX FIFO Flush Setting this bit will Flush the TX FIFO. Before reseting this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed.
0x400F126C C   FIELD 08w03 SFIFOCTL_RXTRIG: RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO.
0x400F126C C   FIELD 15w01 SFIFOCTL_RXFLUSH: RX FIFO Flush Setting this bit will Flush the RX FIFO. Before reseting this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed.
0x400F1270 B  REGISTER SFIFOSR (ro): I2C Slave FIFO Status Register
0x400F1270 C   FIELD 00w04 SFIFOSR_RXFIFOCNT (ro): Number of Bytes which could be read from the RX FIFO
0x400F1270 C   FIELD 07w01 SFIFOSR_RXFLUSH: RX FIFO Flush When this bit is set a Flush operation for the RX FIFO is active. Clear the RXFLUSH bit in the control register to stop.
0x400F1270 C   FIELD 08w04 SFIFOSR_TXFIFOCNT (ro): Number of Bytes which could be put into the TX FIFO
0x400F1270 C   FIELD 15w01 SFIFOSR_TXFLUSH: TX FIFO Flush When this bit is set a Flush operation for the TX FIFO is active. Clear the TXFLUSH bit in the control register to stop.
0x400F1274 B  REGISTER SLAVE_PECCTL (rw): I2C Slave PEC control register
0x400F1274 C   FIELD 00w09 SLAVE_PECCTL_PECCNT: When this field is non zero, the number of I2C data bytes are counted. When the byte count = PECCNT and the state machine is transmitting, the contents of the LSFR is loaded into the shift register instead of the byte received from the Tx FIFO. When the state machine is receiving, after the last bit of this byte is received the LSFR is checked and if it is non-zero, a PEC RX Error interrupt is generated. The I2C packet must be padded to include the PEC byte for both transmit and receive. In transmit mode the FIFO must be loaded with a dummy PEC byte. In receive mode the PEC byte will be passed to the Rx FIFO. In the normal Slave use case, FW would set PECEN=1 and PECCNT=0 and use the ACKOEN until the remaining SMB packet length is known. FW would then set the PECCNT to the remaining packet length (Including PEC bye). FW would then configure DMA to allow the packet to complete unassisted and exit NoAck mode. Note that when the byte count = PEC CNT, the byte count is reset to 0 and multiple PEC calculation can automatically occur within a single I2C transaction
0x400F1274 C   FIELD 12w01 SLAVE_PECCTL_PECEN: PEC Enable This bit enables the SMB Packet Error Checking (PEC). When enabled the PEC is calculated on all bits accept the Start, Stop, Ack and Nack. The PEC LSFR and the Byte Counter is set to 0 when the State Machine is in the IDLE state, which occur following a Stop or when a timeout occurs. The Counter is also set to 0 after the PEC byte is sent or received. Note that the NACK is automatically send following a PEC byte that results in a PEC error. The PEC Polynomial is x^8 + x^2 + x^1 + 1.
0x400F1278 B  REGISTER SLAVE_PECSR (ro): I2C slave PEC status register
0x400F1278 C   FIELD 00w09 SLAVE_PECSR_PECBYTECNT: This is the current PEC Byte Count of the Slave State Machine.
0x400F1278 C   FIELD 16w01 SLAVE_PECSR_PECSTS_CHECK: This status bit indicates if the PEC was checked in the transaction that occurred before the last Stop. Latched on Stop.
0x400F1278 C   FIELD 17w01 SLAVE_PECSR_PECSTS_ERROR: This status bit indicates if a PEC check error occurred in the transaction that occurred before the last Stop. Latched on Stop.
0x400F2000 A PERIPHERAL I2C1
0x400F2800 B  REGISTER PWREN (rw): Power enable
0x400F2800 C   FIELD 00w01 PWREN_ENABLE (rw): Enable the power
0x400F2800 C   FIELD 24w08 PWREN_KEY (wo): KEY to allow Power State Change
0x400F2804 B  REGISTER RSTCTL (wo): Reset Control
0x400F2804 C   FIELD 00w01 RSTCTL_RESETASSERT (wo): Assert reset to the peripheral
0x400F2804 C   FIELD 01w01 RSTCTL_RESETSTKYCLR (wo): Clear the RESETSTKY bit in the STAT register
0x400F2804 C   FIELD 24w08 RSTCTL_KEY (wo): Unlock key
0x400F2808 B  REGISTER CLKCFG (rw): Peripheral Clock Configuration Register
0x400F2808 C   FIELD 08w01 CLKCFG_BLOCKASYNC (rw): Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz
0x400F2808 C   FIELD 24w08 CLKCFG_KEY (wo): KEY to Allow State Change -- 0xA9
0x400F2814 B  REGISTER STAT (ro): Status Register
0x400F2814 C   FIELD 16w01 STAT_RESETSTKY (ro): This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register
0x400F3000 B  REGISTER CLKDIV (rw): Clock Divider
0x400F3000 C   FIELD 00w03 CLKDIV_RATIO: Selects divide ratio of module clock
0x400F3004 B  REGISTER CLKSEL (rw): Clock Select for Ultra Low Power peripherals
0x400F3004 C   FIELD 02w01 CLKSEL_MFCLK_SEL (rw): Selects MFCLK as clock source if enabled
0x400F3004 C   FIELD 03w01 CLKSEL_BUSCLK_SEL (rw): Selects BUSCLK as clock source if enabled
0x400F3018 B  REGISTER PDBGCTL (rw): Peripheral Debug Control
0x400F3018 C   FIELD 00w01 PDBGCTL_FREE (rw): Free run control
0x400F3018 C   FIELD 01w01 PDBGCTL_SOFT (rw): Soft halt boundary control. This function is only available, if [FREE] is set to 'STOP'
0x400F3020 B  REGISTER INT_EVENT0_IIDX (ro): Interrupt index
0x400F3020 C   FIELD 00w08 INT_EVENT0_IIDX_STAT (ro): I2C Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MISC. 15h-1Fh = Reserved
0x400F3028 B  REGISTER INT_EVENT0_IMASK (rw): Interrupt mask
0x400F3028 C   FIELD 00w01 INT_EVENT0_IMASK_MRXDONE: Master Receive Transaction completed Interrupt
0x400F3028 C   FIELD 01w01 INT_EVENT0_IMASK_MTXDONE: Master Transmit Transaction completed Interrupt
0x400F3028 C   FIELD 02w01 INT_EVENT0_IMASK_MRXFIFOTRG: Master Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes
0x400F3028 C   FIELD 03w01 INT_EVENT0_IMASK_MTXFIFOTRG: Master Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes
0x400F3028 C   FIELD 04w01 INT_EVENT0_IMASK_MRXFIFOFULL: RXFIFO full event. This interrupt is set if an RX FIFO is full.
0x400F3028 C   FIELD 05w01 INT_EVENT0_IMASK_MTXEMPTY: Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode.
0x400F3028 C   FIELD 07w01 INT_EVENT0_IMASK_MNACK: Address/Data NACK Interrupt
0x400F3028 C   FIELD 08w01 INT_EVENT0_IMASK_MSTART: START Detection Interrupt
0x400F3028 C   FIELD 09w01 INT_EVENT0_IMASK_MSTOP: STOP Detection Interrupt
0x400F3028 C   FIELD 10w01 INT_EVENT0_IMASK_MARBLOST: Arbitration Lost Interrupt
0x400F3028 C   FIELD 11w01 INT_EVENT0_IMASK_MDMA_DONE1_2: DMA Done 1 on Event Channel 2
0x400F3028 C   FIELD 12w01 INT_EVENT0_IMASK_MDMA_DONE1_3: DMA Done 1 on Event Channel 3
0x400F3028 C   FIELD 13w01 INT_EVENT0_IMASK_MPEC_RX_ERR: Master RX Pec Error Interrupt
0x400F3028 C   FIELD 14w01 INT_EVENT0_IMASK_TIMEOUTA: Timeout A Interrupt
0x400F3028 C   FIELD 15w01 INT_EVENT0_IMASK_TIMEOUTB: Timeout B Interrupt
0x400F3028 C   FIELD 16w01 INT_EVENT0_IMASK_SRXDONE: Slave Receive Data Interrupt Signals that a byte has been received
0x400F3028 C   FIELD 17w01 INT_EVENT0_IMASK_STXDONE: Slave Transmit Transaction completed Interrupt
0x400F3028 C   FIELD 18w01 INT_EVENT0_IMASK_SRXFIFOTRG: Slave Receive FIFO Trigger
0x400F3028 C   FIELD 19w01 INT_EVENT0_IMASK_STXFIFOTRG: Slave Transmit FIFO Trigger
0x400F3028 C   FIELD 20w01 INT_EVENT0_IMASK_SRXFIFOFULL: RXFIFO full event. This interrupt is set if an Slave RX FIFO is full.
0x400F3028 C   FIELD 21w01 INT_EVENT0_IMASK_STXEMPTY: Slave Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode.
0x400F3028 C   FIELD 22w01 INT_EVENT0_IMASK_SSTART: Start Condition Interrupt
0x400F3028 C   FIELD 23w01 INT_EVENT0_IMASK_SSTOP: Stop Condition Interrupt
0x400F3028 C   FIELD 24w01 INT_EVENT0_IMASK_SGENCALL: General Call Interrupt
0x400F3028 C   FIELD 25w01 INT_EVENT0_IMASK_SDMA_DONE1_2: Slave DMA Done 1 on Event Channel 2
0x400F3028 C   FIELD 26w01 INT_EVENT0_IMASK_SDMA_DONE1_3: Slave DMA Done 1 on Event Channel 3
0x400F3028 C   FIELD 27w01 INT_EVENT0_IMASK_SPEC_RX_ERR: Slave RX Pec Error Interrupt
0x400F3028 C   FIELD 28w01 INT_EVENT0_IMASK_STX_UNFL: Slave TX FIFO underflow
0x400F3028 C   FIELD 29w01 INT_EVENT0_IMASK_SRX_OVFL: Slave RX FIFO overflow
0x400F3028 C   FIELD 30w01 INT_EVENT0_IMASK_SARBLOST: Slave Arbitration Lost
0x400F3028 C   FIELD 31w01 INT_EVENT0_IMASK_INTR_OVFL: Interrupt Overflow Interrupt Mask
0x400F3030 B  REGISTER INT_EVENT0_RIS (ro): Raw interrupt status
0x400F3030 C   FIELD 00w01 INT_EVENT0_RIS_MRXDONE: Master Receive Transaction completed Interrupt
0x400F3030 C   FIELD 01w01 INT_EVENT0_RIS_MTXDONE: Master Transmit Transaction completed Interrupt
0x400F3030 C   FIELD 02w01 INT_EVENT0_RIS_MRXFIFOTRG: Master Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes
0x400F3030 C   FIELD 03w01 INT_EVENT0_RIS_MTXFIFOTRG: Master Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes
0x400F3030 C   FIELD 04w01 INT_EVENT0_RIS_MRXFIFOFULL: RXFIFO full event. This interrupt is set if an RX FIFO is full.
0x400F3030 C   FIELD 05w01 INT_EVENT0_RIS_MTXEMPTY: Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode.
0x400F3030 C   FIELD 07w01 INT_EVENT0_RIS_MNACK: Address/Data NACK Interrupt
0x400F3030 C   FIELD 08w01 INT_EVENT0_RIS_MSTART: START Detection Interrupt
0x400F3030 C   FIELD 09w01 INT_EVENT0_RIS_MSTOP: STOP Detection Interrupt
0x400F3030 C   FIELD 10w01 INT_EVENT0_RIS_MARBLOST: Arbitration Lost Interrupt
0x400F3030 C   FIELD 11w01 INT_EVENT0_RIS_MDMA_DONE1_2: DMA Done 1 on Event Channel 2
0x400F3030 C   FIELD 12w01 INT_EVENT0_RIS_MDMA_DONE1_3: DMA Done 1 on Event Channel 3
0x400F3030 C   FIELD 13w01 INT_EVENT0_RIS_MPEC_RX_ERR: Master RX Pec Error Interrupt
0x400F3030 C   FIELD 14w01 INT_EVENT0_RIS_TIMEOUTA: Timeout A Interrupt
0x400F3030 C   FIELD 15w01 INT_EVENT0_RIS_TIMEOUTB: Timeout B Interrupt
0x400F3030 C   FIELD 16w01 INT_EVENT0_RIS_SRXDONE: Slave Receive Data Interrupt Signals that a byte has been received
0x400F3030 C   FIELD 17w01 INT_EVENT0_RIS_STXDONE: Slave Transmit Transaction completed Interrupt
0x400F3030 C   FIELD 18w01 INT_EVENT0_RIS_SRXFIFOTRG: Slave Receive FIFO Trigger
0x400F3030 C   FIELD 19w01 INT_EVENT0_RIS_STXFIFOTRG: Slave Transmit FIFO Trigger
0x400F3030 C   FIELD 20w01 INT_EVENT0_RIS_SRXFIFOFULL: RXFIFO full event. This interrupt is set if an RX FIFO is full.
0x400F3030 C   FIELD 21w01 INT_EVENT0_RIS_STXEMPTY: Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode.
0x400F3030 C   FIELD 22w01 INT_EVENT0_RIS_SSTART: Start Condition Interrupt
0x400F3030 C   FIELD 23w01 INT_EVENT0_RIS_SSTOP: Stop Condition Interrupt
0x400F3030 C   FIELD 24w01 INT_EVENT0_RIS_SGENCALL: General Call Interrupt
0x400F3030 C   FIELD 25w01 INT_EVENT0_RIS_SDMA_DONE1_2: DMA Done 1 on Event Channel 2
0x400F3030 C   FIELD 26w01 INT_EVENT0_RIS_SDMA_DONE1_3: DMA Done 1 on Event Channel 3
0x400F3030 C   FIELD 27w01 INT_EVENT0_RIS_SPEC_RX_ERR: Slave RX Pec Error Interrupt
0x400F3030 C   FIELD 28w01 INT_EVENT0_RIS_STX_UNFL: Slave TX FIFO underflow
0x400F3030 C   FIELD 29w01 INT_EVENT0_RIS_SRX_OVFL: Slave RX FIFO overflow
0x400F3030 C   FIELD 30w01 INT_EVENT0_RIS_SARBLOST: Slave Arbitration Lost
0x400F3030 C   FIELD 31w01 INT_EVENT0_RIS_INTR_OVFL: Interrupt overflow interrupt It is set when SSTART or SSTOP interrupts overflow i.e. occur twice without being serviced
0x400F3038 B  REGISTER INT_EVENT0_MIS (ro): Masked interrupt status
0x400F3038 C   FIELD 00w01 INT_EVENT0_MIS_MRXDONE: Master Receive Data Interrupt
0x400F3038 C   FIELD 01w01 INT_EVENT0_MIS_MTXDONE: Master Transmit Transaction completed Interrupt
0x400F3038 C   FIELD 02w01 INT_EVENT0_MIS_MRXFIFOTRG: Master Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes
0x400F3038 C   FIELD 03w01 INT_EVENT0_MIS_MTXFIFOTRG: Master Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes
0x400F3038 C   FIELD 04w01 INT_EVENT0_MIS_MRXFIFOFULL: RXFIFO full event. This interrupt is set if the RX FIFO is full.
0x400F3038 C   FIELD 05w01 INT_EVENT0_MIS_MTXEMPTY: Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode.
0x400F3038 C   FIELD 07w01 INT_EVENT0_MIS_MNACK: Address/Data NACK Interrupt
0x400F3038 C   FIELD 08w01 INT_EVENT0_MIS_MSTART: START Detection Interrupt
0x400F3038 C   FIELD 09w01 INT_EVENT0_MIS_MSTOP: STOP Detection Interrupt
0x400F3038 C   FIELD 10w01 INT_EVENT0_MIS_MARBLOST: Arbitration Lost Interrupt
0x400F3038 C   FIELD 11w01 INT_EVENT0_MIS_MDMA_DONE1_2: DMA Done 1 on Event Channel 2
0x400F3038 C   FIELD 12w01 INT_EVENT0_MIS_MDMA_DONE1_3: DMA Done 1 on Event Channel 3
0x400F3038 C   FIELD 13w01 INT_EVENT0_MIS_MPEC_RX_ERR: Master RX Pec Error Interrupt
0x400F3038 C   FIELD 14w01 INT_EVENT0_MIS_TIMEOUTA: Timeout A Interrupt
0x400F3038 C   FIELD 15w01 INT_EVENT0_MIS_TIMEOUTB: Timeout B Interrupt
0x400F3038 C   FIELD 16w01 INT_EVENT0_MIS_SRXDONE: Slave Receive Data Interrupt Signals that a byte has been received
0x400F3038 C   FIELD 17w01 INT_EVENT0_MIS_STXDONE: Slave Transmit Transaction completed Interrupt
0x400F3038 C   FIELD 18w01 INT_EVENT0_MIS_SRXFIFOTRG: Slave Receive FIFO Trigger
0x400F3038 C   FIELD 19w01 INT_EVENT0_MIS_STXFIFOTRG: Slave Transmit FIFO Trigger
0x400F3038 C   FIELD 20w01 INT_EVENT0_MIS_SRXFIFOFULL: RXFIFO full event. This interrupt is set if an RX FIFO is full.
0x400F3038 C   FIELD 21w01 INT_EVENT0_MIS_STXEMPTY: Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode.
0x400F3038 C   FIELD 22w01 INT_EVENT0_MIS_SSTART: Slave START Detection Interrupt
0x400F3038 C   FIELD 23w01 INT_EVENT0_MIS_SSTOP: Slave STOP Detection Interrupt
0x400F3038 C   FIELD 24w01 INT_EVENT0_MIS_SGENCALL: General Call Interrupt
0x400F3038 C   FIELD 25w01 INT_EVENT0_MIS_SDMA_DONE1_2: DMA Done 1 on Event Channel 2
0x400F3038 C   FIELD 26w01 INT_EVENT0_MIS_SDMA_DONE1_3: DMA Done 1 on Event Channel 3
0x400F3038 C   FIELD 27w01 INT_EVENT0_MIS_SPEC_RX_ERR: Slave RX Pec Error Interrupt
0x400F3038 C   FIELD 28w01 INT_EVENT0_MIS_STX_UNFL: Slave TX FIFO underflow
0x400F3038 C   FIELD 29w01 INT_EVENT0_MIS_SRX_OVFL: Slave RX FIFO overflow
0x400F3038 C   FIELD 30w01 INT_EVENT0_MIS_SARBLOST: Slave Arbitration Lost
0x400F3038 C   FIELD 31w01 INT_EVENT0_MIS_INTR_OVFL: Interrupt overflow
0x400F3040 B  REGISTER INT_EVENT0_ISET (wo): Interrupt set
0x400F3040 C   FIELD 00w01 INT_EVENT0_ISET_MRXDONE: Master Receive Data Interrupt Signals that a byte has been received
0x400F3040 C   FIELD 01w01 INT_EVENT0_ISET_MTXDONE: Master Transmit Transaction completed Interrupt
0x400F3040 C   FIELD 02w01 INT_EVENT0_ISET_MRXFIFOTRG: Master Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes
0x400F3040 C   FIELD 03w01 INT_EVENT0_ISET_MTXFIFOTRG: Master Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes
0x400F3040 C   FIELD 04w01 INT_EVENT0_ISET_MRXFIFOFULL: RXFIFO full event.
0x400F3040 C   FIELD 05w01 INT_EVENT0_ISET_MTXEMPTY: Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode.
0x400F3040 C   FIELD 07w01 INT_EVENT0_ISET_MNACK: Address/Data NACK Interrupt
0x400F3040 C   FIELD 08w01 INT_EVENT0_ISET_MSTART: START Detection Interrupt
0x400F3040 C   FIELD 09w01 INT_EVENT0_ISET_MSTOP: STOP Detection Interrupt
0x400F3040 C   FIELD 10w01 INT_EVENT0_ISET_MARBLOST: Arbitration Lost Interrupt
0x400F3040 C   FIELD 11w01 INT_EVENT0_ISET_MDMA_DONE1_2: DMA Done 1 on Event Channel 2
0x400F3040 C   FIELD 12w01 INT_EVENT0_ISET_MDMA_DONE1_3: DMA Done 1 on Event Channel 3
0x400F3040 C   FIELD 13w01 INT_EVENT0_ISET_MPEC_RX_ERR: Master RX Pec Error Interrupt
0x400F3040 C   FIELD 14w01 INT_EVENT0_ISET_TIMEOUTA: Timeout A interrupt
0x400F3040 C   FIELD 15w01 INT_EVENT0_ISET_TIMEOUTB: Timeout B Interrupt
0x400F3040 C   FIELD 16w01 INT_EVENT0_ISET_SRXDONE: Slave Receive Data Interrupt Signals that a byte has been received
0x400F3040 C   FIELD 17w01 INT_EVENT0_ISET_STXDONE: Slave Transmit Transaction completed Interrupt
0x400F3040 C   FIELD 18w01 INT_EVENT0_ISET_SRXFIFOTRG: Slave Receive FIFO Trigger
0x400F3040 C   FIELD 19w01 INT_EVENT0_ISET_STXFIFOTRG: Slave Transmit FIFO Trigger
0x400F3040 C   FIELD 20w01 INT_EVENT0_ISET_SRXFIFOFULL: RXFIFO full event. This interrupt is set if an RX FIFO is full.
0x400F3040 C   FIELD 21w01 INT_EVENT0_ISET_STXEMPTY: Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode.
0x400F3040 C   FIELD 22w01 INT_EVENT0_ISET_SSTART: Start Condition Interrupt
0x400F3040 C   FIELD 23w01 INT_EVENT0_ISET_SSTOP: Stop Condition Interrupt
0x400F3040 C   FIELD 24w01 INT_EVENT0_ISET_SGENCALL: General Call Interrupt
0x400F3040 C   FIELD 25w01 INT_EVENT0_ISET_SDMA_DONE1_2: DMA Done 1 on Event Channel 2
0x400F3040 C   FIELD 26w01 INT_EVENT0_ISET_SDMA_DONE1_3: DMA Done 1 on Event Channel 3
0x400F3040 C   FIELD 27w01 INT_EVENT0_ISET_SPEC_RX_ERR: Slave RX Pec Error Interrupt
0x400F3040 C   FIELD 28w01 INT_EVENT0_ISET_STX_UNFL: Slave TX FIFO underflow
0x400F3040 C   FIELD 29w01 INT_EVENT0_ISET_SRX_OVFL: Slave RX FIFO overflow
0x400F3040 C   FIELD 30w01 INT_EVENT0_ISET_SARBLOST: Slave Arbitration Lost
0x400F3040 C   FIELD 31w01 INT_EVENT0_ISET_INTR_OVFL: Interrupt overflow
0x400F3048 B  REGISTER INT_EVENT0_ICLR (wo): Interrupt clear
0x400F3048 C   FIELD 00w01 INT_EVENT0_ICLR_MRXDONE: Master Receive Data Interrupt Signals that a byte has been received
0x400F3048 C   FIELD 01w01 INT_EVENT0_ICLR_MTXDONE: Master Transmit Transaction completed Interrupt
0x400F3048 C   FIELD 02w01 INT_EVENT0_ICLR_MRXFIFOTRG: Master Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes
0x400F3048 C   FIELD 03w01 INT_EVENT0_ICLR_MTXFIFOTRG: Master Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes
0x400F3048 C   FIELD 04w01 INT_EVENT0_ICLR_MRXFIFOFULL: RXFIFO full event.
0x400F3048 C   FIELD 05w01 INT_EVENT0_ICLR_MTXEMPTY: Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode.
0x400F3048 C   FIELD 07w01 INT_EVENT0_ICLR_MNACK: Address/Data NACK Interrupt
0x400F3048 C   FIELD 08w01 INT_EVENT0_ICLR_MSTART: START Detection Interrupt
0x400F3048 C   FIELD 09w01 INT_EVENT0_ICLR_MSTOP: STOP Detection Interrupt
0x400F3048 C   FIELD 10w01 INT_EVENT0_ICLR_MARBLOST: Arbitration Lost Interrupt
0x400F3048 C   FIELD 11w01 INT_EVENT0_ICLR_MDMA_DONE1_2: DMA Done 1 on Event Channel 2
0x400F3048 C   FIELD 12w01 INT_EVENT0_ICLR_MDMA_DONE1_3: DMA Done 1 on Event Channel 3
0x400F3048 C   FIELD 13w01 INT_EVENT0_ICLR_MPEC_RX_ERR: Master RX Pec Error Interrupt
0x400F3048 C   FIELD 14w01 INT_EVENT0_ICLR_TIMEOUTA: Timeout A interrupt
0x400F3048 C   FIELD 15w01 INT_EVENT0_ICLR_TIMEOUTB: Timeout B Interrupt
0x400F3048 C   FIELD 16w01 INT_EVENT0_ICLR_SRXDONE: Slave Receive Data Interrupt Signals that a byte has been received
0x400F3048 C   FIELD 17w01 INT_EVENT0_ICLR_STXDONE: Slave Transmit Transaction completed Interrupt
0x400F3048 C   FIELD 18w01 INT_EVENT0_ICLR_SRXFIFOTRG: Slave Receive FIFO Trigger
0x400F3048 C   FIELD 19w01 INT_EVENT0_ICLR_STXFIFOTRG: Slave Transmit FIFO Trigger
0x400F3048 C   FIELD 20w01 INT_EVENT0_ICLR_SRXFIFOFULL: RXFIFO full event. This interrupt is set if an RX FIFO is full.
0x400F3048 C   FIELD 21w01 INT_EVENT0_ICLR_STXEMPTY: Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode.
0x400F3048 C   FIELD 22w01 INT_EVENT0_ICLR_SSTART: Slave START Detection Interrupt
0x400F3048 C   FIELD 23w01 INT_EVENT0_ICLR_SSTOP: Slave STOP Detection Interrupt
0x400F3048 C   FIELD 24w01 INT_EVENT0_ICLR_SGENCALL: General Call Interrupt
0x400F3048 C   FIELD 25w01 INT_EVENT0_ICLR_SDMA_DONE1_2: DMA Done 1 on Event Channel 2
0x400F3048 C   FIELD 26w01 INT_EVENT0_ICLR_SDMA_DONE1_3: DMA Done 1 on Event Channel 3
0x400F3048 C   FIELD 27w01 INT_EVENT0_ICLR_SPEC_RX_ERR: Slave RX Pec Error Interrupt
0x400F3048 C   FIELD 28w01 INT_EVENT0_ICLR_STX_UNFL: Slave TX FIFO underflow
0x400F3048 C   FIELD 29w01 INT_EVENT0_ICLR_SRX_OVFL: Slave RX FIFO overflow
0x400F3048 C   FIELD 30w01 INT_EVENT0_ICLR_SARBLOST: Slave Arbitration Lost
0x400F3048 C   FIELD 31w01 INT_EVENT0_ICLR_INTR_OVFL: Interrupt overflow
0x400F3050 B  REGISTER INT_EVENT1_IIDX (ro): Interrupt index
0x400F3050 C   FIELD 00w08 INT_EVENT1_IIDX_STAT (ro): I2C Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MISC. 15h-1Fh = Reserved
0x400F3058 B  REGISTER INT_EVENT1_IMASK (rw): Interrupt mask
0x400F3058 C   FIELD 00w01 INT_EVENT1_IMASK_MRXFIFOTRG: Master Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes
0x400F3058 C   FIELD 01w01 INT_EVENT1_IMASK_MTXFIFOTRG: Master Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes
0x400F3058 C   FIELD 02w01 INT_EVENT1_IMASK_SRXFIFOTRG: Slave Receive FIFO Trigger
0x400F3058 C   FIELD 03w01 INT_EVENT1_IMASK_STXFIFOTRG: Slave Transmit FIFO Trigger
0x400F3060 B  REGISTER INT_EVENT1_RIS (ro): Raw interrupt status
0x400F3060 C   FIELD 00w01 INT_EVENT1_RIS_MRXFIFOTRG: Master Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes
0x400F3060 C   FIELD 01w01 INT_EVENT1_RIS_MTXFIFOTRG: Master Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes
0x400F3060 C   FIELD 02w01 INT_EVENT1_RIS_SRXFIFOTRG: Slave Receive FIFO Trigger
0x400F3060 C   FIELD 03w01 INT_EVENT1_RIS_STXFIFOTRG: Slave Transmit FIFO Trigger
0x400F3068 B  REGISTER INT_EVENT1_MIS (ro): Masked interrupt status
0x400F3068 C   FIELD 00w01 INT_EVENT1_MIS_MRXFIFOTRG: Master Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes
0x400F3068 C   FIELD 01w01 INT_EVENT1_MIS_MTXFIFOTRG: Master Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes
0x400F3068 C   FIELD 02w01 INT_EVENT1_MIS_SRXFIFOTRG: Slave Receive FIFO Trigger
0x400F3068 C   FIELD 03w01 INT_EVENT1_MIS_STXFIFOTRG: Slave Transmit FIFO Trigger
0x400F3070 B  REGISTER INT_EVENT1_ISET (wo): Interrupt set
0x400F3070 C   FIELD 00w01 INT_EVENT1_ISET_MRXFIFOTRG: Master Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes
0x400F3070 C   FIELD 01w01 INT_EVENT1_ISET_MTXFIFOTRG: Master Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes
0x400F3070 C   FIELD 02w01 INT_EVENT1_ISET_SRXFIFOTRG: Slave Receive FIFO Trigger
0x400F3070 C   FIELD 03w01 INT_EVENT1_ISET_STXFIFOTRG: Slave Transmit FIFO Trigger
0x400F3078 B  REGISTER INT_EVENT1_ICLR (wo): Interrupt clear
0x400F3078 C   FIELD 00w01 INT_EVENT1_ICLR_MRXFIFOTRG: Master Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes
0x400F3078 C   FIELD 01w01 INT_EVENT1_ICLR_MTXFIFOTRG: Master Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes
0x400F3078 C   FIELD 02w01 INT_EVENT1_ICLR_SRXFIFOTRG: Slave Receive FIFO Trigger
0x400F3078 C   FIELD 03w01 INT_EVENT1_ICLR_STXFIFOTRG: Slave Transmit FIFO Trigger
0x400F3080 B  REGISTER INT_EVENT2_IIDX (ro): Interrupt index
0x400F3080 C   FIELD 00w08 INT_EVENT2_IIDX_STAT (ro): I2C Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MISC. 15h-1Fh = Reserved
0x400F3088 B  REGISTER INT_EVENT2_IMASK (rw): Interrupt mask
0x400F3088 C   FIELD 00w01 INT_EVENT2_IMASK_MRXFIFOTRG: Master Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes
0x400F3088 C   FIELD 01w01 INT_EVENT2_IMASK_MTXFIFOTRG: Master Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes
0x400F3088 C   FIELD 02w01 INT_EVENT2_IMASK_SRXFIFOTRG: Slave Receive FIFO Trigger
0x400F3088 C   FIELD 03w01 INT_EVENT2_IMASK_STXFIFOTRG: Slave Transmit FIFO Trigger
0x400F3090 B  REGISTER INT_EVENT2_RIS (ro): Raw interrupt status
0x400F3090 C   FIELD 00w01 INT_EVENT2_RIS_MRXFIFOTRG: Master Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes
0x400F3090 C   FIELD 01w01 INT_EVENT2_RIS_MTXFIFOTRG: Master Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes
0x400F3090 C   FIELD 02w01 INT_EVENT2_RIS_SRXFIFOTRG: Slave Receive FIFO Trigger
0x400F3090 C   FIELD 03w01 INT_EVENT2_RIS_STXFIFOTRG: Slave Transmit FIFO Trigger
0x400F3098 B  REGISTER INT_EVENT2_MIS (ro): Masked interrupt status
0x400F3098 C   FIELD 00w01 INT_EVENT2_MIS_MRXFIFOTRG: Master Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes
0x400F3098 C   FIELD 01w01 INT_EVENT2_MIS_MTXFIFOTRG: Master Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes
0x400F3098 C   FIELD 02w01 INT_EVENT2_MIS_SRXFIFOTRG: Slave Receive FIFO Trigger
0x400F3098 C   FIELD 03w01 INT_EVENT2_MIS_STXFIFOTRG: Slave Transmit FIFO Trigger
0x400F30A0 B  REGISTER INT_EVENT2_ISET (wo): Interrupt set
0x400F30A0 C   FIELD 00w01 INT_EVENT2_ISET_MRXFIFOTRG: Master Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes
0x400F30A0 C   FIELD 01w01 INT_EVENT2_ISET_MTXFIFOTRG: Master Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes
0x400F30A0 C   FIELD 02w01 INT_EVENT2_ISET_SRXFIFOTRG: Slave Receive FIFO Trigger
0x400F30A0 C   FIELD 03w01 INT_EVENT2_ISET_STXFIFOTRG: Slave Transmit FIFO Trigger
0x400F30A8 B  REGISTER INT_EVENT2_ICLR (wo): Interrupt clear
0x400F30A8 C   FIELD 00w01 INT_EVENT2_ICLR_MRXFIFOTRG: Master Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes
0x400F30A8 C   FIELD 01w01 INT_EVENT2_ICLR_MTXFIFOTRG: Master Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes
0x400F30A8 C   FIELD 02w01 INT_EVENT2_ICLR_SRXFIFOTRG: Slave Receive FIFO Trigger
0x400F30A8 C   FIELD 03w01 INT_EVENT2_ICLR_STXFIFOTRG: Slave Transmit FIFO Trigger
0x400F30E0 B  REGISTER EVT_MODE (rw): Event Mode
0x400F30E0 C   FIELD 00w02 EVT_MODE_INT0_CFG (ro): Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT0]
0x400F30E0 C   FIELD 02w02 EVT_MODE_INT1_CFG (ro): Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT1]
0x400F30E0 C   FIELD 04w02 EVT_MODE_EVT2_CFG (ro): Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT2]
0x400F30FC B  REGISTER DESC (ro): Module Description
0x400F30FC C   FIELD 00w04 DESC_MINREV: Minor rev of the IP
0x400F30FC C   FIELD 04w04 DESC_MAJREV: Major rev of the IP
0x400F30FC C   FIELD 08w04 DESC_INSTNUM: Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances
0x400F30FC C   FIELD 12w04 DESC_FEATUREVER: Feature Set for the module *instance*
0x400F30FC C   FIELD 16w16 DESC_MODULEID: Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness.
0x400F3200 B  REGISTER GFCTL (rw): I2C Glitch Filter Control
0x400F3200 C   FIELD 00w03 GFCTL_DGFSEL (rw): Glitch Suppression Pulse Width This field controls the pulse width select for glitch suppression on the SCL and SDA lines. The following values are the glitch suppression values in terms of functional clocks. (Core Domain only)
0x400F3200 C   FIELD 08w01 GFCTL_AGFEN (rw): Analog Glitch Suppression Enable
0x400F3200 C   FIELD 09w02 GFCTL_AGFSEL (rw): Analog Glitch Suppression Pulse Width This field controls the pulse width select for the analog glitch suppression on SCL and SDA lines. See device datasheet for exact values. (ULP I2C only)
0x400F3200 C   FIELD 11w01 GFCTL_CHAIN: Analog and digital noise filters chaining enable.
0x400F3204 B  REGISTER TIMEOUT_CTL (rw): I2C Timeout Count Control Register
0x400F3204 C   FIELD 00w08 TIMEOUT_CTL_TCNTLA (rw): Timeout counter A load value Counter A is used for SCL low detection. This field contains the upper 8 bits of a 12-bit pre-load value for the Timeout A count. NOTE: The value of CNTLA must be greater than 1h. Each count is equal to 520 times the timeout period of functional clock. For example, with 8MHz functional clock and a 100KHz operating I2C clock, one timeout period will be equal to (1 / 8MHz) * 520 or 65 us.
0x400F3204 C   FIELD 15w01 TIMEOUT_CTL_TCNTAEN (rw): Timeout Counter A Enable
0x400F3204 C   FIELD 16w08 TIMEOUT_CTL_TCNTLB (rw): Timeout Count B Load: Counter B is used for SCL High Detection. This field contains the upper 8 bits of a 12-bit pre-load value for the Timeout B count. NOTE: The value of CNTLB must be greater than 1h. Each count is equal to 1* clock period. For example, with 10MHz functional clock one timeout period will be equal to1*100ns.
0x400F3204 C   FIELD 31w01 TIMEOUT_CTL_TCNTBEN (rw): Timeout Counter B Enable
0x400F3208 B  REGISTER TIMEOUT_CNT (ro): I2C Timeout Count Register
0x400F3208 C   FIELD 00w08 TIMEOUT_CNT_TCNTA (ro): Timeout Count A Current Count: This field contains the upper 8 bits of a 12-bit current counter for timeout counter A
0x400F3208 C   FIELD 16w08 TIMEOUT_CNT_TCNTB: Timeout Count B Current Count: This field contains the upper 8 bits of a 12-bit current counter for timeout counter B
0x400F3210 B  REGISTER MSA (rw): I2C Master Slave Address Register
0x400F3210 C   FIELD 00w01 MSA_DIR: Receive/Send The DIR bit specifies if the next master operation is a Receive (High) or Transmit (Low). 0h = Transmit 1h = Receive
0x400F3210 C   FIELD 01w10 MSA_SADDR: I2C Slave Address This field specifies bits A9 through A0 of the slave address. In 7-bit addressing mode as selected by MSA.MODE bit, the top 3 bits are don't care
0x400F3210 C   FIELD 15w01 MSA_MMODE: This bit selects the adressing mode to be used in master mode When 0, 7-bit addressing is used. When 1, 10-bit addressing is used.
0x400F3214 B  REGISTER MCTR (rw): I2C Master Control Register
0x400F3214 C   FIELD 00w01 MCTR_BURSTRUN (rw): I2C Master Enable and start transaction
0x400F3214 C   FIELD 01w01 MCTR_START (rw): Generate START
0x400F3214 C   FIELD 02w01 MCTR_STOP (rw): Generate STOP
0x400F3214 C   FIELD 03w01 MCTR_ACK (rw): Data Acknowledge Enable. Software needs to configure this bit to send the ACK or NACK. See field decoding in Table: MCTR Field decoding.
0x400F3214 C   FIELD 04w01 MCTR_MACKOEN: Master ACK overrride Enable
0x400F3214 C   FIELD 05w01 MCTR_RD_ON_TXEMPTY: Read on TX Empty
0x400F3214 C   FIELD 16w12 MCTR_MBLEN (rw): I2C transaction length This field contains the programmed length of bytes of the Transaction.
0x400F3218 B  REGISTER MSR (ro): I2C Master Status Register
0x400F3218 C   FIELD 00w01 MSR_BUSY (ro): I2C Master FSM Busy The BUSY bit is set during an ongoing transaction, so is set during the transmit/receive of the amount of data set in MBLEN including START, RESTART, Address and STOP signal generation when required for the current transaction.
0x400F3218 C   FIELD 01w01 MSR_ERR (ro): Error The error can be from the slave address not being acknowledged or the transmit data not being acknowledged.
0x400F3218 C   FIELD 02w01 MSR_ADRACK (ro): Acknowledge Address
0x400F3218 C   FIELD 03w01 MSR_DATACK (ro): Acknowledge Data
0x400F3218 C   FIELD 04w01 MSR_ARBLST (ro): Arbitration Lost
0x400F3218 C   FIELD 05w01 MSR_IDLE (ro): I2C Idle
0x400F3218 C   FIELD 06w01 MSR_BUSBSY (ro): I2C Bus is Busy Master State Machine will wait until this bit is cleared before starting a transaction. When first enabling the Master in multi master environments, FW should wait for one I2C clock period after setting ACTIVE high before writing to the MTCR register to start the transaction so that if SCL goes low it will trigger the BUSBSY.
0x400F3218 C   FIELD 16w12 MSR_MBCNT (ro): I2C Master Transaction Count This field contains the current count-down value of the transaction.
0x400F321C B  REGISTER MRXDATA (ro): I2C Master RXData
0x400F321C C   FIELD 00w08 MRXDATA_VALUE (ro): Received Data. This field contains the last received data.
0x400F3220 B  REGISTER MTXDATA (rw): I2C Master TXData
0x400F3220 C   FIELD 00w08 MTXDATA_VALUE (rw): Transmit Data This byte contains the data to be transferred during the next transaction.
0x400F3224 B  REGISTER MTPR (rw): I2C Master Timer Period
0x400F3224 C   FIELD 00w07 MTPR_TPR (rw): Timer Period This field is used in the equation to configure SCL_PERIOD : SCL_PERIOD = (1 + TPR ) * (SCL_LP + SCL_HP ) * INT_CLK_PRD where: SCL_PRD is the SCL line period (I2C clock). TPR is the Timer Period register value (range of 1 to 127). SCL_LP is the SCL Low period (fixed at 6). SCL_HP is the SCL High period (fixed at 4). CLK_PRD is the functional clock period in ns.
0x400F3228 B  REGISTER MCR (rw): I2C Master Configuration
0x400F3228 C   FIELD 00w01 MCR_ACTIVE (rw): Device Active After this bit has been set, it should not be set again unless it has been cleared by writing a 0 or by a reset, otherwise transfer failures may occur.
0x400F3228 C   FIELD 01w01 MCR_MMST (rw): Multimaster mode. In Multimaster mode the SCL high time counts once the SCL line has been detected high. If this is not enabled the high time counts as soon as the SCL line has been set high by the I2C controller.
0x400F3228 C   FIELD 02w01 MCR_CLKSTRETCH (rw): Clock Stretching. This bit controls the support for clock stretching of the I2C bus.
0x400F3228 C   FIELD 08w01 MCR_LPBK (rw): I2C Loopback
0x400F3234 B  REGISTER MBMON (ro): I2C Master Bus Monitor
0x400F3234 C   FIELD 00w01 MBMON_SCL (ro): I2C SCL Status
0x400F3234 C   FIELD 01w01 MBMON_SDA (ro): I2C SDA Status
0x400F3238 B  REGISTER MFIFOCTL (rw): I2C Master FIFO Control
0x400F3238 C   FIELD 00w03 MFIFOCTL_TXTRIG: TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated.
0x400F3238 C   FIELD 07w01 MFIFOCTL_TXFLUSH: TX FIFO Flush Setting this bit will Flush the TX FIFO. Before reseting this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed.
0x400F3238 C   FIELD 08w03 MFIFOCTL_RXTRIG: RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO.
0x400F3238 C   FIELD 15w01 MFIFOCTL_RXFLUSH: RX FIFO Flush Setting this bit will Flush the RX FIFO. Before reseting this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed.
0x400F323C B  REGISTER MFIFOSR (ro): I2C Master FIFO Status Register
0x400F323C C   FIELD 00w04 MFIFOSR_RXFIFOCNT (ro): Number of Bytes which could be read from the RX FIFO
0x400F323C C   FIELD 07w01 MFIFOSR_RXFLUSH: RX FIFO Flush When this bit is set a Flush operation for the RX FIFO is active. Clear the RXFLUSH bit in the control register to stop.
0x400F323C C   FIELD 08w04 MFIFOSR_TXFIFOCNT (ro): Number of Bytes which could be put into the TX FIFO
0x400F323C C   FIELD 15w01 MFIFOSR_TXFLUSH: TX FIFO Flush When this bit is set a Flush operation for the TX FIFO is active. Clear the TXFLUSH bit in the control register to stop.
0x400F3240 B  REGISTER MASTER_I2CPECCTL (rw): I2C master PEC control register
0x400F3240 C   FIELD 00w09 MASTER_I2CPECCTL_PECCNT: PEC Count When this field is non zero, the number of I2C bytes are counted (Note that although the PEC is calculated on the I2C address it is not counted at a byte). When the byte count = PECCNT and the state machine is transmitting, the contents of the LSFR is loaded into the shift register instead of the byte received from the Tx FIFO. When the state machine is receiving, after the last bit of this byte is received the LSFR is checked and if it is non-zero, a PEC RX Error interrupt is generated. The I2C packet must be padded to include the PEC byte for both transmit and receive. In transmit mode the FIFO must be loaded with a dummy PEC byte. In receive mode the PEC byte will be passed to the Rx FIFO. In the normal Master use case, FW would set PECEN=1 and PECCNT=SMB packet length (Not including Slave Address byte, but including the PEC byte). FW would then configure DMA to allow the packet to complete unassisted and write MCTR to initiate the transaction. Note that when the byte count = PEC CNT, the byte count is reset to 0 and multiple PEC calculation can automatically occur within a single I2C transaction. Note that any write to the MASTER_I2CPECCTL Register will clear the current PEC Byte Count in the Master State Machine.
0x400F3240 C   FIELD 12w01 MASTER_I2CPECCTL_PECEN: PEC Enable This bit enables the SMB Packet Error Checking (PEC). When enabled the PEC is calculated on all bits accept the Start, Stop, Ack and Nack. The PEC LSFR and the Byte Counter is set to 0 when the State Machine is in the IDLE state, which occur following a Stop or when a timeout occurs. The Counter is also set to 0 after the PEC byte is sent or received. Note that the NACK is automatically send following a PEC byte that results in a PEC error. The PEC Polynomial is x^8 + x^2 + x^1 + 1.
0x400F3244 B  REGISTER MASTER_PECSR (ro): I2C master PEC status register
0x400F3244 C   FIELD 00w09 MASTER_PECSR_PECBYTECNT: PEC Byte Count This is the current PEC Byte Count of the Master State Machine.
0x400F3244 C   FIELD 16w01 MASTER_PECSR_PECSTS_CHECK: This status bit indicates if the PEC was checked in the transaction that occurred before the last Stop. Latched on Stop.
0x400F3244 C   FIELD 17w01 MASTER_PECSR_PECSTS_ERROR: This status bit indicates if a PEC check error occurred in the transaction that occurred before the last Stop. Latched on Stop.
0x400F3250 B  REGISTER SOAR (rw): I2C Slave Own Address
0x400F3250 C   FIELD 00w10 SOAR_OAR (rw): I2C Slave Own Address: This field specifies bits A9 through A0 of the slave address. In 7-bit addressing mode as selected by I2CSOAR.MODE bit, the top 3 bits are don't care
0x400F3250 C   FIELD 14w01 SOAR_OAREN: I2C Slave Own Address Enable
0x400F3250 C   FIELD 15w01 SOAR_SMODE: This bit selects the adressing mode to be used in slave mode. When 0, 7-bit addressing is used. When 1, 10-bit addressing is used.
0x400F3254 B  REGISTER SOAR2 (rw): I2C Slave Own Address 2
0x400F3254 C   FIELD 00w07 SOAR2_OAR2 (rw): I2C Slave Own Address 2 This field specifies the alternate OAR2 address.
0x400F3254 C   FIELD 07w01 SOAR2_OAR2EN (rw): I2C Slave Own Address 2 Enable
0x400F3254 C   FIELD 16w07 SOAR2_OAR2_MASK: I2C Slave Own Address 2 Mask: This field specifies bits A6 through A0 of the slave address. The bits with value 1 in SOAR2.OAR2_MASK field will make the corresponding incoming address bits to match by default regardless of the value inside SOAR2.OAR2 i.e. corresponding SOAR2.OAR2 bit is a dont care.
0x400F3258 B  REGISTER SCTR (rw): I2C Slave Control Register
0x400F3258 C   FIELD 00w01 SCTR_ACTIVE (rw): Device Active. Setting this bit enables the slave functionality.
0x400F3258 C   FIELD 01w01 SCTR_GENCALL (rw): General call response enable. This bit is only available in UCBxI2COA0. Modify only when UCSWRST = 1. 0b = Do not respond to a general call 1b = Respond to a general call
0x400F3258 C   FIELD 02w01 SCTR_SCLKSTRETCH: Slave Clock Stretch Enable
0x400F3258 C   FIELD 03w01 SCTR_TXEMPTY_ON_TREQ: Tx Empty Interrupt on TREQ
0x400F3258 C   FIELD 04w01 SCTR_TXTRIG_TXMODE: Tx Trigger when slave FSM is in Tx Mode
0x400F3258 C   FIELD 05w01 SCTR_TXWAIT_STALE_TXFIFO: Tx transfer waits when stale data in Tx FIFO. This prevents stale bytes left in the TX FIFO from automatically being sent on the next I2C packet. Note: this should be used with TXEMPTY_ON_TREQ set to prevent the Slave State Machine from waiting for TX FIFO data without an interrupt notification when the FIFO data is stale.
0x400F3258 C   FIELD 06w01 SCTR_RXFULL_ON_RREQ: Rx full interrupt generated on RREQ condition as indicated in SSR
0x400F3258 C   FIELD 07w01 SCTR_EN_DEFHOSTADR: Enable Default Host Address
0x400F3258 C   FIELD 08w01 SCTR_EN_ALRESPADR: Enable Alert Response Address
0x400F3258 C   FIELD 09w01 SCTR_EN_DEFDEVADR: Enable Deault device address
0x400F3258 C   FIELD 10w01 SCTR_SWUEN: Slave Wakeup Enable
0x400F325C B  REGISTER SSR (ro): I2C Slave Status Register
0x400F325C C   FIELD 00w01 SSR_RREQ (ro): Receive Request
0x400F325C C   FIELD 01w01 SSR_TREQ (ro): Transmit Request
0x400F325C C   FIELD 02w01 SSR_RXMODE: Slave FSM is in Rx MODE
0x400F325C C   FIELD 03w01 SSR_OAR2SEL (ro): OAR2 Address Matched This bit gets reevaluated after every address comparison.
0x400F325C C   FIELD 04w01 SSR_QCMDST (ro): Quick Command Status Value Description: 0: The last transaction was a normal transaction or a transaction has not occurred. 1: The last transaction was a Quick Command transaction
0x400F325C C   FIELD 05w01 SSR_QCMDRW (ro): Quick Command Read / Write This bit only has meaning when the QCMDST bit is set. Value Description: 0: Quick command was a write 1: Quick command was a read
0x400F325C C   FIELD 06w01 SSR_BUSBSY: I2C bus is busy
0x400F325C C   FIELD 07w01 SSR_TXMODE: Slave FSM is in TX MODE
0x400F325C C   FIELD 08w01 SSR_STALE_TXFIFO: Stale Tx FIFO
0x400F325C C   FIELD 09w10 SSR_ADDRMATCH: Indicates the address for which slave address match happened
0x400F3260 B  REGISTER SRXDATA (ro): I2C Slave RXData
0x400F3260 C   FIELD 00w08 SRXDATA_VALUE (ro): Received Data. This field contains the last received data.
0x400F3264 B  REGISTER STXDATA (rw): I2C Slave TXData
0x400F3264 C   FIELD 00w08 STXDATA_VALUE (rw): Transmit Data This byte contains the data to be transferred during the next transaction.
0x400F3268 B  REGISTER SACKCTL (rw): I2C Slave ACK Control
0x400F3268 C   FIELD 00w01 SACKCTL_ACKOEN (rw): I2C Slave ACK Override Enable
0x400F3268 C   FIELD 01w01 SACKCTL_ACKOVAL (rw): I2C Slave ACK Override Value Note: for General Call this bit will be ignored if set to NACK and slave continues to receive data.
0x400F3268 C   FIELD 02w01 SACKCTL_ACKOEN_ON_START: When set this bit will automatically turn on the Slave ACKOEN field following a Start Condition.
0x400F3268 C   FIELD 03w01 SACKCTL_ACKOEN_ON_PECNEXT: When set this bit will automatically turn on the Slave ACKOEN field following the ACK/NACK of the byte received just prior to the PEC byte. Note that when ACKOEN is set the PEC byte will not automatically be ACKed/NACKed by the State Machine and FW must perform this function by writing SLAVE_SACKCTL.
0x400F3268 C   FIELD 04w01 SACKCTL_ACKOEN_ON_PECDONE: When set this bit will automatically turn on the Slave ACKOEN field following the ACK/NACK of the received PEC byte.
0x400F326C B  REGISTER SFIFOCTL (rw): I2C Slave FIFO Control
0x400F326C C   FIELD 00w03 SFIFOCTL_TXTRIG: TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated.
0x400F326C C   FIELD 07w01 SFIFOCTL_TXFLUSH: TX FIFO Flush Setting this bit will Flush the TX FIFO. Before reseting this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed.
0x400F326C C   FIELD 08w03 SFIFOCTL_RXTRIG: RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO.
0x400F326C C   FIELD 15w01 SFIFOCTL_RXFLUSH: RX FIFO Flush Setting this bit will Flush the RX FIFO. Before reseting this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed.
0x400F3270 B  REGISTER SFIFOSR (ro): I2C Slave FIFO Status Register
0x400F3270 C   FIELD 00w04 SFIFOSR_RXFIFOCNT (ro): Number of Bytes which could be read from the RX FIFO
0x400F3270 C   FIELD 07w01 SFIFOSR_RXFLUSH: RX FIFO Flush When this bit is set a Flush operation for the RX FIFO is active. Clear the RXFLUSH bit in the control register to stop.
0x400F3270 C   FIELD 08w04 SFIFOSR_TXFIFOCNT (ro): Number of Bytes which could be put into the TX FIFO
0x400F3270 C   FIELD 15w01 SFIFOSR_TXFLUSH: TX FIFO Flush When this bit is set a Flush operation for the TX FIFO is active. Clear the TXFLUSH bit in the control register to stop.
0x400F3274 B  REGISTER SLAVE_PECCTL (rw): I2C Slave PEC control register
0x400F3274 C   FIELD 00w09 SLAVE_PECCTL_PECCNT: When this field is non zero, the number of I2C data bytes are counted. When the byte count = PECCNT and the state machine is transmitting, the contents of the LSFR is loaded into the shift register instead of the byte received from the Tx FIFO. When the state machine is receiving, after the last bit of this byte is received the LSFR is checked and if it is non-zero, a PEC RX Error interrupt is generated. The I2C packet must be padded to include the PEC byte for both transmit and receive. In transmit mode the FIFO must be loaded with a dummy PEC byte. In receive mode the PEC byte will be passed to the Rx FIFO. In the normal Slave use case, FW would set PECEN=1 and PECCNT=0 and use the ACKOEN until the remaining SMB packet length is known. FW would then set the PECCNT to the remaining packet length (Including PEC bye). FW would then configure DMA to allow the packet to complete unassisted and exit NoAck mode. Note that when the byte count = PEC CNT, the byte count is reset to 0 and multiple PEC calculation can automatically occur within a single I2C transaction
0x400F3274 C   FIELD 12w01 SLAVE_PECCTL_PECEN: PEC Enable This bit enables the SMB Packet Error Checking (PEC). When enabled the PEC is calculated on all bits accept the Start, Stop, Ack and Nack. The PEC LSFR and the Byte Counter is set to 0 when the State Machine is in the IDLE state, which occur following a Stop or when a timeout occurs. The Counter is also set to 0 after the PEC byte is sent or received. Note that the NACK is automatically send following a PEC byte that results in a PEC error. The PEC Polynomial is x^8 + x^2 + x^1 + 1.
0x400F3278 B  REGISTER SLAVE_PECSR (ro): I2C slave PEC status register
0x400F3278 C   FIELD 00w09 SLAVE_PECSR_PECBYTECNT: This is the current PEC Byte Count of the Slave State Machine.
0x400F3278 C   FIELD 16w01 SLAVE_PECSR_PECSTS_CHECK: This status bit indicates if the PEC was checked in the transaction that occurred before the last Stop. Latched on Stop.
0x400F3278 C   FIELD 17w01 SLAVE_PECSR_PECSTS_ERROR: This status bit indicates if a PEC check error occurred in the transaction that occurred before the last Stop. Latched on Stop.
0x40100000 A PERIPHERAL UART1
0x40100800 B  REGISTER PWREN (rw): Power enable
0x40100800 C   FIELD 00w01 PWREN_ENABLE (rw): Enable the power
0x40100800 C   FIELD 24w08 PWREN_KEY (wo): KEY to allow Power State Change
0x40100804 B  REGISTER RSTCTL (wo): Reset Control
0x40100804 C   FIELD 00w01 RSTCTL_RESETASSERT (wo): Assert reset to the peripheral
0x40100804 C   FIELD 01w01 RSTCTL_RESETSTKYCLR (wo): Clear the RESETSTKY bit in the STAT register
0x40100804 C   FIELD 24w08 RSTCTL_KEY (wo): Unlock key
0x40100808 B  REGISTER CLKCFG (rw): Peripheral Clock Configuration Register
0x40100808 C   FIELD 08w01 CLKCFG_BLOCKASYNC (rw): Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz
0x40100808 C   FIELD 24w08 CLKCFG_KEY (wo): KEY to Allow State Change -- 0xA9
0x40100814 B  REGISTER GPRCM_STAT (ro): Status Register
0x40100814 C   FIELD 16w01 GPRCM_STAT_RESETSTKY (ro): This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register
0x40101000 B  REGISTER CLKDIV (rw): Clock Divider
0x40101000 C   FIELD 00w03 CLKDIV_RATIO: Selects divide ratio of module clock
0x40101008 B  REGISTER CLKSEL (rw): Clock Select for Ultra Low Power peripherals
0x40101008 C   FIELD 01w01 CLKSEL_LFCLK_SEL (rw): Selects LFCLK as clock source if enabled
0x40101008 C   FIELD 02w01 CLKSEL_MFCLK_SEL (rw): Selects MFCLK as clock source if enabled
0x40101008 C   FIELD 03w01 CLKSEL_BUSCLK_SEL (rw): Selects BUS CLK as clock source if enabled
0x40101018 B  REGISTER PDBGCTL (rw): Peripheral Debug Control
0x40101018 C   FIELD 00w01 PDBGCTL_FREE (rw): Free run control
0x40101018 C   FIELD 01w01 PDBGCTL_SOFT (rw): Soft halt boundary control. This function is only available, if [FREE] is set to 'STOP'
0x40101020 B  REGISTER INT_EVENT0_IIDX (ro): Interrupt index
0x40101020 C   FIELD 00w08 INT_EVENT0_IIDX_STAT (ro): UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved
0x40101028 B  REGISTER INT_EVENT0_IMASK (rw): Interrupt mask
0x40101028 C   FIELD 00w01 INT_EVENT0_IMASK_RTOUT: Enable UARTOUT Receive Time-Out Interrupt.
0x40101028 C   FIELD 01w01 INT_EVENT0_IMASK_FRMERR: Enable UART Framing Error Interrupt.
0x40101028 C   FIELD 02w01 INT_EVENT0_IMASK_PARERR: Enable UART Parity Error Interrupt.
0x40101028 C   FIELD 03w01 INT_EVENT0_IMASK_BRKERR: Enable UART Break Error Interrupt.
0x40101028 C   FIELD 04w01 INT_EVENT0_IMASK_OVRERR: Enable UART Receive Overrun Error Interrupt.
0x40101028 C   FIELD 05w01 INT_EVENT0_IMASK_RXNE: Enable Negative Edge on UARTxRXD Interrupt.
0x40101028 C   FIELD 06w01 INT_EVENT0_IMASK_RXPE: Enable Positive Edge on UARTxRXD Interrupt.
0x40101028 C   FIELD 10w01 INT_EVENT0_IMASK_RXINT: Enable UART Receive Interrupt.
0x40101028 C   FIELD 11w01 INT_EVENT0_IMASK_TXINT: Enable UART Transmit Interrupt.
0x40101028 C   FIELD 12w01 INT_EVENT0_IMASK_EOT: Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.
0x40101028 C   FIELD 13w01 INT_EVENT0_IMASK_ADDR_MATCH: Enable Address Match Interrupt.
0x40101028 C   FIELD 14w01 INT_EVENT0_IMASK_CTS: Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled
0x40101028 C   FIELD 15w01 INT_EVENT0_IMASK_DMA_DONE_RX: Enable DMA Done on RX Event Channel
0x40101028 C   FIELD 16w01 INT_EVENT0_IMASK_DMA_DONE_TX: Enable DMA Done on TX Event Channel
0x40101028 C   FIELD 17w01 INT_EVENT0_IMASK_NERR: Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal
0x40101030 B  REGISTER INT_EVENT0_RIS (ro): Raw interrupt status
0x40101030 C   FIELD 00w01 INT_EVENT0_RIS_RTOUT: UARTOUT Receive Time-Out Interrupt.
0x40101030 C   FIELD 01w01 INT_EVENT0_RIS_FRMERR: UART Framing Error Interrupt.
0x40101030 C   FIELD 02w01 INT_EVENT0_RIS_PARERR: UART Parity Error Interrupt.
0x40101030 C   FIELD 03w01 INT_EVENT0_RIS_BRKERR: UART Break Error Interrupt.
0x40101030 C   FIELD 04w01 INT_EVENT0_RIS_OVRERR: UART Receive Overrun Error Interrupt.
0x40101030 C   FIELD 05w01 INT_EVENT0_RIS_RXNE: Negative Edge on UARTxRXD Interrupt.
0x40101030 C   FIELD 06w01 INT_EVENT0_RIS_RXPE: Positive Edge on UARTxRXD Interrupt.
0x40101030 C   FIELD 10w01 INT_EVENT0_RIS_RXINT: UART Receive Interrupt.
0x40101030 C   FIELD 11w01 INT_EVENT0_RIS_TXINT: UART Transmit Interrupt.
0x40101030 C   FIELD 12w01 INT_EVENT0_RIS_EOT: UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.
0x40101030 C   FIELD 13w01 INT_EVENT0_RIS_ADDR_MATCH: Address Match Interrupt.
0x40101030 C   FIELD 14w01 INT_EVENT0_RIS_CTS: UART Clear to Send Modem Interrupt. 0 = Interrupt disabled
0x40101030 C   FIELD 15w01 INT_EVENT0_RIS_DMA_DONE_RX: DMA Done on RX Event Channel
0x40101030 C   FIELD 16w01 INT_EVENT0_RIS_DMA_DONE_TX: DMA Done on TX Event Channel
0x40101030 C   FIELD 17w01 INT_EVENT0_RIS_NERR: Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal
0x40101038 B  REGISTER INT_EVENT0_MIS (ro): Masked interrupt status
0x40101038 C   FIELD 00w01 INT_EVENT0_MIS_RTOUT: Masked UARTOUT Receive Time-Out Interrupt.
0x40101038 C   FIELD 01w01 INT_EVENT0_MIS_FRMERR: Masked UART Framing Error Interrupt.
0x40101038 C   FIELD 02w01 INT_EVENT0_MIS_PARERR: Masked UART Parity Error Interrupt.
0x40101038 C   FIELD 03w01 INT_EVENT0_MIS_BRKERR: Masked UART Break Error Interrupt.
0x40101038 C   FIELD 04w01 INT_EVENT0_MIS_OVRERR: Masked UART Receive Overrun Error Interrupt.
0x40101038 C   FIELD 05w01 INT_EVENT0_MIS_RXNE: Masked Negative Edge on UARTxRXD Interrupt.
0x40101038 C   FIELD 06w01 INT_EVENT0_MIS_RXPE: Masked Positive Edge on UARTxRXD Interrupt.
0x40101038 C   FIELD 10w01 INT_EVENT0_MIS_RXINT: Masked UART Receive Interrupt.
0x40101038 C   FIELD 11w01 INT_EVENT0_MIS_TXINT: Masked UART Transmit Interrupt.
0x40101038 C   FIELD 12w01 INT_EVENT0_MIS_EOT: UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.
0x40101038 C   FIELD 13w01 INT_EVENT0_MIS_ADDR_MATCH: Masked Address Match Interrupt.
0x40101038 C   FIELD 14w01 INT_EVENT0_MIS_CTS: Masked UART Clear to Send Modem Interrupt. 0 = Interrupt disabled
0x40101038 C   FIELD 15w01 INT_EVENT0_MIS_DMA_DONE_RX: Masked DMA Done on RX Event Channel
0x40101038 C   FIELD 16w01 INT_EVENT0_MIS_DMA_DONE_TX: Masked DMA Done on TX Event Channel
0x40101038 C   FIELD 17w01 INT_EVENT0_MIS_NERR: Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal
0x40101040 B  REGISTER INT_EVENT0_ISET (wo): Interrupt set
0x40101040 C   FIELD 00w01 INT_EVENT0_ISET_RTOUT: Set UARTOUT Receive Time-Out Interrupt.
0x40101040 C   FIELD 01w01 INT_EVENT0_ISET_FRMERR: Set UART Framing Error Interrupt.
0x40101040 C   FIELD 02w01 INT_EVENT0_ISET_PARERR: Set UART Parity Error Interrupt.
0x40101040 C   FIELD 03w01 INT_EVENT0_ISET_BRKERR: Set UART Break Error Interrupt.
0x40101040 C   FIELD 04w01 INT_EVENT0_ISET_OVRERR: Set UART Receive Overrun Error Interrupt.
0x40101040 C   FIELD 05w01 INT_EVENT0_ISET_RXNE: Set Negative Edge on UARTxRXD Interrupt.
0x40101040 C   FIELD 06w01 INT_EVENT0_ISET_RXPE: Set Positive Edge on UARTxRXD Interrupt.
0x40101040 C   FIELD 10w01 INT_EVENT0_ISET_RXINT: Set UART Receive Interrupt.
0x40101040 C   FIELD 11w01 INT_EVENT0_ISET_TXINT: Set UART Transmit Interrupt.
0x40101040 C   FIELD 12w01 INT_EVENT0_ISET_EOT: Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.
0x40101040 C   FIELD 13w01 INT_EVENT0_ISET_ADDR_MATCH: Set Address Match Interrupt.
0x40101040 C   FIELD 14w01 INT_EVENT0_ISET_CTS: Set UART Clear to Send Modem Interrupt. 0 = Interrupt disabled
0x40101040 C   FIELD 15w01 INT_EVENT0_ISET_DMA_DONE_RX: Set DMA Done on RX Event Channel
0x40101040 C   FIELD 16w01 INT_EVENT0_ISET_DMA_DONE_TX: Set DMA Done on TX Event Channel
0x40101040 C   FIELD 17w01 INT_EVENT0_ISET_NERR: Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal
0x40101048 B  REGISTER INT_EVENT0_ICLR (wo): Interrupt clear
0x40101048 C   FIELD 00w01 INT_EVENT0_ICLR_RTOUT: Clear UARTOUT Receive Time-Out Interrupt.
0x40101048 C   FIELD 01w01 INT_EVENT0_ICLR_FRMERR: Clear UART Framing Error Interrupt.
0x40101048 C   FIELD 02w01 INT_EVENT0_ICLR_PARERR: Clear UART Parity Error Interrupt.
0x40101048 C   FIELD 03w01 INT_EVENT0_ICLR_BRKERR: Clear UART Break Error Interrupt.
0x40101048 C   FIELD 04w01 INT_EVENT0_ICLR_OVRERR: Clear UART Receive Overrun Error Interrupt.
0x40101048 C   FIELD 05w01 INT_EVENT0_ICLR_RXNE: Clear Negative Edge on UARTxRXD Interrupt.
0x40101048 C   FIELD 06w01 INT_EVENT0_ICLR_RXPE: Clear Positive Edge on UARTxRXD Interrupt.
0x40101048 C   FIELD 10w01 INT_EVENT0_ICLR_RXINT: Clear UART Receive Interrupt.
0x40101048 C   FIELD 11w01 INT_EVENT0_ICLR_TXINT: Clear UART Transmit Interrupt.
0x40101048 C   FIELD 12w01 INT_EVENT0_ICLR_EOT: Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.
0x40101048 C   FIELD 13w01 INT_EVENT0_ICLR_ADDR_MATCH: Clear Address Match Interrupt.
0x40101048 C   FIELD 14w01 INT_EVENT0_ICLR_CTS: Clear UART Clear to Send Modem Interrupt. 0 = Interrupt disabled
0x40101048 C   FIELD 15w01 INT_EVENT0_ICLR_DMA_DONE_RX: Clear DMA Done on RX Event Channel
0x40101048 C   FIELD 16w01 INT_EVENT0_ICLR_DMA_DONE_TX: Clear DMA Done on TX Event Channel
0x40101048 C   FIELD 17w01 INT_EVENT0_ICLR_NERR: Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal
0x40101050 B  REGISTER INT_EVENT1_IIDX (ro): Interrupt index
0x40101050 C   FIELD 00w08 INT_EVENT1_IIDX_STAT (ro): UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved
0x40101058 B  REGISTER INT_EVENT1_IMASK (rw): Interrupt mask
0x40101058 C   FIELD 00w01 INT_EVENT1_IMASK_RTOUT: Enable UARTOUT Receive Time-Out Interrupt.
0x40101058 C   FIELD 10w01 INT_EVENT1_IMASK_RXINT: Enable UART Receive Interrupt.
0x40101060 B  REGISTER INT_EVENT1_RIS (ro): Raw interrupt status
0x40101060 C   FIELD 00w01 INT_EVENT1_RIS_RTOUT: UARTOUT Receive Time-Out Interrupt.
0x40101060 C   FIELD 10w01 INT_EVENT1_RIS_RXINT: UART Receive Interrupt.
0x40101068 B  REGISTER INT_EVENT1_MIS (ro): Masked interrupt status
0x40101068 C   FIELD 00w01 INT_EVENT1_MIS_RTOUT: Masked UARTOUT Receive Time-Out Interrupt.
0x40101068 C   FIELD 10w01 INT_EVENT1_MIS_RXINT: Masked UART Receive Interrupt.
0x40101070 B  REGISTER INT_EVENT1_ISET (wo): Interrupt set
0x40101070 C   FIELD 00w01 INT_EVENT1_ISET_RTOUT: Set UARTOUT Receive Time-Out Interrupt.
0x40101070 C   FIELD 10w01 INT_EVENT1_ISET_RXINT: Set UART Receive Interrupt.
0x40101078 B  REGISTER INT_EVENT1_ICLR (wo): Interrupt clear
0x40101078 C   FIELD 00w01 INT_EVENT1_ICLR_RTOUT: Clear UARTOUT Receive Time-Out Interrupt.
0x40101078 C   FIELD 10w01 INT_EVENT1_ICLR_RXINT: Clear UART Receive Interrupt.
0x40101080 B  REGISTER INT_EVENT2_IIDX (ro): Interrupt index
0x40101080 C   FIELD 00w08 INT_EVENT2_IIDX_STAT (ro): UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved
0x40101088 B  REGISTER INT_EVENT2_IMASK (rw): Interrupt mask
0x40101088 C   FIELD 11w01 INT_EVENT2_IMASK_TXINT: Enable UART Transmit Interrupt.
0x40101090 B  REGISTER INT_EVENT2_RIS (ro): Raw interrupt status
0x40101090 C   FIELD 11w01 INT_EVENT2_RIS_TXINT: UART Transmit Interrupt.
0x40101098 B  REGISTER INT_EVENT2_MIS (ro): Masked interrupt status
0x40101098 C   FIELD 11w01 INT_EVENT2_MIS_TXINT: Masked UART Transmit Interrupt.
0x401010A0 B  REGISTER INT_EVENT2_ISET (wo): Interrupt set
0x401010A0 C   FIELD 11w01 INT_EVENT2_ISET_TXINT: Set UART Transmit Interrupt.
0x401010A8 B  REGISTER INT_EVENT2_ICLR (wo): Interrupt clear
0x401010A8 C   FIELD 11w01 INT_EVENT2_ICLR_TXINT: Clear UART Transmit Interrupt.
0x401010E0 B  REGISTER EVT_MODE (rw): Event Mode
0x401010E0 C   FIELD 00w02 EVT_MODE_INT0_CFG (ro): Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT0]
0x401010E0 C   FIELD 02w02 EVT_MODE_EVT1_CFG (ro): Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT1]
0x401010E0 C   FIELD 04w02 EVT_MODE_EVT2_CFG (ro): Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT2]
0x401010FC B  REGISTER DESC (ro): Module Description
0x401010FC C   FIELD 00w04 DESC_MINREV: Minor rev of the IP
0x401010FC C   FIELD 04w04 DESC_MAJREV: Major rev of the IP
0x401010FC C   FIELD 08w04 DESC_INSTNUM: Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances
0x401010FC C   FIELD 12w04 DESC_FEATUREVER: Feature Set for the module *instance*
0x401010FC C   FIELD 16w16 DESC_MODULEID: Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness.
0x40101100 B  REGISTER CTL0 (rw): UART Control Register 0
0x40101100 C   FIELD 00w01 CTL0_ENABLE (rw): UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state.
0x40101100 C   FIELD 02w01 CTL0_LBE (rw): UART Loop Back Enable
0x40101100 C   FIELD 03w01 CTL0_RXE (rw): UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set.
0x40101100 C   FIELD 04w01 CTL0_TXE (rw): UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set.
0x40101100 C   FIELD 05w01 CTL0_TXD_OUT_EN (rw): TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 1 = UARTxTXD pin can be controlled by TXD_OUT, if TXE = 0
0x40101100 C   FIELD 06w01 CTL0_TXD_OUT (rw): TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0.
0x40101100 C   FIELD 08w03 CTL0_MODE (rw): Set the communication mode and protocol used. (Not defined settings uses the default setting: 0)
0x40101100 C   FIELD 12w01 CTL0_RTS (rw): Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output.
0x40101100 C   FIELD 13w01 CTL0_RTSEN (rw): Enable hardware controlled Request to Send
0x40101100 C   FIELD 14w01 CTL0_CTSEN (rw): Enable Clear To Send
0x40101100 C   FIELD 15w02 CTL0_HSE (rw): High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set).
0x40101100 C   FIELD 17w01 CTL0_FEN (rw): UART Enable FIFOs
0x40101100 C   FIELD 18w01 CTL0_MAJVOTE (rw): When enabled with oversmapling of 16, samples samples 7, 8, and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match, RIS.NERR bit is set along with RDR.NERR When enabled with oversmapling of 8, samples samples 3, 4, and 5 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values donot match, RIS.NERR bit is set along with RDR.NERR When disabled, only a single sample of received bit is taken.
0x40101100 C   FIELD 19w01 CTL0_MSBFIRST (rw): Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit.
0x40101104 B  REGISTER LCRH (rw): UART Line Control Register
0x40101104 C   FIELD 00w01 LCRH_BRK (rw): UART Send Break (for LIN Protocol)
0x40101104 C   FIELD 01w01 LCRH_PEN (rw): UART Parity Enable
0x40101104 C   FIELD 02w01 LCRH_EPS (rw): UART Even Parity Select This bit has no effect when parity is disabled by the PEN bit. For 9-Bit UART Mode transmissions, this bit controls the address byte and data byte indication (9th bit). 0 = The transferred byte is a data byte 1 = The transferred byte is an address byte
0x40101104 C   FIELD 03w01 LCRH_STP2 (rw): UART Two Stop Bits Select When in 7816 smart card mode (the SMART bit is set in the UARTCTL register), the number of stop bits is forced to 2.
0x40101104 C   FIELD 04w02 LCRH_WLEN (rw): UART Word Length The bits indicate the number of data bits transmitted or received in a frame as follows:
0x40101104 C   FIELD 06w01 LCRH_SPS (rw): UART Stick Parity Select The Stick Parity Select (SPS) bit is used to set either a permanent '1' or a permanent '0' as parity when transmitting or receiving data. Its purpose is to typically indicate the first byte of a package or to mark an address byte, for example in a multi-drop RS-485 network. 0h = Stick parity is disabled 1h = Stick parity is enabled. When bits PEN, EPS, and SPS of UARTLCRH are set, the parity bit is transmitted and checked as a 0. When bits PEN and SPS are set and EPS is cleared, the parity bit is transmitted and checked as a 1.
0x40101104 C   FIELD 07w01 LCRH_SENDIDLE (rw): UART send IDLE pattern. When this bit is set an SENDIDLE period of 11 bit times will be sent on the TX line. The bit is cleared by hardware afterwards.
0x40101104 C   FIELD 16w05 LCRH_EXTDIR_SETUP (rw): Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be set before the START bit is send
0x40101104 C   FIELD 21w05 LCRH_EXTDIR_HOLD (rw): Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be reset after the beginning of the stop bit. (If 2 STOP bits are enabled the beginning of the 2nd STOP bit.)
0x40101108 B  REGISTER STAT (ro): UART Status Register
0x40101108 C   FIELD 00w01 STAT_BUSY (ro): UART Busy This bit is set as soon as the transmit FIFO or TXBuffer becomes non-empty (regardless of whether UART is enabled) or if a receive data is currently ongoing (after the start edge have been detected until a complete byte, including all stop bits, has been received by the shift register). In IDLE_Line mode the Busy signal also stays set during the idle time generation.
0x40101108 C   FIELD 02w01 STAT_RXFE (ro): UART Receive FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register.
0x40101108 C   FIELD 03w01 STAT_RXFF (ro): UART Receive FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register.
0x40101108 C   FIELD 06w01 STAT_TXFE (ro): UART Transmit FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register.
0x40101108 C   FIELD 07w01 STAT_TXFF (ro): UART Transmit FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register.
0x40101108 C   FIELD 08w01 STAT_CTS (ro): Clear To Send
0x40101108 C   FIELD 09w01 STAT_IDLE (ro): IDLE mode has been detected in Idleline-Mulitprocessor-Mode. The IDLE bit is used as an address tag for each block of characters. In idle-line multiprocessor format, this bit is set when a received character is an address.
0x4010110C B  REGISTER IFLS (rw): UART Interrupt FIFO Level Select Register
0x4010110C C   FIELD 00w03 IFLS_TXIFLSEL (rw): UART Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows: Note: for undefined settings the default configuration is used.
0x4010110C C   FIELD 04w03 IFLS_RXIFLSEL (rw): UART Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows: Note: In ULP domain the trigger levels are used for: 0: LVL_1_4 4: LVL_FULL For undefined settings the default configuration is used.
0x4010110C C   FIELD 08w04 IFLS_RXTOSEL (rw): UART Receive Interrupt Timeout Select. When receiving no start edge for an additional character within the set bittimes a RX interrupt is set even if the FIFO level is not reached. A value of 0 disables this function.
0x40101110 B  REGISTER IBRD (rw): UART Integer Baud-Rate Divisor Register
0x40101110 C   FIELD 00w16 IBRD_DIVINT (rw): Integer Baud-Rate Divisor
0x40101114 B  REGISTER FBRD (rw): UART Fractional Baud-Rate Divisor Register
0x40101114 C   FIELD 00w06 FBRD_DIVFRAC (rw): Fractional Baud-Rate Divisor
0x40101118 B  REGISTER GFCTL (rw): Glitch Filter Control
0x40101118 C   FIELD 08w01 GFCTL_AGFEN (rw): Analog Glitch Suppression Enable
0x40101118 C   FIELD 09w02 GFCTL_AGFSEL (rw): Analog Glitch Suppression Pulse Width This field controls the pulse width select for the analog glitch suppression on the RX line. See device datasheet for exact values. (ULP UART only)
0x40101120 B  REGISTER TXDATA (rw): UART Transmit Data Register
0x40101120 C   FIELD 00w08 TXDATA_DATA (rw): Data Transmitted or Received Data that is to be transmitted via the UART is written to this field. When read, this field contains the data that was received by the UART.
0x40101124 B  REGISTER RXDATA (ro): UART Receive Data Register
0x40101124 C   FIELD 00w08 RXDATA_DATA (ro): Data Transmitted or Received Data that is to be transmitted via the UART is written to this field. When read, this field contains the data that was received by the UART.
0x40101124 C   FIELD 08w01 RXDATA_FRMERR (ro): UART Framing Error Writing to this bit has no effect. The flag is cleared by writing 1 to the FRMERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO.
0x40101124 C   FIELD 09w01 RXDATA_PARERR (ro): UART Parity Error Writing to this bit has no effect. The flag is cleared by writing 1 to the PARERR bit in the UART EVENT ICLR register.
0x40101124 C   FIELD 10w01 RXDATA_BRKERR (ro): UART Break Error Writing to this bit has no effect. The flag is cleared by writing 1 to the BRKERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state) and the next valid start bit is received.
0x40101124 C   FIELD 11w01 RXDATA_OVRERR (ro): UART Receive Overrun Error Writing to this bit has no effect. The flag is cleared by writing 1 to the OVRERR bit in the UART EVENT ICLR register. In case of a receive FIFO overflow, the FIFO contents remain valid because no further data is written when the FIFO is full. Only the contents of the shift register are overwritten. The CPU must read the data in order to empty the FIFO.
0x40101124 C   FIELD 12w01 RXDATA_NERR (ro): Noise Error. Writing to this bit has no effect. The flag is cleared by writing 1 to the NERR bit in the UART EVENT ICLR register.
0x40101148 B  REGISTER AMASK (rw): Self Address Mask Register
0x40101148 C   FIELD 00w08 AMASK_VALUE (rw): Self Address Mask for 9-Bit Mode This field contains the address mask that creates a set of addresses that should be matched. A 0 bit in the MSK bitfield configures, that the corresponding bit in the ADDR bitfield of the UART9BITADDR register is don't care. A 1 bit in the MSK bitfield configures, that the corresponding bit in the ADDR bitfield of the UART9BITADDR register must match.
0x4010114C B  REGISTER ADDR (rw): Self Address Register
0x4010114C C   FIELD 00w08 ADDR_VALUE (rw): Self Address for 9-Bit Mode This field contains the address that should be matched when UART9BITAMASK is FFh.
0x40108000 A PERIPHERAL UART0
0x40108800 B  REGISTER PWREN (rw): Power enable
0x40108800 C   FIELD 00w01 PWREN_ENABLE (rw): Enable the power
0x40108800 C   FIELD 24w08 PWREN_KEY (wo): KEY to allow Power State Change
0x40108804 B  REGISTER RSTCTL (wo): Reset Control
0x40108804 C   FIELD 00w01 RSTCTL_RESETASSERT (wo): Assert reset to the peripheral
0x40108804 C   FIELD 01w01 RSTCTL_RESETSTKYCLR (wo): Clear the RESETSTKY bit in the STAT register
0x40108804 C   FIELD 24w08 RSTCTL_KEY (wo): Unlock key
0x40108808 B  REGISTER CLKCFG (rw): Peripheral Clock Configuration Register
0x40108808 C   FIELD 08w01 CLKCFG_BLOCKASYNC (rw): Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz
0x40108808 C   FIELD 24w08 CLKCFG_KEY (wo): KEY to Allow State Change -- 0xA9
0x40108814 B  REGISTER GPRCM_STAT (ro): Status Register
0x40108814 C   FIELD 16w01 GPRCM_STAT_RESETSTKY (ro): This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register
0x40109000 B  REGISTER CLKDIV (rw): Clock Divider
0x40109000 C   FIELD 00w03 CLKDIV_RATIO: Selects divide ratio of module clock
0x40109008 B  REGISTER CLKSEL (rw): Clock Select for Ultra Low Power peripherals
0x40109008 C   FIELD 01w01 CLKSEL_LFCLK_SEL (rw): Selects LFCLK as clock source if enabled
0x40109008 C   FIELD 02w01 CLKSEL_MFCLK_SEL (rw): Selects MFCLK as clock source if enabled
0x40109008 C   FIELD 03w01 CLKSEL_BUSCLK_SEL (rw): Selects BUS CLK as clock source if enabled
0x40109018 B  REGISTER PDBGCTL (rw): Peripheral Debug Control
0x40109018 C   FIELD 00w01 PDBGCTL_FREE (rw): Free run control
0x40109018 C   FIELD 01w01 PDBGCTL_SOFT (rw): Soft halt boundary control. This function is only available, if [FREE] is set to 'STOP'
0x40109020 B  REGISTER INT_EVENT0_IIDX (ro): Interrupt index
0x40109020 C   FIELD 00w08 INT_EVENT0_IIDX_STAT (ro): UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved
0x40109028 B  REGISTER INT_EVENT0_IMASK (rw): Interrupt mask
0x40109028 C   FIELD 00w01 INT_EVENT0_IMASK_RTOUT: Enable UARTOUT Receive Time-Out Interrupt.
0x40109028 C   FIELD 01w01 INT_EVENT0_IMASK_FRMERR: Enable UART Framing Error Interrupt.
0x40109028 C   FIELD 02w01 INT_EVENT0_IMASK_PARERR: Enable UART Parity Error Interrupt.
0x40109028 C   FIELD 03w01 INT_EVENT0_IMASK_BRKERR: Enable UART Break Error Interrupt.
0x40109028 C   FIELD 04w01 INT_EVENT0_IMASK_OVRERR: Enable UART Receive Overrun Error Interrupt.
0x40109028 C   FIELD 05w01 INT_EVENT0_IMASK_RXNE: Enable Negative Edge on UARTxRXD Interrupt.
0x40109028 C   FIELD 06w01 INT_EVENT0_IMASK_RXPE: Enable Positive Edge on UARTxRXD Interrupt.
0x40109028 C   FIELD 07w01 INT_EVENT0_IMASK_LINC0: Enable LIN Capture 0 / Match Interrupt .
0x40109028 C   FIELD 08w01 INT_EVENT0_IMASK_LINC1: Enable LIN Capture 1 Interrupt.
0x40109028 C   FIELD 09w01 INT_EVENT0_IMASK_LINOVF: Enable LIN Hardware Counter Overflow Interrupt.
0x40109028 C   FIELD 10w01 INT_EVENT0_IMASK_RXINT: Enable UART Receive Interrupt.
0x40109028 C   FIELD 11w01 INT_EVENT0_IMASK_TXINT: Enable UART Transmit Interrupt.
0x40109028 C   FIELD 12w01 INT_EVENT0_IMASK_EOT: Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.
0x40109028 C   FIELD 13w01 INT_EVENT0_IMASK_ADDR_MATCH: Enable Address Match Interrupt.
0x40109028 C   FIELD 14w01 INT_EVENT0_IMASK_CTS: Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled
0x40109028 C   FIELD 15w01 INT_EVENT0_IMASK_DMA_DONE_RX: Enable DMA Done on RX Event Channel
0x40109028 C   FIELD 16w01 INT_EVENT0_IMASK_DMA_DONE_TX: Enable DMA Done on TX Event Channel
0x40109028 C   FIELD 17w01 INT_EVENT0_IMASK_NERR: Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal
0x40109030 B  REGISTER INT_EVENT0_RIS (ro): Raw interrupt status
0x40109030 C   FIELD 00w01 INT_EVENT0_RIS_RTOUT: UARTOUT Receive Time-Out Interrupt.
0x40109030 C   FIELD 01w01 INT_EVENT0_RIS_FRMERR: UART Framing Error Interrupt.
0x40109030 C   FIELD 02w01 INT_EVENT0_RIS_PARERR: UART Parity Error Interrupt.
0x40109030 C   FIELD 03w01 INT_EVENT0_RIS_BRKERR: UART Break Error Interrupt.
0x40109030 C   FIELD 04w01 INT_EVENT0_RIS_OVRERR: UART Receive Overrun Error Interrupt.
0x40109030 C   FIELD 05w01 INT_EVENT0_RIS_RXNE: Negative Edge on UARTxRXD Interrupt.
0x40109030 C   FIELD 06w01 INT_EVENT0_RIS_RXPE: Positive Edge on UARTxRXD Interrupt.
0x40109030 C   FIELD 07w01 INT_EVENT0_RIS_LINC0: LIN Capture 0 / Match Interrupt .
0x40109030 C   FIELD 08w01 INT_EVENT0_RIS_LINC1: LIN Capture 1 Interrupt.
0x40109030 C   FIELD 09w01 INT_EVENT0_RIS_LINOVF: LIN Hardware Counter Overflow Interrupt.
0x40109030 C   FIELD 10w01 INT_EVENT0_RIS_RXINT: UART Receive Interrupt.
0x40109030 C   FIELD 11w01 INT_EVENT0_RIS_TXINT: UART Transmit Interrupt.
0x40109030 C   FIELD 12w01 INT_EVENT0_RIS_EOT: UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.
0x40109030 C   FIELD 13w01 INT_EVENT0_RIS_ADDR_MATCH: Address Match Interrupt.
0x40109030 C   FIELD 14w01 INT_EVENT0_RIS_CTS: UART Clear to Send Modem Interrupt. 0 = Interrupt disabled
0x40109030 C   FIELD 15w01 INT_EVENT0_RIS_DMA_DONE_RX: DMA Done on RX Event Channel
0x40109030 C   FIELD 16w01 INT_EVENT0_RIS_DMA_DONE_TX: DMA Done on TX Event Channel
0x40109030 C   FIELD 17w01 INT_EVENT0_RIS_NERR: Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal
0x40109038 B  REGISTER INT_EVENT0_MIS (ro): Masked interrupt status
0x40109038 C   FIELD 00w01 INT_EVENT0_MIS_RTOUT: Masked UARTOUT Receive Time-Out Interrupt.
0x40109038 C   FIELD 01w01 INT_EVENT0_MIS_FRMERR: Masked UART Framing Error Interrupt.
0x40109038 C   FIELD 02w01 INT_EVENT0_MIS_PARERR: Masked UART Parity Error Interrupt.
0x40109038 C   FIELD 03w01 INT_EVENT0_MIS_BRKERR: Masked UART Break Error Interrupt.
0x40109038 C   FIELD 04w01 INT_EVENT0_MIS_OVRERR: Masked UART Receive Overrun Error Interrupt.
0x40109038 C   FIELD 05w01 INT_EVENT0_MIS_RXNE: Masked Negative Edge on UARTxRXD Interrupt.
0x40109038 C   FIELD 06w01 INT_EVENT0_MIS_RXPE: Masked Positive Edge on UARTxRXD Interrupt.
0x40109038 C   FIELD 07w01 INT_EVENT0_MIS_LINC0: Masked LIN Capture 0 / Match Interrupt .
0x40109038 C   FIELD 08w01 INT_EVENT0_MIS_LINC1: Masked LIN Capture 1 Interrupt.
0x40109038 C   FIELD 09w01 INT_EVENT0_MIS_LINOVF: Masked LIN Hardware Counter Overflow Interrupt.
0x40109038 C   FIELD 10w01 INT_EVENT0_MIS_RXINT: Masked UART Receive Interrupt.
0x40109038 C   FIELD 11w01 INT_EVENT0_MIS_TXINT: Masked UART Transmit Interrupt.
0x40109038 C   FIELD 12w01 INT_EVENT0_MIS_EOT: UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.
0x40109038 C   FIELD 13w01 INT_EVENT0_MIS_ADDR_MATCH: Masked Address Match Interrupt.
0x40109038 C   FIELD 14w01 INT_EVENT0_MIS_CTS: Masked UART Clear to Send Modem Interrupt. 0 = Interrupt disabled
0x40109038 C   FIELD 15w01 INT_EVENT0_MIS_DMA_DONE_RX: Masked DMA Done on RX Event Channel
0x40109038 C   FIELD 16w01 INT_EVENT0_MIS_DMA_DONE_TX: Masked DMA Done on TX Event Channel
0x40109038 C   FIELD 17w01 INT_EVENT0_MIS_NERR: Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal
0x40109040 B  REGISTER INT_EVENT0_ISET (wo): Interrupt set
0x40109040 C   FIELD 00w01 INT_EVENT0_ISET_RTOUT: Set UARTOUT Receive Time-Out Interrupt.
0x40109040 C   FIELD 01w01 INT_EVENT0_ISET_FRMERR: Set UART Framing Error Interrupt.
0x40109040 C   FIELD 02w01 INT_EVENT0_ISET_PARERR: Set UART Parity Error Interrupt.
0x40109040 C   FIELD 03w01 INT_EVENT0_ISET_BRKERR: Set UART Break Error Interrupt.
0x40109040 C   FIELD 04w01 INT_EVENT0_ISET_OVRERR: Set UART Receive Overrun Error Interrupt.
0x40109040 C   FIELD 05w01 INT_EVENT0_ISET_RXNE: Set Negative Edge on UARTxRXD Interrupt.
0x40109040 C   FIELD 06w01 INT_EVENT0_ISET_RXPE: Set Positive Edge on UARTxRXD Interrupt.
0x40109040 C   FIELD 07w01 INT_EVENT0_ISET_LINC0: Set LIN Capture 0 / Match Interrupt .
0x40109040 C   FIELD 08w01 INT_EVENT0_ISET_LINC1: Set LIN Capture 1 Interrupt.
0x40109040 C   FIELD 09w01 INT_EVENT0_ISET_LINOVF: Set LIN Hardware Counter Overflow Interrupt.
0x40109040 C   FIELD 10w01 INT_EVENT0_ISET_RXINT: Set UART Receive Interrupt.
0x40109040 C   FIELD 11w01 INT_EVENT0_ISET_TXINT: Set UART Transmit Interrupt.
0x40109040 C   FIELD 12w01 INT_EVENT0_ISET_EOT: Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.
0x40109040 C   FIELD 13w01 INT_EVENT0_ISET_ADDR_MATCH: Set Address Match Interrupt.
0x40109040 C   FIELD 14w01 INT_EVENT0_ISET_CTS: Set UART Clear to Send Modem Interrupt. 0 = Interrupt disabled
0x40109040 C   FIELD 15w01 INT_EVENT0_ISET_DMA_DONE_RX: Set DMA Done on RX Event Channel
0x40109040 C   FIELD 16w01 INT_EVENT0_ISET_DMA_DONE_TX: Set DMA Done on TX Event Channel
0x40109040 C   FIELD 17w01 INT_EVENT0_ISET_NERR: Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal
0x40109048 B  REGISTER INT_EVENT0_ICLR (wo): Interrupt clear
0x40109048 C   FIELD 00w01 INT_EVENT0_ICLR_RTOUT: Clear UARTOUT Receive Time-Out Interrupt.
0x40109048 C   FIELD 01w01 INT_EVENT0_ICLR_FRMERR: Clear UART Framing Error Interrupt.
0x40109048 C   FIELD 02w01 INT_EVENT0_ICLR_PARERR: Clear UART Parity Error Interrupt.
0x40109048 C   FIELD 03w01 INT_EVENT0_ICLR_BRKERR: Clear UART Break Error Interrupt.
0x40109048 C   FIELD 04w01 INT_EVENT0_ICLR_OVRERR: Clear UART Receive Overrun Error Interrupt.
0x40109048 C   FIELD 05w01 INT_EVENT0_ICLR_RXNE: Clear Negative Edge on UARTxRXD Interrupt.
0x40109048 C   FIELD 06w01 INT_EVENT0_ICLR_RXPE: Clear Positive Edge on UARTxRXD Interrupt.
0x40109048 C   FIELD 07w01 INT_EVENT0_ICLR_LINC0: Clear LIN Capture 0 / Match Interrupt .
0x40109048 C   FIELD 08w01 INT_EVENT0_ICLR_LINC1: Clear LIN Capture 1 Interrupt.
0x40109048 C   FIELD 09w01 INT_EVENT0_ICLR_LINOVF: Clear LIN Hardware Counter Overflow Interrupt.
0x40109048 C   FIELD 10w01 INT_EVENT0_ICLR_RXINT: Clear UART Receive Interrupt.
0x40109048 C   FIELD 11w01 INT_EVENT0_ICLR_TXINT: Clear UART Transmit Interrupt.
0x40109048 C   FIELD 12w01 INT_EVENT0_ICLR_EOT: Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.
0x40109048 C   FIELD 13w01 INT_EVENT0_ICLR_ADDR_MATCH: Clear Address Match Interrupt.
0x40109048 C   FIELD 14w01 INT_EVENT0_ICLR_CTS: Clear UART Clear to Send Modem Interrupt. 0 = Interrupt disabled
0x40109048 C   FIELD 15w01 INT_EVENT0_ICLR_DMA_DONE_RX: Clear DMA Done on RX Event Channel
0x40109048 C   FIELD 16w01 INT_EVENT0_ICLR_DMA_DONE_TX: Clear DMA Done on TX Event Channel
0x40109048 C   FIELD 17w01 INT_EVENT0_ICLR_NERR: Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal
0x40109050 B  REGISTER INT_EVENT1_IIDX (ro): Interrupt index
0x40109050 C   FIELD 00w08 INT_EVENT1_IIDX_STAT (ro): UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved
0x40109058 B  REGISTER INT_EVENT1_IMASK (rw): Interrupt mask
0x40109058 C   FIELD 00w01 INT_EVENT1_IMASK_RTOUT: Enable UARTOUT Receive Time-Out Interrupt.
0x40109058 C   FIELD 10w01 INT_EVENT1_IMASK_RXINT: Enable UART Receive Interrupt.
0x40109060 B  REGISTER INT_EVENT1_RIS (ro): Raw interrupt status
0x40109060 C   FIELD 00w01 INT_EVENT1_RIS_RTOUT: UARTOUT Receive Time-Out Interrupt.
0x40109060 C   FIELD 10w01 INT_EVENT1_RIS_RXINT: UART Receive Interrupt.
0x40109068 B  REGISTER INT_EVENT1_MIS (ro): Masked interrupt status
0x40109068 C   FIELD 00w01 INT_EVENT1_MIS_RTOUT: Masked UARTOUT Receive Time-Out Interrupt.
0x40109068 C   FIELD 10w01 INT_EVENT1_MIS_RXINT: Masked UART Receive Interrupt.
0x40109070 B  REGISTER INT_EVENT1_ISET (wo): Interrupt set
0x40109070 C   FIELD 00w01 INT_EVENT1_ISET_RTOUT: Set UARTOUT Receive Time-Out Interrupt.
0x40109070 C   FIELD 10w01 INT_EVENT1_ISET_RXINT: Set UART Receive Interrupt.
0x40109078 B  REGISTER INT_EVENT1_ICLR (wo): Interrupt clear
0x40109078 C   FIELD 00w01 INT_EVENT1_ICLR_RTOUT: Clear UARTOUT Receive Time-Out Interrupt.
0x40109078 C   FIELD 10w01 INT_EVENT1_ICLR_RXINT: Clear UART Receive Interrupt.
0x40109080 B  REGISTER INT_EVENT2_IIDX (ro): Interrupt index
0x40109080 C   FIELD 00w08 INT_EVENT2_IIDX_STAT (ro): UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved
0x40109088 B  REGISTER INT_EVENT2_IMASK (rw): Interrupt mask
0x40109088 C   FIELD 11w01 INT_EVENT2_IMASK_TXINT: Enable UART Transmit Interrupt.
0x40109090 B  REGISTER INT_EVENT2_RIS (ro): Raw interrupt status
0x40109090 C   FIELD 11w01 INT_EVENT2_RIS_TXINT: UART Transmit Interrupt.
0x40109098 B  REGISTER INT_EVENT2_MIS (ro): Masked interrupt status
0x40109098 C   FIELD 11w01 INT_EVENT2_MIS_TXINT: Masked UART Transmit Interrupt.
0x401090A0 B  REGISTER INT_EVENT2_ISET (wo): Interrupt set
0x401090A0 C   FIELD 11w01 INT_EVENT2_ISET_TXINT: Set UART Transmit Interrupt.
0x401090A8 B  REGISTER INT_EVENT2_ICLR (wo): Interrupt clear
0x401090A8 C   FIELD 11w01 INT_EVENT2_ICLR_TXINT: Clear UART Transmit Interrupt.
0x401090E0 B  REGISTER EVT_MODE (rw): Event Mode
0x401090E0 C   FIELD 00w02 EVT_MODE_INT0_CFG (ro): Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT0]
0x401090E0 C   FIELD 02w02 EVT_MODE_EVT1_CFG (ro): Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT1]
0x401090E0 C   FIELD 04w02 EVT_MODE_EVT2_CFG (ro): Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT2]
0x401090FC B  REGISTER DESC (ro): Module Description
0x401090FC C   FIELD 00w04 DESC_MINREV: Minor rev of the IP
0x401090FC C   FIELD 04w04 DESC_MAJREV: Major rev of the IP
0x401090FC C   FIELD 08w04 DESC_INSTNUM: Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances
0x401090FC C   FIELD 12w04 DESC_FEATUREVER: Feature Set for the module *instance*
0x401090FC C   FIELD 16w16 DESC_MODULEID: Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness.
0x40109100 B  REGISTER CTL0 (rw): UART Control Register 0
0x40109100 C   FIELD 00w01 CTL0_ENABLE (rw): UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state.
0x40109100 C   FIELD 02w01 CTL0_LBE (rw): UART Loop Back Enable
0x40109100 C   FIELD 03w01 CTL0_RXE (rw): UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set.
0x40109100 C   FIELD 04w01 CTL0_TXE (rw): UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set.
0x40109100 C   FIELD 05w01 CTL0_TXD_OUT_EN (rw): TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 1 = UARTxTXD pin can be controlled by TXD_OUT, if TXE = 0
0x40109100 C   FIELD 06w01 CTL0_TXD_OUT (rw): TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0.
0x40109100 C   FIELD 07w01 CTL0_MENC (rw): Manchester Encode enable
0x40109100 C   FIELD 08w03 CTL0_MODE (rw): Set the communication mode and protocol used. (Not defined settings uses the default setting: 0)
0x40109100 C   FIELD 12w01 CTL0_RTS (rw): Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output.
0x40109100 C   FIELD 13w01 CTL0_RTSEN (rw): Enable hardware controlled Request to Send
0x40109100 C   FIELD 14w01 CTL0_CTSEN (rw): Enable Clear To Send
0x40109100 C   FIELD 15w02 CTL0_HSE (rw): High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set).
0x40109100 C   FIELD 17w01 CTL0_FEN (rw): UART Enable FIFOs
0x40109100 C   FIELD 18w01 CTL0_MAJVOTE (rw): When enabled with oversmapling of 16, samples samples 7, 8, and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match, RIS.NERR bit is set along with RDR.NERR When enabled with oversmapling of 8, samples samples 3, 4, and 5 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values donot match, RIS.NERR bit is set along with RDR.NERR When disabled, only a single sample of received bit is taken.
0x40109100 C   FIELD 19w01 CTL0_MSBFIRST (rw): Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit.
0x40109104 B  REGISTER LCRH (rw): UART Line Control Register
0x40109104 C   FIELD 00w01 LCRH_BRK (rw): UART Send Break (for LIN Protocol)
0x40109104 C   FIELD 01w01 LCRH_PEN (rw): UART Parity Enable
0x40109104 C   FIELD 02w01 LCRH_EPS (rw): UART Even Parity Select This bit has no effect when parity is disabled by the PEN bit. For 9-Bit UART Mode transmissions, this bit controls the address byte and data byte indication (9th bit). 0 = The transferred byte is a data byte 1 = The transferred byte is an address byte
0x40109104 C   FIELD 03w01 LCRH_STP2 (rw): UART Two Stop Bits Select When in 7816 smart card mode (the SMART bit is set in the UARTCTL register), the number of stop bits is forced to 2.
0x40109104 C   FIELD 04w02 LCRH_WLEN (rw): UART Word Length The bits indicate the number of data bits transmitted or received in a frame as follows:
0x40109104 C   FIELD 06w01 LCRH_SPS (rw): UART Stick Parity Select The Stick Parity Select (SPS) bit is used to set either a permanent '1' or a permanent '0' as parity when transmitting or receiving data. Its purpose is to typically indicate the first byte of a package or to mark an address byte, for example in a multi-drop RS-485 network. 0h = Stick parity is disabled 1h = Stick parity is enabled. When bits PEN, EPS, and SPS of UARTLCRH are set, the parity bit is transmitted and checked as a 0. When bits PEN and SPS are set and EPS is cleared, the parity bit is transmitted and checked as a 1.
0x40109104 C   FIELD 07w01 LCRH_SENDIDLE (rw): UART send IDLE pattern. When this bit is set an SENDIDLE period of 11 bit times will be sent on the TX line. The bit is cleared by hardware afterwards.
0x40109104 C   FIELD 16w05 LCRH_EXTDIR_SETUP (rw): Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be set before the START bit is send
0x40109104 C   FIELD 21w05 LCRH_EXTDIR_HOLD (rw): Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be reset after the beginning of the stop bit. (If 2 STOP bits are enabled the beginning of the 2nd STOP bit.)
0x40109108 B  REGISTER STAT (ro): UART Status Register
0x40109108 C   FIELD 00w01 STAT_BUSY (ro): UART Busy This bit is set as soon as the transmit FIFO or TXBuffer becomes non-empty (regardless of whether UART is enabled) or if a receive data is currently ongoing (after the start edge have been detected until a complete byte, including all stop bits, has been received by the shift register). In IDLE_Line mode the Busy signal also stays set during the idle time generation.
0x40109108 C   FIELD 02w01 STAT_RXFE (ro): UART Receive FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register.
0x40109108 C   FIELD 03w01 STAT_RXFF (ro): UART Receive FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register.
0x40109108 C   FIELD 06w01 STAT_TXFE (ro): UART Transmit FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register.
0x40109108 C   FIELD 07w01 STAT_TXFF (ro): UART Transmit FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register.
0x40109108 C   FIELD 08w01 STAT_CTS (ro): Clear To Send
0x40109108 C   FIELD 09w01 STAT_IDLE (ro): IDLE mode has been detected in Idleline-Mulitprocessor-Mode. The IDLE bit is used as an address tag for each block of characters. In idle-line multiprocessor format, this bit is set when a received character is an address.
0x4010910C B  REGISTER IFLS (rw): UART Interrupt FIFO Level Select Register
0x4010910C C   FIELD 00w03 IFLS_TXIFLSEL (rw): UART Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows: Note: for undefined settings the default configuration is used.
0x4010910C C   FIELD 04w03 IFLS_RXIFLSEL (rw): UART Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows: Note: In ULP domain the trigger levels are used for: 0: LVL_1_4 4: LVL_FULL For undefined settings the default configuration is used.
0x4010910C C   FIELD 08w04 IFLS_RXTOSEL (rw): UART Receive Interrupt Timeout Select. When receiving no start edge for an additional character within the set bittimes a RX interrupt is set even if the FIFO level is not reached. A value of 0 disables this function.
0x40109110 B  REGISTER IBRD (rw): UART Integer Baud-Rate Divisor Register
0x40109110 C   FIELD 00w16 IBRD_DIVINT (rw): Integer Baud-Rate Divisor
0x40109114 B  REGISTER FBRD (rw): UART Fractional Baud-Rate Divisor Register
0x40109114 C   FIELD 00w06 FBRD_DIVFRAC (rw): Fractional Baud-Rate Divisor
0x40109118 B  REGISTER GFCTL (rw): Glitch Filter Control
0x40109118 C   FIELD 00w06 GFCTL_DGFSEL (rw): Glitch Suppression Pulse Width This field controls the pulse width select for glitch suppression on the RX line. The following values are the glitch suppression values in terms of functional clocks. In IRDA mode: Receive filter length. The minimum pulse length for receive is given by: t(MIN) = (DGFSEL) / f(IRTXCLK)
0x40109118 C   FIELD 08w01 GFCTL_AGFEN (rw): Analog Glitch Suppression Enable
0x40109118 C   FIELD 09w02 GFCTL_AGFSEL (rw): Analog Glitch Suppression Pulse Width This field controls the pulse width select for the analog glitch suppression on the RX line. See device datasheet for exact values. (ULP UART only)
0x40109118 C   FIELD 11w01 GFCTL_CHAIN (rw): Analog and digital noise filters chaining enable. 0 DISABLE: When 0, chaining is disabled and only digital filter output is available to IP logic for sampling 1 ENABLE: When 1, analog and digital glitch filters are chained and the output of the combination is made available to IP logic for sampling
0x40109120 B  REGISTER TXDATA (rw): UART Transmit Data Register
0x40109120 C   FIELD 00w08 TXDATA_DATA (rw): Data Transmitted or Received Data that is to be transmitted via the UART is written to this field. When read, this field contains the data that was received by the UART.
0x40109124 B  REGISTER RXDATA (ro): UART Receive Data Register
0x40109124 C   FIELD 00w08 RXDATA_DATA (ro): Data Transmitted or Received Data that is to be transmitted via the UART is written to this field. When read, this field contains the data that was received by the UART.
0x40109124 C   FIELD 08w01 RXDATA_FRMERR (ro): UART Framing Error Writing to this bit has no effect. The flag is cleared by writing 1 to the FRMERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO.
0x40109124 C   FIELD 09w01 RXDATA_PARERR (ro): UART Parity Error Writing to this bit has no effect. The flag is cleared by writing 1 to the PARERR bit in the UART EVENT ICLR register.
0x40109124 C   FIELD 10w01 RXDATA_BRKERR (ro): UART Break Error Writing to this bit has no effect. The flag is cleared by writing 1 to the BRKERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state) and the next valid start bit is received.
0x40109124 C   FIELD 11w01 RXDATA_OVRERR (ro): UART Receive Overrun Error Writing to this bit has no effect. The flag is cleared by writing 1 to the OVRERR bit in the UART EVENT ICLR register. In case of a receive FIFO overflow, the FIFO contents remain valid because no further data is written when the FIFO is full. Only the contents of the shift register are overwritten. The CPU must read the data in order to empty the FIFO.
0x40109124 C   FIELD 12w01 RXDATA_NERR (ro): Noise Error. Writing to this bit has no effect. The flag is cleared by writing 1 to the NERR bit in the UART EVENT ICLR register.
0x40109130 B  REGISTER LINCNT (rw): UART LIN Mode Counter Register
0x40109130 C   FIELD 00w16 LINCNT_VALUE (rw): 16 bit up counter clocked by the module clock of the UART.
0x40109134 B  REGISTER LINCTL (rw): UART LIN Mode Control Register
0x40109134 C   FIELD 00w01 LINCTL_CTRENA (rw): LIN Counter Enable. LIN counter will only count when enabled.
0x40109134 C   FIELD 01w01 LINCTL_ZERONE (rw): Zero on negative Edge of RXD. When enabled the counter is set to 0 and starts counting on a negative edge of RXD
0x40109134 C   FIELD 02w01 LINCTL_CNTRXLOW (rw): Count while low Signal on RXD When counter is enabled and the signal on RXD is low, the counter increments.
0x40109134 C   FIELD 04w01 LINCTL_LINC0CAP (rw): Capture Counter on negative RXD Edge. When enabled the counter value is captured to LINC0 register on each negative RXD edge. A LINC0 interrupt is triggered when enabled.
0x40109134 C   FIELD 05w01 LINCTL_LINC1CAP (rw): Capture Counter on positive RXD Edge. When enabled the counter value is captured to LINC1 register on each positive RXD edge. A LINC1 interrupt is triggered when enabled.
0x40109134 C   FIELD 06w01 LINCTL_LINC0_MATCH (rw): Counter Compare Match Mode When this bit is set to 1 a counter compare match with LINC0 register triggers an LINC0 interrupt when enabled.
0x40109138 B  REGISTER LINC0 (rw): UART LIN Mode Capture 0 Register
0x40109138 C   FIELD 00w16 LINC0_DATA (rw): 16 Bit Capture / Compare Register Captures current LINCTR value on RXD falling edge when enabled. It can generate a DATA interrupt on capture. If compare mode is enabled (DATA_MATCH = 1) a counter match can generate a LINC0 interrupt.
0x4010913C B  REGISTER LINC1 (rw): UART LIN Mode Capture 1 Register
0x4010913C C   FIELD 00w16 LINC1_DATA (rw): 16 Bit Capture / Compare Register Captures current LINCTR value on RXD rising edge when enabled. It can generate a LINC1 interrupt on capture.
0x40109140 B  REGISTER IRCTL (rw): eUSCI_Ax IrDA Control Word Register
0x40109140 C   FIELD 00w01 IRCTL_IREN (rw): IrDA encoder/decoder enable
0x40109140 C   FIELD 01w01 IRCTL_IRTXCLK (rw): IrDA transmit pulse clock select
0x40109140 C   FIELD 02w06 IRCTL_IRTXPL (rw): Transmit pulse length. Pulse length t(PULSE) = (IRTXPLx + 1) / [2 * f(IRTXCLK)] (IRTXCLK = functional clock of the UART)
0x40109140 C   FIELD 09w01 IRCTL_IRRXPL (rw): IrDA receive input UCAxRXD polarity
0x40109148 B  REGISTER AMASK (rw): Self Address Mask Register
0x40109148 C   FIELD 00w08 AMASK_VALUE (rw): Self Address Mask for 9-Bit Mode This field contains the address mask that creates a set of addresses that should be matched. A 0 bit in the MSK bitfield configures, that the corresponding bit in the ADDR bitfield of the UART9BITADDR register is don't care. A 1 bit in the MSK bitfield configures, that the corresponding bit in the ADDR bitfield of the UART9BITADDR register must match.
0x4010914C B  REGISTER ADDR (rw): Self Address Register
0x4010914C C   FIELD 00w08 ADDR_VALUE (rw): Self Address for 9-Bit Mode This field contains the address that should be matched when UART9BITAMASK is FFh.
0x40109160 B  REGISTER CLKDIV2 (rw): Clock Divider
0x40109160 C   FIELD 00w03 CLKDIV2_RATIO: Selects divide ratio of module clock
0x40400000 A PERIPHERAL CPUSS
0x404010E0 B  REGISTER EVT_MODE (ro): Event Mode
0x404010E0 C   FIELD 00w02 EVT_MODE_INT_CFG (ro): Event line mode select
0x404010FC B  REGISTER DESC (ro): Module Description
0x404010FC C   FIELD 00w04 DESC_MINREV (ro): Minor rev of the IP
0x404010FC C   FIELD 04w04 DESC_MAJREV (ro): Major rev of the IP
0x404010FC C   FIELD 12w04 DESC_FEATUREVER (ro): Feature Set for the module *instance*
0x404010FC C   FIELD 16w16 DESC_MODULEID (ro): Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness.
0x40401100 B  REGISTER INT_GROUP0_IIDX (ro): Interrupt index
0x40401100 C   FIELD 00w08 INT_GROUP0_IIDX_STAT (ro): Interrupt index status
0x40401108 B  REGISTER INT_GROUP0_IMASK (ro): Interrupt mask
0x40401108 C   FIELD 00w08 INT_GROUP0_IMASK_INT (ro): Masks the corresponding interrupt
0x40401110 B  REGISTER INT_GROUP0_RIS (ro): Raw interrupt status
0x40401110 C   FIELD 00w08 INT_GROUP0_RIS_INT: Raw interrupt status for INT
0x40401118 B  REGISTER INT_GROUP0_MIS (ro): Masked interrupt status
0x40401118 C   FIELD 00w01 INT_GROUP0_MIS_INT: Masked interrupt status for INT0
0x40401120 B  REGISTER INT_GROUP0_ISET (wo): Interrupt set
0x40401120 C   FIELD 00w01 INT_GROUP0_ISET_INT: Sets INT in RIS register
0x40401128 B  REGISTER INT_GROUP0_ICLR (wo): Interrupt clear
0x40401128 C   FIELD 00w01 INT_GROUP0_ICLR_INT: Clears INT in RIS register
0x40401130 B  REGISTER INT_GROUP1_IIDX (ro): Interrupt index
0x40401130 C   FIELD 00w08 INT_GROUP1_IIDX_STAT (ro): Interrupt index status
0x40401138 B  REGISTER INT_GROUP1_IMASK (ro): Interrupt mask
0x40401138 C   FIELD 00w08 INT_GROUP1_IMASK_INT (ro): Masks the corresponding interrupt
0x40401140 B  REGISTER INT_GROUP1_RIS (ro): Raw interrupt status
0x40401140 C   FIELD 00w01 INT_GROUP1_RIS_INT: Raw interrupt status for INT
0x40401148 B  REGISTER INT_GROUP1_MIS (ro): Masked interrupt status
0x40401148 C   FIELD 00w01 INT_GROUP1_MIS_INT: Masked interrupt status for INT0
0x40401150 B  REGISTER INT_GROUP1_ISET (wo): Interrupt set
0x40401150 C   FIELD 00w01 INT_GROUP1_ISET_INT: Sets INT in RIS register
0x40401158 B  REGISTER INT_GROUP1_ICLR (wo): Interrupt clear
0x40401158 C   FIELD 00w01 INT_GROUP1_ICLR_INT: Clears INT in RIS register
0x40401300 B  REGISTER CTL (rw): Prefetch/Cache control
0x40401300 C   FIELD 00w01 CTL_PREFETCH (rw): Used to enable/disable instruction prefetch to Flash.
0x40401300 C   FIELD 01w01 CTL_ICACHE (rw): Used to enable/disable Instruction caching on flash access.
0x40401300 C   FIELD 02w01 CTL_LITEN (rw): Literal caching and prefetch enable. This bit is a subset of ICACHE/PREFETCH bit i.e. literal caching or literal prefetching will only happen if ICACHE or PREFETCH bits have been set respectively When enabled, the cache and prefetcher structures inside CPUSS will cache and prefetch literals When disabled, the cache and prefetcher structures inside CPUSS will not cache and prefetch literals
0x40424000 A PERIPHERAL WUC
0x40424400 B  REGISTER FSUB_0 (rw): Subscriber Port 0
0x40424400 C   FIELD 00w02 FSUB_0_CHANID: 0 = disconnected. 1-15 = connected to channelID = CHANID.
0x40424404 B  REGISTER FSUB_1 (rw): Subscriber Port 1
0x40424404 C   FIELD 00w02 FSUB_1_CHANID: 0 = disconnected. 1-15 = connected to channelID = CHANID.
0x40428000 A PERIPHERAL IOMUX
0x40428004 B  REGISTER PINCM[0] (rw): Pin Control Management Register in SECCFG region
0x40428004 C   FIELD 00w06 PINCM_PF (rw): P channel Function selection bits
0x40428004 C   FIELD 07w01 PINCM_PC (rw): Peripheral is Connected
0x40428004 C   FIELD 13w01 PINCM_WAKESTAT (ro): This has the IOPAD WAKEUP signal as status bit.
0x40428004 C   FIELD 16w01 PINCM_PIPD (rw): Pull Down control selection
0x40428004 C   FIELD 17w01 PINCM_PIPU (rw): Pull Up control selection
0x40428004 C   FIELD 18w01 PINCM_INENA (rw): Input Enable Control Selection
0x40428004 C   FIELD 19w01 PINCM_HYSTEN (rw): Hystersis Enable Control Selection
0x40428004 C   FIELD 20w01 PINCM_DRV (rw): Drive strength control selection, for HS IOCELL only
0x40428004 C   FIELD 25w01 PINCM_HIZ1 (rw): High output value will tri-state the output when this bit is enabled
0x40428004 C   FIELD 26w01 PINCM_INV (rw): Data inversion selection
0x40428004 C   FIELD 27w01 PINCM_WUEN (rw): Wakeup Enable bit
0x40428004 C   FIELD 28w01 PINCM_WCOMP (rw): Wakeup Compare Value bit
0x40428008 B  REGISTER PINCM[1] (rw): Pin Control Management Register in SECCFG region
0x40428008 C   FIELD 00w06 PINCM_PF (rw): P channel Function selection bits
0x40428008 C   FIELD 07w01 PINCM_PC (rw): Peripheral is Connected
0x40428008 C   FIELD 13w01 PINCM_WAKESTAT (ro): This has the IOPAD WAKEUP signal as status bit.
0x40428008 C   FIELD 16w01 PINCM_PIPD (rw): Pull Down control selection
0x40428008 C   FIELD 17w01 PINCM_PIPU (rw): Pull Up control selection
0x40428008 C   FIELD 18w01 PINCM_INENA (rw): Input Enable Control Selection
0x40428008 C   FIELD 19w01 PINCM_HYSTEN (rw): Hystersis Enable Control Selection
0x40428008 C   FIELD 20w01 PINCM_DRV (rw): Drive strength control selection, for HS IOCELL only
0x40428008 C   FIELD 25w01 PINCM_HIZ1 (rw): High output value will tri-state the output when this bit is enabled
0x40428008 C   FIELD 26w01 PINCM_INV (rw): Data inversion selection
0x40428008 C   FIELD 27w01 PINCM_WUEN (rw): Wakeup Enable bit
0x40428008 C   FIELD 28w01 PINCM_WCOMP (rw): Wakeup Compare Value bit
0x4042800C B  REGISTER PINCM[2] (rw): Pin Control Management Register in SECCFG region
0x4042800C C   FIELD 00w06 PINCM_PF (rw): P channel Function selection bits
0x4042800C C   FIELD 07w01 PINCM_PC (rw): Peripheral is Connected
0x4042800C C   FIELD 13w01 PINCM_WAKESTAT (ro): This has the IOPAD WAKEUP signal as status bit.
0x4042800C C   FIELD 16w01 PINCM_PIPD (rw): Pull Down control selection
0x4042800C C   FIELD 17w01 PINCM_PIPU (rw): Pull Up control selection
0x4042800C C   FIELD 18w01 PINCM_INENA (rw): Input Enable Control Selection
0x4042800C C   FIELD 19w01 PINCM_HYSTEN (rw): Hystersis Enable Control Selection
0x4042800C C   FIELD 20w01 PINCM_DRV (rw): Drive strength control selection, for HS IOCELL only
0x4042800C C   FIELD 25w01 PINCM_HIZ1 (rw): High output value will tri-state the output when this bit is enabled
0x4042800C C   FIELD 26w01 PINCM_INV (rw): Data inversion selection
0x4042800C C   FIELD 27w01 PINCM_WUEN (rw): Wakeup Enable bit
0x4042800C C   FIELD 28w01 PINCM_WCOMP (rw): Wakeup Compare Value bit
0x40428010 B  REGISTER PINCM[3] (rw): Pin Control Management Register in SECCFG region
0x40428010 C   FIELD 00w06 PINCM_PF (rw): P channel Function selection bits
0x40428010 C   FIELD 07w01 PINCM_PC (rw): Peripheral is Connected
0x40428010 C   FIELD 13w01 PINCM_WAKESTAT (ro): This has the IOPAD WAKEUP signal as status bit.
0x40428010 C   FIELD 16w01 PINCM_PIPD (rw): Pull Down control selection
0x40428010 C   FIELD 17w01 PINCM_PIPU (rw): Pull Up control selection
0x40428010 C   FIELD 18w01 PINCM_INENA (rw): Input Enable Control Selection
0x40428010 C   FIELD 19w01 PINCM_HYSTEN (rw): Hystersis Enable Control Selection
0x40428010 C   FIELD 20w01 PINCM_DRV (rw): Drive strength control selection, for HS IOCELL only
0x40428010 C   FIELD 25w01 PINCM_HIZ1 (rw): High output value will tri-state the output when this bit is enabled
0x40428010 C   FIELD 26w01 PINCM_INV (rw): Data inversion selection
0x40428010 C   FIELD 27w01 PINCM_WUEN (rw): Wakeup Enable bit
0x40428010 C   FIELD 28w01 PINCM_WCOMP (rw): Wakeup Compare Value bit
0x40428014 B  REGISTER PINCM[4] (rw): Pin Control Management Register in SECCFG region
0x40428014 C   FIELD 00w06 PINCM_PF (rw): P channel Function selection bits
0x40428014 C   FIELD 07w01 PINCM_PC (rw): Peripheral is Connected
0x40428014 C   FIELD 13w01 PINCM_WAKESTAT (ro): This has the IOPAD WAKEUP signal as status bit.
0x40428014 C   FIELD 16w01 PINCM_PIPD (rw): Pull Down control selection
0x40428014 C   FIELD 17w01 PINCM_PIPU (rw): Pull Up control selection
0x40428014 C   FIELD 18w01 PINCM_INENA (rw): Input Enable Control Selection
0x40428014 C   FIELD 19w01 PINCM_HYSTEN (rw): Hystersis Enable Control Selection
0x40428014 C   FIELD 20w01 PINCM_DRV (rw): Drive strength control selection, for HS IOCELL only
0x40428014 C   FIELD 25w01 PINCM_HIZ1 (rw): High output value will tri-state the output when this bit is enabled
0x40428014 C   FIELD 26w01 PINCM_INV (rw): Data inversion selection
0x40428014 C   FIELD 27w01 PINCM_WUEN (rw): Wakeup Enable bit
0x40428014 C   FIELD 28w01 PINCM_WCOMP (rw): Wakeup Compare Value bit
0x40428018 B  REGISTER PINCM[5] (rw): Pin Control Management Register in SECCFG region
0x40428018 C   FIELD 00w06 PINCM_PF (rw): P channel Function selection bits
0x40428018 C   FIELD 07w01 PINCM_PC (rw): Peripheral is Connected
0x40428018 C   FIELD 13w01 PINCM_WAKESTAT (ro): This has the IOPAD WAKEUP signal as status bit.
0x40428018 C   FIELD 16w01 PINCM_PIPD (rw): Pull Down control selection
0x40428018 C   FIELD 17w01 PINCM_PIPU (rw): Pull Up control selection
0x40428018 C   FIELD 18w01 PINCM_INENA (rw): Input Enable Control Selection
0x40428018 C   FIELD 19w01 PINCM_HYSTEN (rw): Hystersis Enable Control Selection
0x40428018 C   FIELD 20w01 PINCM_DRV (rw): Drive strength control selection, for HS IOCELL only
0x40428018 C   FIELD 25w01 PINCM_HIZ1 (rw): High output value will tri-state the output when this bit is enabled
0x40428018 C   FIELD 26w01 PINCM_INV (rw): Data inversion selection
0x40428018 C   FIELD 27w01 PINCM_WUEN (rw): Wakeup Enable bit
0x40428018 C   FIELD 28w01 PINCM_WCOMP (rw): Wakeup Compare Value bit
0x4042801C B  REGISTER PINCM[6] (rw): Pin Control Management Register in SECCFG region
0x4042801C C   FIELD 00w06 PINCM_PF (rw): P channel Function selection bits
0x4042801C C   FIELD 07w01 PINCM_PC (rw): Peripheral is Connected
0x4042801C C   FIELD 13w01 PINCM_WAKESTAT (ro): This has the IOPAD WAKEUP signal as status bit.
0x4042801C C   FIELD 16w01 PINCM_PIPD (rw): Pull Down control selection
0x4042801C C   FIELD 17w01 PINCM_PIPU (rw): Pull Up control selection
0x4042801C C   FIELD 18w01 PINCM_INENA (rw): Input Enable Control Selection
0x4042801C C   FIELD 19w01 PINCM_HYSTEN (rw): Hystersis Enable Control Selection
0x4042801C C   FIELD 20w01 PINCM_DRV (rw): Drive strength control selection, for HS IOCELL only
0x4042801C C   FIELD 25w01 PINCM_HIZ1 (rw): High output value will tri-state the output when this bit is enabled
0x4042801C C   FIELD 26w01 PINCM_INV (rw): Data inversion selection
0x4042801C C   FIELD 27w01 PINCM_WUEN (rw): Wakeup Enable bit
0x4042801C C   FIELD 28w01 PINCM_WCOMP (rw): Wakeup Compare Value bit
0x40428020 B  REGISTER PINCM[7] (rw): Pin Control Management Register in SECCFG region
0x40428020 C   FIELD 00w06 PINCM_PF (rw): P channel Function selection bits
0x40428020 C   FIELD 07w01 PINCM_PC (rw): Peripheral is Connected
0x40428020 C   FIELD 13w01 PINCM_WAKESTAT (ro): This has the IOPAD WAKEUP signal as status bit.
0x40428020 C   FIELD 16w01 PINCM_PIPD (rw): Pull Down control selection
0x40428020 C   FIELD 17w01 PINCM_PIPU (rw): Pull Up control selection
0x40428020 C   FIELD 18w01 PINCM_INENA (rw): Input Enable Control Selection
0x40428020 C   FIELD 19w01 PINCM_HYSTEN (rw): Hystersis Enable Control Selection
0x40428020 C   FIELD 20w01 PINCM_DRV (rw): Drive strength control selection, for HS IOCELL only
0x40428020 C   FIELD 25w01 PINCM_HIZ1 (rw): High output value will tri-state the output when this bit is enabled
0x40428020 C   FIELD 26w01 PINCM_INV (rw): Data inversion selection
0x40428020 C   FIELD 27w01 PINCM_WUEN (rw): Wakeup Enable bit
0x40428020 C   FIELD 28w01 PINCM_WCOMP (rw): Wakeup Compare Value bit
0x40428024 B  REGISTER PINCM[8] (rw): Pin Control Management Register in SECCFG region
0x40428024 C   FIELD 00w06 PINCM_PF (rw): P channel Function selection bits
0x40428024 C   FIELD 07w01 PINCM_PC (rw): Peripheral is Connected
0x40428024 C   FIELD 13w01 PINCM_WAKESTAT (ro): This has the IOPAD WAKEUP signal as status bit.
0x40428024 C   FIELD 16w01 PINCM_PIPD (rw): Pull Down control selection
0x40428024 C   FIELD 17w01 PINCM_PIPU (rw): Pull Up control selection
0x40428024 C   FIELD 18w01 PINCM_INENA (rw): Input Enable Control Selection
0x40428024 C   FIELD 19w01 PINCM_HYSTEN (rw): Hystersis Enable Control Selection
0x40428024 C   FIELD 20w01 PINCM_DRV (rw): Drive strength control selection, for HS IOCELL only
0x40428024 C   FIELD 25w01 PINCM_HIZ1 (rw): High output value will tri-state the output when this bit is enabled
0x40428024 C   FIELD 26w01 PINCM_INV (rw): Data inversion selection
0x40428024 C   FIELD 27w01 PINCM_WUEN (rw): Wakeup Enable bit
0x40428024 C   FIELD 28w01 PINCM_WCOMP (rw): Wakeup Compare Value bit
0x40428028 B  REGISTER PINCM[9] (rw): Pin Control Management Register in SECCFG region
0x40428028 C   FIELD 00w06 PINCM_PF (rw): P channel Function selection bits
0x40428028 C   FIELD 07w01 PINCM_PC (rw): Peripheral is Connected
0x40428028 C   FIELD 13w01 PINCM_WAKESTAT (ro): This has the IOPAD WAKEUP signal as status bit.
0x40428028 C   FIELD 16w01 PINCM_PIPD (rw): Pull Down control selection
0x40428028 C   FIELD 17w01 PINCM_PIPU (rw): Pull Up control selection
0x40428028 C   FIELD 18w01 PINCM_INENA (rw): Input Enable Control Selection
0x40428028 C   FIELD 19w01 PINCM_HYSTEN (rw): Hystersis Enable Control Selection
0x40428028 C   FIELD 20w01 PINCM_DRV (rw): Drive strength control selection, for HS IOCELL only
0x40428028 C   FIELD 25w01 PINCM_HIZ1 (rw): High output value will tri-state the output when this bit is enabled
0x40428028 C   FIELD 26w01 PINCM_INV (rw): Data inversion selection
0x40428028 C   FIELD 27w01 PINCM_WUEN (rw): Wakeup Enable bit
0x40428028 C   FIELD 28w01 PINCM_WCOMP (rw): Wakeup Compare Value bit
0x4042802C B  REGISTER PINCM[10] (rw): Pin Control Management Register in SECCFG region
0x4042802C C   FIELD 00w06 PINCM_PF (rw): P channel Function selection bits
0x4042802C C   FIELD 07w01 PINCM_PC (rw): Peripheral is Connected
0x4042802C C   FIELD 13w01 PINCM_WAKESTAT (ro): This has the IOPAD WAKEUP signal as status bit.
0x4042802C C   FIELD 16w01 PINCM_PIPD (rw): Pull Down control selection
0x4042802C C   FIELD 17w01 PINCM_PIPU (rw): Pull Up control selection
0x4042802C C   FIELD 18w01 PINCM_INENA (rw): Input Enable Control Selection
0x4042802C C   FIELD 19w01 PINCM_HYSTEN (rw): Hystersis Enable Control Selection
0x4042802C C   FIELD 20w01 PINCM_DRV (rw): Drive strength control selection, for HS IOCELL only
0x4042802C C   FIELD 25w01 PINCM_HIZ1 (rw): High output value will tri-state the output when this bit is enabled
0x4042802C C   FIELD 26w01 PINCM_INV (rw): Data inversion selection
0x4042802C C   FIELD 27w01 PINCM_WUEN (rw): Wakeup Enable bit
0x4042802C C   FIELD 28w01 PINCM_WCOMP (rw): Wakeup Compare Value bit
0x40428030 B  REGISTER PINCM[11] (rw): Pin Control Management Register in SECCFG region
0x40428030 C   FIELD 00w06 PINCM_PF (rw): P channel Function selection bits
0x40428030 C   FIELD 07w01 PINCM_PC (rw): Peripheral is Connected
0x40428030 C   FIELD 13w01 PINCM_WAKESTAT (ro): This has the IOPAD WAKEUP signal as status bit.
0x40428030 C   FIELD 16w01 PINCM_PIPD (rw): Pull Down control selection
0x40428030 C   FIELD 17w01 PINCM_PIPU (rw): Pull Up control selection
0x40428030 C   FIELD 18w01 PINCM_INENA (rw): Input Enable Control Selection
0x40428030 C   FIELD 19w01 PINCM_HYSTEN (rw): Hystersis Enable Control Selection
0x40428030 C   FIELD 20w01 PINCM_DRV (rw): Drive strength control selection, for HS IOCELL only
0x40428030 C   FIELD 25w01 PINCM_HIZ1 (rw): High output value will tri-state the output when this bit is enabled
0x40428030 C   FIELD 26w01 PINCM_INV (rw): Data inversion selection
0x40428030 C   FIELD 27w01 PINCM_WUEN (rw): Wakeup Enable bit
0x40428030 C   FIELD 28w01 PINCM_WCOMP (rw): Wakeup Compare Value bit
0x40428034 B  REGISTER PINCM[12] (rw): Pin Control Management Register in SECCFG region
0x40428034 C   FIELD 00w06 PINCM_PF (rw): P channel Function selection bits
0x40428034 C   FIELD 07w01 PINCM_PC (rw): Peripheral is Connected
0x40428034 C   FIELD 13w01 PINCM_WAKESTAT (ro): This has the IOPAD WAKEUP signal as status bit.
0x40428034 C   FIELD 16w01 PINCM_PIPD (rw): Pull Down control selection
0x40428034 C   FIELD 17w01 PINCM_PIPU (rw): Pull Up control selection
0x40428034 C   FIELD 18w01 PINCM_INENA (rw): Input Enable Control Selection
0x40428034 C   FIELD 19w01 PINCM_HYSTEN (rw): Hystersis Enable Control Selection
0x40428034 C   FIELD 20w01 PINCM_DRV (rw): Drive strength control selection, for HS IOCELL only
0x40428034 C   FIELD 25w01 PINCM_HIZ1 (rw): High output value will tri-state the output when this bit is enabled
0x40428034 C   FIELD 26w01 PINCM_INV (rw): Data inversion selection
0x40428034 C   FIELD 27w01 PINCM_WUEN (rw): Wakeup Enable bit
0x40428034 C   FIELD 28w01 PINCM_WCOMP (rw): Wakeup Compare Value bit
0x40428038 B  REGISTER PINCM[13] (rw): Pin Control Management Register in SECCFG region
0x40428038 C   FIELD 00w06 PINCM_PF (rw): P channel Function selection bits
0x40428038 C   FIELD 07w01 PINCM_PC (rw): Peripheral is Connected
0x40428038 C   FIELD 13w01 PINCM_WAKESTAT (ro): This has the IOPAD WAKEUP signal as status bit.
0x40428038 C   FIELD 16w01 PINCM_PIPD (rw): Pull Down control selection
0x40428038 C   FIELD 17w01 PINCM_PIPU (rw): Pull Up control selection
0x40428038 C   FIELD 18w01 PINCM_INENA (rw): Input Enable Control Selection
0x40428038 C   FIELD 19w01 PINCM_HYSTEN (rw): Hystersis Enable Control Selection
0x40428038 C   FIELD 20w01 PINCM_DRV (rw): Drive strength control selection, for HS IOCELL only
0x40428038 C   FIELD 25w01 PINCM_HIZ1 (rw): High output value will tri-state the output when this bit is enabled
0x40428038 C   FIELD 26w01 PINCM_INV (rw): Data inversion selection
0x40428038 C   FIELD 27w01 PINCM_WUEN (rw): Wakeup Enable bit
0x40428038 C   FIELD 28w01 PINCM_WCOMP (rw): Wakeup Compare Value bit
0x4042803C B  REGISTER PINCM[14] (rw): Pin Control Management Register in SECCFG region
0x4042803C C   FIELD 00w06 PINCM_PF (rw): P channel Function selection bits
0x4042803C C   FIELD 07w01 PINCM_PC (rw): Peripheral is Connected
0x4042803C C   FIELD 13w01 PINCM_WAKESTAT (ro): This has the IOPAD WAKEUP signal as status bit.
0x4042803C C   FIELD 16w01 PINCM_PIPD (rw): Pull Down control selection
0x4042803C C   FIELD 17w01 PINCM_PIPU (rw): Pull Up control selection
0x4042803C C   FIELD 18w01 PINCM_INENA (rw): Input Enable Control Selection
0x4042803C C   FIELD 19w01 PINCM_HYSTEN (rw): Hystersis Enable Control Selection
0x4042803C C   FIELD 20w01 PINCM_DRV (rw): Drive strength control selection, for HS IOCELL only
0x4042803C C   FIELD 25w01 PINCM_HIZ1 (rw): High output value will tri-state the output when this bit is enabled
0x4042803C C   FIELD 26w01 PINCM_INV (rw): Data inversion selection
0x4042803C C   FIELD 27w01 PINCM_WUEN (rw): Wakeup Enable bit
0x4042803C C   FIELD 28w01 PINCM_WCOMP (rw): Wakeup Compare Value bit
0x40428040 B  REGISTER PINCM[15] (rw): Pin Control Management Register in SECCFG region
0x40428040 C   FIELD 00w06 PINCM_PF (rw): P channel Function selection bits
0x40428040 C   FIELD 07w01 PINCM_PC (rw): Peripheral is Connected
0x40428040 C   FIELD 13w01 PINCM_WAKESTAT (ro): This has the IOPAD WAKEUP signal as status bit.
0x40428040 C   FIELD 16w01 PINCM_PIPD (rw): Pull Down control selection
0x40428040 C   FIELD 17w01 PINCM_PIPU (rw): Pull Up control selection
0x40428040 C   FIELD 18w01 PINCM_INENA (rw): Input Enable Control Selection
0x40428040 C   FIELD 19w01 PINCM_HYSTEN (rw): Hystersis Enable Control Selection
0x40428040 C   FIELD 20w01 PINCM_DRV (rw): Drive strength control selection, for HS IOCELL only
0x40428040 C   FIELD 25w01 PINCM_HIZ1 (rw): High output value will tri-state the output when this bit is enabled
0x40428040 C   FIELD 26w01 PINCM_INV (rw): Data inversion selection
0x40428040 C   FIELD 27w01 PINCM_WUEN (rw): Wakeup Enable bit
0x40428040 C   FIELD 28w01 PINCM_WCOMP (rw): Wakeup Compare Value bit
0x40428044 B  REGISTER PINCM[16] (rw): Pin Control Management Register in SECCFG region
0x40428044 C   FIELD 00w06 PINCM_PF (rw): P channel Function selection bits
0x40428044 C   FIELD 07w01 PINCM_PC (rw): Peripheral is Connected
0x40428044 C   FIELD 13w01 PINCM_WAKESTAT (ro): This has the IOPAD WAKEUP signal as status bit.
0x40428044 C   FIELD 16w01 PINCM_PIPD (rw): Pull Down control selection
0x40428044 C   FIELD 17w01 PINCM_PIPU (rw): Pull Up control selection
0x40428044 C   FIELD 18w01 PINCM_INENA (rw): Input Enable Control Selection
0x40428044 C   FIELD 19w01 PINCM_HYSTEN (rw): Hystersis Enable Control Selection
0x40428044 C   FIELD 20w01 PINCM_DRV (rw): Drive strength control selection, for HS IOCELL only
0x40428044 C   FIELD 25w01 PINCM_HIZ1 (rw): High output value will tri-state the output when this bit is enabled
0x40428044 C   FIELD 26w01 PINCM_INV (rw): Data inversion selection
0x40428044 C   FIELD 27w01 PINCM_WUEN (rw): Wakeup Enable bit
0x40428044 C   FIELD 28w01 PINCM_WCOMP (rw): Wakeup Compare Value bit
0x40428048 B  REGISTER PINCM[17] (rw): Pin Control Management Register in SECCFG region
0x40428048 C   FIELD 00w06 PINCM_PF (rw): P channel Function selection bits
0x40428048 C   FIELD 07w01 PINCM_PC (rw): Peripheral is Connected
0x40428048 C   FIELD 13w01 PINCM_WAKESTAT (ro): This has the IOPAD WAKEUP signal as status bit.
0x40428048 C   FIELD 16w01 PINCM_PIPD (rw): Pull Down control selection
0x40428048 C   FIELD 17w01 PINCM_PIPU (rw): Pull Up control selection
0x40428048 C   FIELD 18w01 PINCM_INENA (rw): Input Enable Control Selection
0x40428048 C   FIELD 19w01 PINCM_HYSTEN (rw): Hystersis Enable Control Selection
0x40428048 C   FIELD 20w01 PINCM_DRV (rw): Drive strength control selection, for HS IOCELL only
0x40428048 C   FIELD 25w01 PINCM_HIZ1 (rw): High output value will tri-state the output when this bit is enabled
0x40428048 C   FIELD 26w01 PINCM_INV (rw): Data inversion selection
0x40428048 C   FIELD 27w01 PINCM_WUEN (rw): Wakeup Enable bit
0x40428048 C   FIELD 28w01 PINCM_WCOMP (rw): Wakeup Compare Value bit
0x4042804C B  REGISTER PINCM[18] (rw): Pin Control Management Register in SECCFG region
0x4042804C C   FIELD 00w06 PINCM_PF (rw): P channel Function selection bits
0x4042804C C   FIELD 07w01 PINCM_PC (rw): Peripheral is Connected
0x4042804C C   FIELD 13w01 PINCM_WAKESTAT (ro): This has the IOPAD WAKEUP signal as status bit.
0x4042804C C   FIELD 16w01 PINCM_PIPD (rw): Pull Down control selection
0x4042804C C   FIELD 17w01 PINCM_PIPU (rw): Pull Up control selection
0x4042804C C   FIELD 18w01 PINCM_INENA (rw): Input Enable Control Selection
0x4042804C C   FIELD 19w01 PINCM_HYSTEN (rw): Hystersis Enable Control Selection
0x4042804C C   FIELD 20w01 PINCM_DRV (rw): Drive strength control selection, for HS IOCELL only
0x4042804C C   FIELD 25w01 PINCM_HIZ1 (rw): High output value will tri-state the output when this bit is enabled
0x4042804C C   FIELD 26w01 PINCM_INV (rw): Data inversion selection
0x4042804C C   FIELD 27w01 PINCM_WUEN (rw): Wakeup Enable bit
0x4042804C C   FIELD 28w01 PINCM_WCOMP (rw): Wakeup Compare Value bit
0x40428050 B  REGISTER PINCM[19] (rw): Pin Control Management Register in SECCFG region
0x40428050 C   FIELD 00w06 PINCM_PF (rw): P channel Function selection bits
0x40428050 C   FIELD 07w01 PINCM_PC (rw): Peripheral is Connected
0x40428050 C   FIELD 13w01 PINCM_WAKESTAT (ro): This has the IOPAD WAKEUP signal as status bit.
0x40428050 C   FIELD 16w01 PINCM_PIPD (rw): Pull Down control selection
0x40428050 C   FIELD 17w01 PINCM_PIPU (rw): Pull Up control selection
0x40428050 C   FIELD 18w01 PINCM_INENA (rw): Input Enable Control Selection
0x40428050 C   FIELD 19w01 PINCM_HYSTEN (rw): Hystersis Enable Control Selection
0x40428050 C   FIELD 20w01 PINCM_DRV (rw): Drive strength control selection, for HS IOCELL only
0x40428050 C   FIELD 25w01 PINCM_HIZ1 (rw): High output value will tri-state the output when this bit is enabled
0x40428050 C   FIELD 26w01 PINCM_INV (rw): Data inversion selection
0x40428050 C   FIELD 27w01 PINCM_WUEN (rw): Wakeup Enable bit
0x40428050 C   FIELD 28w01 PINCM_WCOMP (rw): Wakeup Compare Value bit
0x40428054 B  REGISTER PINCM[20] (rw): Pin Control Management Register in SECCFG region
0x40428054 C   FIELD 00w06 PINCM_PF (rw): P channel Function selection bits
0x40428054 C   FIELD 07w01 PINCM_PC (rw): Peripheral is Connected
0x40428054 C   FIELD 13w01 PINCM_WAKESTAT (ro): This has the IOPAD WAKEUP signal as status bit.
0x40428054 C   FIELD 16w01 PINCM_PIPD (rw): Pull Down control selection
0x40428054 C   FIELD 17w01 PINCM_PIPU (rw): Pull Up control selection
0x40428054 C   FIELD 18w01 PINCM_INENA (rw): Input Enable Control Selection
0x40428054 C   FIELD 19w01 PINCM_HYSTEN (rw): Hystersis Enable Control Selection
0x40428054 C   FIELD 20w01 PINCM_DRV (rw): Drive strength control selection, for HS IOCELL only
0x40428054 C   FIELD 25w01 PINCM_HIZ1 (rw): High output value will tri-state the output when this bit is enabled
0x40428054 C   FIELD 26w01 PINCM_INV (rw): Data inversion selection
0x40428054 C   FIELD 27w01 PINCM_WUEN (rw): Wakeup Enable bit
0x40428054 C   FIELD 28w01 PINCM_WCOMP (rw): Wakeup Compare Value bit
0x40428058 B  REGISTER PINCM[21] (rw): Pin Control Management Register in SECCFG region
0x40428058 C   FIELD 00w06 PINCM_PF (rw): P channel Function selection bits
0x40428058 C   FIELD 07w01 PINCM_PC (rw): Peripheral is Connected
0x40428058 C   FIELD 13w01 PINCM_WAKESTAT (ro): This has the IOPAD WAKEUP signal as status bit.
0x40428058 C   FIELD 16w01 PINCM_PIPD (rw): Pull Down control selection
0x40428058 C   FIELD 17w01 PINCM_PIPU (rw): Pull Up control selection
0x40428058 C   FIELD 18w01 PINCM_INENA (rw): Input Enable Control Selection
0x40428058 C   FIELD 19w01 PINCM_HYSTEN (rw): Hystersis Enable Control Selection
0x40428058 C   FIELD 20w01 PINCM_DRV (rw): Drive strength control selection, for HS IOCELL only
0x40428058 C   FIELD 25w01 PINCM_HIZ1 (rw): High output value will tri-state the output when this bit is enabled
0x40428058 C   FIELD 26w01 PINCM_INV (rw): Data inversion selection
0x40428058 C   FIELD 27w01 PINCM_WUEN (rw): Wakeup Enable bit
0x40428058 C   FIELD 28w01 PINCM_WCOMP (rw): Wakeup Compare Value bit
0x4042805C B  REGISTER PINCM[22] (rw): Pin Control Management Register in SECCFG region
0x4042805C C   FIELD 00w06 PINCM_PF (rw): P channel Function selection bits
0x4042805C C   FIELD 07w01 PINCM_PC (rw): Peripheral is Connected
0x4042805C C   FIELD 13w01 PINCM_WAKESTAT (ro): This has the IOPAD WAKEUP signal as status bit.
0x4042805C C   FIELD 16w01 PINCM_PIPD (rw): Pull Down control selection
0x4042805C C   FIELD 17w01 PINCM_PIPU (rw): Pull Up control selection
0x4042805C C   FIELD 18w01 PINCM_INENA (rw): Input Enable Control Selection
0x4042805C C   FIELD 19w01 PINCM_HYSTEN (rw): Hystersis Enable Control Selection
0x4042805C C   FIELD 20w01 PINCM_DRV (rw): Drive strength control selection, for HS IOCELL only
0x4042805C C   FIELD 25w01 PINCM_HIZ1 (rw): High output value will tri-state the output when this bit is enabled
0x4042805C C   FIELD 26w01 PINCM_INV (rw): Data inversion selection
0x4042805C C   FIELD 27w01 PINCM_WUEN (rw): Wakeup Enable bit
0x4042805C C   FIELD 28w01 PINCM_WCOMP (rw): Wakeup Compare Value bit
0x40428060 B  REGISTER PINCM[23] (rw): Pin Control Management Register in SECCFG region
0x40428060 C   FIELD 00w06 PINCM_PF (rw): P channel Function selection bits
0x40428060 C   FIELD 07w01 PINCM_PC (rw): Peripheral is Connected
0x40428060 C   FIELD 13w01 PINCM_WAKESTAT (ro): This has the IOPAD WAKEUP signal as status bit.
0x40428060 C   FIELD 16w01 PINCM_PIPD (rw): Pull Down control selection
0x40428060 C   FIELD 17w01 PINCM_PIPU (rw): Pull Up control selection
0x40428060 C   FIELD 18w01 PINCM_INENA (rw): Input Enable Control Selection
0x40428060 C   FIELD 19w01 PINCM_HYSTEN (rw): Hystersis Enable Control Selection
0x40428060 C   FIELD 20w01 PINCM_DRV (rw): Drive strength control selection, for HS IOCELL only
0x40428060 C   FIELD 25w01 PINCM_HIZ1 (rw): High output value will tri-state the output when this bit is enabled
0x40428060 C   FIELD 26w01 PINCM_INV (rw): Data inversion selection
0x40428060 C   FIELD 27w01 PINCM_WUEN (rw): Wakeup Enable bit
0x40428060 C   FIELD 28w01 PINCM_WCOMP (rw): Wakeup Compare Value bit
0x40428064 B  REGISTER PINCM[24] (rw): Pin Control Management Register in SECCFG region
0x40428064 C   FIELD 00w06 PINCM_PF (rw): P channel Function selection bits
0x40428064 C   FIELD 07w01 PINCM_PC (rw): Peripheral is Connected
0x40428064 C   FIELD 13w01 PINCM_WAKESTAT (ro): This has the IOPAD WAKEUP signal as status bit.
0x40428064 C   FIELD 16w01 PINCM_PIPD (rw): Pull Down control selection
0x40428064 C   FIELD 17w01 PINCM_PIPU (rw): Pull Up control selection
0x40428064 C   FIELD 18w01 PINCM_INENA (rw): Input Enable Control Selection
0x40428064 C   FIELD 19w01 PINCM_HYSTEN (rw): Hystersis Enable Control Selection
0x40428064 C   FIELD 20w01 PINCM_DRV (rw): Drive strength control selection, for HS IOCELL only
0x40428064 C   FIELD 25w01 PINCM_HIZ1 (rw): High output value will tri-state the output when this bit is enabled
0x40428064 C   FIELD 26w01 PINCM_INV (rw): Data inversion selection
0x40428064 C   FIELD 27w01 PINCM_WUEN (rw): Wakeup Enable bit
0x40428064 C   FIELD 28w01 PINCM_WCOMP (rw): Wakeup Compare Value bit
0x40428068 B  REGISTER PINCM[25] (rw): Pin Control Management Register in SECCFG region
0x40428068 C   FIELD 00w06 PINCM_PF (rw): P channel Function selection bits
0x40428068 C   FIELD 07w01 PINCM_PC (rw): Peripheral is Connected
0x40428068 C   FIELD 13w01 PINCM_WAKESTAT (ro): This has the IOPAD WAKEUP signal as status bit.
0x40428068 C   FIELD 16w01 PINCM_PIPD (rw): Pull Down control selection
0x40428068 C   FIELD 17w01 PINCM_PIPU (rw): Pull Up control selection
0x40428068 C   FIELD 18w01 PINCM_INENA (rw): Input Enable Control Selection
0x40428068 C   FIELD 19w01 PINCM_HYSTEN (rw): Hystersis Enable Control Selection
0x40428068 C   FIELD 20w01 PINCM_DRV (rw): Drive strength control selection, for HS IOCELL only
0x40428068 C   FIELD 25w01 PINCM_HIZ1 (rw): High output value will tri-state the output when this bit is enabled
0x40428068 C   FIELD 26w01 PINCM_INV (rw): Data inversion selection
0x40428068 C   FIELD 27w01 PINCM_WUEN (rw): Wakeup Enable bit
0x40428068 C   FIELD 28w01 PINCM_WCOMP (rw): Wakeup Compare Value bit
0x4042806C B  REGISTER PINCM[26] (rw): Pin Control Management Register in SECCFG region
0x4042806C C   FIELD 00w06 PINCM_PF (rw): P channel Function selection bits
0x4042806C C   FIELD 07w01 PINCM_PC (rw): Peripheral is Connected
0x4042806C C   FIELD 13w01 PINCM_WAKESTAT (ro): This has the IOPAD WAKEUP signal as status bit.
0x4042806C C   FIELD 16w01 PINCM_PIPD (rw): Pull Down control selection
0x4042806C C   FIELD 17w01 PINCM_PIPU (rw): Pull Up control selection
0x4042806C C   FIELD 18w01 PINCM_INENA (rw): Input Enable Control Selection
0x4042806C C   FIELD 19w01 PINCM_HYSTEN (rw): Hystersis Enable Control Selection
0x4042806C C   FIELD 20w01 PINCM_DRV (rw): Drive strength control selection, for HS IOCELL only
0x4042806C C   FIELD 25w01 PINCM_HIZ1 (rw): High output value will tri-state the output when this bit is enabled
0x4042806C C   FIELD 26w01 PINCM_INV (rw): Data inversion selection
0x4042806C C   FIELD 27w01 PINCM_WUEN (rw): Wakeup Enable bit
0x4042806C C   FIELD 28w01 PINCM_WCOMP (rw): Wakeup Compare Value bit
0x40428070 B  REGISTER PINCM[27] (rw): Pin Control Management Register in SECCFG region
0x40428070 C   FIELD 00w06 PINCM_PF (rw): P channel Function selection bits
0x40428070 C   FIELD 07w01 PINCM_PC (rw): Peripheral is Connected
0x40428070 C   FIELD 13w01 PINCM_WAKESTAT (ro): This has the IOPAD WAKEUP signal as status bit.
0x40428070 C   FIELD 16w01 PINCM_PIPD (rw): Pull Down control selection
0x40428070 C   FIELD 17w01 PINCM_PIPU (rw): Pull Up control selection
0x40428070 C   FIELD 18w01 PINCM_INENA (rw): Input Enable Control Selection
0x40428070 C   FIELD 19w01 PINCM_HYSTEN (rw): Hystersis Enable Control Selection
0x40428070 C   FIELD 20w01 PINCM_DRV (rw): Drive strength control selection, for HS IOCELL only
0x40428070 C   FIELD 25w01 PINCM_HIZ1 (rw): High output value will tri-state the output when this bit is enabled
0x40428070 C   FIELD 26w01 PINCM_INV (rw): Data inversion selection
0x40428070 C   FIELD 27w01 PINCM_WUEN (rw): Wakeup Enable bit
0x40428070 C   FIELD 28w01 PINCM_WCOMP (rw): Wakeup Compare Value bit
0x40428074 B  REGISTER PINCM[28] (rw): Pin Control Management Register in SECCFG region
0x40428074 C   FIELD 00w06 PINCM_PF (rw): P channel Function selection bits
0x40428074 C   FIELD 07w01 PINCM_PC (rw): Peripheral is Connected
0x40428074 C   FIELD 13w01 PINCM_WAKESTAT (ro): This has the IOPAD WAKEUP signal as status bit.
0x40428074 C   FIELD 16w01 PINCM_PIPD (rw): Pull Down control selection
0x40428074 C   FIELD 17w01 PINCM_PIPU (rw): Pull Up control selection
0x40428074 C   FIELD 18w01 PINCM_INENA (rw): Input Enable Control Selection
0x40428074 C   FIELD 19w01 PINCM_HYSTEN (rw): Hystersis Enable Control Selection
0x40428074 C   FIELD 20w01 PINCM_DRV (rw): Drive strength control selection, for HS IOCELL only
0x40428074 C   FIELD 25w01 PINCM_HIZ1 (rw): High output value will tri-state the output when this bit is enabled
0x40428074 C   FIELD 26w01 PINCM_INV (rw): Data inversion selection
0x40428074 C   FIELD 27w01 PINCM_WUEN (rw): Wakeup Enable bit
0x40428074 C   FIELD 28w01 PINCM_WCOMP (rw): Wakeup Compare Value bit
0x40428078 B  REGISTER PINCM[29] (rw): Pin Control Management Register in SECCFG region
0x40428078 C   FIELD 00w06 PINCM_PF (rw): P channel Function selection bits
0x40428078 C   FIELD 07w01 PINCM_PC (rw): Peripheral is Connected
0x40428078 C   FIELD 13w01 PINCM_WAKESTAT (ro): This has the IOPAD WAKEUP signal as status bit.
0x40428078 C   FIELD 16w01 PINCM_PIPD (rw): Pull Down control selection
0x40428078 C   FIELD 17w01 PINCM_PIPU (rw): Pull Up control selection
0x40428078 C   FIELD 18w01 PINCM_INENA (rw): Input Enable Control Selection
0x40428078 C   FIELD 19w01 PINCM_HYSTEN (rw): Hystersis Enable Control Selection
0x40428078 C   FIELD 20w01 PINCM_DRV (rw): Drive strength control selection, for HS IOCELL only
0x40428078 C   FIELD 25w01 PINCM_HIZ1 (rw): High output value will tri-state the output when this bit is enabled
0x40428078 C   FIELD 26w01 PINCM_INV (rw): Data inversion selection
0x40428078 C   FIELD 27w01 PINCM_WUEN (rw): Wakeup Enable bit
0x40428078 C   FIELD 28w01 PINCM_WCOMP (rw): Wakeup Compare Value bit
0x4042807C B  REGISTER PINCM[30] (rw): Pin Control Management Register in SECCFG region
0x4042807C C   FIELD 00w06 PINCM_PF (rw): P channel Function selection bits
0x4042807C C   FIELD 07w01 PINCM_PC (rw): Peripheral is Connected
0x4042807C C   FIELD 13w01 PINCM_WAKESTAT (ro): This has the IOPAD WAKEUP signal as status bit.
0x4042807C C   FIELD 16w01 PINCM_PIPD (rw): Pull Down control selection
0x4042807C C   FIELD 17w01 PINCM_PIPU (rw): Pull Up control selection
0x4042807C C   FIELD 18w01 PINCM_INENA (rw): Input Enable Control Selection
0x4042807C C   FIELD 19w01 PINCM_HYSTEN (rw): Hystersis Enable Control Selection
0x4042807C C   FIELD 20w01 PINCM_DRV (rw): Drive strength control selection, for HS IOCELL only
0x4042807C C   FIELD 25w01 PINCM_HIZ1 (rw): High output value will tri-state the output when this bit is enabled
0x4042807C C   FIELD 26w01 PINCM_INV (rw): Data inversion selection
0x4042807C C   FIELD 27w01 PINCM_WUEN (rw): Wakeup Enable bit
0x4042807C C   FIELD 28w01 PINCM_WCOMP (rw): Wakeup Compare Value bit
0x40428080 B  REGISTER PINCM[31] (rw): Pin Control Management Register in SECCFG region
0x40428080 C   FIELD 00w06 PINCM_PF (rw): P channel Function selection bits
0x40428080 C   FIELD 07w01 PINCM_PC (rw): Peripheral is Connected
0x40428080 C   FIELD 13w01 PINCM_WAKESTAT (ro): This has the IOPAD WAKEUP signal as status bit.
0x40428080 C   FIELD 16w01 PINCM_PIPD (rw): Pull Down control selection
0x40428080 C   FIELD 17w01 PINCM_PIPU (rw): Pull Up control selection
0x40428080 C   FIELD 18w01 PINCM_INENA (rw): Input Enable Control Selection
0x40428080 C   FIELD 19w01 PINCM_HYSTEN (rw): Hystersis Enable Control Selection
0x40428080 C   FIELD 20w01 PINCM_DRV (rw): Drive strength control selection, for HS IOCELL only
0x40428080 C   FIELD 25w01 PINCM_HIZ1 (rw): High output value will tri-state the output when this bit is enabled
0x40428080 C   FIELD 26w01 PINCM_INV (rw): Data inversion selection
0x40428080 C   FIELD 27w01 PINCM_WUEN (rw): Wakeup Enable bit
0x40428080 C   FIELD 28w01 PINCM_WCOMP (rw): Wakeup Compare Value bit
0x40428084 B  REGISTER PINCM[32] (rw): Pin Control Management Register in SECCFG region
0x40428084 C   FIELD 00w06 PINCM_PF (rw): P channel Function selection bits
0x40428084 C   FIELD 07w01 PINCM_PC (rw): Peripheral is Connected
0x40428084 C   FIELD 13w01 PINCM_WAKESTAT (ro): This has the IOPAD WAKEUP signal as status bit.
0x40428084 C   FIELD 16w01 PINCM_PIPD (rw): Pull Down control selection
0x40428084 C   FIELD 17w01 PINCM_PIPU (rw): Pull Up control selection
0x40428084 C   FIELD 18w01 PINCM_INENA (rw): Input Enable Control Selection
0x40428084 C   FIELD 19w01 PINCM_HYSTEN (rw): Hystersis Enable Control Selection
0x40428084 C   FIELD 20w01 PINCM_DRV (rw): Drive strength control selection, for HS IOCELL only
0x40428084 C   FIELD 25w01 PINCM_HIZ1 (rw): High output value will tri-state the output when this bit is enabled
0x40428084 C   FIELD 26w01 PINCM_INV (rw): Data inversion selection
0x40428084 C   FIELD 27w01 PINCM_WUEN (rw): Wakeup Enable bit
0x40428084 C   FIELD 28w01 PINCM_WCOMP (rw): Wakeup Compare Value bit
0x40428088 B  REGISTER PINCM[33] (rw): Pin Control Management Register in SECCFG region
0x40428088 C   FIELD 00w06 PINCM_PF (rw): P channel Function selection bits
0x40428088 C   FIELD 07w01 PINCM_PC (rw): Peripheral is Connected
0x40428088 C   FIELD 13w01 PINCM_WAKESTAT (ro): This has the IOPAD WAKEUP signal as status bit.
0x40428088 C   FIELD 16w01 PINCM_PIPD (rw): Pull Down control selection
0x40428088 C   FIELD 17w01 PINCM_PIPU (rw): Pull Up control selection
0x40428088 C   FIELD 18w01 PINCM_INENA (rw): Input Enable Control Selection
0x40428088 C   FIELD 19w01 PINCM_HYSTEN (rw): Hystersis Enable Control Selection
0x40428088 C   FIELD 20w01 PINCM_DRV (rw): Drive strength control selection, for HS IOCELL only
0x40428088 C   FIELD 25w01 PINCM_HIZ1 (rw): High output value will tri-state the output when this bit is enabled
0x40428088 C   FIELD 26w01 PINCM_INV (rw): Data inversion selection
0x40428088 C   FIELD 27w01 PINCM_WUEN (rw): Wakeup Enable bit
0x40428088 C   FIELD 28w01 PINCM_WCOMP (rw): Wakeup Compare Value bit
0x4042808C B  REGISTER PINCM[34] (rw): Pin Control Management Register in SECCFG region
0x4042808C C   FIELD 00w06 PINCM_PF (rw): P channel Function selection bits
0x4042808C C   FIELD 07w01 PINCM_PC (rw): Peripheral is Connected
0x4042808C C   FIELD 13w01 PINCM_WAKESTAT (ro): This has the IOPAD WAKEUP signal as status bit.
0x4042808C C   FIELD 16w01 PINCM_PIPD (rw): Pull Down control selection
0x4042808C C   FIELD 17w01 PINCM_PIPU (rw): Pull Up control selection
0x4042808C C   FIELD 18w01 PINCM_INENA (rw): Input Enable Control Selection
0x4042808C C   FIELD 19w01 PINCM_HYSTEN (rw): Hystersis Enable Control Selection
0x4042808C C   FIELD 20w01 PINCM_DRV (rw): Drive strength control selection, for HS IOCELL only
0x4042808C C   FIELD 25w01 PINCM_HIZ1 (rw): High output value will tri-state the output when this bit is enabled
0x4042808C C   FIELD 26w01 PINCM_INV (rw): Data inversion selection
0x4042808C C   FIELD 27w01 PINCM_WUEN (rw): Wakeup Enable bit
0x4042808C C   FIELD 28w01 PINCM_WCOMP (rw): Wakeup Compare Value bit
0x40428090 B  REGISTER PINCM[35] (rw): Pin Control Management Register in SECCFG region
0x40428090 C   FIELD 00w06 PINCM_PF (rw): P channel Function selection bits
0x40428090 C   FIELD 07w01 PINCM_PC (rw): Peripheral is Connected
0x40428090 C   FIELD 13w01 PINCM_WAKESTAT (ro): This has the IOPAD WAKEUP signal as status bit.
0x40428090 C   FIELD 16w01 PINCM_PIPD (rw): Pull Down control selection
0x40428090 C   FIELD 17w01 PINCM_PIPU (rw): Pull Up control selection
0x40428090 C   FIELD 18w01 PINCM_INENA (rw): Input Enable Control Selection
0x40428090 C   FIELD 19w01 PINCM_HYSTEN (rw): Hystersis Enable Control Selection
0x40428090 C   FIELD 20w01 PINCM_DRV (rw): Drive strength control selection, for HS IOCELL only
0x40428090 C   FIELD 25w01 PINCM_HIZ1 (rw): High output value will tri-state the output when this bit is enabled
0x40428090 C   FIELD 26w01 PINCM_INV (rw): Data inversion selection
0x40428090 C   FIELD 27w01 PINCM_WUEN (rw): Wakeup Enable bit
0x40428090 C   FIELD 28w01 PINCM_WCOMP (rw): Wakeup Compare Value bit
0x40428094 B  REGISTER PINCM[36] (rw): Pin Control Management Register in SECCFG region
0x40428094 C   FIELD 00w06 PINCM_PF (rw): P channel Function selection bits
0x40428094 C   FIELD 07w01 PINCM_PC (rw): Peripheral is Connected
0x40428094 C   FIELD 13w01 PINCM_WAKESTAT (ro): This has the IOPAD WAKEUP signal as status bit.
0x40428094 C   FIELD 16w01 PINCM_PIPD (rw): Pull Down control selection
0x40428094 C   FIELD 17w01 PINCM_PIPU (rw): Pull Up control selection
0x40428094 C   FIELD 18w01 PINCM_INENA (rw): Input Enable Control Selection
0x40428094 C   FIELD 19w01 PINCM_HYSTEN (rw): Hystersis Enable Control Selection
0x40428094 C   FIELD 20w01 PINCM_DRV (rw): Drive strength control selection, for HS IOCELL only
0x40428094 C   FIELD 25w01 PINCM_HIZ1 (rw): High output value will tri-state the output when this bit is enabled
0x40428094 C   FIELD 26w01 PINCM_INV (rw): Data inversion selection
0x40428094 C   FIELD 27w01 PINCM_WUEN (rw): Wakeup Enable bit
0x40428094 C   FIELD 28w01 PINCM_WCOMP (rw): Wakeup Compare Value bit
0x40428098 B  REGISTER PINCM[37] (rw): Pin Control Management Register in SECCFG region
0x40428098 C   FIELD 00w06 PINCM_PF (rw): P channel Function selection bits
0x40428098 C   FIELD 07w01 PINCM_PC (rw): Peripheral is Connected
0x40428098 C   FIELD 13w01 PINCM_WAKESTAT (ro): This has the IOPAD WAKEUP signal as status bit.
0x40428098 C   FIELD 16w01 PINCM_PIPD (rw): Pull Down control selection
0x40428098 C   FIELD 17w01 PINCM_PIPU (rw): Pull Up control selection
0x40428098 C   FIELD 18w01 PINCM_INENA (rw): Input Enable Control Selection
0x40428098 C   FIELD 19w01 PINCM_HYSTEN (rw): Hystersis Enable Control Selection
0x40428098 C   FIELD 20w01 PINCM_DRV (rw): Drive strength control selection, for HS IOCELL only
0x40428098 C   FIELD 25w01 PINCM_HIZ1 (rw): High output value will tri-state the output when this bit is enabled
0x40428098 C   FIELD 26w01 PINCM_INV (rw): Data inversion selection
0x40428098 C   FIELD 27w01 PINCM_WUEN (rw): Wakeup Enable bit
0x40428098 C   FIELD 28w01 PINCM_WCOMP (rw): Wakeup Compare Value bit
0x4042809C B  REGISTER PINCM[38] (rw): Pin Control Management Register in SECCFG region
0x4042809C C   FIELD 00w06 PINCM_PF (rw): P channel Function selection bits
0x4042809C C   FIELD 07w01 PINCM_PC (rw): Peripheral is Connected
0x4042809C C   FIELD 13w01 PINCM_WAKESTAT (ro): This has the IOPAD WAKEUP signal as status bit.
0x4042809C C   FIELD 16w01 PINCM_PIPD (rw): Pull Down control selection
0x4042809C C   FIELD 17w01 PINCM_PIPU (rw): Pull Up control selection
0x4042809C C   FIELD 18w01 PINCM_INENA (rw): Input Enable Control Selection
0x4042809C C   FIELD 19w01 PINCM_HYSTEN (rw): Hystersis Enable Control Selection
0x4042809C C   FIELD 20w01 PINCM_DRV (rw): Drive strength control selection, for HS IOCELL only
0x4042809C C   FIELD 25w01 PINCM_HIZ1 (rw): High output value will tri-state the output when this bit is enabled
0x4042809C C   FIELD 26w01 PINCM_INV (rw): Data inversion selection
0x4042809C C   FIELD 27w01 PINCM_WUEN (rw): Wakeup Enable bit
0x4042809C C   FIELD 28w01 PINCM_WCOMP (rw): Wakeup Compare Value bit
0x404280A0 B  REGISTER PINCM[39] (rw): Pin Control Management Register in SECCFG region
0x404280A0 C   FIELD 00w06 PINCM_PF (rw): P channel Function selection bits
0x404280A0 C   FIELD 07w01 PINCM_PC (rw): Peripheral is Connected
0x404280A0 C   FIELD 13w01 PINCM_WAKESTAT (ro): This has the IOPAD WAKEUP signal as status bit.
0x404280A0 C   FIELD 16w01 PINCM_PIPD (rw): Pull Down control selection
0x404280A0 C   FIELD 17w01 PINCM_PIPU (rw): Pull Up control selection
0x404280A0 C   FIELD 18w01 PINCM_INENA (rw): Input Enable Control Selection
0x404280A0 C   FIELD 19w01 PINCM_HYSTEN (rw): Hystersis Enable Control Selection
0x404280A0 C   FIELD 20w01 PINCM_DRV (rw): Drive strength control selection, for HS IOCELL only
0x404280A0 C   FIELD 25w01 PINCM_HIZ1 (rw): High output value will tri-state the output when this bit is enabled
0x404280A0 C   FIELD 26w01 PINCM_INV (rw): Data inversion selection
0x404280A0 C   FIELD 27w01 PINCM_WUEN (rw): Wakeup Enable bit
0x404280A0 C   FIELD 28w01 PINCM_WCOMP (rw): Wakeup Compare Value bit
0x404280A4 B  REGISTER PINCM[40] (rw): Pin Control Management Register in SECCFG region
0x404280A4 C   FIELD 00w06 PINCM_PF (rw): P channel Function selection bits
0x404280A4 C   FIELD 07w01 PINCM_PC (rw): Peripheral is Connected
0x404280A4 C   FIELD 13w01 PINCM_WAKESTAT (ro): This has the IOPAD WAKEUP signal as status bit.
0x404280A4 C   FIELD 16w01 PINCM_PIPD (rw): Pull Down control selection
0x404280A4 C   FIELD 17w01 PINCM_PIPU (rw): Pull Up control selection
0x404280A4 C   FIELD 18w01 PINCM_INENA (rw): Input Enable Control Selection
0x404280A4 C   FIELD 19w01 PINCM_HYSTEN (rw): Hystersis Enable Control Selection
0x404280A4 C   FIELD 20w01 PINCM_DRV (rw): Drive strength control selection, for HS IOCELL only
0x404280A4 C   FIELD 25w01 PINCM_HIZ1 (rw): High output value will tri-state the output when this bit is enabled
0x404280A4 C   FIELD 26w01 PINCM_INV (rw): Data inversion selection
0x404280A4 C   FIELD 27w01 PINCM_WUEN (rw): Wakeup Enable bit
0x404280A4 C   FIELD 28w01 PINCM_WCOMP (rw): Wakeup Compare Value bit
0x404280A8 B  REGISTER PINCM[41] (rw): Pin Control Management Register in SECCFG region
0x404280A8 C   FIELD 00w06 PINCM_PF (rw): P channel Function selection bits
0x404280A8 C   FIELD 07w01 PINCM_PC (rw): Peripheral is Connected
0x404280A8 C   FIELD 13w01 PINCM_WAKESTAT (ro): This has the IOPAD WAKEUP signal as status bit.
0x404280A8 C   FIELD 16w01 PINCM_PIPD (rw): Pull Down control selection
0x404280A8 C   FIELD 17w01 PINCM_PIPU (rw): Pull Up control selection
0x404280A8 C   FIELD 18w01 PINCM_INENA (rw): Input Enable Control Selection
0x404280A8 C   FIELD 19w01 PINCM_HYSTEN (rw): Hystersis Enable Control Selection
0x404280A8 C   FIELD 20w01 PINCM_DRV (rw): Drive strength control selection, for HS IOCELL only
0x404280A8 C   FIELD 25w01 PINCM_HIZ1 (rw): High output value will tri-state the output when this bit is enabled
0x404280A8 C   FIELD 26w01 PINCM_INV (rw): Data inversion selection
0x404280A8 C   FIELD 27w01 PINCM_WUEN (rw): Wakeup Enable bit
0x404280A8 C   FIELD 28w01 PINCM_WCOMP (rw): Wakeup Compare Value bit
0x404280AC B  REGISTER PINCM[42] (rw): Pin Control Management Register in SECCFG region
0x404280AC C   FIELD 00w06 PINCM_PF (rw): P channel Function selection bits
0x404280AC C   FIELD 07w01 PINCM_PC (rw): Peripheral is Connected
0x404280AC C   FIELD 13w01 PINCM_WAKESTAT (ro): This has the IOPAD WAKEUP signal as status bit.
0x404280AC C   FIELD 16w01 PINCM_PIPD (rw): Pull Down control selection
0x404280AC C   FIELD 17w01 PINCM_PIPU (rw): Pull Up control selection
0x404280AC C   FIELD 18w01 PINCM_INENA (rw): Input Enable Control Selection
0x404280AC C   FIELD 19w01 PINCM_HYSTEN (rw): Hystersis Enable Control Selection
0x404280AC C   FIELD 20w01 PINCM_DRV (rw): Drive strength control selection, for HS IOCELL only
0x404280AC C   FIELD 25w01 PINCM_HIZ1 (rw): High output value will tri-state the output when this bit is enabled
0x404280AC C   FIELD 26w01 PINCM_INV (rw): Data inversion selection
0x404280AC C   FIELD 27w01 PINCM_WUEN (rw): Wakeup Enable bit
0x404280AC C   FIELD 28w01 PINCM_WCOMP (rw): Wakeup Compare Value bit
0x404280B0 B  REGISTER PINCM[43] (rw): Pin Control Management Register in SECCFG region
0x404280B0 C   FIELD 00w06 PINCM_PF (rw): P channel Function selection bits
0x404280B0 C   FIELD 07w01 PINCM_PC (rw): Peripheral is Connected
0x404280B0 C   FIELD 13w01 PINCM_WAKESTAT (ro): This has the IOPAD WAKEUP signal as status bit.
0x404280B0 C   FIELD 16w01 PINCM_PIPD (rw): Pull Down control selection
0x404280B0 C   FIELD 17w01 PINCM_PIPU (rw): Pull Up control selection
0x404280B0 C   FIELD 18w01 PINCM_INENA (rw): Input Enable Control Selection
0x404280B0 C   FIELD 19w01 PINCM_HYSTEN (rw): Hystersis Enable Control Selection
0x404280B0 C   FIELD 20w01 PINCM_DRV (rw): Drive strength control selection, for HS IOCELL only
0x404280B0 C   FIELD 25w01 PINCM_HIZ1 (rw): High output value will tri-state the output when this bit is enabled
0x404280B0 C   FIELD 26w01 PINCM_INV (rw): Data inversion selection
0x404280B0 C   FIELD 27w01 PINCM_WUEN (rw): Wakeup Enable bit
0x404280B0 C   FIELD 28w01 PINCM_WCOMP (rw): Wakeup Compare Value bit
0x404280B4 B  REGISTER PINCM[44] (rw): Pin Control Management Register in SECCFG region
0x404280B4 C   FIELD 00w06 PINCM_PF (rw): P channel Function selection bits
0x404280B4 C   FIELD 07w01 PINCM_PC (rw): Peripheral is Connected
0x404280B4 C   FIELD 13w01 PINCM_WAKESTAT (ro): This has the IOPAD WAKEUP signal as status bit.
0x404280B4 C   FIELD 16w01 PINCM_PIPD (rw): Pull Down control selection
0x404280B4 C   FIELD 17w01 PINCM_PIPU (rw): Pull Up control selection
0x404280B4 C   FIELD 18w01 PINCM_INENA (rw): Input Enable Control Selection
0x404280B4 C   FIELD 19w01 PINCM_HYSTEN (rw): Hystersis Enable Control Selection
0x404280B4 C   FIELD 20w01 PINCM_DRV (rw): Drive strength control selection, for HS IOCELL only
0x404280B4 C   FIELD 25w01 PINCM_HIZ1 (rw): High output value will tri-state the output when this bit is enabled
0x404280B4 C   FIELD 26w01 PINCM_INV (rw): Data inversion selection
0x404280B4 C   FIELD 27w01 PINCM_WUEN (rw): Wakeup Enable bit
0x404280B4 C   FIELD 28w01 PINCM_WCOMP (rw): Wakeup Compare Value bit
0x404280B8 B  REGISTER PINCM[45] (rw): Pin Control Management Register in SECCFG region
0x404280B8 C   FIELD 00w06 PINCM_PF (rw): P channel Function selection bits
0x404280B8 C   FIELD 07w01 PINCM_PC (rw): Peripheral is Connected
0x404280B8 C   FIELD 13w01 PINCM_WAKESTAT (ro): This has the IOPAD WAKEUP signal as status bit.
0x404280B8 C   FIELD 16w01 PINCM_PIPD (rw): Pull Down control selection
0x404280B8 C   FIELD 17w01 PINCM_PIPU (rw): Pull Up control selection
0x404280B8 C   FIELD 18w01 PINCM_INENA (rw): Input Enable Control Selection
0x404280B8 C   FIELD 19w01 PINCM_HYSTEN (rw): Hystersis Enable Control Selection
0x404280B8 C   FIELD 20w01 PINCM_DRV (rw): Drive strength control selection, for HS IOCELL only
0x404280B8 C   FIELD 25w01 PINCM_HIZ1 (rw): High output value will tri-state the output when this bit is enabled
0x404280B8 C   FIELD 26w01 PINCM_INV (rw): Data inversion selection
0x404280B8 C   FIELD 27w01 PINCM_WUEN (rw): Wakeup Enable bit
0x404280B8 C   FIELD 28w01 PINCM_WCOMP (rw): Wakeup Compare Value bit
0x404280BC B  REGISTER PINCM[46] (rw): Pin Control Management Register in SECCFG region
0x404280BC C   FIELD 00w06 PINCM_PF (rw): P channel Function selection bits
0x404280BC C   FIELD 07w01 PINCM_PC (rw): Peripheral is Connected
0x404280BC C   FIELD 13w01 PINCM_WAKESTAT (ro): This has the IOPAD WAKEUP signal as status bit.
0x404280BC C   FIELD 16w01 PINCM_PIPD (rw): Pull Down control selection
0x404280BC C   FIELD 17w01 PINCM_PIPU (rw): Pull Up control selection
0x404280BC C   FIELD 18w01 PINCM_INENA (rw): Input Enable Control Selection
0x404280BC C   FIELD 19w01 PINCM_HYSTEN (rw): Hystersis Enable Control Selection
0x404280BC C   FIELD 20w01 PINCM_DRV (rw): Drive strength control selection, for HS IOCELL only
0x404280BC C   FIELD 25w01 PINCM_HIZ1 (rw): High output value will tri-state the output when this bit is enabled
0x404280BC C   FIELD 26w01 PINCM_INV (rw): Data inversion selection
0x404280BC C   FIELD 27w01 PINCM_WUEN (rw): Wakeup Enable bit
0x404280BC C   FIELD 28w01 PINCM_WCOMP (rw): Wakeup Compare Value bit
0x404280C0 B  REGISTER PINCM[47] (rw): Pin Control Management Register in SECCFG region
0x404280C0 C   FIELD 00w06 PINCM_PF (rw): P channel Function selection bits
0x404280C0 C   FIELD 07w01 PINCM_PC (rw): Peripheral is Connected
0x404280C0 C   FIELD 13w01 PINCM_WAKESTAT (ro): This has the IOPAD WAKEUP signal as status bit.
0x404280C0 C   FIELD 16w01 PINCM_PIPD (rw): Pull Down control selection
0x404280C0 C   FIELD 17w01 PINCM_PIPU (rw): Pull Up control selection
0x404280C0 C   FIELD 18w01 PINCM_INENA (rw): Input Enable Control Selection
0x404280C0 C   FIELD 19w01 PINCM_HYSTEN (rw): Hystersis Enable Control Selection
0x404280C0 C   FIELD 20w01 PINCM_DRV (rw): Drive strength control selection, for HS IOCELL only
0x404280C0 C   FIELD 25w01 PINCM_HIZ1 (rw): High output value will tri-state the output when this bit is enabled
0x404280C0 C   FIELD 26w01 PINCM_INV (rw): Data inversion selection
0x404280C0 C   FIELD 27w01 PINCM_WUEN (rw): Wakeup Enable bit
0x404280C0 C   FIELD 28w01 PINCM_WCOMP (rw): Wakeup Compare Value bit
0x404280C4 B  REGISTER PINCM[48] (rw): Pin Control Management Register in SECCFG region
0x404280C4 C   FIELD 00w06 PINCM_PF (rw): P channel Function selection bits
0x404280C4 C   FIELD 07w01 PINCM_PC (rw): Peripheral is Connected
0x404280C4 C   FIELD 13w01 PINCM_WAKESTAT (ro): This has the IOPAD WAKEUP signal as status bit.
0x404280C4 C   FIELD 16w01 PINCM_PIPD (rw): Pull Down control selection
0x404280C4 C   FIELD 17w01 PINCM_PIPU (rw): Pull Up control selection
0x404280C4 C   FIELD 18w01 PINCM_INENA (rw): Input Enable Control Selection
0x404280C4 C   FIELD 19w01 PINCM_HYSTEN (rw): Hystersis Enable Control Selection
0x404280C4 C   FIELD 20w01 PINCM_DRV (rw): Drive strength control selection, for HS IOCELL only
0x404280C4 C   FIELD 25w01 PINCM_HIZ1 (rw): High output value will tri-state the output when this bit is enabled
0x404280C4 C   FIELD 26w01 PINCM_INV (rw): Data inversion selection
0x404280C4 C   FIELD 27w01 PINCM_WUEN (rw): Wakeup Enable bit
0x404280C4 C   FIELD 28w01 PINCM_WCOMP (rw): Wakeup Compare Value bit
0x404280C8 B  REGISTER PINCM[49] (rw): Pin Control Management Register in SECCFG region
0x404280C8 C   FIELD 00w06 PINCM_PF (rw): P channel Function selection bits
0x404280C8 C   FIELD 07w01 PINCM_PC (rw): Peripheral is Connected
0x404280C8 C   FIELD 13w01 PINCM_WAKESTAT (ro): This has the IOPAD WAKEUP signal as status bit.
0x404280C8 C   FIELD 16w01 PINCM_PIPD (rw): Pull Down control selection
0x404280C8 C   FIELD 17w01 PINCM_PIPU (rw): Pull Up control selection
0x404280C8 C   FIELD 18w01 PINCM_INENA (rw): Input Enable Control Selection
0x404280C8 C   FIELD 19w01 PINCM_HYSTEN (rw): Hystersis Enable Control Selection
0x404280C8 C   FIELD 20w01 PINCM_DRV (rw): Drive strength control selection, for HS IOCELL only
0x404280C8 C   FIELD 25w01 PINCM_HIZ1 (rw): High output value will tri-state the output when this bit is enabled
0x404280C8 C   FIELD 26w01 PINCM_INV (rw): Data inversion selection
0x404280C8 C   FIELD 27w01 PINCM_WUEN (rw): Wakeup Enable bit
0x404280C8 C   FIELD 28w01 PINCM_WCOMP (rw): Wakeup Compare Value bit
0x404280CC B  REGISTER PINCM[50] (rw): Pin Control Management Register in SECCFG region
0x404280CC C   FIELD 00w06 PINCM_PF (rw): P channel Function selection bits
0x404280CC C   FIELD 07w01 PINCM_PC (rw): Peripheral is Connected
0x404280CC C   FIELD 13w01 PINCM_WAKESTAT (ro): This has the IOPAD WAKEUP signal as status bit.
0x404280CC C   FIELD 16w01 PINCM_PIPD (rw): Pull Down control selection
0x404280CC C   FIELD 17w01 PINCM_PIPU (rw): Pull Up control selection
0x404280CC C   FIELD 18w01 PINCM_INENA (rw): Input Enable Control Selection
0x404280CC C   FIELD 19w01 PINCM_HYSTEN (rw): Hystersis Enable Control Selection
0x404280CC C   FIELD 20w01 PINCM_DRV (rw): Drive strength control selection, for HS IOCELL only
0x404280CC C   FIELD 25w01 PINCM_HIZ1 (rw): High output value will tri-state the output when this bit is enabled
0x404280CC C   FIELD 26w01 PINCM_INV (rw): Data inversion selection
0x404280CC C   FIELD 27w01 PINCM_WUEN (rw): Wakeup Enable bit
0x404280CC C   FIELD 28w01 PINCM_WCOMP (rw): Wakeup Compare Value bit
0x404280D0 B  REGISTER PINCM[51] (rw): Pin Control Management Register in SECCFG region
0x404280D0 C   FIELD 00w06 PINCM_PF (rw): P channel Function selection bits
0x404280D0 C   FIELD 07w01 PINCM_PC (rw): Peripheral is Connected
0x404280D0 C   FIELD 13w01 PINCM_WAKESTAT (ro): This has the IOPAD WAKEUP signal as status bit.
0x404280D0 C   FIELD 16w01 PINCM_PIPD (rw): Pull Down control selection
0x404280D0 C   FIELD 17w01 PINCM_PIPU (rw): Pull Up control selection
0x404280D0 C   FIELD 18w01 PINCM_INENA (rw): Input Enable Control Selection
0x404280D0 C   FIELD 19w01 PINCM_HYSTEN (rw): Hystersis Enable Control Selection
0x404280D0 C   FIELD 20w01 PINCM_DRV (rw): Drive strength control selection, for HS IOCELL only
0x404280D0 C   FIELD 25w01 PINCM_HIZ1 (rw): High output value will tri-state the output when this bit is enabled
0x404280D0 C   FIELD 26w01 PINCM_INV (rw): Data inversion selection
0x404280D0 C   FIELD 27w01 PINCM_WUEN (rw): Wakeup Enable bit
0x404280D0 C   FIELD 28w01 PINCM_WCOMP (rw): Wakeup Compare Value bit
0x404280D4 B  REGISTER PINCM[52] (rw): Pin Control Management Register in SECCFG region
0x404280D4 C   FIELD 00w06 PINCM_PF (rw): P channel Function selection bits
0x404280D4 C   FIELD 07w01 PINCM_PC (rw): Peripheral is Connected
0x404280D4 C   FIELD 13w01 PINCM_WAKESTAT (ro): This has the IOPAD WAKEUP signal as status bit.
0x404280D4 C   FIELD 16w01 PINCM_PIPD (rw): Pull Down control selection
0x404280D4 C   FIELD 17w01 PINCM_PIPU (rw): Pull Up control selection
0x404280D4 C   FIELD 18w01 PINCM_INENA (rw): Input Enable Control Selection
0x404280D4 C   FIELD 19w01 PINCM_HYSTEN (rw): Hystersis Enable Control Selection
0x404280D4 C   FIELD 20w01 PINCM_DRV (rw): Drive strength control selection, for HS IOCELL only
0x404280D4 C   FIELD 25w01 PINCM_HIZ1 (rw): High output value will tri-state the output when this bit is enabled
0x404280D4 C   FIELD 26w01 PINCM_INV (rw): Data inversion selection
0x404280D4 C   FIELD 27w01 PINCM_WUEN (rw): Wakeup Enable bit
0x404280D4 C   FIELD 28w01 PINCM_WCOMP (rw): Wakeup Compare Value bit
0x404280D8 B  REGISTER PINCM[53] (rw): Pin Control Management Register in SECCFG region
0x404280D8 C   FIELD 00w06 PINCM_PF (rw): P channel Function selection bits
0x404280D8 C   FIELD 07w01 PINCM_PC (rw): Peripheral is Connected
0x404280D8 C   FIELD 13w01 PINCM_WAKESTAT (ro): This has the IOPAD WAKEUP signal as status bit.
0x404280D8 C   FIELD 16w01 PINCM_PIPD (rw): Pull Down control selection
0x404280D8 C   FIELD 17w01 PINCM_PIPU (rw): Pull Up control selection
0x404280D8 C   FIELD 18w01 PINCM_INENA (rw): Input Enable Control Selection
0x404280D8 C   FIELD 19w01 PINCM_HYSTEN (rw): Hystersis Enable Control Selection
0x404280D8 C   FIELD 20w01 PINCM_DRV (rw): Drive strength control selection, for HS IOCELL only
0x404280D8 C   FIELD 25w01 PINCM_HIZ1 (rw): High output value will tri-state the output when this bit is enabled
0x404280D8 C   FIELD 26w01 PINCM_INV (rw): Data inversion selection
0x404280D8 C   FIELD 27w01 PINCM_WUEN (rw): Wakeup Enable bit
0x404280D8 C   FIELD 28w01 PINCM_WCOMP (rw): Wakeup Compare Value bit
0x404280DC B  REGISTER PINCM[54] (rw): Pin Control Management Register in SECCFG region
0x404280DC C   FIELD 00w06 PINCM_PF (rw): P channel Function selection bits
0x404280DC C   FIELD 07w01 PINCM_PC (rw): Peripheral is Connected
0x404280DC C   FIELD 13w01 PINCM_WAKESTAT (ro): This has the IOPAD WAKEUP signal as status bit.
0x404280DC C   FIELD 16w01 PINCM_PIPD (rw): Pull Down control selection
0x404280DC C   FIELD 17w01 PINCM_PIPU (rw): Pull Up control selection
0x404280DC C   FIELD 18w01 PINCM_INENA (rw): Input Enable Control Selection
0x404280DC C   FIELD 19w01 PINCM_HYSTEN (rw): Hystersis Enable Control Selection
0x404280DC C   FIELD 20w01 PINCM_DRV (rw): Drive strength control selection, for HS IOCELL only
0x404280DC C   FIELD 25w01 PINCM_HIZ1 (rw): High output value will tri-state the output when this bit is enabled
0x404280DC C   FIELD 26w01 PINCM_INV (rw): Data inversion selection
0x404280DC C   FIELD 27w01 PINCM_WUEN (rw): Wakeup Enable bit
0x404280DC C   FIELD 28w01 PINCM_WCOMP (rw): Wakeup Compare Value bit
0x404280E0 B  REGISTER PINCM[55] (rw): Pin Control Management Register in SECCFG region
0x404280E0 C   FIELD 00w06 PINCM_PF (rw): P channel Function selection bits
0x404280E0 C   FIELD 07w01 PINCM_PC (rw): Peripheral is Connected
0x404280E0 C   FIELD 13w01 PINCM_WAKESTAT (ro): This has the IOPAD WAKEUP signal as status bit.
0x404280E0 C   FIELD 16w01 PINCM_PIPD (rw): Pull Down control selection
0x404280E0 C   FIELD 17w01 PINCM_PIPU (rw): Pull Up control selection
0x404280E0 C   FIELD 18w01 PINCM_INENA (rw): Input Enable Control Selection
0x404280E0 C   FIELD 19w01 PINCM_HYSTEN (rw): Hystersis Enable Control Selection
0x404280E0 C   FIELD 20w01 PINCM_DRV (rw): Drive strength control selection, for HS IOCELL only
0x404280E0 C   FIELD 25w01 PINCM_HIZ1 (rw): High output value will tri-state the output when this bit is enabled
0x404280E0 C   FIELD 26w01 PINCM_INV (rw): Data inversion selection
0x404280E0 C   FIELD 27w01 PINCM_WUEN (rw): Wakeup Enable bit
0x404280E0 C   FIELD 28w01 PINCM_WCOMP (rw): Wakeup Compare Value bit
0x404280E4 B  REGISTER PINCM[56] (rw): Pin Control Management Register in SECCFG region
0x404280E4 C   FIELD 00w06 PINCM_PF (rw): P channel Function selection bits
0x404280E4 C   FIELD 07w01 PINCM_PC (rw): Peripheral is Connected
0x404280E4 C   FIELD 13w01 PINCM_WAKESTAT (ro): This has the IOPAD WAKEUP signal as status bit.
0x404280E4 C   FIELD 16w01 PINCM_PIPD (rw): Pull Down control selection
0x404280E4 C   FIELD 17w01 PINCM_PIPU (rw): Pull Up control selection
0x404280E4 C   FIELD 18w01 PINCM_INENA (rw): Input Enable Control Selection
0x404280E4 C   FIELD 19w01 PINCM_HYSTEN (rw): Hystersis Enable Control Selection
0x404280E4 C   FIELD 20w01 PINCM_DRV (rw): Drive strength control selection, for HS IOCELL only
0x404280E4 C   FIELD 25w01 PINCM_HIZ1 (rw): High output value will tri-state the output when this bit is enabled
0x404280E4 C   FIELD 26w01 PINCM_INV (rw): Data inversion selection
0x404280E4 C   FIELD 27w01 PINCM_WUEN (rw): Wakeup Enable bit
0x404280E4 C   FIELD 28w01 PINCM_WCOMP (rw): Wakeup Compare Value bit
0x404280E8 B  REGISTER PINCM[57] (rw): Pin Control Management Register in SECCFG region
0x404280E8 C   FIELD 00w06 PINCM_PF (rw): P channel Function selection bits
0x404280E8 C   FIELD 07w01 PINCM_PC (rw): Peripheral is Connected
0x404280E8 C   FIELD 13w01 PINCM_WAKESTAT (ro): This has the IOPAD WAKEUP signal as status bit.
0x404280E8 C   FIELD 16w01 PINCM_PIPD (rw): Pull Down control selection
0x404280E8 C   FIELD 17w01 PINCM_PIPU (rw): Pull Up control selection
0x404280E8 C   FIELD 18w01 PINCM_INENA (rw): Input Enable Control Selection
0x404280E8 C   FIELD 19w01 PINCM_HYSTEN (rw): Hystersis Enable Control Selection
0x404280E8 C   FIELD 20w01 PINCM_DRV (rw): Drive strength control selection, for HS IOCELL only
0x404280E8 C   FIELD 25w01 PINCM_HIZ1 (rw): High output value will tri-state the output when this bit is enabled
0x404280E8 C   FIELD 26w01 PINCM_INV (rw): Data inversion selection
0x404280E8 C   FIELD 27w01 PINCM_WUEN (rw): Wakeup Enable bit
0x404280E8 C   FIELD 28w01 PINCM_WCOMP (rw): Wakeup Compare Value bit
0x404280EC B  REGISTER PINCM[58] (rw): Pin Control Management Register in SECCFG region
0x404280EC C   FIELD 00w06 PINCM_PF (rw): P channel Function selection bits
0x404280EC C   FIELD 07w01 PINCM_PC (rw): Peripheral is Connected
0x404280EC C   FIELD 13w01 PINCM_WAKESTAT (ro): This has the IOPAD WAKEUP signal as status bit.
0x404280EC C   FIELD 16w01 PINCM_PIPD (rw): Pull Down control selection
0x404280EC C   FIELD 17w01 PINCM_PIPU (rw): Pull Up control selection
0x404280EC C   FIELD 18w01 PINCM_INENA (rw): Input Enable Control Selection
0x404280EC C   FIELD 19w01 PINCM_HYSTEN (rw): Hystersis Enable Control Selection
0x404280EC C   FIELD 20w01 PINCM_DRV (rw): Drive strength control selection, for HS IOCELL only
0x404280EC C   FIELD 25w01 PINCM_HIZ1 (rw): High output value will tri-state the output when this bit is enabled
0x404280EC C   FIELD 26w01 PINCM_INV (rw): Data inversion selection
0x404280EC C   FIELD 27w01 PINCM_WUEN (rw): Wakeup Enable bit
0x404280EC C   FIELD 28w01 PINCM_WCOMP (rw): Wakeup Compare Value bit
0x404280F0 B  REGISTER PINCM[59] (rw): Pin Control Management Register in SECCFG region
0x404280F0 C   FIELD 00w06 PINCM_PF (rw): P channel Function selection bits
0x404280F0 C   FIELD 07w01 PINCM_PC (rw): Peripheral is Connected
0x404280F0 C   FIELD 13w01 PINCM_WAKESTAT (ro): This has the IOPAD WAKEUP signal as status bit.
0x404280F0 C   FIELD 16w01 PINCM_PIPD (rw): Pull Down control selection
0x404280F0 C   FIELD 17w01 PINCM_PIPU (rw): Pull Up control selection
0x404280F0 C   FIELD 18w01 PINCM_INENA (rw): Input Enable Control Selection
0x404280F0 C   FIELD 19w01 PINCM_HYSTEN (rw): Hystersis Enable Control Selection
0x404280F0 C   FIELD 20w01 PINCM_DRV (rw): Drive strength control selection, for HS IOCELL only
0x404280F0 C   FIELD 25w01 PINCM_HIZ1 (rw): High output value will tri-state the output when this bit is enabled
0x404280F0 C   FIELD 26w01 PINCM_INV (rw): Data inversion selection
0x404280F0 C   FIELD 27w01 PINCM_WUEN (rw): Wakeup Enable bit
0x404280F0 C   FIELD 28w01 PINCM_WCOMP (rw): Wakeup Compare Value bit
0x404280F4 B  REGISTER PINCM[60] (rw): Pin Control Management Register in SECCFG region
0x404280F4 C   FIELD 00w06 PINCM_PF (rw): P channel Function selection bits
0x404280F4 C   FIELD 07w01 PINCM_PC (rw): Peripheral is Connected
0x404280F4 C   FIELD 13w01 PINCM_WAKESTAT (ro): This has the IOPAD WAKEUP signal as status bit.
0x404280F4 C   FIELD 16w01 PINCM_PIPD (rw): Pull Down control selection
0x404280F4 C   FIELD 17w01 PINCM_PIPU (rw): Pull Up control selection
0x404280F4 C   FIELD 18w01 PINCM_INENA (rw): Input Enable Control Selection
0x404280F4 C   FIELD 19w01 PINCM_HYSTEN (rw): Hystersis Enable Control Selection
0x404280F4 C   FIELD 20w01 PINCM_DRV (rw): Drive strength control selection, for HS IOCELL only
0x404280F4 C   FIELD 25w01 PINCM_HIZ1 (rw): High output value will tri-state the output when this bit is enabled
0x404280F4 C   FIELD 26w01 PINCM_INV (rw): Data inversion selection
0x404280F4 C   FIELD 27w01 PINCM_WUEN (rw): Wakeup Enable bit
0x404280F4 C   FIELD 28w01 PINCM_WCOMP (rw): Wakeup Compare Value bit
0x4042A000 A PERIPHERAL DMA
0x4042A400 B  REGISTER FSUB_0 (rw): Subscriber Port 0
0x4042A400 C   FIELD 00w02 FSUB_0_CHANID: 0 = disconnected. 1-255 = connected to channelID = CHANID.
0x4042A404 B  REGISTER FSUB_1 (rw): Subscriber Port 1
0x4042A404 C   FIELD 00w02 FSUB_1_CHANID: 0 = disconnected. 1-255 = connected to channelID = CHANID.
0x4042A444 B  REGISTER FPUB_1 (rw): Publisher Port 0
0x4042A444 C   FIELD 00w02 FPUB_1_CHANID: 0 = disconnected. 1-255 = connected to channelID = CHANID.
0x4042B018 B  REGISTER PDBGCTL (rw): Peripheral Debug Control
0x4042B018 C   FIELD 00w01 PDBGCTL_FREE: Free run control
0x4042B018 C   FIELD 01w01 PDBGCTL_SOFT: Soft halt boundary control. This function is only available, if [FREE] is set to 'STOP'
0x4042B020 B  REGISTER IIDX (ro): Interrupt index
0x4042B020 C   FIELD 00w08 IIDX_STAT (ro): Interrupt index status
0x4042B028 B  REGISTER IMASK (rw): Interrupt mask
0x4042B028 C   FIELD 00w01 IMASK_DMACH0: DMA Channel 0 interrupt signal. Size counter reached zero (DMASZ=0).
0x4042B028 C   FIELD 01w01 IMASK_DMACH1 (rw): DMA Channel 1 interrupt signal. Size counter reached zero (DMASZ=0).
0x4042B028 C   FIELD 02w01 IMASK_DMACH2: DMA Channel 2 interrupt signal. Size counter reached zero (DMASZ=0).
0x4042B028 C   FIELD 16w01 IMASK_PREIRQCH0: Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold.
0x4042B028 C   FIELD 24w01 IMASK_ADDRERR: DMA address error, SRC address not reachable.
0x4042B028 C   FIELD 25w01 IMASK_DATAERR: DMA data error, SRC data might be corrupted (PAR or ECC error).
0x4042B030 B  REGISTER RIS (ro): Raw interrupt status
0x4042B030 C   FIELD 00w01 RIS_DMACH0: DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0).
0x4042B030 C   FIELD 01w01 RIS_DMACH1: DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0).
0x4042B030 C   FIELD 02w01 RIS_DMACH2: DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0).
0x4042B030 C   FIELD 16w01 RIS_PREIRQCH0: Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold.
0x4042B030 C   FIELD 24w01 RIS_ADDRERR: DMA address error, SRC address not reachable.
0x4042B030 C   FIELD 25w01 RIS_DATAERR: DMA data error, SRC data might be corrupted (PAR or ECC error).
0x4042B038 B  REGISTER MIS (ro): Masked interrupt status
0x4042B038 C   FIELD 00w01 MIS_DMACH0: DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0).
0x4042B038 C   FIELD 01w01 MIS_DMACH1: DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0).
0x4042B038 C   FIELD 02w01 MIS_DMACH2: DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0).
0x4042B038 C   FIELD 16w01 MIS_PREIRQCH0: Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold.
0x4042B038 C   FIELD 24w01 MIS_ADDRERR: DMA address error, SRC address not reachable.
0x4042B038 C   FIELD 25w01 MIS_DATAERR: DMA data error, SRC data might be corrupted (PAR or ECC error).
0x4042B040 B  REGISTER ISET (wo): Interrupt set
0x4042B040 C   FIELD 00w01 ISET_DMACH0: DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0).
0x4042B040 C   FIELD 01w01 ISET_DMACH1: DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0).
0x4042B040 C   FIELD 02w01 ISET_DMACH2: DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0).
0x4042B040 C   FIELD 16w01 ISET_PREIRQCH0: Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold.
0x4042B040 C   FIELD 24w01 ISET_ADDRERR: DMA address error, SRC address not reachable.
0x4042B040 C   FIELD 25w01 ISET_DATAERR: DMA data error, SRC data might be corrupted (PAR or ECC error).
0x4042B048 B  REGISTER ICLR (wo): Interrupt clear
0x4042B048 C   FIELD 00w01 ICLR_DMACH0: DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0).
0x4042B048 C   FIELD 01w01 ICLR_DMACH1: DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0).
0x4042B048 C   FIELD 02w01 ICLR_DMACH2: DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0).
0x4042B048 C   FIELD 16w01 ICLR_PREIRQCH0: Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold.
0x4042B048 C   FIELD 24w01 ICLR_ADDRERR: DMA address error, SRC address not reachable.
0x4042B048 C   FIELD 25w01 ICLR_DATAERR: DMA data error, SRC data might be corrupted (PAR or ECC error).
0x4042B0E0 B  REGISTER EVT_MODE (rw): Event Mode
0x4042B0E0 C   FIELD 00w02 EVT_MODE_INT0_CFG (ro): Event line mode select for event corresponding to interrupt event INT_EVENT[0]
0x4042B0E0 C   FIELD 02w02 EVT_MODE_EVT1_CFG (ro): Event line mode select for event corresponding to generic event INT_EVENT[1]
0x4042B0FC B  REGISTER DESC (ro): Module Description
0x4042B0FC C   FIELD 00w04 DESC_MINREV: Minor rev of the IP
0x4042B0FC C   FIELD 04w04 DESC_MAJREV: Major rev of the IP
0x4042B0FC C   FIELD 12w04 DESC_FEATUREVER: Feature Set for the DMA: number of DMA channel minus one (e.g. 0->1ch, 2->3ch, 15->16ch).
0x4042B0FC C   FIELD 16w16 DESC_MODULEID: Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness.
0x4042B100 B  REGISTER DMAPRIO (rw): DMA Channel Priority Control
0x4042B100 C   FIELD 00w01 DMAPRIO_ROUNDROBIN: Round robin. This bit enables the round-robin DMA channel priorities.
0x4042B100 C   FIELD 16w02 DMAPRIO_BURSTSZ: Define the burst size of a block transfer, before the priority is re-evaluated
0x4042B110 B  REGISTER DMATCTL (rw): DMA Trigger Select
0x4042B110 C   FIELD 00w06 DMATCTL_DMATSEL: DMA Trigger Select Note: Reference the datasheet of the device to see the specific trigger mapping.
0x4042B110 C   FIELD 07w01 DMATCTL_DMATINT: DMA Trigger by Internal Channel
0x4042B200 B  REGISTER DMACTL (rw): DMA Channel Control
0x4042B200 C   FIELD 00w01 DMACTL_DMAREQ: DMA request. Software-controlled DMA start. DMAREQ is reset automatically.
0x4042B200 C   FIELD 01w01 DMACTL_DMAEN: DMA enable
0x4042B200 C   FIELD 04w03 DMACTL_DMAPREIRQ: Enable an early IRQ event. This can help software to react quicker to and DMA done event or allows some additional configuration before the channel is complete. Note: This register is only available in a FULL-channel configuration. Please consult the datasheet of the specific device to map which channel number has FULL or BASIC capability. In a BASIC configuration this register is a read only value and always reads as 0x0.
0x4042B200 C   FIELD 08w02 DMACTL_DMASRCWDTH: DMA source width. This bit selects the source data width as a byte, half word, word or long word.
0x4042B200 C   FIELD 12w02 DMACTL_DMADSTWDTH: DMA destination width. This bit selects the destination as a byte, half word, word or long word.
0x4042B200 C   FIELD 16w04 DMACTL_DMASRCINCR: DMA source increment. This bit selects automatic incrementing or decrementing of the source address DMASA for each transfer. The amount of change to the DMASA is based on the definitin in the DMASRCWDTH. For example an increment of 1 (+1) on a WORD transfer will increment the DMASA by 4.
0x4042B200 C   FIELD 20w04 DMACTL_DMADSTINCR: DMA destination increment. This bit selects automatic incrementing or decrementing of the destination address DMADA for each transfer. The amount of change to the DMADA is based on the definitin in the DMADSTWDTH. For example an increment of 1 (+1) on a WORD transfer will increment the DMADA by 4.
0x4042B200 C   FIELD 24w02 DMACTL_DMAEM: DMA extended mode Note: The extended transfer modes are only available in a FULL-channel configuration. Please consult the datasheet of the specific device to map which channel number has FULL or BASIC capability. In a BASIC channel configuration this register is a read-only register and reads 0x0.
0x4042B200 C   FIELD 28w02 DMACTL_DMATM: DMA transfer mode register Note: The repeat-single (2h) and repeat-block (3h) transfer are only available in a FULL-channel configuration. Please consult the datasheet of the specific device to map which channel number has FULL or BASIC capability. In a BASIC channel configuration only the values for single (0h) and block (1h) transfer can be set.
0x4042B204 B  REGISTER DMASA (rw): DMA Channel Source Address
0x4042B204 C   FIELD 00w32 DMASA_ADDR: DMA Channel Source Address
0x4042B208 B  REGISTER DMADA (rw): DMA Channel Destination Address
0x4042B208 C   FIELD 00w32 DMADA_ADDR: DMA Channel Destination Address
0x4042B20C B  REGISTER DMASZ (rw): DMA Channel Size
0x4042B20C C   FIELD 00w16 DMASZ_SIZE: DMA Channel Size in number of transfers
0x40440000 A PERIPHERAL CRC
0x40440800 B  REGISTER PWREN (rw): Power enable
0x40440800 C   FIELD 00w01 PWREN_ENABLE (rw): Enable the power
0x40440800 C   FIELD 24w08 PWREN_KEY (wo): KEY to allow Power State Change
0x40440804 B  REGISTER RSTCTL (wo): Reset Control
0x40440804 C   FIELD 00w01 RSTCTL_RESETASSERT (wo): Assert reset to the peripheral
0x40440804 C   FIELD 01w01 RSTCTL_RESETSTKYCLR (wo): Clear the RESETSTKY bit in the STAT register
0x40440804 C   FIELD 24w08 RSTCTL_KEY (wo): Unlock key
0x40440814 B  REGISTER STAT (ro): Status Register
0x40440814 C   FIELD 16w01 STAT_RESETSTKY (ro): This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register
0x404410FC B  REGISTER DESC (ro): Module Description
0x404410FC C   FIELD 00w04 DESC_MINREV: Minor rev of the IP
0x404410FC C   FIELD 04w04 DESC_MAJREV: Major rev of the IP
0x404410FC C   FIELD 08w04 DESC_INSTNUM: Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances
0x404410FC C   FIELD 12w04 DESC_FEATUREVER: Feature Set for the module *instance*
0x404410FC C   FIELD 16w16 DESC_MODULEID: Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness.
0x40441100 B  REGISTER CRCCTRL (rw): CRC Control Register
0x40441100 C   FIELD 00w01 CRCCTRL_POLYSIZE (rw): This bit indicates which CRC calculation is performed by the generator.
0x40441100 C   FIELD 01w01 CRCCTRL_BITREVERSE (rw): CRC Bit Input and output Reverse. This bit indictes that the bit order of each input byte used for the CRC calculation is reversed before it is passed to the generator, and that the bit order of the calculated CRC is be reversed when read from CRC_RESULT.
0x40441100 C   FIELD 02w01 CRCCTRL_INPUT_ENDIANNESS (rw): CRC Endian. This bit indicates the byte order within a word or half word of input data.
0x40441100 C   FIELD 04w01 CRCCTRL_OUTPUT_BYTESWAP (rw): CRC Output Byteswap Enable. This bit controls whether the output is byte-swapped upon a read of the CRCOUT register. If CRCOUT is accessed as a half-word, and the OUTPUT_BYTESWAP is set to to 1, then the two bytes in the 16-bit access are swapped and returned. B1 is returned as B0 B0 is returned as B1 If CRCOUT is accessed as a word, and the OUTPUT_BYTESWAP is set to 1, then the four bytes in the 32-bit read are swapped. B3 is returned as B0 B2 is returned as B1 B1 is returned as B2 B0 is returned as B3 Note that if the CRC POLYSIZE is 16-bit and a 32-bit read of CRCOUT is performed with OUTPUT_BYTESWAP enabled, then the output is: MSB LSB 0x0 0x0 B0 B1 If the CRC POLYSIZE is 16-bit and a 32-bit read of CRCOUT is performed with OUTPUT_BYTESWAP disabled, then the output is: MSB LSB 0x0 0x0 B1 B0
0x40441104 B  REGISTER CRCSEED (wo): CRC Seed Register
0x40441104 C   FIELD 00w32 CRCSEED_SEED (wo): Seed Data
0x40441108 B  REGISTER CRCIN (wo): CRC Input Data Register
0x40441108 C   FIELD 00w32 CRCIN_DATA (wo): Input Data
0x4044110C B  REGISTER CRCOUT (ro): CRC Output Result Register
0x4044110C C   FIELD 00w32 CRCOUT_RESULT (ro): Result
0x40441800 B  REGISTER CRCIN_IDX[0] (wo): CRC Input Data Array Register
0x40441800 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441804 B  REGISTER CRCIN_IDX[1] (wo): CRC Input Data Array Register
0x40441804 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441808 B  REGISTER CRCIN_IDX[2] (wo): CRC Input Data Array Register
0x40441808 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x4044180C B  REGISTER CRCIN_IDX[3] (wo): CRC Input Data Array Register
0x4044180C C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441810 B  REGISTER CRCIN_IDX[4] (wo): CRC Input Data Array Register
0x40441810 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441814 B  REGISTER CRCIN_IDX[5] (wo): CRC Input Data Array Register
0x40441814 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441818 B  REGISTER CRCIN_IDX[6] (wo): CRC Input Data Array Register
0x40441818 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x4044181C B  REGISTER CRCIN_IDX[7] (wo): CRC Input Data Array Register
0x4044181C C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441820 B  REGISTER CRCIN_IDX[8] (wo): CRC Input Data Array Register
0x40441820 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441824 B  REGISTER CRCIN_IDX[9] (wo): CRC Input Data Array Register
0x40441824 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441828 B  REGISTER CRCIN_IDX[10] (wo): CRC Input Data Array Register
0x40441828 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x4044182C B  REGISTER CRCIN_IDX[11] (wo): CRC Input Data Array Register
0x4044182C C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441830 B  REGISTER CRCIN_IDX[12] (wo): CRC Input Data Array Register
0x40441830 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441834 B  REGISTER CRCIN_IDX[13] (wo): CRC Input Data Array Register
0x40441834 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441838 B  REGISTER CRCIN_IDX[14] (wo): CRC Input Data Array Register
0x40441838 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x4044183C B  REGISTER CRCIN_IDX[15] (wo): CRC Input Data Array Register
0x4044183C C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441840 B  REGISTER CRCIN_IDX[16] (wo): CRC Input Data Array Register
0x40441840 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441844 B  REGISTER CRCIN_IDX[17] (wo): CRC Input Data Array Register
0x40441844 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441848 B  REGISTER CRCIN_IDX[18] (wo): CRC Input Data Array Register
0x40441848 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x4044184C B  REGISTER CRCIN_IDX[19] (wo): CRC Input Data Array Register
0x4044184C C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441850 B  REGISTER CRCIN_IDX[20] (wo): CRC Input Data Array Register
0x40441850 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441854 B  REGISTER CRCIN_IDX[21] (wo): CRC Input Data Array Register
0x40441854 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441858 B  REGISTER CRCIN_IDX[22] (wo): CRC Input Data Array Register
0x40441858 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x4044185C B  REGISTER CRCIN_IDX[23] (wo): CRC Input Data Array Register
0x4044185C C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441860 B  REGISTER CRCIN_IDX[24] (wo): CRC Input Data Array Register
0x40441860 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441864 B  REGISTER CRCIN_IDX[25] (wo): CRC Input Data Array Register
0x40441864 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441868 B  REGISTER CRCIN_IDX[26] (wo): CRC Input Data Array Register
0x40441868 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x4044186C B  REGISTER CRCIN_IDX[27] (wo): CRC Input Data Array Register
0x4044186C C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441870 B  REGISTER CRCIN_IDX[28] (wo): CRC Input Data Array Register
0x40441870 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441874 B  REGISTER CRCIN_IDX[29] (wo): CRC Input Data Array Register
0x40441874 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441878 B  REGISTER CRCIN_IDX[30] (wo): CRC Input Data Array Register
0x40441878 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x4044187C B  REGISTER CRCIN_IDX[31] (wo): CRC Input Data Array Register
0x4044187C C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441880 B  REGISTER CRCIN_IDX[32] (wo): CRC Input Data Array Register
0x40441880 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441884 B  REGISTER CRCIN_IDX[33] (wo): CRC Input Data Array Register
0x40441884 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441888 B  REGISTER CRCIN_IDX[34] (wo): CRC Input Data Array Register
0x40441888 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x4044188C B  REGISTER CRCIN_IDX[35] (wo): CRC Input Data Array Register
0x4044188C C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441890 B  REGISTER CRCIN_IDX[36] (wo): CRC Input Data Array Register
0x40441890 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441894 B  REGISTER CRCIN_IDX[37] (wo): CRC Input Data Array Register
0x40441894 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441898 B  REGISTER CRCIN_IDX[38] (wo): CRC Input Data Array Register
0x40441898 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x4044189C B  REGISTER CRCIN_IDX[39] (wo): CRC Input Data Array Register
0x4044189C C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x404418A0 B  REGISTER CRCIN_IDX[40] (wo): CRC Input Data Array Register
0x404418A0 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x404418A4 B  REGISTER CRCIN_IDX[41] (wo): CRC Input Data Array Register
0x404418A4 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x404418A8 B  REGISTER CRCIN_IDX[42] (wo): CRC Input Data Array Register
0x404418A8 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x404418AC B  REGISTER CRCIN_IDX[43] (wo): CRC Input Data Array Register
0x404418AC C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x404418B0 B  REGISTER CRCIN_IDX[44] (wo): CRC Input Data Array Register
0x404418B0 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x404418B4 B  REGISTER CRCIN_IDX[45] (wo): CRC Input Data Array Register
0x404418B4 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x404418B8 B  REGISTER CRCIN_IDX[46] (wo): CRC Input Data Array Register
0x404418B8 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x404418BC B  REGISTER CRCIN_IDX[47] (wo): CRC Input Data Array Register
0x404418BC C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x404418C0 B  REGISTER CRCIN_IDX[48] (wo): CRC Input Data Array Register
0x404418C0 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x404418C4 B  REGISTER CRCIN_IDX[49] (wo): CRC Input Data Array Register
0x404418C4 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x404418C8 B  REGISTER CRCIN_IDX[50] (wo): CRC Input Data Array Register
0x404418C8 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x404418CC B  REGISTER CRCIN_IDX[51] (wo): CRC Input Data Array Register
0x404418CC C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x404418D0 B  REGISTER CRCIN_IDX[52] (wo): CRC Input Data Array Register
0x404418D0 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x404418D4 B  REGISTER CRCIN_IDX[53] (wo): CRC Input Data Array Register
0x404418D4 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x404418D8 B  REGISTER CRCIN_IDX[54] (wo): CRC Input Data Array Register
0x404418D8 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x404418DC B  REGISTER CRCIN_IDX[55] (wo): CRC Input Data Array Register
0x404418DC C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x404418E0 B  REGISTER CRCIN_IDX[56] (wo): CRC Input Data Array Register
0x404418E0 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x404418E4 B  REGISTER CRCIN_IDX[57] (wo): CRC Input Data Array Register
0x404418E4 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x404418E8 B  REGISTER CRCIN_IDX[58] (wo): CRC Input Data Array Register
0x404418E8 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x404418EC B  REGISTER CRCIN_IDX[59] (wo): CRC Input Data Array Register
0x404418EC C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x404418F0 B  REGISTER CRCIN_IDX[60] (wo): CRC Input Data Array Register
0x404418F0 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x404418F4 B  REGISTER CRCIN_IDX[61] (wo): CRC Input Data Array Register
0x404418F4 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x404418F8 B  REGISTER CRCIN_IDX[62] (wo): CRC Input Data Array Register
0x404418F8 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x404418FC B  REGISTER CRCIN_IDX[63] (wo): CRC Input Data Array Register
0x404418FC C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441900 B  REGISTER CRCIN_IDX[64] (wo): CRC Input Data Array Register
0x40441900 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441904 B  REGISTER CRCIN_IDX[65] (wo): CRC Input Data Array Register
0x40441904 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441908 B  REGISTER CRCIN_IDX[66] (wo): CRC Input Data Array Register
0x40441908 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x4044190C B  REGISTER CRCIN_IDX[67] (wo): CRC Input Data Array Register
0x4044190C C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441910 B  REGISTER CRCIN_IDX[68] (wo): CRC Input Data Array Register
0x40441910 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441914 B  REGISTER CRCIN_IDX[69] (wo): CRC Input Data Array Register
0x40441914 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441918 B  REGISTER CRCIN_IDX[70] (wo): CRC Input Data Array Register
0x40441918 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x4044191C B  REGISTER CRCIN_IDX[71] (wo): CRC Input Data Array Register
0x4044191C C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441920 B  REGISTER CRCIN_IDX[72] (wo): CRC Input Data Array Register
0x40441920 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441924 B  REGISTER CRCIN_IDX[73] (wo): CRC Input Data Array Register
0x40441924 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441928 B  REGISTER CRCIN_IDX[74] (wo): CRC Input Data Array Register
0x40441928 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x4044192C B  REGISTER CRCIN_IDX[75] (wo): CRC Input Data Array Register
0x4044192C C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441930 B  REGISTER CRCIN_IDX[76] (wo): CRC Input Data Array Register
0x40441930 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441934 B  REGISTER CRCIN_IDX[77] (wo): CRC Input Data Array Register
0x40441934 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441938 B  REGISTER CRCIN_IDX[78] (wo): CRC Input Data Array Register
0x40441938 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x4044193C B  REGISTER CRCIN_IDX[79] (wo): CRC Input Data Array Register
0x4044193C C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441940 B  REGISTER CRCIN_IDX[80] (wo): CRC Input Data Array Register
0x40441940 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441944 B  REGISTER CRCIN_IDX[81] (wo): CRC Input Data Array Register
0x40441944 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441948 B  REGISTER CRCIN_IDX[82] (wo): CRC Input Data Array Register
0x40441948 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x4044194C B  REGISTER CRCIN_IDX[83] (wo): CRC Input Data Array Register
0x4044194C C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441950 B  REGISTER CRCIN_IDX[84] (wo): CRC Input Data Array Register
0x40441950 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441954 B  REGISTER CRCIN_IDX[85] (wo): CRC Input Data Array Register
0x40441954 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441958 B  REGISTER CRCIN_IDX[86] (wo): CRC Input Data Array Register
0x40441958 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x4044195C B  REGISTER CRCIN_IDX[87] (wo): CRC Input Data Array Register
0x4044195C C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441960 B  REGISTER CRCIN_IDX[88] (wo): CRC Input Data Array Register
0x40441960 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441964 B  REGISTER CRCIN_IDX[89] (wo): CRC Input Data Array Register
0x40441964 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441968 B  REGISTER CRCIN_IDX[90] (wo): CRC Input Data Array Register
0x40441968 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x4044196C B  REGISTER CRCIN_IDX[91] (wo): CRC Input Data Array Register
0x4044196C C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441970 B  REGISTER CRCIN_IDX[92] (wo): CRC Input Data Array Register
0x40441970 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441974 B  REGISTER CRCIN_IDX[93] (wo): CRC Input Data Array Register
0x40441974 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441978 B  REGISTER CRCIN_IDX[94] (wo): CRC Input Data Array Register
0x40441978 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x4044197C B  REGISTER CRCIN_IDX[95] (wo): CRC Input Data Array Register
0x4044197C C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441980 B  REGISTER CRCIN_IDX[96] (wo): CRC Input Data Array Register
0x40441980 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441984 B  REGISTER CRCIN_IDX[97] (wo): CRC Input Data Array Register
0x40441984 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441988 B  REGISTER CRCIN_IDX[98] (wo): CRC Input Data Array Register
0x40441988 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x4044198C B  REGISTER CRCIN_IDX[99] (wo): CRC Input Data Array Register
0x4044198C C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441990 B  REGISTER CRCIN_IDX[100] (wo): CRC Input Data Array Register
0x40441990 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441994 B  REGISTER CRCIN_IDX[101] (wo): CRC Input Data Array Register
0x40441994 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441998 B  REGISTER CRCIN_IDX[102] (wo): CRC Input Data Array Register
0x40441998 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x4044199C B  REGISTER CRCIN_IDX[103] (wo): CRC Input Data Array Register
0x4044199C C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x404419A0 B  REGISTER CRCIN_IDX[104] (wo): CRC Input Data Array Register
0x404419A0 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x404419A4 B  REGISTER CRCIN_IDX[105] (wo): CRC Input Data Array Register
0x404419A4 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x404419A8 B  REGISTER CRCIN_IDX[106] (wo): CRC Input Data Array Register
0x404419A8 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x404419AC B  REGISTER CRCIN_IDX[107] (wo): CRC Input Data Array Register
0x404419AC C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x404419B0 B  REGISTER CRCIN_IDX[108] (wo): CRC Input Data Array Register
0x404419B0 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x404419B4 B  REGISTER CRCIN_IDX[109] (wo): CRC Input Data Array Register
0x404419B4 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x404419B8 B  REGISTER CRCIN_IDX[110] (wo): CRC Input Data Array Register
0x404419B8 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x404419BC B  REGISTER CRCIN_IDX[111] (wo): CRC Input Data Array Register
0x404419BC C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x404419C0 B  REGISTER CRCIN_IDX[112] (wo): CRC Input Data Array Register
0x404419C0 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x404419C4 B  REGISTER CRCIN_IDX[113] (wo): CRC Input Data Array Register
0x404419C4 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x404419C8 B  REGISTER CRCIN_IDX[114] (wo): CRC Input Data Array Register
0x404419C8 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x404419CC B  REGISTER CRCIN_IDX[115] (wo): CRC Input Data Array Register
0x404419CC C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x404419D0 B  REGISTER CRCIN_IDX[116] (wo): CRC Input Data Array Register
0x404419D0 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x404419D4 B  REGISTER CRCIN_IDX[117] (wo): CRC Input Data Array Register
0x404419D4 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x404419D8 B  REGISTER CRCIN_IDX[118] (wo): CRC Input Data Array Register
0x404419D8 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x404419DC B  REGISTER CRCIN_IDX[119] (wo): CRC Input Data Array Register
0x404419DC C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x404419E0 B  REGISTER CRCIN_IDX[120] (wo): CRC Input Data Array Register
0x404419E0 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x404419E4 B  REGISTER CRCIN_IDX[121] (wo): CRC Input Data Array Register
0x404419E4 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x404419E8 B  REGISTER CRCIN_IDX[122] (wo): CRC Input Data Array Register
0x404419E8 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x404419EC B  REGISTER CRCIN_IDX[123] (wo): CRC Input Data Array Register
0x404419EC C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x404419F0 B  REGISTER CRCIN_IDX[124] (wo): CRC Input Data Array Register
0x404419F0 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x404419F4 B  REGISTER CRCIN_IDX[125] (wo): CRC Input Data Array Register
0x404419F4 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x404419F8 B  REGISTER CRCIN_IDX[126] (wo): CRC Input Data Array Register
0x404419F8 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x404419FC B  REGISTER CRCIN_IDX[127] (wo): CRC Input Data Array Register
0x404419FC C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441A00 B  REGISTER CRCIN_IDX[128] (wo): CRC Input Data Array Register
0x40441A00 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441A04 B  REGISTER CRCIN_IDX[129] (wo): CRC Input Data Array Register
0x40441A04 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441A08 B  REGISTER CRCIN_IDX[130] (wo): CRC Input Data Array Register
0x40441A08 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441A0C B  REGISTER CRCIN_IDX[131] (wo): CRC Input Data Array Register
0x40441A0C C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441A10 B  REGISTER CRCIN_IDX[132] (wo): CRC Input Data Array Register
0x40441A10 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441A14 B  REGISTER CRCIN_IDX[133] (wo): CRC Input Data Array Register
0x40441A14 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441A18 B  REGISTER CRCIN_IDX[134] (wo): CRC Input Data Array Register
0x40441A18 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441A1C B  REGISTER CRCIN_IDX[135] (wo): CRC Input Data Array Register
0x40441A1C C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441A20 B  REGISTER CRCIN_IDX[136] (wo): CRC Input Data Array Register
0x40441A20 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441A24 B  REGISTER CRCIN_IDX[137] (wo): CRC Input Data Array Register
0x40441A24 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441A28 B  REGISTER CRCIN_IDX[138] (wo): CRC Input Data Array Register
0x40441A28 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441A2C B  REGISTER CRCIN_IDX[139] (wo): CRC Input Data Array Register
0x40441A2C C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441A30 B  REGISTER CRCIN_IDX[140] (wo): CRC Input Data Array Register
0x40441A30 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441A34 B  REGISTER CRCIN_IDX[141] (wo): CRC Input Data Array Register
0x40441A34 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441A38 B  REGISTER CRCIN_IDX[142] (wo): CRC Input Data Array Register
0x40441A38 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441A3C B  REGISTER CRCIN_IDX[143] (wo): CRC Input Data Array Register
0x40441A3C C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441A40 B  REGISTER CRCIN_IDX[144] (wo): CRC Input Data Array Register
0x40441A40 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441A44 B  REGISTER CRCIN_IDX[145] (wo): CRC Input Data Array Register
0x40441A44 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441A48 B  REGISTER CRCIN_IDX[146] (wo): CRC Input Data Array Register
0x40441A48 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441A4C B  REGISTER CRCIN_IDX[147] (wo): CRC Input Data Array Register
0x40441A4C C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441A50 B  REGISTER CRCIN_IDX[148] (wo): CRC Input Data Array Register
0x40441A50 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441A54 B  REGISTER CRCIN_IDX[149] (wo): CRC Input Data Array Register
0x40441A54 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441A58 B  REGISTER CRCIN_IDX[150] (wo): CRC Input Data Array Register
0x40441A58 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441A5C B  REGISTER CRCIN_IDX[151] (wo): CRC Input Data Array Register
0x40441A5C C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441A60 B  REGISTER CRCIN_IDX[152] (wo): CRC Input Data Array Register
0x40441A60 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441A64 B  REGISTER CRCIN_IDX[153] (wo): CRC Input Data Array Register
0x40441A64 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441A68 B  REGISTER CRCIN_IDX[154] (wo): CRC Input Data Array Register
0x40441A68 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441A6C B  REGISTER CRCIN_IDX[155] (wo): CRC Input Data Array Register
0x40441A6C C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441A70 B  REGISTER CRCIN_IDX[156] (wo): CRC Input Data Array Register
0x40441A70 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441A74 B  REGISTER CRCIN_IDX[157] (wo): CRC Input Data Array Register
0x40441A74 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441A78 B  REGISTER CRCIN_IDX[158] (wo): CRC Input Data Array Register
0x40441A78 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441A7C B  REGISTER CRCIN_IDX[159] (wo): CRC Input Data Array Register
0x40441A7C C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441A80 B  REGISTER CRCIN_IDX[160] (wo): CRC Input Data Array Register
0x40441A80 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441A84 B  REGISTER CRCIN_IDX[161] (wo): CRC Input Data Array Register
0x40441A84 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441A88 B  REGISTER CRCIN_IDX[162] (wo): CRC Input Data Array Register
0x40441A88 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441A8C B  REGISTER CRCIN_IDX[163] (wo): CRC Input Data Array Register
0x40441A8C C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441A90 B  REGISTER CRCIN_IDX[164] (wo): CRC Input Data Array Register
0x40441A90 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441A94 B  REGISTER CRCIN_IDX[165] (wo): CRC Input Data Array Register
0x40441A94 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441A98 B  REGISTER CRCIN_IDX[166] (wo): CRC Input Data Array Register
0x40441A98 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441A9C B  REGISTER CRCIN_IDX[167] (wo): CRC Input Data Array Register
0x40441A9C C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441AA0 B  REGISTER CRCIN_IDX[168] (wo): CRC Input Data Array Register
0x40441AA0 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441AA4 B  REGISTER CRCIN_IDX[169] (wo): CRC Input Data Array Register
0x40441AA4 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441AA8 B  REGISTER CRCIN_IDX[170] (wo): CRC Input Data Array Register
0x40441AA8 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441AAC B  REGISTER CRCIN_IDX[171] (wo): CRC Input Data Array Register
0x40441AAC C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441AB0 B  REGISTER CRCIN_IDX[172] (wo): CRC Input Data Array Register
0x40441AB0 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441AB4 B  REGISTER CRCIN_IDX[173] (wo): CRC Input Data Array Register
0x40441AB4 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441AB8 B  REGISTER CRCIN_IDX[174] (wo): CRC Input Data Array Register
0x40441AB8 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441ABC B  REGISTER CRCIN_IDX[175] (wo): CRC Input Data Array Register
0x40441ABC C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441AC0 B  REGISTER CRCIN_IDX[176] (wo): CRC Input Data Array Register
0x40441AC0 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441AC4 B  REGISTER CRCIN_IDX[177] (wo): CRC Input Data Array Register
0x40441AC4 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441AC8 B  REGISTER CRCIN_IDX[178] (wo): CRC Input Data Array Register
0x40441AC8 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441ACC B  REGISTER CRCIN_IDX[179] (wo): CRC Input Data Array Register
0x40441ACC C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441AD0 B  REGISTER CRCIN_IDX[180] (wo): CRC Input Data Array Register
0x40441AD0 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441AD4 B  REGISTER CRCIN_IDX[181] (wo): CRC Input Data Array Register
0x40441AD4 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441AD8 B  REGISTER CRCIN_IDX[182] (wo): CRC Input Data Array Register
0x40441AD8 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441ADC B  REGISTER CRCIN_IDX[183] (wo): CRC Input Data Array Register
0x40441ADC C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441AE0 B  REGISTER CRCIN_IDX[184] (wo): CRC Input Data Array Register
0x40441AE0 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441AE4 B  REGISTER CRCIN_IDX[185] (wo): CRC Input Data Array Register
0x40441AE4 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441AE8 B  REGISTER CRCIN_IDX[186] (wo): CRC Input Data Array Register
0x40441AE8 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441AEC B  REGISTER CRCIN_IDX[187] (wo): CRC Input Data Array Register
0x40441AEC C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441AF0 B  REGISTER CRCIN_IDX[188] (wo): CRC Input Data Array Register
0x40441AF0 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441AF4 B  REGISTER CRCIN_IDX[189] (wo): CRC Input Data Array Register
0x40441AF4 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441AF8 B  REGISTER CRCIN_IDX[190] (wo): CRC Input Data Array Register
0x40441AF8 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441AFC B  REGISTER CRCIN_IDX[191] (wo): CRC Input Data Array Register
0x40441AFC C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441B00 B  REGISTER CRCIN_IDX[192] (wo): CRC Input Data Array Register
0x40441B00 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441B04 B  REGISTER CRCIN_IDX[193] (wo): CRC Input Data Array Register
0x40441B04 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441B08 B  REGISTER CRCIN_IDX[194] (wo): CRC Input Data Array Register
0x40441B08 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441B0C B  REGISTER CRCIN_IDX[195] (wo): CRC Input Data Array Register
0x40441B0C C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441B10 B  REGISTER CRCIN_IDX[196] (wo): CRC Input Data Array Register
0x40441B10 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441B14 B  REGISTER CRCIN_IDX[197] (wo): CRC Input Data Array Register
0x40441B14 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441B18 B  REGISTER CRCIN_IDX[198] (wo): CRC Input Data Array Register
0x40441B18 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441B1C B  REGISTER CRCIN_IDX[199] (wo): CRC Input Data Array Register
0x40441B1C C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441B20 B  REGISTER CRCIN_IDX[200] (wo): CRC Input Data Array Register
0x40441B20 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441B24 B  REGISTER CRCIN_IDX[201] (wo): CRC Input Data Array Register
0x40441B24 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441B28 B  REGISTER CRCIN_IDX[202] (wo): CRC Input Data Array Register
0x40441B28 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441B2C B  REGISTER CRCIN_IDX[203] (wo): CRC Input Data Array Register
0x40441B2C C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441B30 B  REGISTER CRCIN_IDX[204] (wo): CRC Input Data Array Register
0x40441B30 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441B34 B  REGISTER CRCIN_IDX[205] (wo): CRC Input Data Array Register
0x40441B34 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441B38 B  REGISTER CRCIN_IDX[206] (wo): CRC Input Data Array Register
0x40441B38 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441B3C B  REGISTER CRCIN_IDX[207] (wo): CRC Input Data Array Register
0x40441B3C C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441B40 B  REGISTER CRCIN_IDX[208] (wo): CRC Input Data Array Register
0x40441B40 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441B44 B  REGISTER CRCIN_IDX[209] (wo): CRC Input Data Array Register
0x40441B44 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441B48 B  REGISTER CRCIN_IDX[210] (wo): CRC Input Data Array Register
0x40441B48 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441B4C B  REGISTER CRCIN_IDX[211] (wo): CRC Input Data Array Register
0x40441B4C C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441B50 B  REGISTER CRCIN_IDX[212] (wo): CRC Input Data Array Register
0x40441B50 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441B54 B  REGISTER CRCIN_IDX[213] (wo): CRC Input Data Array Register
0x40441B54 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441B58 B  REGISTER CRCIN_IDX[214] (wo): CRC Input Data Array Register
0x40441B58 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441B5C B  REGISTER CRCIN_IDX[215] (wo): CRC Input Data Array Register
0x40441B5C C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441B60 B  REGISTER CRCIN_IDX[216] (wo): CRC Input Data Array Register
0x40441B60 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441B64 B  REGISTER CRCIN_IDX[217] (wo): CRC Input Data Array Register
0x40441B64 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441B68 B  REGISTER CRCIN_IDX[218] (wo): CRC Input Data Array Register
0x40441B68 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441B6C B  REGISTER CRCIN_IDX[219] (wo): CRC Input Data Array Register
0x40441B6C C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441B70 B  REGISTER CRCIN_IDX[220] (wo): CRC Input Data Array Register
0x40441B70 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441B74 B  REGISTER CRCIN_IDX[221] (wo): CRC Input Data Array Register
0x40441B74 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441B78 B  REGISTER CRCIN_IDX[222] (wo): CRC Input Data Array Register
0x40441B78 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441B7C B  REGISTER CRCIN_IDX[223] (wo): CRC Input Data Array Register
0x40441B7C C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441B80 B  REGISTER CRCIN_IDX[224] (wo): CRC Input Data Array Register
0x40441B80 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441B84 B  REGISTER CRCIN_IDX[225] (wo): CRC Input Data Array Register
0x40441B84 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441B88 B  REGISTER CRCIN_IDX[226] (wo): CRC Input Data Array Register
0x40441B88 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441B8C B  REGISTER CRCIN_IDX[227] (wo): CRC Input Data Array Register
0x40441B8C C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441B90 B  REGISTER CRCIN_IDX[228] (wo): CRC Input Data Array Register
0x40441B90 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441B94 B  REGISTER CRCIN_IDX[229] (wo): CRC Input Data Array Register
0x40441B94 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441B98 B  REGISTER CRCIN_IDX[230] (wo): CRC Input Data Array Register
0x40441B98 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441B9C B  REGISTER CRCIN_IDX[231] (wo): CRC Input Data Array Register
0x40441B9C C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441BA0 B  REGISTER CRCIN_IDX[232] (wo): CRC Input Data Array Register
0x40441BA0 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441BA4 B  REGISTER CRCIN_IDX[233] (wo): CRC Input Data Array Register
0x40441BA4 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441BA8 B  REGISTER CRCIN_IDX[234] (wo): CRC Input Data Array Register
0x40441BA8 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441BAC B  REGISTER CRCIN_IDX[235] (wo): CRC Input Data Array Register
0x40441BAC C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441BB0 B  REGISTER CRCIN_IDX[236] (wo): CRC Input Data Array Register
0x40441BB0 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441BB4 B  REGISTER CRCIN_IDX[237] (wo): CRC Input Data Array Register
0x40441BB4 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441BB8 B  REGISTER CRCIN_IDX[238] (wo): CRC Input Data Array Register
0x40441BB8 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441BBC B  REGISTER CRCIN_IDX[239] (wo): CRC Input Data Array Register
0x40441BBC C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441BC0 B  REGISTER CRCIN_IDX[240] (wo): CRC Input Data Array Register
0x40441BC0 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441BC4 B  REGISTER CRCIN_IDX[241] (wo): CRC Input Data Array Register
0x40441BC4 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441BC8 B  REGISTER CRCIN_IDX[242] (wo): CRC Input Data Array Register
0x40441BC8 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441BCC B  REGISTER CRCIN_IDX[243] (wo): CRC Input Data Array Register
0x40441BCC C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441BD0 B  REGISTER CRCIN_IDX[244] (wo): CRC Input Data Array Register
0x40441BD0 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441BD4 B  REGISTER CRCIN_IDX[245] (wo): CRC Input Data Array Register
0x40441BD4 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441BD8 B  REGISTER CRCIN_IDX[246] (wo): CRC Input Data Array Register
0x40441BD8 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441BDC B  REGISTER CRCIN_IDX[247] (wo): CRC Input Data Array Register
0x40441BDC C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441BE0 B  REGISTER CRCIN_IDX[248] (wo): CRC Input Data Array Register
0x40441BE0 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441BE4 B  REGISTER CRCIN_IDX[249] (wo): CRC Input Data Array Register
0x40441BE4 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441BE8 B  REGISTER CRCIN_IDX[250] (wo): CRC Input Data Array Register
0x40441BE8 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441BEC B  REGISTER CRCIN_IDX[251] (wo): CRC Input Data Array Register
0x40441BEC C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441BF0 B  REGISTER CRCIN_IDX[252] (wo): CRC Input Data Array Register
0x40441BF0 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441BF4 B  REGISTER CRCIN_IDX[253] (wo): CRC Input Data Array Register
0x40441BF4 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441BF8 B  REGISTER CRCIN_IDX[254] (wo): CRC Input Data Array Register
0x40441BF8 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441BFC B  REGISTER CRCIN_IDX[255] (wo): CRC Input Data Array Register
0x40441BFC C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441C00 B  REGISTER CRCIN_IDX[256] (wo): CRC Input Data Array Register
0x40441C00 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441C04 B  REGISTER CRCIN_IDX[257] (wo): CRC Input Data Array Register
0x40441C04 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441C08 B  REGISTER CRCIN_IDX[258] (wo): CRC Input Data Array Register
0x40441C08 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441C0C B  REGISTER CRCIN_IDX[259] (wo): CRC Input Data Array Register
0x40441C0C C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441C10 B  REGISTER CRCIN_IDX[260] (wo): CRC Input Data Array Register
0x40441C10 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441C14 B  REGISTER CRCIN_IDX[261] (wo): CRC Input Data Array Register
0x40441C14 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441C18 B  REGISTER CRCIN_IDX[262] (wo): CRC Input Data Array Register
0x40441C18 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441C1C B  REGISTER CRCIN_IDX[263] (wo): CRC Input Data Array Register
0x40441C1C C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441C20 B  REGISTER CRCIN_IDX[264] (wo): CRC Input Data Array Register
0x40441C20 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441C24 B  REGISTER CRCIN_IDX[265] (wo): CRC Input Data Array Register
0x40441C24 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441C28 B  REGISTER CRCIN_IDX[266] (wo): CRC Input Data Array Register
0x40441C28 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441C2C B  REGISTER CRCIN_IDX[267] (wo): CRC Input Data Array Register
0x40441C2C C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441C30 B  REGISTER CRCIN_IDX[268] (wo): CRC Input Data Array Register
0x40441C30 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441C34 B  REGISTER CRCIN_IDX[269] (wo): CRC Input Data Array Register
0x40441C34 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441C38 B  REGISTER CRCIN_IDX[270] (wo): CRC Input Data Array Register
0x40441C38 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441C3C B  REGISTER CRCIN_IDX[271] (wo): CRC Input Data Array Register
0x40441C3C C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441C40 B  REGISTER CRCIN_IDX[272] (wo): CRC Input Data Array Register
0x40441C40 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441C44 B  REGISTER CRCIN_IDX[273] (wo): CRC Input Data Array Register
0x40441C44 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441C48 B  REGISTER CRCIN_IDX[274] (wo): CRC Input Data Array Register
0x40441C48 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441C4C B  REGISTER CRCIN_IDX[275] (wo): CRC Input Data Array Register
0x40441C4C C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441C50 B  REGISTER CRCIN_IDX[276] (wo): CRC Input Data Array Register
0x40441C50 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441C54 B  REGISTER CRCIN_IDX[277] (wo): CRC Input Data Array Register
0x40441C54 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441C58 B  REGISTER CRCIN_IDX[278] (wo): CRC Input Data Array Register
0x40441C58 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441C5C B  REGISTER CRCIN_IDX[279] (wo): CRC Input Data Array Register
0x40441C5C C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441C60 B  REGISTER CRCIN_IDX[280] (wo): CRC Input Data Array Register
0x40441C60 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441C64 B  REGISTER CRCIN_IDX[281] (wo): CRC Input Data Array Register
0x40441C64 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441C68 B  REGISTER CRCIN_IDX[282] (wo): CRC Input Data Array Register
0x40441C68 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441C6C B  REGISTER CRCIN_IDX[283] (wo): CRC Input Data Array Register
0x40441C6C C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441C70 B  REGISTER CRCIN_IDX[284] (wo): CRC Input Data Array Register
0x40441C70 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441C74 B  REGISTER CRCIN_IDX[285] (wo): CRC Input Data Array Register
0x40441C74 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441C78 B  REGISTER CRCIN_IDX[286] (wo): CRC Input Data Array Register
0x40441C78 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441C7C B  REGISTER CRCIN_IDX[287] (wo): CRC Input Data Array Register
0x40441C7C C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441C80 B  REGISTER CRCIN_IDX[288] (wo): CRC Input Data Array Register
0x40441C80 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441C84 B  REGISTER CRCIN_IDX[289] (wo): CRC Input Data Array Register
0x40441C84 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441C88 B  REGISTER CRCIN_IDX[290] (wo): CRC Input Data Array Register
0x40441C88 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441C8C B  REGISTER CRCIN_IDX[291] (wo): CRC Input Data Array Register
0x40441C8C C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441C90 B  REGISTER CRCIN_IDX[292] (wo): CRC Input Data Array Register
0x40441C90 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441C94 B  REGISTER CRCIN_IDX[293] (wo): CRC Input Data Array Register
0x40441C94 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441C98 B  REGISTER CRCIN_IDX[294] (wo): CRC Input Data Array Register
0x40441C98 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441C9C B  REGISTER CRCIN_IDX[295] (wo): CRC Input Data Array Register
0x40441C9C C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441CA0 B  REGISTER CRCIN_IDX[296] (wo): CRC Input Data Array Register
0x40441CA0 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441CA4 B  REGISTER CRCIN_IDX[297] (wo): CRC Input Data Array Register
0x40441CA4 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441CA8 B  REGISTER CRCIN_IDX[298] (wo): CRC Input Data Array Register
0x40441CA8 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441CAC B  REGISTER CRCIN_IDX[299] (wo): CRC Input Data Array Register
0x40441CAC C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441CB0 B  REGISTER CRCIN_IDX[300] (wo): CRC Input Data Array Register
0x40441CB0 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441CB4 B  REGISTER CRCIN_IDX[301] (wo): CRC Input Data Array Register
0x40441CB4 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441CB8 B  REGISTER CRCIN_IDX[302] (wo): CRC Input Data Array Register
0x40441CB8 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441CBC B  REGISTER CRCIN_IDX[303] (wo): CRC Input Data Array Register
0x40441CBC C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441CC0 B  REGISTER CRCIN_IDX[304] (wo): CRC Input Data Array Register
0x40441CC0 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441CC4 B  REGISTER CRCIN_IDX[305] (wo): CRC Input Data Array Register
0x40441CC4 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441CC8 B  REGISTER CRCIN_IDX[306] (wo): CRC Input Data Array Register
0x40441CC8 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441CCC B  REGISTER CRCIN_IDX[307] (wo): CRC Input Data Array Register
0x40441CCC C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441CD0 B  REGISTER CRCIN_IDX[308] (wo): CRC Input Data Array Register
0x40441CD0 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441CD4 B  REGISTER CRCIN_IDX[309] (wo): CRC Input Data Array Register
0x40441CD4 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441CD8 B  REGISTER CRCIN_IDX[310] (wo): CRC Input Data Array Register
0x40441CD8 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441CDC B  REGISTER CRCIN_IDX[311] (wo): CRC Input Data Array Register
0x40441CDC C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441CE0 B  REGISTER CRCIN_IDX[312] (wo): CRC Input Data Array Register
0x40441CE0 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441CE4 B  REGISTER CRCIN_IDX[313] (wo): CRC Input Data Array Register
0x40441CE4 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441CE8 B  REGISTER CRCIN_IDX[314] (wo): CRC Input Data Array Register
0x40441CE8 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441CEC B  REGISTER CRCIN_IDX[315] (wo): CRC Input Data Array Register
0x40441CEC C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441CF0 B  REGISTER CRCIN_IDX[316] (wo): CRC Input Data Array Register
0x40441CF0 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441CF4 B  REGISTER CRCIN_IDX[317] (wo): CRC Input Data Array Register
0x40441CF4 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441CF8 B  REGISTER CRCIN_IDX[318] (wo): CRC Input Data Array Register
0x40441CF8 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441CFC B  REGISTER CRCIN_IDX[319] (wo): CRC Input Data Array Register
0x40441CFC C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441D00 B  REGISTER CRCIN_IDX[320] (wo): CRC Input Data Array Register
0x40441D00 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441D04 B  REGISTER CRCIN_IDX[321] (wo): CRC Input Data Array Register
0x40441D04 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441D08 B  REGISTER CRCIN_IDX[322] (wo): CRC Input Data Array Register
0x40441D08 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441D0C B  REGISTER CRCIN_IDX[323] (wo): CRC Input Data Array Register
0x40441D0C C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441D10 B  REGISTER CRCIN_IDX[324] (wo): CRC Input Data Array Register
0x40441D10 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441D14 B  REGISTER CRCIN_IDX[325] (wo): CRC Input Data Array Register
0x40441D14 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441D18 B  REGISTER CRCIN_IDX[326] (wo): CRC Input Data Array Register
0x40441D18 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441D1C B  REGISTER CRCIN_IDX[327] (wo): CRC Input Data Array Register
0x40441D1C C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441D20 B  REGISTER CRCIN_IDX[328] (wo): CRC Input Data Array Register
0x40441D20 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441D24 B  REGISTER CRCIN_IDX[329] (wo): CRC Input Data Array Register
0x40441D24 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441D28 B  REGISTER CRCIN_IDX[330] (wo): CRC Input Data Array Register
0x40441D28 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441D2C B  REGISTER CRCIN_IDX[331] (wo): CRC Input Data Array Register
0x40441D2C C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441D30 B  REGISTER CRCIN_IDX[332] (wo): CRC Input Data Array Register
0x40441D30 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441D34 B  REGISTER CRCIN_IDX[333] (wo): CRC Input Data Array Register
0x40441D34 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441D38 B  REGISTER CRCIN_IDX[334] (wo): CRC Input Data Array Register
0x40441D38 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441D3C B  REGISTER CRCIN_IDX[335] (wo): CRC Input Data Array Register
0x40441D3C C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441D40 B  REGISTER CRCIN_IDX[336] (wo): CRC Input Data Array Register
0x40441D40 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441D44 B  REGISTER CRCIN_IDX[337] (wo): CRC Input Data Array Register
0x40441D44 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441D48 B  REGISTER CRCIN_IDX[338] (wo): CRC Input Data Array Register
0x40441D48 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441D4C B  REGISTER CRCIN_IDX[339] (wo): CRC Input Data Array Register
0x40441D4C C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441D50 B  REGISTER CRCIN_IDX[340] (wo): CRC Input Data Array Register
0x40441D50 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441D54 B  REGISTER CRCIN_IDX[341] (wo): CRC Input Data Array Register
0x40441D54 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441D58 B  REGISTER CRCIN_IDX[342] (wo): CRC Input Data Array Register
0x40441D58 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441D5C B  REGISTER CRCIN_IDX[343] (wo): CRC Input Data Array Register
0x40441D5C C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441D60 B  REGISTER CRCIN_IDX[344] (wo): CRC Input Data Array Register
0x40441D60 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441D64 B  REGISTER CRCIN_IDX[345] (wo): CRC Input Data Array Register
0x40441D64 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441D68 B  REGISTER CRCIN_IDX[346] (wo): CRC Input Data Array Register
0x40441D68 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441D6C B  REGISTER CRCIN_IDX[347] (wo): CRC Input Data Array Register
0x40441D6C C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441D70 B  REGISTER CRCIN_IDX[348] (wo): CRC Input Data Array Register
0x40441D70 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441D74 B  REGISTER CRCIN_IDX[349] (wo): CRC Input Data Array Register
0x40441D74 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441D78 B  REGISTER CRCIN_IDX[350] (wo): CRC Input Data Array Register
0x40441D78 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441D7C B  REGISTER CRCIN_IDX[351] (wo): CRC Input Data Array Register
0x40441D7C C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441D80 B  REGISTER CRCIN_IDX[352] (wo): CRC Input Data Array Register
0x40441D80 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441D84 B  REGISTER CRCIN_IDX[353] (wo): CRC Input Data Array Register
0x40441D84 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441D88 B  REGISTER CRCIN_IDX[354] (wo): CRC Input Data Array Register
0x40441D88 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441D8C B  REGISTER CRCIN_IDX[355] (wo): CRC Input Data Array Register
0x40441D8C C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441D90 B  REGISTER CRCIN_IDX[356] (wo): CRC Input Data Array Register
0x40441D90 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441D94 B  REGISTER CRCIN_IDX[357] (wo): CRC Input Data Array Register
0x40441D94 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441D98 B  REGISTER CRCIN_IDX[358] (wo): CRC Input Data Array Register
0x40441D98 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441D9C B  REGISTER CRCIN_IDX[359] (wo): CRC Input Data Array Register
0x40441D9C C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441DA0 B  REGISTER CRCIN_IDX[360] (wo): CRC Input Data Array Register
0x40441DA0 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441DA4 B  REGISTER CRCIN_IDX[361] (wo): CRC Input Data Array Register
0x40441DA4 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441DA8 B  REGISTER CRCIN_IDX[362] (wo): CRC Input Data Array Register
0x40441DA8 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441DAC B  REGISTER CRCIN_IDX[363] (wo): CRC Input Data Array Register
0x40441DAC C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441DB0 B  REGISTER CRCIN_IDX[364] (wo): CRC Input Data Array Register
0x40441DB0 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441DB4 B  REGISTER CRCIN_IDX[365] (wo): CRC Input Data Array Register
0x40441DB4 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441DB8 B  REGISTER CRCIN_IDX[366] (wo): CRC Input Data Array Register
0x40441DB8 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441DBC B  REGISTER CRCIN_IDX[367] (wo): CRC Input Data Array Register
0x40441DBC C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441DC0 B  REGISTER CRCIN_IDX[368] (wo): CRC Input Data Array Register
0x40441DC0 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441DC4 B  REGISTER CRCIN_IDX[369] (wo): CRC Input Data Array Register
0x40441DC4 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441DC8 B  REGISTER CRCIN_IDX[370] (wo): CRC Input Data Array Register
0x40441DC8 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441DCC B  REGISTER CRCIN_IDX[371] (wo): CRC Input Data Array Register
0x40441DCC C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441DD0 B  REGISTER CRCIN_IDX[372] (wo): CRC Input Data Array Register
0x40441DD0 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441DD4 B  REGISTER CRCIN_IDX[373] (wo): CRC Input Data Array Register
0x40441DD4 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441DD8 B  REGISTER CRCIN_IDX[374] (wo): CRC Input Data Array Register
0x40441DD8 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441DDC B  REGISTER CRCIN_IDX[375] (wo): CRC Input Data Array Register
0x40441DDC C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441DE0 B  REGISTER CRCIN_IDX[376] (wo): CRC Input Data Array Register
0x40441DE0 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441DE4 B  REGISTER CRCIN_IDX[377] (wo): CRC Input Data Array Register
0x40441DE4 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441DE8 B  REGISTER CRCIN_IDX[378] (wo): CRC Input Data Array Register
0x40441DE8 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441DEC B  REGISTER CRCIN_IDX[379] (wo): CRC Input Data Array Register
0x40441DEC C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441DF0 B  REGISTER CRCIN_IDX[380] (wo): CRC Input Data Array Register
0x40441DF0 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441DF4 B  REGISTER CRCIN_IDX[381] (wo): CRC Input Data Array Register
0x40441DF4 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441DF8 B  REGISTER CRCIN_IDX[382] (wo): CRC Input Data Array Register
0x40441DF8 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441DFC B  REGISTER CRCIN_IDX[383] (wo): CRC Input Data Array Register
0x40441DFC C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441E00 B  REGISTER CRCIN_IDX[384] (wo): CRC Input Data Array Register
0x40441E00 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441E04 B  REGISTER CRCIN_IDX[385] (wo): CRC Input Data Array Register
0x40441E04 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441E08 B  REGISTER CRCIN_IDX[386] (wo): CRC Input Data Array Register
0x40441E08 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441E0C B  REGISTER CRCIN_IDX[387] (wo): CRC Input Data Array Register
0x40441E0C C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441E10 B  REGISTER CRCIN_IDX[388] (wo): CRC Input Data Array Register
0x40441E10 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441E14 B  REGISTER CRCIN_IDX[389] (wo): CRC Input Data Array Register
0x40441E14 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441E18 B  REGISTER CRCIN_IDX[390] (wo): CRC Input Data Array Register
0x40441E18 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441E1C B  REGISTER CRCIN_IDX[391] (wo): CRC Input Data Array Register
0x40441E1C C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441E20 B  REGISTER CRCIN_IDX[392] (wo): CRC Input Data Array Register
0x40441E20 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441E24 B  REGISTER CRCIN_IDX[393] (wo): CRC Input Data Array Register
0x40441E24 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441E28 B  REGISTER CRCIN_IDX[394] (wo): CRC Input Data Array Register
0x40441E28 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441E2C B  REGISTER CRCIN_IDX[395] (wo): CRC Input Data Array Register
0x40441E2C C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441E30 B  REGISTER CRCIN_IDX[396] (wo): CRC Input Data Array Register
0x40441E30 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441E34 B  REGISTER CRCIN_IDX[397] (wo): CRC Input Data Array Register
0x40441E34 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441E38 B  REGISTER CRCIN_IDX[398] (wo): CRC Input Data Array Register
0x40441E38 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441E3C B  REGISTER CRCIN_IDX[399] (wo): CRC Input Data Array Register
0x40441E3C C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441E40 B  REGISTER CRCIN_IDX[400] (wo): CRC Input Data Array Register
0x40441E40 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441E44 B  REGISTER CRCIN_IDX[401] (wo): CRC Input Data Array Register
0x40441E44 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441E48 B  REGISTER CRCIN_IDX[402] (wo): CRC Input Data Array Register
0x40441E48 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441E4C B  REGISTER CRCIN_IDX[403] (wo): CRC Input Data Array Register
0x40441E4C C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441E50 B  REGISTER CRCIN_IDX[404] (wo): CRC Input Data Array Register
0x40441E50 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441E54 B  REGISTER CRCIN_IDX[405] (wo): CRC Input Data Array Register
0x40441E54 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441E58 B  REGISTER CRCIN_IDX[406] (wo): CRC Input Data Array Register
0x40441E58 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441E5C B  REGISTER CRCIN_IDX[407] (wo): CRC Input Data Array Register
0x40441E5C C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441E60 B  REGISTER CRCIN_IDX[408] (wo): CRC Input Data Array Register
0x40441E60 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441E64 B  REGISTER CRCIN_IDX[409] (wo): CRC Input Data Array Register
0x40441E64 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441E68 B  REGISTER CRCIN_IDX[410] (wo): CRC Input Data Array Register
0x40441E68 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441E6C B  REGISTER CRCIN_IDX[411] (wo): CRC Input Data Array Register
0x40441E6C C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441E70 B  REGISTER CRCIN_IDX[412] (wo): CRC Input Data Array Register
0x40441E70 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441E74 B  REGISTER CRCIN_IDX[413] (wo): CRC Input Data Array Register
0x40441E74 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441E78 B  REGISTER CRCIN_IDX[414] (wo): CRC Input Data Array Register
0x40441E78 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441E7C B  REGISTER CRCIN_IDX[415] (wo): CRC Input Data Array Register
0x40441E7C C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441E80 B  REGISTER CRCIN_IDX[416] (wo): CRC Input Data Array Register
0x40441E80 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441E84 B  REGISTER CRCIN_IDX[417] (wo): CRC Input Data Array Register
0x40441E84 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441E88 B  REGISTER CRCIN_IDX[418] (wo): CRC Input Data Array Register
0x40441E88 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441E8C B  REGISTER CRCIN_IDX[419] (wo): CRC Input Data Array Register
0x40441E8C C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441E90 B  REGISTER CRCIN_IDX[420] (wo): CRC Input Data Array Register
0x40441E90 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441E94 B  REGISTER CRCIN_IDX[421] (wo): CRC Input Data Array Register
0x40441E94 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441E98 B  REGISTER CRCIN_IDX[422] (wo): CRC Input Data Array Register
0x40441E98 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441E9C B  REGISTER CRCIN_IDX[423] (wo): CRC Input Data Array Register
0x40441E9C C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441EA0 B  REGISTER CRCIN_IDX[424] (wo): CRC Input Data Array Register
0x40441EA0 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441EA4 B  REGISTER CRCIN_IDX[425] (wo): CRC Input Data Array Register
0x40441EA4 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441EA8 B  REGISTER CRCIN_IDX[426] (wo): CRC Input Data Array Register
0x40441EA8 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441EAC B  REGISTER CRCIN_IDX[427] (wo): CRC Input Data Array Register
0x40441EAC C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441EB0 B  REGISTER CRCIN_IDX[428] (wo): CRC Input Data Array Register
0x40441EB0 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441EB4 B  REGISTER CRCIN_IDX[429] (wo): CRC Input Data Array Register
0x40441EB4 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441EB8 B  REGISTER CRCIN_IDX[430] (wo): CRC Input Data Array Register
0x40441EB8 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441EBC B  REGISTER CRCIN_IDX[431] (wo): CRC Input Data Array Register
0x40441EBC C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441EC0 B  REGISTER CRCIN_IDX[432] (wo): CRC Input Data Array Register
0x40441EC0 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441EC4 B  REGISTER CRCIN_IDX[433] (wo): CRC Input Data Array Register
0x40441EC4 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441EC8 B  REGISTER CRCIN_IDX[434] (wo): CRC Input Data Array Register
0x40441EC8 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441ECC B  REGISTER CRCIN_IDX[435] (wo): CRC Input Data Array Register
0x40441ECC C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441ED0 B  REGISTER CRCIN_IDX[436] (wo): CRC Input Data Array Register
0x40441ED0 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441ED4 B  REGISTER CRCIN_IDX[437] (wo): CRC Input Data Array Register
0x40441ED4 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441ED8 B  REGISTER CRCIN_IDX[438] (wo): CRC Input Data Array Register
0x40441ED8 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441EDC B  REGISTER CRCIN_IDX[439] (wo): CRC Input Data Array Register
0x40441EDC C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441EE0 B  REGISTER CRCIN_IDX[440] (wo): CRC Input Data Array Register
0x40441EE0 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441EE4 B  REGISTER CRCIN_IDX[441] (wo): CRC Input Data Array Register
0x40441EE4 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441EE8 B  REGISTER CRCIN_IDX[442] (wo): CRC Input Data Array Register
0x40441EE8 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441EEC B  REGISTER CRCIN_IDX[443] (wo): CRC Input Data Array Register
0x40441EEC C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441EF0 B  REGISTER CRCIN_IDX[444] (wo): CRC Input Data Array Register
0x40441EF0 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441EF4 B  REGISTER CRCIN_IDX[445] (wo): CRC Input Data Array Register
0x40441EF4 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441EF8 B  REGISTER CRCIN_IDX[446] (wo): CRC Input Data Array Register
0x40441EF8 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441EFC B  REGISTER CRCIN_IDX[447] (wo): CRC Input Data Array Register
0x40441EFC C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441F00 B  REGISTER CRCIN_IDX[448] (wo): CRC Input Data Array Register
0x40441F00 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441F04 B  REGISTER CRCIN_IDX[449] (wo): CRC Input Data Array Register
0x40441F04 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441F08 B  REGISTER CRCIN_IDX[450] (wo): CRC Input Data Array Register
0x40441F08 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441F0C B  REGISTER CRCIN_IDX[451] (wo): CRC Input Data Array Register
0x40441F0C C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441F10 B  REGISTER CRCIN_IDX[452] (wo): CRC Input Data Array Register
0x40441F10 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441F14 B  REGISTER CRCIN_IDX[453] (wo): CRC Input Data Array Register
0x40441F14 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441F18 B  REGISTER CRCIN_IDX[454] (wo): CRC Input Data Array Register
0x40441F18 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441F1C B  REGISTER CRCIN_IDX[455] (wo): CRC Input Data Array Register
0x40441F1C C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441F20 B  REGISTER CRCIN_IDX[456] (wo): CRC Input Data Array Register
0x40441F20 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441F24 B  REGISTER CRCIN_IDX[457] (wo): CRC Input Data Array Register
0x40441F24 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441F28 B  REGISTER CRCIN_IDX[458] (wo): CRC Input Data Array Register
0x40441F28 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441F2C B  REGISTER CRCIN_IDX[459] (wo): CRC Input Data Array Register
0x40441F2C C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441F30 B  REGISTER CRCIN_IDX[460] (wo): CRC Input Data Array Register
0x40441F30 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441F34 B  REGISTER CRCIN_IDX[461] (wo): CRC Input Data Array Register
0x40441F34 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441F38 B  REGISTER CRCIN_IDX[462] (wo): CRC Input Data Array Register
0x40441F38 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441F3C B  REGISTER CRCIN_IDX[463] (wo): CRC Input Data Array Register
0x40441F3C C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441F40 B  REGISTER CRCIN_IDX[464] (wo): CRC Input Data Array Register
0x40441F40 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441F44 B  REGISTER CRCIN_IDX[465] (wo): CRC Input Data Array Register
0x40441F44 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441F48 B  REGISTER CRCIN_IDX[466] (wo): CRC Input Data Array Register
0x40441F48 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441F4C B  REGISTER CRCIN_IDX[467] (wo): CRC Input Data Array Register
0x40441F4C C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441F50 B  REGISTER CRCIN_IDX[468] (wo): CRC Input Data Array Register
0x40441F50 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441F54 B  REGISTER CRCIN_IDX[469] (wo): CRC Input Data Array Register
0x40441F54 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441F58 B  REGISTER CRCIN_IDX[470] (wo): CRC Input Data Array Register
0x40441F58 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441F5C B  REGISTER CRCIN_IDX[471] (wo): CRC Input Data Array Register
0x40441F5C C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441F60 B  REGISTER CRCIN_IDX[472] (wo): CRC Input Data Array Register
0x40441F60 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441F64 B  REGISTER CRCIN_IDX[473] (wo): CRC Input Data Array Register
0x40441F64 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441F68 B  REGISTER CRCIN_IDX[474] (wo): CRC Input Data Array Register
0x40441F68 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441F6C B  REGISTER CRCIN_IDX[475] (wo): CRC Input Data Array Register
0x40441F6C C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441F70 B  REGISTER CRCIN_IDX[476] (wo): CRC Input Data Array Register
0x40441F70 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441F74 B  REGISTER CRCIN_IDX[477] (wo): CRC Input Data Array Register
0x40441F74 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441F78 B  REGISTER CRCIN_IDX[478] (wo): CRC Input Data Array Register
0x40441F78 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441F7C B  REGISTER CRCIN_IDX[479] (wo): CRC Input Data Array Register
0x40441F7C C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441F80 B  REGISTER CRCIN_IDX[480] (wo): CRC Input Data Array Register
0x40441F80 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441F84 B  REGISTER CRCIN_IDX[481] (wo): CRC Input Data Array Register
0x40441F84 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441F88 B  REGISTER CRCIN_IDX[482] (wo): CRC Input Data Array Register
0x40441F88 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441F8C B  REGISTER CRCIN_IDX[483] (wo): CRC Input Data Array Register
0x40441F8C C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441F90 B  REGISTER CRCIN_IDX[484] (wo): CRC Input Data Array Register
0x40441F90 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441F94 B  REGISTER CRCIN_IDX[485] (wo): CRC Input Data Array Register
0x40441F94 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441F98 B  REGISTER CRCIN_IDX[486] (wo): CRC Input Data Array Register
0x40441F98 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441F9C B  REGISTER CRCIN_IDX[487] (wo): CRC Input Data Array Register
0x40441F9C C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441FA0 B  REGISTER CRCIN_IDX[488] (wo): CRC Input Data Array Register
0x40441FA0 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441FA4 B  REGISTER CRCIN_IDX[489] (wo): CRC Input Data Array Register
0x40441FA4 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441FA8 B  REGISTER CRCIN_IDX[490] (wo): CRC Input Data Array Register
0x40441FA8 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441FAC B  REGISTER CRCIN_IDX[491] (wo): CRC Input Data Array Register
0x40441FAC C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441FB0 B  REGISTER CRCIN_IDX[492] (wo): CRC Input Data Array Register
0x40441FB0 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441FB4 B  REGISTER CRCIN_IDX[493] (wo): CRC Input Data Array Register
0x40441FB4 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441FB8 B  REGISTER CRCIN_IDX[494] (wo): CRC Input Data Array Register
0x40441FB8 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441FBC B  REGISTER CRCIN_IDX[495] (wo): CRC Input Data Array Register
0x40441FBC C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441FC0 B  REGISTER CRCIN_IDX[496] (wo): CRC Input Data Array Register
0x40441FC0 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441FC4 B  REGISTER CRCIN_IDX[497] (wo): CRC Input Data Array Register
0x40441FC4 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441FC8 B  REGISTER CRCIN_IDX[498] (wo): CRC Input Data Array Register
0x40441FC8 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441FCC B  REGISTER CRCIN_IDX[499] (wo): CRC Input Data Array Register
0x40441FCC C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441FD0 B  REGISTER CRCIN_IDX[500] (wo): CRC Input Data Array Register
0x40441FD0 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441FD4 B  REGISTER CRCIN_IDX[501] (wo): CRC Input Data Array Register
0x40441FD4 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441FD8 B  REGISTER CRCIN_IDX[502] (wo): CRC Input Data Array Register
0x40441FD8 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441FDC B  REGISTER CRCIN_IDX[503] (wo): CRC Input Data Array Register
0x40441FDC C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441FE0 B  REGISTER CRCIN_IDX[504] (wo): CRC Input Data Array Register
0x40441FE0 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441FE4 B  REGISTER CRCIN_IDX[505] (wo): CRC Input Data Array Register
0x40441FE4 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441FE8 B  REGISTER CRCIN_IDX[506] (wo): CRC Input Data Array Register
0x40441FE8 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441FEC B  REGISTER CRCIN_IDX[507] (wo): CRC Input Data Array Register
0x40441FEC C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441FF0 B  REGISTER CRCIN_IDX[508] (wo): CRC Input Data Array Register
0x40441FF0 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441FF4 B  REGISTER CRCIN_IDX[509] (wo): CRC Input Data Array Register
0x40441FF4 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441FF8 B  REGISTER CRCIN_IDX[510] (wo): CRC Input Data Array Register
0x40441FF8 C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40441FFC B  REGISTER CRCIN_IDX[511] (wo): CRC Input Data Array Register
0x40441FFC C   FIELD 00w32 CRCIN_IDX_DATA (wo): Input Data
0x40468000 A PERIPHERAL SPI0
0x40468800 B  REGISTER PWREN (rw): Power enable
0x40468800 C   FIELD 00w01 PWREN_ENABLE (rw): Enable the power
0x40468800 C   FIELD 24w08 PWREN_KEY (wo): KEY to allow Power State Change
0x40468804 B  REGISTER RSTCTL (wo): Reset Control
0x40468804 C   FIELD 00w01 RSTCTL_RESETASSERT (wo): Assert reset to the peripheral
0x40468804 C   FIELD 01w01 RSTCTL_RESETSTKYCLR (wo): Clear the RESETSTKY bit in the STAT register
0x40468804 C   FIELD 24w08 RSTCTL_KEY (wo): Unlock key
0x40468808 B  REGISTER CLKCFG (rw): Peripheral Clock Configuration Register
0x40468808 C   FIELD 08w01 CLKCFG_BLOCKASYNC (rw): Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz
0x40468808 C   FIELD 24w08 CLKCFG_KEY (wo): KEY to Allow State Change -- 0xA9
0x40468814 B  REGISTER GPRCM_STAT (ro): Status Register
0x40468814 C   FIELD 16w01 GPRCM_STAT_RESETSTKY (ro): This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register
0x40469000 B  REGISTER CLKDIV (rw): Clock Divider
0x40469000 C   FIELD 00w03 CLKDIV_RATIO: Selects divide ratio of module clock
0x40469004 B  REGISTER CLKSEL (rw): Clock Select for Ultra Low Power peripherals
0x40469004 C   FIELD 01w01 CLKSEL_LFCLK_SEL (rw): Selects LFCLK as clock source if enabled
0x40469004 C   FIELD 02w01 CLKSEL_MFCLK_SEL (rw): Selects MFCLK as clock source if enabled
0x40469004 C   FIELD 03w01 CLKSEL_SYSCLK_SEL (rw): Selects SYSCLK as clock source if enabled
0x40469018 B  REGISTER PDBGCTL (rw): Peripheral Debug Control
0x40469018 C   FIELD 00w01 PDBGCTL_FREE (rw): Free run control
0x40469018 C   FIELD 01w01 PDBGCTL_SOFT (rw): Soft halt boundary control. This function is only available, if [FREE] is set to 'STOP'
0x40469020 B  REGISTER INT_EVENT0_IIDX (ro): Interrupt Index Register
0x40469020 C   FIELD 00w08 INT_EVENT0_IIDX_STAT (ro): Interrupt index status
0x40469028 B  REGISTER INT_EVENT0_IMASK (rw): Interrupt mask
0x40469028 C   FIELD 00w01 INT_EVENT0_IMASK_RXFIFO_OVF: RXFIFO overflow event mask.
0x40469028 C   FIELD 01w01 INT_EVENT0_IMASK_PER: Parity error event mask.
0x40469028 C   FIELD 02w01 INT_EVENT0_IMASK_RTOUT: Enable SPI Receive Time-Out event mask.
0x40469028 C   FIELD 03w01 INT_EVENT0_IMASK_RX: Receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached
0x40469028 C   FIELD 04w01 INT_EVENT0_IMASK_TX: Transmit FIFO event mask.
0x40469028 C   FIELD 05w01 INT_EVENT0_IMASK_TXEMPTY: Transmit FIFO Empty event mask.
0x40469028 C   FIELD 06w01 INT_EVENT0_IMASK_IDLE: SPI Idle event mask.
0x40469028 C   FIELD 07w01 INT_EVENT0_IMASK_DMA_DONE_RX: DMA Done 1 event for RX event mask.
0x40469028 C   FIELD 08w01 INT_EVENT0_IMASK_DMA_DONE_TX: DMA Done 1 event for TX event mask.
0x40469028 C   FIELD 09w01 INT_EVENT0_IMASK_TXFIFO_UNF (rw): TX FIFO underflow interrupt mask
0x40469028 C   FIELD 10w01 INT_EVENT0_IMASK_RXFULL (rw): RX FIFO Full Interrupt Mask
0x40469030 B  REGISTER INT_EVENT0_RIS (ro): Raw interrupt status
0x40469030 C   FIELD 00w01 INT_EVENT0_RIS_RXFIFO_OVF: RXFIFO overflow event. This interrupt is set if an RX FIFO overflow has been detected.
0x40469030 C   FIELD 01w01 INT_EVENT0_RIS_PER: Parity error event: this bit is set if a Parity error has been detected
0x40469030 C   FIELD 02w01 INT_EVENT0_RIS_RTOUT: SPI Receive Time-Out event.
0x40469030 C   FIELD 03w01 INT_EVENT0_RIS_RX: Receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached
0x40469030 C   FIELD 04w01 INT_EVENT0_RIS_TX: Transmit FIFO event..This interrupt is set if the selected Transmit FIFO level has been reached.
0x40469030 C   FIELD 05w01 INT_EVENT0_RIS_TXEMPTY: Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been move to the shift register.
0x40469030 C   FIELD 06w01 INT_EVENT0_RIS_IDLE: SPI has done finished transfers and changed into IDLE mode. This bit is set when BUSY goes low.
0x40469030 C   FIELD 07w01 INT_EVENT0_RIS_DMA_DONE_RX: DMA Done 1 event for RX. This interrupt is set if the RX DMA channel sends the DONE signal. This allows the handling of the DMA event inside the mapped peripheral.
0x40469030 C   FIELD 08w01 INT_EVENT0_RIS_DMA_DONE_TX: DMA Done 1 event for TX. This interrupt is set if the TX DMA channel sends the DONE signal. This allows the handling of the DMA event inside the mapped peripheral.
0x40469030 C   FIELD 09w01 INT_EVENT0_RIS_TXFIFO_UNF: TX FIFO Underflow Interrupt
0x40469030 C   FIELD 10w01 INT_EVENT0_RIS_RXFULL: RX FIFO Full Interrupt
0x40469038 B  REGISTER INT_EVENT0_MIS (ro): Masked interrupt status
0x40469038 C   FIELD 00w01 INT_EVENT0_MIS_RXFIFO_OVF: Masked RXFIFO overflow event. This interrupt is set if an RX FIFO overflow has been detected.
0x40469038 C   FIELD 01w01 INT_EVENT0_MIS_PER: Masked Parity error event: this bit if a Parity error has been detected
0x40469038 C   FIELD 02w01 INT_EVENT0_MIS_RTOUT: Masked SPI Receive Time-Out Interrupt.
0x40469038 C   FIELD 03w01 INT_EVENT0_MIS_RX: Masked receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached
0x40469038 C   FIELD 04w01 INT_EVENT0_MIS_TX: Masked Transmit FIFO event. This interrupt is set if the selected Transmit FIFO level has been reached.
0x40469038 C   FIELD 05w01 INT_EVENT0_MIS_TXEMPTY: Masked Transmit FIFO Empty event.
0x40469038 C   FIELD 06w01 INT_EVENT0_MIS_IDLE: Masked SPI IDLE mode event.
0x40469038 C   FIELD 07w01 INT_EVENT0_MIS_DMA_DONE_RX: Masked DMA Done 1 event for RX.
0x40469038 C   FIELD 08w01 INT_EVENT0_MIS_DMA_DONE_TX: Masked DMA Done 1 event for TX.
0x40469038 C   FIELD 09w01 INT_EVENT0_MIS_TXFIFO_UNF: TX FIFO underflow interrupt
0x40469038 C   FIELD 10w01 INT_EVENT0_MIS_RXFULL: RX FIFO Full Interrupt
0x40469040 B  REGISTER INT_EVENT0_ISET (wo): Interrupt set
0x40469040 C   FIELD 00w01 INT_EVENT0_ISET_RXFIFO_OVF: Set RXFIFO overflow event.
0x40469040 C   FIELD 01w01 INT_EVENT0_ISET_PER: Set Parity error event.
0x40469040 C   FIELD 02w01 INT_EVENT0_ISET_RTOUT: Set SPI Receive Time-Out Event.
0x40469040 C   FIELD 03w01 INT_EVENT0_ISET_RX: Set Receive FIFO event.
0x40469040 C   FIELD 04w01 INT_EVENT0_ISET_TX: Set Transmit FIFO event.
0x40469040 C   FIELD 05w01 INT_EVENT0_ISET_TXEMPTY: Set Transmit FIFO Empty event.
0x40469040 C   FIELD 06w01 INT_EVENT0_ISET_IDLE: Set SPI IDLE mode event.
0x40469040 C   FIELD 07w01 INT_EVENT0_ISET_DMA_DONE_RX: Set DMA Done 1 event for RX.
0x40469040 C   FIELD 08w01 INT_EVENT0_ISET_DMA_DONE_TX: Set DMA Done 1 event for TX.
0x40469040 C   FIELD 09w01 INT_EVENT0_ISET_TXFIFO_UNF: Set TX FIFO Underflow Event
0x40469040 C   FIELD 10w01 INT_EVENT0_ISET_RXFULL: Set RX FIFO Full Event
0x40469048 B  REGISTER INT_EVENT0_ICLR (wo): Interrupt clear
0x40469048 C   FIELD 00w01 INT_EVENT0_ICLR_RXFIFO_OVF: Clear RXFIFO overflow event.
0x40469048 C   FIELD 01w01 INT_EVENT0_ICLR_PER: Clear Parity error event.
0x40469048 C   FIELD 02w01 INT_EVENT0_ICLR_RTOUT: Clear SPI Receive Time-Out Event.
0x40469048 C   FIELD 03w01 INT_EVENT0_ICLR_RX: Clear Receive FIFO event.
0x40469048 C   FIELD 04w01 INT_EVENT0_ICLR_TX: Clear Transmit FIFO event.
0x40469048 C   FIELD 05w01 INT_EVENT0_ICLR_TXEMPTY: Clear Transmit FIFO Empty event.
0x40469048 C   FIELD 06w01 INT_EVENT0_ICLR_IDLE: Clear SPI IDLE mode event.
0x40469048 C   FIELD 07w01 INT_EVENT0_ICLR_DMA_DONE_RX: Clear DMA Done 1 event for RX.
0x40469048 C   FIELD 08w01 INT_EVENT0_ICLR_DMA_DONE_TX: Clear DMA Done 1 event for TX.
0x40469048 C   FIELD 09w01 INT_EVENT0_ICLR_TXFIFO_UNF: Clear TXFIFO underflow event
0x40469048 C   FIELD 10w01 INT_EVENT0_ICLR_RXFULL: Clear RX FIFO underflow event
0x40469050 B  REGISTER INT_EVENT1_IIDX (ro): Interrupt Index Register
0x40469050 C   FIELD 00w08 INT_EVENT1_IIDX_STAT (ro): Interrupt index status
0x40469058 B  REGISTER INT_EVENT1_IMASK (rw): Interrupt mask
0x40469058 C   FIELD 02w01 INT_EVENT1_IMASK_RTOUT: SPI Receive Time-Out event mask.
0x40469058 C   FIELD 03w01 INT_EVENT1_IMASK_RX: Receive FIFO event mask.
0x40469060 B  REGISTER INT_EVENT1_RIS (ro): Raw interrupt status
0x40469060 C   FIELD 02w01 INT_EVENT1_RIS_RTOUT: SPI Receive Time-Out Event.
0x40469060 C   FIELD 03w01 INT_EVENT1_RIS_RX: Receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached
0x40469068 B  REGISTER INT_EVENT1_MIS (ro): Masked interrupt status
0x40469068 C   FIELD 02w01 INT_EVENT1_MIS_RTOUT: SPI Receive Time-Out event mask.
0x40469068 C   FIELD 03w01 INT_EVENT1_MIS_RX: Receive FIFO event mask.
0x40469070 B  REGISTER INT_EVENT1_ISET (wo): Interrupt set
0x40469070 C   FIELD 02w01 INT_EVENT1_ISET_RTOUT: Set SPI Receive Time-Out event.
0x40469070 C   FIELD 03w01 INT_EVENT1_ISET_RX: Set Receive FIFO event.
0x40469078 B  REGISTER INT_EVENT1_ICLR (wo): Interrupt clear
0x40469078 C   FIELD 02w01 INT_EVENT1_ICLR_RTOUT: Clear SPI Receive Time-Out event.
0x40469078 C   FIELD 03w01 INT_EVENT1_ICLR_RX: Clear Receive FIFO event.
0x40469080 B  REGISTER INT_EVENT2_IIDX (ro): Interrupt Index Register
0x40469080 C   FIELD 00w08 INT_EVENT2_IIDX_STAT (ro): Interrupt index status
0x40469088 B  REGISTER INT_EVENT2_IMASK (rw): Interrupt mask
0x40469088 C   FIELD 04w01 INT_EVENT2_IMASK_TX: Transmit FIFO event mask.
0x40469090 B  REGISTER INT_EVENT2_RIS (ro): Raw interrupt status
0x40469090 C   FIELD 04w01 INT_EVENT2_RIS_TX: Transmit FIFO event: A read returns the current mask for transmit FIFO interrupt. On a write of 1, the mask for transmit FIFO interrupt is set which means the interrupt state will be reflected in MIS.TXMIS. A write of 0 clears the mask which means MIS.TXMIS will not reflect the interrupt.
0x40469098 B  REGISTER INT_EVENT2_MIS (ro): Masked interrupt status
0x40469098 C   FIELD 04w01 INT_EVENT2_MIS_TX: Masked Transmit FIFO event
0x404690A0 B  REGISTER INT_EVENT2_ISET (wo): Interrupt set
0x404690A0 C   FIELD 04w01 INT_EVENT2_ISET_TX: Set Transmit FIFO event.
0x404690A8 B  REGISTER INT_EVENT2_ICLR (wo): Interrupt clear
0x404690A8 C   FIELD 04w01 INT_EVENT2_ICLR_TX: Clear Transmit FIFO event.
0x404690E0 B  REGISTER EVT_MODE (rw): Event Mode
0x404690E0 C   FIELD 00w02 EVT_MODE_INT0_CFG (ro): Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT0]
0x404690E0 C   FIELD 02w02 EVT_MODE_INT1_CFG (ro): Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT1]
0x404690E0 C   FIELD 04w02 EVT_MODE_INT2_CFG (ro): Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT2]
0x40469100 B  REGISTER CTL0 (rw): SPI control register 0
0x40469100 C   FIELD 00w05 CTL0_DSS (rw): Data Size Select. Values 0 - 2 are reserved and shall not be used. 3h = 4_BIT : 4-bit data SPI allows only values up to 16 Bit
0x40469100 C   FIELD 05w02 CTL0_FRF (rw): Frame format Select
0x40469100 C   FIELD 07w01 CTL0_PACKEN (rw): Packing Enable. When 1, packing feature is enabled inside the IP When 0, packing feature is disabled inside the IP
0x40469100 C   FIELD 08w01 CTL0_SPO (rw): CLKOUT polarity (Motorola SPI frame format only)
0x40469100 C   FIELD 09w01 CTL0_SPH (rw): CLKOUT phase (Motorola SPI frame format only) This bit selects the clock edge that captures data and enables it to change state. It has the most impact on the first bit transmitted by either permitting or not permitting a clock transition before the first data capture edge.
0x40469100 C   FIELD 12w02 CTL0_CSSEL (rw): Select the CS line to control on data transfer This bit is for controller mode only.
0x40469100 C   FIELD 14w01 CTL0_CSCLR (rw): Clear shift register counter on CS inactive This bit is relevant only in the peripheral, CTL1.MS=0.
0x40469104 B  REGISTER CTL1 (rw): SPI control register 1
0x40469104 C   FIELD 00w01 CTL1_ENABLE (rw): SPI enable
0x40469104 C   FIELD 01w01 CTL1_LBM (rw): Loop back mode
0x40469104 C   FIELD 02w01 CTL1_MS (rw): Controller or peripheral mode select. This bit can be modified only when SPI is disabled, CTL1.ENABLE=0.
0x40469104 C   FIELD 03w01 CTL1_SOD (rw): Peripheral-mode: Data output disabled This bit is relevant only in the peripheral mode, CTL1.MS=1. In multiple-peripheral systems, it is possible for an SPI controller to broadcast a message to all peripherals in the system while ensuring that only one peripheral drives data onto its serial output line. In such systems the MISO lines from multiple peripherals could be tied together. To operate in such systems, this bitfield can be set if the SPI peripheral is not supposed to drive the MISO line:
0x40469104 C   FIELD 04w01 CTL1_MSB (rw): MSB first select. Controls the direction of the receive and transmit shift register.
0x40469104 C   FIELD 05w01 CTL1_PREN (rw): Parity receive enable If enabled, parity reception check will be done for both controller and peripheral modes In case of a parity miss-match the parity error flag RIS.PER will be set.
0x40469104 C   FIELD 06w01 CTL1_PES (rw): Even Parity Select
0x40469104 C   FIELD 07w01 CTL1_PBS (rw): Parity Bit Select
0x40469104 C   FIELD 08w01 CTL1_PTEN (rw): Parity transmit enable If enabled, parity transmission will be done for both controller and peripheral modes.
0x40469104 C   FIELD 11w01 CTL1_CDENABLE (rw): Command/Data Mode enable
0x40469104 C   FIELD 12w04 CTL1_CDMODE (rw): Command/Data Mode Value When CTL1.CDENABLE is 1, CS3 line is used as C/D signal to distinguish between Command (C/D low) and Data (C/D high) information. When a value is written into the CTL1.CDMODE bits, the C/D (CS3) line will go low for the given numbers of byte which are sent by the SPI, starting with the next value to be transmitted after which, C/D line will go high automatically 0: Manual mode with C/D signal as High 1-14: C/D is low while this number of bytes are being sent after which, this field sets to 0 and C/D goes high. Reading this field at any time returns the remaining number of command bytes. 15: Manual mode with C/D signal as Low.
0x40469104 C   FIELD 16w08 CTL1_REPEATTX (rw): Counter to repeat last transfer 0: repeat last transfer is disabled. x: repeat the last transfer with the given number. The transfer will be started with writing a data into the TX Buffer. Sending the data will be repeated with the given value, so the data will be transferred X+1 times in total. The behavior is identical as if the data would be written into the TX Buffer that many times as defined by the value here. It can be used to clean a transfer or to pull a certain amount of data by a peripheral.
0x40469104 C   FIELD 24w06 CTL1_RXTIMEOUT (rw): Receive Timeout (only for Peripheral mode) Defines the number of Clock Cycles before after which the Receive Timeout flag RTOUT is set. The time is calculated using the control register for the clock selection and divider in the Controller mode configuration. A value of 0 disables this function.
0x40469108 B  REGISTER CLKCTL (rw): Clock prescaler and divider register.
0x40469108 C   FIELD 00w10 CLKCTL_SCR (rw): Serial clock divider: This is used to generate the transmit and receive bit rate of the SPI. The SPI bit rate is (SPI's functional clock frequency)/((SCR+1)*2). SCR is a value from 0-1023.
0x40469108 C   FIELD 28w04 CLKCTL_DSAMPLE (rw): Delayed sampling value. In controller mode the data on the input pin will be delayed sampled by the defined clock cycles of internal functional clock hence relaxing the setup time of input data. This setting is useful in systems where the board delays and external peripheral delays are more than the input setup time of the controller. Please refer to the datasheet for values of controller input setup time and assess what DSAMPLE value meets the requirement of the system. Note: High values of DSAMPLE can cause HOLD time violations and must be factored in the calculations.
0x4046910C B  REGISTER IFLS (rw): UART Interrupt FIFO Level Select Register
0x4046910C C   FIELD 00w03 IFLS_TXIFLSEL (rw): SPI Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows:
0x4046910C C   FIELD 03w03 IFLS_RXIFLSEL (rw): SPI Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows:
0x40469110 B  REGISTER STAT (ro): Status Register
0x40469110 C   FIELD 00w01 STAT_TFE: Transmit FIFO empty.
0x40469110 C   FIELD 01w01 STAT_TNF: Transmit FIFO not full
0x40469110 C   FIELD 02w01 STAT_RFE: Receive FIFO empty.
0x40469110 C   FIELD 03w01 STAT_RNF: Receive FIFO not full
0x40469110 C   FIELD 04w01 STAT_BUSY: Busy
0x40469130 B  REGISTER RXDATA (ro): RXDATA Register
0x40469130 C   FIELD 00w16 RXDATA_DATA (ro): Received Data When PACKEN=1,two entries of the FIFO are returned as a 32-bit value. When PACKEN=0, 1 entry of FIFO is returned as 16-bit value. As data values are removed by the receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. Received data less than 16 bits is automatically right justified in the receive buffer.
0x40469140 B  REGISTER TXDATA (rw): TXDATA Register
0x40469140 C   FIELD 00w16 TXDATA_DATA (rw): Transmit Data WWhen read, last written value will be returned. If the last write to this field was a 32-bit write (with PACKEN=1), 32-bits will be returned and if the last write was a 16-bit write (PACKEN=0), those 16-bits will be returned. When written, one or two FIFO entries will be written depending on PACKEN value. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the TXD output pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits.
0x4055A000 A PERIPHERAL ADC0_SVT
0x4055A160 B  REGISTER FIFODATA (ro): FIFO Data Register
0x4055A160 C   FIELD 00w32 FIFODATA_DATA: Read from this data field returns the ADC sample from FIFO.
0x4055A280 B  REGISTER MEMRES[0] (ro): Memory Result Register
0x4055A280 C   FIELD 00w16 MEMRES_DATA: MEMRES result register. If DF = 0, unsigned binary: The conversion results are right aligned. In 10 and 8 bit modes, the unused MSB bits are forced to 0. If DF = 1, 2s-complement format: The conversion results are left aligned. In 10 and 8 bit modes, the unused LSB bits are forced to 0. The data is stored in the right-justified format and is converted to the left-justified 2s-complement format during read back.
0x4055A284 B  REGISTER MEMRES[1] (ro): Memory Result Register
0x4055A284 C   FIELD 00w16 MEMRES_DATA: MEMRES result register. If DF = 0, unsigned binary: The conversion results are right aligned. In 10 and 8 bit modes, the unused MSB bits are forced to 0. If DF = 1, 2s-complement format: The conversion results are left aligned. In 10 and 8 bit modes, the unused LSB bits are forced to 0. The data is stored in the right-justified format and is converted to the left-justified 2s-complement format during read back.
0x4055A288 B  REGISTER MEMRES[2] (ro): Memory Result Register
0x4055A288 C   FIELD 00w16 MEMRES_DATA: MEMRES result register. If DF = 0, unsigned binary: The conversion results are right aligned. In 10 and 8 bit modes, the unused MSB bits are forced to 0. If DF = 1, 2s-complement format: The conversion results are left aligned. In 10 and 8 bit modes, the unused LSB bits are forced to 0. The data is stored in the right-justified format and is converted to the left-justified 2s-complement format during read back.
0x4055A28C B  REGISTER MEMRES[3] (ro): Memory Result Register
0x4055A28C C   FIELD 00w16 MEMRES_DATA: MEMRES result register. If DF = 0, unsigned binary: The conversion results are right aligned. In 10 and 8 bit modes, the unused MSB bits are forced to 0. If DF = 1, 2s-complement format: The conversion results are left aligned. In 10 and 8 bit modes, the unused LSB bits are forced to 0. The data is stored in the right-justified format and is converted to the left-justified 2s-complement format during read back.