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STM32F410.svd
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STM32F410.svd
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<?xml version="1.0" encoding="utf-8" standalone="no"?>
<!--
Copyright (c) 2021 STMicroelectronics.
SPDX-License-Identifier: Apache-2.0
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
-->
<device schemaVersion="1.1"
xmlns:xs="http://www.w3.org/2001/XMLSchema-instance"
xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
<name>STM32F410</name>
<version>1.4</version>
<description>STM32F410</description>
<cpu>
<name>CM4</name>
<revision>r0p1</revision>
<endian>little</endian>
<mpuPresent>true</mpuPresent>
<fpuPresent>true</fpuPresent>
<nvicPrioBits>4</nvicPrioBits>
<vendorSystickConfig>false</vendorSystickConfig>
</cpu>
<addressUnitBits>8</addressUnitBits>
<width>32</width>
<size>0x20</size>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<peripherals>
<peripheral>
<name>ADC_Common</name>
<description>ADC common registers</description>
<groupName>ADC</groupName>
<baseAddress>0x40012300</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x9</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>CSR</name>
<displayName>CSR</displayName>
<description>ADC Common status register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OVR3</name>
<description>Overrun flag of ADC3</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STRT3</name>
<description>Regular channel Start flag of ADC
3</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>JSTRT3</name>
<description>Injected channel Start flag of ADC
3</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>JEOC3</name>
<description>Injected channel end of conversion of
ADC 3</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOC3</name>
<description>End of conversion of ADC 3</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AWD3</name>
<description>Analog watchdog flag of ADC
3</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVR2</name>
<description>Overrun flag of ADC 2</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STRT2</name>
<description>Regular channel Start flag of ADC
2</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>JSTRT2</name>
<description>Injected channel Start flag of ADC
2</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>JEOC2</name>
<description>Injected channel end of conversion of
ADC 2</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOC2</name>
<description>End of conversion of ADC 2</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AWD2</name>
<description>Analog watchdog flag of ADC
2</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVR1</name>
<description>Overrun flag of ADC 1</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STRT1</name>
<description>Regular channel Start flag of ADC
1</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>JSTRT1</name>
<description>Injected channel Start flag of ADC
1</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>JEOC1</name>
<description>Injected channel end of conversion of
ADC 1</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOC1</name>
<description>End of conversion of ADC 1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AWD1</name>
<description>Analog watchdog flag of ADC
1</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCR</name>
<displayName>CCR</displayName>
<description>ADC common control register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TSVREFE</name>
<description>Temperature sensor and VREFINT
enable</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>VBATE</name>
<description>VBAT enable</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADCPRE</name>
<description>ADC prescaler</description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DMA</name>
<description>Direct memory access mode for multi ADC
mode</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DDS</name>
<description>DMA disable selection for multi-ADC
mode</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DELAY</name>
<description>Delay between 2 sampling
phases</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>ADC1</name>
<description>Analog-to-digital converter</description>
<groupName>ADC</groupName>
<baseAddress>0x40012000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x51</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>ADC</name>
<description>ADC1 global interrupt</description>
<value>18</value>
</interrupt>
<registers>
<register>
<name>SR</name>
<displayName>SR</displayName>
<description>status register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OVR</name>
<description>Overrun</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STRT</name>
<description>Regular channel start flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>JSTRT</name>
<description>Injected channel start
flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>JEOC</name>
<description>Injected channel end of
conversion</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOC</name>
<description>Regular channel end of
conversion</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AWD</name>
<description>Analog watchdog flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CR1</name>
<displayName>CR1</displayName>
<description>control register 1</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OVRIE</name>
<description>Overrun interrupt enable</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RES</name>
<description>Resolution</description>
<bitOffset>24</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>AWDEN</name>
<description>Analog watchdog enable on regular
channels</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>JAWDEN</name>
<description>Analog watchdog enable on injected
channels</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DISCNUM</name>
<description>Discontinuous mode channel
count</description>
<bitOffset>13</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>JDISCEN</name>
<description>Discontinuous mode on injected
channels</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DISCEN</name>
<description>Discontinuous mode on regular
channels</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>JAUTO</name>
<description>Automatic injected group
conversion</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AWDSGL</name>
<description>Enable the watchdog on a single channel
in scan mode</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SCAN</name>
<description>Scan mode</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>JEOCIE</name>
<description>Interrupt enable for injected
channels</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AWDIE</name>
<description>Analog watchdog interrupt
enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOCIE</name>
<description>Interrupt enable for EOC</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AWDCH</name>
<description>Analog watchdog channel select
bits</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>CR2</name>
<displayName>CR2</displayName>
<description>control register 2</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SWSTART</name>
<description>Start conversion of regular
channels</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTEN</name>
<description>External trigger enable for regular
channels</description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>EXTSEL</name>
<description>External event select for regular
group</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>JSWSTART</name>
<description>Start conversion of injected
channels</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>JEXTEN</name>
<description>External trigger enable for injected
channels</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>JEXTSEL</name>
<description>External event select for injected
group</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>ALIGN</name>
<description>Data alignment</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EOCS</name>
<description>End of conversion
selection</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DDS</name>
<description>DMA disable selection (for single ADC
mode)</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMA</name>
<description>Direct memory access mode (for single
ADC mode)</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CONT</name>
<description>Continuous conversion</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADON</name>
<description>A/D Converter ON / OFF</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SMPR1</name>
<displayName>SMPR1</displayName>
<description>sample time register 1</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SMPx_x</name>
<description>Sample time bits</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>SMPR2</name>
<displayName>SMPR2</displayName>
<description>sample time register 2</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SMPx_x</name>
<description>Sample time bits</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>JOFR1</name>
<displayName>JOFR1</displayName>
<description>injected channel data offset register
x</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>JOFFSET1</name>
<description>Data offset for injected channel
x</description>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>JOFR2</name>
<displayName>JOFR2</displayName>
<description>injected channel data offset register
x</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>JOFFSET2</name>
<description>Data offset for injected channel
x</description>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>JOFR3</name>
<displayName>JOFR3</displayName>
<description>injected channel data offset register
x</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>JOFFSET3</name>
<description>Data offset for injected channel
x</description>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>JOFR4</name>
<displayName>JOFR4</displayName>
<description>injected channel data offset register
x</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>JOFFSET4</name>
<description>Data offset for injected channel
x</description>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>HTR</name>
<displayName>HTR</displayName>
<description>watchdog higher threshold
register</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000FFF</resetValue>
<fields>
<field>
<name>HT</name>
<description>Analog watchdog higher
threshold</description>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>LTR</name>
<displayName>LTR</displayName>
<description>watchdog lower threshold
register</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LT</name>
<description>Analog watchdog lower
threshold</description>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>SQR1</name>
<displayName>SQR1</displayName>
<description>regular sequence register 1</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>L</name>
<description>Regular channel sequence
length</description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>SQ16</name>
<description>16th conversion in regular
sequence</description>
<bitOffset>15</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SQ15</name>
<description>15th conversion in regular
sequence</description>
<bitOffset>10</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SQ14</name>
<description>14th conversion in regular
sequence</description>
<bitOffset>5</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SQ13</name>
<description>13th conversion in regular
sequence</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>SQR2</name>
<displayName>SQR2</displayName>
<description>regular sequence register 2</description>
<addressOffset>0x30</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SQ12</name>
<description>12th conversion in regular
sequence</description>
<bitOffset>25</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SQ11</name>
<description>11th conversion in regular
sequence</description>
<bitOffset>20</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SQ10</name>
<description>10th conversion in regular
sequence</description>
<bitOffset>15</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SQ9</name>
<description>9th conversion in regular
sequence</description>
<bitOffset>10</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SQ8</name>
<description>8th conversion in regular
sequence</description>
<bitOffset>5</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SQ7</name>
<description>7th conversion in regular
sequence</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>SQR3</name>
<displayName>SQR3</displayName>
<description>regular sequence register 3</description>
<addressOffset>0x34</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SQ6</name>
<description>6th conversion in regular
sequence</description>
<bitOffset>25</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SQ5</name>
<description>5th conversion in regular
sequence</description>
<bitOffset>20</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SQ4</name>
<description>4th conversion in regular
sequence</description>
<bitOffset>15</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SQ3</name>
<description>3rd conversion in regular
sequence</description>
<bitOffset>10</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SQ2</name>
<description>2nd conversion in regular
sequence</description>
<bitOffset>5</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SQ1</name>
<description>1st conversion in regular
sequence</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>JSQR</name>
<displayName>JSQR</displayName>
<description>injected sequence register</description>
<addressOffset>0x38</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>JL</name>
<description>Injected sequence length</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>JSQ4</name>
<description>4th conversion in injected
sequence</description>
<bitOffset>15</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>JSQ3</name>
<description>3rd conversion in injected
sequence</description>
<bitOffset>10</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>JSQ2</name>
<description>2nd conversion in injected
sequence</description>
<bitOffset>5</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>JSQ1</name>
<description>1st conversion in injected
sequence</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>JDR1</name>
<displayName>JDR1</displayName>
<description>injected data register x</description>
<addressOffset>0x3C</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>JDATA</name>
<description>Injected data</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>JDR2</name>
<displayName>JDR2</displayName>
<description>injected data register x</description>
<addressOffset>0x40</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>JDATA</name>
<description>Injected data</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>JDR3</name>
<displayName>JDR3</displayName>
<description>injected data register x</description>
<addressOffset>0x44</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>JDATA</name>
<description>Injected data</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>JDR4</name>
<displayName>JDR4</displayName>
<description>injected data register x</description>
<addressOffset>0x48</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>JDATA</name>
<description>Injected data</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>DR</name>
<displayName>DR</displayName>
<description>regular data register</description>
<addressOffset>0x4C</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DATA</name>
<description>Regular data</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>CRC</name>
<description>Cryptographic processor</description>
<groupName>CRC</groupName>
<baseAddress>0x40023000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>DR</name>
<displayName>DR</displayName>
<description>Data register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0xFFFFFFFF</resetValue>
<fields>
<field>
<name>DR</name>
<description>Data Register</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>IDR</name>
<displayName>IDR</displayName>
<description>Independent Data register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IDR</name>
<description>Independent Data register</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>CR</name>
<displayName>CR</displayName>
<description>Control register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CR</name>
<description>Control regidter</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>DBG</name>
<description>Debug support</description>
<groupName>DBG</groupName>
<baseAddress>0xE0042000</baseAddress>
<addressBlock>
<offset>0x0</offset>