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STM32G0B0.svd
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STM32G0B0.svd
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<?xml version="1.0" encoding="utf-8" standalone="no"?>
<!--
Copyright (c) 2020 STMicroelectronics.
SPDX-License-Identifier: Apache-2.0
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
-->
<device schemaVersion="1.1"
xmlns:xs="http://www.w3.org/2001/XMLSchema-instance"
xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
<name>STM32G0B0</name>
<version>1.1</version>
<description>STM32G0B0</description>
<cpu>
<name>CM0</name>
<revision>r0p1</revision>
<endian>little</endian>
<mpuPresent>true</mpuPresent>
<fpuPresent>false</fpuPresent>
<nvicPrioBits>4</nvicPrioBits>
<vendorSystickConfig>false</vendorSystickConfig>
</cpu>
<addressUnitBits>8</addressUnitBits>
<width>32</width>
<size>0x20</size>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<peripherals>
<peripheral>
<name>CRC</name>
<description>Cyclic redundancy check calculation
unit</description>
<groupName>CRC</groupName>
<baseAddress>0x40023000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>CRC_DR</name>
<displayName>CRC_DR</displayName>
<description>Data register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0xFFFFFFFF</resetValue>
<fields>
<field>
<name>DR</name>
<description>Data register bits</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CRC_IDR</name>
<displayName>CRC_IDR</displayName>
<description>Independent data register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IDR</name>
<description>General-purpose 32-bit data register
bits</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CRC_CR</name>
<displayName>CRC_CR</displayName>
<description>Control register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>REV_OUT</name>
<description>Reverse output data
This bit controls the reversal of the bit order of the output data.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Bit order not affected</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Bit-reversed output format</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>REV_IN</name>
<description>Reverse input data
These bits control the reversal of the bit order of the input data</description>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Bit order not affected</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Bit reversal done by byte</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>Bit reversal done by half-word</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>Bit reversal done by word</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>POLYSIZE</name>
<description>Polynomial size
These bits control the size of the polynomial.</description>
<bitOffset>3</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>32 bit polynomial</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>16 bit polynomial</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>8 bit polynomial</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>7 bit polynomial</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESET</name>
<description>RESET bit</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
</fields>
</register>
<register>
<name>CRC_INIT</name>
<displayName>CRC_INIT</displayName>
<description>Initial CRC value</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0xFFFFFFFF</resetValue>
<fields>
<field>
<name>CRC_INIT</name>
<description>Programmable initial CRC
value</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CRC_POL</name>
<displayName>CRC_POL</displayName>
<description>polynomial</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x04C11DB7</resetValue>
<fields>
<field>
<name>POL</name>
<description>Programmable polynomial</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>DBG</name>
<description>Debug support</description>
<groupName>DBG</groupName>
<baseAddress>0x40015800</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>IDCODE</name>
<displayName>IDCODE</displayName>
<description>MCU Device ID Code Register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>DEV_ID</name>
<description>Device Identifier</description>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
</field>
<field>
<name>REV_ID</name>
<description>Revision Identifier</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>DBG_CR</name>
<displayName>DBG_CR</displayName>
<description>DBG configuration register </description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DBG_STOP</name>
<description>Debug Stop mode
Debug options in Stop mode.
Upon Stop mode exit, the software must re-establish the desired clock configuration.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>All clocks disabled, including FCLK and HCLK. Upon Stop mode exit, the CPU is clocked by the HSI internal RC oscillator. </description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>FCLK and HCLK running, derived from the internal RC oscillator remaining active. If Systick is enabled, it may generate periodic interrupt and wake up events.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DBG_STANDBY</name>
<description>Debug Standby and Shutdown modes
Debug options in Standby or Shutdown mode.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Digital part powered. From software point of view, exiting Standby and Shutdown modes is identical as fetching reset vector (except for status bits indicating that the MCU exits Standby)</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Digital part powered and FCLK and HCLK running, derived from the internal RC oscillator remaining active. The MCU generates a system reset so that exiting Standby and Shutdown has the same effect as starting from reset.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>DBG_APB_FZ1</name>
<displayName>DBG_APB_FZ1</displayName>
<description>DBG APB freeze register 1 </description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DBG_TIM2_STOP</name>
<description>Clocking of TIM2 counter when the core is halted
This bit enables/disables the clock to the counter of TIM2 when the core is halted:</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Enable</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Disable</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DBG_TIM3_STOP</name>
<description>Clocking of TIM3 counter when the core is halted
This bit enables/disables the clock to the counter of TIM3 when the core is halted:</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Enable</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Disable</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DBG_TIM6_STOP</name>
<description>Clocking of TIM6 counter when the core is halted
This bit enables/disables the clock to the counter of TIM6 when the core is halted:</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Enable</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Disable</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DBG_TIM7_STOP</name>
<description>Clocking of TIM7 counter when the core is halted.
This bit enables/disables the clock to the counter of ITIM7 when the core is halted:</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Enable</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Disable</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DBG_RTC_STOP</name>
<description>Clocking of RTC counter when the core is halted
This bit enables/disables the clock to the counter of RTC when the core is halted:</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Enable</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Disable</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DBG_WWDG_STOP</name>
<description>Clocking of WWDG counter when the core is halted
This bit enables/disables the clock to the counter of WWDG when the core is halted:</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Enable</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Disable</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DBG_IWDG_STOP</name>
<description>Clocking of IWDG counter when the core is halted
This bit enables/disables the clock to the counter of IWDG when the core is halted:</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Enable</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Disable</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DBG_I2C1_SMBUS_TIMEOUT</name>
<description>SMBUS timeout when core is halted</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Same behavior as in normal mode</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>The SMBUS timeout is frozen</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DBG_LPTIM2_STOP</name>
<description>Clocking of LPTIMER2 counter when the core is halted
This bit enables/disables the clock to the counter of LPTIMER2 when the core is halted:</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Enable</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Disable</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DBG_LPTIM1_STOP</name>
<description>Clocking of LPTIMER1 counter when the core is halted
This bit enables/disables the clock to the counter of LPTIMER1 when the core is halted:</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Enable</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Disable</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>DBG_APB_FZ2</name>
<displayName>DBG_APB_FZ2</displayName>
<description>DBG APB freeze register 2 </description>
<addressOffset>0xc</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DBG_TIM1_STOP</name>
<description>Clocking of TIM1 counter when the core is halted
This bit enables/disables the clock to the counter of TIM1 when the core is halted:</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Enable</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Disable</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DBG_TIM14_STOP</name>
<description>Clocking of TIM14 counter when the core is halted
This bit enables/disables the clock to the counter of TIM14 when the core is halted:</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Enable</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Disable</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DBG_TIM15_STOP</name>
<description>Clocking of TIM15 counter when the core is halted
This bit enables/disables the clock to the counter of TIM15 when the core is halted:
Only available on STM32G071xx and STM32G081xx, reserved on STM32G031xx and STM32G041xx.</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Enable</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Disable</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DBG_TIM16_STOP</name>
<description>Clocking of TIM16 counter when the core is halted
This bit enables/disables the clock to the counter of TIM16 when the core is halted:</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Enable</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Disable</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DBG_TIM17_STOP</name>
<description>Clocking of TIM17 counter when the core is halted
This bit enables/disables the clock to the counter of TIM17 when the core is halted:</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>Enable</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>Disable</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>DMAMUX</name>
<description>DMAMUX</description>
<groupName>DMAMUX</groupName>
<baseAddress>0x40020800</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x800</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>DMA_Channel4_5_6_7</name>
<description>DMA channel 4, 5, 6 & 7 and
DMAMUX</description>
<value>11</value>
</interrupt>
<registers>
<register>
<name>DMAMUX_C0CR</name>
<displayName>DMAMUX_C0CR</displayName>
<description>DMAMUX request line multiplexer channel x configuration register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DMAREQ_ID</name>
<description>DMA request identification
Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources.</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SOIE</name>
<description>Synchronization overrun interrupt enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>interrupt disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>interrupt enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EGE</name>
<description>Event generation enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>event generation disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>event generation enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SE</name>
<description>Synchronization enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>synchronization disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>synchronization enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPOL</name>
<description>Synchronization polarity
Defines the edge polarity of the selected synchronization input:</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>no event, i.e. no synchronization nor detection.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>rising edge</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>falling edge</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>rising and falling edge</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>NBREQ</name>
<description>Number of DMA requests minus 1 to forward
Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated.
This field shall only be written when both SE and EGE bits are low.</description>
<bitOffset>19</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SYNC_ID</name>
<description>Synchronization identification
Selects the synchronization input (see inputs to resources STM32G0).</description>
<bitOffset>24</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DMAMUX_C1CR</name>
<displayName>DMAMUX_C1CR</displayName>
<description>DMAMUX request line multiplexer channel x configuration register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DMAREQ_ID</name>
<description>DMA request identification
Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources.</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SOIE</name>
<description>Synchronization overrun interrupt enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>interrupt disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>interrupt enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EGE</name>
<description>Event generation enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>event generation disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>event generation enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SE</name>
<description>Synchronization enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>synchronization disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>synchronization enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPOL</name>
<description>Synchronization polarity
Defines the edge polarity of the selected synchronization input:</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>no event, i.e. no synchronization nor detection.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>rising edge</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>falling edge</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>rising and falling edge</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>NBREQ</name>
<description>Number of DMA requests minus 1 to forward
Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated.
This field shall only be written when both SE and EGE bits are low.</description>
<bitOffset>19</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SYNC_ID</name>
<description>Synchronization identification
Selects the synchronization input (see inputs to resources STM32G0).</description>
<bitOffset>24</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DMAMUX_C2CR</name>
<displayName>DMAMUX_C2CR</displayName>
<description>DMAMUX request line multiplexer channel x configuration register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DMAREQ_ID</name>
<description>DMA request identification
Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources.</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SOIE</name>
<description>Synchronization overrun interrupt enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>interrupt disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>interrupt enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>EGE</name>
<description>Event generation enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>event generation disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>event generation enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SE</name>
<description>Synchronization enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>synchronization disabled</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>synchronization enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SPOL</name>
<description>Synchronization polarity
Defines the edge polarity of the selected synchronization input:</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>B_0x0</name>
<description>no event, i.e. no synchronization nor detection.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x1</name>
<description>rising edge</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x2</name>
<description>falling edge</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>B_0x3</name>
<description>rising and falling edge</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>NBREQ</name>
<description>Number of DMA requests minus 1 to forward