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dottorilog.qsf
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dottorilog.qsf
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2012 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 32-bit
# Version 12.0 Build 178 05/31/2012 SJ Web Edition
# Date created = 13:44:34 August 14, 2017
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# dottorilog_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone II"
set_global_assignment -name DEVICE EP2C20F484C7
set_global_assignment -name TOP_LEVEL_ENTITY top
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 12.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:44:34 AUGUST 14, 2017"
set_global_assignment -name LAST_QUARTUS_VERSION 12.0
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name USE_CONFIGURATION_DEVICE ON
set_global_assignment -name STRATIX_CONFIGURATION_DEVICE EPCS4
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_location_assignment PIN_L22 -to SW[0]
set_location_assignment PIN_L21 -to SW[1]
set_location_assignment PIN_M22 -to SW[2]
set_location_assignment PIN_V12 -to SW[3]
set_location_assignment PIN_W12 -to SW[4]
set_location_assignment PIN_R22 -to KEY[0]
set_location_assignment PIN_R21 -to KEY[1]
set_location_assignment PIN_T22 -to KEY[2]
set_location_assignment PIN_T21 -to KEY[3]
set_location_assignment PIN_B12 -to CLOCK_24[0]
set_location_assignment PIN_A12 -to CLOCK_24[1]
set_location_assignment PIN_D9 -to VGA_R[0]
set_location_assignment PIN_C9 -to VGA_R[1]
set_location_assignment PIN_A7 -to VGA_R[2]
set_location_assignment PIN_B7 -to VGA_R[3]
set_location_assignment PIN_B8 -to VGA_G[0]
set_location_assignment PIN_C10 -to VGA_G[1]
set_location_assignment PIN_B9 -to VGA_G[2]
set_location_assignment PIN_A8 -to VGA_G[3]
set_location_assignment PIN_A9 -to VGA_B[0]
set_location_assignment PIN_D11 -to VGA_B[1]
set_location_assignment PIN_A10 -to VGA_B[2]
set_location_assignment PIN_B10 -to VGA_B[3]
set_location_assignment PIN_A11 -to VGA_HS
set_location_assignment PIN_B11 -to VGA_VS
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity DE1_Default -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity DE1_Default -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -entity DE1_Default -section_id Top
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity DE1_Default -section_id Top
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
set_global_assignment -name VERILOG_FILE verilog/tv80_reg.v
set_global_assignment -name VERILOG_FILE verilog/tv80_mcode.v
set_global_assignment -name VERILOG_FILE verilog/tv80_core.v
set_global_assignment -name VERILOG_FILE verilog/tv80_alu.v
set_global_assignment -name VERILOG_FILE verilog/top.v
set_global_assignment -name VERILOG_FILE verilog/ROM.v
set_global_assignment -name VERILOG_FILE verilog/RAM.v
set_global_assignment -name VERILOG_FILE verilog/dottori.v
set_global_assignment -name VERILOG_FILE verilog/cpu_z80.v
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top