add10y.aag

aag 161 30 2 1 129
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i0 controllable_c<0>
i1 controllable_c<1>
i2 controllable_c<2>
i3 controllable_c<3>
i4 controllable_c<4>
i5 controllable_c<5>
i6 controllable_c<6>
i7 controllable_c<7>
i8 controllable_c<8>
i9 controllable_c<9>
i10 a<0>
i11 a<1>
i12 a<2>
i13 a<3>
i14 a<4>
i15 a<5>
i16 a<6>
i17 a<7>
i18 a<8>
i19 a<9>
i20 b<0>
i21 b<1>
i22 b<2>
i23 b<3>
i24 b<4>
i25 b<5>
i26 b<6>
i27 b<7>
i28 b<8>
i29 b<9>
l0 n63
l1 err_out
o0 err
c
bench
This file was written by ABC on Sat Aug 31 20:25:02 2013
For information about AIGER format, refer to http://fmv.jku.at/aiger
-------------------------------
This AIGER file has been created by the following sequence of commands:
> vl2mv add10.v   ---gives--> add10.mv
> abc -c "read_blif_mv add10.mv; strash; refactor; rewrite; dfraig; rewrite; dfraig; write_aiger -s add10y.aig"   ---gives--> add10y.aig
> aigtoaig add10y.aig add10y.aag   ---gives--> add10y.aag (this file)
Content of add10.v:
// realizable
module bench(clk, a, b, controllable_c, err);
  input clk;
  input [9:0] a;
  input [9:0] b;
  input [9:0] controllable_c;
  output err;
  reg err;

  initial
  begin
    err = 1'b0;
  end

  always @ (posedge clk)
  begin
    if(controllable_c == a + b)
         err = 1'b0;
      else
         err = 1'b1;
   end
endmodule
-------------------------------