add12y.aag

aag 195 36 2 1 157
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i0 controllable_c<0>
i1 controllable_c<1>
i2 controllable_c<2>
i3 controllable_c<3>
i4 controllable_c<4>
i5 controllable_c<5>
i6 controllable_c<6>
i7 controllable_c<7>
i8 controllable_c<8>
i9 controllable_c<9>
i10 controllable_c<10>
i11 controllable_c<11>
i12 a<0>
i13 a<1>
i14 a<2>
i15 a<3>
i16 a<4>
i17 a<5>
i18 a<6>
i19 a<7>
i20 a<8>
i21 a<9>
i22 a<10>
i23 a<11>
i24 b<0>
i25 b<1>
i26 b<2>
i27 b<3>
i28 b<4>
i29 b<5>
i30 b<6>
i31 b<7>
i32 b<8>
i33 b<9>
i34 b<10>
i35 b<11>
l0 n75
l1 err_out
o0 err
c
bench
This file was written by ABC on Sat Aug 31 20:25:01 2013
For information about AIGER format, refer to http://fmv.jku.at/aiger
-------------------------------
This AIGER file has been created by the following sequence of commands:
> vl2mv add12.v   ---gives--> add12.mv
> abc -c "read_blif_mv add12.mv; strash; refactor; rewrite; dfraig; rewrite; dfraig; write_aiger -s add12y.aig"   ---gives--> add12y.aig
> aigtoaig add12y.aig add12y.aag   ---gives--> add12y.aag (this file)
Content of add12.v:
// realizable
module bench(clk, a, b, controllable_c, err);
  input clk;
  input [11:0] a;
  input [11:0] b;
  input [11:0] controllable_c;
  output err;
  reg err;

  initial
  begin
    err = 1'b0;
  end

  always @ (posedge clk)
  begin
    if(controllable_c == a + b)
         err = 1'b0;
      else
         err = 1'b1;
   end
endmodule
-------------------------------