add2y.aag

aag 25 6 2 1 17
2
4
6
8
10
12
14 1
16 51
18
18 16 14
20 10 6
22 11 7
24 23 21
26 24 3
28 25 2
30 29 27
32 12 9
34 13 8
36 35 33
38 36 20
40 37 21
42 41 39
44 43 5
46 42 4
48 47 45
50 48 30
i0 controllable_c<0>
i1 controllable_c<1>
i2 a<0>
i3 a<1>
i4 b<0>
i5 b<1>
l0 n15
l1 err_out
o0 err
c
bench
This file was written by ABC on Sat Aug 31 20:24:59 2013
For information about AIGER format, refer to http://fmv.jku.at/aiger
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This AIGER file has been created by the following sequence of commands:
> vl2mv add2.v   ---gives--> add2.mv
> abc -c "read_blif_mv add2.mv; strash; refactor; rewrite; dfraig; rewrite; dfraig; write_aiger -s add2y.aig"   ---gives--> add2y.aig
> aigtoaig add2y.aig add2y.aag   ---gives--> add2y.aag (this file)
Content of add2.v:
// realizable
module bench(clk, a, b, controllable_c, err);
  input clk;
  input [1:0] a;
  input [1:0] b;
  input [1:0] controllable_c;
  output err;
  reg err;

  initial
  begin
    err = 1'b0;
  end

  always @ (posedge clk)
  begin
    if(controllable_c == a + b)
         err = 1'b0;
      else
         err = 1'b1;
   end
endmodule
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