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amba10c5y.aag
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i0 controllable_nhgrant0
i1 controllable_hgrant1
i2 controllable_locked
i3 controllable_nstart
i4 controllable_hgrant2
i5 i_hlock0
i6 controllable_hgrant3
i7 i_hlock1
i8 controllable_hgrant4
i9 i_hlock2
i10 controllable_hgrant5
i11 i_hlock3
i12 controllable_hgrant6
i13 i_hlock4
i14 i_hlock5
i15 controllable_hgrant7
i16 i_hlock6
i17 controllable_hgrant8
i18 controllable_hgrant9
i19 i_hlock7
i20 i_hlock8
i21 controllable_busreq
i22 i_hlock9
i23 i_hready
i24 i_hburst1
i25 i_hburst0
i26 i_hbusreq0
i27 i_hbusreq1
i28 i_hbusreq2
i29 i_hbusreq3
i30 controllable_ndecide
i31 i_hbusreq4
i32 i_hbusreq5
i33 i_hbusreq6
i34 i_hbusreq7
i35 i_hbusreq8
i36 i_hbusreq9
i37 controllable_hmaster3
i38 controllable_hmaster2
i39 controllable_hmaster1
i40 controllable_hmaster0
i41 controllable_hmastlock
l0 n87
l1 reg_i_hbusreq2_out
l2 reg_controllable_hgrant8_out
l3 reg_i_hbusreq3_out
l4 reg_controllable_hgrant9_out
l5 reg_i_hbusreq4_out
l6 reg_i_hbusreq5_out
l7 reg_i_hbusreq6_out
l8 reg_controllable_nstart_out
l9 reg_i_hbusreq7_out
l10 reg_i_hbusreq8_out
l11 reg_i_hbusreq9_out
l12 reg_stateG3_0_out
l13 reg_stateG3_1_out
l14 reg_stateG3_2_out
l15 reg_i_hlock9_out
l16 reg_stateA1_out
l17 reg_controllable_hmastlock_out
l18 reg_i_hlock8_out
l19 fair_cnt<0>_out
l20 fair_cnt<1>_out
l21 fair_cnt<2>_out
l22 reg_i_hlock7_out
l23 reg_controllable_hmaster0_out
l24 reg_stateG10_1_out
l25 reg_i_hlock6_out
l26 next_env_fair_out
l27 reg_stateG10_2_out
l28 reg_stateG2_out
l29 reg_i_hlock5_out
l30 reg_controllable_hmaster1_out
l31 reg_stateG10_3_out
l32 reg_i_hlock4_out
l33 reg_controllable_hmaster2_out
l34 reg_controllable_ndecide_out
l35 reg_stateG10_4_out
l36 reg_i_hready_out
l37 reg_i_hlock3_out
l38 reg_controllable_hmaster3_out
l39 reg_stateG10_5_out
l40 reg_controllable_hgrant1_out
l41 reg_i_hlock2_out
l42 reg_controllable_busreq_out
l43 reg_i_hlock1_out
l44 reg_stateG10_6_out
l45 reg_controllable_hgrant2_out
l46 reg_i_hlock0_out
l47 reg_controllable_nhgrant0_out
l48 reg_stateG10_7_out
l49 reg_controllable_hgrant3_out
l50 env_safe_err_happened_out
l51 reg_stateG10_8_out
l52 reg_controllable_hgrant4_out
l53 reg_stateG10_9_out
l54 reg_controllable_hgrant5_out
l55 reg_i_hbusreq0_out
l56 reg_controllable_hgrant6_out
l57 next_sys_fair<0>_out
l58 next_sys_fair<1>_out
l59 next_sys_fair<2>_out
l60 next_sys_fair<3>_out
l61 next_sys_fair<4>_out
l62 reg_i_hbusreq1_out
l63 reg_controllable_hgrant7_out
l64 reg_controllable_locked_out
o0 o_err
c
amba_10_new_5
This file was written by ABC on Sat Aug 31 20:24:45 2013
For information about AIGER format, refer to http://fmv.jku.at/aiger
-------------------------------
This AIGER file has been created by the following sequence of commands:
> vl2mv amba10c5.v ---gives--> amba10c5.mv
> abc -c "read_blif_mv amba10c5.mv; strash; refactor; rewrite; dfraig; rewrite; dfraig; write_aiger -s amba10c5y.aig" ---gives--> amba10c5y.aig
> aigtoaig amba10c5y.aig amba10c5y.aag ---gives--> amba10c5y.aag (this file)
Content of amba10c5.v:
module amba_10_new_5(
o_err,
i_clk,
i_hready,
i_hbusreq0,
i_hlock0,
i_hbusreq1,
i_hlock1,
i_hbusreq2,
i_hlock2,
i_hbusreq3,
i_hlock3,
i_hbusreq4,
i_hlock4,
i_hbusreq5,
i_hlock5,
i_hbusreq6,
i_hlock6,
i_hbusreq7,
i_hlock7,
i_hbusreq8,
i_hlock8,
i_hbusreq9,
i_hlock9,
i_hburst0,
i_hburst1,
controllable_hmaster0,
controllable_hmaster1,
controllable_hmaster2,
controllable_hmaster3,
controllable_hmastlock,
controllable_nstart,
controllable_ndecide,
controllable_locked,
controllable_nhgrant0,
controllable_hgrant1,
controllable_hgrant2,
controllable_hgrant3,
controllable_hgrant4,
controllable_hgrant5,
controllable_hgrant6,
controllable_hgrant7,
controllable_hgrant8,
controllable_hgrant9,
controllable_busreq);
input i_clk;
input i_hready;
input i_hbusreq0;
input i_hlock0;
input i_hbusreq1;
input i_hlock1;
input i_hbusreq2;
input i_hlock2;
input i_hbusreq3;
input i_hlock3;
input i_hbusreq4;
input i_hlock4;
input i_hbusreq5;
input i_hlock5;
input i_hbusreq6;
input i_hlock6;
input i_hbusreq7;
input i_hlock7;
input i_hbusreq8;
input i_hlock8;
input i_hbusreq9;
input i_hlock9;
input i_hburst0;
input i_hburst1;
input controllable_hmaster0;
input controllable_hmaster1;
input controllable_hmaster2;
input controllable_hmaster3;
input controllable_hmastlock;
input controllable_nstart;
input controllable_ndecide;
input controllable_locked;
input controllable_nhgrant0;
input controllable_hgrant1;
input controllable_hgrant2;
input controllable_hgrant3;
input controllable_hgrant4;
input controllable_hgrant5;
input controllable_hgrant6;
input controllable_hgrant7;
input controllable_hgrant8;
input controllable_hgrant9;
input controllable_busreq;
output o_err;
reg reg_i_hready;
reg reg_i_hbusreq0;
reg reg_i_hlock0;
reg reg_i_hbusreq1;
reg reg_i_hlock1;
reg reg_i_hbusreq2;
reg reg_i_hlock2;
reg reg_i_hbusreq3;
reg reg_i_hlock3;
reg reg_i_hbusreq4;
reg reg_i_hlock4;
reg reg_i_hbusreq5;
reg reg_i_hlock5;
reg reg_i_hbusreq6;
reg reg_i_hlock6;
reg reg_i_hbusreq7;
reg reg_i_hlock7;
reg reg_i_hbusreq8;
reg reg_i_hlock8;
reg reg_i_hbusreq9;
reg reg_i_hlock9;
reg reg_controllable_hmaster0;
reg reg_controllable_hmaster1;
reg reg_controllable_hmaster2;
reg reg_controllable_hmaster3;
reg reg_controllable_hmastlock;
reg reg_controllable_nstart;
reg reg_controllable_ndecide;
reg reg_controllable_locked;
reg reg_controllable_nhgrant0;
reg reg_controllable_hgrant1;
reg reg_controllable_hgrant2;
reg reg_controllable_hgrant3;
reg reg_controllable_hgrant4;
reg reg_controllable_hgrant5;
reg reg_controllable_hgrant6;
reg reg_controllable_hgrant7;
reg reg_controllable_hgrant8;
reg reg_controllable_hgrant9;
reg reg_controllable_busreq;
reg reg_stateA1;
reg reg_stateG2;
reg reg_stateG3_0;
reg reg_stateG3_1;
reg reg_stateG3_2;
reg reg_stateG10_1;
reg reg_stateG10_2;
reg reg_stateG10_3;
reg reg_stateG10_4;
reg reg_stateG10_5;
reg reg_stateG10_6;
reg reg_stateG10_7;