diff --git a/.gitmodules b/.gitmodules index 7de9fd0d02..a9cbf261df 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1139,6 +1139,9 @@ [submodule "vendor/grammars/thrift.tmbundle"] path = vendor/grammars/thrift.tmbundle url = https://github.com/textmate/thrift.tmbundle +[submodule "vendor/grammars/tlv-vscode"] + path = vendor/grammars/tlv-vscode + url = https://github.com/adamint/tlv-vscode [submodule "vendor/grammars/toml.tmbundle"] path = vendor/grammars/toml.tmbundle url = https://github.com/textmate/toml.tmbundle diff --git a/grammars.yml b/grammars.yml index 052574ba58..18293954f1 100644 --- a/grammars.yml +++ b/grammars.yml @@ -1024,6 +1024,8 @@ vendor/grammars/textproto-grammar: - source.textproto vendor/grammars/thrift.tmbundle: - source.thrift +vendor/grammars/tlv-vscode: +- source.tlverilog vendor/grammars/toml.tmbundle: - source.toml vendor/grammars/turtle.tmbundle: diff --git a/lib/linguist/heuristics.yml b/lib/linguist/heuristics.yml index 147b2c4635..c7eb38db44 100644 --- a/lib/linguist/heuristics.yml +++ b/lib/linguist/heuristics.yml @@ -147,7 +147,7 @@ disambiguations: - named_pattern: vb-class - pattern: '^\s*BEGIN\R\s*MultiUse\s*=.*\R\s*Persistable\s*=' - language: VBA - named_pattern: vb-class + named_pattern: vb-class - language: TeX pattern: '^\s*\\(?:NeedsTeXFormat|ProvidesClass){' - language: ObjectScript @@ -258,7 +258,7 @@ disambiguations: - language: Visual Basic 6.0 and: - named_pattern: vb-form - - pattern: '^\s*Begin\s+VB\.Form\s+' + - pattern: '^\s*Begin\s+VB\.Form\s+' - extensions: ['.fs'] rules: - language: Forth @@ -696,6 +696,10 @@ disambiguations: rules: - language: Java Server Pages pattern: '<%[@!=\s]?\s*(taglib|tag|include|attribute|variable)\s' +- extensions: ['.tlv'] + rules: + - language: TL-Verilog + pattern: '^\\.{0,10}TLV_version' - extensions: ['.toc'] rules: - language: World of Warcraft Addon Data diff --git a/lib/linguist/languages.yml b/lib/linguist/languages.yml index b9139595b4..89adb061cd 100644 --- a/lib/linguist/languages.yml +++ b/lib/linguist/languages.yml @@ -6726,6 +6726,14 @@ TI Program: - ".8xp.txt" language_id: 422 tm_scope: none +TL-Verilog: + type: programming + extensions: + - ".tlv" + tm_scope: source.tlverilog + ace_mode: verilog + color: "#C40023" + language_id: 118656070 TLA: type: programming color: "#4b0079" diff --git a/samples/TL-Verilog/calculator_kernel.tlv b/samples/TL-Verilog/calculator_kernel.tlv new file mode 100644 index 0000000000..2cf254b3de --- /dev/null +++ b/samples/TL-Verilog/calculator_kernel.tlv @@ -0,0 +1,71 @@ +\m4_TLV_version 1d: tl-x.org +\SV +m4+definitions([' + m4_include_url(['https://raw.githubusercontent.com/stevehoover/makerchip_examples/ceebf870862e222ebc6eaf92d5a7fb85a525d069/1st-claas_template_with_macros.tlv']) +']) +m4_makerchip_module_with_random_kernel_tb(my, ['assign passed = cyc_cnt > 20;']) +m4+definitions(['']) // A hack to reset line alignment to address the fact that the above macro is multi-line. +\TLV + // A default direct hookup from |in to |out. + m4+tlv_wrapper(|in, @0, |out, @0, /trans) + |in + @0 + $data[31:0] = >>1$output; + @1 + // Calculator logic + + + // Extract input fields from input data + $val1[31:0] = >>1$output; + $val2[31:0] = /trans$data[31:0]; + $op[2:0] = /trans$data[34:32]; + + //counter + $counter = $reset?0:(>>1$counter+1); + $valid = $reset || $counter; + + ?$valid + @1 + $sum[31:0] = $val1[31:0] + $val2[31:0]; + $diff[31:0] = $val1[31:0] - $val2[31:0]; + $mult[31:0] = $val1[31:0] * $val2[31:0]; + $quot[31:0] = $val1[31:0] / $val2[31:0]; + //@2 + $mem[31:0] = + $reset ? 0: + ($op[2:0]==3'b101) + ? >>1$mem[31:0] : >>1$output; + + + $output[31:0] = + $reset ? 0: + ($op[2:0]==3'b000) + ? $sum[31:0] : + ($op[2:0]==3'b001) + ? $diff[31:0] : + ($op[2:0]==3'b010) + ? $mult[31:0] : + ($op[2:0]==3'b011) + ? $quot[31:0] : + ($op[2:0]==3'b100) + ? >>1$mem[31:0] : $val1[31:0]; + + + |out + @0 + // Hook up inputs to outputs to implement a no-op kernel. + // Delete this to add your kernel. + $ANY = /top|in<>0$ANY; + + $ready = *out_ready; + *out_avail = $avail; + *out_data = $data; + //`BOGUS_USE($op $rand $ready) + `BOGUS_USE($ready) + + // Extract output data to the output field + /trans@0$data = |in@1$output; + + m4+rename_flow(/top, |in, @0, |out, @0, /trans) +\SV + endmodule \ No newline at end of file diff --git a/samples/TL-Verilog/warp-v_config.tlv b/samples/TL-Verilog/warp-v_config.tlv new file mode 100644 index 0000000000..03b236c11f --- /dev/null +++ b/samples/TL-Verilog/warp-v_config.tlv @@ -0,0 +1,46 @@ + +Viewed +@@ -0,0 +1,43 @@ +\m4_TLV_version 1d: tl-x.org +m4+definitions([' + // This file can be used to build a coarsely-configured implementation of WARP-V within makerchip.com. + // This enables exploration of a generated model (as TL-Verilog (without M4 macros) and/or Verilog/SystemVerilog). + // Simulation waveforms can be explored. + // + // High-level settings are described here. For detailed settings, consult the included warp-v.tlv file. + + + // ----------------------------------------------------------- + // CONFIGURATION: + + // ISA. Legal Values: [MINI, RISCV, MIPSI, POWER, DUMMY] + m4_define(M4_ISA, RISCV) + + // Standard configuration. Legal Values: [1-stage, 4-stage, 6-stage, none (and define individual parameters)] + m4_define(M4_STANDARD_CONFIG, 4-stage) + + + // OPTIONAL CONFIGURATION: + + // Branch predictor. Legal Values: [fallthrough, two_bit] + // m4_define(M4_BRANCH_PRED, fallthrough) + + + // DETAILED CONFIGURATION: + + // (See included warp-v.tlv) + + // ----------------------------------------------------------- + +']) +\SV + // Include WARP-V. + m4_include_lib(['https://raw.githubusercontent.com/stevehoover/warp-v/master/warp-v.tlv']) + +m4+module_def +\TLV + m4+warpv() + m4+warpv_makerchip_cnt10_tb() + m4+makerchip_pass_fail() +\SV + endmodule \ No newline at end of file diff --git a/test/test_heuristics.rb b/test/test_heuristics.rb index c8f51086c0..75c2413d6b 100755 --- a/test/test_heuristics.rb +++ b/test/test_heuristics.rb @@ -430,7 +430,7 @@ def test_fr_by_heuristics "Text" => all_fixtures("Text", "*.fr") }) end - + def test_frm_by_heuristics assert_heuristics({ "VBA" => all_fixtures("VBA", "*.frm"), @@ -935,6 +935,12 @@ def test_tag_by_heuristics }) end + def test_tlv_by_heuristics + assert_heuristics({ + "TL-Verilog" => all_fixtures("TL-Verilog", "*.tlv"), + }) + end + def test_toc_by_heuristics assert_heuristics({ "TeX" => all_fixtures("TeX", "*.toc"), diff --git a/vendor/README.md b/vendor/README.md index f94010a8a5..490280318b 100644 --- a/vendor/README.md +++ b/vendor/README.md @@ -524,6 +524,7 @@ This is a list of grammars that Linguist selects to provide syntax highlighting - **Sway:** [FuelLabs/sway-vscode-plugin](https://github.com/FuelLabs/sway-vscode-plugin) - **Swift:** [textmate/swift.tmbundle](https://github.com/textmate/swift.tmbundle) - **SystemVerilog:** [TheClams/SystemVerilog](https://github.com/TheClams/SystemVerilog) +- **TL-Verilog:** [adamint/tlv-vscode](https://github.com/adamint/tlv-vscode) - **TLA:** [tlaplus-community/tree-sitter-tlaplus](https://github.com/tlaplus-community/tree-sitter-tlaplus) 🐌 - **TOML:** [textmate/toml.tmbundle](https://github.com/textmate/toml.tmbundle) - **TSQL:** [beau-witter/language-tsql](https://github.com/beau-witter/language-tsql) diff --git a/vendor/grammars/tlv-vscode b/vendor/grammars/tlv-vscode new file mode 160000 index 0000000000..af933c4b87 --- /dev/null +++ b/vendor/grammars/tlv-vscode @@ -0,0 +1 @@ +Subproject commit af933c4b87d36310f731cad7808ff8c386c3e433 diff --git a/vendor/licenses/git_submodule/tlv-vscode.dep.yml b/vendor/licenses/git_submodule/tlv-vscode.dep.yml new file mode 100644 index 0000000000..bf2521dffd --- /dev/null +++ b/vendor/licenses/git_submodule/tlv-vscode.dep.yml @@ -0,0 +1,33 @@ +--- +name: tlv-vscode +version: af933c4b87d36310f731cad7808ff8c386c3e433 +type: git_submodule +homepage: https://github.com/adamint/tlv-vscode +license: mit +licenses: +- sources: LICENSE + text: | + The MIT License (MIT) + + Copyright (c) 2016-2017 Dmytro Bogatov + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to deal + in the Software without restriction, including without limitation the rights + to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in all + copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + SOFTWARE. +- sources: README.md + text: "[MIT](LICENSE)" +notices: []