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impl_x86__base_implementation.inl
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impl_x86__base_implementation.inl
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// Copyright 2017 Google LLC
// Copyright 2020 Intel Corporation
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include <stdbool.h>
#include <string.h>
#include "copy.h"
#include "cpuinfo_x86.h"
#include "equals.h"
#include "internal/bit_utils.h"
#include "internal/cpuid_x86.h"
#if !defined(CPU_FEATURES_ARCH_X86)
#error "Cannot compile cpuinfo_x86 on a non x86 platform."
#endif
////////////////////////////////////////////////////////////////////////////////
// Definitions for CpuId and GetXCR0Eax.
////////////////////////////////////////////////////////////////////////////////
#if defined(CPU_FEATURES_MOCK_CPUID_X86)
// Implementation will be provided by test/cpuinfo_x86_test.cc.
#elif defined(CPU_FEATURES_COMPILER_CLANG) || defined(CPU_FEATURES_COMPILER_GCC)
#include <cpuid.h>
Leaf GetCpuidLeaf(uint32_t leaf_id, int ecx) {
Leaf leaf;
__cpuid_count(leaf_id, ecx, leaf.eax, leaf.ebx, leaf.ecx, leaf.edx);
return leaf;
}
uint32_t GetXCR0Eax(void) {
uint32_t eax, edx;
/* named form of xgetbv not supported on OSX, so must use byte form, see:
https://github.com/asmjit/asmjit/issues/78
*/
__asm(".byte 0x0F, 0x01, 0xd0" : "=a"(eax), "=d"(edx) : "c"(0));
return eax;
}
#elif defined(CPU_FEATURES_COMPILER_MSC)
#include <immintrin.h>
#include <intrin.h> // For __cpuidex()
Leaf GetCpuidLeaf(uint32_t leaf_id, int ecx) {
Leaf leaf;
int data[4];
__cpuidex(data, leaf_id, ecx);
leaf.eax = data[0];
leaf.ebx = data[1];
leaf.ecx = data[2];
leaf.edx = data[3];
return leaf;
}
uint32_t GetXCR0Eax(void) { return (uint32_t)_xgetbv(0); }
#else
#error "Unsupported compiler, x86 cpuid requires either GCC, Clang or MSVC."
#endif
static Leaf CpuId(uint32_t leaf_id) { return GetCpuidLeaf(leaf_id, 0); }
static const Leaf kEmptyLeaf;
static Leaf SafeCpuIdEx(uint32_t max_cpuid_leaf, uint32_t leaf_id, int ecx) {
if (leaf_id <= max_cpuid_leaf) {
return GetCpuidLeaf(leaf_id, ecx);
} else {
return kEmptyLeaf;
}
}
static Leaf SafeCpuId(uint32_t max_cpuid_leaf, uint32_t leaf_id) {
return SafeCpuIdEx(max_cpuid_leaf, leaf_id, 0);
}
////////////////////////////////////////////////////////////////////////////////
// OS support
// TODO: Add documentation
////////////////////////////////////////////////////////////////////////////////
#define MASK_XMM 0x2
#define MASK_YMM 0x4
#define MASK_MASKREG 0x20
#define MASK_ZMM0_15 0x40
#define MASK_ZMM16_31 0x80
#define MASK_XTILECFG 0x20000
#define MASK_XTILEDATA 0x40000
static bool HasMask(uint32_t value, uint32_t mask) {
return (value & mask) == mask;
}
// Checks that operating system saves and restores xmm registers during context
// switches.
static bool HasXmmOsXSave(uint32_t xcr0_eax) {
return HasMask(xcr0_eax, MASK_XMM);
}
// Checks that operating system saves and restores ymm registers during context
// switches.
static bool HasYmmOsXSave(uint32_t xcr0_eax) {
return HasMask(xcr0_eax, MASK_XMM | MASK_YMM);
}
// Checks that operating system saves and restores zmm registers during context
// switches.
static bool HasZmmOsXSave(uint32_t xcr0_eax) {
return HasMask(xcr0_eax, MASK_XMM | MASK_YMM | MASK_MASKREG | MASK_ZMM0_15 |
MASK_ZMM16_31);
}
// Checks that operating system saves and restores AMX/TMUL state during context
// switches.
static bool HasTmmOsXSave(uint32_t xcr0_eax) {
return HasMask(xcr0_eax, MASK_XMM | MASK_YMM | MASK_MASKREG | MASK_ZMM0_15 |
MASK_ZMM16_31 | MASK_XTILECFG | MASK_XTILEDATA);
}
////////////////////////////////////////////////////////////////////////////////
// Vendor
////////////////////////////////////////////////////////////////////////////////
static void SetVendor(const Leaf leaf, char* const vendor) {
*(uint32_t*)(vendor) = leaf.ebx;
*(uint32_t*)(vendor + 4) = leaf.edx;
*(uint32_t*)(vendor + 8) = leaf.ecx;
vendor[12] = '\0';
}
static int IsVendor(const Leaf leaf, const char* const name) {
const uint32_t ebx = *(const uint32_t*)(name);
const uint32_t edx = *(const uint32_t*)(name + 4);
const uint32_t ecx = *(const uint32_t*)(name + 8);
return leaf.ebx == ebx && leaf.ecx == ecx && leaf.edx == edx;
}
static int IsVendorByX86Info(const X86Info* info, const char* const name) {
return equals(info->vendor, name, sizeof(info->vendor));
}
void FillX86BrandString(char brand_string[49]) {
const Leaf leaf_ext_0 = CpuId(0x80000000);
const uint32_t max_cpuid_leaf_ext = leaf_ext_0.eax;
const Leaf leaves[3] = {
SafeCpuId(max_cpuid_leaf_ext, 0x80000002),
SafeCpuId(max_cpuid_leaf_ext, 0x80000003),
SafeCpuId(max_cpuid_leaf_ext, 0x80000004),
};
#if __STDC_VERSION__ >= 201112L
_Static_assert(sizeof(leaves) == 48, "Leaves must be packed");
#endif
copy(brand_string, (const char*)(leaves), 48);
brand_string[48] = '\0';
}
////////////////////////////////////////////////////////////////////////////////
// CpuId
////////////////////////////////////////////////////////////////////////////////
static bool HasSecondFMA(uint32_t model) {
// Skylake server
if (model == 0x55) {
char proc_name[49] = {0};
FillX86BrandString(proc_name);
// detect Xeon
if (proc_name[9] == 'X') {
// detect Silver or Bronze
if (proc_name[17] == 'S' || proc_name[17] == 'B') return false;
// detect Gold 5_20 and below, except for Gold 53__
if (proc_name[17] == 'G' && proc_name[22] == '5')
return ((proc_name[23] == '3') ||
(proc_name[24] == '2' && proc_name[25] == '2'));
// detect Xeon W 210x
if (proc_name[17] == 'W' && proc_name[21] == '0') return false;
// detect Xeon D 2xxx
if (proc_name[17] == 'D' && proc_name[19] == '2' && proc_name[20] == '1')
return false;
}
return true;
}
// Cannon Lake client
if (model == 0x66) return false;
// Ice Lake client
if (model == 0x7d || model == 0x7e) return false;
// This is the right default...
return true;
}
// Internal structure to hold the OS support for vector operations.
// Avoid to recompute them since each call to cpuid is ~100 cycles.
typedef struct {
bool sse_registers;
bool avx_registers;
bool avx512_registers;
bool amx_registers;
} OsPreserves;
// These two functions have to be implemented by the OS, that is the file
// including this file.
static void OverrideOsPreserves(OsPreserves* os_preserves);
static void DetectFeaturesFromOs(X86Features* features);
// Reference https://en.wikipedia.org/wiki/CPUID.
static void ParseCpuId(const uint32_t max_cpuid_leaf, X86Info* info,
OsPreserves* os_preserves) {
const Leaf leaf_1 = SafeCpuId(max_cpuid_leaf, 1);
const Leaf leaf_7 = SafeCpuId(max_cpuid_leaf, 7);
const Leaf leaf_7_1 = SafeCpuIdEx(max_cpuid_leaf, 7, 1);
const bool have_xsave = IsBitSet(leaf_1.ecx, 26);
const bool have_osxsave = IsBitSet(leaf_1.ecx, 27);
const bool have_xcr0 = have_xsave && have_osxsave;
const uint32_t family = ExtractBitRange(leaf_1.eax, 11, 8);
const uint32_t extended_family = ExtractBitRange(leaf_1.eax, 27, 20);
const uint32_t model = ExtractBitRange(leaf_1.eax, 7, 4);
const uint32_t extended_model = ExtractBitRange(leaf_1.eax, 19, 16);
X86Features* const features = &info->features;
info->family = extended_family + family;
info->model = (extended_model << 4) + model;
info->stepping = ExtractBitRange(leaf_1.eax, 3, 0);
features->fpu = IsBitSet(leaf_1.edx, 0);
features->tsc = IsBitSet(leaf_1.edx, 4);
features->cx8 = IsBitSet(leaf_1.edx, 8);
features->clfsh = IsBitSet(leaf_1.edx, 19);
features->mmx = IsBitSet(leaf_1.edx, 23);
features->ss = IsBitSet(leaf_1.edx, 27);
features->pclmulqdq = IsBitSet(leaf_1.ecx, 1);
features->smx = IsBitSet(leaf_1.ecx, 6);
features->cx16 = IsBitSet(leaf_1.ecx, 13);
features->dca = IsBitSet(leaf_1.ecx, 18);
features->movbe = IsBitSet(leaf_1.ecx, 22);
features->popcnt = IsBitSet(leaf_1.ecx, 23);
features->aes = IsBitSet(leaf_1.ecx, 25);
features->f16c = IsBitSet(leaf_1.ecx, 29);
features->rdrnd = IsBitSet(leaf_1.ecx, 30);
features->sgx = IsBitSet(leaf_7.ebx, 2);
features->bmi1 = IsBitSet(leaf_7.ebx, 3);
features->hle = IsBitSet(leaf_7.ebx, 4);
features->bmi2 = IsBitSet(leaf_7.ebx, 8);
features->erms = IsBitSet(leaf_7.ebx, 9);
features->rtm = IsBitSet(leaf_7.ebx, 11);
features->rdseed = IsBitSet(leaf_7.ebx, 18);
features->clflushopt = IsBitSet(leaf_7.ebx, 23);
features->clwb = IsBitSet(leaf_7.ebx, 24);
features->sha = IsBitSet(leaf_7.ebx, 29);
features->vaes = IsBitSet(leaf_7.ecx, 9);
features->vpclmulqdq = IsBitSet(leaf_7.ecx, 10);
features->adx = IsBitSet(leaf_7.ebx, 19);
/////////////////////////////////////////////////////////////////////////////
// The following section is devoted to Vector Extensions.
/////////////////////////////////////////////////////////////////////////////
// CPU with AVX expose XCR0 which enables checking vector extensions OS
// support through cpuid.
if (have_xcr0) {
// Here we rely exclusively on cpuid for both CPU and OS support of vector
// extensions.
const uint32_t xcr0_eax = GetXCR0Eax();
os_preserves->sse_registers = HasXmmOsXSave(xcr0_eax);
os_preserves->avx_registers = HasYmmOsXSave(xcr0_eax);
os_preserves->avx512_registers = HasZmmOsXSave(xcr0_eax);
os_preserves->amx_registers = HasTmmOsXSave(xcr0_eax);
OverrideOsPreserves(os_preserves);
if (os_preserves->sse_registers) {
features->sse = IsBitSet(leaf_1.edx, 25);
features->sse2 = IsBitSet(leaf_1.edx, 26);
features->sse3 = IsBitSet(leaf_1.ecx, 0);
features->ssse3 = IsBitSet(leaf_1.ecx, 9);
features->sse4_1 = IsBitSet(leaf_1.ecx, 19);
features->sse4_2 = IsBitSet(leaf_1.ecx, 20);
}
if (os_preserves->avx_registers) {
features->fma3 = IsBitSet(leaf_1.ecx, 12);
features->avx = IsBitSet(leaf_1.ecx, 28);
features->avx2 = IsBitSet(leaf_7.ebx, 5);
}
if (os_preserves->avx512_registers) {
features->avx512f = IsBitSet(leaf_7.ebx, 16);
features->avx512cd = IsBitSet(leaf_7.ebx, 28);
features->avx512er = IsBitSet(leaf_7.ebx, 27);
features->avx512pf = IsBitSet(leaf_7.ebx, 26);
features->avx512bw = IsBitSet(leaf_7.ebx, 30);
features->avx512dq = IsBitSet(leaf_7.ebx, 17);
features->avx512vl = IsBitSet(leaf_7.ebx, 31);
features->avx512ifma = IsBitSet(leaf_7.ebx, 21);
features->avx512vbmi = IsBitSet(leaf_7.ecx, 1);
features->avx512vbmi2 = IsBitSet(leaf_7.ecx, 6);
features->avx512vnni = IsBitSet(leaf_7.ecx, 11);
features->avx512bitalg = IsBitSet(leaf_7.ecx, 12);
features->avx512vpopcntdq = IsBitSet(leaf_7.ecx, 14);
features->avx512_4vnniw = IsBitSet(leaf_7.edx, 2);
features->avx512_4vbmi2 = IsBitSet(leaf_7.edx, 3);
features->avx512_second_fma = HasSecondFMA(info->model);
features->avx512_4fmaps = IsBitSet(leaf_7.edx, 3);
features->avx512_bf16 = IsBitSet(leaf_7_1.eax, 5);
features->avx512_vp2intersect = IsBitSet(leaf_7.edx, 8);
}
if (os_preserves->amx_registers) {
features->amx_bf16 = IsBitSet(leaf_7.edx, 22);
features->amx_tile = IsBitSet(leaf_7.edx, 24);
features->amx_int8 = IsBitSet(leaf_7.edx, 25);
}
} else {
// When XCR0 is not available (Atom based or older cpus) we need to defer to
// the OS via custom code.
DetectFeaturesFromOs(features);
// Now that we have queried the OS for SSE support, we report this back to
// os_preserves. This is needed in case of AMD CPU's to enable testing of
// sse4a (See ParseExtraAMDCpuId below).
if (features->sse) os_preserves->sse_registers = true;
}
}
// Reference
// https://en.wikipedia.org/wiki/CPUID#EAX=80000000h:_Get_Highest_Extended_Function_Implemented.
static Leaf GetLeafByIdAMD(uint32_t leaf_id) {
uint32_t max_extended = CpuId(0x80000000).eax;
return SafeCpuId(max_extended, leaf_id);
}
static void ParseExtraAMDCpuId(X86Info* info, OsPreserves os_preserves) {
const Leaf leaf_80000001 = GetLeafByIdAMD(0x80000001);
X86Features* const features = &info->features;
if (os_preserves.sse_registers) {
features->sse4a = IsBitSet(leaf_80000001.ecx, 6);
}
if (os_preserves.avx_registers) {
features->fma4 = IsBitSet(leaf_80000001.ecx, 16);
}
}
static const X86Info kEmptyX86Info;
static const OsPreserves kEmptyOsPreserves;
X86Info GetX86Info(void) {
X86Info info = kEmptyX86Info;
const Leaf leaf_0 = CpuId(0);
const bool is_intel = IsVendor(leaf_0, CPU_FEATURES_VENDOR_GENUINE_INTEL);
const bool is_amd = IsVendor(leaf_0, CPU_FEATURES_VENDOR_AUTHENTIC_AMD);
const bool is_hygon = IsVendor(leaf_0, CPU_FEATURES_VENDOR_HYGON_GENUINE);
SetVendor(leaf_0, info.vendor);
if (is_intel || is_amd || is_hygon) {
OsPreserves os_preserves = kEmptyOsPreserves;
const uint32_t max_cpuid_leaf = leaf_0.eax;
ParseCpuId(max_cpuid_leaf, &info, &os_preserves);
if (is_amd || is_hygon) {
ParseExtraAMDCpuId(&info, os_preserves);
}
}
return info;
}
////////////////////////////////////////////////////////////////////////////////
// Microarchitecture
////////////////////////////////////////////////////////////////////////////////
#define CPUID(FAMILY, MODEL) ((((FAMILY)&0xFF) << 8) | ((MODEL)&0xFF))
X86Microarchitecture GetX86Microarchitecture(const X86Info* info) {
if (IsVendorByX86Info(info, CPU_FEATURES_VENDOR_GENUINE_INTEL)) {
switch (CPUID(info->family, info->model)) {
case CPUID(0x06, 0x1C): // Intel(R) Atom(TM) CPU 230 @ 1.60GHz
case CPUID(0x06, 0x35):
case CPUID(0x06, 0x36):
case CPUID(0x06, 0x70): // https://en.wikichip.org/wiki/intel/atom/230
// https://en.wikipedia.org/wiki/Bonnell_(microarchitecture)
return INTEL_ATOM_BNL;
case CPUID(0x06, 0x37):
case CPUID(0x06, 0x4C):
// https://en.wikipedia.org/wiki/Silvermont
return INTEL_ATOM_SMT;
case CPUID(0x06, 0x5C):
// https://en.wikipedia.org/wiki/Goldmont
return INTEL_ATOM_GMT;
case CPUID(0x06, 0x0F):
case CPUID(0x06, 0x16):
// https://en.wikipedia.org/wiki/Intel_Core_(microarchitecture)
return INTEL_CORE;
case CPUID(0x06, 0x17):
case CPUID(0x06, 0x1D):
// https://en.wikipedia.org/wiki/Penryn_(microarchitecture)
return INTEL_PNR;
case CPUID(0x06, 0x1A):
case CPUID(0x06, 0x1E):
case CPUID(0x06, 0x1F):
case CPUID(0x06, 0x2E):
// https://en.wikipedia.org/wiki/Nehalem_(microarchitecture)
return INTEL_NHM;
case CPUID(0x06, 0x25):
case CPUID(0x06, 0x2C):
case CPUID(0x06, 0x2F):
// https://en.wikipedia.org/wiki/Westmere_(microarchitecture)
return INTEL_WSM;
case CPUID(0x06, 0x2A):
case CPUID(0x06, 0x2D):
// https://en.wikipedia.org/wiki/Sandy_Bridge#Models_and_steppings
return INTEL_SNB;
case CPUID(0x06, 0x3A):
case CPUID(0x06, 0x3E):
// https://en.wikipedia.org/wiki/Ivy_Bridge_(microarchitecture)#Models_and_steppings
return INTEL_IVB;
case CPUID(0x06, 0x3C):
case CPUID(0x06, 0x3F):
case CPUID(0x06, 0x45):
case CPUID(0x06, 0x46):
// https://en.wikipedia.org/wiki/Haswell_(microarchitecture)
return INTEL_HSW;
case CPUID(0x06, 0x3D):
case CPUID(0x06, 0x47):
case CPUID(0x06, 0x4F):
case CPUID(0x06, 0x56):
// https://en.wikipedia.org/wiki/Broadwell_(microarchitecture)
return INTEL_BDW;
case CPUID(0x06, 0x4E):
case CPUID(0x06, 0x55):
case CPUID(0x06, 0x5E):
// https://en.wikipedia.org/wiki/Skylake_(microarchitecture)
return INTEL_SKL;
case CPUID(0x06, 0x66):
// https://en.wikipedia.org/wiki/Cannon_Lake_(microarchitecture)
return INTEL_CNL;
case CPUID(0x06, 0x7D): // client
case CPUID(0x06, 0x7E): // client
case CPUID(0x06, 0x9D): // NNP-I
case CPUID(0x06, 0x6A): // server
case CPUID(0x06, 0x6C): // server
// https://en.wikipedia.org/wiki/Ice_Lake_(microprocessor)
return INTEL_ICL;
case CPUID(0x06, 0x8C):
case CPUID(0x06, 0x8D):
// https://en.wikipedia.org/wiki/Tiger_Lake_(microarchitecture)
return INTEL_TGL;
case CPUID(0x06, 0x8F):
// https://en.wikipedia.org/wiki/Sapphire_Rapids
return INTEL_SPR;
case CPUID(0x06, 0x8E):
switch (info->stepping) {
case 9:
return INTEL_KBL; // https://en.wikipedia.org/wiki/Kaby_Lake
case 10:
return INTEL_CFL; // https://en.wikipedia.org/wiki/Coffee_Lake
case 11:
return INTEL_WHL; // https://en.wikipedia.org/wiki/Whiskey_Lake_(microarchitecture)
default:
return X86_UNKNOWN;
}
case CPUID(0x06, 0x9E):
if (info->stepping > 9) {
// https://en.wikipedia.org/wiki/Coffee_Lake
return INTEL_CFL;
} else {
// https://en.wikipedia.org/wiki/Kaby_Lake
return INTEL_KBL;
}
default:
return X86_UNKNOWN;
}
}
if (IsVendorByX86Info(info, CPU_FEATURES_VENDOR_AUTHENTIC_AMD)) {
switch (CPUID(info->family, info->model)) {
// https://en.wikichip.org/wiki/amd/cpuid
case CPUID(0xF, 0x04):
case CPUID(0xF, 0x05):
case CPUID(0xF, 0x07):
case CPUID(0xF, 0x08):
case CPUID(0xF, 0x0C):
case CPUID(0xF, 0x0E):
case CPUID(0xF, 0x0F):
case CPUID(0xF, 0x14):
case CPUID(0xF, 0x15):
case CPUID(0xF, 0x17):
case CPUID(0xF, 0x18):
case CPUID(0xF, 0x1B):
case CPUID(0xF, 0x1C):
case CPUID(0xF, 0x1F):
case CPUID(0xF, 0x21):
case CPUID(0xF, 0x23):
case CPUID(0xF, 0x24):
case CPUID(0xF, 0x25):
case CPUID(0xF, 0x27):
case CPUID(0xF, 0x2B):
case CPUID(0xF, 0x2C):
case CPUID(0xF, 0x2F):
case CPUID(0xF, 0x41):
case CPUID(0xF, 0x43):
case CPUID(0xF, 0x48):
case CPUID(0xF, 0x4B):
case CPUID(0xF, 0x4C):
case CPUID(0xF, 0x4F):
case CPUID(0xF, 0x5D):
case CPUID(0xF, 0x5F):
case CPUID(0xF, 0x68):
case CPUID(0xF, 0x6B):
case CPUID(0xF, 0x6F):
case CPUID(0xF, 0x7F):
case CPUID(0xF, 0xC1):
return AMD_HAMMER;
case CPUID(0x10, 0x02):
case CPUID(0x10, 0x04):
case CPUID(0x10, 0x05):
case CPUID(0x10, 0x06):
case CPUID(0x10, 0x08):
case CPUID(0x10, 0x09):
case CPUID(0x10, 0x0A):
return AMD_K10;
case CPUID(0x11, 0x03):
// http://developer.amd.com/wordpress/media/2012/10/41788.pdf
return AMD_K11;
case CPUID(0x12, 0x01):
// https://www.amd.com/system/files/TechDocs/44739_12h_Rev_Gd.pdf
return AMD_K12;
case CPUID(0x14, 0x00):
case CPUID(0x14, 0x01):
case CPUID(0x14, 0x02):
// https://www.amd.com/system/files/TechDocs/47534_14h_Mod_00h-0Fh_Rev_Guide.pdf
return AMD_BOBCAT;
case CPUID(0x15, 0x01):
// https://en.wikichip.org/wiki/amd/microarchitectures/bulldozer
return AMD_BULLDOZER;
case CPUID(0x15, 0x02):
case CPUID(0x15, 0x11):
case CPUID(0x15, 0x13):
// https://en.wikichip.org/wiki/amd/microarchitectures/piledriver
return AMD_PILEDRIVER;
case CPUID(0x15, 0x30):
case CPUID(0x15, 0x38):
// https://en.wikichip.org/wiki/amd/microarchitectures/steamroller
return AMD_STREAMROLLER;
case CPUID(0x15, 0x60):
case CPUID(0x15, 0x65):
case CPUID(0x15, 0x70):
// https://en.wikichip.org/wiki/amd/microarchitectures/excavator
return AMD_EXCAVATOR;
case CPUID(0x16, 0x00):
return AMD_JAGUAR;
case CPUID(0x16, 0x30):
return AMD_PUMA;
case CPUID(0x17, 0x01):
case CPUID(0x17, 0x11):
case CPUID(0x17, 0x18):
case CPUID(0x17, 0x20):
// https://en.wikichip.org/wiki/amd/microarchitectures/zen
return AMD_ZEN;
case CPUID(0x17, 0x08):
// https://en.wikichip.org/wiki/amd/microarchitectures/zen%2B
return AMD_ZEN_PLUS;
case CPUID(0x17, 0x31):
case CPUID(0x17, 0x47):
case CPUID(0x17, 0x60):
case CPUID(0x17, 0x68):
case CPUID(0x17, 0x71):
case CPUID(0x17, 0x90):
case CPUID(0x17, 0x98):
// https://en.wikichip.org/wiki/amd/microarchitectures/zen_2
return AMD_ZEN2;
case CPUID(0x19, 0x01):
case CPUID(0x19, 0x21):
case CPUID(0x19, 0x30):
case CPUID(0x19, 0x40):
case CPUID(0x19, 0x50):
// https://en.wikichip.org/wiki/amd/microarchitectures/zen_3
return AMD_ZEN3;
default:
return X86_UNKNOWN;
}
}
if (IsVendorByX86Info(info, CPU_FEATURES_VENDOR_HYGON_GENUINE)) {
switch (CPUID(info->family, info->model)) {
case CPUID(0x18, 0x00):
return AMD_ZEN;
}
}
return X86_UNKNOWN;
}
////////////////////////////////////////////////////////////////////////////////
// CacheInfo
////////////////////////////////////////////////////////////////////////////////
static const CacheLevelInfo kEmptyCacheLevelInfo;
static CacheLevelInfo GetCacheLevelInfo(const uint32_t reg) {
const int UNDEF = -1;
const int KiB = 1024;
const int MiB = 1024 * KiB;
switch (reg) {
case 0x01:
return (CacheLevelInfo){.level = UNDEF,
.cache_type = CPU_FEATURE_CACHE_TLB,
.cache_size = 4 * KiB,
.ways = 4,
.line_size = UNDEF,
.tlb_entries = 32,
.partitioning = 0};
case 0x02:
return (CacheLevelInfo){.level = UNDEF,
.cache_type = CPU_FEATURE_CACHE_TLB,
.cache_size = 4 * MiB,
.ways = 0xFF,
.line_size = UNDEF,
.tlb_entries = 2,
.partitioning = 0};
case 0x03:
return (CacheLevelInfo){.level = UNDEF,
.cache_type = CPU_FEATURE_CACHE_TLB,
.cache_size = 4 * KiB,
.ways = 4,
.line_size = UNDEF,
.tlb_entries = 64,
.partitioning = 0};
case 0x04:
return (CacheLevelInfo){.level = UNDEF,
.cache_type = CPU_FEATURE_CACHE_TLB,
.cache_size = 4 * MiB,
.ways = 4,
.line_size = UNDEF,
.tlb_entries = 8,
.partitioning = 0};
case 0x05:
return (CacheLevelInfo){.level = UNDEF,
.cache_type = CPU_FEATURE_CACHE_TLB,
.cache_size = 4 * MiB,
.ways = 4,
.line_size = UNDEF,
.tlb_entries = 32,
.partitioning = 0};
case 0x06:
return (CacheLevelInfo){.level = 1,
.cache_type = CPU_FEATURE_CACHE_INSTRUCTION,
.cache_size = 8 * KiB,
.ways = 4,
.line_size = 32,
.tlb_entries = UNDEF,
.partitioning = 0};
case 0x08:
return (CacheLevelInfo){.level = 1,
.cache_type = CPU_FEATURE_CACHE_INSTRUCTION,
.cache_size = 16 * KiB,
.ways = 4,
.line_size = 32,
.tlb_entries = UNDEF,
.partitioning = 0};
case 0x09:
return (CacheLevelInfo){.level = 1,
.cache_type = CPU_FEATURE_CACHE_INSTRUCTION,
.cache_size = 32 * KiB,
.ways = 4,
.line_size = 64,
.tlb_entries = UNDEF,
.partitioning = 0};
case 0x0A:
return (CacheLevelInfo){.level = 1,
.cache_type = CPU_FEATURE_CACHE_DATA,
.cache_size = 8 * KiB,
.ways = 2,
.line_size = 32,
.tlb_entries = UNDEF,
.partitioning = 0};
case 0x0B:
return (CacheLevelInfo){.level = UNDEF,
.cache_type = CPU_FEATURE_CACHE_TLB,
.cache_size = 4 * MiB,
.ways = 4,
.line_size = UNDEF,
.tlb_entries = 4,
.partitioning = 0};
case 0x0C:
return (CacheLevelInfo){.level = 1,
.cache_type = CPU_FEATURE_CACHE_DATA,
.cache_size = 16 * KiB,
.ways = 4,
.line_size = 32,
.tlb_entries = UNDEF,
.partitioning = 0};
case 0x0D:
return (CacheLevelInfo){.level = 1,
.cache_type = CPU_FEATURE_CACHE_DATA,
.cache_size = 16 * KiB,
.ways = 4,
.line_size = 64,
.tlb_entries = UNDEF,
.partitioning = 0};
case 0x0E:
return (CacheLevelInfo){.level = 1,
.cache_type = CPU_FEATURE_CACHE_DATA,
.cache_size = 24 * KiB,
.ways = 6,
.line_size = 64,
.tlb_entries = UNDEF,
.partitioning = 0};
case 0x1D:
return (CacheLevelInfo){.level = 2,
.cache_type = CPU_FEATURE_CACHE_DATA,
.cache_size = 128 * KiB,
.ways = 2,
.line_size = 64,
.tlb_entries = UNDEF,
.partitioning = 0};
case 0x21:
return (CacheLevelInfo){.level = 2,
.cache_type = CPU_FEATURE_CACHE_DATA,
.cache_size = 256 * KiB,
.ways = 8,
.line_size = 64,
.tlb_entries = UNDEF,
.partitioning = 0};
case 0x22:
return (CacheLevelInfo){.level = 3,
.cache_type = CPU_FEATURE_CACHE_DATA,
.cache_size = 512 * KiB,
.ways = 4,
.line_size = 64,
.tlb_entries = UNDEF,
.partitioning = 2};
case 0x23:
return (CacheLevelInfo){.level = 3,
.cache_type = CPU_FEATURE_CACHE_DATA,
.cache_size = 1 * MiB,
.ways = 8,
.line_size = 64,
.tlb_entries = UNDEF,
.partitioning = 2};
case 0x24:
return (CacheLevelInfo){.level = 2,
.cache_type = CPU_FEATURE_CACHE_DATA,
.cache_size = 1 * MiB,
.ways = 16,
.line_size = 64,
.tlb_entries = UNDEF,
.partitioning = 0};
case 0x25:
return (CacheLevelInfo){.level = 3,
.cache_type = CPU_FEATURE_CACHE_DATA,
.cache_size = 2 * MiB,
.ways = 8,
.line_size = 64,
.tlb_entries = UNDEF,
.partitioning = 2};
case 0x29:
return (CacheLevelInfo){.level = 3,
.cache_type = CPU_FEATURE_CACHE_DATA,
.cache_size = 4 * MiB,
.ways = 8,
.line_size = 64,
.tlb_entries = UNDEF,
.partitioning = 2};
case 0x2C:
return (CacheLevelInfo){.level = 1,
.cache_type = CPU_FEATURE_CACHE_DATA,
.cache_size = 32 * KiB,
.ways = 8,
.line_size = 64,
.tlb_entries = UNDEF,
.partitioning = 0};
case 0x30:
return (CacheLevelInfo){.level = 1,
.cache_type = CPU_FEATURE_CACHE_INSTRUCTION,
.cache_size = 32 * KiB,
.ways = 8,
.line_size = 64,
.tlb_entries = UNDEF,
.partitioning = 0};
case 0x40:
return (CacheLevelInfo){.level = UNDEF,
.cache_type = CPU_FEATURE_CACHE_DATA,
.cache_size = UNDEF,
.ways = UNDEF,
.line_size = UNDEF,
.tlb_entries = UNDEF,
.partitioning = 0};
case 0x41:
return (CacheLevelInfo){.level = 2,
.cache_type = CPU_FEATURE_CACHE_DATA,
.cache_size = 128 * KiB,
.ways = 4,
.line_size = 32,
.tlb_entries = UNDEF,
.partitioning = 0};
case 0x42:
return (CacheLevelInfo){.level = 2,
.cache_type = CPU_FEATURE_CACHE_DATA,
.cache_size = 256 * KiB,
.ways = 4,
.line_size = 32,
.tlb_entries = UNDEF,
.partitioning = 0};
case 0x43:
return (CacheLevelInfo){.level = 2,
.cache_type = CPU_FEATURE_CACHE_DATA,
.cache_size = 512 * KiB,
.ways = 4,
.line_size = 32,
.tlb_entries = UNDEF,
.partitioning = 0};
case 0x44:
return (CacheLevelInfo){.level = 2,
.cache_type = CPU_FEATURE_CACHE_DATA,
.cache_size = 1 * MiB,
.ways = 4,
.line_size = 32,
.tlb_entries = UNDEF,
.partitioning = 0};
case 0x45:
return (CacheLevelInfo){.level = 2,
.cache_type = CPU_FEATURE_CACHE_DATA,
.cache_size = 2 * MiB,
.ways = 4,
.line_size = 32,
.tlb_entries = UNDEF,
.partitioning = 0};
case 0x46:
return (CacheLevelInfo){.level = 3,
.cache_type = CPU_FEATURE_CACHE_DATA,
.cache_size = 4 * MiB,
.ways = 4,
.line_size = 64,
.tlb_entries = UNDEF,
.partitioning = 0};
case 0x47:
return (CacheLevelInfo){.level = 3,
.cache_type = CPU_FEATURE_CACHE_DATA,
.cache_size = 8 * MiB,
.ways = 8,
.line_size = 64,
.tlb_entries = UNDEF,
.partitioning = 0};
case 0x48:
return (CacheLevelInfo){.level = 2,
.cache_type = CPU_FEATURE_CACHE_DATA,
.cache_size = 3 * MiB,
.ways = 12,
.line_size = 64,
.tlb_entries = UNDEF,
.partitioning = 0};
case 0x49:
return (CacheLevelInfo){.level = 2,
.cache_type = CPU_FEATURE_CACHE_DATA,
.cache_size = 4 * MiB,
.ways = 16,
.line_size = 64,
.tlb_entries = UNDEF,
.partitioning = 0};
case (0x49 | (1 << 8)):
return (CacheLevelInfo){.level = 3,
.cache_type = CPU_FEATURE_CACHE_DATA,
.cache_size = 4 * MiB,
.ways = 16,
.line_size = 64,
.tlb_entries = UNDEF,
.partitioning = 0};
case 0x4A:
return (CacheLevelInfo){.level = 3,
.cache_type = CPU_FEATURE_CACHE_DATA,
.cache_size = 6 * MiB,
.ways = 12,
.line_size = 64,
.tlb_entries = UNDEF,
.partitioning = 0};
case 0x4B:
return (CacheLevelInfo){.level = 3,
.cache_type = CPU_FEATURE_CACHE_DATA,
.cache_size = 8 * MiB,
.ways = 16,
.line_size = 64,
.tlb_entries = UNDEF,
.partitioning = 0};
case 0x4C:
return (CacheLevelInfo){.level = 3,
.cache_type = CPU_FEATURE_CACHE_DATA,
.cache_size = 12 * MiB,
.ways = 12,
.line_size = 64,
.tlb_entries = UNDEF,
.partitioning = 0};
case 0x4D:
return (CacheLevelInfo){.level = 3,
.cache_type = CPU_FEATURE_CACHE_DATA,
.cache_size = 16 * MiB,
.ways = 16,
.line_size = 64,
.tlb_entries = UNDEF,
.partitioning = 0};
case 0x4E:
return (CacheLevelInfo){.level = 2,
.cache_type = CPU_FEATURE_CACHE_DATA,
.cache_size = 6 * MiB,
.ways = 24,
.line_size = 64,
.tlb_entries = UNDEF,
.partitioning = 0};
case 0x4F:
return (CacheLevelInfo){.level = UNDEF,
.cache_type = CPU_FEATURE_CACHE_TLB,
.cache_size = 4 * KiB,
.ways = UNDEF,
.line_size = UNDEF,
.tlb_entries = 32,
.partitioning = 0};
case 0x50:
return (CacheLevelInfo){.level = UNDEF,
.cache_type = CPU_FEATURE_CACHE_TLB,
.cache_size = 4 * KiB,
.ways = UNDEF,
.line_size = UNDEF,
.tlb_entries = 64,
.partitioning = 0};
case 0x51:
return (CacheLevelInfo){.level = UNDEF,
.cache_type = CPU_FEATURE_CACHE_TLB,
.cache_size = 4 * KiB,
.ways = UNDEF,
.line_size = UNDEF,
.tlb_entries = 128,
.partitioning = 0};
case 0x52:
return (CacheLevelInfo){.level = UNDEF,
.cache_type = CPU_FEATURE_CACHE_TLB,
.cache_size = 4 * KiB,
.ways = UNDEF,
.line_size = UNDEF,
.tlb_entries = 256,
.partitioning = 0};
case 0x55:
return (CacheLevelInfo){.level = UNDEF,
.cache_type = CPU_FEATURE_CACHE_TLB,
.cache_size = 2 * MiB,
.ways = 0xFF,
.line_size = UNDEF,
.tlb_entries = 7,
.partitioning = 0};
case 0x56:
return (CacheLevelInfo){.level = UNDEF,
.cache_type = CPU_FEATURE_CACHE_TLB,
.cache_size = 4 * MiB,
.ways = 4,
.line_size = UNDEF,
.tlb_entries = 16,
.partitioning = 0};
case 0x57:
return (CacheLevelInfo){.level = UNDEF,
.cache_type = CPU_FEATURE_CACHE_TLB,
.cache_size = 4 * KiB,
.ways = 4,
.line_size = UNDEF,
.tlb_entries = 16,
.partitioning = 0};
case 0x59:
return (CacheLevelInfo){.level = UNDEF,
.cache_type = CPU_FEATURE_CACHE_TLB,
.cache_size = 4 * KiB,
.ways = 0xFF,
.line_size = UNDEF,
.tlb_entries = 16,
.partitioning = 0};
case 0x5A:
return (CacheLevelInfo){.level = UNDEF,
.cache_type = CPU_FEATURE_CACHE_TLB,
.cache_size = 2 * MiB,
.ways = 4,
.line_size = UNDEF,
.tlb_entries = 32,
.partitioning = 0};
case 0x5B:
return (CacheLevelInfo){.level = UNDEF,
.cache_type = CPU_FEATURE_CACHE_TLB,
.cache_size = 4 * KiB,
.ways = UNDEF,
.line_size = UNDEF,
.tlb_entries = 64,
.partitioning = 0};
case 0x5C:
return (CacheLevelInfo){.level = UNDEF,
.cache_type = CPU_FEATURE_CACHE_TLB,
.cache_size = 4 * KiB,
.ways = UNDEF,