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iOS armv7 加载静态库直接crash,arm64正常(版本GmSSL 2.0 - OpenSSL 1.1.0d 26 Jan 2017) #367
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你好 我想请问一下GmSSL如何编译armv7和arm64的静态库?谢谢 |
@bossbei 感谢 我会再去多做一下尝试的 |
@bossbei 您好,我还是想请教一下关于静态库的编译问题,我参照http://blog.cocoachina.com/article/38141 尝试了很多次依然无法成功编译,原因在于无法找到文中说的makefilem文件,而我修改Makefile文件又不对。因为对shell完全没有经验,所以您提供的后一种方法也不是很明白。不知可否再请教您一下 |
@timgeo4ever 先要运行 ./Configure ios64-cross 生成相应平台的makefile,./Configure --help可以看到支持的平台 |
@bossbei 竟然是这样的啊 我再去试试 太感谢您了! |
@bossbei 您好 我在修改完CC= /Applications/XCode.app/Contents/Developer/Toolchains/XcodeDefault.xctoolchain/usr/bin/clang -arch arm64 是因为我使用的XCode是9.1的11.1SDK的缘故吗 |
@timgeo4ever 你可以看看log,看看具体错误的原因 |
@bossbei 日志里有这么几句: 明确标记在这里不可用 |
@bossbei 百度了一下果然是iOS 11移除了system方法 |
@timgeo4ever 你找到那个文件注释了就好了,那是测试,不打紧 |
@bossbei 在您的帮助下终于编译成功了,十分感谢!另:您的armv7静态库运行依然有崩溃吗 |
@bossbei 又有一个问题需要麻烦您了。。再次编译时报了这个错 |
@bossbei 啊 这个自己把share文件夹删掉就解决了。。不麻烦您啦 谢谢! |
@bossbei 想问一下您现在armv7能正常工作吗 |
@bossbei @timgeo4ever 想请教下两位,编译arm64的时候下面的错误: |
@lixiayi 请教你的问题解决了吗,我编译也是报这个错误 |
@lixiayi 同样遇到,请问解决了没有呢 |
@ljx09195117 @lixiayi 修改crypto/aes/aes_core.c 632行的int bits为const unsigned int bits就可以了。然后问题来了编译好怎么用这两个库。。。。http://blog.cocoachina.com/article/38141按照这里报 SM2_CIPHERTEXT_VALUE未定义 |
@ljx09195117 @mixuan 没有,请问你们解决了吗 |
你好,提示找不到SM2_CIPHERTEXT_VALUE的?有没有小伙伴遇到这个问题? |
Marked as stale issue. Will be closed later if no activity for a while. |
dyld`_dyld_start:
0x36f000 <+0>: mov r8, sp
0x36f004 <+4>: sub sp, sp, #16
0x36f008 <+8>: bic sp, sp, #15
0x36f00c <+12>: ldr r3, [pc, #0x70] ; <+132>
0x36f010 <+16>: sub r0, pc, #8
0x36f014 <+20>: ldr r3, [r0, r3]
0x36f018 <+24>: sub r3, r0, r3
0x36f01c <+28>: ldr r0, [r8]
0x36f020 <+32>: ldr r1, [r8, #0x4]
0x36f024 <+36>: add r2, r8, #8
0x36f028 <+40>: ldr r4, [pc, #0x58] ; <+136>
0x36f02c <+44>: add r4, r4, pc
0x36f030 <+48>: str r4, [sp]
0x36f034 <+52>: add r4, sp, #12
0x36f038 <+56>: str r4, [sp, #0x4]
0x36f03c <+60>: blx 0x36f08c ; dyldbootstrap::start(macho_header const*, int, char const**, long, macho_header const*, unsigned long*)
0x36f040 <+64>: ldr r5, [sp, #0xc]
0x36f044 <+68>: cmp r5, #0
0x36f048 <+72>: bne 0x36f054 ; <+84>
0x36f04c <+76>: add sp, r8, #4
0x36f050 <+80>: bx r0
0x36f054 <+84>: mov lr, r5
0x36f058 <+88>: mov r5, r0
0x36f05c <+92>: ldr r0, [r8, #0x4]
0x36f060 <+96>: add r1, r8, #8
0x36f064 <+100>: add r2, r1, r0, lsl #2
0x36f068 <+104>: add r2, r2, #4
0x36f06c <+108>: mov r3, r2
0x36f070 <+112>: ldr r4, [r3]
0x36f074 <+116>: add r3, r3, #4
0x36f078 <+120>: cmp r4, #0
0x36f07c <+124>: bne 0x36f070 ; <+112>
0x36f080 <+128>: bx r5
0x36f084 <+132>: andeq r12, r2, r0, lsr #19
0x36f088 <+136>: .long 0xffffefcc ; unknown opcode
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