From a9ff6d7deba9466e84de4da34e60a24acc337dee Mon Sep 17 00:00:00 2001 From: Gyorgy Szombathelyi Date: Fri, 15 Feb 2019 20:57:00 +0100 Subject: [PATCH] Adjust cache controller for the changed SDRAM controller --- src/TwoWayCache.v | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/TwoWayCache.v b/src/TwoWayCache.v index 06e9635..e61e7b8 100644 --- a/src/TwoWayCache.v +++ b/src/TwoWayCache.v @@ -333,7 +333,7 @@ begin begin sdram_req<=1'b0; data_to_cpu <= data_from_sdram; - cpu_ack<=1'b1; // Too soon? + //cpu_ack<=1'b1; // Too soon? // write first word to Cache... data_ports_w<={2'b11,data_from_sdram}; @@ -345,7 +345,7 @@ begin FILL2: begin - //cpu_ack<=cpu_req; // Maintain ack signal if necessary + cpu_ack<=1'b1; // Maintain ack signal if necessary // write second word to Cache... readword_burst<=1'b1; readword<=readword+1'b1; @@ -357,7 +357,7 @@ begin FILL3: begin - //cpu_ack<=cpu_req; // Maintain ack signal if necessary + //cpu_ack<=1'b1; // Maintain ack signal if necessary // write third word to Cache... readword_burst<=1'b1; readword<=readword+1'b1; @@ -382,8 +382,8 @@ begin begin //cpu_ack <= 1'b1; readword<=cpu_addr[2:1]; -// state<=WAITING; - state<=PAUSE1; // Allow one extra clock after clearing readword_burst + state<=WAITING; +// state<=PAUSE1; // Allow one extra clock after clearing readword_burst end default: