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<!DOCTYPE html>
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<head>
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<title>Projects - Hanbin Hu</title>
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<h2>Hanbin Hu's Homepage</h2>
</div>
<nav class="navbar navbar-inverse">
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<div id="navbar" class="collapse navbar-collapse">
<ul class="nav navbar-nav">
<li><a href="index.html"><span class="glyphicon glyphicon-home"></span> Home</a></li>
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<h3 style="margin-bottom:20px; margin-top:10px"><strong>Selected Projects</strong></h3>
<div class="row">
<div class="col-xs-8 thumbnail">
<ul style="margin-top:10px">
<li>
<a href="#Corporation">Corporation Projects</a>
<ul class="nestul">
<li><a href="#corp1">HSPICE Parser Refactoring & Test Database Creation (Synopsys)</a></li>
<li><a href="#corp3">SPICE Model of Polyswitch Device (TE Connectivity)</a></li>
</ul>
</li>
<li>
<a href="#Course">Course Projects</a>
<ul class="nestul">
<li><a href="#cor1">GUI Development for Kalman Filter & Data Fusion</a></li>
<li><a href="#cor2">Power Analysis for Switching Strategies in SAR ADC Design</a></li>
<!--<li><a href="#cor3">Implementation and Observation of EKV 2.6 Model</a></li>-->
<li><a href="#cor4">A Low Voltage Low Power Sigma Delta Modulator Design</a></li>
<!--<li><a href="#cor5">A Narrow-Band LNA Design</a></li>-->
<!--<li><a href="#cor6">A Light-Weighted SPICE Simulator Design</a></li>-->
<li><a href="#cor7">A Processor Design using MIPS Instruction Set with Verilog</a></li>
</ul>
</li>
</ul>
</div>
</div>
<h4 id="Corporation"><strong><font color="#1E78B8"><font size="5">C</font>orporation <font size="5">P</font>rojects</font></strong></h4>
<hr/>
<div class="container content-right-padding">
<div class="row project-title" id="corp1">
<div class="col-xs-6"><strong><font size="3">HSPICE Parser Refactoring & Test Database Creation</font></strong></div>
<div class="col-xs-6 date"><i>July 2014 - September 2014 & July 2015 - September 2015</i></div>
<div class="col-xs-12"><strong>Field:</strong> SPICE Development, Software Refactoring, Regression Test</div>
</div>
<p>Corporation Name: <strong>Synopsys, Inc.</strong> Shanghai Site. (Summer Internship)</p>
<p>
<div class="row">
<div class="col-xs-7">Mentor: Mrs. Guoyu Yang and Mr. Yifei Huang, <a href="http://www.synopsys.com/home.aspx" target="_blank">Synopsys, Inc.</a> (2015)</div>
<div class="col-xs-5">Manager: Mrs.Liping Zhu, <a href="http://www.synopsys.com/home.aspx" target="_blank">Synopsys, Inc.</a> (2015)</div>
</div>
<div class="row">
<div class="col-xs-7">Mentor: Mr. Lianpeng Sang, <a href="http://www.synopsys.com/home.aspx" target="_blank">Synopsys, Inc.</a> (2014)</div>
<div class="col-xs-5">Manager: Mr. Deng Shi, <a href="http://www.synopsys.com/home.aspx" target="_blank">Synopsys, Inc.</a> (2014)</div>
</div>
</p>
<p>
Goal: HSPICE is one of the flagship products at Synopsys. This project in 2015 was to refactor parser codes for three input commands (.set_sample_time, .dout, and .store) in HSPICE from Fortran to C++.
This work was awarded as <strong>one of the best internship projects</strong> at Synopsys, China in 2015.
I was invited to be present the project on Synopsys R&D Demo Day.
This project in 2014 was to gather feature information from the quality assurance (QA) system to accelerate the test procedure by providing problem-specific test cases in every regression test.
[<a href="data/report/2015_Summer_Intern_Synopsys.pdf" , target="_blank">Slides 2015</a>] [<a href="data/report/2014_Summer_Intern_Synopsys.pdf" , target="_blank">Slides 2014</a>]
</p>
<ul>
<li>Refactored 3 commond input routines in HSPICE from Fortran to C++.</li>
<li>Proposed the design methodology for future parser refactoring work and related software architecture.</li>
<li>Reconstructed the simulation engine for transfer function simulation.</li>
<li>Built a Perl script to gather information for database construction from 20,586 test netlists in the quality assurance (QA) system.</li>
<li>Detected and fixed 11 bugs in HSPICE and HSP_PACK2GO, including several command malfunctions, file path problems, etc.</li>
</ul>
<div class="row">
<div class="col-xs-6" style="text-align:center; color:darkgrey"><img src="image/Snps15_PT.png" class="imgBorder imgPadding" alt="Synopsys 2015" /><p>HSPICE top-level procedure for parser.</p></div>
<div class="col-xs-6" style="text-align:center; color:darkgrey"><img src="image/Snps14_PT.png" class="imgBorder imgPadding" alt="Synopsys 2015" /><p>Photo taken with my mentor.</p></div>
</div>
<!--<div class="row project-title" id="corp1">
<div class="col-xs-9"><strong><font size="3">HSPICE Parser Data Structure Refactoring with C++</font></strong></div>
<div class="col-xs-3 date"><i>July 2015 - September 2015</i></div>
</div>
<p>Corporation Name: <strong>Synopsys, Inc.</strong> Shanghai Site. (Summer Internship)</p>
<div class="row">
<div class="col-xs-6"><p>Mentor: Mrs. Guoyu Yang and Mr. Yifei Huang, <a href="http://www.synopsys.com/home.aspx" target="_blank">Synopsys, Inc.</a></p></div>
<div class="col-xs-6"><p>Manager: Mrs.Liping Zhu, <a href="http://www.synopsys.com/home.aspx" target="_blank">Synopsys, Inc.</a></p></div>
</div>
<p>
Goal: HSPICE is one of the flagship products at Synopsys; however, there still remain a large amount of Fortran codes in its latest release of HSPICE wich increases maintenance difficulty and extra development cost.
This project was to refactor parser codes for three input commands (.set_sample_time, .dout, and .store) in HSPICE from Fortran to C++.
This work was awarded as <strong>one of the best internship projects</strong> at Synopsys, China in 2015.
I was invited to be present the project on Synopsys R&D Demo Day.
[<a href="data/report/2015_Summer_Intern_Synopsys.pdf", target="_blank">Slides</a>]
</p>
<ul>
<li>Refactored 3 commond input routines in HSPICE from Fortran to C++.</li>
<li>Proposed the design methodology for future parser refactoring work and related software architecture.</li>
<li>Provided several common interfaces like token processing and expression evaluation for reference.</li>
<li>Reconstructed the simulation engine for transfer function simulation.</li>
<li>Passed all regression tests with 8,993 test cases according to the QA report.</li>
<li>Detected and fixed 6 bugs in HSPICE, including two command malfunctions, one manual inconformity and three format problems.</li>
</ul>
<div class="row">
<div class="col-xs-offset-1 col-xs-6" style="text-align:center; color:darkgrey"><img src="image/Snps15_PT.png" class="imgBorder imgPadding" alt="Synopsys 2015" /><p>HSPICE top-level procedure for parser.</p></div>
<div class="col-xs-4" style="text-align:center; color:darkgrey"><img src="image/Snps15_Photo.png" class="imgBorder imgPadding" alt="Synopsys 2015" /><p>Photo taken with my mentor.</p></div>
</div>
<div class="row project-title" id="corp2">
<div class="col-xs-9"><strong><font size="3">HSPICE Test Case Database Creation</font></strong></div>
<div class="col-xs-3 date"><i>July 2014 - September 2014</i></div>
</div>
<p>Corporation Name: <strong>Synopsys, Inc.</strong> Shanghai Site. (Summer Internship)</p>
<div class="row">
<div class="col-xs-6"><p>Mentor: Mr. Lianpeng Sang, <a href="http://www.synopsys.com/home.aspx" target="_blank">Synopsys, Inc.</a></p></div>
<div class="col-xs-6"><p>Manager: Mr. Deng Shi, <a href="http://www.synopsys.com/home.aspx" target="_blank">Synopsys, Inc.</a></p></div>
</div>
<p>
Goal: Gather feature information from 20,000+ test cases in the quality assurance (QA) system to accelerate the test procedure by providing problem-specific test cases in every regression test.
[<a href="data/report/2014_Summer_Intern_Synopsys.pdf", target="_blank">Slides</a>]
</p>
<ul>
<li>Built a Perl script to gather netlist information for database construction from 20,586 test cases in the quality assurance (QA) system.</li>
<li>Analyzed 674 test cases to recognize corresponding circuit types by manual analysis.</li>
<li>Detected 5 bugs in HSPICE and HSP_PACK2GO about file paths.</li>
</ul>
<div class="row">
<div class="col-xs-6" style="text-align:center; color:darkgrey"><img src="image/Snps14_PT.png" class="imgBorder imgPadding" alt="Synopsys 2014" /><p>Required database structure.</p></div>
<div class="col-xs-6" style="text-align:center; color:darkgrey"><img src="image/Snps14_Photo.png" class="imgBorder imgPadding" alt="Synopsys 2014" /><p>Photo taken at defense.</p></div>
</div>-->
<div class="row project-title" id="corp3">
<div class="col-xs-8"><strong><font size="3">SPICE Model of Polyswitch Device</font></strong></div>
<div class="col-xs-4 date"><i>November 2014 - March 2015</i></div>
<div class="col-xs-12"><strong>Field:</strong> Device Modeling</div>
</div>
<p>Corporation Name: <strong>TE Connectivity Ltd.</strong> (College-Industry Cooperation)</p>
<p>Advisor: <a href="http://ic.sjtu.edu.cn/ic/en/faculty/shiguoyong/" target="_blank">Prof. Guoyong Shi</a> & <a href="http://ic.sjtu.edu.cn/ic/en/faculty/wangqin/" target="_blank">Prof. Qin Wang</a>, <a href="http://en.sjtu.edu.cn/" target="_blank">Shanghai Jiao Tong University</a></p>
<p>Mentor: Mr. Taichu Dai & Mr. Hongye Xia, <a href="http://www.te.com/usa-en/home.html" target="_blank">TE Connectivity Ltd.</a></p>
<p>
Goal: Build a SPICE model for Polymer Positive Temperature Coefficient (PPTC) resistor
considering current limit and time to trip variation with temperature for PSPICE simulation.
[<a href="data/report/2014_PPTC_TE_Connectivity.pdf" target="_blank">PDF</a>]
</p>
<ul>
<li>Designed a macro model for a PPTC device by taking into account three factors: temperature, current and time.</li>
<li>Proposed parameter extraction methods to obtain model data for a specific device.</li>
<li>Experimented the proposed model in both transient and temperature sweep simulation.</li>
</ul>
<div class="row">
<div class="col-xs-7" style="text-align:center; color:darkgrey"><img src="image/TE_BG.png" class="imgBorder" style="height:300px" alt="TE Connectivity 2014" /><p>Fundamental principle of PPTC.</p></div>
<div class="col-xs-5" style="text-align:center; color:darkgrey"><img src="image/TE_Circuit.png" class="imgBorder" style="height:300px" alt="TE Connectivity 2014" /><p>Proposed behavior model for PPTC.</p></div>
</div>
</div>
<h4 id="Course"><strong><font color="#1E78B8"><font size="5">C</font>ourse <font size="5">P</font>rojects</font></strong></h4>
<hr/>
<div class="container content-right-padding">
<div class="row project-title" id="cor1">
<div class="col-xs-9"><strong><font size="3">GUI Development for Kalman Filter & Data Fusion</font></strong></div>
<div class="col-xs-3 date"><i>May 2014 - June 2014</i></div>
<div class="col-xs-12"><strong>Field:</strong> Signal Processing, Parameter Estimation</div>
</div>
<div class="row">
<div class="col-xs-8"><p>Course: Optimal Estimation and System Modeling (Master)</p></div>
<div class="col-xs-4"><p>Lecturer: <a href="http://www.math.sjtu.edu.cn/Showteacher.aspx?id=13&info_lb=98&flag=98" target="_blank">Prof. Xiaomin Wang</a></p></div>
</div>
<div class="row">
<div class="col-xs-6">
<p>Goal: The Kalman filter and multisensor data fusion play a significant role in parameter estimation in engineering.
This project was to develop a vivid and interactive Graphical User Interface (GUI) for engineers to observe the experimental results of Kalman filter and the effect of data fusion for multiple sensors.
[<a href="data/report/GUI_Kalman_Filter.pdf" target="_blank">PDF</a>] (Chinese Version)
</p>
<ul>
<li>Developed a MATLAB GUI for parameter estimation.</li>
<li>Realized the Kalman filter algorithm and data fusion algorithm for multiple sensors with different weighting methods.</li>
<li>Provided functions for system's controllability and observability verification.</li>
<li>Checked the validity of all input data for software robustness.</li>
</ul>
</div>
<div class="col-xs-6" style="text-align:center; color:darkgrey"><img src="image/Kalman_GUI.png" class="imgBorder imgPadding" alt="Kalman" /><p>GUI for Kalman filter & data fusion.</p></div>
</div>
<div class="row">
<div class="col-xs-offset-2 col-xs-8" style="text-align:center; color:darkgrey"><img src="image/IF.png" class="imgBorder imgPadding" alt="Kalman" /><p>Data fusion results.</p></div>
</div>
<div class="row project-title" id="cor2">
<div class="col-xs-8"><strong><font size="3">Power Analysis for Switching Strategies in SAR ADC Design</font></strong></div>
<div class="col-xs-4 date"><i>January 2014</i></div>
<div class="col-xs-12"><strong>Field:</strong> Power Analysis, Mixed-Signal Circuit</div>
</div>
<div class="row">
<div class="col-xs-8"><p>Course: Circuit Design for Biomedical Implants (Master)</p></div>
<div class="col-xs-4"><p>Lecturer: <a href="http://ic.sjtu.edu.cn/bicasl/_Wang%20guoxing_en.html" target="_blank">Prof. Guoxing Wang</a></p></div>
</div>
<p>Goal: Due to the straightforward mechanism, low power consumption, and fairly fast sampling rate, Successive Approximation Register (SAR) ADC has become one of the most popular ADC research topics in recent years.
This project was to figure out the power consumption difference for three types of switching sequences in DAC: common voltage down switching sequence, common voltage back switching sequence, and common voltage fixed switching sequence.
[<a href="data/report/SAR_ADC_Switching.pdf" target="_blank">PDF</a>] (Chinese Version)
</p>
<ul>
<li>Built an analytic model for SAR ADC in C++ to simulate its sampling behavior.</li>
<li>Realized all the three switching sequences and the corresponding power conusmption model in C++ to estimate the power consumption of SAR ADC.</li>
</ul>
<div class="row">
<div class="col-xs-6" style="text-align:center; color:darkgrey"><img src="image/SARADC.png" class="imgBorder imgPadding" alt="SAR ADC" /><p>DAC structure for SAR ADC.</p></div>
<div class="col-xs-6" style="text-align:center; color:darkgrey"><img src="image/SARpower.png" class="imgBorder imgPadding" alt="SAR ADC" /><p>Power consumption comparison for different switching methods.</p></div>
</div>
<!--
<div class="row project-title" id="cor3">
<div class="col-xs-8"><strong><font size="3">Implementation and Observation of EKV 2.6 Model</font></strong></div>
<div class="col-xs-4 date"><i>September 2013 - January 2014</i></div>
</div>
<div class="row">
<div class="col-xs-8"><p>Course: Mixed-Signal Circuit Design and Automation Methods (Master)</p></div>
<div class="col-xs-4"><p>Lecturer: <a href="http://ic.sjtu.edu.cn/ic/en/faculty/shiguoyong/" target="_blank">Prof. Guoyong Shi</a></p></div>
</div>
<p>Goal: Low-power low-voltage design is increasingly popular in analog circuit design in recent years.
EKV model and gm/ID methodology have been used to assist this type of design in the past 20 years.
This work illustrated the basic EKV model and explained several secondary effects considered in the EKV v2.6 model.
Furthermore, a CAD tool with GUI was implemented along with an engine that simulated the EKV 2.6 model to facilitate the g<sub>m</sub>/I<sub>D</sub> methodology.
[<a href="data/report/SPICE_report.pdf" target="_blank">PDF</a>]
</p>
<ul>
<li>Implemented a MOSFET device model with the EKV v2.6 model according to the official manual from <a href="http://ekv.epfl.ch/" target="_blank">EPFL</a>.</li>
<li>Developed an interactive GUI for easy interpretation of the MOSFET behavior, and provided the relative g<sub>m</sub>/I<sub>D</sub> curve for engineers to observe the inversion degree and cultivate a better sense of device data.</li>
</ul>
<div class="row">
<div class="col-xs-offset-2 col-xs-8" style="text-align:center; color:darkgrey"><img src="image/EKVGUI.png" class="imgBorder imgPadding" alt="EKV Model" /><p>GUI for EKV model simulation.</p></div>
</div>
-->
<div class="row project-title" id="cor4">
<div class="col-xs-9"><strong><font size="3">A Low Voltage Low Power Sigma Delta Modulator Design</font></strong></div>
<div class="col-xs-3 date"><i>July 2013</i></div>
<div class="col-xs-12"><strong>Field:</strong> Low Power Circuit Design, Analog & Mixed-Signal Circuit</div>
</div>
<div class="row">
<div class="col-xs-8"><p>Course: Advanced Topics on Analog Mixed-Mode Signal Circuit Design (Bachelor)</p></div>
<div class="col-xs-4"><p>Lecturer: <a href="http://www.mohamadsawan.org/" target="_blank">Prof. Mohamad Sawan</a></p></div>
</div>
<p>Goal: Bio-medical electronics have made great progress in the past decade.
Data converter plays an important role in the whole system, which stands for the bridge between analog and digital domain.
In this work, a discrete-time sigma-delta modulator was presented with low power consumption and sufficient resolution in purpose of ECG signal sampling for pacemaker application.
[<a href="data/report/SDM_report.pdf" target="_blank">PDF</a>]
</p>
<ul>
<li>Designed a bulk-driven fully differential operational amplifier, working under 1.0V power supply and 245nA current, with an open loop gain of 73dB and a GBW of 226.6kHz.</li>
<li>Built a first-order Sigma-Delta Modulator (SDM) with an OSR of 20 and an SNR of 22.5dB, integrated a low power track and latch comparator with 39nA current.</li>
</ul>
<div class="row">
<div class="col-xs-6" style="text-align:center; color:darkgrey"><img src="image/BDOTA.png" class="imgBorder imgPadding" style="height:275px" alt="Sigma-Delta ADC" /><p>Bulk-driven OTA design.</p></div>
<div class="col-xs-6" style="text-align:center; color:darkgrey"><img src="image/SDMPSD.png" class="imgBorder imgPadding" style="height:275px" alt="Sigma-Delta ADC" /><p>Power spectral density (PSD) for the system.</p></div>
</div>
<!--
<div class="row project-title" id="cor5">
<div class="col-xs-8"><strong><font size="3">A Narrow-Band LNA Design</font></strong></div>
<div class="col-xs-4 date"><i>September 2012 - November 2012</i></div>
</div>
<div class="row">
<div class="col-xs-8"><p>Course: Introduction to RF IC Design (Bachelor)</p></div>
<div class="col-xs-4"><p>Lecturer: <a href="http://ic.sjtu.edu.cn/ic/carfic/en/members/jianjun-zhou/" target="_blank">Prof. Jianjun Zhou</a></p></div>
</div>
<p>More information about this project will be <i><strong>coming soon</strong></i>.</p>
<div class="row project-title" id="cor6">
<div class="col-xs-8"><strong><font size="3">A Light-Weighted SPICE Simulator Design</font></strong></div>
<div class="col-xs-4 date"><i>February 2012 - May 2012</i></div>
</div>
<div class="row">
<div class="col-xs-8"><p>Course: Introduction to Design Automation (Bachelor)</p></div>
<div class="col-xs-4"><p>Lecturer: <a href="http://ic.sjtu.edu.cn/ic/en/faculty/shiguoyong/" target="_blank">Prof. Guoyong Shi</a></p></div>
</div>
<p>Goal:
SPICE is the acronym for Simulation Program with Integrated Circuit Emphasis, which is the most popular and reliable simulation program in analog and mixed-signal integrated circuit design.
This project was to implement a light-weighted SPICE for circuits including linear and nonlinear devices in different simulation configurations.
[<a href="data/report/SPICE_Report_2012.pdf" target="_blank">PDF</a>] (Chinese Version)
</p>
<ul>
<li>Developed a SPICE simulation engine to analyze a circuit netlist whose sub-circuits contain both linear devices such as resistors and capacitors as well as nonlinear devices such as MOSFETs.</li>
<li>Built a compiler processing circuit netlist that includes sub-circuits and device models using Flex/Bison.</li>
<li>Performed operational point analysis, transient analysis and small signal analysis of analog circuits with various numerical algorithms including Backward Euler and Newton-Rhapson Iteration.</li>
</ul>
<div class="row">
<div class="col-xs-6" style="text-align:center; color:darkgrey"><img src="image/Trans_Alg.png" class="imgBorder imgPadding" alt="SPICE" /><p>Transient simulation procedure.</p></div>
<div class="col-xs-6" style="text-align:center; color:darkgrey"><img src="image/Inv_Res.png" class="imgBorder imgPadding" alt="SPICE" /><p>Simulated CMOS inverter results.</p></div>
</div>
-->
<div class="row project-title" id="cor7">
<div class="col-xs-8"><strong><font size="3">A Processor Design using MIPS Instruction Set with Verilog</font></strong></div>
<div class="col-xs-4 date"><i>December 2011 - January 2012</i></div>
<div class="col-xs-12"><strong>Field:</strong> Computer Architecture, Verilog Design</div>
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<div class="col-xs-8"><p>Course: Computer Organization and Embedded System (Bachelor)</p></div>
<div class="col-xs-4"><p>Lecturer: <a href="http://ic.sjtu.edu.cn/ic/en/faculty/jiangjiang/" target="_blank">Prof. Jiang Jiang</a></p></div>
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<p>Goal: Build a processor using MIPS instruction set with a 5-stage pipeline architecture in Verilog considering branch prediction.
[<a href="data/report/MIPS_Report.pdf" target="_blank">PDF</a>] (Chinese Version)
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<li>Designed the top level architecture and assigned related works to group members.</li>
<li>Programmed the 'hazard detection', 'register', 'ALU', 'control', 'forwarding', 'sign extended' block in the system.</li>
<li>Provided the testbench and verified the whole system.</li>
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<img src="image/MIPS_Architecture.png" class="imgBorder imgPadding" alt="MIPS" /><p>MIPS Architecture.</p>
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<div class="col-xs-6" style="text-align:center; color:darkgrey"><img src="image/MIPS_Instruction.png" class="imgBorder imgPadding" style="height:480px" alt="MIPS" /><p>MIPS Instruction Set.</p></div>
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