-
Notifications
You must be signed in to change notification settings - Fork 0
/
bb_learn_rpt.html
606 lines (534 loc) · 30.2 KB
/
bb_learn_rpt.html
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
<HTML>
<HEAD><TITLE>HTML_REPORT_FILE</TITLE>
<STYLE TYPE="text/css">
<!--
.blink {text-decoration:blink}
.ms {font-size: 10pt; font-family: monospace; font-weight: normal}
.msb {font-size: 10pt; font-family: monospace; font-weight: bold }
-->
</STYLE>
</HEAD>
<PRE>
<A name="Top"></A><H2 align=center> ispLEVER Classic 2.0.00.17.20.15 Fitter Report File </H2>
<H2 align=center>Copyright(C), 1992-2012, Lattice Semiconductor Corporation</H2>
<H2 align=center>All Rights Reserved</H2>
The Basic/Detailed Report Format can be selected in the dialog box
Tools->Fitter Report File Format...
<A name="Project_Summary"></A><FONT COLOR=maroon><U><B><big>Project_Summary</big></B></U></FONT>
<BR>
Project Name : bb_learn
Project Path : C:\projects\ispMach-learn-verilog
Project Fitted on : Sun Jul 29 16:36:31 2018
Device : M4256_96
Package : 144
GLB Input Mux Size : 33
Available Blocks : 16
Speed : -5.8
Part Number : LC4256ZE-5TN144C
Source Format : Pure_Verilog_HDL
<font color=green size=4><span class=blink><strong><B>Project 'bb_learn' Fit Successfully!</B></strong></span></font>
<A name="Compilation_Times"></A><FONT COLOR=maroon><U><B><big>Compilation_Times</big></B></U></FONT>
<BR>
Prefit Time 0 secs
Load Design Time 0.05 secs
Partition Time 0.01 secs
Place Time 0.02 secs
Route Time 0.00 secs
Total Fit Time 00:00:01
<A name="Design_Summary"></A><FONT COLOR=maroon><U><B><big>Design_Summary</big></B></U></FONT>
<BR>
Total Input Pins 1
Total Logic Functions 16
Total Output Pins 8
Total Bidir I/O Pins 0
Total Buried Nodes 8
Total Flip-Flops 8
Total D Flip-Flops 8
Total T Flip-Flops 0
Total Latches 0
Total Product Terms 28
Total Reserved Pins 0
Total Locked Pins 9
Total Locked Nodes 2
Total Unique Output Enables 0
Total Unique Clocks 1
Total Unique Clock Enables 0
Total Unique Resets 1
Total Unique Presets 1
Fmax Logic Levels -
<A name="Device_Resource_Summary"></A><FONT COLOR=maroon><U><B><big>Device_Resource_Summary</big></B></U></FONT>
<BR>
<B> Device
Total Used Not Used Utilization
-----------------------------------------------------------------------
</B>Dedicated Pins
Clock/Input Pins 4 0 4 --> 0
Input-Only Pins 10 1 9 --> 10
I/O / Enable Pins 2 0 2 --> 0
I/O Pins 94 8 86 --> 8
Logic Functions 256 15 241 --> 5
Input Registers 96 0 96 --> 0
GLB Inputs 576 8 568 --> 1
Logical Product Terms 1280 12 1268 --> 0
Occupied GLBs 16 4 12 --> 25
Macrocells 256 14 242 --> 5
Control Product Terms:
GLB Clock/Clock Enables 16 1 15 --> 6
GLB Reset/Presets 16 0 16 --> 0
Macrocell Clocks 256 0 256 --> 0
Macrocell Clock Enables 256 0 256 --> 0
Macrocell Enables 256 0 256 --> 0
Macrocell Resets 256 0 256 --> 0
Macrocell Presets 256 0 256 --> 0
Global Routing Pool 356 6 350 --> 1
GRP from IFB .. 0 .. --> ..
(from input signals) .. 0 .. --> ..
(from output signals) .. 0 .. --> ..
(from bidir signals) .. 0 .. --> ..
GRP from MFB .. 6 .. --> ..
----------------------------------------------------------------------
<Note> 1 : The available PT is the product term that has not been used.
<Note> 2 : IFB is I/O feedback.
<Note> 3 : MFB is macrocell feedback.
<A name="GLB_Resource_Summary"></A><FONT COLOR=maroon><U><B><big>GLB_Resource_Summary</big></B></U></FONT>
<BR>
<B> # of PT
--- Fanin --- I/O Input Macrocells Macrocells Logic clusters
Unique Shared Total Pins Regs Used Inaccessible available PTs used
-------------------------------------------------------------------------------------------
Maximum
GLB 36 *(1) 8 -- -- 16 80 16
</B>-------------------------------------------------------------------------------------------
GLB A 0 0 0 0/6 0 0 0 16 0 0
GLB B 0 0 0 0/6 0 0 0 16 0 0
GLB C 0 0 0 0/6 0 1 0 15 0 1
GLB D 0 0 0 0/6 0 0 0 16 0 0
-------------------------------------------------------------------------------------------
GLB E 0 0 0 0/6 0 0 0 16 0 0
GLB F 0 0 0 0/6 0 1 0 15 0 1
GLB G 0 0 0 0/6 0 0 0 16 0 0
GLB H 0 0 0 0/6 0 0 0 16 0 0
-------------------------------------------------------------------------------------------
GLB I 0 6 6 6/6 0 10 0 6 10 10
GLB J 2 0 2 2/6 0 2 0 14 2 2
GLB K 0 0 0 0/6 0 0 0 16 0 0
GLB L 0 0 0 0/6 0 0 0 16 0 0
-------------------------------------------------------------------------------------------
GLB M 0 0 0 0/6 0 0 0 16 0 0
GLB N 0 0 0 0/6 0 0 0 16 0 0
GLB O 0 0 0 0/6 0 0 0 16 0 0
GLB P 0 0 0 0/6 0 0 0 16 0 0
-------------------------------------------------------------------------------------------
TOTALS: 2 6 8 8/96 0 14 0 242 12 14
<Note> 1 : For ispMACH 4000 devices, the number of IOs depends on the GLB.
<Note> 2 : Four rightmost columns above reflect last status of the placement process.
<A name="GLB_Control_Summary"></A><FONT COLOR=maroon><U><B><big>GLB_Control_Summary</big></B></U></FONT>
<BR>
<B> Shared Shared | Mcell Mcell Mcell Mcell Mcell
Clk/CE Rst/Pr | Clock CE Enable Reset Preset
------------------------------------------------------------------------------
Maximum
GLB 1 1 16 16 16 16 16
==============================================================================
</B> GLB A 0 0 0 0 0 0 0
GLB B 0 0 0 0 0 0 0
GLB C 0 0 0 0 0 0 0
GLB D 0 0 0 0 0 0 0
------------------------------------------------------------------------------
GLB E 0 0 0 0 0 0 0
GLB F 0 0 0 0 0 0 0
GLB G 0 0 0 0 0 0 0
GLB H 0 0 0 0 0 0 0
------------------------------------------------------------------------------
GLB I 1 0 0 0 0 0 0
GLB J 0 0 0 0 0 0 0
GLB K 0 0 0 0 0 0 0
GLB L 0 0 0 0 0 0 0
------------------------------------------------------------------------------
GLB M 0 0 0 0 0 0 0
GLB N 0 0 0 0 0 0 0
GLB O 0 0 0 0 0 0 0
GLB P 0 0 0 0 0 0 0
------------------------------------------------------------------------------
<Note> 1 : For ispMACH 4000 devices, the number of output enables depends on the GLB.
<A name="Optimizer_and_Fitter_Options"></A><FONT COLOR=maroon><U><B><big>Optimizer_and_Fitter_Options</big></B></U></FONT>
<BR>
Pin Assignment : Yes
Group Assignment : No
Pin Reservation : No
@Ignore_Project_Constraints :
Pin Assignments : No
Keep Block Assignment --
Keep Segment Assignment --
Group Assignments : No
Macrocell Assignment : No
Keep Block Assignment --
Keep Segment Assignment --
@Backannotate_Project_Constraints
Pin Assignments : No
Pin And Block Assignments : No
Pin, Macrocell and Block : No
@Timing_Constraints : No
@Global_Project_Optimization :
Balanced Partitioning : Yes
Spread Placement : Yes
Note :
Pack Design :
Balanced Partitioning = No
Spread Placement = No
Spread Design :
Balanced Partitioning = Yes
Spread Placement = Yes
@Logic_Synthesis :
Logic Reduction : Yes
Node Collapsing : FMAX
Fmax_Logic_Level : 1
D/T Synthesis : Yes
XOR Synthesis : Yes
Max. P-Term for Collapsing : 16
Max. P-Term for Splitting : 80
Max Symbols : 24
@Utilization_options
Max. % of Macrocells used : 100
@Usercode (HEX)
@IO_Types Default = LVCMOS18 (2)
@Output_Slew_Rate Default = FAST (2)
@Power Default = HIGH (2)
@Pull Default = PULLUP_DOWN (2)
@Input_Registers Default = None (2)
@Register_Powerup Default = None
Device Options:
<Note> 1 : Reserved unused I/Os can be independently driven to Low or High, and does not
follow the drive level set for the Global Configure Unused I/O Option.
<Note> 2 : For user-specified constraints on individual signals, refer to the Output,
Bidir and Buried Signal Lists.
<A name="OSCTIMER_Summary"></A><FONT COLOR=maroon><U><B><big>OSCTIMER_Summary</big></B></U></FONT>
<BR>
OSCTIMER: Pin/Node
OSCTIMER Instance Name I1
Dynamic Disable Signal gnd_n_n
Timer Reset Signal _dup_gnd_n_n
Oscillator Output Clock mfb C-15 A0_OSCOUT
Timer Output Clock mfb F-15 clk
Oscillator Output Clock Frequency 5.0000 MHz
Timer Output Clock Frequency 4.7684 Hz
Timer Divider 1048576
<A name="Pinout_Listing"></A><FONT COLOR=maroon><U><B><big>Pinout_Listing</big></B></U></FONT>
<BR>
<B> | Pin | Bank |GLB |Assigned| | Signal| | PG
Pin No| Type |Number|Pad |Pin | I/O Type | Type | Signal name| Enable
</B>-----------------------------------------------------------------------------------
1 | GND | - | | | | | |
2 | TDI | - | | | | | |
3 |VCCIO0 | - | | | | | |
4 | I_O | 0 |C12 | | | | |
5 | I_O | 0 |C10 | | | | |
6 | I_O | 0 |C8 | | | | |
7 | I_O | 0 |C6 | | | | |
8 | I_O | 0 |C4 | | | | |
9 | I_O | 0 |C2 | | | | |
10 |GNDIO0 | - | | | | | |
11 | I_O | 0 |D14 | | | | |
12 | I_O | 0 |D12 | | | | |
13 | I_O | 0 |D10 | | | | |
14 | I_O | 0 |D8 | | | | |
15 | I_O | 0 |D6 | | | | |
16 | I_O | 0 |D4 | | | | |
17 | IN0 | 0 | | | | | |
18 | NC | - | | | | | |
19 |VCCIO0 | - | | | | | |
20 | IN1 | 0 | | | | | |
21 | I_O | 0 |E2 | | | | |
22 | I_O | 0 |E4 | | | | |
23 | I_O | 0 |E6 | | | | |
24 | I_O | 0 |E8 | | | | |
25 | I_O | 0 |E10 | | | | |
26 | I_O | 0 |E12 | | | | |
27 |GNDIO0 | - | | | | | |
28 | I_O | 0 |F2 | | | | |
29 | I_O | 0 |F4 | | | | |
30 | I_O | 0 |F6 | | | | |
31 | I_O | 0 |F8 | | | | |
32 | I_O | 0 |F10 | | | | |
33 | I_O | 0 |F12 | | | | |
34 |VCCIO0 | - | | | | | |
35 | TCK | - | | | | | |
36 | VCC | - | | | | | |
37 | GND | - | | | | | |
38 | IN2 | 0 | | | | | |
39 | I_O | 0 |G12 | | | | |
40 | I_O | 0 |G10 | | | | |
41 | I_O | 0 |G8 | | | | |
42 | I_O | 0 |G6 | | | | |
43 | I_O | 0 |G4 | | | | |
44 | I_O | 0 |G2 | | | | |
45 | IN3 | 0 | | | | | |
46 |GNDIO0 | - | | | | | |
47 |VCCIO0 | - | | | | | |
48 | I_O | 0 |H12 | | | | |
49 | I_O | 0 |H10 | | | | |
50 | I_O | 0 |H8 | | | | |
51 | I_O | 0 |H6 | | | | |
52 | I_O | 0 |H4 | | | | |
53 | I_O | 0 |H2 | | | | |
54 |INCLK1 | 0 | | | | | |
55 |GNDIO1 | - | | | | | |
56 |INCLK2 | 1 | | | | | |
57 | VCC | - | | | | | |
58 | I_O | 1 |I2 | * |LVCMOS33 | Output|<A href=#6>nled_7_</A>|
59 | I_O | 1 |I4 | * |LVCMOS33 | Output|<A href=#8>nled_6_</A>|
60 | I_O | 1 |I6 | * |LVCMOS33 | Output|<A href=#9>nled_5_</A>|
61 | I_O | 1 |I8 | * |LVCMOS33 | Output|<A href=#10>nled_4_</A>|
62 | I_O | 1 |I10 | * |LVCMOS33 | Output|<A href=#11>nled_3_</A>|
63 | I_O | 1 |I12 | * |LVCMOS33 | Output|<A href=#12>nled_2_</A>|
64 |VCCIO1 | - | | | | | |
65 |GNDIO1 | - | | | | | |
66 | I_O | 1 |J2 | | | | |
67 | I_O | 1 |J4 | | | | |
68 | I_O | 1 |J6 | | | | |
69 | I_O | 1 |J8 | | | | |
70 | I_O | 1 |J10 | * |LVCMOS33 | Output|<A href=#13>nled_1_</A>|
71 | I_O | 1 |J12 | * |LVCMOS33 | Output|<A href=#14>nled_0_</A>|
72 | IN4 | 0 | | * |LVCMOS33 | Input |<A href=#7>nrst</A>|
73 | GND | - | | | | | |
74 | TMS | - | | | | | |
75 |VCCIO1 | - | | | | | |
76 | I_O | 1 |K12 | | | | |
77 | I_O | 1 |K10 | | | | |
78 | I_O | 1 |K8 | | | | |
79 | I_O | 1 |K6 | | | | |
80 | I_O | 1 |K4 | | | | |
81 | I_O | 1 |K2 | | | | |
82 |GNDIO1 | - | | | | | |
83 | I_O | 1 |L14 | | | | |
84 | I_O | 1 |L12 | | | | |
85 | I_O | 1 |L10 | | | | |
86 | I_O | 1 |L8 | | | | |
87 | I_O | 1 |L6 | | | | |
88 | I_O | 1 |L4 | | | | |
89 | IN5 | 1 | | | | | |
90 | NC | - | | | | | |
91 |VCCIO1 | - | | | | | |
92 | IN6 | 1 | | | | | |
93 | I_O | 1 |M2 | | | | |
94 | I_O | 1 |M4 | | | | |
95 | I_O | 1 |M6 | | | | |
96 | I_O | 1 |M8 | | | | |
97 | I_O | 1 |M10 | | | | |
98 | I_O | 1 |M12 | | | | |
99 |GNDIO1 | - | | | | | |
100 | I_O | 1 |N2 | | | | |
101 | I_O | 1 |N4 | | | | |
102 | I_O | 1 |N6 | | | | |
103 | I_O | 1 |N8 | | | | |
104 | I_O | 1 |N10 | | | | |
105 | I_O | 1 |N12 | | | | |
106 |VCCIO1 | - | | | | | |
107 | TDO | - | | | | | |
108 | VCC | - | | | | | |
109 | GND | - | | | | | |
110 | IN7 | 1 | | | | | |
111 | I_O | 1 |O12 | | | | |
112 | I_O | 1 |O10 | | | | |
113 | I_O | 1 |O8 | | | | |
114 | I_O | 1 |O6 | | | | |
115 | I_O | 1 |O4 | | | | |
116 | I_O | 1 |O2 | | | | |
117 | IN8 | 1 | | | | | |
118 |GNDIO1 | - | | | | | |
119 |VCCIO1 | - | | | | | |
120 | I_O | 1 |P12 | | | | |
121 | I_O | 1 |P10 | | | | |
122 | I_O | 1 |P8 | | | | |
123 | I_O | 1 |P6 | | | | |
124 | I_O | 1 |P4 | | | | |
125 | I_O/OE| 1 |P2 | | | | |
126 |INCLK3 | 1 | | | | | |
127 |GNDIO0 | - | | | | | |
128 |INCLK0 | 0 | | | | | |
129 | VCC | - | | | | | |
130 | I_O/OE| 0 |A2 | | | | |
131 | I_O | 0 |A4 | | | | |
132 | I_O | 0 |A6 | | | | |
133 | I_O | 0 |A8 | | | | |
134 | I_O | 0 |A10 | | | | |
135 | I_O | 0 |A12 | | | | |
136 |VCCIO0 | - | | | | | |
137 |GNDIO0 | - | | | | | |
138 | I_O | 0 |B2 | | | | |
139 | I_O | 0 |B4 | | | | |
140 | I_O | 0 |B6 | | | | |
141 | I_O | 0 |B8 | | | | |
142 | I_O | 0 |B10 | | | | |
143 | I_O | 0 |B12 | | | | |
144 | IN9 | 0 | | | | | |
-----------------------------------------------------------------------------------
<Note> GLB Pad : This notation refers to the GLB I/O pad number in the device.
<Note> Assigned Pin : user or dedicated input assignment (E.g. Clock pins).
<Note> Pin Type :
ClkIn : Dedicated input or clock pin
CLK : Dedicated clock pin
I_O : Input/Output pin
INP : Dedicated input pin
JTAG : JTAG Control and test pin
NC : No connected
<A name="Input_Signal_List"></A><FONT COLOR=maroon><U><B><big>Input_Signal_List</big></B></U></FONT>
<BR>
<B> Input
Pin Fanout
Pin GLB Type Pullup Signal
</B>-------------------------------------------------
72 -- IN ---------------- Off <A name=7>nrst</A>
-------------------------------------------------
<A name="Output_Signal_List"></A><FONT COLOR=maroon><U><B><big>Output_Signal_List</big></B></U></FONT>
<BR>
<B> I C P R P O Output
N L Mc R E U C O F B Fanout
Pin GLB P LL PTs S Type E S P E E P P Slew Pullup Signal
</B>--------------------------------------------------------------------------------
71 J 1 1 1 1 COM ---------------- Fast Off <A href=#14>nled_0_</A>
70 J 1 - 1 1 COM ---------------- Fast Off <A href=#13>nled_1_</A>
63 I 0 - 1 1 COM ---------------- Fast Off <A href=#12>nled_2_</A>
62 I 0 - 1 1 COM ---------------- Fast Off <A href=#11>nled_3_</A>
61 I 3 - 1 1 DFF * R ---------------- Fast Off <A href=#10>nled_4_</A>
60 I 3 - 1 1 DFF * S ---------------- Fast Off <A href=#9>nled_5_</A>
59 I 3 - 1 1 DFF * S ---------------- Fast Off <A href=#8>nled_6_</A>
58 I 3 - 1 1 DFF * S ---------------- Fast Off <A href=#6>nled_7_</A>
--------------------------------------------------------------------------------
<Note> CLS = Number of clusters used
INP = Number of input signals
PTs = Number of product terms
LL = Number of logic levels
PRE = Has preset equation
RES = Has reset equation
PUP = Power-Up initial state: R=Reset, S=Set
CE = Has clock enable equation
OE = Has output enable equation
FP = Fast path used
OBP = ORP bypass used
<A name="Bidir_Signal_List"></A><FONT COLOR=maroon><U><B><big>Bidir_Signal_List</big></B></U></FONT>
<BR>
<B> I C P R P O Bidir
N L Mc R E U C O F B Fanout
Pin GLB P LL PTs S Type E S P E E P P Slew Pullup Signal
</B>-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
<Note> CLS = Number of clusters used
INP = Number of input signals
PTs = Number of product terms
LL = Number of logic levels
PRE = Has preset equation
RES = Has reset equation
PUP = Power-Up initial state: R=Reset, S=Set
CE = Has clock enable equation
OE = Has output enable equation
FP = Fast path used
OBP = ORP bypass used
<A name="Buried_Signal_List"></A><FONT COLOR=maroon><U><B><big>Buried_Signal_List</big></B></U></FONT>
<BR>
<B> I C P R P Node
N L Mc R E U C I F Fanout
Mc GLB P LL PTs S Type E S P E R P Signal
</B>---------------------------------------------------------------------
15 F 0 - 0 1 COM 2 --------IJ------ <A href=#22>_dup_gnd_n_n</A>
3 I 3 - 1 1 DFF * S 1 --------I------- <A href=#17>bbs1_dout_0_</A>
5 I 3 - 1 1 DFF * R 1 --------I------- <A href=#18>bbs1_dout_1_</A>
7 I 3 - 1 1 DFF * R 1 --------I------- <A href=#19>bbs1_dout_2_</A>
12 I 3 - 1 1 DFF * R 1 --------I------- <A href=#20>bbs1_dout_3_</A>
15 F 0 - 0 0 COM 2 --------IJ------ <A href=#16>clk</A>
15 C 0 - 0 1 COM ---------------- <A href=#15>gnd_n_n</A>
---------------------------------------------------------------------
<Note> CLS = Number of clusters used
INP = Number of input signals
PTs = Number of product terms
LL = Number of logic levels
PRE = Has preset equation
RES = Has reset equation
PUP = Power-Up initial state: R=Reset, S=Set
CE = Has clock enable equation
OE = Has output enable equation
IR = Input register
FP = Fast path used
OBP = ORP bypass used
<A name="PostFit_Equations"></A><FONT COLOR=maroon><U><B><big>PostFit_Equations</big></B></U></FONT>
<BR>
<A name=22>_dup_gnd_n_n</A> = 0 ; (0 pterm, 0 signal)
<A name=17>bbs1_dout_0_.D</A> = <A href=#20>bbs1_dout_3_.Q</A> ; (1 pterm, 1 signal)
bbs1_dout_0_.C = <A href=#16>clk</A> ; (1 pterm, 1 signal)
bbs1_dout_0_.AP = !<A href=#7>nrst</A> ; (1 pterm, 1 signal)
<A name=18>bbs1_dout_1_.D</A> = <A href=#17>bbs1_dout_0_.Q</A> ; (1 pterm, 1 signal)
bbs1_dout_1_.C = <A href=#16>clk</A> ; (1 pterm, 1 signal)
bbs1_dout_1_.AR = !<A href=#7>nrst</A> ; (1 pterm, 1 signal)
<A name=19>bbs1_dout_2_.D</A> = <A href=#18>bbs1_dout_1_.Q</A> ; (1 pterm, 1 signal)
bbs1_dout_2_.C = <A href=#16>clk</A> ; (1 pterm, 1 signal)
bbs1_dout_2_.AR = !<A href=#7>nrst</A> ; (1 pterm, 1 signal)
<A name=20>bbs1_dout_3_.D</A> = <A href=#19>bbs1_dout_2_.Q</A> ; (1 pterm, 1 signal)
bbs1_dout_3_.C = <A href=#16>clk</A> ; (1 pterm, 1 signal)
bbs1_dout_3_.AR = !<A href=#7>nrst</A> ; (1 pterm, 1 signal)
<A name=15>gnd_n_n</A> = 0 ; (0 pterm, 0 signal)
<A name=14>nled_0_</A> = <A href=#7>nrst</A> ; (1 pterm, 1 signal)
<A name=13>nled_1_</A> = !<A href=#16>clk</A> ; (1 pterm, 1 signal)
<A name=12>nled_2_</A> = 1 ; (1 pterm, 0 signal)
<A name=11>nled_3_</A> = 1 ; (1 pterm, 0 signal)
<A name=10>nled_4_.D</A> = !<A href=#20>bbs1_dout_3_.Q</A> ; (1 pterm, 1 signal)
nled_4_.C = <A href=#16>clk</A> ; (1 pterm, 1 signal)
nled_4_.AR = !<A href=#7>nrst</A> ; (1 pterm, 1 signal)
<A name=9>nled_5_.D</A> = !<A href=#17>bbs1_dout_0_.Q</A> ; (1 pterm, 1 signal)
nled_5_.C = <A href=#16>clk</A> ; (1 pterm, 1 signal)
nled_5_.AP = !<A href=#7>nrst</A> ; (1 pterm, 1 signal)
<A name=8>nled_6_.D</A> = !<A href=#18>bbs1_dout_1_.Q</A> ; (1 pterm, 1 signal)
nled_6_.C = <A href=#16>clk</A> ; (1 pterm, 1 signal)
nled_6_.AP = !<A href=#7>nrst</A> ; (1 pterm, 1 signal)
<A name=6>nled_7_.D</A> = !<A href=#19>bbs1_dout_2_.Q</A> ; (1 pterm, 1 signal)
nled_7_.C = <A href=#16>clk</A> ; (1 pterm, 1 signal)
nled_7_.AP = !<A href=#7>nrst</A> ; (1 pterm, 1 signal)
<BR>
<BR>
<BR>
<BR>
<BR>
<BR>
<BR>
<BR>
<BR>
<BR>
<BR>
<BR>
<BR>
<BR>
<BR>
<BR>
<BR>
<BR>
<BR>
<BR>
<BR>
<BR>
<BR>
<BR>
<BR>
<BR>
<BR>
<BR>
<BR>
<BR>
<BR>
<BR>
<BR>
<BR>
<BR>
<BR>
<BR>
<BR>
<BR>
<BR>
<BR>
<BR>
<BR>
<BR>
<BR>
<BR>
<BR>
<BR>
<BR>
<BR>