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x86_tree.cpp
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x86_tree.cpp
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#include <iostream>
#include "native_lib.h"
#include "x86_tree.h"
#include "util.h"
using namespace std;
MemPool *xpool;
void *XNode::operator new(size_t sz)
{
return xpool->memAlloc(sz);
}
void XNode::operator delete(void *ptrb)
{
return xpool->memFree(ptrb);
}
#define IMPLEMENT_ALU_INSTRUCTION_2ARG(opname, opcode, function) \
bool XI_##opcode::exec(X86Sim *sim, XReference &result) { \
XReference ref1; \
\
if (!arg1->getReference(sim, ref1)) \
return false; \
\
if ((ref1.type != RT_Reg) && (ref1.type != RT_Mem)) { \
reportRuntimeError("Invalid destination '%s' for " opname " instruction.\n", arg1->toString().c_str()); \
return false; \
} \
\
XReference ref2; \
\
if (!arg2->getReference(sim, ref2)) \
return false; \
\
if ((ref1.type == RT_Mem) && (ref2.type == RT_Mem)) { \
reportRuntimeError("Memory-Memory references are not allowed.\n"); \
return false; \
} \
uint32_t value2; \
\
if (ref2.bitSize == 0) \
ref2.bitSize = ref1.bitSize; \
\
if (!ref2.deref(value2)) { \
reportRuntimeError("Unexpected error (deref) maybe a BUG '%s'\n", getName()); \
return false; \
} \
\
if (!sim->doOperation(function, ref1, value2)) { \
reportRuntimeError("Invalid arguments for operation.\n"); \
return false; \
} \
\
if ((function != XFN_CMP) && (function != XFN_TEST)) { \
result = ref1; \
} else { \
result.type = RT_None; \
} \
\
return true; \
}
#define SET_BYTE_ON_CONDITION_INST_PROLOG(a_ref) \
do { \
if (arg->getKind() != XARG_MEMREF && \
arg->getKind() != XARG_REGISTER) { \
reportRuntimeError("Invalid argument '%s' for instruction '%s'\n", \
arg->toString().c_str(), \
this->getName()); \
return false; \
} \
\
if (!arg->getReference(sim, a_ref)) { \
return false; \
} \
\
if (a_ref.bitSize != BS_8) { \
reportRuntimeError("Invalid operand size in instruction '%s'\n", this->getName()); \
return false; \
} \
} while (0)
/* XArgument 'eval' method implementation */
bool XArgRegister::eval(X86Sim *xsim, int resultSize, uint8_t flags, uint32_t &result)
{
if (!WANT_XTEND(flags) && resultSize != regSize) {
reportRuntimeError("Operand sizes do not match. Expected %d bits size.\n", BIT_SIZE(resultSize));
return false;
}
if (WANT_XTEND(flags) && regSize >= resultSize) {
reportRuntimeError("Invalid size of operand '%s'. Size is %d bits.\n", toString().c_str(), regSize);
return false;
}
uint32_t value;
if (!xsim->getRegValue(regId, value))
return false;
result = (flags & SX_MASK)? signExtend(value, regSize, resultSize) : value;
return true;
}
bool XArgRegister::getReference(X86Sim *sim, XReference &ref)
{
UNUSED(sim);
ref.type = RT_Reg;
ref.bitSize = this->regSize;
ref.address = this->regId;
ref.sim = sim;
return true;
}
bool XArgMemRef::eval(X86Sim *xsim, int resultSize, uint8_t flags, uint32_t &result)
{
int wordSize;
wordSize = (sizeDirective==0)? resultSize : sizeDirective;
if (!WANT_XTEND(flags) && resultSize != wordSize) {
reportRuntimeError("Error: Operand sizes do not match. Expected %d bits size.\n", BIT_SIZE(resultSize));
return false;
}
if (WANT_XTEND(flags) && wordSize >= resultSize) {
reportRuntimeError("Invalid size of operand '%s'\n", toString().c_str());
return false;
}
uint32_t vaddr;
if (!expr->eval(xsim, vaddr))
return false;
uint32_t value;
if (!xsim->readMem(vaddr, value, wordSize)) {
reportRuntimeError("Cannot read address '0x%X'.\n", vaddr);
return false;
}
result = (flags & SX_MASK)? signExtend(value, wordSize, resultSize) : value;
return true;
}
bool XArgMemRef::getReference(X86Sim *xsim, XReference &ref)
{
uint32_t vaddr;
if (!expr->eval(xsim, vaddr))
return false;
ref.type = RT_Mem;
ref.bitSize = this->sizeDirective;
ref.address = vaddr;
ref.sim = xsim;
return true;
}
bool XArgPhyAddress::getReference(X86Sim *sim, XReference &ref)
{
uint32_t vaddr;
if (!expr->eval(sim, vaddr))
return false;
ref.type = RT_PMem;
ref.bitSize = BS_32;
ref.address = vaddr;
ref.sim = sim;
return true;
}
bool XArgPhyAddress::eval(X86Sim *sim, int resultSize, uint8_t flags, uint32_t &result)
{
XReference my_ref;
if (!getReference(sim, my_ref))
return false;
return my_ref.deref(result);
}
bool XArgConstant::eval(X86Sim *sim, int resultSize, uint8_t flags, uint32_t &result)
{
UNUSED(sim);
if (WANT_XTEND(flags)) {
reportRuntimeError("Invalid operand '%s'.\n", toString().c_str());
return false;
}
uint32_t mask = MASK_FOR(resultSize);
result = value & mask;
return true;
}
bool XArgConstant::getReference(X86Sim *sim, XReference &ref)
{
UNUSED(sim);
ref.type = RT_Const;
ref.bitSize = BS_32;
ref.address = value;
ref.sim = sim;
return true;
}
/* XAddrExpr 'eval' method implementation */
bool XAddrExprReg::eval(X86Sim *xsim, uint32_t &result)
{
if (reg->getKind() != XARG_REGISTER) {
string str = reg->toString();
reportRuntimeError("Invalid register '%s' in memory address expression\n", str.c_str());
return false;
}
XArgRegister *r = (XArgRegister *)reg;
return xsim->getRegValue(r->regId, result);
}
bool XAddrExprConst::eval(X86Sim *sim, uint32_t &result)
{
UNUSED(sim);
result = value;
return true;
}
bool XAddrExpr2Term::eval(X86Sim *xsim, uint32_t &result)
{
uint32_t v1, v2;
if ((op == XOP_MINUS) && !expr2->isA(XADDR_EXPR_CONST)) {
reportRuntimeError("Invalid expression '%s' in memory reference.\n", toString().c_str());
return false;
}
if ( (expr1->isA(XADDR_EXPR_REG) && expr2->isA(XADDR_EXPR_MULT)) ||
(expr1->isA(XADDR_EXPR_REG) && expr2->isA(XADDR_EXPR_CONST)) ||
(expr1->isA(XADDR_EXPR_REG) && expr2->isA(XADDR_EXPR_REG)) ||
(expr1->isA(XADDR_EXPR_CONST) && expr2->isA(XADDR_EXPR_MULT)) ||
(expr1->isA(XADDR_EXPR_CONST) && expr2->isA(XADDR_EXPR_CONST)) ||
(expr1->isA(XADDR_EXPR_CONST) && expr2->isA(XADDR_EXPR_REG)) ||
(expr1->isA(XADDR_EXPR_MULT) && expr2->isA(XADDR_EXPR_CONST)) ||
(expr1->isA(XADDR_EXPR_MULT) && expr2->isA(XADDR_EXPR_REG)) ) {
if (!expr1->eval(xsim, v1))
return false;
if (!expr2->eval(xsim, v2))
return false;
if (op == XOP_PLUS)
result = v1 + v2;
else
result = v1 - v2;
return true;
} else {
reportRuntimeError("Invalid expression '%s' in memory reference.\n", toString().c_str());
return false;
}
}
bool XAddrExpr3Term::eval(X86Sim *xsim, uint32_t &result)
{
if ((op1 == XOP_MINUS) && !expr2->isA(XADDR_EXPR_CONST)) {
reportRuntimeError("Invalid expression '%s' in memory reference.\n", toString().c_str());
return false;
}
if ((op2 == XOP_MINUS) && !expr3->isA(XADDR_EXPR_CONST)) {
reportRuntimeError("Invalid expression '%s' in memory reference.\n", toString().c_str());
return false;
}
if ( (expr1->isA(XADDR_EXPR_REG) && expr2->isA(XADDR_EXPR_MULT) && expr3->isA(XADDR_EXPR_CONST)) ||
(expr1->isA(XADDR_EXPR_REG) && expr2->isA(XADDR_EXPR_CONST) && expr3->isA(XADDR_EXPR_MULT)) ||
(expr1->isA(XADDR_EXPR_CONST) && expr2->isA(XADDR_EXPR_REG) && expr3->isA(XADDR_EXPR_MULT)) ||
(expr1->isA(XADDR_EXPR_CONST) && expr2->isA(XADDR_EXPR_MULT) && expr3->isA(XADDR_EXPR_REG)) ||
(expr1->isA(XADDR_EXPR_MULT) && expr2->isA(XADDR_EXPR_CONST) && expr3->isA(XADDR_EXPR_REG)) ||
(expr1->isA(XADDR_EXPR_MULT) && expr2->isA(XADDR_EXPR_REG) && expr3->isA(XADDR_EXPR_CONST))
) {
uint32_t v1, v2, v3;
if (!expr1->eval(xsim, v1))
return false;
if (!expr2->eval(xsim, v2))
return false;
if (!expr3->eval(xsim, v3))
return false;
if (op1 == XOP_PLUS)
result = v1 + v2;
else
result = v1 - v2;
if (op2 == XOP_PLUS)
result += v3;
else
result -= v3;
return true;
} else {
reportRuntimeError("Invalid expression '%s' in memory reference.\n", toString().c_str());
return false;
}
}
bool XAddrExprMult::eval(X86Sim *xsim, uint32_t &result)
{
uint32_t v1, v2;
if (!expr1->eval(xsim, v1))
return false;
if (!expr2->eval(xsim, v2))
return false;
if (expr1->isA(XADDR_EXPR_REG) &&
expr2->isA(XADDR_EXPR_CONST)) {
uint32_t temp = v2;
v2 = v1;
v1 = temp;
} else if ( expr1->isA(XADDR_EXPR_CONST) &&
expr2->isA(XADDR_EXPR_REG) ) {
} else {
reportRuntimeError("Invalid expression '%s' in memory reference.\n", toString().c_str());
return false;
}
if ((v1 != 1) && (v1 != 2) && (v1 != 4) && (v1 != 8)) {
reportRuntimeError("Invalid scalar multiplier %d in address expression '%s'. "
"Valid values are 1, 2, 4, 8.", v1, toString().c_str());
return false;
}
result = v1 * v2;
return true;
}
/* Instructions implementation */
IMPLEMENT_INSTRUCTION(Mov) {
XReference ref1;
if (!arg1->getReference(sim, ref1))
return false;
if ((ref1.type == RT_Mem) && (arg2->getKind() == XARG_MEMREF)) {
reportRuntimeError("Memory-Memory references are not allowed.\n");
return false;
}
uint32_t value2;
if (!arg2->eval(sim, ref1.bitSize, 0, value2)) {
reportRuntimeError("Invalid argument '%s' in mov instruction.\n", arg2->toString().c_str());
return false;
}
if (ref1.bitSize == 0) ref1.bitSize = BS_32;
result = ref1;
return ref1.assign(value2);
}
IMPLEMENT_INSTRUCTION(Movsx) {
XReference ref1;
if (!arg1->getReference(sim, ref1))
return false;
if ((ref1.type == RT_Mem) && (arg2->getKind() == XARG_MEMREF)) {
reportRuntimeError("Memory-Memory references are not allowed.\n");
return false;
}
uint32_t value2;
if (!arg2->eval(sim, ref1.bitSize, SX_MASK, value2)) {
reportRuntimeError("Invalid argument '%s' in movsx instruction.\n", arg2->toString().c_str());
return false;
}
result = ref1;
return ref1.assign(value2);
}
IMPLEMENT_INSTRUCTION(Movzx) {
XReference ref1;
if (!arg1->getReference(sim, ref1))
return false;
if ((ref1.type == RT_Mem) && (arg2->getKind() == XARG_MEMREF)) {
reportRuntimeError("Memory-Memory references are not allowed.\n");
return false;
}
uint32_t value2;
if (!arg2->eval(sim, ref1.bitSize, ZX_MASK, value2)) {
reportRuntimeError("Invalid argument '%s' in movzx instruction.\n", arg2->toString().c_str());
return false;
}
result = ref1;
return ref1.assign(value2);
}
IMPLEMENT_INSTRUCTION(Push) {
XReference ref1;
if (!arg->getReference(sim, ref1)) {
reportRuntimeError("getReference error %s\n", arg->toString().c_str());
return false;
}
if (ref1.bitSize < BS_16) {
reportRuntimeError("Expected 32 or 16 bits argument. Found %d bit size.\n", ref1.bitSize);
return false;
}
uint32_t value;
if (!ref1.deref(value)) {
reportRuntimeError("getValue error %X\n", ref1.address);
return false;
}
uint32_t esp;
sim->getRegValue(R_ESP, esp);
esp -= ref1.bitSize / 8;
if (!sim->writeMem(esp, value, ref1.bitSize)) {
reportRuntimeError("Invalid address '0x%X'. Maybe stack overflow.\n", esp);
return false;
}
sim->setRegValue(R_ESP, esp);
result.type = RT_Mem;
result.bitSize = ref1.bitSize;
result.address = esp;
return true;
}
IMPLEMENT_INSTRUCTION(Pop) {
XReference ref1;
if (!arg->getReference(sim, ref1))
return false;
if (ref1.bitSize < BS_16) {
reportRuntimeError("Expected 32 or 16 bits argument. Found %d bit size.\n", ref1.bitSize);
return false;
}
uint32_t esp, value;
sim->getRegValue(R_ESP, esp);
if (!sim->readMem(esp, value, ref1.bitSize)) {
reportRuntimeError("Invalid address '0x%X'.\n", esp);
return false;
}
if (!ref1.assign(value)) {
reportRuntimeError("Oops: BUG in the machine.\n", esp);
return false;
}
esp += ref1.bitSize / 8;
sim->setRegValue(R_ESP, esp);
result = ref1;
return true;
}
IMPLEMENT_INSTRUCTION(Lea) {
XReference ref1;
if (!arg1->getReference(sim, ref1))
return false;
if (ref1.type != RT_Reg) {
reportRuntimeError("Invalid destination '%s' for 'lea' instruction.\n", arg1->toString().c_str());
return false;
}
XReference ref2;
if (!arg2->getReference(sim, ref2))
return false;
if (ref2.type != RT_Mem) {
reportRuntimeError("Second argument of instruction 'lea' should be a memory reference.\n");
return false;
}
if (!ref1.assign(ref2.address))
return false;
result = ref1;
return true;
}
IMPLEMENT_ALU_INSTRUCTION_2ARG("'add'", Add, XFN_ADD)
IMPLEMENT_ALU_INSTRUCTION_2ARG("'sub'", Sub, XFN_SUB)
IMPLEMENT_ALU_INSTRUCTION_2ARG("'and'", And, XFN_AND)
IMPLEMENT_ALU_INSTRUCTION_2ARG("'or'", Or, XFN_OR)
IMPLEMENT_ALU_INSTRUCTION_2ARG("'xor'", Xor, XFN_XOR)
IMPLEMENT_ALU_INSTRUCTION_2ARG("'cmp'", Cmp, XFN_CMP)
IMPLEMENT_ALU_INSTRUCTION_2ARG("'test'", Test, XFN_TEST)
IMPLEMENT_INSTRUCTION(Shl) {
XReference ref1, ref2;
if (!arg1->getReference(sim, ref1))
return false;
if (!arg2->getReference(sim, ref2))
return false;
if (ref2.type != RT_Reg && ref2.type != RT_Const) {
reportRuntimeError("Invalid argument for shift operation. Expected register register or constant.\n");
return false;
}
if ((ref2.type == RT_Reg) && (ref2.address != R_CL)) {
reportRuntimeError("Invalid argument for shift operation. Expected register 'cl'.\n");
return false;
}
uint32_t value2;
if (!ref2.deref(value2)) {
reportRuntimeError("Unexpected error %d: %s.\n", __LINE__, __FUNCTION__);
return false;
}
if (!sim->doOperation(XFN_SHL, ref1, value2)) {
reportRuntimeError("Invalid argument for operation.\n");
return false;
}
result = ref1;
return true;
}
IMPLEMENT_INSTRUCTION(Shr) {
XReference ref1, ref2;
if (!arg1->getReference(sim, ref1))
return false;
if (!arg2->getReference(sim, ref2))
return false;
if (ref2.type != RT_Reg && ref2.type != RT_Const) {
reportRuntimeError("Invalid argument for shift operation. Expected register register or constant.\n");
return false;
}
if ((ref2.type == RT_Reg) && (ref2.address != R_CL)) {
reportRuntimeError("Invalid argument for shift operation. Expected register 'cl'.\n");
return false;
}
uint32_t value2;
if (!ref2.deref(value2)) {
reportRuntimeError("Unexpected error %d: %s.\n", __LINE__, __FUNCTION__);
return false;
}
if (!sim->doOperation(XFN_SHR, ref1, value2)) {
reportRuntimeError("Invalid argument for operation.\n");
return false;
}
result = ref1;
return true;
}
IMPLEMENT_INSTRUCTION(Leave) {
UNUSED(result);
uint32_t ebp_value, old_ebp_value;
sim->getRegValue(R_EBP, ebp_value);
sim->setRegValue(R_ESP, ebp_value);
if (!sim->readMem(ebp_value, old_ebp_value, BS_32)) {
reportRuntimeError("Invalid address '0x%X'.\n", ebp_value);
return false;
}
sim->setRegValue(R_EBP, old_ebp_value);
ebp_value += 4;
sim->setRegValue(R_ESP, ebp_value);
return true;
}
IMPLEMENT_INSTRUCTION(Imul1) {
if (!arg->isA(XARG_REGISTER) && !arg->isA(XARG_MEMREF)) {
reportRuntimeError("Invalid arguments '%s' in iMul instruction\n", arg->toString().c_str());
return false;
}
XReference a_ref;
if (!arg->getReference(sim,a_ref))
return false;
uint32_t arg_value, eflags = 0;
if (!a_ref.deref(arg_value))
return false;
result.type = RT_Reg;
result.sim = sim;
switch(a_ref.bitSize) {
case BS_8:{
int32_t temp;
uint32_t reg_al, reg_ax;
sim->getRegValue(R_AL, reg_al);
temp = (int32_t)reg_al * (int32_t)arg_value;
reg_ax = temp & 0xFFFF;
sim->setRegValue(R_AX, reg_ax);
sim->getRegValue(R_AL, reg_al);
if ( (int32_t)reg_al != (int32_t)reg_ax ) {
eflags = (1 << CF_POS) | (1 << OF_POS);
}
result.address = R_AX;
result.bitSize = BS_16;
break;
}
case BS_16:{
int32_t temp;
uint32_t reg_ax, reg_dx;
sim->getRegValue(R_AX,reg_ax);
temp = (int32_t)reg_ax * (int32_t)arg_value;
reg_ax = temp & 0xFFFF;
reg_dx = (temp & (0xFFFF << 16)) >> 16;
sim->setRegValue(R_AX,reg_ax);
sim->setRegValue(R_AX,reg_dx);
if (temp != (int32_t)reg_ax) {
eflags = (1 << CF_POS) | (1 << OF_POS);
}
result.address = R_AX;
result.bitSize = BS_16;
break;
}
case BS_32:{
int64_t temp;
uint32_t reg_eax, reg_edx;
sim->getRegValue(R_EAX,reg_eax);
temp = (int64_t)reg_eax * (int64_t)arg_value;
reg_eax = temp & 0xFFFFFFFF;
reg_edx = ((int64_t)temp & 0xFFFFFFFF00000000) >> 32;
sim->setRegValue(R_EAX,reg_eax);
sim->setRegValue(R_EDX,reg_edx);
if ((int64_t)temp != (int64_t)reg_eax) {
eflags = (1 << CF_POS) | (1 << OF_POS);
}
result.address = R_EAX;
result.bitSize = BS_32;
break;
}
}
sim->setRegValue(R_EFLAGS, eflags);
return true;
}
IMPLEMENT_INSTRUCTION(Imul2) {
XReference ref1;
if (!arg1->getReference(sim, ref1))
return false;
if ( (ref1.type != RT_Reg) || ((ref1.bitSize != BS_16) && (ref1.bitSize != BS_32)) ) {
reportRuntimeError("Invalid destination '%s' for IMUL instruction.\n", arg1->toString().c_str());
return false;
}
XReference ref2;
if (!arg2->getReference(sim, ref2))
return false;
if (ref2.bitSize == 0)
ref2.bitSize = ref1.bitSize;
switch (ref2.type) {
case RT_Mem:
case RT_Reg: {
if (ref1.bitSize != ref2.bitSize) {
reportRuntimeError("Invalid arguments in IMUL instruction. Both operands should be 16 bits or 32 bits.\n");
return false;
}
break;
}
case RT_Const: {
break;
}
}
uint32_t value1, value2;
if (!ref1.deref(value1)) {
reportRuntimeError("Unexpected error %d: %s.\n", __LINE__, __FUNCTION__);
return false;
}
if (!ref2.deref(value2)) {
reportRuntimeError("Unexpected error %d: %s.\n", __LINE__, __FUNCTION__);
return false;
}
uint32_t eflags = 0;
switch (ref1.bitSize) {
case BS_16: {
int32_t temp = (int32_t)((int16_t)value1) * (int32_t)((int16_t)value2);
value1 = temp & 0xFFFF;
if ( (int32_t)((int16_t)value1) != temp ) {
eflags = (1 << CF_POS) | (1 << OF_POS);
}
break;
}
case BS_32: {
int64_t temp = (int64_t)((int32_t)value1) * (int64_t)((int32_t)value2);
value1 = temp & 0xFFFFFFFF;
if ( (int64_t)((int32_t)value1) != temp ) {
eflags = (1 << CF_POS) | (1 << OF_POS);
}
break;
}
}
sim->setRegValue(R_EFLAGS, eflags);
if (!ref1.assign(value1)) {
return false;
}
result = ref1;
return true;
}
IMPLEMENT_INSTRUCTION(Imul3) {
UNUSED(sim);
UNUSED(result);
reportRuntimeError("IMUL instruction with three argument not supported.\n");
return false;
}
IMPLEMENT_INSTRUCTION(Idiv) {
UNUSED(sim);
UNUSED(result);
if (!arg->isA(XARG_REGISTER) && !arg->isA(XARG_MEMREF)) {
reportRuntimeError("Invalid arguments '%s' in IDIV instruction\n", arg->toString().c_str());
return false;
}
XReference ref;
if (!arg->getReference(sim, ref)) {
reportRuntimeError("Unknown error in getRef '%s'\n", arg->toString().c_str());
return false;
}
switch (ref.bitSize) {
case BS_8:
case BS_16:
reportRuntimeError("EasyASM only supports 32 bits operands in IDIV instruction\n");
return false;
case BS_32: {
int64_t temp, edx_eax;
uint32_t eax, edx, arg_value;
sim->getRegValue(R_EAX, eax);
sim->getRegValue(R_EDX, edx);
ref.deref(arg_value);
edx_eax = ((int64_t)edx << 32) | eax;
temp = edx_eax / (int32_t)arg_value;
if(temp > 0x7FFFFFFF || temp < (int32_t)0x80000000) {
reportRuntimeError("Exception in IDIV instruction, quotient too big.\n");
sim->runtimeCtx->stop = true;
return false;
}
eax = temp & 0xFFFFFFFF;
edx = edx_eax % ((int32_t)arg_value);
sim->setRegValue(R_EAX, eax);
sim->setRegValue(R_EDX, edx);
return true;
}
default:
reportRuntimeError("Memory reference in IDIV instruction requires size directive 'byte', 'word' or 'dword'\n");
return false;
}
}
IMPLEMENT_INSTRUCTION(Mul) {
if (!arg->isA(XARG_REGISTER) && !arg->isA(XARG_MEMREF)) {
reportRuntimeError("Invalid arguments '%s' in Mul instruction\n", arg->toString().c_str());
return false;
}
XReference a_ref;
if (!arg->getReference(sim, a_ref))
return false;
uint32_t arg_value, eflags = 0;
if (!a_ref.deref(arg_value))
return false;
result.type = RT_Reg;
result.sim = sim;
switch (a_ref.bitSize) {
case BS_8: {
uint32_t temp, reg_al;
sim->getRegValue(R_AL, reg_al);
temp = reg_al * arg_value;
arg_value = temp & 0xFFFF;
sim->setRegValue(R_AX, arg_value);
if ( (temp & 0xFF00) != 0 ) {
eflags = (1 << CF_POS) | (1 << OF_POS);
}
result.address = R_AX;
result.bitSize = BS_16;
break;
}
case BS_16: {
uint32_t temp, reg_ax, reg_dx;
sim->getRegValue(R_AX, reg_ax);
temp = reg_ax * arg_value;
reg_ax = temp & 0x0000FFFF;
reg_dx = (temp & 0xFFFF0000) >> 16;
sim->setRegValue(R_AX, reg_ax);
sim->setRegValue(R_DX, reg_dx);
if (reg_dx != 0) {
eflags = (1 << CF_POS) | (1 << OF_POS);
}
result.address = R_AX;
result.bitSize = BS_16;
break;
}
case BS_32: {
uint64_t temp;
uint32_t reg_eax, reg_edx;
sim->getRegValue(R_EAX, reg_eax);
temp = (uint64_t)reg_eax * (uint64_t)arg_value;
reg_eax = temp & 0xFFFFFFFF;
reg_edx = (temp & 0xFFFFFFFF00000000) >> 32;
sim->setRegValue(R_EAX, reg_eax);
sim->setRegValue(R_EDX, reg_edx);
if (reg_edx != 0) {
eflags = (1 << CF_POS) | (1 << OF_POS);
}
result.address = R_EAX;
result.bitSize = BS_32;
break;
}
}
sim->setRegValue(R_EFLAGS, eflags);
return true;
}
IMPLEMENT_INSTRUCTION(Div) {
if (!arg->isA(XARG_REGISTER) && !arg->isA(XARG_MEMREF)) {
reportRuntimeError("Invalid arguments '%s' in Div instruction\n", arg->toString().c_str());
return false;
}
XReference a_ref;
if (!arg->getReference(sim, a_ref))
return false;
uint32_t arg_value, eflags = 0;
if (!a_ref.deref(arg_value))
return false;
if (arg_value == 0) {
reportRuntimeError("Divide error in Div instruction, divide by zero not supported.\n");
return false;
}
result.type = RT_Reg;
result.sim = sim;
switch(a_ref.bitSize){
case BS_8:{
uint32_t temp, reg_ax;
sim->getRegValue(R_AX, reg_ax);
temp = reg_ax / arg_value;
if (temp > 0xFF) {
reportRuntimeError("Divide error Maximum Quotient: 2^8 - 1\n");
return false;
}
temp |= (reg_ax % arg_value) << 8;
arg_value = temp & 0xFFFF;
sim->setRegValue(R_AX, arg_value);
result.address = R_AL;
result.bitSize = BS_8;
break;
}
case BS_16:{
uint32_t reg_dx, reg_ax, reg_dx_ax;
sim->getRegValue(R_DX,reg_dx);
sim->getRegValue(R_AX,reg_ax);
reg_dx_ax = (reg_dx << 16) | reg_ax;
reg_ax = reg_dx_ax / arg_value;