From 6fa58f4c3c1899460b81e1cb7af0d2553c8f8aaf Mon Sep 17 00:00:00 2001 From: imkiva Date: Fri, 25 Oct 2024 13:11:59 +0800 Subject: [PATCH] [Clang][XTHeadVector] Implement zvlsseg unit-stride variant (#131) --- .../Basic/riscv_vector_xtheadv_wrappers.td | 490 ++++++++++++++++++ .../zvlsseg/unit-stride/{ => thead}/vlseg2b.c | 0 .../unit-stride/{ => thead}/vlseg2e16.c | 0 .../unit-stride/{ => thead}/vlseg2e16ff.c | 0 .../unit-stride/{ => thead}/vlseg2e32.c | 0 .../unit-stride/{ => thead}/vlseg2e32ff.c | 0 .../unit-stride/{ => thead}/vlseg2e64.c | 0 .../unit-stride/{ => thead}/vlseg2e64ff.c | 0 .../unit-stride/{ => thead}/vlseg2e8.c | 0 .../unit-stride/{ => thead}/vlseg2e8ff.c | 0 .../unit-stride/{ => thead}/vlseg3e16.c | 0 .../unit-stride/{ => thead}/vlseg3e16ff.c | 0 .../unit-stride/{ => thead}/vlseg3e32.c | 0 .../unit-stride/{ => thead}/vlseg3e32ff.c | 0 .../unit-stride/{ => thead}/vlseg3e64.c | 0 .../unit-stride/{ => thead}/vlseg3e64ff.c | 0 .../unit-stride/{ => thead}/vlseg3e8.c | 0 .../unit-stride/{ => thead}/vlseg3e8ff.c | 0 .../unit-stride/{ => thead}/vlseg4e16.c | 0 .../unit-stride/{ => thead}/vlseg4e16ff.c | 0 .../unit-stride/{ => thead}/vlseg4e32.c | 0 .../unit-stride/{ => thead}/vlseg4e32ff.c | 0 .../unit-stride/{ => thead}/vlseg4e64.c | 0 .../unit-stride/{ => thead}/vlseg4e64ff.c | 0 .../unit-stride/{ => thead}/vlseg4e8.c | 0 .../unit-stride/{ => thead}/vlseg4e8ff.c | 0 .../unit-stride/{ => thead}/vlseg5e16.c | 0 .../unit-stride/{ => thead}/vlseg5e16ff.c | 0 .../unit-stride/{ => thead}/vlseg5e32.c | 0 .../unit-stride/{ => thead}/vlseg5e32ff.c | 0 .../unit-stride/{ => thead}/vlseg5e64.c | 0 .../unit-stride/{ => thead}/vlseg5e64ff.c | 0 .../unit-stride/{ => thead}/vlseg5e8.c | 0 .../unit-stride/{ => thead}/vlseg5e8ff.c | 0 .../unit-stride/{ => thead}/vlseg6e16.c | 0 .../unit-stride/{ => thead}/vlseg6e16ff.c | 0 .../unit-stride/{ => thead}/vlseg6e32.c | 0 .../unit-stride/{ => thead}/vlseg6e32ff.c | 0 .../unit-stride/{ => thead}/vlseg6e64.c | 0 .../unit-stride/{ => thead}/vlseg6e64ff.c | 0 .../unit-stride/{ => thead}/vlseg6e8.c | 0 .../unit-stride/{ => thead}/vlseg6e8ff.c | 0 .../unit-stride/{ => thead}/vlseg7e16.c | 0 .../unit-stride/{ => thead}/vlseg7e16ff.c | 0 .../unit-stride/{ => thead}/vlseg7e32.c | 0 .../unit-stride/{ => thead}/vlseg7e32ff.c | 0 .../unit-stride/{ => thead}/vlseg7e64.c | 0 .../unit-stride/{ => thead}/vlseg7e64ff.c | 0 .../unit-stride/{ => thead}/vlseg7e8.c | 0 .../unit-stride/{ => thead}/vlseg7e8ff.c | 0 .../unit-stride/{ => thead}/vlseg8e16.c | 0 .../unit-stride/{ => thead}/vlseg8e16ff.c | 0 .../unit-stride/{ => thead}/vlseg8e32.c | 0 .../unit-stride/{ => thead}/vlseg8e32ff.c | 0 .../unit-stride/{ => thead}/vlseg8e64.c | 0 .../unit-stride/{ => thead}/vlseg8e64ff.c | 0 .../unit-stride/{ => thead}/vlseg8e8.c | 0 .../unit-stride/{ => thead}/vlseg8e8ff.c | 0 .../zvlsseg/unit-stride/thead/vsseg2e16.c | 260 ++++++++++ .../zvlsseg/unit-stride/thead/vsseg2e32.c | 260 ++++++++++ .../zvlsseg/unit-stride/thead/vsseg2e64.c | 260 ++++++++++ .../zvlsseg/unit-stride/thead/vsseg2e8.c | 176 +++++++ .../zvlsseg/unit-stride/thead/vsseg3e16.c | 200 +++++++ .../zvlsseg/unit-stride/thead/vsseg3e32.c | 200 +++++++ .../zvlsseg/unit-stride/thead/vsseg3e64.c | 200 +++++++ .../zvlsseg/unit-stride/thead/vsseg3e8.c | 136 +++++ .../zvlsseg/unit-stride/thead/vsseg4e16.c | 224 ++++++++ .../zvlsseg/unit-stride/thead/vsseg4e32.c | 224 ++++++++ .../zvlsseg/unit-stride/thead/vsseg4e64.c | 224 ++++++++ .../zvlsseg/unit-stride/thead/vsseg4e8.c | 152 ++++++ .../zvlsseg/unit-stride/thead/vsseg5e16.c | 128 +++++ .../zvlsseg/unit-stride/thead/vsseg5e32.c | 128 +++++ .../zvlsseg/unit-stride/thead/vsseg5e64.c | 128 +++++ .../zvlsseg/unit-stride/thead/vsseg5e8.c | 88 ++++ .../zvlsseg/unit-stride/thead/vsseg6e16.c | 140 +++++ .../zvlsseg/unit-stride/thead/vsseg6e32.c | 140 +++++ .../zvlsseg/unit-stride/thead/vsseg6e64.c | 140 +++++ .../zvlsseg/unit-stride/thead/vsseg6e8.c | 96 ++++ .../zvlsseg/unit-stride/thead/vsseg7e16.c | 152 ++++++ .../zvlsseg/unit-stride/thead/vsseg7e32.c | 152 ++++++ .../zvlsseg/unit-stride/thead/vsseg7e64.c | 152 ++++++ .../zvlsseg/unit-stride/thead/vsseg7e8.c | 104 ++++ .../zvlsseg/unit-stride/thead/vsseg8e16.c | 164 ++++++ .../zvlsseg/unit-stride/thead/vsseg8e32.c | 164 ++++++ .../zvlsseg/unit-stride/thead/vsseg8e64.c | 164 ++++++ .../zvlsseg/unit-stride/thead/vsseg8e8.c | 112 ++++ .../zvlsseg/unit-stride/vsseg2e8.c | 91 ---- .../zvlsseg/unit-stride/wrappers/vlseg2b.c | 17 + .../zvlsseg/unit-stride/wrappers/vlseg2e16.c | 97 ++++ .../unit-stride/wrappers/vlseg2e16ff.c | 151 ++++++ .../zvlsseg/unit-stride/wrappers/vlseg2e32.c | 97 ++++ .../unit-stride/wrappers/vlseg2e32ff.c | 151 ++++++ .../zvlsseg/unit-stride/wrappers/vlseg2e64.c | 97 ++++ .../unit-stride/wrappers/vlseg2e64ff.c | 151 ++++++ .../zvlsseg/unit-stride/wrappers/vlseg2e8.c | 67 +++ .../zvlsseg/unit-stride/wrappers/vlseg2e8ff.c | 103 ++++ .../zvlsseg/unit-stride/wrappers/vlseg3e16.c | 67 +++ .../unit-stride/wrappers/vlseg3e16ff.c | 115 ++++ .../zvlsseg/unit-stride/wrappers/vlseg3e32.c | 67 +++ .../unit-stride/wrappers/vlseg3e32ff.c | 115 ++++ .../zvlsseg/unit-stride/wrappers/vlseg3e64.c | 67 +++ .../unit-stride/wrappers/vlseg3e64ff.c | 115 ++++ .../zvlsseg/unit-stride/wrappers/vlseg3e8.c | 47 ++ .../zvlsseg/unit-stride/wrappers/vlseg3e8ff.c | 79 +++ .../zvlsseg/unit-stride/wrappers/vlseg4e16.c | 67 +++ .../unit-stride/wrappers/vlseg4e16ff.c | 127 +++++ .../zvlsseg/unit-stride/wrappers/vlseg4e32.c | 67 +++ .../unit-stride/wrappers/vlseg4e32ff.c | 128 +++++ .../zvlsseg/unit-stride/wrappers/vlseg4e64.c | 67 +++ .../unit-stride/wrappers/vlseg4e64ff.c | 127 +++++ .../zvlsseg/unit-stride/wrappers/vlseg4e8.c | 47 ++ .../zvlsseg/unit-stride/wrappers/vlseg4e8ff.c | 87 ++++ .../zvlsseg/unit-stride/wrappers/vlseg5e16.c | 37 ++ .../unit-stride/wrappers/vlseg5e16ff.c | 73 +++ .../zvlsseg/unit-stride/wrappers/vlseg5e32.c | 39 ++ .../unit-stride/wrappers/vlseg5e32ff.c | 73 +++ .../zvlsseg/unit-stride/wrappers/vlseg5e64.c | 37 ++ .../unit-stride/wrappers/vlseg5e64ff.c | 73 +++ .../zvlsseg/unit-stride/wrappers/vlseg5e8.c | 27 + .../zvlsseg/unit-stride/wrappers/vlseg5e8ff.c | 51 ++ .../zvlsseg/unit-stride/wrappers/vlseg6e16.c | 37 ++ .../unit-stride/wrappers/vlseg6e16ff.c | 79 +++ .../zvlsseg/unit-stride/wrappers/vlseg6e32.c | 37 ++ .../unit-stride/wrappers/vlseg6e32ff.c | 79 +++ .../zvlsseg/unit-stride/wrappers/vlseg6e64.c | 37 ++ .../unit-stride/wrappers/vlseg6e64ff.c | 79 +++ .../zvlsseg/unit-stride/wrappers/vlseg6e8.c | 27 + .../zvlsseg/unit-stride/wrappers/vlseg6e8ff.c | 55 ++ .../zvlsseg/unit-stride/wrappers/vlseg7e16.c | 37 ++ .../unit-stride/wrappers/vlseg7e16ff.c | 85 +++ .../zvlsseg/unit-stride/wrappers/vlseg7e32.c | 37 ++ .../unit-stride/wrappers/vlseg7e32ff.c | 85 +++ .../zvlsseg/unit-stride/wrappers/vlseg7e64.c | 37 ++ .../unit-stride/wrappers/vlseg7e64ff.c | 85 +++ .../zvlsseg/unit-stride/wrappers/vlseg7e8.c | 28 + .../zvlsseg/unit-stride/wrappers/vlseg7e8ff.c | 59 +++ .../zvlsseg/unit-stride/wrappers/vlseg8e16.c | 37 ++ .../unit-stride/wrappers/vlseg8e16ff.c | 91 ++++ .../zvlsseg/unit-stride/wrappers/vlseg8e32.c | 37 ++ .../unit-stride/wrappers/vlseg8e32ff.c | 91 ++++ .../zvlsseg/unit-stride/wrappers/vlseg8e64.c | 37 ++ .../unit-stride/wrappers/vlseg8e64ff.c | 91 ++++ .../zvlsseg/unit-stride/wrappers/vlseg8e8.c | 28 + .../zvlsseg/unit-stride/wrappers/vlseg8e8ff.c | 63 +++ .../zvlsseg/unit-stride/wrappers/vsseg2e16.c | 260 ++++++++++ .../zvlsseg/unit-stride/wrappers/vsseg2e32.c | 260 ++++++++++ .../zvlsseg/unit-stride/wrappers/vsseg2e64.c | 260 ++++++++++ .../zvlsseg/unit-stride/wrappers/vsseg2e8.c | 176 +++++++ .../zvlsseg/unit-stride/wrappers/vsseg3e16.c | 200 +++++++ .../zvlsseg/unit-stride/wrappers/vsseg3e32.c | 200 +++++++ .../zvlsseg/unit-stride/wrappers/vsseg3e64.c | 200 +++++++ .../zvlsseg/unit-stride/wrappers/vsseg3e8.c | 136 +++++ .../zvlsseg/unit-stride/wrappers/vsseg4e16.c | 224 ++++++++ .../zvlsseg/unit-stride/wrappers/vsseg4e32.c | 224 ++++++++ .../zvlsseg/unit-stride/wrappers/vsseg4e64.c | 224 ++++++++ .../zvlsseg/unit-stride/wrappers/vsseg4e8.c | 152 ++++++ .../zvlsseg/unit-stride/wrappers/vsseg5e16.c | 128 +++++ .../zvlsseg/unit-stride/wrappers/vsseg5e32.c | 128 +++++ .../zvlsseg/unit-stride/wrappers/vsseg5e64.c | 128 +++++ .../zvlsseg/unit-stride/wrappers/vsseg5e8.c | 88 ++++ .../zvlsseg/unit-stride/wrappers/vsseg6e16.c | 140 +++++ .../zvlsseg/unit-stride/wrappers/vsseg6e32.c | 140 +++++ .../zvlsseg/unit-stride/wrappers/vsseg6e64.c | 140 +++++ .../zvlsseg/unit-stride/wrappers/vsseg6e8.c | 96 ++++ .../zvlsseg/unit-stride/wrappers/vsseg7e16.c | 152 ++++++ .../zvlsseg/unit-stride/wrappers/vsseg7e32.c | 152 ++++++ .../zvlsseg/unit-stride/wrappers/vsseg7e64.c | 152 ++++++ .../zvlsseg/unit-stride/wrappers/vsseg7e8.c | 104 ++++ .../zvlsseg/unit-stride/wrappers/vsseg8e16.c | 164 ++++++ .../zvlsseg/unit-stride/wrappers/vsseg8e32.c | 164 ++++++ .../zvlsseg/unit-stride/wrappers/vsseg8e64.c | 164 ++++++ .../zvlsseg/unit-stride/wrappers/vsseg8e8.c | 112 ++++ 172 files changed, 13914 insertions(+), 91 deletions(-) rename clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/{ => thead}/vlseg2b.c (100%) rename clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/{ => thead}/vlseg2e16.c (100%) rename clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/{ => thead}/vlseg2e16ff.c (100%) rename clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/{ => thead}/vlseg2e32.c (100%) rename clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/{ => thead}/vlseg2e32ff.c (100%) rename clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/{ => thead}/vlseg2e64.c (100%) rename clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/{ => thead}/vlseg2e64ff.c (100%) rename clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/{ => thead}/vlseg2e8.c (100%) rename clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/{ => thead}/vlseg2e8ff.c (100%) rename clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/{ => thead}/vlseg3e16.c (100%) rename clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/{ => thead}/vlseg3e16ff.c (100%) rename clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/{ => thead}/vlseg3e32.c (100%) rename clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/{ => thead}/vlseg3e32ff.c (100%) rename clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/{ => thead}/vlseg3e64.c (100%) rename clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/{ => thead}/vlseg3e64ff.c (100%) rename clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/{ => thead}/vlseg3e8.c (100%) rename clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/{ => thead}/vlseg3e8ff.c (100%) rename clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/{ => thead}/vlseg4e16.c (100%) rename clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/{ => thead}/vlseg4e16ff.c (100%) rename clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/{ => thead}/vlseg4e32.c (100%) rename clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/{ => thead}/vlseg4e32ff.c (100%) rename clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/{ => thead}/vlseg4e64.c (100%) rename clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/{ => thead}/vlseg4e64ff.c (100%) rename clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/{ => thead}/vlseg4e8.c (100%) rename clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/{ => thead}/vlseg4e8ff.c (100%) rename clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/{ => thead}/vlseg5e16.c (100%) rename clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/{ => thead}/vlseg5e16ff.c (100%) rename clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/{ => thead}/vlseg5e32.c (100%) rename clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/{ => thead}/vlseg5e32ff.c (100%) rename clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/{ => thead}/vlseg5e64.c (100%) rename clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/{ => thead}/vlseg5e64ff.c (100%) rename clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/{ => thead}/vlseg5e8.c (100%) rename clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/{ => thead}/vlseg5e8ff.c (100%) rename clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/{ => thead}/vlseg6e16.c (100%) rename clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/{ => thead}/vlseg6e16ff.c (100%) rename clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/{ => thead}/vlseg6e32.c (100%) rename clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/{ => thead}/vlseg6e32ff.c (100%) rename clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/{ => thead}/vlseg6e64.c (100%) rename clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/{ => thead}/vlseg6e64ff.c (100%) rename clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/{ => thead}/vlseg6e8.c (100%) rename clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/{ => thead}/vlseg6e8ff.c (100%) rename clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/{ => thead}/vlseg7e16.c (100%) rename clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/{ => thead}/vlseg7e16ff.c (100%) rename clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/{ => thead}/vlseg7e32.c (100%) rename clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/{ => thead}/vlseg7e32ff.c (100%) rename clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/{ => thead}/vlseg7e64.c (100%) rename clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/{ => thead}/vlseg7e64ff.c (100%) rename clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/{ => thead}/vlseg7e8.c (100%) rename clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/{ => thead}/vlseg7e8ff.c (100%) rename clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/{ => thead}/vlseg8e16.c (100%) rename clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/{ => thead}/vlseg8e16ff.c (100%) rename clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/{ => thead}/vlseg8e32.c (100%) rename clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/{ => thead}/vlseg8e32ff.c (100%) rename clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/{ => thead}/vlseg8e64.c (100%) rename clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/{ => thead}/vlseg8e64ff.c (100%) rename clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/{ => thead}/vlseg8e8.c (100%) rename clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/{ => thead}/vlseg8e8ff.c (100%) create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg2e16.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg2e32.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg2e64.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg2e8.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg3e16.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg3e32.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg3e64.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg3e8.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg4e16.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg4e32.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg4e64.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg4e8.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg5e16.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg5e32.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg5e64.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg5e8.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg6e16.c create mode 100644 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create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg8e64.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg8e8.c delete mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vsseg2e8.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg2b.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg2e16.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg2e16ff.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg2e32.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg2e32ff.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg2e64.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg2e64ff.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg2e8.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg2e8ff.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg3e16.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg3e16ff.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg3e32.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg3e32ff.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg3e64.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg3e64ff.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg3e8.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg3e8ff.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg4e16.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg4e16ff.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg4e32.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg4e32ff.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg4e64.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg4e64ff.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg4e8.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg4e8ff.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg5e16.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg5e16ff.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg5e32.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg5e32ff.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg5e64.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg5e64ff.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg5e8.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg5e8ff.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg6e16.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg6e16ff.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg6e32.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg6e32ff.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg6e64.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg6e64ff.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg6e8.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg6e8ff.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg7e16.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg7e16ff.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg7e32.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg7e32ff.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg7e64.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg7e64ff.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg7e8.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg7e8ff.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg8e16.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg8e16ff.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg8e32.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg8e32ff.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg8e64.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg8e64ff.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg8e8.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg8e8ff.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg2e16.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg2e32.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg2e64.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg2e8.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg3e16.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg3e32.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg3e64.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg3e8.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg4e16.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg4e32.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg4e64.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg4e8.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg5e16.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg5e32.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg5e64.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg5e8.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg6e16.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg6e32.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg6e64.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg6e8.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg7e16.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg7e32.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg7e64.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg7e8.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg8e16.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg8e32.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg8e64.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg8e8.c diff --git a/clang/include/clang/Basic/riscv_vector_xtheadv_wrappers.td b/clang/include/clang/Basic/riscv_vector_xtheadv_wrappers.td index b067aca1aa2b59..8e2dfe1dcfd69a 100644 --- a/clang/include/clang/Basic/riscv_vector_xtheadv_wrappers.td +++ b/clang/include/clang/Basic/riscv_vector_xtheadv_wrappers.td @@ -932,6 +932,496 @@ let HeaderCode = }] in def th_indexed_wrapper_macros: RVVHeader; +let HeaderCode = +[{ +#define __riscv_vlseg2b_v_i8m1x2(base, vl) __riscv_th_vlseg2b_v_i8m1x2(base, vl) +#define __riscv_vlseg2e16_v_f16m1x2(base, vl) __riscv_th_vlseg2e16_v_f16m1x2(base, vl) +#define __riscv_vlseg2e16_v_f16m2x2(base, vl) __riscv_th_vlseg2e16_v_f16m2x2(base, vl) +#define __riscv_vlseg2e16_v_f16m4x2(base, vl) __riscv_th_vlseg2e16_v_f16m4x2(base, vl) +#define __riscv_vlseg2e16_v_i16m1x2(base, vl) __riscv_th_vlseg2e16_v_i16m1x2(base, vl) +#define __riscv_vlseg2e16_v_i16m2x2(base, vl) __riscv_th_vlseg2e16_v_i16m2x2(base, vl) +#define __riscv_vlseg2e16_v_i16m4x2(base, vl) __riscv_th_vlseg2e16_v_i16m4x2(base, vl) +#define __riscv_vlseg2e16_v_u16m1x2(base, vl) __riscv_th_vlseg2e16_v_u16m1x2(base, vl) +#define __riscv_vlseg2e16_v_u16m2x2(base, vl) __riscv_th_vlseg2e16_v_u16m2x2(base, vl) +#define __riscv_vlseg2e16_v_u16m4x2(base, vl) __riscv_th_vlseg2e16_v_u16m4x2(base, vl) +#define __riscv_vlseg2e16ff_v_f16m1x2(base, new_vl, vl) __riscv_th_vlseg2e16ff_v_f16m1x2(base, new_vl, vl) +#define __riscv_vlseg2e16ff_v_f16m2x2(base, new_vl, vl) __riscv_th_vlseg2e16ff_v_f16m2x2(base, new_vl, vl) +#define __riscv_vlseg2e16ff_v_f16m4x2(base, new_vl, vl) __riscv_th_vlseg2e16ff_v_f16m4x2(base, new_vl, vl) +#define __riscv_vlseg2e16ff_v_i16m1x2(base, new_vl, vl) __riscv_th_vlseg2e16ff_v_i16m1x2(base, new_vl, vl) +#define __riscv_vlseg2e16ff_v_i16m2x2(base, new_vl, vl) __riscv_th_vlseg2e16ff_v_i16m2x2(base, new_vl, vl) +#define __riscv_vlseg2e16ff_v_i16m4x2(base, new_vl, vl) __riscv_th_vlseg2e16ff_v_i16m4x2(base, new_vl, vl) +#define __riscv_vlseg2e16ff_v_u16m1x2(base, new_vl, vl) __riscv_th_vlseg2e16ff_v_u16m1x2(base, new_vl, vl) +#define __riscv_vlseg2e16ff_v_u16m2x2(base, new_vl, vl) __riscv_th_vlseg2e16ff_v_u16m2x2(base, new_vl, vl) +#define __riscv_vlseg2e16ff_v_u16m4x2(base, new_vl, vl) __riscv_th_vlseg2e16ff_v_u16m4x2(base, new_vl, vl) +#define __riscv_vlseg2e32_v_f32m1x2(base, vl) __riscv_th_vlseg2e32_v_f32m1x2(base, vl) +#define __riscv_vlseg2e32_v_f32m2x2(base, vl) __riscv_th_vlseg2e32_v_f32m2x2(base, vl) +#define __riscv_vlseg2e32_v_f32m4x2(base, vl) __riscv_th_vlseg2e32_v_f32m4x2(base, vl) +#define __riscv_vlseg2e32_v_i32m1x2(base, vl) __riscv_th_vlseg2e32_v_i32m1x2(base, vl) +#define __riscv_vlseg2e32_v_i32m2x2(base, vl) __riscv_th_vlseg2e32_v_i32m2x2(base, vl) +#define __riscv_vlseg2e32_v_i32m4x2(base, vl) __riscv_th_vlseg2e32_v_i32m4x2(base, vl) +#define __riscv_vlseg2e32_v_u32m1x2(base, vl) __riscv_th_vlseg2e32_v_u32m1x2(base, vl) +#define __riscv_vlseg2e32_v_u32m2x2(base, vl) __riscv_th_vlseg2e32_v_u32m2x2(base, vl) +#define __riscv_vlseg2e32_v_u32m4x2(base, vl) __riscv_th_vlseg2e32_v_u32m4x2(base, vl) +#define __riscv_vlseg2e32ff_v_f32m1x2(base, new_vl, vl) __riscv_th_vlseg2e32ff_v_f32m1x2(base, new_vl, vl) +#define __riscv_vlseg2e32ff_v_f32m2x2(base, new_vl, vl) __riscv_th_vlseg2e32ff_v_f32m2x2(base, new_vl, vl) +#define __riscv_vlseg2e32ff_v_f32m4x2(base, new_vl, vl) __riscv_th_vlseg2e32ff_v_f32m4x2(base, new_vl, vl) +#define __riscv_vlseg2e32ff_v_i32m1x2(base, new_vl, vl) __riscv_th_vlseg2e32ff_v_i32m1x2(base, new_vl, vl) +#define __riscv_vlseg2e32ff_v_i32m2x2(base, new_vl, vl) __riscv_th_vlseg2e32ff_v_i32m2x2(base, new_vl, vl) +#define __riscv_vlseg2e32ff_v_i32m4x2(base, new_vl, vl) __riscv_th_vlseg2e32ff_v_i32m4x2(base, new_vl, vl) +#define __riscv_vlseg2e32ff_v_u32m1x2(base, new_vl, vl) __riscv_th_vlseg2e32ff_v_u32m1x2(base, new_vl, vl) +#define __riscv_vlseg2e32ff_v_u32m2x2(base, new_vl, vl) __riscv_th_vlseg2e32ff_v_u32m2x2(base, new_vl, vl) +#define __riscv_vlseg2e32ff_v_u32m4x2(base, new_vl, vl) __riscv_th_vlseg2e32ff_v_u32m4x2(base, new_vl, vl) +#define __riscv_vlseg2e64_v_f64m1x2(base, vl) __riscv_th_vlseg2e64_v_f64m1x2(base, vl) +#define __riscv_vlseg2e64_v_f64m2x2(base, vl) __riscv_th_vlseg2e64_v_f64m2x2(base, vl) +#define __riscv_vlseg2e64_v_f64m4x2(base, vl) __riscv_th_vlseg2e64_v_f64m4x2(base, vl) +#define __riscv_vlseg2e64_v_i64m1x2(base, vl) __riscv_th_vlseg2e64_v_i64m1x2(base, vl) +#define __riscv_vlseg2e64_v_i64m2x2(base, vl) __riscv_th_vlseg2e64_v_i64m2x2(base, vl) +#define __riscv_vlseg2e64_v_i64m4x2(base, vl) __riscv_th_vlseg2e64_v_i64m4x2(base, vl) +#define __riscv_vlseg2e64_v_u64m1x2(base, vl) __riscv_th_vlseg2e64_v_u64m1x2(base, vl) +#define __riscv_vlseg2e64_v_u64m2x2(base, vl) __riscv_th_vlseg2e64_v_u64m2x2(base, vl) +#define __riscv_vlseg2e64_v_u64m4x2(base, vl) __riscv_th_vlseg2e64_v_u64m4x2(base, vl) +#define __riscv_vlseg2e64ff_v_f64m1x2(base, new_vl, vl) __riscv_th_vlseg2e64ff_v_f64m1x2(base, new_vl, vl) +#define __riscv_vlseg2e64ff_v_f64m2x2(base, new_vl, vl) __riscv_th_vlseg2e64ff_v_f64m2x2(base, new_vl, vl) +#define __riscv_vlseg2e64ff_v_f64m4x2(base, new_vl, vl) __riscv_th_vlseg2e64ff_v_f64m4x2(base, new_vl, vl) +#define __riscv_vlseg2e64ff_v_i64m1x2(base, new_vl, vl) __riscv_th_vlseg2e64ff_v_i64m1x2(base, new_vl, vl) +#define __riscv_vlseg2e64ff_v_i64m2x2(base, new_vl, vl) __riscv_th_vlseg2e64ff_v_i64m2x2(base, new_vl, vl) +#define __riscv_vlseg2e64ff_v_i64m4x2(base, new_vl, vl) __riscv_th_vlseg2e64ff_v_i64m4x2(base, new_vl, vl) +#define __riscv_vlseg2e64ff_v_u64m1x2(base, new_vl, vl) __riscv_th_vlseg2e64ff_v_u64m1x2(base, new_vl, vl) +#define __riscv_vlseg2e64ff_v_u64m2x2(base, new_vl, vl) __riscv_th_vlseg2e64ff_v_u64m2x2(base, new_vl, vl) +#define __riscv_vlseg2e64ff_v_u64m4x2(base, new_vl, vl) __riscv_th_vlseg2e64ff_v_u64m4x2(base, new_vl, vl) +#define __riscv_vlseg2e8_v_i8m1x2(base, vl) __riscv_th_vlseg2e8_v_i8m1x2(base, vl) +#define __riscv_vlseg2e8_v_i8m2x2(base, vl) __riscv_th_vlseg2e8_v_i8m2x2(base, vl) +#define __riscv_vlseg2e8_v_i8m4x2(base, vl) __riscv_th_vlseg2e8_v_i8m4x2(base, vl) +#define __riscv_vlseg2e8_v_u8m1x2(base, vl) __riscv_th_vlseg2e8_v_u8m1x2(base, vl) +#define __riscv_vlseg2e8_v_u8m2x2(base, vl) __riscv_th_vlseg2e8_v_u8m2x2(base, vl) +#define __riscv_vlseg2e8_v_u8m4x2(base, vl) __riscv_th_vlseg2e8_v_u8m4x2(base, vl) +#define __riscv_vlseg2e8ff_v_i8m1x2(base, new_vl, vl) __riscv_th_vlseg2e8ff_v_i8m1x2(base, new_vl, vl) +#define __riscv_vlseg2e8ff_v_i8m2x2(base, new_vl, vl) __riscv_th_vlseg2e8ff_v_i8m2x2(base, new_vl, vl) +#define __riscv_vlseg2e8ff_v_i8m4x2(base, new_vl, vl) __riscv_th_vlseg2e8ff_v_i8m4x2(base, new_vl, vl) +#define __riscv_vlseg2e8ff_v_u8m1x2(base, new_vl, vl) __riscv_th_vlseg2e8ff_v_u8m1x2(base, new_vl, vl) +#define __riscv_vlseg2e8ff_v_u8m2x2(base, new_vl, vl) __riscv_th_vlseg2e8ff_v_u8m2x2(base, new_vl, vl) +#define __riscv_vlseg2e8ff_v_u8m4x2(base, new_vl, vl) __riscv_th_vlseg2e8ff_v_u8m4x2(base, new_vl, vl) +#define __riscv_vlseg3e16_v_f16m1x3(base, vl) __riscv_th_vlseg3e16_v_f16m1x3(base, vl) +#define __riscv_vlseg3e16_v_f16m2x3(base, vl) __riscv_th_vlseg3e16_v_f16m2x3(base, vl) +#define __riscv_vlseg3e16_v_i16m1x3(base, vl) __riscv_th_vlseg3e16_v_i16m1x3(base, vl) +#define __riscv_vlseg3e16_v_i16m2x3(base, vl) __riscv_th_vlseg3e16_v_i16m2x3(base, vl) +#define __riscv_vlseg3e16_v_u16m1x3(base, vl) __riscv_th_vlseg3e16_v_u16m1x3(base, vl) +#define __riscv_vlseg3e16_v_u16m2x3(base, vl) __riscv_th_vlseg3e16_v_u16m2x3(base, vl) +#define __riscv_vlseg3e16ff_v_f16m1x3(base, new_vl, vl) __riscv_th_vlseg3e16ff_v_f16m1x3(base, new_vl, vl) +#define __riscv_vlseg3e16ff_v_f16m2x3(base, new_vl, vl) __riscv_th_vlseg3e16ff_v_f16m2x3(base, new_vl, vl) +#define __riscv_vlseg3e16ff_v_i16m1x3(base, new_vl, vl) __riscv_th_vlseg3e16ff_v_i16m1x3(base, new_vl, vl) +#define __riscv_vlseg3e16ff_v_i16m2x3(base, new_vl, vl) __riscv_th_vlseg3e16ff_v_i16m2x3(base, new_vl, vl) +#define __riscv_vlseg3e16ff_v_u16m1x3(base, new_vl, vl) __riscv_th_vlseg3e16ff_v_u16m1x3(base, new_vl, vl) +#define __riscv_vlseg3e16ff_v_u16m2x3(base, new_vl, vl) __riscv_th_vlseg3e16ff_v_u16m2x3(base, new_vl, vl) +#define __riscv_vlseg3e32_v_f32m1x3(base, vl) __riscv_th_vlseg3e32_v_f32m1x3(base, vl) +#define __riscv_vlseg3e32_v_f32m2x3(base, vl) __riscv_th_vlseg3e32_v_f32m2x3(base, vl) +#define __riscv_vlseg3e32_v_i32m1x3(base, vl) __riscv_th_vlseg3e32_v_i32m1x3(base, vl) +#define __riscv_vlseg3e32_v_i32m2x3(base, vl) __riscv_th_vlseg3e32_v_i32m2x3(base, vl) +#define __riscv_vlseg3e32_v_u32m1x3(base, vl) __riscv_th_vlseg3e32_v_u32m1x3(base, vl) +#define __riscv_vlseg3e32_v_u32m2x3(base, vl) __riscv_th_vlseg3e32_v_u32m2x3(base, vl) +#define __riscv_vlseg3e32ff_v_f32m1x3(base, new_vl, vl) __riscv_th_vlseg3e32ff_v_f32m1x3(base, new_vl, vl) +#define __riscv_vlseg3e32ff_v_f32m2x3(base, new_vl, vl) __riscv_th_vlseg3e32ff_v_f32m2x3(base, new_vl, vl) +#define __riscv_vlseg3e32ff_v_i32m1x3(base, new_vl, vl) __riscv_th_vlseg3e32ff_v_i32m1x3(base, new_vl, vl) +#define __riscv_vlseg3e32ff_v_i32m2x3(base, new_vl, vl) __riscv_th_vlseg3e32ff_v_i32m2x3(base, new_vl, vl) +#define __riscv_vlseg3e32ff_v_u32m1x3(base, new_vl, vl) __riscv_th_vlseg3e32ff_v_u32m1x3(base, new_vl, vl) +#define __riscv_vlseg3e32ff_v_u32m2x3(base, new_vl, vl) __riscv_th_vlseg3e32ff_v_u32m2x3(base, new_vl, vl) +#define __riscv_vlseg3e64_v_f64m1x3(base, vl) __riscv_th_vlseg3e64_v_f64m1x3(base, vl) +#define __riscv_vlseg3e64_v_f64m2x3(base, vl) __riscv_th_vlseg3e64_v_f64m2x3(base, vl) +#define __riscv_vlseg3e64_v_i64m1x3(base, vl) __riscv_th_vlseg3e64_v_i64m1x3(base, vl) +#define __riscv_vlseg3e64_v_i64m2x3(base, vl) __riscv_th_vlseg3e64_v_i64m2x3(base, vl) +#define __riscv_vlseg3e64_v_u64m1x3(base, vl) __riscv_th_vlseg3e64_v_u64m1x3(base, vl) +#define __riscv_vlseg3e64_v_u64m2x3(base, vl) __riscv_th_vlseg3e64_v_u64m2x3(base, vl) +#define __riscv_vlseg3e64ff_v_f64m1x3(base, new_vl, vl) __riscv_th_vlseg3e64ff_v_f64m1x3(base, new_vl, vl) +#define __riscv_vlseg3e64ff_v_f64m2x3(base, new_vl, vl) __riscv_th_vlseg3e64ff_v_f64m2x3(base, new_vl, vl) +#define __riscv_vlseg3e64ff_v_i64m1x3(base, new_vl, vl) __riscv_th_vlseg3e64ff_v_i64m1x3(base, new_vl, vl) +#define __riscv_vlseg3e64ff_v_i64m2x3(base, new_vl, vl) __riscv_th_vlseg3e64ff_v_i64m2x3(base, new_vl, vl) +#define __riscv_vlseg3e64ff_v_u64m1x3(base, new_vl, vl) __riscv_th_vlseg3e64ff_v_u64m1x3(base, new_vl, vl) +#define __riscv_vlseg3e64ff_v_u64m2x3(base, new_vl, vl) __riscv_th_vlseg3e64ff_v_u64m2x3(base, new_vl, vl) +#define __riscv_vlseg3e8_v_i8m1x3(base, vl) __riscv_th_vlseg3e8_v_i8m1x3(base, vl) +#define __riscv_vlseg3e8_v_i8m2x3(base, vl) __riscv_th_vlseg3e8_v_i8m2x3(base, vl) +#define __riscv_vlseg3e8_v_u8m1x3(base, vl) __riscv_th_vlseg3e8_v_u8m1x3(base, vl) +#define __riscv_vlseg3e8_v_u8m2x3(base, vl) __riscv_th_vlseg3e8_v_u8m2x3(base, vl) +#define __riscv_vlseg3e8ff_v_i8m1x3(base, new_vl, vl) __riscv_th_vlseg3e8ff_v_i8m1x3(base, new_vl, vl) +#define __riscv_vlseg3e8ff_v_i8m2x3(base, new_vl, vl) __riscv_th_vlseg3e8ff_v_i8m2x3(base, new_vl, vl) +#define __riscv_vlseg3e8ff_v_u8m1x3(base, new_vl, vl) __riscv_th_vlseg3e8ff_v_u8m1x3(base, new_vl, vl) +#define __riscv_vlseg3e8ff_v_u8m2x3(base, new_vl, vl) __riscv_th_vlseg3e8ff_v_u8m2x3(base, new_vl, vl) +#define __riscv_vlseg4e16_v_f16m1x4(base, vl) __riscv_th_vlseg4e16_v_f16m1x4(base, vl) +#define __riscv_vlseg4e16_v_f16m2x4(base, vl) __riscv_th_vlseg4e16_v_f16m2x4(base, vl) +#define __riscv_vlseg4e16_v_i16m1x4(base, vl) __riscv_th_vlseg4e16_v_i16m1x4(base, vl) +#define __riscv_vlseg4e16_v_i16m2x4(base, vl) __riscv_th_vlseg4e16_v_i16m2x4(base, vl) +#define __riscv_vlseg4e16_v_u16m1x4(base, vl) __riscv_th_vlseg4e16_v_u16m1x4(base, vl) +#define __riscv_vlseg4e16_v_u16m2x4(base, vl) __riscv_th_vlseg4e16_v_u16m2x4(base, vl) +#define __riscv_vlseg4e16ff_v_f16m1x4(base, new_vl, vl) __riscv_th_vlseg4e16ff_v_f16m1x4(base, new_vl, vl) +#define __riscv_vlseg4e16ff_v_f16m2x4(base, new_vl, vl) __riscv_th_vlseg4e16ff_v_f16m2x4(base, new_vl, vl) +#define __riscv_vlseg4e16ff_v_i16m1x4(base, new_vl, vl) __riscv_th_vlseg4e16ff_v_i16m1x4(base, new_vl, vl) +#define __riscv_vlseg4e16ff_v_i16m2x4(base, new_vl, vl) __riscv_th_vlseg4e16ff_v_i16m2x4(base, new_vl, vl) +#define __riscv_vlseg4e16ff_v_u16m1x4(base, new_vl, vl) __riscv_th_vlseg4e16ff_v_u16m1x4(base, new_vl, vl) +#define __riscv_vlseg4e16ff_v_u16m2x4(base, new_vl, vl) __riscv_th_vlseg4e16ff_v_u16m2x4(base, new_vl, vl) +#define __riscv_vlseg4e32_v_f32m1x4(base, vl) __riscv_th_vlseg4e32_v_f32m1x4(base, vl) +#define __riscv_vlseg4e32_v_f32m2x4(base, vl) __riscv_th_vlseg4e32_v_f32m2x4(base, vl) +#define __riscv_vlseg4e32_v_i32m1x4(base, vl) __riscv_th_vlseg4e32_v_i32m1x4(base, vl) +#define __riscv_vlseg4e32_v_i32m2x4(base, vl) __riscv_th_vlseg4e32_v_i32m2x4(base, vl) +#define __riscv_vlseg4e32_v_u32m1x4(base, vl) __riscv_th_vlseg4e32_v_u32m1x4(base, vl) +#define __riscv_vlseg4e32_v_u32m2x4(base, vl) __riscv_th_vlseg4e32_v_u32m2x4(base, vl) +#define __riscv_vlseg4e32ff_v_f32m1x4(base, new_vl, vl) __riscv_th_vlseg4e32ff_v_f32m1x4(base, new_vl, vl) +#define __riscv_vlseg4e32ff_v_f32m2x4(base, new_vl, vl) __riscv_th_vlseg4e32ff_v_f32m2x4(base, new_vl, vl) +#define __riscv_vlseg4e32ff_v_i32m1x4(base, new_vl, vl) __riscv_th_vlseg4e32ff_v_i32m1x4(base, new_vl, vl) +#define __riscv_vlseg4e32ff_v_i32m2x4(base, new_vl, vl) __riscv_th_vlseg4e32ff_v_i32m2x4(base, new_vl, vl) +#define __riscv_vlseg4e32ff_v_u32m1x4(base, new_vl, vl) __riscv_th_vlseg4e32ff_v_u32m1x4(base, new_vl, vl) +#define __riscv_vlseg4e32ff_v_u32m2x4(base, new_vl, vl) __riscv_th_vlseg4e32ff_v_u32m2x4(base, new_vl, vl) +#define __riscv_vlseg4e64_v_f64m1x4(base, vl) __riscv_th_vlseg4e64_v_f64m1x4(base, vl) +#define __riscv_vlseg4e64_v_f64m2x4(base, vl) __riscv_th_vlseg4e64_v_f64m2x4(base, vl) +#define __riscv_vlseg4e64_v_i64m1x4(base, vl) __riscv_th_vlseg4e64_v_i64m1x4(base, vl) +#define __riscv_vlseg4e64_v_i64m2x4(base, vl) __riscv_th_vlseg4e64_v_i64m2x4(base, vl) +#define __riscv_vlseg4e64_v_u64m1x4(base, vl) __riscv_th_vlseg4e64_v_u64m1x4(base, vl) +#define __riscv_vlseg4e64_v_u64m2x4(base, vl) __riscv_th_vlseg4e64_v_u64m2x4(base, vl) +#define __riscv_vlseg4e64ff_v_f64m1x4(base, new_vl, vl) __riscv_th_vlseg4e64ff_v_f64m1x4(base, new_vl, vl) +#define __riscv_vlseg4e64ff_v_f64m2x4(base, new_vl, vl) __riscv_th_vlseg4e64ff_v_f64m2x4(base, new_vl, vl) +#define __riscv_vlseg4e64ff_v_i64m1x4(base, new_vl, vl) __riscv_th_vlseg4e64ff_v_i64m1x4(base, new_vl, vl) +#define __riscv_vlseg4e64ff_v_i64m2x4(base, new_vl, vl) __riscv_th_vlseg4e64ff_v_i64m2x4(base, new_vl, vl) +#define __riscv_vlseg4e64ff_v_u64m1x4(base, new_vl, vl) __riscv_th_vlseg4e64ff_v_u64m1x4(base, new_vl, vl) +#define __riscv_vlseg4e64ff_v_u64m2x4(base, new_vl, vl) __riscv_th_vlseg4e64ff_v_u64m2x4(base, new_vl, vl) +#define __riscv_vlseg4e8_v_i8m1x4(base, vl) __riscv_th_vlseg4e8_v_i8m1x4(base, vl) +#define __riscv_vlseg4e8_v_i8m2x4(base, vl) __riscv_th_vlseg4e8_v_i8m2x4(base, vl) +#define __riscv_vlseg4e8_v_u8m1x4(base, vl) __riscv_th_vlseg4e8_v_u8m1x4(base, vl) +#define __riscv_vlseg4e8_v_u8m2x4(base, vl) __riscv_th_vlseg4e8_v_u8m2x4(base, vl) +#define __riscv_vlseg4e8ff_v_i8m1x4(base, new_vl, vl) __riscv_th_vlseg4e8ff_v_i8m1x4(base, new_vl, vl) +#define __riscv_vlseg4e8ff_v_i8m2x4(base, new_vl, vl) __riscv_th_vlseg4e8ff_v_i8m2x4(base, new_vl, vl) +#define __riscv_vlseg4e8ff_v_u8m1x4(base, new_vl, vl) __riscv_th_vlseg4e8ff_v_u8m1x4(base, new_vl, vl) +#define __riscv_vlseg4e8ff_v_u8m2x4(base, new_vl, vl) __riscv_th_vlseg4e8ff_v_u8m2x4(base, new_vl, vl) +#define __riscv_vlseg5e16_v_f16m1x5(base, vl) __riscv_th_vlseg5e16_v_f16m1x5(base, vl) +#define __riscv_vlseg5e16_v_i16m1x5(base, vl) __riscv_th_vlseg5e16_v_i16m1x5(base, vl) +#define __riscv_vlseg5e16_v_u16m1x5(base, vl) __riscv_th_vlseg5e16_v_u16m1x5(base, vl) +#define __riscv_vlseg5e16ff_v_f16m1x5(base, new_vl, vl) __riscv_th_vlseg5e16ff_v_f16m1x5(base, new_vl, vl) +#define __riscv_vlseg5e16ff_v_i16m1x5(base, new_vl, vl) __riscv_th_vlseg5e16ff_v_i16m1x5(base, new_vl, vl) +#define __riscv_vlseg5e16ff_v_u16m1x5(base, new_vl, vl) __riscv_th_vlseg5e16ff_v_u16m1x5(base, new_vl, vl) +#define __riscv_vlseg5e32_v_f32m1x5(base, vl) __riscv_th_vlseg5e32_v_f32m1x5(base, vl) +#define __riscv_vlseg5e32_v_i32m1x5(base, vl) __riscv_th_vlseg5e32_v_i32m1x5(base, vl) +#define __riscv_vlseg5e32_v_u32m1x5(base, vl) __riscv_th_vlseg5e32_v_u32m1x5(base, vl) +#define __riscv_vlseg5e32ff_v_f32m1x5(base, new_vl, vl) __riscv_th_vlseg5e32ff_v_f32m1x5(base, new_vl, vl) +#define __riscv_vlseg5e32ff_v_i32m1x5(base, new_vl, vl) __riscv_th_vlseg5e32ff_v_i32m1x5(base, new_vl, vl) +#define __riscv_vlseg5e32ff_v_u32m1x5(base, new_vl, vl) __riscv_th_vlseg5e32ff_v_u32m1x5(base, new_vl, vl) +#define __riscv_vlseg5e64_v_f64m1x5(base, vl) __riscv_th_vlseg5e64_v_f64m1x5(base, vl) +#define __riscv_vlseg5e64_v_i64m1x5(base, vl) __riscv_th_vlseg5e64_v_i64m1x5(base, vl) +#define __riscv_vlseg5e64_v_u64m1x5(base, vl) __riscv_th_vlseg5e64_v_u64m1x5(base, vl) +#define __riscv_vlseg5e64ff_v_f64m1x5(base, new_vl, vl) __riscv_th_vlseg5e64ff_v_f64m1x5(base, new_vl, vl) +#define __riscv_vlseg5e64ff_v_i64m1x5(base, new_vl, vl) __riscv_th_vlseg5e64ff_v_i64m1x5(base, new_vl, vl) +#define __riscv_vlseg5e64ff_v_u64m1x5(base, new_vl, vl) __riscv_th_vlseg5e64ff_v_u64m1x5(base, new_vl, vl) +#define __riscv_vlseg5e8_v_i8m1x5(base, vl) __riscv_th_vlseg5e8_v_i8m1x5(base, vl) +#define __riscv_vlseg5e8_v_u8m1x5(base, vl) __riscv_th_vlseg5e8_v_u8m1x5(base, vl) +#define __riscv_vlseg5e8ff_v_i8m1x5(base, new_vl, vl) __riscv_th_vlseg5e8ff_v_i8m1x5(base, new_vl, vl) +#define __riscv_vlseg5e8ff_v_u8m1x5(base, new_vl, vl) __riscv_th_vlseg5e8ff_v_u8m1x5(base, new_vl, vl) +#define __riscv_vlseg6e16_v_f16m1x6(base, vl) __riscv_th_vlseg6e16_v_f16m1x6(base, vl) +#define __riscv_vlseg6e16_v_i16m1x6(base, vl) __riscv_th_vlseg6e16_v_i16m1x6(base, vl) +#define __riscv_vlseg6e16_v_u16m1x6(base, vl) __riscv_th_vlseg6e16_v_u16m1x6(base, vl) +#define __riscv_vlseg6e16ff_v_f16m1x6(base, new_vl, vl) __riscv_th_vlseg6e16ff_v_f16m1x6(base, new_vl, vl) +#define __riscv_vlseg6e16ff_v_i16m1x6(base, new_vl, vl) __riscv_th_vlseg6e16ff_v_i16m1x6(base, new_vl, vl) +#define __riscv_vlseg6e16ff_v_u16m1x6(base, new_vl, vl) __riscv_th_vlseg6e16ff_v_u16m1x6(base, new_vl, vl) +#define __riscv_vlseg6e32_v_f32m1x6(base, vl) __riscv_th_vlseg6e32_v_f32m1x6(base, vl) +#define __riscv_vlseg6e32_v_i32m1x6(base, vl) __riscv_th_vlseg6e32_v_i32m1x6(base, vl) +#define __riscv_vlseg6e32_v_u32m1x6(base, vl) __riscv_th_vlseg6e32_v_u32m1x6(base, vl) +#define __riscv_vlseg6e32ff_v_f32m1x6(base, new_vl, vl) __riscv_th_vlseg6e32ff_v_f32m1x6(base, new_vl, vl) +#define __riscv_vlseg6e32ff_v_i32m1x6(base, new_vl, vl) __riscv_th_vlseg6e32ff_v_i32m1x6(base, new_vl, vl) +#define __riscv_vlseg6e32ff_v_u32m1x6(base, new_vl, vl) __riscv_th_vlseg6e32ff_v_u32m1x6(base, new_vl, vl) +#define __riscv_vlseg6e64_v_f64m1x6(base, vl) __riscv_th_vlseg6e64_v_f64m1x6(base, vl) +#define __riscv_vlseg6e64_v_i64m1x6(base, vl) __riscv_th_vlseg6e64_v_i64m1x6(base, vl) +#define __riscv_vlseg6e64_v_u64m1x6(base, vl) __riscv_th_vlseg6e64_v_u64m1x6(base, vl) +#define __riscv_vlseg6e64ff_v_f64m1x6(base, new_vl, vl) __riscv_th_vlseg6e64ff_v_f64m1x6(base, new_vl, vl) +#define __riscv_vlseg6e64ff_v_i64m1x6(base, new_vl, vl) __riscv_th_vlseg6e64ff_v_i64m1x6(base, new_vl, vl) +#define __riscv_vlseg6e64ff_v_u64m1x6(base, new_vl, vl) __riscv_th_vlseg6e64ff_v_u64m1x6(base, new_vl, vl) +#define __riscv_vlseg6e8_v_i8m1x6(base, vl) __riscv_th_vlseg6e8_v_i8m1x6(base, vl) +#define __riscv_vlseg6e8_v_u8m1x6(base, vl) __riscv_th_vlseg6e8_v_u8m1x6(base, vl) +#define __riscv_vlseg6e8ff_v_i8m1x6(base, new_vl, vl) __riscv_th_vlseg6e8ff_v_i8m1x6(base, new_vl, vl) +#define __riscv_vlseg6e8ff_v_u8m1x6(base, new_vl, vl) __riscv_th_vlseg6e8ff_v_u8m1x6(base, new_vl, vl) +#define __riscv_vlseg7e16_v_f16m1x7(base, vl) __riscv_th_vlseg7e16_v_f16m1x7(base, vl) +#define __riscv_vlseg7e16_v_i16m1x7(base, vl) __riscv_th_vlseg7e16_v_i16m1x7(base, vl) +#define __riscv_vlseg7e16_v_u16m1x7(base, vl) __riscv_th_vlseg7e16_v_u16m1x7(base, vl) +#define __riscv_vlseg7e16ff_v_f16m1x7(base, new_vl, vl) __riscv_th_vlseg7e16ff_v_f16m1x7(base, new_vl, vl) +#define __riscv_vlseg7e16ff_v_i16m1x7(base, new_vl, vl) __riscv_th_vlseg7e16ff_v_i16m1x7(base, new_vl, vl) +#define __riscv_vlseg7e16ff_v_u16m1x7(base, new_vl, vl) __riscv_th_vlseg7e16ff_v_u16m1x7(base, new_vl, vl) +#define __riscv_vlseg7e32_v_f32m1x7(base, vl) __riscv_th_vlseg7e32_v_f32m1x7(base, vl) +#define __riscv_vlseg7e32_v_i32m1x7(base, vl) __riscv_th_vlseg7e32_v_i32m1x7(base, vl) +#define __riscv_vlseg7e32_v_u32m1x7(base, vl) __riscv_th_vlseg7e32_v_u32m1x7(base, vl) +#define __riscv_vlseg7e32ff_v_f32m1x7(base, new_vl, vl) __riscv_th_vlseg7e32ff_v_f32m1x7(base, new_vl, vl) +#define __riscv_vlseg7e32ff_v_i32m1x7(base, new_vl, vl) __riscv_th_vlseg7e32ff_v_i32m1x7(base, new_vl, vl) +#define __riscv_vlseg7e32ff_v_u32m1x7(base, new_vl, vl) __riscv_th_vlseg7e32ff_v_u32m1x7(base, new_vl, vl) +#define __riscv_vlseg7e64_v_f64m1x7(base, vl) __riscv_th_vlseg7e64_v_f64m1x7(base, vl) +#define __riscv_vlseg7e64_v_i64m1x7(base, vl) __riscv_th_vlseg7e64_v_i64m1x7(base, vl) +#define __riscv_vlseg7e64_v_u64m1x7(base, vl) __riscv_th_vlseg7e64_v_u64m1x7(base, vl) +#define __riscv_vlseg7e64ff_v_f64m1x7(base, new_vl, vl) __riscv_th_vlseg7e64ff_v_f64m1x7(base, new_vl, vl) +#define __riscv_vlseg7e64ff_v_i64m1x7(base, new_vl, vl) __riscv_th_vlseg7e64ff_v_i64m1x7(base, new_vl, vl) +#define __riscv_vlseg7e64ff_v_u64m1x7(base, new_vl, vl) __riscv_th_vlseg7e64ff_v_u64m1x7(base, new_vl, vl) +#define __riscv_vlseg7e8_v_i8m1x7(base, vl) __riscv_th_vlseg7e8_v_i8m1x7(base, vl) +#define __riscv_vlseg7e8_v_u8m1x7(base, vl) __riscv_th_vlseg7e8_v_u8m1x7(base, vl) +#define __riscv_vlseg7e8ff_v_i8m1x7(base, new_vl, vl) __riscv_th_vlseg7e8ff_v_i8m1x7(base, new_vl, vl) +#define __riscv_vlseg7e8ff_v_u8m1x7(base, new_vl, vl) __riscv_th_vlseg7e8ff_v_u8m1x7(base, new_vl, vl) +#define __riscv_vlseg8e16_v_f16m1x8(base, vl) __riscv_th_vlseg8e16_v_f16m1x8(base, vl) +#define __riscv_vlseg8e16_v_i16m1x8(base, vl) __riscv_th_vlseg8e16_v_i16m1x8(base, vl) +#define __riscv_vlseg8e16_v_u16m1x8(base, vl) __riscv_th_vlseg8e16_v_u16m1x8(base, vl) +#define __riscv_vlseg8e16ff_v_f16m1x8(base, new_vl, vl) __riscv_th_vlseg8e16ff_v_f16m1x8(base, new_vl, vl) +#define __riscv_vlseg8e16ff_v_i16m1x8(base, new_vl, vl) __riscv_th_vlseg8e16ff_v_i16m1x8(base, new_vl, vl) +#define __riscv_vlseg8e16ff_v_u16m1x8(base, new_vl, vl) __riscv_th_vlseg8e16ff_v_u16m1x8(base, new_vl, vl) +#define __riscv_vlseg8e32_v_f32m1x8(base, vl) __riscv_th_vlseg8e32_v_f32m1x8(base, vl) +#define __riscv_vlseg8e32_v_i32m1x8(base, vl) __riscv_th_vlseg8e32_v_i32m1x8(base, vl) +#define __riscv_vlseg8e32_v_u32m1x8(base, vl) __riscv_th_vlseg8e32_v_u32m1x8(base, vl) +#define __riscv_vlseg8e32ff_v_f32m1x8(base, new_vl, vl) __riscv_th_vlseg8e32ff_v_f32m1x8(base, new_vl, vl) +#define __riscv_vlseg8e32ff_v_i32m1x8(base, new_vl, vl) __riscv_th_vlseg8e32ff_v_i32m1x8(base, new_vl, vl) +#define __riscv_vlseg8e32ff_v_u32m1x8(base, new_vl, vl) __riscv_th_vlseg8e32ff_v_u32m1x8(base, new_vl, vl) +#define __riscv_vlseg8e64_v_f64m1x8(base, vl) __riscv_th_vlseg8e64_v_f64m1x8(base, vl) +#define __riscv_vlseg8e64_v_i64m1x8(base, vl) __riscv_th_vlseg8e64_v_i64m1x8(base, vl) +#define __riscv_vlseg8e64_v_u64m1x8(base, vl) __riscv_th_vlseg8e64_v_u64m1x8(base, vl) +#define __riscv_vlseg8e64ff_v_f64m1x8(base, new_vl, vl) __riscv_th_vlseg8e64ff_v_f64m1x8(base, new_vl, vl) +#define __riscv_vlseg8e64ff_v_i64m1x8(base, new_vl, vl) __riscv_th_vlseg8e64ff_v_i64m1x8(base, new_vl, vl) +#define __riscv_vlseg8e64ff_v_u64m1x8(base, new_vl, vl) __riscv_th_vlseg8e64ff_v_u64m1x8(base, new_vl, vl) +#define __riscv_vlseg8e8_v_i8m1x8(base, vl) __riscv_th_vlseg8e8_v_i8m1x8(base, vl) +#define __riscv_vlseg8e8_v_u8m1x8(base, vl) __riscv_th_vlseg8e8_v_u8m1x8(base, vl) +#define __riscv_vlseg8e8ff_v_i8m1x8(base, new_vl, vl) __riscv_th_vlseg8e8ff_v_i8m1x8(base, new_vl, vl) +#define __riscv_vlseg8e8ff_v_u8m1x8(base, new_vl, vl) __riscv_th_vlseg8e8ff_v_u8m1x8(base, new_vl, vl) +#define __riscv_vsseg2e16_v_f16m1x2(base, v_tuple, vl) __riscv_th_vsseg2e16_v_f16m1x2(base, v_tuple, vl) +#define __riscv_vsseg2e16_v_f16m2x2(base, v_tuple, vl) __riscv_th_vsseg2e16_v_f16m2x2(base, v_tuple, vl) +#define __riscv_vsseg2e16_v_f16m4x2(base, v_tuple, vl) __riscv_th_vsseg2e16_v_f16m4x2(base, v_tuple, vl) +#define __riscv_vsseg2e16_v_i16m1x2(base, v_tuple, vl) __riscv_th_vsseg2e16_v_i16m1x2(base, v_tuple, vl) +#define __riscv_vsseg2e16_v_i16m2x2(base, v_tuple, vl) __riscv_th_vsseg2e16_v_i16m2x2(base, v_tuple, vl) +#define __riscv_vsseg2e16_v_i16m4x2(base, v_tuple, vl) __riscv_th_vsseg2e16_v_i16m4x2(base, v_tuple, vl) +#define __riscv_vsseg2e16_v_u16m1x2(base, v_tuple, vl) __riscv_th_vsseg2e16_v_u16m1x2(base, v_tuple, vl) +#define __riscv_vsseg2e16_v_u16m2x2(base, v_tuple, vl) __riscv_th_vsseg2e16_v_u16m2x2(base, v_tuple, vl) +#define __riscv_vsseg2e16_v_u16m4x2(base, v_tuple, vl) __riscv_th_vsseg2e16_v_u16m4x2(base, v_tuple, vl) +#define __riscv_vsseg2e16_v_f16m1x2_m(mask, base, v_tuple, vl) __riscv_th_vsseg2e16_v_f16m1x2_m(mask, base, v_tuple, vl) +#define __riscv_vsseg2e16_v_f16m2x2_m(mask, base, v_tuple, vl) __riscv_th_vsseg2e16_v_f16m2x2_m(mask, base, v_tuple, vl) +#define __riscv_vsseg2e16_v_f16m4x2_m(mask, base, v_tuple, vl) __riscv_th_vsseg2e16_v_f16m4x2_m(mask, base, v_tuple, vl) +#define __riscv_vsseg2e16_v_i16m1x2_m(mask, base, v_tuple, vl) __riscv_th_vsseg2e16_v_i16m1x2_m(mask, base, v_tuple, vl) +#define __riscv_vsseg2e16_v_i16m2x2_m(mask, base, v_tuple, vl) __riscv_th_vsseg2e16_v_i16m2x2_m(mask, base, v_tuple, vl) +#define __riscv_vsseg2e16_v_i16m4x2_m(mask, base, v_tuple, vl) __riscv_th_vsseg2e16_v_i16m4x2_m(mask, base, v_tuple, vl) +#define __riscv_vsseg2e16_v_u16m1x2_m(mask, base, v_tuple, vl) __riscv_th_vsseg2e16_v_u16m1x2_m(mask, base, v_tuple, vl) +#define __riscv_vsseg2e16_v_u16m2x2_m(mask, base, v_tuple, vl) __riscv_th_vsseg2e16_v_u16m2x2_m(mask, base, v_tuple, vl) +#define __riscv_vsseg2e16_v_u16m4x2_m(mask, base, v_tuple, vl) __riscv_th_vsseg2e16_v_u16m4x2_m(mask, base, v_tuple, vl) +#define __riscv_vsseg2e32_v_f32m1x2(base, v_tuple, vl) __riscv_th_vsseg2e32_v_f32m1x2(base, v_tuple, vl) +#define __riscv_vsseg2e32_v_f32m2x2(base, v_tuple, vl) __riscv_th_vsseg2e32_v_f32m2x2(base, v_tuple, vl) +#define __riscv_vsseg2e32_v_f32m4x2(base, v_tuple, vl) __riscv_th_vsseg2e32_v_f32m4x2(base, v_tuple, vl) +#define __riscv_vsseg2e32_v_i32m1x2(base, v_tuple, vl) __riscv_th_vsseg2e32_v_i32m1x2(base, v_tuple, vl) +#define __riscv_vsseg2e32_v_i32m2x2(base, v_tuple, vl) __riscv_th_vsseg2e32_v_i32m2x2(base, v_tuple, vl) +#define __riscv_vsseg2e32_v_i32m4x2(base, v_tuple, vl) __riscv_th_vsseg2e32_v_i32m4x2(base, v_tuple, vl) +#define __riscv_vsseg2e32_v_u32m1x2(base, v_tuple, vl) __riscv_th_vsseg2e32_v_u32m1x2(base, v_tuple, vl) +#define __riscv_vsseg2e32_v_u32m2x2(base, v_tuple, vl) __riscv_th_vsseg2e32_v_u32m2x2(base, v_tuple, vl) +#define __riscv_vsseg2e32_v_u32m4x2(base, v_tuple, vl) __riscv_th_vsseg2e32_v_u32m4x2(base, v_tuple, vl) +#define __riscv_vsseg2e32_v_f32m1x2_m(mask, base, v_tuple, vl) __riscv_th_vsseg2e32_v_f32m1x2_m(mask, base, v_tuple, vl) +#define __riscv_vsseg2e32_v_f32m2x2_m(mask, base, v_tuple, vl) __riscv_th_vsseg2e32_v_f32m2x2_m(mask, base, v_tuple, vl) +#define __riscv_vsseg2e32_v_f32m4x2_m(mask, base, v_tuple, vl) __riscv_th_vsseg2e32_v_f32m4x2_m(mask, base, v_tuple, vl) +#define __riscv_vsseg2e32_v_i32m1x2_m(mask, base, v_tuple, vl) __riscv_th_vsseg2e32_v_i32m1x2_m(mask, base, v_tuple, vl) +#define __riscv_vsseg2e32_v_i32m2x2_m(mask, base, v_tuple, vl) __riscv_th_vsseg2e32_v_i32m2x2_m(mask, base, v_tuple, vl) +#define __riscv_vsseg2e32_v_i32m4x2_m(mask, base, v_tuple, vl) __riscv_th_vsseg2e32_v_i32m4x2_m(mask, base, v_tuple, vl) +#define __riscv_vsseg2e32_v_u32m1x2_m(mask, base, v_tuple, vl) __riscv_th_vsseg2e32_v_u32m1x2_m(mask, base, v_tuple, vl) +#define __riscv_vsseg2e32_v_u32m2x2_m(mask, base, v_tuple, vl) __riscv_th_vsseg2e32_v_u32m2x2_m(mask, base, v_tuple, vl) +#define __riscv_vsseg2e32_v_u32m4x2_m(mask, base, v_tuple, vl) __riscv_th_vsseg2e32_v_u32m4x2_m(mask, base, v_tuple, vl) +#define __riscv_vsseg2e64_v_f64m1x2(base, v_tuple, vl) __riscv_th_vsseg2e64_v_f64m1x2(base, v_tuple, vl) +#define __riscv_vsseg2e64_v_f64m2x2(base, v_tuple, vl) __riscv_th_vsseg2e64_v_f64m2x2(base, v_tuple, vl) +#define __riscv_vsseg2e64_v_f64m4x2(base, v_tuple, vl) __riscv_th_vsseg2e64_v_f64m4x2(base, v_tuple, vl) +#define __riscv_vsseg2e64_v_i64m1x2(base, v_tuple, vl) __riscv_th_vsseg2e64_v_i64m1x2(base, v_tuple, vl) +#define __riscv_vsseg2e64_v_i64m2x2(base, v_tuple, vl) __riscv_th_vsseg2e64_v_i64m2x2(base, v_tuple, vl) +#define __riscv_vsseg2e64_v_i64m4x2(base, v_tuple, vl) __riscv_th_vsseg2e64_v_i64m4x2(base, v_tuple, vl) +#define __riscv_vsseg2e64_v_u64m1x2(base, v_tuple, vl) __riscv_th_vsseg2e64_v_u64m1x2(base, v_tuple, vl) +#define __riscv_vsseg2e64_v_u64m2x2(base, v_tuple, vl) __riscv_th_vsseg2e64_v_u64m2x2(base, v_tuple, vl) +#define __riscv_vsseg2e64_v_u64m4x2(base, v_tuple, vl) __riscv_th_vsseg2e64_v_u64m4x2(base, v_tuple, vl) +#define __riscv_vsseg2e64_v_f64m1x2_m(mask, base, v_tuple, vl) __riscv_th_vsseg2e64_v_f64m1x2_m(mask, base, v_tuple, vl) +#define __riscv_vsseg2e64_v_f64m2x2_m(mask, base, v_tuple, vl) __riscv_th_vsseg2e64_v_f64m2x2_m(mask, base, v_tuple, vl) +#define __riscv_vsseg2e64_v_f64m4x2_m(mask, base, v_tuple, vl) __riscv_th_vsseg2e64_v_f64m4x2_m(mask, base, v_tuple, vl) +#define __riscv_vsseg2e64_v_i64m1x2_m(mask, base, v_tuple, vl) __riscv_th_vsseg2e64_v_i64m1x2_m(mask, base, v_tuple, vl) +#define __riscv_vsseg2e64_v_i64m2x2_m(mask, base, v_tuple, vl) __riscv_th_vsseg2e64_v_i64m2x2_m(mask, base, v_tuple, vl) +#define __riscv_vsseg2e64_v_i64m4x2_m(mask, base, v_tuple, vl) __riscv_th_vsseg2e64_v_i64m4x2_m(mask, base, v_tuple, vl) +#define __riscv_vsseg2e64_v_u64m1x2_m(mask, base, v_tuple, vl) __riscv_th_vsseg2e64_v_u64m1x2_m(mask, base, v_tuple, vl) +#define __riscv_vsseg2e64_v_u64m2x2_m(mask, base, v_tuple, vl) __riscv_th_vsseg2e64_v_u64m2x2_m(mask, base, v_tuple, vl) +#define __riscv_vsseg2e64_v_u64m4x2_m(mask, base, v_tuple, vl) __riscv_th_vsseg2e64_v_u64m4x2_m(mask, base, v_tuple, vl) +#define __riscv_vsseg2e8_v_i8m1x2(base, v_tuple, vl) __riscv_th_vsseg2e8_v_i8m1x2(base, v_tuple, vl) +#define __riscv_vsseg2e8_v_i8m2x2(base, v_tuple, vl) __riscv_th_vsseg2e8_v_i8m2x2(base, v_tuple, vl) +#define __riscv_vsseg2e8_v_i8m4x2(base, v_tuple, vl) __riscv_th_vsseg2e8_v_i8m4x2(base, v_tuple, vl) +#define __riscv_vsseg2e8_v_u8m1x2(base, v_tuple, vl) __riscv_th_vsseg2e8_v_u8m1x2(base, v_tuple, vl) +#define __riscv_vsseg2e8_v_u8m2x2(base, v_tuple, vl) __riscv_th_vsseg2e8_v_u8m2x2(base, v_tuple, vl) +#define __riscv_vsseg2e8_v_u8m4x2(base, v_tuple, vl) __riscv_th_vsseg2e8_v_u8m4x2(base, v_tuple, vl) +#define __riscv_vsseg2e8_v_i8m1x2_m(mask, base, v_tuple, vl) __riscv_th_vsseg2e8_v_i8m1x2_m(mask, base, v_tuple, vl) +#define __riscv_vsseg2e8_v_i8m2x2_m(mask, base, v_tuple, vl) __riscv_th_vsseg2e8_v_i8m2x2_m(mask, base, v_tuple, vl) +#define __riscv_vsseg2e8_v_i8m4x2_m(mask, base, v_tuple, vl) __riscv_th_vsseg2e8_v_i8m4x2_m(mask, base, v_tuple, vl) +#define __riscv_vsseg2e8_v_u8m1x2_m(mask, base, v_tuple, vl) __riscv_th_vsseg2e8_v_u8m1x2_m(mask, base, v_tuple, vl) +#define __riscv_vsseg2e8_v_u8m2x2_m(mask, base, v_tuple, vl) __riscv_th_vsseg2e8_v_u8m2x2_m(mask, base, v_tuple, vl) +#define __riscv_vsseg2e8_v_u8m4x2_m(mask, base, v_tuple, vl) __riscv_th_vsseg2e8_v_u8m4x2_m(mask, base, v_tuple, vl) +#define __riscv_vsseg3e16_v_f16m1x3(base, v_tuple, vl) __riscv_th_vsseg3e16_v_f16m1x3(base, v_tuple, vl) +#define __riscv_vsseg3e16_v_f16m2x3(base, v_tuple, vl) __riscv_th_vsseg3e16_v_f16m2x3(base, v_tuple, vl) +#define __riscv_vsseg3e16_v_i16m1x3(base, v_tuple, vl) __riscv_th_vsseg3e16_v_i16m1x3(base, v_tuple, vl) +#define __riscv_vsseg3e16_v_i16m2x3(base, v_tuple, vl) __riscv_th_vsseg3e16_v_i16m2x3(base, v_tuple, vl) +#define __riscv_vsseg3e16_v_u16m1x3(base, v_tuple, vl) __riscv_th_vsseg3e16_v_u16m1x3(base, v_tuple, vl) +#define __riscv_vsseg3e16_v_u16m2x3(base, v_tuple, vl) __riscv_th_vsseg3e16_v_u16m2x3(base, v_tuple, vl) +#define __riscv_vsseg3e16_v_f16m1x3_m(mask, base, v_tuple, vl) __riscv_th_vsseg3e16_v_f16m1x3_m(mask, base, v_tuple, vl) +#define __riscv_vsseg3e16_v_f16m2x3_m(mask, base, v_tuple, vl) __riscv_th_vsseg3e16_v_f16m2x3_m(mask, base, v_tuple, vl) +#define __riscv_vsseg3e16_v_i16m1x3_m(mask, base, v_tuple, vl) __riscv_th_vsseg3e16_v_i16m1x3_m(mask, base, v_tuple, vl) +#define __riscv_vsseg3e16_v_i16m2x3_m(mask, base, v_tuple, vl) __riscv_th_vsseg3e16_v_i16m2x3_m(mask, base, v_tuple, vl) +#define __riscv_vsseg3e16_v_u16m1x3_m(mask, base, v_tuple, vl) __riscv_th_vsseg3e16_v_u16m1x3_m(mask, base, v_tuple, vl) +#define __riscv_vsseg3e16_v_u16m2x3_m(mask, base, v_tuple, vl) __riscv_th_vsseg3e16_v_u16m2x3_m(mask, base, v_tuple, vl) +#define __riscv_vsseg3e32_v_f32m1x3(base, v_tuple, vl) __riscv_th_vsseg3e32_v_f32m1x3(base, v_tuple, vl) +#define __riscv_vsseg3e32_v_f32m2x3(base, v_tuple, vl) __riscv_th_vsseg3e32_v_f32m2x3(base, v_tuple, vl) +#define __riscv_vsseg3e32_v_i32m1x3(base, v_tuple, vl) __riscv_th_vsseg3e32_v_i32m1x3(base, v_tuple, vl) +#define __riscv_vsseg3e32_v_i32m2x3(base, v_tuple, vl) __riscv_th_vsseg3e32_v_i32m2x3(base, v_tuple, vl) +#define __riscv_vsseg3e32_v_u32m1x3(base, v_tuple, vl) __riscv_th_vsseg3e32_v_u32m1x3(base, v_tuple, vl) +#define __riscv_vsseg3e32_v_u32m2x3(base, v_tuple, vl) __riscv_th_vsseg3e32_v_u32m2x3(base, v_tuple, vl) +#define __riscv_vsseg3e32_v_f32m1x3_m(mask, base, v_tuple, vl) __riscv_th_vsseg3e32_v_f32m1x3_m(mask, base, v_tuple, vl) +#define __riscv_vsseg3e32_v_f32m2x3_m(mask, base, v_tuple, vl) __riscv_th_vsseg3e32_v_f32m2x3_m(mask, base, v_tuple, vl) +#define __riscv_vsseg3e32_v_i32m1x3_m(mask, base, v_tuple, vl) __riscv_th_vsseg3e32_v_i32m1x3_m(mask, base, v_tuple, vl) +#define __riscv_vsseg3e32_v_i32m2x3_m(mask, base, v_tuple, vl) __riscv_th_vsseg3e32_v_i32m2x3_m(mask, base, v_tuple, vl) +#define __riscv_vsseg3e32_v_u32m1x3_m(mask, base, v_tuple, vl) __riscv_th_vsseg3e32_v_u32m1x3_m(mask, base, v_tuple, vl) +#define __riscv_vsseg3e32_v_u32m2x3_m(mask, base, v_tuple, vl) __riscv_th_vsseg3e32_v_u32m2x3_m(mask, base, v_tuple, vl) +#define __riscv_vsseg3e64_v_f64m1x3(base, v_tuple, vl) __riscv_th_vsseg3e64_v_f64m1x3(base, v_tuple, vl) +#define __riscv_vsseg3e64_v_f64m2x3(base, v_tuple, vl) __riscv_th_vsseg3e64_v_f64m2x3(base, v_tuple, vl) +#define __riscv_vsseg3e64_v_i64m1x3(base, v_tuple, vl) __riscv_th_vsseg3e64_v_i64m1x3(base, v_tuple, vl) +#define __riscv_vsseg3e64_v_i64m2x3(base, v_tuple, vl) __riscv_th_vsseg3e64_v_i64m2x3(base, v_tuple, vl) +#define __riscv_vsseg3e64_v_u64m1x3(base, v_tuple, vl) __riscv_th_vsseg3e64_v_u64m1x3(base, v_tuple, vl) +#define __riscv_vsseg3e64_v_u64m2x3(base, v_tuple, vl) __riscv_th_vsseg3e64_v_u64m2x3(base, v_tuple, vl) +#define __riscv_vsseg3e64_v_f64m1x3_m(mask, base, v_tuple, vl) __riscv_th_vsseg3e64_v_f64m1x3_m(mask, base, v_tuple, vl) +#define __riscv_vsseg3e64_v_f64m2x3_m(mask, base, v_tuple, vl) __riscv_th_vsseg3e64_v_f64m2x3_m(mask, base, v_tuple, vl) +#define __riscv_vsseg3e64_v_i64m1x3_m(mask, base, v_tuple, vl) __riscv_th_vsseg3e64_v_i64m1x3_m(mask, base, v_tuple, vl) +#define __riscv_vsseg3e64_v_i64m2x3_m(mask, base, v_tuple, vl) __riscv_th_vsseg3e64_v_i64m2x3_m(mask, base, v_tuple, vl) +#define __riscv_vsseg3e64_v_u64m1x3_m(mask, base, v_tuple, vl) __riscv_th_vsseg3e64_v_u64m1x3_m(mask, base, v_tuple, vl) +#define __riscv_vsseg3e64_v_u64m2x3_m(mask, base, v_tuple, vl) __riscv_th_vsseg3e64_v_u64m2x3_m(mask, base, v_tuple, vl) +#define __riscv_vsseg3e8_v_i8m1x3(base, v_tuple, vl) __riscv_th_vsseg3e8_v_i8m1x3(base, v_tuple, vl) +#define __riscv_vsseg3e8_v_i8m2x3(base, v_tuple, vl) __riscv_th_vsseg3e8_v_i8m2x3(base, v_tuple, vl) +#define __riscv_vsseg3e8_v_u8m1x3(base, v_tuple, vl) __riscv_th_vsseg3e8_v_u8m1x3(base, v_tuple, vl) +#define __riscv_vsseg3e8_v_u8m2x3(base, v_tuple, vl) __riscv_th_vsseg3e8_v_u8m2x3(base, v_tuple, vl) +#define __riscv_vsseg3e8_v_i8m1x3_m(mask, base, v_tuple, vl) __riscv_th_vsseg3e8_v_i8m1x3_m(mask, base, v_tuple, vl) +#define __riscv_vsseg3e8_v_i8m2x3_m(mask, base, v_tuple, vl) __riscv_th_vsseg3e8_v_i8m2x3_m(mask, base, v_tuple, vl) +#define __riscv_vsseg3e8_v_u8m1x3_m(mask, base, v_tuple, vl) __riscv_th_vsseg3e8_v_u8m1x3_m(mask, base, v_tuple, vl) +#define __riscv_vsseg3e8_v_u8m2x3_m(mask, base, v_tuple, vl) __riscv_th_vsseg3e8_v_u8m2x3_m(mask, base, v_tuple, vl) +#define __riscv_vsseg4e16_v_f16m1x4(base, v_tuple, vl) __riscv_th_vsseg4e16_v_f16m1x4(base, v_tuple, vl) +#define __riscv_vsseg4e16_v_f16m2x4(base, v_tuple, vl) __riscv_th_vsseg4e16_v_f16m2x4(base, v_tuple, vl) +#define __riscv_vsseg4e16_v_i16m1x4(base, v_tuple, vl) __riscv_th_vsseg4e16_v_i16m1x4(base, v_tuple, vl) +#define __riscv_vsseg4e16_v_i16m2x4(base, v_tuple, vl) __riscv_th_vsseg4e16_v_i16m2x4(base, v_tuple, vl) +#define __riscv_vsseg4e16_v_u16m1x4(base, v_tuple, vl) __riscv_th_vsseg4e16_v_u16m1x4(base, v_tuple, vl) +#define __riscv_vsseg4e16_v_u16m2x4(base, v_tuple, vl) __riscv_th_vsseg4e16_v_u16m2x4(base, v_tuple, vl) +#define __riscv_vsseg4e16_v_f16m1x4_m(mask, base, v_tuple, vl) __riscv_th_vsseg4e16_v_f16m1x4_m(mask, base, v_tuple, vl) +#define __riscv_vsseg4e16_v_f16m2x4_m(mask, base, v_tuple, vl) __riscv_th_vsseg4e16_v_f16m2x4_m(mask, base, v_tuple, vl) +#define __riscv_vsseg4e16_v_i16m1x4_m(mask, base, v_tuple, vl) __riscv_th_vsseg4e16_v_i16m1x4_m(mask, base, v_tuple, vl) +#define __riscv_vsseg4e16_v_i16m2x4_m(mask, base, v_tuple, vl) __riscv_th_vsseg4e16_v_i16m2x4_m(mask, base, v_tuple, vl) +#define __riscv_vsseg4e16_v_u16m1x4_m(mask, base, v_tuple, vl) __riscv_th_vsseg4e16_v_u16m1x4_m(mask, base, v_tuple, vl) +#define __riscv_vsseg4e16_v_u16m2x4_m(mask, base, v_tuple, vl) __riscv_th_vsseg4e16_v_u16m2x4_m(mask, base, v_tuple, vl) +#define __riscv_vsseg4e32_v_f32m1x4(base, v_tuple, vl) __riscv_th_vsseg4e32_v_f32m1x4(base, v_tuple, vl) +#define __riscv_vsseg4e32_v_f32m2x4(base, v_tuple, vl) __riscv_th_vsseg4e32_v_f32m2x4(base, v_tuple, vl) +#define __riscv_vsseg4e32_v_i32m1x4(base, v_tuple, vl) __riscv_th_vsseg4e32_v_i32m1x4(base, v_tuple, vl) +#define __riscv_vsseg4e32_v_i32m2x4(base, v_tuple, vl) __riscv_th_vsseg4e32_v_i32m2x4(base, v_tuple, vl) +#define __riscv_vsseg4e32_v_u32m1x4(base, v_tuple, vl) __riscv_th_vsseg4e32_v_u32m1x4(base, v_tuple, vl) +#define __riscv_vsseg4e32_v_u32m2x4(base, v_tuple, vl) __riscv_th_vsseg4e32_v_u32m2x4(base, v_tuple, vl) +#define __riscv_vsseg4e32_v_f32m1x4_m(mask, base, v_tuple, vl) __riscv_th_vsseg4e32_v_f32m1x4_m(mask, base, v_tuple, vl) +#define __riscv_vsseg4e32_v_f32m2x4_m(mask, base, v_tuple, vl) __riscv_th_vsseg4e32_v_f32m2x4_m(mask, base, v_tuple, vl) +#define __riscv_vsseg4e32_v_i32m1x4_m(mask, base, v_tuple, vl) __riscv_th_vsseg4e32_v_i32m1x4_m(mask, base, v_tuple, vl) +#define __riscv_vsseg4e32_v_i32m2x4_m(mask, base, v_tuple, vl) __riscv_th_vsseg4e32_v_i32m2x4_m(mask, base, v_tuple, vl) +#define __riscv_vsseg4e32_v_u32m1x4_m(mask, base, v_tuple, vl) __riscv_th_vsseg4e32_v_u32m1x4_m(mask, base, v_tuple, vl) +#define __riscv_vsseg4e32_v_u32m2x4_m(mask, base, v_tuple, vl) __riscv_th_vsseg4e32_v_u32m2x4_m(mask, base, v_tuple, vl) +#define __riscv_vsseg4e64_v_f64m1x4(base, v_tuple, vl) __riscv_th_vsseg4e64_v_f64m1x4(base, v_tuple, vl) +#define __riscv_vsseg4e64_v_f64m2x4(base, v_tuple, vl) __riscv_th_vsseg4e64_v_f64m2x4(base, v_tuple, vl) +#define __riscv_vsseg4e64_v_i64m1x4(base, v_tuple, vl) __riscv_th_vsseg4e64_v_i64m1x4(base, v_tuple, vl) +#define __riscv_vsseg4e64_v_i64m2x4(base, v_tuple, vl) __riscv_th_vsseg4e64_v_i64m2x4(base, v_tuple, vl) +#define __riscv_vsseg4e64_v_u64m1x4(base, v_tuple, vl) __riscv_th_vsseg4e64_v_u64m1x4(base, v_tuple, vl) +#define __riscv_vsseg4e64_v_u64m2x4(base, v_tuple, vl) __riscv_th_vsseg4e64_v_u64m2x4(base, v_tuple, vl) +#define __riscv_vsseg4e64_v_f64m1x4_m(mask, base, v_tuple, vl) __riscv_th_vsseg4e64_v_f64m1x4_m(mask, base, v_tuple, vl) +#define __riscv_vsseg4e64_v_f64m2x4_m(mask, base, v_tuple, vl) __riscv_th_vsseg4e64_v_f64m2x4_m(mask, base, v_tuple, vl) +#define __riscv_vsseg4e64_v_i64m1x4_m(mask, base, v_tuple, vl) __riscv_th_vsseg4e64_v_i64m1x4_m(mask, base, v_tuple, vl) +#define __riscv_vsseg4e64_v_i64m2x4_m(mask, base, v_tuple, vl) __riscv_th_vsseg4e64_v_i64m2x4_m(mask, base, v_tuple, vl) +#define __riscv_vsseg4e64_v_u64m1x4_m(mask, base, v_tuple, vl) __riscv_th_vsseg4e64_v_u64m1x4_m(mask, base, v_tuple, vl) +#define __riscv_vsseg4e64_v_u64m2x4_m(mask, base, v_tuple, vl) __riscv_th_vsseg4e64_v_u64m2x4_m(mask, base, v_tuple, vl) +#define __riscv_vsseg4e8_v_i8m1x4(base, v_tuple, vl) __riscv_th_vsseg4e8_v_i8m1x4(base, v_tuple, vl) +#define __riscv_vsseg4e8_v_i8m2x4(base, v_tuple, vl) __riscv_th_vsseg4e8_v_i8m2x4(base, v_tuple, vl) +#define __riscv_vsseg4e8_v_u8m1x4(base, v_tuple, vl) __riscv_th_vsseg4e8_v_u8m1x4(base, v_tuple, vl) +#define __riscv_vsseg4e8_v_u8m2x4(base, v_tuple, vl) __riscv_th_vsseg4e8_v_u8m2x4(base, v_tuple, vl) +#define __riscv_vsseg4e8_v_i8m1x4_m(mask, base, v_tuple, vl) __riscv_th_vsseg4e8_v_i8m1x4_m(mask, base, v_tuple, vl) +#define __riscv_vsseg4e8_v_i8m2x4_m(mask, base, v_tuple, vl) __riscv_th_vsseg4e8_v_i8m2x4_m(mask, base, v_tuple, vl) +#define __riscv_vsseg4e8_v_u8m1x4_m(mask, base, v_tuple, vl) __riscv_th_vsseg4e8_v_u8m1x4_m(mask, base, v_tuple, vl) +#define __riscv_vsseg4e8_v_u8m2x4_m(mask, base, v_tuple, vl) __riscv_th_vsseg4e8_v_u8m2x4_m(mask, base, v_tuple, vl) +#define __riscv_vsseg5e16_v_f16m1x5(base, v_tuple, vl) __riscv_th_vsseg5e16_v_f16m1x5(base, v_tuple, vl) +#define __riscv_vsseg5e16_v_i16m1x5(base, v_tuple, vl) __riscv_th_vsseg5e16_v_i16m1x5(base, v_tuple, vl) +#define __riscv_vsseg5e16_v_u16m1x5(base, v_tuple, vl) __riscv_th_vsseg5e16_v_u16m1x5(base, v_tuple, vl) +#define __riscv_vsseg5e16_v_f16m1x5_m(mask, base, v_tuple, vl) __riscv_th_vsseg5e16_v_f16m1x5_m(mask, base, v_tuple, vl) +#define __riscv_vsseg5e16_v_i16m1x5_m(mask, base, v_tuple, vl) __riscv_th_vsseg5e16_v_i16m1x5_m(mask, base, v_tuple, vl) +#define __riscv_vsseg5e16_v_u16m1x5_m(mask, base, v_tuple, vl) __riscv_th_vsseg5e16_v_u16m1x5_m(mask, base, v_tuple, vl) +#define __riscv_vsseg5e32_v_f32m1x5(base, v_tuple, vl) __riscv_th_vsseg5e32_v_f32m1x5(base, v_tuple, vl) +#define __riscv_vsseg5e32_v_i32m1x5(base, v_tuple, vl) __riscv_th_vsseg5e32_v_i32m1x5(base, v_tuple, vl) +#define __riscv_vsseg5e32_v_u32m1x5(base, v_tuple, vl) __riscv_th_vsseg5e32_v_u32m1x5(base, v_tuple, vl) +#define __riscv_vsseg5e32_v_f32m1x5_m(mask, base, v_tuple, vl) __riscv_th_vsseg5e32_v_f32m1x5_m(mask, base, v_tuple, vl) +#define __riscv_vsseg5e32_v_i32m1x5_m(mask, base, v_tuple, vl) __riscv_th_vsseg5e32_v_i32m1x5_m(mask, base, v_tuple, vl) +#define __riscv_vsseg5e32_v_u32m1x5_m(mask, base, v_tuple, vl) __riscv_th_vsseg5e32_v_u32m1x5_m(mask, base, v_tuple, vl) +#define __riscv_vsseg5e64_v_f64m1x5(base, v_tuple, vl) __riscv_th_vsseg5e64_v_f64m1x5(base, v_tuple, vl) +#define __riscv_vsseg5e64_v_i64m1x5(base, v_tuple, vl) __riscv_th_vsseg5e64_v_i64m1x5(base, v_tuple, vl) +#define __riscv_vsseg5e64_v_u64m1x5(base, v_tuple, vl) __riscv_th_vsseg5e64_v_u64m1x5(base, v_tuple, vl) +#define __riscv_vsseg5e64_v_f64m1x5_m(mask, base, v_tuple, vl) __riscv_th_vsseg5e64_v_f64m1x5_m(mask, base, v_tuple, vl) +#define __riscv_vsseg5e64_v_i64m1x5_m(mask, base, v_tuple, vl) __riscv_th_vsseg5e64_v_i64m1x5_m(mask, base, v_tuple, vl) +#define __riscv_vsseg5e64_v_u64m1x5_m(mask, base, v_tuple, vl) __riscv_th_vsseg5e64_v_u64m1x5_m(mask, base, v_tuple, vl) +#define __riscv_vsseg5e8_v_i8m1x5(base, v_tuple, vl) __riscv_th_vsseg5e8_v_i8m1x5(base, v_tuple, vl) +#define __riscv_vsseg5e8_v_u8m1x5(base, v_tuple, vl) __riscv_th_vsseg5e8_v_u8m1x5(base, v_tuple, vl) +#define __riscv_vsseg5e8_v_i8m1x5_m(mask, base, v_tuple, vl) __riscv_th_vsseg5e8_v_i8m1x5_m(mask, base, v_tuple, vl) +#define __riscv_vsseg5e8_v_u8m1x5_m(mask, base, v_tuple, vl) __riscv_th_vsseg5e8_v_u8m1x5_m(mask, base, v_tuple, vl) +#define __riscv_vsseg6e16_v_f16m1x6(base, v_tuple, vl) __riscv_th_vsseg6e16_v_f16m1x6(base, v_tuple, vl) +#define __riscv_vsseg6e16_v_i16m1x6(base, v_tuple, vl) __riscv_th_vsseg6e16_v_i16m1x6(base, v_tuple, vl) +#define __riscv_vsseg6e16_v_u16m1x6(base, v_tuple, vl) __riscv_th_vsseg6e16_v_u16m1x6(base, v_tuple, vl) +#define __riscv_vsseg6e16_v_f16m1x6_m(mask, base, v_tuple, vl) __riscv_th_vsseg6e16_v_f16m1x6_m(mask, base, v_tuple, vl) +#define __riscv_vsseg6e16_v_i16m1x6_m(mask, base, v_tuple, vl) __riscv_th_vsseg6e16_v_i16m1x6_m(mask, base, v_tuple, vl) +#define __riscv_vsseg6e16_v_u16m1x6_m(mask, base, v_tuple, vl) __riscv_th_vsseg6e16_v_u16m1x6_m(mask, base, v_tuple, vl) +#define __riscv_vsseg6e32_v_f32m1x6(base, v_tuple, vl) __riscv_th_vsseg6e32_v_f32m1x6(base, v_tuple, vl) +#define __riscv_vsseg6e32_v_i32m1x6(base, v_tuple, vl) __riscv_th_vsseg6e32_v_i32m1x6(base, v_tuple, vl) +#define __riscv_vsseg6e32_v_u32m1x6(base, v_tuple, vl) __riscv_th_vsseg6e32_v_u32m1x6(base, v_tuple, vl) +#define __riscv_vsseg6e32_v_f32m1x6_m(mask, base, v_tuple, vl) __riscv_th_vsseg6e32_v_f32m1x6_m(mask, base, v_tuple, vl) +#define __riscv_vsseg6e32_v_i32m1x6_m(mask, base, v_tuple, vl) __riscv_th_vsseg6e32_v_i32m1x6_m(mask, base, v_tuple, vl) +#define __riscv_vsseg6e32_v_u32m1x6_m(mask, base, v_tuple, vl) __riscv_th_vsseg6e32_v_u32m1x6_m(mask, base, v_tuple, vl) +#define __riscv_vsseg6e64_v_f64m1x6(base, v_tuple, vl) __riscv_th_vsseg6e64_v_f64m1x6(base, v_tuple, vl) +#define __riscv_vsseg6e64_v_i64m1x6(base, v_tuple, vl) __riscv_th_vsseg6e64_v_i64m1x6(base, v_tuple, vl) +#define __riscv_vsseg6e64_v_u64m1x6(base, v_tuple, vl) __riscv_th_vsseg6e64_v_u64m1x6(base, v_tuple, vl) +#define __riscv_vsseg6e64_v_f64m1x6_m(mask, base, v_tuple, vl) __riscv_th_vsseg6e64_v_f64m1x6_m(mask, base, v_tuple, vl) +#define __riscv_vsseg6e64_v_i64m1x6_m(mask, base, v_tuple, vl) __riscv_th_vsseg6e64_v_i64m1x6_m(mask, base, v_tuple, vl) +#define __riscv_vsseg6e64_v_u64m1x6_m(mask, base, v_tuple, vl) __riscv_th_vsseg6e64_v_u64m1x6_m(mask, base, v_tuple, vl) +#define __riscv_vsseg6e8_v_i8m1x6(base, v_tuple, vl) __riscv_th_vsseg6e8_v_i8m1x6(base, v_tuple, vl) +#define __riscv_vsseg6e8_v_u8m1x6(base, v_tuple, vl) __riscv_th_vsseg6e8_v_u8m1x6(base, v_tuple, vl) +#define __riscv_vsseg6e8_v_i8m1x6_m(mask, base, v_tuple, vl) __riscv_th_vsseg6e8_v_i8m1x6_m(mask, base, v_tuple, vl) +#define __riscv_vsseg6e8_v_u8m1x6_m(mask, base, v_tuple, vl) __riscv_th_vsseg6e8_v_u8m1x6_m(mask, base, v_tuple, vl) +#define __riscv_vsseg7e16_v_f16m1x7(base, v_tuple, vl) __riscv_th_vsseg7e16_v_f16m1x7(base, v_tuple, vl) +#define __riscv_vsseg7e16_v_i16m1x7(base, v_tuple, vl) __riscv_th_vsseg7e16_v_i16m1x7(base, v_tuple, vl) +#define __riscv_vsseg7e16_v_u16m1x7(base, v_tuple, vl) __riscv_th_vsseg7e16_v_u16m1x7(base, v_tuple, vl) +#define __riscv_vsseg7e16_v_f16m1x7_m(mask, base, v_tuple, vl) __riscv_th_vsseg7e16_v_f16m1x7_m(mask, base, v_tuple, vl) +#define __riscv_vsseg7e16_v_i16m1x7_m(mask, base, v_tuple, vl) __riscv_th_vsseg7e16_v_i16m1x7_m(mask, base, v_tuple, vl) +#define __riscv_vsseg7e16_v_u16m1x7_m(mask, base, v_tuple, vl) __riscv_th_vsseg7e16_v_u16m1x7_m(mask, base, v_tuple, vl) +#define __riscv_vsseg7e32_v_f32m1x7(base, v_tuple, vl) __riscv_th_vsseg7e32_v_f32m1x7(base, v_tuple, vl) +#define __riscv_vsseg7e32_v_i32m1x7(base, v_tuple, vl) __riscv_th_vsseg7e32_v_i32m1x7(base, v_tuple, vl) +#define __riscv_vsseg7e32_v_u32m1x7(base, v_tuple, vl) __riscv_th_vsseg7e32_v_u32m1x7(base, v_tuple, vl) +#define __riscv_vsseg7e32_v_f32m1x7_m(mask, base, v_tuple, vl) __riscv_th_vsseg7e32_v_f32m1x7_m(mask, base, v_tuple, vl) +#define __riscv_vsseg7e32_v_i32m1x7_m(mask, base, v_tuple, vl) __riscv_th_vsseg7e32_v_i32m1x7_m(mask, base, v_tuple, vl) +#define __riscv_vsseg7e32_v_u32m1x7_m(mask, base, v_tuple, vl) __riscv_th_vsseg7e32_v_u32m1x7_m(mask, base, v_tuple, vl) +#define __riscv_vsseg7e64_v_f64m1x7(base, v_tuple, vl) __riscv_th_vsseg7e64_v_f64m1x7(base, v_tuple, vl) +#define __riscv_vsseg7e64_v_i64m1x7(base, v_tuple, vl) __riscv_th_vsseg7e64_v_i64m1x7(base, v_tuple, vl) +#define __riscv_vsseg7e64_v_u64m1x7(base, v_tuple, vl) __riscv_th_vsseg7e64_v_u64m1x7(base, v_tuple, vl) +#define __riscv_vsseg7e64_v_f64m1x7_m(mask, base, v_tuple, vl) __riscv_th_vsseg7e64_v_f64m1x7_m(mask, base, v_tuple, vl) +#define __riscv_vsseg7e64_v_i64m1x7_m(mask, base, v_tuple, vl) __riscv_th_vsseg7e64_v_i64m1x7_m(mask, base, v_tuple, vl) +#define __riscv_vsseg7e64_v_u64m1x7_m(mask, base, v_tuple, vl) __riscv_th_vsseg7e64_v_u64m1x7_m(mask, base, v_tuple, vl) +#define __riscv_vsseg7e8_v_i8m1x7(base, v_tuple, vl) __riscv_th_vsseg7e8_v_i8m1x7(base, v_tuple, vl) +#define __riscv_vsseg7e8_v_u8m1x7(base, v_tuple, vl) __riscv_th_vsseg7e8_v_u8m1x7(base, v_tuple, vl) +#define __riscv_vsseg7e8_v_i8m1x7_m(mask, base, v_tuple, vl) __riscv_th_vsseg7e8_v_i8m1x7_m(mask, base, v_tuple, vl) +#define __riscv_vsseg7e8_v_u8m1x7_m(mask, base, v_tuple, vl) __riscv_th_vsseg7e8_v_u8m1x7_m(mask, base, v_tuple, vl) +#define __riscv_vsseg8e16_v_f16m1x8(base, v_tuple, vl) __riscv_th_vsseg8e16_v_f16m1x8(base, v_tuple, vl) +#define __riscv_vsseg8e16_v_i16m1x8(base, v_tuple, vl) __riscv_th_vsseg8e16_v_i16m1x8(base, v_tuple, vl) +#define __riscv_vsseg8e16_v_u16m1x8(base, v_tuple, vl) __riscv_th_vsseg8e16_v_u16m1x8(base, v_tuple, vl) +#define __riscv_vsseg8e16_v_f16m1x8_m(mask, base, v_tuple, vl) __riscv_th_vsseg8e16_v_f16m1x8_m(mask, base, v_tuple, vl) +#define __riscv_vsseg8e16_v_i16m1x8_m(mask, base, v_tuple, vl) __riscv_th_vsseg8e16_v_i16m1x8_m(mask, base, v_tuple, vl) +#define __riscv_vsseg8e16_v_u16m1x8_m(mask, base, v_tuple, vl) __riscv_th_vsseg8e16_v_u16m1x8_m(mask, base, v_tuple, vl) +#define __riscv_vsseg8e32_v_f32m1x8(base, v_tuple, vl) __riscv_th_vsseg8e32_v_f32m1x8(base, v_tuple, vl) +#define __riscv_vsseg8e32_v_i32m1x8(base, v_tuple, vl) __riscv_th_vsseg8e32_v_i32m1x8(base, v_tuple, vl) +#define __riscv_vsseg8e32_v_u32m1x8(base, v_tuple, vl) __riscv_th_vsseg8e32_v_u32m1x8(base, v_tuple, vl) +#define __riscv_vsseg8e32_v_f32m1x8_m(mask, base, v_tuple, vl) __riscv_th_vsseg8e32_v_f32m1x8_m(mask, base, v_tuple, vl) +#define __riscv_vsseg8e32_v_i32m1x8_m(mask, base, v_tuple, vl) __riscv_th_vsseg8e32_v_i32m1x8_m(mask, base, v_tuple, vl) +#define __riscv_vsseg8e32_v_u32m1x8_m(mask, base, v_tuple, vl) __riscv_th_vsseg8e32_v_u32m1x8_m(mask, base, v_tuple, vl) +#define __riscv_vsseg8e64_v_f64m1x8(base, v_tuple, vl) __riscv_th_vsseg8e64_v_f64m1x8(base, v_tuple, vl) +#define __riscv_vsseg8e64_v_i64m1x8(base, v_tuple, vl) __riscv_th_vsseg8e64_v_i64m1x8(base, v_tuple, vl) +#define __riscv_vsseg8e64_v_u64m1x8(base, v_tuple, vl) __riscv_th_vsseg8e64_v_u64m1x8(base, v_tuple, vl) +#define __riscv_vsseg8e64_v_f64m1x8_m(mask, base, v_tuple, vl) __riscv_th_vsseg8e64_v_f64m1x8_m(mask, base, v_tuple, vl) +#define __riscv_vsseg8e64_v_i64m1x8_m(mask, base, v_tuple, vl) __riscv_th_vsseg8e64_v_i64m1x8_m(mask, base, v_tuple, vl) +#define __riscv_vsseg8e64_v_u64m1x8_m(mask, base, v_tuple, vl) __riscv_th_vsseg8e64_v_u64m1x8_m(mask, base, v_tuple, vl) +#define __riscv_vsseg8e8_v_i8m1x8(base, v_tuple, vl) __riscv_th_vsseg8e8_v_i8m1x8(base, v_tuple, vl) +#define __riscv_vsseg8e8_v_u8m1x8(base, v_tuple, vl) __riscv_th_vsseg8e8_v_u8m1x8(base, v_tuple, vl) +#define __riscv_vsseg8e8_v_i8m1x8_m(mask, base, v_tuple, vl) __riscv_th_vsseg8e8_v_i8m1x8_m(mask, base, v_tuple, vl) +#define __riscv_vsseg8e8_v_u8m1x8_m(mask, base, v_tuple, vl) __riscv_th_vsseg8e8_v_u8m1x8_m(mask, base, v_tuple, vl) + +}] in +def th_zvlsseg_wrapper_macros: RVVHeader; let HeaderCode = [{ diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg2b.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg2b.c similarity index 100% rename from clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg2b.c rename to clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg2b.c diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg2e16.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg2e16.c similarity index 100% rename from clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg2e16.c rename to clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg2e16.c diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg2e16ff.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg2e16ff.c similarity index 100% rename from clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg2e16ff.c rename to clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg2e16ff.c diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg2e32.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg2e32.c similarity index 100% rename from clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg2e32.c rename to clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg2e32.c diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg2e32ff.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg2e32ff.c similarity index 100% rename from clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg2e32ff.c rename to clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg2e32ff.c diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg2e64.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg2e64.c similarity index 100% rename from clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg2e64.c rename to clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg2e64.c diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg2e64ff.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg2e64ff.c similarity index 100% rename from clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg2e64ff.c rename to clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg2e64ff.c diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg2e8.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg2e8.c similarity index 100% rename from clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg2e8.c rename to clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg2e8.c diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg2e8ff.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg2e8ff.c similarity index 100% rename from clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg2e8ff.c rename to clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg2e8ff.c diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg3e16.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg3e16.c similarity index 100% rename from clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg3e16.c rename to clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg3e16.c diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg3e16ff.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg3e16ff.c similarity index 100% rename from clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg3e16ff.c rename to clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg3e16ff.c diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg3e32.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg3e32.c similarity index 100% rename from clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg3e32.c rename to clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg3e32.c diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg3e32ff.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg3e32ff.c similarity index 100% rename from clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg3e32ff.c rename to clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg3e32ff.c diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg3e64.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg3e64.c similarity index 100% rename from clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg3e64.c rename to clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg3e64.c diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg3e64ff.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg3e64ff.c similarity index 100% rename from clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg3e64ff.c rename to clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg3e64ff.c diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg3e8.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg3e8.c similarity index 100% rename from clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg3e8.c rename to clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg3e8.c diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg3e8ff.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg3e8ff.c similarity index 100% rename from clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg3e8ff.c rename to clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg3e8ff.c diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg4e16.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg4e16.c similarity index 100% rename from clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg4e16.c rename to clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg4e16.c diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg4e16ff.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg4e16ff.c similarity index 100% rename from clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg4e16ff.c rename to clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg4e16ff.c diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg4e32.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg4e32.c similarity index 100% rename from clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg4e32.c rename to clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg4e32.c diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg4e32ff.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg4e32ff.c similarity index 100% rename from clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg4e32ff.c rename to clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg4e32ff.c diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg4e64.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg4e64.c similarity index 100% rename from clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg4e64.c rename to clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg4e64.c diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg4e64ff.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg4e64ff.c similarity index 100% rename from clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg4e64ff.c rename to clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg4e64ff.c diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg4e8.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg4e8.c similarity index 100% rename from clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg4e8.c rename to clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg4e8.c diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg4e8ff.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg4e8ff.c similarity index 100% rename from clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg4e8ff.c rename to clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg4e8ff.c diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg5e16.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg5e16.c similarity index 100% rename from clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg5e16.c rename to clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg5e16.c diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg5e16ff.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg5e16ff.c similarity index 100% rename from clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg5e16ff.c rename to clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg5e16ff.c diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg5e32.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg5e32.c similarity index 100% rename from clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg5e32.c rename to clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg5e32.c diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg5e32ff.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg5e32ff.c similarity index 100% rename from clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg5e32ff.c rename to clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg5e32ff.c diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg5e64.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg5e64.c similarity index 100% rename from clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg5e64.c rename to clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg5e64.c diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg5e64ff.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg5e64ff.c similarity index 100% rename from clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg5e64ff.c rename to clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg5e64ff.c diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg5e8.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg5e8.c similarity index 100% rename from clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg5e8.c rename to clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg5e8.c diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg5e8ff.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg5e8ff.c similarity index 100% rename from clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg5e8ff.c rename to clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg5e8ff.c diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg6e16.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg6e16.c similarity index 100% rename from clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg6e16.c rename to clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg6e16.c diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg6e16ff.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg6e16ff.c similarity index 100% rename from clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg6e16ff.c rename to clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg6e16ff.c diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg6e32.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg6e32.c similarity index 100% rename from clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg6e32.c rename to clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg6e32.c diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg6e32ff.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg6e32ff.c similarity index 100% rename from clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg6e32ff.c rename to clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg6e32ff.c diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg6e64.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg6e64.c similarity index 100% rename from clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg6e64.c rename to clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg6e64.c diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg6e64ff.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg6e64ff.c similarity index 100% rename from clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg6e64ff.c rename to clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg6e64ff.c diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg6e8.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg6e8.c similarity index 100% rename from clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg6e8.c rename to clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg6e8.c diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg6e8ff.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg6e8ff.c similarity index 100% rename from clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg6e8ff.c rename to clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg6e8ff.c diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg7e16.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg7e16.c similarity index 100% rename from clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg7e16.c rename to clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg7e16.c diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg7e16ff.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg7e16ff.c similarity index 100% rename from clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg7e16ff.c rename to clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg7e16ff.c diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg7e32.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg7e32.c similarity index 100% rename from clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg7e32.c rename to clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg7e32.c diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg7e32ff.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg7e32ff.c similarity index 100% rename from clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg7e32ff.c rename to clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg7e32ff.c diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg7e64.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg7e64.c similarity index 100% rename from clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg7e64.c rename to clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg7e64.c diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg7e64ff.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg7e64ff.c similarity index 100% rename from clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg7e64ff.c rename to clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg7e64ff.c diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg7e8.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg7e8.c similarity index 100% rename from clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg7e8.c rename to clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg7e8.c diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg7e8ff.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg7e8ff.c similarity index 100% rename from clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg7e8ff.c rename to clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg7e8ff.c diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg8e16.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg8e16.c similarity index 100% rename from clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg8e16.c rename to clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg8e16.c diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg8e16ff.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg8e16ff.c similarity index 100% rename from clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg8e16ff.c rename to clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg8e16ff.c diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg8e32.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg8e32.c similarity index 100% rename from clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg8e32.c rename to clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg8e32.c diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg8e32ff.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg8e32ff.c similarity index 100% rename from clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg8e32ff.c rename to clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg8e32ff.c diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg8e64.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg8e64.c similarity index 100% rename from clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg8e64.c rename to clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg8e64.c diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg8e64ff.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg8e64ff.c similarity index 100% rename from clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg8e64ff.c rename to clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg8e64ff.c diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg8e8.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg8e8.c similarity index 100% rename from clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg8e8.c rename to clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg8e8.c diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg8e8ff.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg8e8ff.c similarity index 100% rename from clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vlseg8e8ff.c rename to clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vlseg8e8ff.c diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg2e16.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg2e16.c new file mode 100644 index 00000000000000..163fa94918b2b2 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg2e16.c @@ -0,0 +1,260 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e16_v_f16m1x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.nxv4f16.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e16_v_f16m1x2(_Float16 *base, vfloat16m1x2_t v_tuple, size_t vl) { + return __riscv_th_vsseg2e16_v_f16m1x2(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e16_v_f16m2x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.nxv8f16.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e16_v_f16m2x2(_Float16 *base, vfloat16m2x2_t v_tuple, size_t vl) { + return __riscv_th_vsseg2e16_v_f16m2x2(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e16_v_f16m4x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.nxv16f16.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e16_v_f16m4x2(_Float16 *base, vfloat16m4x2_t v_tuple, size_t vl) { + return __riscv_th_vsseg2e16_v_f16m4x2(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e16_v_i16m1x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.nxv4i16.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e16_v_i16m1x2(int16_t *base, vint16m1x2_t v_tuple, size_t vl) { + return __riscv_th_vsseg2e16_v_i16m1x2(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e16_v_i16m2x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.nxv8i16.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e16_v_i16m2x2(int16_t *base, vint16m2x2_t v_tuple, size_t vl) { + return __riscv_th_vsseg2e16_v_i16m2x2(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e16_v_i16m4x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.nxv16i16.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e16_v_i16m4x2(int16_t *base, vint16m4x2_t v_tuple, size_t vl) { + return __riscv_th_vsseg2e16_v_i16m4x2(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e16_v_u16m1x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.nxv4i16.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e16_v_u16m1x2(uint16_t *base, vuint16m1x2_t v_tuple, size_t vl) { + return __riscv_th_vsseg2e16_v_u16m1x2(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e16_v_u16m2x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.nxv8i16.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e16_v_u16m2x2(uint16_t *base, vuint16m2x2_t v_tuple, size_t vl) { + return __riscv_th_vsseg2e16_v_u16m2x2(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e16_v_u16m4x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.nxv16i16.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e16_v_u16m4x2(uint16_t *base, vuint16m4x2_t v_tuple, size_t vl) { + return __riscv_th_vsseg2e16_v_u16m4x2(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e16_v_f16m1x2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.mask.nxv4f16.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e16_v_f16m1x2_m(vbool16_t mask, _Float16 *base, vfloat16m1x2_t v_tuple, size_t vl) { + return __riscv_th_vsseg2e16_v_f16m1x2_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e16_v_f16m2x2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.mask.nxv8f16.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e16_v_f16m2x2_m(vbool8_t mask, _Float16 *base, vfloat16m2x2_t v_tuple, size_t vl) { + return __riscv_th_vsseg2e16_v_f16m2x2_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e16_v_f16m4x2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.mask.nxv16f16.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e16_v_f16m4x2_m(vbool4_t mask, _Float16 *base, vfloat16m4x2_t v_tuple, size_t vl) { + return __riscv_th_vsseg2e16_v_f16m4x2_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e16_v_i16m1x2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.mask.nxv4i16.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e16_v_i16m1x2_m(vbool16_t mask, int16_t *base, vint16m1x2_t v_tuple, size_t vl) { + return __riscv_th_vsseg2e16_v_i16m1x2_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e16_v_i16m2x2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.mask.nxv8i16.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e16_v_i16m2x2_m(vbool8_t mask, int16_t *base, vint16m2x2_t v_tuple, size_t vl) { + return __riscv_th_vsseg2e16_v_i16m2x2_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e16_v_i16m4x2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.mask.nxv16i16.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e16_v_i16m4x2_m(vbool4_t mask, int16_t *base, vint16m4x2_t v_tuple, size_t vl) { + return __riscv_th_vsseg2e16_v_i16m4x2_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e16_v_u16m1x2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.mask.nxv4i16.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e16_v_u16m1x2_m(vbool16_t mask, uint16_t *base, vuint16m1x2_t v_tuple, size_t vl) { + return __riscv_th_vsseg2e16_v_u16m1x2_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e16_v_u16m2x2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.mask.nxv8i16.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e16_v_u16m2x2_m(vbool8_t mask, uint16_t *base, vuint16m2x2_t v_tuple, size_t vl) { + return __riscv_th_vsseg2e16_v_u16m2x2_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e16_v_u16m4x2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.mask.nxv16i16.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e16_v_u16m4x2_m(vbool4_t mask, uint16_t *base, vuint16m4x2_t v_tuple, size_t vl) { + return __riscv_th_vsseg2e16_v_u16m4x2_m(mask, base, v_tuple, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg2e32.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg2e32.c new file mode 100644 index 00000000000000..b4035d599228b1 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg2e32.c @@ -0,0 +1,260 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e32_v_f32m1x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.nxv2f32.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e32_v_f32m1x2(float *base, vfloat32m1x2_t v_tuple, size_t vl) { + return __riscv_th_vsseg2e32_v_f32m1x2(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e32_v_f32m2x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.nxv4f32.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e32_v_f32m2x2(float *base, vfloat32m2x2_t v_tuple, size_t vl) { + return __riscv_th_vsseg2e32_v_f32m2x2(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e32_v_f32m4x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.nxv8f32.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e32_v_f32m4x2(float *base, vfloat32m4x2_t v_tuple, size_t vl) { + return __riscv_th_vsseg2e32_v_f32m4x2(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e32_v_i32m1x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.nxv2i32.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e32_v_i32m1x2(int32_t *base, vint32m1x2_t v_tuple, size_t vl) { + return __riscv_th_vsseg2e32_v_i32m1x2(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e32_v_i32m2x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.nxv4i32.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e32_v_i32m2x2(int32_t *base, vint32m2x2_t v_tuple, size_t vl) { + return __riscv_th_vsseg2e32_v_i32m2x2(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e32_v_i32m4x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.nxv8i32.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e32_v_i32m4x2(int32_t *base, vint32m4x2_t v_tuple, size_t vl) { + return __riscv_th_vsseg2e32_v_i32m4x2(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e32_v_u32m1x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.nxv2i32.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e32_v_u32m1x2(uint32_t *base, vuint32m1x2_t v_tuple, size_t vl) { + return __riscv_th_vsseg2e32_v_u32m1x2(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e32_v_u32m2x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.nxv4i32.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e32_v_u32m2x2(uint32_t *base, vuint32m2x2_t v_tuple, size_t vl) { + return __riscv_th_vsseg2e32_v_u32m2x2(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e32_v_u32m4x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.nxv8i32.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e32_v_u32m4x2(uint32_t *base, vuint32m4x2_t v_tuple, size_t vl) { + return __riscv_th_vsseg2e32_v_u32m4x2(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e32_v_f32m1x2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.mask.nxv2f32.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e32_v_f32m1x2_m(vbool32_t mask, float *base, vfloat32m1x2_t v_tuple, size_t vl) { + return __riscv_th_vsseg2e32_v_f32m1x2_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e32_v_f32m2x2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.mask.nxv4f32.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e32_v_f32m2x2_m(vbool16_t mask, float *base, vfloat32m2x2_t v_tuple, size_t vl) { + return __riscv_th_vsseg2e32_v_f32m2x2_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e32_v_f32m4x2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.mask.nxv8f32.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e32_v_f32m4x2_m(vbool8_t mask, float *base, vfloat32m4x2_t v_tuple, size_t vl) { + return __riscv_th_vsseg2e32_v_f32m4x2_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e32_v_i32m1x2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.mask.nxv2i32.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e32_v_i32m1x2_m(vbool32_t mask, int32_t *base, vint32m1x2_t v_tuple, size_t vl) { + return __riscv_th_vsseg2e32_v_i32m1x2_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e32_v_i32m2x2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.mask.nxv4i32.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e32_v_i32m2x2_m(vbool16_t mask, int32_t *base, vint32m2x2_t v_tuple, size_t vl) { + return __riscv_th_vsseg2e32_v_i32m2x2_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e32_v_i32m4x2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.mask.nxv8i32.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e32_v_i32m4x2_m(vbool8_t mask, int32_t *base, vint32m4x2_t v_tuple, size_t vl) { + return __riscv_th_vsseg2e32_v_i32m4x2_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e32_v_u32m1x2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.mask.nxv2i32.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e32_v_u32m1x2_m(vbool32_t mask, uint32_t *base, vuint32m1x2_t v_tuple, size_t vl) { + return __riscv_th_vsseg2e32_v_u32m1x2_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e32_v_u32m2x2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.mask.nxv4i32.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e32_v_u32m2x2_m(vbool16_t mask, uint32_t *base, vuint32m2x2_t v_tuple, size_t vl) { + return __riscv_th_vsseg2e32_v_u32m2x2_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e32_v_u32m4x2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.mask.nxv8i32.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e32_v_u32m4x2_m(vbool8_t mask, uint32_t *base, vuint32m4x2_t v_tuple, size_t vl) { + return __riscv_th_vsseg2e32_v_u32m4x2_m(mask, base, v_tuple, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg2e64.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg2e64.c new file mode 100644 index 00000000000000..67fdc0e84b7cd0 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg2e64.c @@ -0,0 +1,260 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e64_v_f64m1x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.nxv1f64.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e64_v_f64m1x2(double *base, vfloat64m1x2_t v_tuple, size_t vl) { + return __riscv_th_vsseg2e64_v_f64m1x2(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e64_v_f64m2x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.nxv2f64.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e64_v_f64m2x2(double *base, vfloat64m2x2_t v_tuple, size_t vl) { + return __riscv_th_vsseg2e64_v_f64m2x2(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e64_v_f64m4x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.nxv4f64.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e64_v_f64m4x2(double *base, vfloat64m4x2_t v_tuple, size_t vl) { + return __riscv_th_vsseg2e64_v_f64m4x2(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e64_v_i64m1x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.nxv1i64.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e64_v_i64m1x2(int64_t *base, vint64m1x2_t v_tuple, size_t vl) { + return __riscv_th_vsseg2e64_v_i64m1x2(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e64_v_i64m2x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.nxv2i64.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e64_v_i64m2x2(int64_t *base, vint64m2x2_t v_tuple, size_t vl) { + return __riscv_th_vsseg2e64_v_i64m2x2(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e64_v_i64m4x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.nxv4i64.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e64_v_i64m4x2(int64_t *base, vint64m4x2_t v_tuple, size_t vl) { + return __riscv_th_vsseg2e64_v_i64m4x2(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e64_v_u64m1x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.nxv1i64.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e64_v_u64m1x2(uint64_t *base, vuint64m1x2_t v_tuple, size_t vl) { + return __riscv_th_vsseg2e64_v_u64m1x2(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e64_v_u64m2x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.nxv2i64.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e64_v_u64m2x2(uint64_t *base, vuint64m2x2_t v_tuple, size_t vl) { + return __riscv_th_vsseg2e64_v_u64m2x2(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e64_v_u64m4x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.nxv4i64.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e64_v_u64m4x2(uint64_t *base, vuint64m4x2_t v_tuple, size_t vl) { + return __riscv_th_vsseg2e64_v_u64m4x2(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e64_v_f64m1x2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.mask.nxv1f64.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e64_v_f64m1x2_m(vbool64_t mask, double *base, vfloat64m1x2_t v_tuple, size_t vl) { + return __riscv_th_vsseg2e64_v_f64m1x2_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e64_v_f64m2x2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.mask.nxv2f64.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e64_v_f64m2x2_m(vbool32_t mask, double *base, vfloat64m2x2_t v_tuple, size_t vl) { + return __riscv_th_vsseg2e64_v_f64m2x2_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e64_v_f64m4x2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.mask.nxv4f64.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e64_v_f64m4x2_m(vbool16_t mask, double *base, vfloat64m4x2_t v_tuple, size_t vl) { + return __riscv_th_vsseg2e64_v_f64m4x2_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e64_v_i64m1x2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.mask.nxv1i64.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e64_v_i64m1x2_m(vbool64_t mask, int64_t *base, vint64m1x2_t v_tuple, size_t vl) { + return __riscv_th_vsseg2e64_v_i64m1x2_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e64_v_i64m2x2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.mask.nxv2i64.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e64_v_i64m2x2_m(vbool32_t mask, int64_t *base, vint64m2x2_t v_tuple, size_t vl) { + return __riscv_th_vsseg2e64_v_i64m2x2_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e64_v_i64m4x2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.mask.nxv4i64.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e64_v_i64m4x2_m(vbool16_t mask, int64_t *base, vint64m4x2_t v_tuple, size_t vl) { + return __riscv_th_vsseg2e64_v_i64m4x2_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e64_v_u64m1x2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.mask.nxv1i64.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e64_v_u64m1x2_m(vbool64_t mask, uint64_t *base, vuint64m1x2_t v_tuple, size_t vl) { + return __riscv_th_vsseg2e64_v_u64m1x2_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e64_v_u64m2x2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.mask.nxv2i64.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e64_v_u64m2x2_m(vbool32_t mask, uint64_t *base, vuint64m2x2_t v_tuple, size_t vl) { + return __riscv_th_vsseg2e64_v_u64m2x2_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e64_v_u64m4x2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.mask.nxv4i64.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e64_v_u64m4x2_m(vbool16_t mask, uint64_t *base, vuint64m4x2_t v_tuple, size_t vl) { + return __riscv_th_vsseg2e64_v_u64m4x2_m(mask, base, v_tuple, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg2e8.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg2e8.c new file mode 100644 index 00000000000000..2d89aae6217e88 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg2e8.c @@ -0,0 +1,176 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e8_v_i8m1x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.nxv8i8.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e8_v_i8m1x2(int8_t *base, vint8m1x2_t v_tuple, size_t vl) { + return __riscv_th_vsseg2e8_v_i8m1x2(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e8_v_i8m2x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.nxv16i8.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e8_v_i8m2x2(int8_t *base, vint8m2x2_t v_tuple, size_t vl) { + return __riscv_th_vsseg2e8_v_i8m2x2(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e8_v_i8m4x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.nxv32i8.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e8_v_i8m4x2(int8_t *base, vint8m4x2_t v_tuple, size_t vl) { + return __riscv_th_vsseg2e8_v_i8m4x2(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e8_v_u8m1x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.nxv8i8.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e8_v_u8m1x2(uint8_t *base, vuint8m1x2_t v_tuple, size_t vl) { + return __riscv_th_vsseg2e8_v_u8m1x2(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e8_v_u8m2x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.nxv16i8.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e8_v_u8m2x2(uint8_t *base, vuint8m2x2_t v_tuple, size_t vl) { + return __riscv_th_vsseg2e8_v_u8m2x2(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e8_v_u8m4x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.nxv32i8.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e8_v_u8m4x2(uint8_t *base, vuint8m4x2_t v_tuple, size_t vl) { + return __riscv_th_vsseg2e8_v_u8m4x2(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e8_v_i8m1x2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.mask.nxv8i8.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e8_v_i8m1x2_m(vbool8_t mask, int8_t *base, vint8m1x2_t v_tuple, size_t vl) { + return __riscv_th_vsseg2e8_v_i8m1x2_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e8_v_i8m2x2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.mask.nxv16i8.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e8_v_i8m2x2_m(vbool4_t mask, int8_t *base, vint8m2x2_t v_tuple, size_t vl) { + return __riscv_th_vsseg2e8_v_i8m2x2_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e8_v_i8m4x2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.mask.nxv32i8.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e8_v_i8m4x2_m(vbool2_t mask, int8_t *base, vint8m4x2_t v_tuple, size_t vl) { + return __riscv_th_vsseg2e8_v_i8m4x2_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e8_v_u8m1x2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.mask.nxv8i8.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e8_v_u8m1x2_m(vbool8_t mask, uint8_t *base, vuint8m1x2_t v_tuple, size_t vl) { + return __riscv_th_vsseg2e8_v_u8m1x2_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e8_v_u8m2x2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.mask.nxv16i8.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e8_v_u8m2x2_m(vbool4_t mask, uint8_t *base, vuint8m2x2_t v_tuple, size_t vl) { + return __riscv_th_vsseg2e8_v_u8m2x2_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e8_v_u8m4x2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.mask.nxv32i8.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e8_v_u8m4x2_m(vbool2_t mask, uint8_t *base, vuint8m4x2_t v_tuple, size_t vl) { + return __riscv_th_vsseg2e8_v_u8m4x2_m(mask, base, v_tuple, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg3e16.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg3e16.c new file mode 100644 index 00000000000000..86da2184ad2531 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg3e16.c @@ -0,0 +1,200 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg3e16_v_f16m1x3 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , } [[TMP2]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg3e.nxv4f16.i64( [[TMP3]], [[TMP4]], [[TMP5]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg3e16_v_f16m1x3(_Float16 *base, vfloat16m1x3_t v_tuple, size_t vl) { + return __riscv_th_vsseg3e16_v_f16m1x3(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg3e16_v_f16m2x3 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , } [[TMP2]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg3e.nxv8f16.i64( [[TMP3]], [[TMP4]], [[TMP5]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg3e16_v_f16m2x3(_Float16 *base, vfloat16m2x3_t v_tuple, size_t vl) { + return __riscv_th_vsseg3e16_v_f16m2x3(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg3e16_v_i16m1x3 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , } [[TMP2]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg3e.nxv4i16.i64( [[TMP3]], [[TMP4]], [[TMP5]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg3e16_v_i16m1x3(int16_t *base, vint16m1x3_t v_tuple, size_t vl) { + return __riscv_th_vsseg3e16_v_i16m1x3(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg3e16_v_i16m2x3 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , } [[TMP2]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg3e.nxv8i16.i64( [[TMP3]], [[TMP4]], [[TMP5]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg3e16_v_i16m2x3(int16_t *base, vint16m2x3_t v_tuple, size_t vl) { + return __riscv_th_vsseg3e16_v_i16m2x3(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg3e16_v_u16m1x3 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , } [[TMP2]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg3e.nxv4i16.i64( [[TMP3]], [[TMP4]], [[TMP5]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg3e16_v_u16m1x3(uint16_t *base, vuint16m1x3_t v_tuple, size_t vl) { + return __riscv_th_vsseg3e16_v_u16m1x3(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg3e16_v_u16m2x3 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , } [[TMP2]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg3e.nxv8i16.i64( [[TMP3]], [[TMP4]], [[TMP5]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg3e16_v_u16m2x3(uint16_t *base, vuint16m2x3_t v_tuple, size_t vl) { + return __riscv_th_vsseg3e16_v_u16m2x3(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg3e16_v_f16m1x3_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , } [[TMP2]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg3e.mask.nxv4f16.i64( [[TMP3]], [[TMP4]], [[TMP5]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg3e16_v_f16m1x3_m(vbool16_t mask, _Float16 *base, vfloat16m1x3_t v_tuple, size_t vl) { + return __riscv_th_vsseg3e16_v_f16m1x3_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg3e16_v_f16m2x3_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , } [[TMP2]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg3e.mask.nxv8f16.i64( [[TMP3]], [[TMP4]], [[TMP5]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg3e16_v_f16m2x3_m(vbool8_t mask, _Float16 *base, vfloat16m2x3_t v_tuple, size_t vl) { + return __riscv_th_vsseg3e16_v_f16m2x3_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg3e16_v_i16m1x3_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , } [[TMP2]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg3e.mask.nxv4i16.i64( [[TMP3]], [[TMP4]], [[TMP5]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg3e16_v_i16m1x3_m(vbool16_t mask, int16_t *base, vint16m1x3_t v_tuple, size_t vl) { + return __riscv_th_vsseg3e16_v_i16m1x3_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg3e16_v_i16m2x3_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , } [[TMP2]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg3e.mask.nxv8i16.i64( [[TMP3]], [[TMP4]], [[TMP5]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg3e16_v_i16m2x3_m(vbool8_t mask, int16_t *base, vint16m2x3_t v_tuple, size_t vl) { + return __riscv_th_vsseg3e16_v_i16m2x3_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg3e16_v_u16m1x3_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , } [[TMP2]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg3e.mask.nxv4i16.i64( [[TMP3]], [[TMP4]], [[TMP5]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg3e16_v_u16m1x3_m(vbool16_t mask, uint16_t *base, vuint16m1x3_t v_tuple, size_t vl) { + return __riscv_th_vsseg3e16_v_u16m1x3_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg3e16_v_u16m2x3_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , } [[TMP2]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg3e.mask.nxv8i16.i64( [[TMP3]], [[TMP4]], [[TMP5]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg3e16_v_u16m2x3_m(vbool8_t mask, uint16_t *base, vuint16m2x3_t v_tuple, size_t vl) { + return __riscv_th_vsseg3e16_v_u16m2x3_m(mask, base, v_tuple, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg3e32.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg3e32.c new file mode 100644 index 00000000000000..1553644663acb6 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg3e32.c @@ -0,0 +1,200 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg3e32_v_f32m1x3 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , } [[TMP2]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg3e.nxv2f32.i64( [[TMP3]], [[TMP4]], [[TMP5]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg3e32_v_f32m1x3(float *base, vfloat32m1x3_t v_tuple, size_t vl) { + return __riscv_th_vsseg3e32_v_f32m1x3(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg3e32_v_f32m2x3 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , } [[TMP2]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg3e.nxv4f32.i64( [[TMP3]], [[TMP4]], [[TMP5]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg3e32_v_f32m2x3(float *base, vfloat32m2x3_t v_tuple, size_t vl) { + return __riscv_th_vsseg3e32_v_f32m2x3(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg3e32_v_i32m1x3 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , } [[TMP2]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg3e.nxv2i32.i64( [[TMP3]], [[TMP4]], [[TMP5]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg3e32_v_i32m1x3(int32_t *base, vint32m1x3_t v_tuple, size_t vl) { + return __riscv_th_vsseg3e32_v_i32m1x3(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg3e32_v_i32m2x3 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , } [[TMP2]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg3e.nxv4i32.i64( [[TMP3]], [[TMP4]], [[TMP5]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg3e32_v_i32m2x3(int32_t *base, vint32m2x3_t v_tuple, size_t vl) { + return __riscv_th_vsseg3e32_v_i32m2x3(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg3e32_v_u32m1x3 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , } [[TMP2]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg3e.nxv2i32.i64( [[TMP3]], [[TMP4]], [[TMP5]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg3e32_v_u32m1x3(uint32_t *base, vuint32m1x3_t v_tuple, size_t vl) { + return __riscv_th_vsseg3e32_v_u32m1x3(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg3e32_v_u32m2x3 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , } [[TMP2]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg3e.nxv4i32.i64( [[TMP3]], [[TMP4]], [[TMP5]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg3e32_v_u32m2x3(uint32_t *base, vuint32m2x3_t v_tuple, size_t vl) { + return __riscv_th_vsseg3e32_v_u32m2x3(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg3e32_v_f32m1x3_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , } [[TMP2]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg3e.mask.nxv2f32.i64( [[TMP3]], [[TMP4]], [[TMP5]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg3e32_v_f32m1x3_m(vbool32_t mask, float *base, vfloat32m1x3_t v_tuple, size_t vl) { + return __riscv_th_vsseg3e32_v_f32m1x3_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg3e32_v_f32m2x3_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , } [[TMP2]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg3e.mask.nxv4f32.i64( [[TMP3]], [[TMP4]], [[TMP5]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg3e32_v_f32m2x3_m(vbool16_t mask, float *base, vfloat32m2x3_t v_tuple, size_t vl) { + return __riscv_th_vsseg3e32_v_f32m2x3_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg3e32_v_i32m1x3_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , } [[TMP2]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg3e.mask.nxv2i32.i64( [[TMP3]], [[TMP4]], [[TMP5]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg3e32_v_i32m1x3_m(vbool32_t mask, int32_t *base, vint32m1x3_t v_tuple, size_t vl) { + return __riscv_th_vsseg3e32_v_i32m1x3_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg3e32_v_i32m2x3_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , } [[TMP2]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg3e.mask.nxv4i32.i64( [[TMP3]], [[TMP4]], [[TMP5]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg3e32_v_i32m2x3_m(vbool16_t mask, int32_t *base, vint32m2x3_t v_tuple, size_t vl) { + return __riscv_th_vsseg3e32_v_i32m2x3_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg3e32_v_u32m1x3_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , } [[TMP2]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg3e.mask.nxv2i32.i64( [[TMP3]], [[TMP4]], [[TMP5]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg3e32_v_u32m1x3_m(vbool32_t mask, uint32_t *base, vuint32m1x3_t v_tuple, size_t vl) { + return __riscv_th_vsseg3e32_v_u32m1x3_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg3e32_v_u32m2x3_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , } [[TMP2]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg3e.mask.nxv4i32.i64( [[TMP3]], [[TMP4]], [[TMP5]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg3e32_v_u32m2x3_m(vbool16_t mask, uint32_t *base, vuint32m2x3_t v_tuple, size_t vl) { + return __riscv_th_vsseg3e32_v_u32m2x3_m(mask, base, v_tuple, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg3e64.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg3e64.c new file mode 100644 index 00000000000000..a2e91447811f81 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg3e64.c @@ -0,0 +1,200 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg3e64_v_f64m1x3 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , } [[TMP2]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg3e.nxv1f64.i64( [[TMP3]], [[TMP4]], [[TMP5]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg3e64_v_f64m1x3(double *base, vfloat64m1x3_t v_tuple, size_t vl) { + return __riscv_th_vsseg3e64_v_f64m1x3(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg3e64_v_f64m2x3 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , } [[TMP2]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg3e.nxv2f64.i64( [[TMP3]], [[TMP4]], [[TMP5]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg3e64_v_f64m2x3(double *base, vfloat64m2x3_t v_tuple, size_t vl) { + return __riscv_th_vsseg3e64_v_f64m2x3(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg3e64_v_i64m1x3 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , } [[TMP2]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg3e.nxv1i64.i64( [[TMP3]], [[TMP4]], [[TMP5]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg3e64_v_i64m1x3(int64_t *base, vint64m1x3_t v_tuple, size_t vl) { + return __riscv_th_vsseg3e64_v_i64m1x3(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg3e64_v_i64m2x3 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , } [[TMP2]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg3e.nxv2i64.i64( [[TMP3]], [[TMP4]], [[TMP5]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg3e64_v_i64m2x3(int64_t *base, vint64m2x3_t v_tuple, size_t vl) { + return __riscv_th_vsseg3e64_v_i64m2x3(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg3e64_v_u64m1x3 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , } [[TMP2]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg3e.nxv1i64.i64( [[TMP3]], [[TMP4]], [[TMP5]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg3e64_v_u64m1x3(uint64_t *base, vuint64m1x3_t v_tuple, size_t vl) { + return __riscv_th_vsseg3e64_v_u64m1x3(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg3e64_v_u64m2x3 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , } [[TMP2]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg3e.nxv2i64.i64( [[TMP3]], [[TMP4]], [[TMP5]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg3e64_v_u64m2x3(uint64_t *base, vuint64m2x3_t v_tuple, size_t vl) { + return __riscv_th_vsseg3e64_v_u64m2x3(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg3e64_v_f64m1x3_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , } [[TMP2]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg3e.mask.nxv1f64.i64( [[TMP3]], [[TMP4]], [[TMP5]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg3e64_v_f64m1x3_m(vbool64_t mask, double *base, vfloat64m1x3_t v_tuple, size_t vl) { + return __riscv_th_vsseg3e64_v_f64m1x3_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg3e64_v_f64m2x3_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , } [[TMP2]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg3e.mask.nxv2f64.i64( [[TMP3]], [[TMP4]], [[TMP5]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg3e64_v_f64m2x3_m(vbool32_t mask, double *base, vfloat64m2x3_t v_tuple, size_t vl) { + return __riscv_th_vsseg3e64_v_f64m2x3_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg3e64_v_i64m1x3_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , } [[TMP2]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg3e.mask.nxv1i64.i64( [[TMP3]], [[TMP4]], [[TMP5]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg3e64_v_i64m1x3_m(vbool64_t mask, int64_t *base, vint64m1x3_t v_tuple, size_t vl) { + return __riscv_th_vsseg3e64_v_i64m1x3_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg3e64_v_i64m2x3_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , } [[TMP2]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg3e.mask.nxv2i64.i64( [[TMP3]], [[TMP4]], [[TMP5]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg3e64_v_i64m2x3_m(vbool32_t mask, int64_t *base, vint64m2x3_t v_tuple, size_t vl) { + return __riscv_th_vsseg3e64_v_i64m2x3_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg3e64_v_u64m1x3_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , } [[TMP2]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg3e.mask.nxv1i64.i64( [[TMP3]], [[TMP4]], [[TMP5]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg3e64_v_u64m1x3_m(vbool64_t mask, uint64_t *base, vuint64m1x3_t v_tuple, size_t vl) { + return __riscv_th_vsseg3e64_v_u64m1x3_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg3e64_v_u64m2x3_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , } [[TMP2]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg3e.mask.nxv2i64.i64( [[TMP3]], [[TMP4]], [[TMP5]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg3e64_v_u64m2x3_m(vbool32_t mask, uint64_t *base, vuint64m2x3_t v_tuple, size_t vl) { + return __riscv_th_vsseg3e64_v_u64m2x3_m(mask, base, v_tuple, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg3e8.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg3e8.c new file mode 100644 index 00000000000000..da961bed2b1a7d --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg3e8.c @@ -0,0 +1,136 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg3e8_v_i8m1x3 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , } [[TMP2]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg3e.nxv8i8.i64( [[TMP3]], [[TMP4]], [[TMP5]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg3e8_v_i8m1x3(int8_t *base, vint8m1x3_t v_tuple, size_t vl) { + return __riscv_th_vsseg3e8_v_i8m1x3(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg3e8_v_i8m2x3 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , } [[TMP2]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg3e.nxv16i8.i64( [[TMP3]], [[TMP4]], [[TMP5]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg3e8_v_i8m2x3(int8_t *base, vint8m2x3_t v_tuple, size_t vl) { + return __riscv_th_vsseg3e8_v_i8m2x3(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg3e8_v_u8m1x3 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , } [[TMP2]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg3e.nxv8i8.i64( [[TMP3]], [[TMP4]], [[TMP5]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg3e8_v_u8m1x3(uint8_t *base, vuint8m1x3_t v_tuple, size_t vl) { + return __riscv_th_vsseg3e8_v_u8m1x3(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg3e8_v_u8m2x3 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , } [[TMP2]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg3e.nxv16i8.i64( [[TMP3]], [[TMP4]], [[TMP5]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg3e8_v_u8m2x3(uint8_t *base, vuint8m2x3_t v_tuple, size_t vl) { + return __riscv_th_vsseg3e8_v_u8m2x3(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg3e8_v_i8m1x3_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , } [[TMP2]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg3e.mask.nxv8i8.i64( [[TMP3]], [[TMP4]], [[TMP5]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg3e8_v_i8m1x3_m(vbool8_t mask, int8_t *base, vint8m1x3_t v_tuple, size_t vl) { + return __riscv_th_vsseg3e8_v_i8m1x3_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg3e8_v_i8m2x3_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , } [[TMP2]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg3e.mask.nxv16i8.i64( [[TMP3]], [[TMP4]], [[TMP5]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg3e8_v_i8m2x3_m(vbool4_t mask, int8_t *base, vint8m2x3_t v_tuple, size_t vl) { + return __riscv_th_vsseg3e8_v_i8m2x3_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg3e8_v_u8m1x3_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , } [[TMP2]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg3e.mask.nxv8i8.i64( [[TMP3]], [[TMP4]], [[TMP5]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg3e8_v_u8m1x3_m(vbool8_t mask, uint8_t *base, vuint8m1x3_t v_tuple, size_t vl) { + return __riscv_th_vsseg3e8_v_u8m1x3_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg3e8_v_u8m2x3_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , } [[TMP2]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg3e.mask.nxv16i8.i64( [[TMP3]], [[TMP4]], [[TMP5]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg3e8_v_u8m2x3_m(vbool4_t mask, uint8_t *base, vuint8m2x3_t v_tuple, size_t vl) { + return __riscv_th_vsseg3e8_v_u8m2x3_m(mask, base, v_tuple, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg4e16.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg4e16.c new file mode 100644 index 00000000000000..c0c42765a120d7 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg4e16.c @@ -0,0 +1,224 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg4e16_v_f16m1x4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg4e.nxv4f16.i64( [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg4e16_v_f16m1x4(_Float16 *base, vfloat16m1x4_t v_tuple, size_t vl) { + return __riscv_th_vsseg4e16_v_f16m1x4(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg4e16_v_f16m2x4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg4e.nxv8f16.i64( [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg4e16_v_f16m2x4(_Float16 *base, vfloat16m2x4_t v_tuple, size_t vl) { + return __riscv_th_vsseg4e16_v_f16m2x4(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg4e16_v_i16m1x4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg4e.nxv4i16.i64( [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg4e16_v_i16m1x4(int16_t *base, vint16m1x4_t v_tuple, size_t vl) { + return __riscv_th_vsseg4e16_v_i16m1x4(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg4e16_v_i16m2x4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg4e.nxv8i16.i64( [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg4e16_v_i16m2x4(int16_t *base, vint16m2x4_t v_tuple, size_t vl) { + return __riscv_th_vsseg4e16_v_i16m2x4(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg4e16_v_u16m1x4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg4e.nxv4i16.i64( [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg4e16_v_u16m1x4(uint16_t *base, vuint16m1x4_t v_tuple, size_t vl) { + return __riscv_th_vsseg4e16_v_u16m1x4(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg4e16_v_u16m2x4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg4e.nxv8i16.i64( [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg4e16_v_u16m2x4(uint16_t *base, vuint16m2x4_t v_tuple, size_t vl) { + return __riscv_th_vsseg4e16_v_u16m2x4(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg4e16_v_f16m1x4_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg4e.mask.nxv4f16.i64( [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg4e16_v_f16m1x4_m(vbool16_t mask, _Float16 *base, vfloat16m1x4_t v_tuple, size_t vl) { + return __riscv_th_vsseg4e16_v_f16m1x4_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg4e16_v_f16m2x4_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg4e.mask.nxv8f16.i64( [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg4e16_v_f16m2x4_m(vbool8_t mask, _Float16 *base, vfloat16m2x4_t v_tuple, size_t vl) { + return __riscv_th_vsseg4e16_v_f16m2x4_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg4e16_v_i16m1x4_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg4e.mask.nxv4i16.i64( [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg4e16_v_i16m1x4_m(vbool16_t mask, int16_t *base, vint16m1x4_t v_tuple, size_t vl) { + return __riscv_th_vsseg4e16_v_i16m1x4_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg4e16_v_i16m2x4_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg4e.mask.nxv8i16.i64( [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg4e16_v_i16m2x4_m(vbool8_t mask, int16_t *base, vint16m2x4_t v_tuple, size_t vl) { + return __riscv_th_vsseg4e16_v_i16m2x4_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg4e16_v_u16m1x4_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg4e.mask.nxv4i16.i64( [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg4e16_v_u16m1x4_m(vbool16_t mask, uint16_t *base, vuint16m1x4_t v_tuple, size_t vl) { + return __riscv_th_vsseg4e16_v_u16m1x4_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg4e16_v_u16m2x4_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg4e.mask.nxv8i16.i64( [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg4e16_v_u16m2x4_m(vbool8_t mask, uint16_t *base, vuint16m2x4_t v_tuple, size_t vl) { + return __riscv_th_vsseg4e16_v_u16m2x4_m(mask, base, v_tuple, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg4e32.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg4e32.c new file mode 100644 index 00000000000000..eda336f16c837b --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg4e32.c @@ -0,0 +1,224 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg4e32_v_f32m1x4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg4e.nxv2f32.i64( [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg4e32_v_f32m1x4(float *base, vfloat32m1x4_t v_tuple, size_t vl) { + return __riscv_th_vsseg4e32_v_f32m1x4(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg4e32_v_f32m2x4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg4e.nxv4f32.i64( [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg4e32_v_f32m2x4(float *base, vfloat32m2x4_t v_tuple, size_t vl) { + return __riscv_th_vsseg4e32_v_f32m2x4(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg4e32_v_i32m1x4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg4e.nxv2i32.i64( [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg4e32_v_i32m1x4(int32_t *base, vint32m1x4_t v_tuple, size_t vl) { + return __riscv_th_vsseg4e32_v_i32m1x4(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg4e32_v_i32m2x4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg4e.nxv4i32.i64( [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg4e32_v_i32m2x4(int32_t *base, vint32m2x4_t v_tuple, size_t vl) { + return __riscv_th_vsseg4e32_v_i32m2x4(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg4e32_v_u32m1x4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg4e.nxv2i32.i64( [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg4e32_v_u32m1x4(uint32_t *base, vuint32m1x4_t v_tuple, size_t vl) { + return __riscv_th_vsseg4e32_v_u32m1x4(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg4e32_v_u32m2x4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg4e.nxv4i32.i64( [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg4e32_v_u32m2x4(uint32_t *base, vuint32m2x4_t v_tuple, size_t vl) { + return __riscv_th_vsseg4e32_v_u32m2x4(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg4e32_v_f32m1x4_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg4e.mask.nxv2f32.i64( [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg4e32_v_f32m1x4_m(vbool32_t mask, float *base, vfloat32m1x4_t v_tuple, size_t vl) { + return __riscv_th_vsseg4e32_v_f32m1x4_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg4e32_v_f32m2x4_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg4e.mask.nxv4f32.i64( [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg4e32_v_f32m2x4_m(vbool16_t mask, float *base, vfloat32m2x4_t v_tuple, size_t vl) { + return __riscv_th_vsseg4e32_v_f32m2x4_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg4e32_v_i32m1x4_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg4e.mask.nxv2i32.i64( [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg4e32_v_i32m1x4_m(vbool32_t mask, int32_t *base, vint32m1x4_t v_tuple, size_t vl) { + return __riscv_th_vsseg4e32_v_i32m1x4_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg4e32_v_i32m2x4_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg4e.mask.nxv4i32.i64( [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg4e32_v_i32m2x4_m(vbool16_t mask, int32_t *base, vint32m2x4_t v_tuple, size_t vl) { + return __riscv_th_vsseg4e32_v_i32m2x4_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg4e32_v_u32m1x4_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg4e.mask.nxv2i32.i64( [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg4e32_v_u32m1x4_m(vbool32_t mask, uint32_t *base, vuint32m1x4_t v_tuple, size_t vl) { + return __riscv_th_vsseg4e32_v_u32m1x4_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg4e32_v_u32m2x4_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg4e.mask.nxv4i32.i64( [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg4e32_v_u32m2x4_m(vbool16_t mask, uint32_t *base, vuint32m2x4_t v_tuple, size_t vl) { + return __riscv_th_vsseg4e32_v_u32m2x4_m(mask, base, v_tuple, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg4e64.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg4e64.c new file mode 100644 index 00000000000000..8d7bedd4ecf639 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg4e64.c @@ -0,0 +1,224 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg4e64_v_f64m1x4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg4e.nxv1f64.i64( [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg4e64_v_f64m1x4(double *base, vfloat64m1x4_t v_tuple, size_t vl) { + return __riscv_th_vsseg4e64_v_f64m1x4(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg4e64_v_f64m2x4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg4e.nxv2f64.i64( [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg4e64_v_f64m2x4(double *base, vfloat64m2x4_t v_tuple, size_t vl) { + return __riscv_th_vsseg4e64_v_f64m2x4(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg4e64_v_i64m1x4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg4e.nxv1i64.i64( [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg4e64_v_i64m1x4(int64_t *base, vint64m1x4_t v_tuple, size_t vl) { + return __riscv_th_vsseg4e64_v_i64m1x4(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg4e64_v_i64m2x4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg4e.nxv2i64.i64( [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg4e64_v_i64m2x4(int64_t *base, vint64m2x4_t v_tuple, size_t vl) { + return __riscv_th_vsseg4e64_v_i64m2x4(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg4e64_v_u64m1x4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg4e.nxv1i64.i64( [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg4e64_v_u64m1x4(uint64_t *base, vuint64m1x4_t v_tuple, size_t vl) { + return __riscv_th_vsseg4e64_v_u64m1x4(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg4e64_v_u64m2x4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg4e.nxv2i64.i64( [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg4e64_v_u64m2x4(uint64_t *base, vuint64m2x4_t v_tuple, size_t vl) { + return __riscv_th_vsseg4e64_v_u64m2x4(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg4e64_v_f64m1x4_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg4e.mask.nxv1f64.i64( [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg4e64_v_f64m1x4_m(vbool64_t mask, double *base, vfloat64m1x4_t v_tuple, size_t vl) { + return __riscv_th_vsseg4e64_v_f64m1x4_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg4e64_v_f64m2x4_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg4e.mask.nxv2f64.i64( [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg4e64_v_f64m2x4_m(vbool32_t mask, double *base, vfloat64m2x4_t v_tuple, size_t vl) { + return __riscv_th_vsseg4e64_v_f64m2x4_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg4e64_v_i64m1x4_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg4e.mask.nxv1i64.i64( [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg4e64_v_i64m1x4_m(vbool64_t mask, int64_t *base, vint64m1x4_t v_tuple, size_t vl) { + return __riscv_th_vsseg4e64_v_i64m1x4_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg4e64_v_i64m2x4_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg4e.mask.nxv2i64.i64( [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg4e64_v_i64m2x4_m(vbool32_t mask, int64_t *base, vint64m2x4_t v_tuple, size_t vl) { + return __riscv_th_vsseg4e64_v_i64m2x4_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg4e64_v_u64m1x4_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg4e.mask.nxv1i64.i64( [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg4e64_v_u64m1x4_m(vbool64_t mask, uint64_t *base, vuint64m1x4_t v_tuple, size_t vl) { + return __riscv_th_vsseg4e64_v_u64m1x4_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg4e64_v_u64m2x4_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg4e.mask.nxv2i64.i64( [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg4e64_v_u64m2x4_m(vbool32_t mask, uint64_t *base, vuint64m2x4_t v_tuple, size_t vl) { + return __riscv_th_vsseg4e64_v_u64m2x4_m(mask, base, v_tuple, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg4e8.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg4e8.c new file mode 100644 index 00000000000000..6adce9b8080135 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg4e8.c @@ -0,0 +1,152 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg4e8_v_i8m1x4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg4e.nxv8i8.i64( [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg4e8_v_i8m1x4(int8_t *base, vint8m1x4_t v_tuple, size_t vl) { + return __riscv_th_vsseg4e8_v_i8m1x4(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg4e8_v_i8m2x4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg4e.nxv16i8.i64( [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg4e8_v_i8m2x4(int8_t *base, vint8m2x4_t v_tuple, size_t vl) { + return __riscv_th_vsseg4e8_v_i8m2x4(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg4e8_v_u8m1x4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg4e.nxv8i8.i64( [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg4e8_v_u8m1x4(uint8_t *base, vuint8m1x4_t v_tuple, size_t vl) { + return __riscv_th_vsseg4e8_v_u8m1x4(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg4e8_v_u8m2x4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg4e.nxv16i8.i64( [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg4e8_v_u8m2x4(uint8_t *base, vuint8m2x4_t v_tuple, size_t vl) { + return __riscv_th_vsseg4e8_v_u8m2x4(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg4e8_v_i8m1x4_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg4e.mask.nxv8i8.i64( [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg4e8_v_i8m1x4_m(vbool8_t mask, int8_t *base, vint8m1x4_t v_tuple, size_t vl) { + return __riscv_th_vsseg4e8_v_i8m1x4_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg4e8_v_i8m2x4_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg4e.mask.nxv16i8.i64( [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg4e8_v_i8m2x4_m(vbool4_t mask, int8_t *base, vint8m2x4_t v_tuple, size_t vl) { + return __riscv_th_vsseg4e8_v_i8m2x4_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg4e8_v_u8m1x4_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg4e.mask.nxv8i8.i64( [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg4e8_v_u8m1x4_m(vbool8_t mask, uint8_t *base, vuint8m1x4_t v_tuple, size_t vl) { + return __riscv_th_vsseg4e8_v_u8m1x4_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg4e8_v_u8m2x4_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg4e.mask.nxv16i8.i64( [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg4e8_v_u8m2x4_m(vbool4_t mask, uint8_t *base, vuint8m2x4_t v_tuple, size_t vl) { + return __riscv_th_vsseg4e8_v_u8m2x4_m(mask, base, v_tuple, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg5e16.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg5e16.c new file mode 100644 index 00000000000000..df403a11b6b9a5 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg5e16.c @@ -0,0 +1,128 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg5e16_v_f16m1x5 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , } [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , } [[TMP4]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , } [[TMP4]], 2 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , } [[TMP4]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , } [[TMP4]], 4 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg5e.nxv4f16.i64( [[TMP5]], [[TMP6]], [[TMP7]], [[TMP8]], [[TMP9]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg5e16_v_f16m1x5(_Float16 *base, vfloat16m1x5_t v_tuple, size_t vl) { + return __riscv_th_vsseg5e16_v_f16m1x5(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg5e16_v_i16m1x5 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , } [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , } [[TMP4]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , } [[TMP4]], 2 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , } [[TMP4]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , } [[TMP4]], 4 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg5e.nxv4i16.i64( [[TMP5]], [[TMP6]], [[TMP7]], [[TMP8]], [[TMP9]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg5e16_v_i16m1x5(int16_t *base, vint16m1x5_t v_tuple, size_t vl) { + return __riscv_th_vsseg5e16_v_i16m1x5(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg5e16_v_u16m1x5 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , } [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , } [[TMP4]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , } [[TMP4]], 2 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , } [[TMP4]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , } [[TMP4]], 4 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg5e.nxv4i16.i64( [[TMP5]], [[TMP6]], [[TMP7]], [[TMP8]], [[TMP9]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg5e16_v_u16m1x5(uint16_t *base, vuint16m1x5_t v_tuple, size_t vl) { + return __riscv_th_vsseg5e16_v_u16m1x5(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg5e16_v_f16m1x5_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , } [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , } [[TMP4]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , } [[TMP4]], 2 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , } [[TMP4]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , } [[TMP4]], 4 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg5e.mask.nxv4f16.i64( [[TMP5]], [[TMP6]], [[TMP7]], [[TMP8]], [[TMP9]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg5e16_v_f16m1x5_m(vbool16_t mask, _Float16 *base, vfloat16m1x5_t v_tuple, size_t vl) { + return __riscv_th_vsseg5e16_v_f16m1x5_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg5e16_v_i16m1x5_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , } [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , } [[TMP4]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , } [[TMP4]], 2 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , } [[TMP4]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , } [[TMP4]], 4 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg5e.mask.nxv4i16.i64( [[TMP5]], [[TMP6]], [[TMP7]], [[TMP8]], [[TMP9]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg5e16_v_i16m1x5_m(vbool16_t mask, int16_t *base, vint16m1x5_t v_tuple, size_t vl) { + return __riscv_th_vsseg5e16_v_i16m1x5_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg5e16_v_u16m1x5_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , } [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , } [[TMP4]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , } [[TMP4]], 2 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , } [[TMP4]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , } [[TMP4]], 4 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg5e.mask.nxv4i16.i64( [[TMP5]], [[TMP6]], [[TMP7]], [[TMP8]], [[TMP9]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg5e16_v_u16m1x5_m(vbool16_t mask, uint16_t *base, vuint16m1x5_t v_tuple, size_t vl) { + return __riscv_th_vsseg5e16_v_u16m1x5_m(mask, base, v_tuple, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg5e32.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg5e32.c new file mode 100644 index 00000000000000..2b32738c2c5b86 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg5e32.c @@ -0,0 +1,128 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg5e32_v_f32m1x5 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , } [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , } [[TMP4]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , } [[TMP4]], 2 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , } [[TMP4]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , } [[TMP4]], 4 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg5e.nxv2f32.i64( [[TMP5]], [[TMP6]], [[TMP7]], [[TMP8]], [[TMP9]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg5e32_v_f32m1x5(float *base, vfloat32m1x5_t v_tuple, size_t vl) { + return __riscv_th_vsseg5e32_v_f32m1x5(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg5e32_v_i32m1x5 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , } [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , } [[TMP4]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , } [[TMP4]], 2 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , } [[TMP4]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , } [[TMP4]], 4 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg5e.nxv2i32.i64( [[TMP5]], [[TMP6]], [[TMP7]], [[TMP8]], [[TMP9]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg5e32_v_i32m1x5(int32_t *base, vint32m1x5_t v_tuple, size_t vl) { + return __riscv_th_vsseg5e32_v_i32m1x5(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg5e32_v_u32m1x5 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , } [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , } [[TMP4]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , } [[TMP4]], 2 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , } [[TMP4]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , } [[TMP4]], 4 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg5e.nxv2i32.i64( [[TMP5]], [[TMP6]], [[TMP7]], [[TMP8]], [[TMP9]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg5e32_v_u32m1x5(uint32_t *base, vuint32m1x5_t v_tuple, size_t vl) { + return __riscv_th_vsseg5e32_v_u32m1x5(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg5e32_v_f32m1x5_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , } [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , } [[TMP4]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , } [[TMP4]], 2 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , } [[TMP4]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , } [[TMP4]], 4 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg5e.mask.nxv2f32.i64( [[TMP5]], [[TMP6]], [[TMP7]], [[TMP8]], [[TMP9]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg5e32_v_f32m1x5_m(vbool32_t mask, float *base, vfloat32m1x5_t v_tuple, size_t vl) { + return __riscv_th_vsseg5e32_v_f32m1x5_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg5e32_v_i32m1x5_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , } [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , } [[TMP4]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , } [[TMP4]], 2 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , } [[TMP4]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , } [[TMP4]], 4 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg5e.mask.nxv2i32.i64( [[TMP5]], [[TMP6]], [[TMP7]], [[TMP8]], [[TMP9]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg5e32_v_i32m1x5_m(vbool32_t mask, int32_t *base, vint32m1x5_t v_tuple, size_t vl) { + return __riscv_th_vsseg5e32_v_i32m1x5_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg5e32_v_u32m1x5_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , } [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , } [[TMP4]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , } [[TMP4]], 2 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , } [[TMP4]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , } [[TMP4]], 4 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg5e.mask.nxv2i32.i64( [[TMP5]], [[TMP6]], [[TMP7]], [[TMP8]], [[TMP9]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg5e32_v_u32m1x5_m(vbool32_t mask, uint32_t *base, vuint32m1x5_t v_tuple, size_t vl) { + return __riscv_th_vsseg5e32_v_u32m1x5_m(mask, base, v_tuple, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg5e64.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg5e64.c new file mode 100644 index 00000000000000..5929a2579d21b6 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg5e64.c @@ -0,0 +1,128 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg5e64_v_f64m1x5 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , } [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , } [[TMP4]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , } [[TMP4]], 2 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , } [[TMP4]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , } [[TMP4]], 4 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg5e.nxv1f64.i64( [[TMP5]], [[TMP6]], [[TMP7]], [[TMP8]], [[TMP9]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg5e64_v_f64m1x5(double *base, vfloat64m1x5_t v_tuple, size_t vl) { + return __riscv_th_vsseg5e64_v_f64m1x5(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg5e64_v_i64m1x5 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , } [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , } [[TMP4]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , } [[TMP4]], 2 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , } [[TMP4]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , } [[TMP4]], 4 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg5e.nxv1i64.i64( [[TMP5]], [[TMP6]], [[TMP7]], [[TMP8]], [[TMP9]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg5e64_v_i64m1x5(int64_t *base, vint64m1x5_t v_tuple, size_t vl) { + return __riscv_th_vsseg5e64_v_i64m1x5(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg5e64_v_u64m1x5 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , } [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , } [[TMP4]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , } [[TMP4]], 2 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , } [[TMP4]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , } [[TMP4]], 4 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg5e.nxv1i64.i64( [[TMP5]], [[TMP6]], [[TMP7]], [[TMP8]], [[TMP9]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg5e64_v_u64m1x5(uint64_t *base, vuint64m1x5_t v_tuple, size_t vl) { + return __riscv_th_vsseg5e64_v_u64m1x5(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg5e64_v_f64m1x5_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , } [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , } [[TMP4]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , } [[TMP4]], 2 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , } [[TMP4]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , } [[TMP4]], 4 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg5e.mask.nxv1f64.i64( [[TMP5]], [[TMP6]], [[TMP7]], [[TMP8]], [[TMP9]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg5e64_v_f64m1x5_m(vbool64_t mask, double *base, vfloat64m1x5_t v_tuple, size_t vl) { + return __riscv_th_vsseg5e64_v_f64m1x5_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg5e64_v_i64m1x5_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , } [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , } [[TMP4]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , } [[TMP4]], 2 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , } [[TMP4]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , } [[TMP4]], 4 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg5e.mask.nxv1i64.i64( [[TMP5]], [[TMP6]], [[TMP7]], [[TMP8]], [[TMP9]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg5e64_v_i64m1x5_m(vbool64_t mask, int64_t *base, vint64m1x5_t v_tuple, size_t vl) { + return __riscv_th_vsseg5e64_v_i64m1x5_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg5e64_v_u64m1x5_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , } [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , } [[TMP4]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , } [[TMP4]], 2 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , } [[TMP4]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , } [[TMP4]], 4 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg5e.mask.nxv1i64.i64( [[TMP5]], [[TMP6]], [[TMP7]], [[TMP8]], [[TMP9]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg5e64_v_u64m1x5_m(vbool64_t mask, uint64_t *base, vuint64m1x5_t v_tuple, size_t vl) { + return __riscv_th_vsseg5e64_v_u64m1x5_m(mask, base, v_tuple, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg5e8.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg5e8.c new file mode 100644 index 00000000000000..c8b8ed0ea352fd --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg5e8.c @@ -0,0 +1,88 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg5e8_v_i8m1x5 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , } [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , } [[TMP4]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , } [[TMP4]], 2 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , } [[TMP4]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , } [[TMP4]], 4 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg5e.nxv8i8.i64( [[TMP5]], [[TMP6]], [[TMP7]], [[TMP8]], [[TMP9]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg5e8_v_i8m1x5(int8_t *base, vint8m1x5_t v_tuple, size_t vl) { + return __riscv_th_vsseg5e8_v_i8m1x5(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg5e8_v_u8m1x5 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , } [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , } [[TMP4]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , } [[TMP4]], 2 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , } [[TMP4]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , } [[TMP4]], 4 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg5e.nxv8i8.i64( [[TMP5]], [[TMP6]], [[TMP7]], [[TMP8]], [[TMP9]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg5e8_v_u8m1x5(uint8_t *base, vuint8m1x5_t v_tuple, size_t vl) { + return __riscv_th_vsseg5e8_v_u8m1x5(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg5e8_v_i8m1x5_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , } [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , } [[TMP4]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , } [[TMP4]], 2 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , } [[TMP4]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , } [[TMP4]], 4 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg5e.mask.nxv8i8.i64( [[TMP5]], [[TMP6]], [[TMP7]], [[TMP8]], [[TMP9]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg5e8_v_i8m1x5_m(vbool8_t mask, int8_t *base, vint8m1x5_t v_tuple, size_t vl) { + return __riscv_th_vsseg5e8_v_i8m1x5_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg5e8_v_u8m1x5_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , } [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , } [[TMP4]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , } [[TMP4]], 2 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , } [[TMP4]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , } [[TMP4]], 4 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg5e.mask.nxv8i8.i64( [[TMP5]], [[TMP6]], [[TMP7]], [[TMP8]], [[TMP9]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg5e8_v_u8m1x5_m(vbool8_t mask, uint8_t *base, vuint8m1x5_t v_tuple, size_t vl) { + return __riscv_th_vsseg5e8_v_u8m1x5_m(mask, base, v_tuple, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg6e16.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg6e16.c new file mode 100644 index 00000000000000..8f2756cb3672ec --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg6e16.c @@ -0,0 +1,140 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg6e16_v_f16m1x6 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , } [[TMP5]], 0 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , } [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , } [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , } [[TMP5]], 3 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , } [[TMP5]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , } [[TMP5]], 5 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg6e.nxv4f16.i64( [[TMP6]], [[TMP7]], [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg6e16_v_f16m1x6(_Float16 *base, vfloat16m1x6_t v_tuple, size_t vl) { + return __riscv_th_vsseg6e16_v_f16m1x6(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg6e16_v_i16m1x6 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , } [[TMP5]], 0 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , } [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , } [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , } [[TMP5]], 3 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , } [[TMP5]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , } [[TMP5]], 5 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg6e.nxv4i16.i64( [[TMP6]], [[TMP7]], [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg6e16_v_i16m1x6(int16_t *base, vint16m1x6_t v_tuple, size_t vl) { + return __riscv_th_vsseg6e16_v_i16m1x6(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg6e16_v_u16m1x6 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , } [[TMP5]], 0 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , } [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , } [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , } [[TMP5]], 3 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , } [[TMP5]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , } [[TMP5]], 5 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg6e.nxv4i16.i64( [[TMP6]], [[TMP7]], [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg6e16_v_u16m1x6(uint16_t *base, vuint16m1x6_t v_tuple, size_t vl) { + return __riscv_th_vsseg6e16_v_u16m1x6(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg6e16_v_f16m1x6_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , } [[TMP5]], 0 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , } [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , } [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , } [[TMP5]], 3 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , } [[TMP5]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , } [[TMP5]], 5 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg6e.mask.nxv4f16.i64( [[TMP6]], [[TMP7]], [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg6e16_v_f16m1x6_m(vbool16_t mask, _Float16 *base, vfloat16m1x6_t v_tuple, size_t vl) { + return __riscv_th_vsseg6e16_v_f16m1x6_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg6e16_v_i16m1x6_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , } [[TMP5]], 0 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , } [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , } [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , } [[TMP5]], 3 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , } [[TMP5]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , } [[TMP5]], 5 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg6e.mask.nxv4i16.i64( [[TMP6]], [[TMP7]], [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg6e16_v_i16m1x6_m(vbool16_t mask, int16_t *base, vint16m1x6_t v_tuple, size_t vl) { + return __riscv_th_vsseg6e16_v_i16m1x6_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg6e16_v_u16m1x6_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , } [[TMP5]], 0 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , } [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , } [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , } [[TMP5]], 3 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , } [[TMP5]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , } [[TMP5]], 5 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg6e.mask.nxv4i16.i64( [[TMP6]], [[TMP7]], [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg6e16_v_u16m1x6_m(vbool16_t mask, uint16_t *base, vuint16m1x6_t v_tuple, size_t vl) { + return __riscv_th_vsseg6e16_v_u16m1x6_m(mask, base, v_tuple, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg6e32.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg6e32.c new file mode 100644 index 00000000000000..680c4b6b675b67 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg6e32.c @@ -0,0 +1,140 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg6e32_v_f32m1x6 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , } [[TMP5]], 0 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , } [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , } [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , } [[TMP5]], 3 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , } [[TMP5]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , } [[TMP5]], 5 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg6e.nxv2f32.i64( [[TMP6]], [[TMP7]], [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg6e32_v_f32m1x6(float *base, vfloat32m1x6_t v_tuple, size_t vl) { + return __riscv_th_vsseg6e32_v_f32m1x6(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg6e32_v_i32m1x6 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , } [[TMP5]], 0 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , } [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , } [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , } [[TMP5]], 3 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , } [[TMP5]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , } [[TMP5]], 5 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg6e.nxv2i32.i64( [[TMP6]], [[TMP7]], [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg6e32_v_i32m1x6(int32_t *base, vint32m1x6_t v_tuple, size_t vl) { + return __riscv_th_vsseg6e32_v_i32m1x6(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg6e32_v_u32m1x6 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , } [[TMP5]], 0 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , } [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , } [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , } [[TMP5]], 3 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , } [[TMP5]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , } [[TMP5]], 5 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg6e.nxv2i32.i64( [[TMP6]], [[TMP7]], [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg6e32_v_u32m1x6(uint32_t *base, vuint32m1x6_t v_tuple, size_t vl) { + return __riscv_th_vsseg6e32_v_u32m1x6(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg6e32_v_f32m1x6_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , } [[TMP5]], 0 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , } [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , } [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , } [[TMP5]], 3 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , } [[TMP5]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , } [[TMP5]], 5 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg6e.mask.nxv2f32.i64( [[TMP6]], [[TMP7]], [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg6e32_v_f32m1x6_m(vbool32_t mask, float *base, vfloat32m1x6_t v_tuple, size_t vl) { + return __riscv_th_vsseg6e32_v_f32m1x6_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg6e32_v_i32m1x6_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , } [[TMP5]], 0 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , } [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , } [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , } [[TMP5]], 3 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , } [[TMP5]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , } [[TMP5]], 5 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg6e.mask.nxv2i32.i64( [[TMP6]], [[TMP7]], [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg6e32_v_i32m1x6_m(vbool32_t mask, int32_t *base, vint32m1x6_t v_tuple, size_t vl) { + return __riscv_th_vsseg6e32_v_i32m1x6_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg6e32_v_u32m1x6_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , } [[TMP5]], 0 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , } [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , } [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , } [[TMP5]], 3 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , } [[TMP5]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , } [[TMP5]], 5 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg6e.mask.nxv2i32.i64( [[TMP6]], [[TMP7]], [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg6e32_v_u32m1x6_m(vbool32_t mask, uint32_t *base, vuint32m1x6_t v_tuple, size_t vl) { + return __riscv_th_vsseg6e32_v_u32m1x6_m(mask, base, v_tuple, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg6e64.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg6e64.c new file mode 100644 index 00000000000000..f735af2712b0b1 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg6e64.c @@ -0,0 +1,140 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg6e64_v_f64m1x6 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , } [[TMP5]], 0 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , } [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , } [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , } [[TMP5]], 3 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , } [[TMP5]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , } [[TMP5]], 5 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg6e.nxv1f64.i64( [[TMP6]], [[TMP7]], [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg6e64_v_f64m1x6(double *base, vfloat64m1x6_t v_tuple, size_t vl) { + return __riscv_th_vsseg6e64_v_f64m1x6(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg6e64_v_i64m1x6 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , } [[TMP5]], 0 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , } [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , } [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , } [[TMP5]], 3 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , } [[TMP5]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , } [[TMP5]], 5 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg6e.nxv1i64.i64( [[TMP6]], [[TMP7]], [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg6e64_v_i64m1x6(int64_t *base, vint64m1x6_t v_tuple, size_t vl) { + return __riscv_th_vsseg6e64_v_i64m1x6(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg6e64_v_u64m1x6 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , } [[TMP5]], 0 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , } [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , } [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , } [[TMP5]], 3 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , } [[TMP5]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , } [[TMP5]], 5 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg6e.nxv1i64.i64( [[TMP6]], [[TMP7]], [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg6e64_v_u64m1x6(uint64_t *base, vuint64m1x6_t v_tuple, size_t vl) { + return __riscv_th_vsseg6e64_v_u64m1x6(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg6e64_v_f64m1x6_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , } [[TMP5]], 0 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , } [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , } [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , } [[TMP5]], 3 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , } [[TMP5]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , } [[TMP5]], 5 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg6e.mask.nxv1f64.i64( [[TMP6]], [[TMP7]], [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg6e64_v_f64m1x6_m(vbool64_t mask, double *base, vfloat64m1x6_t v_tuple, size_t vl) { + return __riscv_th_vsseg6e64_v_f64m1x6_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg6e64_v_i64m1x6_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , } [[TMP5]], 0 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , } [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , } [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , } [[TMP5]], 3 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , } [[TMP5]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , } [[TMP5]], 5 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg6e.mask.nxv1i64.i64( [[TMP6]], [[TMP7]], [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg6e64_v_i64m1x6_m(vbool64_t mask, int64_t *base, vint64m1x6_t v_tuple, size_t vl) { + return __riscv_th_vsseg6e64_v_i64m1x6_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg6e64_v_u64m1x6_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , } [[TMP5]], 0 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , } [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , } [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , } [[TMP5]], 3 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , } [[TMP5]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , } [[TMP5]], 5 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg6e.mask.nxv1i64.i64( [[TMP6]], [[TMP7]], [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg6e64_v_u64m1x6_m(vbool64_t mask, uint64_t *base, vuint64m1x6_t v_tuple, size_t vl) { + return __riscv_th_vsseg6e64_v_u64m1x6_m(mask, base, v_tuple, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg6e8.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg6e8.c new file mode 100644 index 00000000000000..6c38f91f6f94d7 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg6e8.c @@ -0,0 +1,96 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg6e8_v_i8m1x6 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , } [[TMP5]], 0 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , } [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , } [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , } [[TMP5]], 3 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , } [[TMP5]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , } [[TMP5]], 5 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg6e.nxv8i8.i64( [[TMP6]], [[TMP7]], [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg6e8_v_i8m1x6(int8_t *base, vint8m1x6_t v_tuple, size_t vl) { + return __riscv_th_vsseg6e8_v_i8m1x6(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg6e8_v_u8m1x6 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , } [[TMP5]], 0 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , } [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , } [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , } [[TMP5]], 3 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , } [[TMP5]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , } [[TMP5]], 5 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg6e.nxv8i8.i64( [[TMP6]], [[TMP7]], [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg6e8_v_u8m1x6(uint8_t *base, vuint8m1x6_t v_tuple, size_t vl) { + return __riscv_th_vsseg6e8_v_u8m1x6(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg6e8_v_i8m1x6_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , } [[TMP5]], 0 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , } [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , } [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , } [[TMP5]], 3 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , } [[TMP5]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , } [[TMP5]], 5 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg6e.mask.nxv8i8.i64( [[TMP6]], [[TMP7]], [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg6e8_v_i8m1x6_m(vbool8_t mask, int8_t *base, vint8m1x6_t v_tuple, size_t vl) { + return __riscv_th_vsseg6e8_v_i8m1x6_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg6e8_v_u8m1x6_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , } [[TMP5]], 0 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , } [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , } [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , } [[TMP5]], 3 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , } [[TMP5]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , } [[TMP5]], 5 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg6e.mask.nxv8i8.i64( [[TMP6]], [[TMP7]], [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg6e8_v_u8m1x6_m(vbool8_t mask, uint8_t *base, vuint8m1x6_t v_tuple, size_t vl) { + return __riscv_th_vsseg6e8_v_u8m1x6_m(mask, base, v_tuple, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg7e16.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg7e16.c new file mode 100644 index 00000000000000..af55fb26cf165a --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg7e16.c @@ -0,0 +1,152 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg7e16_v_f16m1x7 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], [[V_TUPLE_COERCE6:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , } [[TMP5]], [[V_TUPLE_COERCE6]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , } [[TMP6]], 0 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , } [[TMP6]], 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , } [[TMP6]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , } [[TMP6]], 3 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , } [[TMP6]], 4 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , } [[TMP6]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , } [[TMP6]], 6 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg7e.nxv4f16.i64( [[TMP7]], [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], [[TMP12]], [[TMP13]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg7e16_v_f16m1x7(_Float16 *base, vfloat16m1x7_t v_tuple, size_t vl) { + return __riscv_th_vsseg7e16_v_f16m1x7(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg7e16_v_i16m1x7 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], [[V_TUPLE_COERCE6:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , } [[TMP5]], [[V_TUPLE_COERCE6]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , } [[TMP6]], 0 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , } [[TMP6]], 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , } [[TMP6]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , } [[TMP6]], 3 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , } [[TMP6]], 4 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , } [[TMP6]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , } [[TMP6]], 6 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg7e.nxv4i16.i64( [[TMP7]], [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], [[TMP12]], [[TMP13]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg7e16_v_i16m1x7(int16_t *base, vint16m1x7_t v_tuple, size_t vl) { + return __riscv_th_vsseg7e16_v_i16m1x7(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg7e16_v_u16m1x7 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], [[V_TUPLE_COERCE6:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , } [[TMP5]], [[V_TUPLE_COERCE6]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , } [[TMP6]], 0 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , } [[TMP6]], 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , } [[TMP6]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , } [[TMP6]], 3 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , } [[TMP6]], 4 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , } [[TMP6]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , } [[TMP6]], 6 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg7e.nxv4i16.i64( [[TMP7]], [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], [[TMP12]], [[TMP13]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg7e16_v_u16m1x7(uint16_t *base, vuint16m1x7_t v_tuple, size_t vl) { + return __riscv_th_vsseg7e16_v_u16m1x7(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg7e16_v_f16m1x7_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], [[V_TUPLE_COERCE6:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , } [[TMP5]], [[V_TUPLE_COERCE6]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , } [[TMP6]], 0 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , } [[TMP6]], 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , } [[TMP6]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , } [[TMP6]], 3 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , } [[TMP6]], 4 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , } [[TMP6]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , } [[TMP6]], 6 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg7e.mask.nxv4f16.i64( [[TMP7]], [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], [[TMP12]], [[TMP13]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg7e16_v_f16m1x7_m(vbool16_t mask, _Float16 *base, vfloat16m1x7_t v_tuple, size_t vl) { + return __riscv_th_vsseg7e16_v_f16m1x7_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg7e16_v_i16m1x7_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], [[V_TUPLE_COERCE6:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , } [[TMP5]], [[V_TUPLE_COERCE6]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , } [[TMP6]], 0 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , } [[TMP6]], 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , } [[TMP6]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , } [[TMP6]], 3 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , } [[TMP6]], 4 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , } [[TMP6]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , } [[TMP6]], 6 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg7e.mask.nxv4i16.i64( [[TMP7]], [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], [[TMP12]], [[TMP13]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg7e16_v_i16m1x7_m(vbool16_t mask, int16_t *base, vint16m1x7_t v_tuple, size_t vl) { + return __riscv_th_vsseg7e16_v_i16m1x7_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg7e16_v_u16m1x7_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], [[V_TUPLE_COERCE6:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , } [[TMP5]], [[V_TUPLE_COERCE6]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , } [[TMP6]], 0 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , } [[TMP6]], 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , } [[TMP6]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , } [[TMP6]], 3 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , } [[TMP6]], 4 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , } [[TMP6]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , } [[TMP6]], 6 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg7e.mask.nxv4i16.i64( [[TMP7]], [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], [[TMP12]], [[TMP13]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg7e16_v_u16m1x7_m(vbool16_t mask, uint16_t *base, vuint16m1x7_t v_tuple, size_t vl) { + return __riscv_th_vsseg7e16_v_u16m1x7_m(mask, base, v_tuple, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg7e32.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg7e32.c new file mode 100644 index 00000000000000..78b4de325cef04 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg7e32.c @@ -0,0 +1,152 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg7e32_v_f32m1x7 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], [[V_TUPLE_COERCE6:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , } [[TMP5]], [[V_TUPLE_COERCE6]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , } [[TMP6]], 0 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , } [[TMP6]], 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , } [[TMP6]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , } [[TMP6]], 3 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , } [[TMP6]], 4 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , } [[TMP6]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , } [[TMP6]], 6 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg7e.nxv2f32.i64( [[TMP7]], [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], [[TMP12]], [[TMP13]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg7e32_v_f32m1x7(float *base, vfloat32m1x7_t v_tuple, size_t vl) { + return __riscv_th_vsseg7e32_v_f32m1x7(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg7e32_v_i32m1x7 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], [[V_TUPLE_COERCE6:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , } [[TMP5]], [[V_TUPLE_COERCE6]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , } [[TMP6]], 0 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , } [[TMP6]], 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , } [[TMP6]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , } [[TMP6]], 3 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , } [[TMP6]], 4 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , } [[TMP6]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , } [[TMP6]], 6 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg7e.nxv2i32.i64( [[TMP7]], [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], [[TMP12]], [[TMP13]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg7e32_v_i32m1x7(int32_t *base, vint32m1x7_t v_tuple, size_t vl) { + return __riscv_th_vsseg7e32_v_i32m1x7(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg7e32_v_u32m1x7 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], [[V_TUPLE_COERCE6:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , } [[TMP5]], [[V_TUPLE_COERCE6]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , } [[TMP6]], 0 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , } [[TMP6]], 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , } [[TMP6]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , } [[TMP6]], 3 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , } [[TMP6]], 4 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , } [[TMP6]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , } [[TMP6]], 6 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg7e.nxv2i32.i64( [[TMP7]], [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], [[TMP12]], [[TMP13]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg7e32_v_u32m1x7(uint32_t *base, vuint32m1x7_t v_tuple, size_t vl) { + return __riscv_th_vsseg7e32_v_u32m1x7(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg7e32_v_f32m1x7_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], [[V_TUPLE_COERCE6:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , } [[TMP5]], [[V_TUPLE_COERCE6]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , } [[TMP6]], 0 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , } [[TMP6]], 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , } [[TMP6]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , } [[TMP6]], 3 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , } [[TMP6]], 4 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , } [[TMP6]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , } [[TMP6]], 6 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg7e.mask.nxv2f32.i64( [[TMP7]], [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], [[TMP12]], [[TMP13]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg7e32_v_f32m1x7_m(vbool32_t mask, float *base, vfloat32m1x7_t v_tuple, size_t vl) { + return __riscv_th_vsseg7e32_v_f32m1x7_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg7e32_v_i32m1x7_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], [[V_TUPLE_COERCE6:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , } [[TMP5]], [[V_TUPLE_COERCE6]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , } [[TMP6]], 0 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , } [[TMP6]], 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , } [[TMP6]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , } [[TMP6]], 3 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , } [[TMP6]], 4 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , } [[TMP6]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , } [[TMP6]], 6 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg7e.mask.nxv2i32.i64( [[TMP7]], [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], [[TMP12]], [[TMP13]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg7e32_v_i32m1x7_m(vbool32_t mask, int32_t *base, vint32m1x7_t v_tuple, size_t vl) { + return __riscv_th_vsseg7e32_v_i32m1x7_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg7e32_v_u32m1x7_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], [[V_TUPLE_COERCE6:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , } [[TMP5]], [[V_TUPLE_COERCE6]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , } [[TMP6]], 0 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , } [[TMP6]], 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , } [[TMP6]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , } [[TMP6]], 3 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , } [[TMP6]], 4 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , } [[TMP6]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , } [[TMP6]], 6 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg7e.mask.nxv2i32.i64( [[TMP7]], [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], [[TMP12]], [[TMP13]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg7e32_v_u32m1x7_m(vbool32_t mask, uint32_t *base, vuint32m1x7_t v_tuple, size_t vl) { + return __riscv_th_vsseg7e32_v_u32m1x7_m(mask, base, v_tuple, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg7e64.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg7e64.c new file mode 100644 index 00000000000000..9bf1a6c9430b78 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg7e64.c @@ -0,0 +1,152 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg7e64_v_f64m1x7 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], [[V_TUPLE_COERCE6:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , } [[TMP5]], [[V_TUPLE_COERCE6]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , } [[TMP6]], 0 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , } [[TMP6]], 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , } [[TMP6]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , } [[TMP6]], 3 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , } [[TMP6]], 4 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , } [[TMP6]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , } [[TMP6]], 6 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg7e.nxv1f64.i64( [[TMP7]], [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], [[TMP12]], [[TMP13]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg7e64_v_f64m1x7(double *base, vfloat64m1x7_t v_tuple, size_t vl) { + return __riscv_th_vsseg7e64_v_f64m1x7(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg7e64_v_i64m1x7 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], [[V_TUPLE_COERCE6:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , } [[TMP5]], [[V_TUPLE_COERCE6]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , } [[TMP6]], 0 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , } [[TMP6]], 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , } [[TMP6]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , } [[TMP6]], 3 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , } [[TMP6]], 4 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , } [[TMP6]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , } [[TMP6]], 6 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg7e.nxv1i64.i64( [[TMP7]], [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], [[TMP12]], [[TMP13]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg7e64_v_i64m1x7(int64_t *base, vint64m1x7_t v_tuple, size_t vl) { + return __riscv_th_vsseg7e64_v_i64m1x7(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg7e64_v_u64m1x7 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], [[V_TUPLE_COERCE6:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , } [[TMP5]], [[V_TUPLE_COERCE6]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , } [[TMP6]], 0 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , } [[TMP6]], 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , } [[TMP6]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , } [[TMP6]], 3 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , } [[TMP6]], 4 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , } [[TMP6]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , } [[TMP6]], 6 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg7e.nxv1i64.i64( [[TMP7]], [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], [[TMP12]], [[TMP13]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg7e64_v_u64m1x7(uint64_t *base, vuint64m1x7_t v_tuple, size_t vl) { + return __riscv_th_vsseg7e64_v_u64m1x7(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg7e64_v_f64m1x7_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], [[V_TUPLE_COERCE6:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , } [[TMP5]], [[V_TUPLE_COERCE6]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , } [[TMP6]], 0 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , } [[TMP6]], 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , } [[TMP6]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , } [[TMP6]], 3 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , } [[TMP6]], 4 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , } [[TMP6]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , } [[TMP6]], 6 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg7e.mask.nxv1f64.i64( [[TMP7]], [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], [[TMP12]], [[TMP13]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg7e64_v_f64m1x7_m(vbool64_t mask, double *base, vfloat64m1x7_t v_tuple, size_t vl) { + return __riscv_th_vsseg7e64_v_f64m1x7_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg7e64_v_i64m1x7_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], [[V_TUPLE_COERCE6:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , } [[TMP5]], [[V_TUPLE_COERCE6]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , } [[TMP6]], 0 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , } [[TMP6]], 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , } [[TMP6]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , } [[TMP6]], 3 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , } [[TMP6]], 4 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , } [[TMP6]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , } [[TMP6]], 6 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg7e.mask.nxv1i64.i64( [[TMP7]], [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], [[TMP12]], [[TMP13]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg7e64_v_i64m1x7_m(vbool64_t mask, int64_t *base, vint64m1x7_t v_tuple, size_t vl) { + return __riscv_th_vsseg7e64_v_i64m1x7_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg7e64_v_u64m1x7_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], [[V_TUPLE_COERCE6:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , } [[TMP5]], [[V_TUPLE_COERCE6]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , } [[TMP6]], 0 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , } [[TMP6]], 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , } [[TMP6]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , } [[TMP6]], 3 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , } [[TMP6]], 4 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , } [[TMP6]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , } [[TMP6]], 6 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg7e.mask.nxv1i64.i64( [[TMP7]], [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], [[TMP12]], [[TMP13]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg7e64_v_u64m1x7_m(vbool64_t mask, uint64_t *base, vuint64m1x7_t v_tuple, size_t vl) { + return __riscv_th_vsseg7e64_v_u64m1x7_m(mask, base, v_tuple, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg7e8.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg7e8.c new file mode 100644 index 00000000000000..382d6de180c5db --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg7e8.c @@ -0,0 +1,104 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg7e8_v_i8m1x7 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], [[V_TUPLE_COERCE6:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , } [[TMP5]], [[V_TUPLE_COERCE6]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , } [[TMP6]], 0 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , } [[TMP6]], 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , } [[TMP6]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , } [[TMP6]], 3 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , } [[TMP6]], 4 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , } [[TMP6]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , } [[TMP6]], 6 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg7e.nxv8i8.i64( [[TMP7]], [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], [[TMP12]], [[TMP13]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg7e8_v_i8m1x7(int8_t *base, vint8m1x7_t v_tuple, size_t vl) { + return __riscv_th_vsseg7e8_v_i8m1x7(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg7e8_v_u8m1x7 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], [[V_TUPLE_COERCE6:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , } [[TMP5]], [[V_TUPLE_COERCE6]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , } [[TMP6]], 0 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , } [[TMP6]], 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , } [[TMP6]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , } [[TMP6]], 3 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , } [[TMP6]], 4 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , } [[TMP6]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , } [[TMP6]], 6 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg7e.nxv8i8.i64( [[TMP7]], [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], [[TMP12]], [[TMP13]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg7e8_v_u8m1x7(uint8_t *base, vuint8m1x7_t v_tuple, size_t vl) { + return __riscv_th_vsseg7e8_v_u8m1x7(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg7e8_v_i8m1x7_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], [[V_TUPLE_COERCE6:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , } [[TMP5]], [[V_TUPLE_COERCE6]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , } [[TMP6]], 0 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , } [[TMP6]], 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , } [[TMP6]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , } [[TMP6]], 3 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , } [[TMP6]], 4 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , } [[TMP6]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , } [[TMP6]], 6 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg7e.mask.nxv8i8.i64( [[TMP7]], [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], [[TMP12]], [[TMP13]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg7e8_v_i8m1x7_m(vbool8_t mask, int8_t *base, vint8m1x7_t v_tuple, size_t vl) { + return __riscv_th_vsseg7e8_v_i8m1x7_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg7e8_v_u8m1x7_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], [[V_TUPLE_COERCE6:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , } [[TMP5]], [[V_TUPLE_COERCE6]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , } [[TMP6]], 0 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , } [[TMP6]], 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , } [[TMP6]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , } [[TMP6]], 3 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , } [[TMP6]], 4 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , } [[TMP6]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , } [[TMP6]], 6 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg7e.mask.nxv8i8.i64( [[TMP7]], [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], [[TMP12]], [[TMP13]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg7e8_v_u8m1x7_m(vbool8_t mask, uint8_t *base, vuint8m1x7_t v_tuple, size_t vl) { + return __riscv_th_vsseg7e8_v_u8m1x7_m(mask, base, v_tuple, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg8e16.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg8e16.c new file mode 100644 index 00000000000000..f72cb900d855c2 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg8e16.c @@ -0,0 +1,164 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg8e16_v_f16m1x8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], [[V_TUPLE_COERCE6:%.*]], [[V_TUPLE_COERCE7:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , , } [[TMP5]], [[V_TUPLE_COERCE6]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , , , , , , } [[TMP6]], [[V_TUPLE_COERCE7]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 0 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 1 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 2 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 4 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 5 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 6 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 7 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg8e.nxv4f16.i64( [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], [[TMP12]], [[TMP13]], [[TMP14]], [[TMP15]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg8e16_v_f16m1x8(_Float16 *base, vfloat16m1x8_t v_tuple, size_t vl) { + return __riscv_th_vsseg8e16_v_f16m1x8(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg8e16_v_i16m1x8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], [[V_TUPLE_COERCE6:%.*]], [[V_TUPLE_COERCE7:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , , } [[TMP5]], [[V_TUPLE_COERCE6]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , , , , , , } [[TMP6]], [[V_TUPLE_COERCE7]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 0 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 1 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 2 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 4 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 5 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 6 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 7 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg8e.nxv4i16.i64( [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], [[TMP12]], [[TMP13]], [[TMP14]], [[TMP15]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg8e16_v_i16m1x8(int16_t *base, vint16m1x8_t v_tuple, size_t vl) { + return __riscv_th_vsseg8e16_v_i16m1x8(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg8e16_v_u16m1x8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], [[V_TUPLE_COERCE6:%.*]], [[V_TUPLE_COERCE7:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , , } [[TMP5]], [[V_TUPLE_COERCE6]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , , , , , , } [[TMP6]], [[V_TUPLE_COERCE7]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 0 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 1 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 2 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 4 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 5 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 6 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 7 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg8e.nxv4i16.i64( [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], [[TMP12]], [[TMP13]], [[TMP14]], [[TMP15]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg8e16_v_u16m1x8(uint16_t *base, vuint16m1x8_t v_tuple, size_t vl) { + return __riscv_th_vsseg8e16_v_u16m1x8(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg8e16_v_f16m1x8_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], [[V_TUPLE_COERCE6:%.*]], [[V_TUPLE_COERCE7:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , , } [[TMP5]], [[V_TUPLE_COERCE6]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , , , , , , } [[TMP6]], [[V_TUPLE_COERCE7]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 0 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 1 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 2 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 4 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 5 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 6 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 7 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg8e.mask.nxv4f16.i64( [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], [[TMP12]], [[TMP13]], [[TMP14]], [[TMP15]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg8e16_v_f16m1x8_m(vbool16_t mask, _Float16 *base, vfloat16m1x8_t v_tuple, size_t vl) { + return __riscv_th_vsseg8e16_v_f16m1x8_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg8e16_v_i16m1x8_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], [[V_TUPLE_COERCE6:%.*]], [[V_TUPLE_COERCE7:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , , } [[TMP5]], [[V_TUPLE_COERCE6]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , , , , , , } [[TMP6]], [[V_TUPLE_COERCE7]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 0 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 1 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 2 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 4 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 5 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 6 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 7 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg8e.mask.nxv4i16.i64( [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], [[TMP12]], [[TMP13]], [[TMP14]], [[TMP15]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg8e16_v_i16m1x8_m(vbool16_t mask, int16_t *base, vint16m1x8_t v_tuple, size_t vl) { + return __riscv_th_vsseg8e16_v_i16m1x8_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg8e16_v_u16m1x8_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], [[V_TUPLE_COERCE6:%.*]], [[V_TUPLE_COERCE7:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , , } [[TMP5]], [[V_TUPLE_COERCE6]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , , , , , , } [[TMP6]], [[V_TUPLE_COERCE7]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 0 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 1 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 2 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 4 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 5 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 6 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 7 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg8e.mask.nxv4i16.i64( [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], [[TMP12]], [[TMP13]], [[TMP14]], [[TMP15]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg8e16_v_u16m1x8_m(vbool16_t mask, uint16_t *base, vuint16m1x8_t v_tuple, size_t vl) { + return __riscv_th_vsseg8e16_v_u16m1x8_m(mask, base, v_tuple, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg8e32.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg8e32.c new file mode 100644 index 00000000000000..d00407bffe37cc --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg8e32.c @@ -0,0 +1,164 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg8e32_v_f32m1x8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], [[V_TUPLE_COERCE6:%.*]], [[V_TUPLE_COERCE7:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , , } [[TMP5]], [[V_TUPLE_COERCE6]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , , , , , , } [[TMP6]], [[V_TUPLE_COERCE7]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 0 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 1 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 2 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 4 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 5 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 6 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 7 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg8e.nxv2f32.i64( [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], [[TMP12]], [[TMP13]], [[TMP14]], [[TMP15]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg8e32_v_f32m1x8(float *base, vfloat32m1x8_t v_tuple, size_t vl) { + return __riscv_th_vsseg8e32_v_f32m1x8(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg8e32_v_i32m1x8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], [[V_TUPLE_COERCE6:%.*]], [[V_TUPLE_COERCE7:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , , } [[TMP5]], [[V_TUPLE_COERCE6]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , , , , , , } [[TMP6]], [[V_TUPLE_COERCE7]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 0 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 1 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 2 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 4 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 5 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 6 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 7 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg8e.nxv2i32.i64( [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], [[TMP12]], [[TMP13]], [[TMP14]], [[TMP15]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg8e32_v_i32m1x8(int32_t *base, vint32m1x8_t v_tuple, size_t vl) { + return __riscv_th_vsseg8e32_v_i32m1x8(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg8e32_v_u32m1x8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], [[V_TUPLE_COERCE6:%.*]], [[V_TUPLE_COERCE7:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , , } [[TMP5]], [[V_TUPLE_COERCE6]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , , , , , , } [[TMP6]], [[V_TUPLE_COERCE7]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 0 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 1 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 2 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 4 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 5 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 6 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 7 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg8e.nxv2i32.i64( [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], [[TMP12]], [[TMP13]], [[TMP14]], [[TMP15]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg8e32_v_u32m1x8(uint32_t *base, vuint32m1x8_t v_tuple, size_t vl) { + return __riscv_th_vsseg8e32_v_u32m1x8(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg8e32_v_f32m1x8_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], [[V_TUPLE_COERCE6:%.*]], [[V_TUPLE_COERCE7:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , , } [[TMP5]], [[V_TUPLE_COERCE6]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , , , , , , } [[TMP6]], [[V_TUPLE_COERCE7]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 0 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 1 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 2 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 4 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 5 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 6 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 7 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg8e.mask.nxv2f32.i64( [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], [[TMP12]], [[TMP13]], [[TMP14]], [[TMP15]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg8e32_v_f32m1x8_m(vbool32_t mask, float *base, vfloat32m1x8_t v_tuple, size_t vl) { + return __riscv_th_vsseg8e32_v_f32m1x8_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg8e32_v_i32m1x8_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], [[V_TUPLE_COERCE6:%.*]], [[V_TUPLE_COERCE7:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , , } [[TMP5]], [[V_TUPLE_COERCE6]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , , , , , , } [[TMP6]], [[V_TUPLE_COERCE7]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 0 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 1 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 2 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 4 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 5 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 6 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 7 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg8e.mask.nxv2i32.i64( [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], [[TMP12]], [[TMP13]], [[TMP14]], [[TMP15]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg8e32_v_i32m1x8_m(vbool32_t mask, int32_t *base, vint32m1x8_t v_tuple, size_t vl) { + return __riscv_th_vsseg8e32_v_i32m1x8_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg8e32_v_u32m1x8_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], [[V_TUPLE_COERCE6:%.*]], [[V_TUPLE_COERCE7:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , , } [[TMP5]], [[V_TUPLE_COERCE6]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , , , , , , } [[TMP6]], [[V_TUPLE_COERCE7]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 0 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 1 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 2 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 4 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 5 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 6 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 7 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg8e.mask.nxv2i32.i64( [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], [[TMP12]], [[TMP13]], [[TMP14]], [[TMP15]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg8e32_v_u32m1x8_m(vbool32_t mask, uint32_t *base, vuint32m1x8_t v_tuple, size_t vl) { + return __riscv_th_vsseg8e32_v_u32m1x8_m(mask, base, v_tuple, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg8e64.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg8e64.c new file mode 100644 index 00000000000000..288b9b0b5d7488 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg8e64.c @@ -0,0 +1,164 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg8e64_v_f64m1x8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], [[V_TUPLE_COERCE6:%.*]], [[V_TUPLE_COERCE7:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , , } [[TMP5]], [[V_TUPLE_COERCE6]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , , , , , , } [[TMP6]], [[V_TUPLE_COERCE7]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 0 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 1 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 2 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 4 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 5 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 6 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 7 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg8e.nxv1f64.i64( [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], [[TMP12]], [[TMP13]], [[TMP14]], [[TMP15]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg8e64_v_f64m1x8(double *base, vfloat64m1x8_t v_tuple, size_t vl) { + return __riscv_th_vsseg8e64_v_f64m1x8(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg8e64_v_i64m1x8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], [[V_TUPLE_COERCE6:%.*]], [[V_TUPLE_COERCE7:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , , } [[TMP5]], [[V_TUPLE_COERCE6]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , , , , , , } [[TMP6]], [[V_TUPLE_COERCE7]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 0 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 1 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 2 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 4 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 5 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 6 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 7 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg8e.nxv1i64.i64( [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], [[TMP12]], [[TMP13]], [[TMP14]], [[TMP15]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg8e64_v_i64m1x8(int64_t *base, vint64m1x8_t v_tuple, size_t vl) { + return __riscv_th_vsseg8e64_v_i64m1x8(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg8e64_v_u64m1x8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], [[V_TUPLE_COERCE6:%.*]], [[V_TUPLE_COERCE7:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , , } [[TMP5]], [[V_TUPLE_COERCE6]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , , , , , , } [[TMP6]], [[V_TUPLE_COERCE7]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 0 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 1 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 2 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 4 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 5 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 6 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 7 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg8e.nxv1i64.i64( [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], [[TMP12]], [[TMP13]], [[TMP14]], [[TMP15]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg8e64_v_u64m1x8(uint64_t *base, vuint64m1x8_t v_tuple, size_t vl) { + return __riscv_th_vsseg8e64_v_u64m1x8(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg8e64_v_f64m1x8_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], [[V_TUPLE_COERCE6:%.*]], [[V_TUPLE_COERCE7:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , , } [[TMP5]], [[V_TUPLE_COERCE6]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , , , , , , } [[TMP6]], [[V_TUPLE_COERCE7]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 0 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 1 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 2 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 4 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 5 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 6 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 7 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg8e.mask.nxv1f64.i64( [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], [[TMP12]], [[TMP13]], [[TMP14]], [[TMP15]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg8e64_v_f64m1x8_m(vbool64_t mask, double *base, vfloat64m1x8_t v_tuple, size_t vl) { + return __riscv_th_vsseg8e64_v_f64m1x8_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg8e64_v_i64m1x8_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], [[V_TUPLE_COERCE6:%.*]], [[V_TUPLE_COERCE7:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , , } [[TMP5]], [[V_TUPLE_COERCE6]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , , , , , , } [[TMP6]], [[V_TUPLE_COERCE7]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 0 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 1 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 2 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 4 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 5 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 6 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 7 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg8e.mask.nxv1i64.i64( [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], [[TMP12]], [[TMP13]], [[TMP14]], [[TMP15]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg8e64_v_i64m1x8_m(vbool64_t mask, int64_t *base, vint64m1x8_t v_tuple, size_t vl) { + return __riscv_th_vsseg8e64_v_i64m1x8_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg8e64_v_u64m1x8_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], [[V_TUPLE_COERCE6:%.*]], [[V_TUPLE_COERCE7:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , , } [[TMP5]], [[V_TUPLE_COERCE6]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , , , , , , } [[TMP6]], [[V_TUPLE_COERCE7]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 0 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 1 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 2 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 4 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 5 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 6 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 7 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg8e.mask.nxv1i64.i64( [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], [[TMP12]], [[TMP13]], [[TMP14]], [[TMP15]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg8e64_v_u64m1x8_m(vbool64_t mask, uint64_t *base, vuint64m1x8_t v_tuple, size_t vl) { + return __riscv_th_vsseg8e64_v_u64m1x8_m(mask, base, v_tuple, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg8e8.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg8e8.c new file mode 100644 index 00000000000000..b5b6687c328ca8 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/thead/vsseg8e8.c @@ -0,0 +1,112 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg8e8_v_i8m1x8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], [[V_TUPLE_COERCE6:%.*]], [[V_TUPLE_COERCE7:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , , } [[TMP5]], [[V_TUPLE_COERCE6]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , , , , , , } [[TMP6]], [[V_TUPLE_COERCE7]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 0 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 1 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 2 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 4 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 5 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 6 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 7 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg8e.nxv8i8.i64( [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], [[TMP12]], [[TMP13]], [[TMP14]], [[TMP15]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg8e8_v_i8m1x8(int8_t *base, vint8m1x8_t v_tuple, size_t vl) { + return __riscv_th_vsseg8e8_v_i8m1x8(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg8e8_v_u8m1x8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], [[V_TUPLE_COERCE6:%.*]], [[V_TUPLE_COERCE7:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , , } [[TMP5]], [[V_TUPLE_COERCE6]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , , , , , , } [[TMP6]], [[V_TUPLE_COERCE7]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 0 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 1 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 2 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 4 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 5 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 6 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 7 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg8e.nxv8i8.i64( [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], [[TMP12]], [[TMP13]], [[TMP14]], [[TMP15]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg8e8_v_u8m1x8(uint8_t *base, vuint8m1x8_t v_tuple, size_t vl) { + return __riscv_th_vsseg8e8_v_u8m1x8(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg8e8_v_i8m1x8_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], [[V_TUPLE_COERCE6:%.*]], [[V_TUPLE_COERCE7:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , , } [[TMP5]], [[V_TUPLE_COERCE6]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , , , , , , } [[TMP6]], [[V_TUPLE_COERCE7]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 0 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 1 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 2 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 4 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 5 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 6 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 7 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg8e.mask.nxv8i8.i64( [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], [[TMP12]], [[TMP13]], [[TMP14]], [[TMP15]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg8e8_v_i8m1x8_m(vbool8_t mask, int8_t *base, vint8m1x8_t v_tuple, size_t vl) { + return __riscv_th_vsseg8e8_v_i8m1x8_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg8e8_v_u8m1x8_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], [[V_TUPLE_COERCE6:%.*]], [[V_TUPLE_COERCE7:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , , } [[TMP5]], [[V_TUPLE_COERCE6]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , , , , , , } [[TMP6]], [[V_TUPLE_COERCE7]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 0 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 1 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 2 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 4 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 5 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 6 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 7 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg8e.mask.nxv8i8.i64( [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], [[TMP12]], [[TMP13]], [[TMP14]], [[TMP15]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg8e8_v_u8m1x8_m(vbool8_t mask, uint8_t *base, vuint8m1x8_t v_tuple, size_t vl) { + return __riscv_th_vsseg8e8_v_u8m1x8_m(mask, base, v_tuple, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vsseg2e8.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vsseg2e8.c deleted file mode 100644 index c4f0e2cec8cb63..00000000000000 --- a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/vsseg2e8.c +++ /dev/null @@ -1,91 +0,0 @@ -// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 -// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ -// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ -// RUN: opt -S -passes=mem2reg | \ -// RUN: FileCheck --check-prefix=CHECK-RV64 %s - -#include - -// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e8_v_i8m1x2 -// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 -// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 -// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 -// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 -// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.nxv8i8.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], i64 [[VL]]) -// CHECK-RV64-NEXT: ret void -// -void test_th_vsseg2e8_v_i8m1x2(int8_t *base, vint8m1x2_t v_tuple, size_t vl) { - return __riscv_th_vsseg2e8_v_i8m1x2(base, v_tuple, vl); -} - -// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e8_v_i8m2x2 -// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 -// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 -// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 -// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 -// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.nxv16i8.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], i64 [[VL]]) -// CHECK-RV64-NEXT: ret void -// -void test_th_vsseg2e8_v_i8m2x2(int8_t *base, vint8m2x2_t v_tuple, size_t vl) { - return __riscv_th_vsseg2e8_v_i8m2x2(base, v_tuple, vl); -} - -// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e8_v_i8m4x2 -// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 -// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 -// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 -// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 -// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.nxv32i8.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], i64 [[VL]]) -// CHECK-RV64-NEXT: ret void -// -void test_th_vsseg2e8_v_i8m4x2(int8_t *base, vint8m4x2_t v_tuple, size_t vl) { - return __riscv_th_vsseg2e8_v_i8m4x2(base, v_tuple, vl); -} - -// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e8_v_u8m1x2 -// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 -// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 -// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 -// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 -// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.nxv8i8.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], i64 [[VL]]) -// CHECK-RV64-NEXT: ret void -// -void test_th_vsseg2e8_v_u8m1x2(uint8_t *base, vuint8m1x2_t v_tuple, size_t vl) { - return __riscv_th_vsseg2e8_v_u8m1x2(base, v_tuple, vl); -} - -// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e8_v_u8m2x2 -// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 -// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 -// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 -// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 -// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.nxv16i8.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], i64 [[VL]]) -// CHECK-RV64-NEXT: ret void -// -void test_th_vsseg2e8_v_u8m2x2(uint8_t *base, vuint8m2x2_t v_tuple, size_t vl) { - return __riscv_th_vsseg2e8_v_u8m2x2(base, v_tuple, vl); -} - -// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e8_v_u8m4x2 -// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 -// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 -// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 -// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 -// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.nxv32i8.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], i64 [[VL]]) -// CHECK-RV64-NEXT: ret void -// -void test_th_vsseg2e8_v_u8m4x2(uint8_t *base, vuint8m4x2_t v_tuple, size_t vl) { - return __riscv_th_vsseg2e8_v_u8m4x2(base, v_tuple, vl); -} diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg2b.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg2b.c new file mode 100644 index 00000000000000..607f48d957862b --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg2b.c @@ -0,0 +1,17 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , } @test_th_vlseg2b_v_i8m1x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.th.vlseg2b.nxv8i8.i64( poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vint8m1x2_t test_th_vlseg2b_v_i8m1x2(const int8_t *base, size_t vl) { + return __riscv_vlseg2b_v_i8m1x2(base, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg2e16.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg2e16.c new file mode 100644 index 00000000000000..03aa49ce208354 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg2e16.c @@ -0,0 +1,97 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , } @test_th_vlseg2e16_v_f16m1x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.th.vlseg2e.nxv4f16.i64( poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vfloat16m1x2_t test_th_vlseg2e16_v_f16m1x2(const _Float16 *base, size_t vl) { + return __riscv_vlseg2e16_v_f16m1x2(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_th_vlseg2e16_v_f16m2x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.th.vlseg2e.nxv8f16.i64( poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vfloat16m2x2_t test_th_vlseg2e16_v_f16m2x2(const _Float16 *base, size_t vl) { + return __riscv_vlseg2e16_v_f16m2x2(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_th_vlseg2e16_v_f16m4x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.th.vlseg2e.nxv16f16.i64( poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vfloat16m4x2_t test_th_vlseg2e16_v_f16m4x2(const _Float16 *base, size_t vl) { + return __riscv_vlseg2e16_v_f16m4x2(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_th_vlseg2e16_v_i16m1x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.th.vlseg2e.nxv4i16.i64( poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vint16m1x2_t test_th_vlseg2e16_v_i16m1x2(const int16_t *base, size_t vl) { + return __riscv_vlseg2e16_v_i16m1x2(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_th_vlseg2e16_v_i16m2x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.th.vlseg2e.nxv8i16.i64( poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vint16m2x2_t test_th_vlseg2e16_v_i16m2x2(const int16_t *base, size_t vl) { + return __riscv_vlseg2e16_v_i16m2x2(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_th_vlseg2e16_v_i16m4x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.th.vlseg2e.nxv16i16.i64( poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vint16m4x2_t test_th_vlseg2e16_v_i16m4x2(const int16_t *base, size_t vl) { + return __riscv_vlseg2e16_v_i16m4x2(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_th_vlseg2e16_v_u16m1x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.th.vlseg2e.nxv4i16.i64( poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vuint16m1x2_t test_th_vlseg2e16_v_u16m1x2(const uint16_t *base, size_t vl) { + return __riscv_vlseg2e16_v_u16m1x2(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_th_vlseg2e16_v_u16m2x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.th.vlseg2e.nxv8i16.i64( poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vuint16m2x2_t test_th_vlseg2e16_v_u16m2x2(const uint16_t *base, size_t vl) { + return __riscv_vlseg2e16_v_u16m2x2(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_th_vlseg2e16_v_u16m4x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.th.vlseg2e.nxv16i16.i64( poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vuint16m4x2_t test_th_vlseg2e16_v_u16m4x2(const uint16_t *base, size_t vl) { + return __riscv_vlseg2e16_v_u16m4x2(base, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg2e16ff.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg2e16ff.c new file mode 100644 index 00000000000000..653e7765027757 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg2e16ff.c @@ -0,0 +1,151 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , } @test_th_vlseg2e16ff_v_f16m1x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.th.vlseg2eff.nxv4f16.i64( poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP5]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , } [[TMP4]] +// +vfloat16m1x2_t test_th_vlseg2e16ff_v_f16m1x2(const _Float16 *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg2e16ff_v_f16m1x2(base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_th_vlseg2e16ff_v_f16m2x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.th.vlseg2eff.nxv8f16.i64( poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP5]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , } [[TMP4]] +// +vfloat16m2x2_t test_th_vlseg2e16ff_v_f16m2x2(const _Float16 *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg2e16ff_v_f16m2x2(base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_th_vlseg2e16ff_v_f16m4x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.th.vlseg2eff.nxv16f16.i64( poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP5]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , } [[TMP4]] +// +vfloat16m4x2_t test_th_vlseg2e16ff_v_f16m4x2(const _Float16 *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg2e16ff_v_f16m4x2(base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_th_vlseg2e16ff_v_i16m1x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.th.vlseg2eff.nxv4i16.i64( poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP5]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , } [[TMP4]] +// +vint16m1x2_t test_th_vlseg2e16ff_v_i16m1x2(const int16_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg2e16ff_v_i16m1x2(base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_th_vlseg2e16ff_v_i16m2x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.th.vlseg2eff.nxv8i16.i64( poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP5]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , } [[TMP4]] +// +vint16m2x2_t test_th_vlseg2e16ff_v_i16m2x2(const int16_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg2e16ff_v_i16m2x2(base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_th_vlseg2e16ff_v_i16m4x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.th.vlseg2eff.nxv16i16.i64( poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP5]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , } [[TMP4]] +// +vint16m4x2_t test_th_vlseg2e16ff_v_i16m4x2(const int16_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg2e16ff_v_i16m4x2(base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_th_vlseg2e16ff_v_u16m1x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.th.vlseg2eff.nxv4i16.i64( poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP5]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , } [[TMP4]] +// +vuint16m1x2_t test_th_vlseg2e16ff_v_u16m1x2(const uint16_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg2e16ff_v_u16m1x2(base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_th_vlseg2e16ff_v_u16m2x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.th.vlseg2eff.nxv8i16.i64( poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP5]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , } [[TMP4]] +// +vuint16m2x2_t test_th_vlseg2e16ff_v_u16m2x2(const uint16_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg2e16ff_v_u16m2x2(base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_th_vlseg2e16ff_v_u16m4x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.th.vlseg2eff.nxv16i16.i64( poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP5]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , } [[TMP4]] +// +vuint16m4x2_t test_th_vlseg2e16ff_v_u16m4x2(const uint16_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg2e16ff_v_u16m4x2(base, new_vl, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg2e32.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg2e32.c new file mode 100644 index 00000000000000..9433e1f70c16d8 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg2e32.c @@ -0,0 +1,97 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , } @test_th_vlseg2e32_v_f32m1x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.th.vlseg2e.nxv2f32.i64( poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vfloat32m1x2_t test_th_vlseg2e32_v_f32m1x2(const float *base, size_t vl) { + return __riscv_vlseg2e32_v_f32m1x2(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_th_vlseg2e32_v_f32m2x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.th.vlseg2e.nxv4f32.i64( poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vfloat32m2x2_t test_th_vlseg2e32_v_f32m2x2(const float *base, size_t vl) { + return __riscv_vlseg2e32_v_f32m2x2(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_th_vlseg2e32_v_f32m4x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.th.vlseg2e.nxv8f32.i64( poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vfloat32m4x2_t test_th_vlseg2e32_v_f32m4x2(const float *base, size_t vl) { + return __riscv_vlseg2e32_v_f32m4x2(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_th_vlseg2e32_v_i32m1x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.th.vlseg2e.nxv2i32.i64( poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vint32m1x2_t test_th_vlseg2e32_v_i32m1x2(const int32_t *base, size_t vl) { + return __riscv_vlseg2e32_v_i32m1x2(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_th_vlseg2e32_v_i32m2x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.th.vlseg2e.nxv4i32.i64( poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vint32m2x2_t test_th_vlseg2e32_v_i32m2x2(const int32_t *base, size_t vl) { + return __riscv_vlseg2e32_v_i32m2x2(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_th_vlseg2e32_v_i32m4x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.th.vlseg2e.nxv8i32.i64( poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vint32m4x2_t test_th_vlseg2e32_v_i32m4x2(const int32_t *base, size_t vl) { + return __riscv_vlseg2e32_v_i32m4x2(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_th_vlseg2e32_v_u32m1x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.th.vlseg2e.nxv2i32.i64( poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vuint32m1x2_t test_th_vlseg2e32_v_u32m1x2(const uint32_t *base, size_t vl) { + return __riscv_vlseg2e32_v_u32m1x2(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_th_vlseg2e32_v_u32m2x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.th.vlseg2e.nxv4i32.i64( poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vuint32m2x2_t test_th_vlseg2e32_v_u32m2x2(const uint32_t *base, size_t vl) { + return __riscv_vlseg2e32_v_u32m2x2(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_th_vlseg2e32_v_u32m4x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.th.vlseg2e.nxv8i32.i64( poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vuint32m4x2_t test_th_vlseg2e32_v_u32m4x2(const uint32_t *base, size_t vl) { + return __riscv_vlseg2e32_v_u32m4x2(base, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg2e32ff.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg2e32ff.c new file mode 100644 index 00000000000000..cc0d2c30b9bf16 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg2e32ff.c @@ -0,0 +1,151 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , } @test_th_vlseg2e32ff_v_f32m1x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.th.vlseg2eff.nxv2f32.i64( poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP5]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , } [[TMP4]] +// +vfloat32m1x2_t test_th_vlseg2e32ff_v_f32m1x2(const float *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg2e32ff_v_f32m1x2(base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_th_vlseg2e32ff_v_f32m2x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.th.vlseg2eff.nxv4f32.i64( poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP5]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , } [[TMP4]] +// +vfloat32m2x2_t test_th_vlseg2e32ff_v_f32m2x2(const float *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg2e32ff_v_f32m2x2(base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_th_vlseg2e32ff_v_f32m4x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.th.vlseg2eff.nxv8f32.i64( poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP5]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , } [[TMP4]] +// +vfloat32m4x2_t test_th_vlseg2e32ff_v_f32m4x2(const float *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg2e32ff_v_f32m4x2(base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_th_vlseg2e32ff_v_i32m1x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.th.vlseg2eff.nxv2i32.i64( poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP5]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , } [[TMP4]] +// +vint32m1x2_t test_th_vlseg2e32ff_v_i32m1x2(const int32_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg2e32ff_v_i32m1x2(base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_th_vlseg2e32ff_v_i32m2x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.th.vlseg2eff.nxv4i32.i64( poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP5]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , } [[TMP4]] +// +vint32m2x2_t test_th_vlseg2e32ff_v_i32m2x2(const int32_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg2e32ff_v_i32m2x2(base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_th_vlseg2e32ff_v_i32m4x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.th.vlseg2eff.nxv8i32.i64( poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP5]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , } [[TMP4]] +// +vint32m4x2_t test_th_vlseg2e32ff_v_i32m4x2(const int32_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg2e32ff_v_i32m4x2(base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_th_vlseg2e32ff_v_u32m1x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.th.vlseg2eff.nxv2i32.i64( poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP5]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , } [[TMP4]] +// +vuint32m1x2_t test_th_vlseg2e32ff_v_u32m1x2(const uint32_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg2e32ff_v_u32m1x2(base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_th_vlseg2e32ff_v_u32m2x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.th.vlseg2eff.nxv4i32.i64( poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP5]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , } [[TMP4]] +// +vuint32m2x2_t test_th_vlseg2e32ff_v_u32m2x2(const uint32_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg2e32ff_v_u32m2x2(base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_th_vlseg2e32ff_v_u32m4x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.th.vlseg2eff.nxv8i32.i64( poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP5]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , } [[TMP4]] +// +vuint32m4x2_t test_th_vlseg2e32ff_v_u32m4x2(const uint32_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg2e32ff_v_u32m4x2(base, new_vl, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg2e64.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg2e64.c new file mode 100644 index 00000000000000..81294143035bc4 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg2e64.c @@ -0,0 +1,97 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , } @test_th_vlseg2e64_v_f64m1x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.th.vlseg2e.nxv1f64.i64( poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vfloat64m1x2_t test_th_vlseg2e64_v_f64m1x2(const double *base, size_t vl) { + return __riscv_vlseg2e64_v_f64m1x2(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_th_vlseg2e64_v_f64m2x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.th.vlseg2e.nxv2f64.i64( poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vfloat64m2x2_t test_th_vlseg2e64_v_f64m2x2(const double *base, size_t vl) { + return __riscv_vlseg2e64_v_f64m2x2(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_th_vlseg2e64_v_f64m4x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.th.vlseg2e.nxv4f64.i64( poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vfloat64m4x2_t test_th_vlseg2e64_v_f64m4x2(const double *base, size_t vl) { + return __riscv_vlseg2e64_v_f64m4x2(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_th_vlseg2e64_v_i64m1x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.th.vlseg2e.nxv1i64.i64( poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vint64m1x2_t test_th_vlseg2e64_v_i64m1x2(const int64_t *base, size_t vl) { + return __riscv_vlseg2e64_v_i64m1x2(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_th_vlseg2e64_v_i64m2x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.th.vlseg2e.nxv2i64.i64( poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vint64m2x2_t test_th_vlseg2e64_v_i64m2x2(const int64_t *base, size_t vl) { + return __riscv_vlseg2e64_v_i64m2x2(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_th_vlseg2e64_v_i64m4x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.th.vlseg2e.nxv4i64.i64( poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vint64m4x2_t test_th_vlseg2e64_v_i64m4x2(const int64_t *base, size_t vl) { + return __riscv_vlseg2e64_v_i64m4x2(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_th_vlseg2e64_v_u64m1x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.th.vlseg2e.nxv1i64.i64( poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vuint64m1x2_t test_th_vlseg2e64_v_u64m1x2(const uint64_t *base, size_t vl) { + return __riscv_vlseg2e64_v_u64m1x2(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_th_vlseg2e64_v_u64m2x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.th.vlseg2e.nxv2i64.i64( poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vuint64m2x2_t test_th_vlseg2e64_v_u64m2x2(const uint64_t *base, size_t vl) { + return __riscv_vlseg2e64_v_u64m2x2(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_th_vlseg2e64_v_u64m4x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.th.vlseg2e.nxv4i64.i64( poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vuint64m4x2_t test_th_vlseg2e64_v_u64m4x2(const uint64_t *base, size_t vl) { + return __riscv_vlseg2e64_v_u64m4x2(base, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg2e64ff.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg2e64ff.c new file mode 100644 index 00000000000000..58801e3d39934e --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg2e64ff.c @@ -0,0 +1,151 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , } @test_th_vlseg2e64ff_v_f64m1x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.th.vlseg2eff.nxv1f64.i64( poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP5]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , } [[TMP4]] +// +vfloat64m1x2_t test_th_vlseg2e64ff_v_f64m1x2(const double *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg2e64ff_v_f64m1x2(base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_th_vlseg2e64ff_v_f64m2x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.th.vlseg2eff.nxv2f64.i64( poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP5]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , } [[TMP4]] +// +vfloat64m2x2_t test_th_vlseg2e64ff_v_f64m2x2(const double *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg2e64ff_v_f64m2x2(base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_th_vlseg2e64ff_v_f64m4x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.th.vlseg2eff.nxv4f64.i64( poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP5]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , } [[TMP4]] +// +vfloat64m4x2_t test_th_vlseg2e64ff_v_f64m4x2(const double *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg2e64ff_v_f64m4x2(base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_th_vlseg2e64ff_v_i64m1x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.th.vlseg2eff.nxv1i64.i64( poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP5]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , } [[TMP4]] +// +vint64m1x2_t test_th_vlseg2e64ff_v_i64m1x2(const int64_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg2e64ff_v_i64m1x2(base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_th_vlseg2e64ff_v_i64m2x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.th.vlseg2eff.nxv2i64.i64( poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP5]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , } [[TMP4]] +// +vint64m2x2_t test_th_vlseg2e64ff_v_i64m2x2(const int64_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg2e64ff_v_i64m2x2(base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_th_vlseg2e64ff_v_i64m4x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.th.vlseg2eff.nxv4i64.i64( poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP5]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , } [[TMP4]] +// +vint64m4x2_t test_th_vlseg2e64ff_v_i64m4x2(const int64_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg2e64ff_v_i64m4x2(base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_th_vlseg2e64ff_v_u64m1x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.th.vlseg2eff.nxv1i64.i64( poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP5]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , } [[TMP4]] +// +vuint64m1x2_t test_th_vlseg2e64ff_v_u64m1x2(const uint64_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg2e64ff_v_u64m1x2(base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_th_vlseg2e64ff_v_u64m2x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.th.vlseg2eff.nxv2i64.i64( poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP5]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , } [[TMP4]] +// +vuint64m2x2_t test_th_vlseg2e64ff_v_u64m2x2(const uint64_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg2e64ff_v_u64m2x2(base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_th_vlseg2e64ff_v_u64m4x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.th.vlseg2eff.nxv4i64.i64( poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP5]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , } [[TMP4]] +// +vuint64m4x2_t test_th_vlseg2e64ff_v_u64m4x2(const uint64_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg2e64ff_v_u64m4x2(base, new_vl, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg2e8.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg2e8.c new file mode 100644 index 00000000000000..0f9d54ef082158 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg2e8.c @@ -0,0 +1,67 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , } @test_th_vlseg2e8_v_i8m1x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.th.vlseg2e.nxv8i8.i64( poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vint8m1x2_t test_th_vlseg2e8_v_i8m1x2(const int8_t *base, size_t vl) { + return __riscv_vlseg2e8_v_i8m1x2(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_th_vlseg2e8_v_i8m2x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.th.vlseg2e.nxv16i8.i64( poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vint8m2x2_t test_th_vlseg2e8_v_i8m2x2(const int8_t *base, size_t vl) { + return __riscv_vlseg2e8_v_i8m2x2(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_th_vlseg2e8_v_i8m4x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.th.vlseg2e.nxv32i8.i64( poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vint8m4x2_t test_th_vlseg2e8_v_i8m4x2(const int8_t *base, size_t vl) { + return __riscv_vlseg2e8_v_i8m4x2(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_th_vlseg2e8_v_u8m1x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.th.vlseg2e.nxv8i8.i64( poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vuint8m1x2_t test_th_vlseg2e8_v_u8m1x2(const uint8_t *base, size_t vl) { + return __riscv_vlseg2e8_v_u8m1x2(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_th_vlseg2e8_v_u8m2x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.th.vlseg2e.nxv16i8.i64( poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vuint8m2x2_t test_th_vlseg2e8_v_u8m2x2(const uint8_t *base, size_t vl) { + return __riscv_vlseg2e8_v_u8m2x2(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_th_vlseg2e8_v_u8m4x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.th.vlseg2e.nxv32i8.i64( poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vuint8m4x2_t test_th_vlseg2e8_v_u8m4x2(const uint8_t *base, size_t vl) { + return __riscv_vlseg2e8_v_u8m4x2(base, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg2e8ff.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg2e8ff.c new file mode 100644 index 00000000000000..f4eb70b746c3f4 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg2e8ff.c @@ -0,0 +1,103 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , } @test_th_vlseg2e8ff_v_i8m1x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.th.vlseg2eff.nxv8i8.i64( poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP5]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , } [[TMP4]] +// +vint8m1x2_t test_th_vlseg2e8ff_v_i8m1x2(const int8_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg2e8ff_v_i8m1x2(base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_th_vlseg2e8ff_v_i8m2x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.th.vlseg2eff.nxv16i8.i64( poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP5]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , } [[TMP4]] +// +vint8m2x2_t test_th_vlseg2e8ff_v_i8m2x2(const int8_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg2e8ff_v_i8m2x2(base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_th_vlseg2e8ff_v_i8m4x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.th.vlseg2eff.nxv32i8.i64( poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP5]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , } [[TMP4]] +// +vint8m4x2_t test_th_vlseg2e8ff_v_i8m4x2(const int8_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg2e8ff_v_i8m4x2(base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_th_vlseg2e8ff_v_u8m1x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.th.vlseg2eff.nxv8i8.i64( poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP5]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , } [[TMP4]] +// +vuint8m1x2_t test_th_vlseg2e8ff_v_u8m1x2(const uint8_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg2e8ff_v_u8m1x2(base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_th_vlseg2e8ff_v_u8m2x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.th.vlseg2eff.nxv16i8.i64( poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP5]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , } [[TMP4]] +// +vuint8m2x2_t test_th_vlseg2e8ff_v_u8m2x2(const uint8_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg2e8ff_v_u8m2x2(base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_th_vlseg2e8ff_v_u8m4x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.th.vlseg2eff.nxv32i8.i64( poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP5]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , } [[TMP4]] +// +vuint8m4x2_t test_th_vlseg2e8ff_v_u8m4x2(const uint8_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg2e8ff_v_u8m4x2(base, new_vl, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg3e16.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg3e16.c new file mode 100644 index 00000000000000..707b09bfa3a719 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg3e16.c @@ -0,0 +1,67 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , } @test_th_vlseg3e16_v_f16m1x3 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.th.vlseg3e.nxv4f16.i64( poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , } [[TMP0]] +// +vfloat16m1x3_t test_th_vlseg3e16_v_f16m1x3(const _Float16 *base, size_t vl) { + return __riscv_vlseg3e16_v_f16m1x3(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_th_vlseg3e16_v_f16m2x3 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.th.vlseg3e.nxv8f16.i64( poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , } [[TMP0]] +// +vfloat16m2x3_t test_th_vlseg3e16_v_f16m2x3(const _Float16 *base, size_t vl) { + return __riscv_vlseg3e16_v_f16m2x3(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_th_vlseg3e16_v_i16m1x3 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.th.vlseg3e.nxv4i16.i64( poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , } [[TMP0]] +// +vint16m1x3_t test_th_vlseg3e16_v_i16m1x3(const int16_t *base, size_t vl) { + return __riscv_vlseg3e16_v_i16m1x3(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_th_vlseg3e16_v_i16m2x3 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.th.vlseg3e.nxv8i16.i64( poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , } [[TMP0]] +// +vint16m2x3_t test_th_vlseg3e16_v_i16m2x3(const int16_t *base, size_t vl) { + return __riscv_vlseg3e16_v_i16m2x3(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_th_vlseg3e16_v_u16m1x3 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.th.vlseg3e.nxv4i16.i64( poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , } [[TMP0]] +// +vuint16m1x3_t test_th_vlseg3e16_v_u16m1x3(const uint16_t *base, size_t vl) { + return __riscv_vlseg3e16_v_u16m1x3(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_th_vlseg3e16_v_u16m2x3 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.th.vlseg3e.nxv8i16.i64( poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , } [[TMP0]] +// +vuint16m2x3_t test_th_vlseg3e16_v_u16m2x3(const uint16_t *base, size_t vl) { + return __riscv_vlseg3e16_v_u16m2x3(base, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg3e16ff.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg3e16ff.c new file mode 100644 index 00000000000000..deb52448ab1a96 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg3e16ff.c @@ -0,0 +1,115 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , } @test_th_vlseg3e16ff_v_f16m1x3 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.th.vlseg3eff.nxv4f16.i64( poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP7]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , } [[TMP6]] +// +vfloat16m1x3_t test_th_vlseg3e16ff_v_f16m1x3(const _Float16 *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg3e16ff_v_f16m1x3(base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_th_vlseg3e16ff_v_f16m2x3 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.th.vlseg3eff.nxv8f16.i64( poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP7]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , } [[TMP6]] +// +vfloat16m2x3_t test_th_vlseg3e16ff_v_f16m2x3(const _Float16 *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg3e16ff_v_f16m2x3(base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_th_vlseg3e16ff_v_i16m1x3 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.th.vlseg3eff.nxv4i16.i64( poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP7]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , } [[TMP6]] +// +vint16m1x3_t test_th_vlseg3e16ff_v_i16m1x3(const int16_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg3e16ff_v_i16m1x3(base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_th_vlseg3e16ff_v_i16m2x3 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.th.vlseg3eff.nxv8i16.i64( poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP7]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , } [[TMP6]] +// +vint16m2x3_t test_th_vlseg3e16ff_v_i16m2x3(const int16_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg3e16ff_v_i16m2x3(base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_th_vlseg3e16ff_v_u16m1x3 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.th.vlseg3eff.nxv4i16.i64( poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP7]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , } [[TMP6]] +// +vuint16m1x3_t test_th_vlseg3e16ff_v_u16m1x3(const uint16_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg3e16ff_v_u16m1x3(base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_th_vlseg3e16ff_v_u16m2x3 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.th.vlseg3eff.nxv8i16.i64( poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP7]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , } [[TMP6]] +// +vuint16m2x3_t test_th_vlseg3e16ff_v_u16m2x3(const uint16_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg3e16ff_v_u16m2x3(base, new_vl, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg3e32.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg3e32.c new file mode 100644 index 00000000000000..de69281c79a7e9 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg3e32.c @@ -0,0 +1,67 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , } @test_th_vlseg3e32_v_f32m1x3 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.th.vlseg3e.nxv2f32.i64( poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , } [[TMP0]] +// +vfloat32m1x3_t test_th_vlseg3e32_v_f32m1x3(const float *base, size_t vl) { + return __riscv_vlseg3e32_v_f32m1x3(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_th_vlseg3e32_v_f32m2x3 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.th.vlseg3e.nxv4f32.i64( poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , } [[TMP0]] +// +vfloat32m2x3_t test_th_vlseg3e32_v_f32m2x3(const float *base, size_t vl) { + return __riscv_vlseg3e32_v_f32m2x3(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_th_vlseg3e32_v_i32m1x3 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.th.vlseg3e.nxv2i32.i64( poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , } [[TMP0]] +// +vint32m1x3_t test_th_vlseg3e32_v_i32m1x3(const int32_t *base, size_t vl) { + return __riscv_vlseg3e32_v_i32m1x3(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_th_vlseg3e32_v_i32m2x3 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.th.vlseg3e.nxv4i32.i64( poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , } [[TMP0]] +// +vint32m2x3_t test_th_vlseg3e32_v_i32m2x3(const int32_t *base, size_t vl) { + return __riscv_vlseg3e32_v_i32m2x3(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_th_vlseg3e32_v_u32m1x3 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.th.vlseg3e.nxv2i32.i64( poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , } [[TMP0]] +// +vuint32m1x3_t test_th_vlseg3e32_v_u32m1x3(const uint32_t *base, size_t vl) { + return __riscv_vlseg3e32_v_u32m1x3(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_th_vlseg3e32_v_u32m2x3 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.th.vlseg3e.nxv4i32.i64( poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , } [[TMP0]] +// +vuint32m2x3_t test_th_vlseg3e32_v_u32m2x3(const uint32_t *base, size_t vl) { + return __riscv_vlseg3e32_v_u32m2x3(base, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg3e32ff.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg3e32ff.c new file mode 100644 index 00000000000000..c5be598ba0c505 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg3e32ff.c @@ -0,0 +1,115 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , } @test_th_vlseg3e32ff_v_f32m1x3 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.th.vlseg3eff.nxv2f32.i64( poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP7]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , } [[TMP6]] +// +vfloat32m1x3_t test_th_vlseg3e32ff_v_f32m1x3(const float *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg3e32ff_v_f32m1x3(base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_th_vlseg3e32ff_v_f32m2x3 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.th.vlseg3eff.nxv4f32.i64( poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP7]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , } [[TMP6]] +// +vfloat32m2x3_t test_th_vlseg3e32ff_v_f32m2x3(const float *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg3e32ff_v_f32m2x3(base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_th_vlseg3e32ff_v_i32m1x3 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.th.vlseg3eff.nxv2i32.i64( poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP7]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , } [[TMP6]] +// +vint32m1x3_t test_th_vlseg3e32ff_v_i32m1x3(const int32_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg3e32ff_v_i32m1x3(base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_th_vlseg3e32ff_v_i32m2x3 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.th.vlseg3eff.nxv4i32.i64( poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP7]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , } [[TMP6]] +// +vint32m2x3_t test_th_vlseg3e32ff_v_i32m2x3(const int32_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg3e32ff_v_i32m2x3(base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_th_vlseg3e32ff_v_u32m1x3 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.th.vlseg3eff.nxv2i32.i64( poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP7]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , } [[TMP6]] +// +vuint32m1x3_t test_th_vlseg3e32ff_v_u32m1x3(const uint32_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg3e32ff_v_u32m1x3(base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_th_vlseg3e32ff_v_u32m2x3 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.th.vlseg3eff.nxv4i32.i64( poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP7]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , } [[TMP6]] +// +vuint32m2x3_t test_th_vlseg3e32ff_v_u32m2x3(const uint32_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg3e32ff_v_u32m2x3(base, new_vl, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg3e64.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg3e64.c new file mode 100644 index 00000000000000..77d9a3ec7ce3fb --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg3e64.c @@ -0,0 +1,67 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , } @test_th_vlseg3e64_v_f64m1x3 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.th.vlseg3e.nxv1f64.i64( poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , } [[TMP0]] +// +vfloat64m1x3_t test_th_vlseg3e64_v_f64m1x3(const double *base, size_t vl) { + return __riscv_vlseg3e64_v_f64m1x3(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_th_vlseg3e64_v_f64m2x3 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.th.vlseg3e.nxv2f64.i64( poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , } [[TMP0]] +// +vfloat64m2x3_t test_th_vlseg3e64_v_f64m2x3(const double *base, size_t vl) { + return __riscv_vlseg3e64_v_f64m2x3(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_th_vlseg3e64_v_i64m1x3 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.th.vlseg3e.nxv1i64.i64( poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , } [[TMP0]] +// +vint64m1x3_t test_th_vlseg3e64_v_i64m1x3(const int64_t *base, size_t vl) { + return __riscv_vlseg3e64_v_i64m1x3(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_th_vlseg3e64_v_i64m2x3 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.th.vlseg3e.nxv2i64.i64( poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , } [[TMP0]] +// +vint64m2x3_t test_th_vlseg3e64_v_i64m2x3(const int64_t *base, size_t vl) { + return __riscv_vlseg3e64_v_i64m2x3(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_th_vlseg3e64_v_u64m1x3 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.th.vlseg3e.nxv1i64.i64( poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , } [[TMP0]] +// +vuint64m1x3_t test_th_vlseg3e64_v_u64m1x3(const uint64_t *base, size_t vl) { + return __riscv_vlseg3e64_v_u64m1x3(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_th_vlseg3e64_v_u64m2x3 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.th.vlseg3e.nxv2i64.i64( poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , } [[TMP0]] +// +vuint64m2x3_t test_th_vlseg3e64_v_u64m2x3(const uint64_t *base, size_t vl) { + return __riscv_vlseg3e64_v_u64m2x3(base, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg3e64ff.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg3e64ff.c new file mode 100644 index 00000000000000..4cf5e34fa20f67 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg3e64ff.c @@ -0,0 +1,115 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , } @test_th_vlseg3e64ff_v_f64m1x3 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.th.vlseg3eff.nxv1f64.i64( poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP7]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , } [[TMP6]] +// +vfloat64m1x3_t test_th_vlseg3e64ff_v_f64m1x3(const double *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg3e64ff_v_f64m1x3(base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_th_vlseg3e64ff_v_f64m2x3 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.th.vlseg3eff.nxv2f64.i64( poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP7]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , } [[TMP6]] +// +vfloat64m2x3_t test_th_vlseg3e64ff_v_f64m2x3(const double *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg3e64ff_v_f64m2x3(base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_th_vlseg3e64ff_v_i64m1x3 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.th.vlseg3eff.nxv1i64.i64( poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP7]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , } [[TMP6]] +// +vint64m1x3_t test_th_vlseg3e64ff_v_i64m1x3(const int64_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg3e64ff_v_i64m1x3(base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_th_vlseg3e64ff_v_i64m2x3 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.th.vlseg3eff.nxv2i64.i64( poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP7]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , } [[TMP6]] +// +vint64m2x3_t test_th_vlseg3e64ff_v_i64m2x3(const int64_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg3e64ff_v_i64m2x3(base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_th_vlseg3e64ff_v_u64m1x3 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.th.vlseg3eff.nxv1i64.i64( poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP7]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , } [[TMP6]] +// +vuint64m1x3_t test_th_vlseg3e64ff_v_u64m1x3(const uint64_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg3e64ff_v_u64m1x3(base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_th_vlseg3e64ff_v_u64m2x3 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.th.vlseg3eff.nxv2i64.i64( poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP7]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , } [[TMP6]] +// +vuint64m2x3_t test_th_vlseg3e64ff_v_u64m2x3(const uint64_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg3e64ff_v_u64m2x3(base, new_vl, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg3e8.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg3e8.c new file mode 100644 index 00000000000000..847049cba12de8 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg3e8.c @@ -0,0 +1,47 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , } @test_th_vlseg3e8_v_i8m1x3 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.th.vlseg3e.nxv8i8.i64( poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , } [[TMP0]] +// +vint8m1x3_t test_th_vlseg3e8_v_i8m1x3(const int8_t *base, size_t vl) { + return __riscv_vlseg3e8_v_i8m1x3(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_th_vlseg3e8_v_i8m2x3 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.th.vlseg3e.nxv16i8.i64( poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , } [[TMP0]] +// +vint8m2x3_t test_th_vlseg3e8_v_i8m2x3(const int8_t *base, size_t vl) { + return __riscv_vlseg3e8_v_i8m2x3(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_th_vlseg3e8_v_u8m1x3 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.th.vlseg3e.nxv8i8.i64( poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , } [[TMP0]] +// +vuint8m1x3_t test_th_vlseg3e8_v_u8m1x3(const uint8_t *base, size_t vl) { + return __riscv_vlseg3e8_v_u8m1x3(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_th_vlseg3e8_v_u8m2x3 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.th.vlseg3e.nxv16i8.i64( poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , } [[TMP0]] +// +vuint8m2x3_t test_th_vlseg3e8_v_u8m2x3(const uint8_t *base, size_t vl) { + return __riscv_vlseg3e8_v_u8m2x3(base, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg3e8ff.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg3e8ff.c new file mode 100644 index 00000000000000..d9bca2f7b385e5 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg3e8ff.c @@ -0,0 +1,79 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , } @test_th_vlseg3e8ff_v_i8m1x3 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.th.vlseg3eff.nxv8i8.i64( poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP7]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , } [[TMP6]] +// +vint8m1x3_t test_th_vlseg3e8ff_v_i8m1x3(const int8_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg3e8ff_v_i8m1x3(base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_th_vlseg3e8ff_v_i8m2x3 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.th.vlseg3eff.nxv16i8.i64( poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP7]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , } [[TMP6]] +// +vint8m2x3_t test_th_vlseg3e8ff_v_i8m2x3(const int8_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg3e8ff_v_i8m2x3(base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_th_vlseg3e8ff_v_u8m1x3 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.th.vlseg3eff.nxv8i8.i64( poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP7]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , } [[TMP6]] +// +vuint8m1x3_t test_th_vlseg3e8ff_v_u8m1x3(const uint8_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg3e8ff_v_u8m1x3(base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_th_vlseg3e8ff_v_u8m2x3 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.th.vlseg3eff.nxv16i8.i64( poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP7]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , } [[TMP6]] +// +vuint8m2x3_t test_th_vlseg3e8ff_v_u8m2x3(const uint8_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg3e8ff_v_u8m2x3(base, new_vl, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg4e16.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg4e16.c new file mode 100644 index 00000000000000..fbb502621caddd --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg4e16.c @@ -0,0 +1,67 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_th_vlseg4e16_v_f16m1x4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.th.vlseg4e.nxv4f16.i64( poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , } [[TMP0]] +// +vfloat16m1x4_t test_th_vlseg4e16_v_f16m1x4(const _Float16 *base, size_t vl) { + return __riscv_vlseg4e16_v_f16m1x4(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_th_vlseg4e16_v_f16m2x4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.th.vlseg4e.nxv8f16.i64( poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , } [[TMP0]] +// +vfloat16m2x4_t test_th_vlseg4e16_v_f16m2x4(const _Float16 *base, size_t vl) { + return __riscv_vlseg4e16_v_f16m2x4(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_th_vlseg4e16_v_i16m1x4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.th.vlseg4e.nxv4i16.i64( poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , } [[TMP0]] +// +vint16m1x4_t test_th_vlseg4e16_v_i16m1x4(const int16_t *base, size_t vl) { + return __riscv_vlseg4e16_v_i16m1x4(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_th_vlseg4e16_v_i16m2x4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.th.vlseg4e.nxv8i16.i64( poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , } [[TMP0]] +// +vint16m2x4_t test_th_vlseg4e16_v_i16m2x4(const int16_t *base, size_t vl) { + return __riscv_vlseg4e16_v_i16m2x4(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_th_vlseg4e16_v_u16m1x4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.th.vlseg4e.nxv4i16.i64( poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , } [[TMP0]] +// +vuint16m1x4_t test_th_vlseg4e16_v_u16m1x4(const uint16_t *base, size_t vl) { + return __riscv_vlseg4e16_v_u16m1x4(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_th_vlseg4e16_v_u16m2x4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.th.vlseg4e.nxv8i16.i64( poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , } [[TMP0]] +// +vuint16m2x4_t test_th_vlseg4e16_v_u16m2x4(const uint16_t *base, size_t vl) { + return __riscv_vlseg4e16_v_u16m2x4(base, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg4e16ff.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg4e16ff.c new file mode 100644 index 00000000000000..7bf8409fa64087 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg4e16ff.c @@ -0,0 +1,127 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_th_vlseg4e16ff_v_f16m1x4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.th.vlseg4eff.nxv4f16.i64( poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP9]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , } [[TMP8]] +// +vfloat16m1x4_t test_th_vlseg4e16ff_v_f16m1x4(const _Float16 *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg4e16ff_v_f16m1x4(base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_th_vlseg4e16ff_v_f16m2x4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.th.vlseg4eff.nxv8f16.i64( poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP9]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , } [[TMP8]] +// +vfloat16m2x4_t test_th_vlseg4e16ff_v_f16m2x4(const _Float16 *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg4e16ff_v_f16m2x4(base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_th_vlseg4e16ff_v_i16m1x4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.th.vlseg4eff.nxv4i16.i64( poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP9]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , } [[TMP8]] +// +vint16m1x4_t test_th_vlseg4e16ff_v_i16m1x4(const int16_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg4e16ff_v_i16m1x4(base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_th_vlseg4e16ff_v_i16m2x4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.th.vlseg4eff.nxv8i16.i64( poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP9]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , } [[TMP8]] +// +vint16m2x4_t test_th_vlseg4e16ff_v_i16m2x4(const int16_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg4e16ff_v_i16m2x4(base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_th_vlseg4e16ff_v_u16m1x4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.th.vlseg4eff.nxv4i16.i64( poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP9]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , } [[TMP8]] +// +vuint16m1x4_t test_th_vlseg4e16ff_v_u16m1x4(const uint16_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg4e16ff_v_u16m1x4(base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_th_vlseg4e16ff_v_u16m2x4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.th.vlseg4eff.nxv8i16.i64( poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP9]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , } [[TMP8]] +// +vuint16m2x4_t test_th_vlseg4e16ff_v_u16m2x4(const uint16_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg4e16ff_v_u16m2x4(base, new_vl, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg4e32.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg4e32.c new file mode 100644 index 00000000000000..e111df6b093ca1 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg4e32.c @@ -0,0 +1,67 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_th_vlseg4e32_v_f32m1x4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.th.vlseg4e.nxv2f32.i64( poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , } [[TMP0]] +// +vfloat32m1x4_t test_th_vlseg4e32_v_f32m1x4(const float *base, size_t vl) { + return __riscv_vlseg4e32_v_f32m1x4(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_th_vlseg4e32_v_f32m2x4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.th.vlseg4e.nxv4f32.i64( poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , } [[TMP0]] +// +vfloat32m2x4_t test_th_vlseg4e32_v_f32m2x4(const float *base, size_t vl) { + return __riscv_vlseg4e32_v_f32m2x4(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_th_vlseg4e32_v_i32m1x4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.th.vlseg4e.nxv2i32.i64( poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , } [[TMP0]] +// +vint32m1x4_t test_th_vlseg4e32_v_i32m1x4(const int32_t *base, size_t vl) { + return __riscv_vlseg4e32_v_i32m1x4(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_th_vlseg4e32_v_i32m2x4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.th.vlseg4e.nxv4i32.i64( poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , } [[TMP0]] +// +vint32m2x4_t test_th_vlseg4e32_v_i32m2x4(const int32_t *base, size_t vl) { + return __riscv_vlseg4e32_v_i32m2x4(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_th_vlseg4e32_v_u32m1x4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.th.vlseg4e.nxv2i32.i64( poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , } [[TMP0]] +// +vuint32m1x4_t test_th_vlseg4e32_v_u32m1x4(const uint32_t *base, size_t vl) { + return __riscv_vlseg4e32_v_u32m1x4(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_th_vlseg4e32_v_u32m2x4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.th.vlseg4e.nxv4i32.i64( poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , } [[TMP0]] +// +vuint32m2x4_t test_th_vlseg4e32_v_u32m2x4(const uint32_t *base, size_t vl) { + return __riscv_vlseg4e32_v_u32m2x4(base, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg4e32ff.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg4e32ff.c new file mode 100644 index 00000000000000..1e87c3261ff568 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg4e32ff.c @@ -0,0 +1,128 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_th_vlseg4e32ff_v_f32m1x4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.th.vlseg4eff.nxv2f32.i64( poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP9]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , } [[TMP8]] +// +vfloat32m1x4_t test_th_vlseg4e32ff_v_f32m1x4(const float *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg4e32ff_v_f32m1x4(base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_th_vlseg4e32ff_v_f32m2x4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.th.vlseg4eff.nxv4f32.i64( poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP9]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , } [[TMP8]] +// +vfloat32m2x4_t test_th_vlseg4e32ff_v_f32m2x4(const float *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg4e32ff_v_f32m2x4(base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_th_vlseg4e32ff_v_i32m1x4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.th.vlseg4eff.nxv2i32.i64( poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP9]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , } [[TMP8]] +// +vint32m1x4_t test_th_vlseg4e32ff_v_i32m1x4(const int32_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg4e32ff_v_i32m1x4(base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_th_vlseg4e32ff_v_i32m2x4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.th.vlseg4eff.nxv4i32.i64( poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP9]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , } [[TMP8]] +// +vint32m2x4_t test_th_vlseg4e32ff_v_i32m2x4(const int32_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg4e32ff_v_i32m2x4(base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_th_vlseg4e32ff_v_u32m1x4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.th.vlseg4eff.nxv2i32.i64( poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP9]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , } [[TMP8]] +// +vuint32m1x4_t test_th_vlseg4e32ff_v_u32m1x4(const uint32_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg4e32ff_v_u32m1x4(base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_th_vlseg4e32ff_v_u32m2x4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.th.vlseg4eff.nxv4i32.i64( poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP9]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , } [[TMP8]] +// +vuint32m2x4_t test_th_vlseg4e32ff_v_u32m2x4(const uint32_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg4e32ff_v_u32m2x4(base, new_vl, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg4e64.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg4e64.c new file mode 100644 index 00000000000000..ab5b68937105ea --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg4e64.c @@ -0,0 +1,67 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_th_vlseg4e64_v_f64m1x4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.th.vlseg4e.nxv1f64.i64( poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , } [[TMP0]] +// +vfloat64m1x4_t test_th_vlseg4e64_v_f64m1x4(const double *base, size_t vl) { + return __riscv_vlseg4e64_v_f64m1x4(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_th_vlseg4e64_v_f64m2x4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.th.vlseg4e.nxv2f64.i64( poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , } [[TMP0]] +// +vfloat64m2x4_t test_th_vlseg4e64_v_f64m2x4(const double *base, size_t vl) { + return __riscv_vlseg4e64_v_f64m2x4(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_th_vlseg4e64_v_i64m1x4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.th.vlseg4e.nxv1i64.i64( poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , } [[TMP0]] +// +vint64m1x4_t test_th_vlseg4e64_v_i64m1x4(const int64_t *base, size_t vl) { + return __riscv_vlseg4e64_v_i64m1x4(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_th_vlseg4e64_v_i64m2x4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.th.vlseg4e.nxv2i64.i64( poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , } [[TMP0]] +// +vint64m2x4_t test_th_vlseg4e64_v_i64m2x4(const int64_t *base, size_t vl) { + return __riscv_vlseg4e64_v_i64m2x4(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_th_vlseg4e64_v_u64m1x4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.th.vlseg4e.nxv1i64.i64( poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , } [[TMP0]] +// +vuint64m1x4_t test_th_vlseg4e64_v_u64m1x4(const uint64_t *base, size_t vl) { + return __riscv_vlseg4e64_v_u64m1x4(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_th_vlseg4e64_v_u64m2x4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.th.vlseg4e.nxv2i64.i64( poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , } [[TMP0]] +// +vuint64m2x4_t test_th_vlseg4e64_v_u64m2x4(const uint64_t *base, size_t vl) { + return __riscv_vlseg4e64_v_u64m2x4(base, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg4e64ff.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg4e64ff.c new file mode 100644 index 00000000000000..d31795de99daa4 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg4e64ff.c @@ -0,0 +1,127 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_th_vlseg4e64ff_v_f64m1x4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.th.vlseg4eff.nxv1f64.i64( poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP9]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , } [[TMP8]] +// +vfloat64m1x4_t test_th_vlseg4e64ff_v_f64m1x4(const double *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg4e64ff_v_f64m1x4(base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_th_vlseg4e64ff_v_f64m2x4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.th.vlseg4eff.nxv2f64.i64( poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP9]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , } [[TMP8]] +// +vfloat64m2x4_t test_th_vlseg4e64ff_v_f64m2x4(const double *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg4e64ff_v_f64m2x4(base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_th_vlseg4e64ff_v_i64m1x4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.th.vlseg4eff.nxv1i64.i64( poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP9]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , } [[TMP8]] +// +vint64m1x4_t test_th_vlseg4e64ff_v_i64m1x4(const int64_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg4e64ff_v_i64m1x4(base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_th_vlseg4e64ff_v_i64m2x4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.th.vlseg4eff.nxv2i64.i64( poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP9]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , } [[TMP8]] +// +vint64m2x4_t test_th_vlseg4e64ff_v_i64m2x4(const int64_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg4e64ff_v_i64m2x4(base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_th_vlseg4e64ff_v_u64m1x4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.th.vlseg4eff.nxv1i64.i64( poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP9]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , } [[TMP8]] +// +vuint64m1x4_t test_th_vlseg4e64ff_v_u64m1x4(const uint64_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg4e64ff_v_u64m1x4(base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_th_vlseg4e64ff_v_u64m2x4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.th.vlseg4eff.nxv2i64.i64( poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP9]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , } [[TMP8]] +// +vuint64m2x4_t test_th_vlseg4e64ff_v_u64m2x4(const uint64_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg4e64ff_v_u64m2x4(base, new_vl, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg4e8.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg4e8.c new file mode 100644 index 00000000000000..b5a9ee2c183143 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg4e8.c @@ -0,0 +1,47 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_th_vlseg4e8_v_i8m1x4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.th.vlseg4e.nxv8i8.i64( poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , } [[TMP0]] +// +vint8m1x4_t test_th_vlseg4e8_v_i8m1x4(const int8_t *base, size_t vl) { + return __riscv_vlseg4e8_v_i8m1x4(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_th_vlseg4e8_v_i8m2x4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.th.vlseg4e.nxv16i8.i64( poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , } [[TMP0]] +// +vint8m2x4_t test_th_vlseg4e8_v_i8m2x4(const int8_t *base, size_t vl) { + return __riscv_vlseg4e8_v_i8m2x4(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_th_vlseg4e8_v_u8m1x4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.th.vlseg4e.nxv8i8.i64( poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , } [[TMP0]] +// +vuint8m1x4_t test_th_vlseg4e8_v_u8m1x4(const uint8_t *base, size_t vl) { + return __riscv_vlseg4e8_v_u8m1x4(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_th_vlseg4e8_v_u8m2x4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.th.vlseg4e.nxv16i8.i64( poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , } [[TMP0]] +// +vuint8m2x4_t test_th_vlseg4e8_v_u8m2x4(const uint8_t *base, size_t vl) { + return __riscv_vlseg4e8_v_u8m2x4(base, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg4e8ff.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg4e8ff.c new file mode 100644 index 00000000000000..4aa6d08f1af3be --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg4e8ff.c @@ -0,0 +1,87 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_th_vlseg4e8ff_v_i8m1x4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.th.vlseg4eff.nxv8i8.i64( poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP9]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , } [[TMP8]] +// +vint8m1x4_t test_th_vlseg4e8ff_v_i8m1x4(const int8_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg4e8ff_v_i8m1x4(base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_th_vlseg4e8ff_v_i8m2x4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.th.vlseg4eff.nxv16i8.i64( poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP9]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , } [[TMP8]] +// +vint8m2x4_t test_th_vlseg4e8ff_v_i8m2x4(const int8_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg4e8ff_v_i8m2x4(base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_th_vlseg4e8ff_v_u8m1x4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.th.vlseg4eff.nxv8i8.i64( poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP9]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , } [[TMP8]] +// +vuint8m1x4_t test_th_vlseg4e8ff_v_u8m1x4(const uint8_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg4e8ff_v_u8m1x4(base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_th_vlseg4e8ff_v_u8m2x4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.th.vlseg4eff.nxv16i8.i64( poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP9]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , } [[TMP8]] +// +vuint8m2x4_t test_th_vlseg4e8ff_v_u8m2x4(const uint8_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg4e8ff_v_u8m2x4(base, new_vl, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg5e16.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg5e16.c new file mode 100644 index 00000000000000..a355ce3c9a57d1 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg5e16.c @@ -0,0 +1,37 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_th_vlseg5e16_v_f16m1x5 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.th.vlseg5e.nxv4f16.i64( poison, poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP0]] +// +vfloat16m1x5_t test_th_vlseg5e16_v_f16m1x5(const _Float16 *base, size_t vl) { + return __riscv_vlseg5e16_v_f16m1x5(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_th_vlseg5e16_v_i16m1x5 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.th.vlseg5e.nxv4i16.i64( poison, poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP0]] +// +vint16m1x5_t test_th_vlseg5e16_v_i16m1x5(const int16_t *base, size_t vl) { + return __riscv_vlseg5e16_v_i16m1x5(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_th_vlseg5e16_v_u16m1x5 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.th.vlseg5e.nxv4i16.i64( poison, poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP0]] +// +vuint16m1x5_t test_th_vlseg5e16_v_u16m1x5(const uint16_t *base, size_t vl) { + return __riscv_vlseg5e16_v_u16m1x5(base, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg5e16ff.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg5e16ff.c new file mode 100644 index 00000000000000..abcfa8275fd9c2 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg5e16ff.c @@ -0,0 +1,73 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_th_vlseg5e16ff_v_f16m1x5 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , i64 } @llvm.riscv.th.vlseg5eff.nxv4f16.i64( poison, poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , } [[TMP8]], [[TMP9]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store i64 [[TMP11]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , } [[TMP10]] +// +vfloat16m1x5_t test_th_vlseg5e16ff_v_f16m1x5(const _Float16 *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg5e16ff_v_f16m1x5(base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_th_vlseg5e16ff_v_i16m1x5 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , i64 } @llvm.riscv.th.vlseg5eff.nxv4i16.i64( poison, poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , } [[TMP8]], [[TMP9]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store i64 [[TMP11]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , } [[TMP10]] +// +vint16m1x5_t test_th_vlseg5e16ff_v_i16m1x5(const int16_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg5e16ff_v_i16m1x5(base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_th_vlseg5e16ff_v_u16m1x5 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , i64 } @llvm.riscv.th.vlseg5eff.nxv4i16.i64( poison, poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , } [[TMP8]], [[TMP9]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store i64 [[TMP11]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , } [[TMP10]] +// +vuint16m1x5_t test_th_vlseg5e16ff_v_u16m1x5(const uint16_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg5e16ff_v_u16m1x5(base, new_vl, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg5e32.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg5e32.c new file mode 100644 index 00000000000000..37c07921812689 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg5e32.c @@ -0,0 +1,39 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_th_vlseg5e32_v_f32m1x5 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.th.vlseg5e.nxv2f32.i64( poison, poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP0]] +// +vfloat32m1x5_t test_th_vlseg5e32_v_f32m1x5(const float *base, size_t vl) { + return __riscv_vlseg5e32_v_f32m1x5(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_th_vlseg5e32_v_i32m1x5 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.th.vlseg5e.nxv2i32.i64( poison, poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP0]] +// +vint32m1x5_t test_th_vlseg5e32_v_i32m1x5(const int32_t *base, size_t vl) { + return __riscv_vlseg5e32_v_i32m1x5(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_th_vlseg5e32_v_u32m1x5 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.th.vlseg5e.nxv2i32.i64( poison, poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP0]] +// +vuint32m1x5_t test_th_vlseg5e32_v_u32m1x5(const uint32_t *base, size_t vl) { + return __riscv_vlseg5e32_v_u32m1x5(base, vl); +} + + diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg5e32ff.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg5e32ff.c new file mode 100644 index 00000000000000..f12bc2e633751b --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg5e32ff.c @@ -0,0 +1,73 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_th_vlseg5e32ff_v_f32m1x5 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , i64 } @llvm.riscv.th.vlseg5eff.nxv2f32.i64( poison, poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , } [[TMP8]], [[TMP9]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store i64 [[TMP11]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , } [[TMP10]] +// +vfloat32m1x5_t test_th_vlseg5e32ff_v_f32m1x5(const float *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg5e32ff_v_f32m1x5(base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_th_vlseg5e32ff_v_i32m1x5 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , i64 } @llvm.riscv.th.vlseg5eff.nxv2i32.i64( poison, poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , } [[TMP8]], [[TMP9]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store i64 [[TMP11]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , } [[TMP10]] +// +vint32m1x5_t test_th_vlseg5e32ff_v_i32m1x5(const int32_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg5e32ff_v_i32m1x5(base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_th_vlseg5e32ff_v_u32m1x5 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , i64 } @llvm.riscv.th.vlseg5eff.nxv2i32.i64( poison, poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , } [[TMP8]], [[TMP9]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store i64 [[TMP11]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , } [[TMP10]] +// +vuint32m1x5_t test_th_vlseg5e32ff_v_u32m1x5(const uint32_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg5e32ff_v_u32m1x5(base, new_vl, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg5e64.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg5e64.c new file mode 100644 index 00000000000000..0c22d4ceb29d77 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg5e64.c @@ -0,0 +1,37 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_th_vlseg5e64_v_f64m1x5 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.th.vlseg5e.nxv1f64.i64( poison, poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP0]] +// +vfloat64m1x5_t test_th_vlseg5e64_v_f64m1x5(const double *base, size_t vl) { + return __riscv_vlseg5e64_v_f64m1x5(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_th_vlseg5e64_v_i64m1x5 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.th.vlseg5e.nxv1i64.i64( poison, poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP0]] +// +vint64m1x5_t test_th_vlseg5e64_v_i64m1x5(const int64_t *base, size_t vl) { + return __riscv_vlseg5e64_v_i64m1x5(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_th_vlseg5e64_v_u64m1x5 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.th.vlseg5e.nxv1i64.i64( poison, poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP0]] +// +vuint64m1x5_t test_th_vlseg5e64_v_u64m1x5(const uint64_t *base, size_t vl) { + return __riscv_vlseg5e64_v_u64m1x5(base, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg5e64ff.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg5e64ff.c new file mode 100644 index 00000000000000..5ea9e1cc4f645d --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg5e64ff.c @@ -0,0 +1,73 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_th_vlseg5e64ff_v_f64m1x5 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , i64 } @llvm.riscv.th.vlseg5eff.nxv1f64.i64( poison, poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , } [[TMP8]], [[TMP9]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store i64 [[TMP11]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , } [[TMP10]] +// +vfloat64m1x5_t test_th_vlseg5e64ff_v_f64m1x5(const double *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg5e64ff_v_f64m1x5(base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_th_vlseg5e64ff_v_i64m1x5 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , i64 } @llvm.riscv.th.vlseg5eff.nxv1i64.i64( poison, poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , } [[TMP8]], [[TMP9]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store i64 [[TMP11]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , } [[TMP10]] +// +vint64m1x5_t test_th_vlseg5e64ff_v_i64m1x5(const int64_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg5e64ff_v_i64m1x5(base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_th_vlseg5e64ff_v_u64m1x5 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , i64 } @llvm.riscv.th.vlseg5eff.nxv1i64.i64( poison, poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , } [[TMP8]], [[TMP9]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store i64 [[TMP11]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , } [[TMP10]] +// +vuint64m1x5_t test_th_vlseg5e64ff_v_u64m1x5(const uint64_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg5e64ff_v_u64m1x5(base, new_vl, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg5e8.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg5e8.c new file mode 100644 index 00000000000000..1f84fdaf91ea54 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg5e8.c @@ -0,0 +1,27 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_th_vlseg5e8_v_i8m1x5 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.th.vlseg5e.nxv8i8.i64( poison, poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP0]] +// +vint8m1x5_t test_th_vlseg5e8_v_i8m1x5(const int8_t *base, size_t vl) { + return __riscv_vlseg5e8_v_i8m1x5(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_th_vlseg5e8_v_u8m1x5 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.th.vlseg5e.nxv8i8.i64( poison, poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP0]] +// +vuint8m1x5_t test_th_vlseg5e8_v_u8m1x5(const uint8_t *base, size_t vl) { + return __riscv_vlseg5e8_v_u8m1x5(base, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg5e8ff.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg5e8ff.c new file mode 100644 index 00000000000000..50b4ee25fd9209 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg5e8ff.c @@ -0,0 +1,51 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_th_vlseg5e8ff_v_i8m1x5 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , i64 } @llvm.riscv.th.vlseg5eff.nxv8i8.i64( poison, poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , } [[TMP8]], [[TMP9]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store i64 [[TMP11]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , } [[TMP10]] +// +vint8m1x5_t test_th_vlseg5e8ff_v_i8m1x5(const int8_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg5e8ff_v_i8m1x5(base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_th_vlseg5e8ff_v_u8m1x5 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , i64 } @llvm.riscv.th.vlseg5eff.nxv8i8.i64( poison, poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , } [[TMP8]], [[TMP9]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store i64 [[TMP11]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , } [[TMP10]] +// +vuint8m1x5_t test_th_vlseg5e8ff_v_u8m1x5(const uint8_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg5e8ff_v_u8m1x5(base, new_vl, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg6e16.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg6e16.c new file mode 100644 index 00000000000000..648a6ca8d5d462 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg6e16.c @@ -0,0 +1,37 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_th_vlseg6e16_v_f16m1x6 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.th.vlseg6e.nxv4f16.i64( poison, poison, poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP0]] +// +vfloat16m1x6_t test_th_vlseg6e16_v_f16m1x6(const _Float16 *base, size_t vl) { + return __riscv_vlseg6e16_v_f16m1x6(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_th_vlseg6e16_v_i16m1x6 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.th.vlseg6e.nxv4i16.i64( poison, poison, poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP0]] +// +vint16m1x6_t test_th_vlseg6e16_v_i16m1x6(const int16_t *base, size_t vl) { + return __riscv_vlseg6e16_v_i16m1x6(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_th_vlseg6e16_v_u16m1x6 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.th.vlseg6e.nxv4i16.i64( poison, poison, poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP0]] +// +vuint16m1x6_t test_th_vlseg6e16_v_u16m1x6(const uint16_t *base, size_t vl) { + return __riscv_vlseg6e16_v_u16m1x6(base, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg6e16ff.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg6e16ff.c new file mode 100644 index 00000000000000..fb7264c4917014 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg6e16ff.c @@ -0,0 +1,79 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_th_vlseg6e16ff_v_f16m1x6 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , i64 } @llvm.riscv.th.vlseg6eff.nxv4f16.i64( poison, poison, poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , } [[TMP8]], [[TMP9]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , } [[TMP10]], [[TMP11]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: store i64 [[TMP13]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP12]] +// +vfloat16m1x6_t test_th_vlseg6e16ff_v_f16m1x6(const _Float16 *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg6e16ff_v_f16m1x6(base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_th_vlseg6e16ff_v_i16m1x6 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , i64 } @llvm.riscv.th.vlseg6eff.nxv4i16.i64( poison, poison, poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , } [[TMP8]], [[TMP9]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , } [[TMP10]], [[TMP11]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: store i64 [[TMP13]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP12]] +// +vint16m1x6_t test_th_vlseg6e16ff_v_i16m1x6(const int16_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg6e16ff_v_i16m1x6(base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_th_vlseg6e16ff_v_u16m1x6 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , i64 } @llvm.riscv.th.vlseg6eff.nxv4i16.i64( poison, poison, poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , } [[TMP8]], [[TMP9]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , } [[TMP10]], [[TMP11]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: store i64 [[TMP13]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP12]] +// +vuint16m1x6_t test_th_vlseg6e16ff_v_u16m1x6(const uint16_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg6e16ff_v_u16m1x6(base, new_vl, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg6e32.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg6e32.c new file mode 100644 index 00000000000000..2e339c8a06de35 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg6e32.c @@ -0,0 +1,37 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_th_vlseg6e32_v_f32m1x6 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.th.vlseg6e.nxv2f32.i64( poison, poison, poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP0]] +// +vfloat32m1x6_t test_th_vlseg6e32_v_f32m1x6(const float *base, size_t vl) { + return __riscv_vlseg6e32_v_f32m1x6(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_th_vlseg6e32_v_i32m1x6 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.th.vlseg6e.nxv2i32.i64( poison, poison, poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP0]] +// +vint32m1x6_t test_th_vlseg6e32_v_i32m1x6(const int32_t *base, size_t vl) { + return __riscv_vlseg6e32_v_i32m1x6(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_th_vlseg6e32_v_u32m1x6 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.th.vlseg6e.nxv2i32.i64( poison, poison, poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP0]] +// +vuint32m1x6_t test_th_vlseg6e32_v_u32m1x6(const uint32_t *base, size_t vl) { + return __riscv_vlseg6e32_v_u32m1x6(base, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg6e32ff.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg6e32ff.c new file mode 100644 index 00000000000000..a779551cecaf27 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg6e32ff.c @@ -0,0 +1,79 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_th_vlseg6e32ff_v_f32m1x6 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , i64 } @llvm.riscv.th.vlseg6eff.nxv2f32.i64( poison, poison, poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , } [[TMP8]], [[TMP9]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , } [[TMP10]], [[TMP11]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: store i64 [[TMP13]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP12]] +// +vfloat32m1x6_t test_th_vlseg6e32ff_v_f32m1x6(const float *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg6e32ff_v_f32m1x6(base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_th_vlseg6e32ff_v_i32m1x6 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , i64 } @llvm.riscv.th.vlseg6eff.nxv2i32.i64( poison, poison, poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , } [[TMP8]], [[TMP9]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , } [[TMP10]], [[TMP11]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: store i64 [[TMP13]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP12]] +// +vint32m1x6_t test_th_vlseg6e32ff_v_i32m1x6(const int32_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg6e32ff_v_i32m1x6(base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_th_vlseg6e32ff_v_u32m1x6 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , i64 } @llvm.riscv.th.vlseg6eff.nxv2i32.i64( poison, poison, poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , } [[TMP8]], [[TMP9]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , } [[TMP10]], [[TMP11]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: store i64 [[TMP13]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP12]] +// +vuint32m1x6_t test_th_vlseg6e32ff_v_u32m1x6(const uint32_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg6e32ff_v_u32m1x6(base, new_vl, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg6e64.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg6e64.c new file mode 100644 index 00000000000000..c1c217ae8fabad --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg6e64.c @@ -0,0 +1,37 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_th_vlseg6e64_v_f64m1x6 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.th.vlseg6e.nxv1f64.i64( poison, poison, poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP0]] +// +vfloat64m1x6_t test_th_vlseg6e64_v_f64m1x6(const double *base, size_t vl) { + return __riscv_vlseg6e64_v_f64m1x6(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_th_vlseg6e64_v_i64m1x6 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.th.vlseg6e.nxv1i64.i64( poison, poison, poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP0]] +// +vint64m1x6_t test_th_vlseg6e64_v_i64m1x6(const int64_t *base, size_t vl) { + return __riscv_vlseg6e64_v_i64m1x6(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_th_vlseg6e64_v_u64m1x6 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.th.vlseg6e.nxv1i64.i64( poison, poison, poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP0]] +// +vuint64m1x6_t test_th_vlseg6e64_v_u64m1x6(const uint64_t *base, size_t vl) { + return __riscv_vlseg6e64_v_u64m1x6(base, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg6e64ff.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg6e64ff.c new file mode 100644 index 00000000000000..9b0ca28757c576 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg6e64ff.c @@ -0,0 +1,79 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_th_vlseg6e64ff_v_f64m1x6 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , i64 } @llvm.riscv.th.vlseg6eff.nxv1f64.i64( poison, poison, poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , } [[TMP8]], [[TMP9]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , } [[TMP10]], [[TMP11]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: store i64 [[TMP13]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP12]] +// +vfloat64m1x6_t test_th_vlseg6e64ff_v_f64m1x6(const double *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg6e64ff_v_f64m1x6(base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_th_vlseg6e64ff_v_i64m1x6 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , i64 } @llvm.riscv.th.vlseg6eff.nxv1i64.i64( poison, poison, poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , } [[TMP8]], [[TMP9]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , } [[TMP10]], [[TMP11]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: store i64 [[TMP13]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP12]] +// +vint64m1x6_t test_th_vlseg6e64ff_v_i64m1x6(const int64_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg6e64ff_v_i64m1x6(base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_th_vlseg6e64ff_v_u64m1x6 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , i64 } @llvm.riscv.th.vlseg6eff.nxv1i64.i64( poison, poison, poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , } [[TMP8]], [[TMP9]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , } [[TMP10]], [[TMP11]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: store i64 [[TMP13]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP12]] +// +vuint64m1x6_t test_th_vlseg6e64ff_v_u64m1x6(const uint64_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg6e64ff_v_u64m1x6(base, new_vl, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg6e8.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg6e8.c new file mode 100644 index 00000000000000..25b1b4e1affe45 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg6e8.c @@ -0,0 +1,27 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_th_vlseg6e8_v_i8m1x6 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.th.vlseg6e.nxv8i8.i64( poison, poison, poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP0]] +// +vint8m1x6_t test_th_vlseg6e8_v_i8m1x6(const int8_t *base, size_t vl) { + return __riscv_vlseg6e8_v_i8m1x6(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_th_vlseg6e8_v_u8m1x6 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.th.vlseg6e.nxv8i8.i64( poison, poison, poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP0]] +// +vuint8m1x6_t test_th_vlseg6e8_v_u8m1x6(const uint8_t *base, size_t vl) { + return __riscv_vlseg6e8_v_u8m1x6(base, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg6e8ff.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg6e8ff.c new file mode 100644 index 00000000000000..474eb04aac0cd8 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg6e8ff.c @@ -0,0 +1,55 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_th_vlseg6e8ff_v_i8m1x6 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , i64 } @llvm.riscv.th.vlseg6eff.nxv8i8.i64( poison, poison, poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , } [[TMP8]], [[TMP9]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , } [[TMP10]], [[TMP11]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: store i64 [[TMP13]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP12]] +// +vint8m1x6_t test_th_vlseg6e8ff_v_i8m1x6(const int8_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg6e8ff_v_i8m1x6(base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_th_vlseg6e8ff_v_u8m1x6 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , i64 } @llvm.riscv.th.vlseg6eff.nxv8i8.i64( poison, poison, poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , } [[TMP8]], [[TMP9]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , } [[TMP10]], [[TMP11]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: store i64 [[TMP13]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP12]] +// +vuint8m1x6_t test_th_vlseg6e8ff_v_u8m1x6(const uint8_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg6e8ff_v_u8m1x6(base, new_vl, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg7e16.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg7e16.c new file mode 100644 index 00000000000000..da08de0be26e88 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg7e16.c @@ -0,0 +1,37 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_th_vlseg7e16_v_f16m1x7 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.th.vlseg7e.nxv4f16.i64( poison, poison, poison, poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP0]] +// +vfloat16m1x7_t test_th_vlseg7e16_v_f16m1x7(const _Float16 *base, size_t vl) { + return __riscv_vlseg7e16_v_f16m1x7(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_th_vlseg7e16_v_i16m1x7 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.th.vlseg7e.nxv4i16.i64( poison, poison, poison, poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP0]] +// +vint16m1x7_t test_th_vlseg7e16_v_i16m1x7(const int16_t *base, size_t vl) { + return __riscv_vlseg7e16_v_i16m1x7(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_th_vlseg7e16_v_u16m1x7 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.th.vlseg7e.nxv4i16.i64( poison, poison, poison, poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP0]] +// +vuint16m1x7_t test_th_vlseg7e16_v_u16m1x7(const uint16_t *base, size_t vl) { + return __riscv_vlseg7e16_v_u16m1x7(base, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg7e16ff.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg7e16ff.c new file mode 100644 index 00000000000000..e2158e636bc3c0 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg7e16ff.c @@ -0,0 +1,85 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_th_vlseg7e16ff_v_f16m1x7 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , i64 } @llvm.riscv.th.vlseg7eff.nxv4f16.i64( poison, poison, poison, poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , , } [[TMP8]], [[TMP9]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , , } [[TMP10]], [[TMP11]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = insertvalue { , , , , , , } [[TMP12]], [[TMP13]], 6 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 7 +// CHECK-RV64-NEXT: store i64 [[TMP15]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP14]] +// +vfloat16m1x7_t test_th_vlseg7e16ff_v_f16m1x7(const _Float16 *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg7e16ff_v_f16m1x7(base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_th_vlseg7e16ff_v_i16m1x7 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , i64 } @llvm.riscv.th.vlseg7eff.nxv4i16.i64( poison, poison, poison, poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , , } [[TMP8]], [[TMP9]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , , } [[TMP10]], [[TMP11]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = insertvalue { , , , , , , } [[TMP12]], [[TMP13]], 6 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 7 +// CHECK-RV64-NEXT: store i64 [[TMP15]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP14]] +// +vint16m1x7_t test_th_vlseg7e16ff_v_i16m1x7(const int16_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg7e16ff_v_i16m1x7(base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_th_vlseg7e16ff_v_u16m1x7 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , i64 } @llvm.riscv.th.vlseg7eff.nxv4i16.i64( poison, poison, poison, poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , , } [[TMP8]], [[TMP9]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , , } [[TMP10]], [[TMP11]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = insertvalue { , , , , , , } [[TMP12]], [[TMP13]], 6 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 7 +// CHECK-RV64-NEXT: store i64 [[TMP15]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP14]] +// +vuint16m1x7_t test_th_vlseg7e16ff_v_u16m1x7(const uint16_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg7e16ff_v_u16m1x7(base, new_vl, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg7e32.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg7e32.c new file mode 100644 index 00000000000000..4184aac6fb54b5 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg7e32.c @@ -0,0 +1,37 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_th_vlseg7e32_v_f32m1x7 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.th.vlseg7e.nxv2f32.i64( poison, poison, poison, poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP0]] +// +vfloat32m1x7_t test_th_vlseg7e32_v_f32m1x7(const float *base, size_t vl) { + return __riscv_vlseg7e32_v_f32m1x7(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_th_vlseg7e32_v_i32m1x7 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.th.vlseg7e.nxv2i32.i64( poison, poison, poison, poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP0]] +// +vint32m1x7_t test_th_vlseg7e32_v_i32m1x7(const int32_t *base, size_t vl) { + return __riscv_vlseg7e32_v_i32m1x7(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_th_vlseg7e32_v_u32m1x7 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.th.vlseg7e.nxv2i32.i64( poison, poison, poison, poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP0]] +// +vuint32m1x7_t test_th_vlseg7e32_v_u32m1x7(const uint32_t *base, size_t vl) { + return __riscv_vlseg7e32_v_u32m1x7(base, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg7e32ff.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg7e32ff.c new file mode 100644 index 00000000000000..f130f30000b6fc --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg7e32ff.c @@ -0,0 +1,85 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_th_vlseg7e32ff_v_f32m1x7 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , i64 } @llvm.riscv.th.vlseg7eff.nxv2f32.i64( poison, poison, poison, poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , , } [[TMP8]], [[TMP9]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , , } [[TMP10]], [[TMP11]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = insertvalue { , , , , , , } [[TMP12]], [[TMP13]], 6 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 7 +// CHECK-RV64-NEXT: store i64 [[TMP15]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP14]] +// +vfloat32m1x7_t test_th_vlseg7e32ff_v_f32m1x7(const float *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg7e32ff_v_f32m1x7(base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_th_vlseg7e32ff_v_i32m1x7 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , i64 } @llvm.riscv.th.vlseg7eff.nxv2i32.i64( poison, poison, poison, poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , , } [[TMP8]], [[TMP9]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , , } [[TMP10]], [[TMP11]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = insertvalue { , , , , , , } [[TMP12]], [[TMP13]], 6 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 7 +// CHECK-RV64-NEXT: store i64 [[TMP15]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP14]] +// +vint32m1x7_t test_th_vlseg7e32ff_v_i32m1x7(const int32_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg7e32ff_v_i32m1x7(base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_th_vlseg7e32ff_v_u32m1x7 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , i64 } @llvm.riscv.th.vlseg7eff.nxv2i32.i64( poison, poison, poison, poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , , } [[TMP8]], [[TMP9]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , , } [[TMP10]], [[TMP11]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = insertvalue { , , , , , , } [[TMP12]], [[TMP13]], 6 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 7 +// CHECK-RV64-NEXT: store i64 [[TMP15]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP14]] +// +vuint32m1x7_t test_th_vlseg7e32ff_v_u32m1x7(const uint32_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg7e32ff_v_u32m1x7(base, new_vl, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg7e64.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg7e64.c new file mode 100644 index 00000000000000..08cdb9a3df6ce0 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg7e64.c @@ -0,0 +1,37 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_th_vlseg7e64_v_f64m1x7 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.th.vlseg7e.nxv1f64.i64( poison, poison, poison, poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP0]] +// +vfloat64m1x7_t test_th_vlseg7e64_v_f64m1x7(const double *base, size_t vl) { + return __riscv_vlseg7e64_v_f64m1x7(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_th_vlseg7e64_v_i64m1x7 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.th.vlseg7e.nxv1i64.i64( poison, poison, poison, poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP0]] +// +vint64m1x7_t test_th_vlseg7e64_v_i64m1x7(const int64_t *base, size_t vl) { + return __riscv_vlseg7e64_v_i64m1x7(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_th_vlseg7e64_v_u64m1x7 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.th.vlseg7e.nxv1i64.i64( poison, poison, poison, poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP0]] +// +vuint64m1x7_t test_th_vlseg7e64_v_u64m1x7(const uint64_t *base, size_t vl) { + return __riscv_vlseg7e64_v_u64m1x7(base, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg7e64ff.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg7e64ff.c new file mode 100644 index 00000000000000..47c7f4f208dc6c --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg7e64ff.c @@ -0,0 +1,85 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_th_vlseg7e64ff_v_f64m1x7 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , i64 } @llvm.riscv.th.vlseg7eff.nxv1f64.i64( poison, poison, poison, poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , , } [[TMP8]], [[TMP9]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , , } [[TMP10]], [[TMP11]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = insertvalue { , , , , , , } [[TMP12]], [[TMP13]], 6 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 7 +// CHECK-RV64-NEXT: store i64 [[TMP15]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP14]] +// +vfloat64m1x7_t test_th_vlseg7e64ff_v_f64m1x7(const double *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg7e64ff_v_f64m1x7(base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_th_vlseg7e64ff_v_i64m1x7 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , i64 } @llvm.riscv.th.vlseg7eff.nxv1i64.i64( poison, poison, poison, poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , , } [[TMP8]], [[TMP9]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , , } [[TMP10]], [[TMP11]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = insertvalue { , , , , , , } [[TMP12]], [[TMP13]], 6 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 7 +// CHECK-RV64-NEXT: store i64 [[TMP15]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP14]] +// +vint64m1x7_t test_th_vlseg7e64ff_v_i64m1x7(const int64_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg7e64ff_v_i64m1x7(base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_th_vlseg7e64ff_v_u64m1x7 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , i64 } @llvm.riscv.th.vlseg7eff.nxv1i64.i64( poison, poison, poison, poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , , } [[TMP8]], [[TMP9]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , , } [[TMP10]], [[TMP11]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = insertvalue { , , , , , , } [[TMP12]], [[TMP13]], 6 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 7 +// CHECK-RV64-NEXT: store i64 [[TMP15]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP14]] +// +vuint64m1x7_t test_th_vlseg7e64ff_v_u64m1x7(const uint64_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg7e64ff_v_u64m1x7(base, new_vl, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg7e8.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg7e8.c new file mode 100644 index 00000000000000..e4b9160266328c --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg7e8.c @@ -0,0 +1,28 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_th_vlseg7e8_v_i8m1x7 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.th.vlseg7e.nxv8i8.i64( poison, poison, poison, poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP0]] +// +vint8m1x7_t test_th_vlseg7e8_v_i8m1x7(const int8_t *base, size_t vl) { + return __riscv_vlseg7e8_v_i8m1x7(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_th_vlseg7e8_v_u8m1x7 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.th.vlseg7e.nxv8i8.i64( poison, poison, poison, poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP0]] +// +vuint8m1x7_t test_th_vlseg7e8_v_u8m1x7(const uint8_t *base, size_t vl) { + return __riscv_vlseg7e8_v_u8m1x7(base, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg7e8ff.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg7e8ff.c new file mode 100644 index 00000000000000..7ec70f5e86b106 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg7e8ff.c @@ -0,0 +1,59 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_th_vlseg7e8ff_v_i8m1x7 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , i64 } @llvm.riscv.th.vlseg7eff.nxv8i8.i64( poison, poison, poison, poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , , } [[TMP8]], [[TMP9]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , , } [[TMP10]], [[TMP11]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = insertvalue { , , , , , , } [[TMP12]], [[TMP13]], 6 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 7 +// CHECK-RV64-NEXT: store i64 [[TMP15]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP14]] +// +vint8m1x7_t test_th_vlseg7e8ff_v_i8m1x7(const int8_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg7e8ff_v_i8m1x7(base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_th_vlseg7e8ff_v_u8m1x7 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , i64 } @llvm.riscv.th.vlseg7eff.nxv8i8.i64( poison, poison, poison, poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , , } [[TMP8]], [[TMP9]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , , } [[TMP10]], [[TMP11]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = insertvalue { , , , , , , } [[TMP12]], [[TMP13]], 6 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 7 +// CHECK-RV64-NEXT: store i64 [[TMP15]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP14]] +// +vuint8m1x7_t test_th_vlseg7e8ff_v_u8m1x7(const uint8_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg7e8ff_v_u8m1x7(base, new_vl, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg8e16.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg8e16.c new file mode 100644 index 00000000000000..ea3eeff6fc1d74 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg8e16.c @@ -0,0 +1,37 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_th_vlseg8e16_v_f16m1x8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.th.vlseg8e.nxv4f16.i64( poison, poison, poison, poison, poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP0]] +// +vfloat16m1x8_t test_th_vlseg8e16_v_f16m1x8(const _Float16 *base, size_t vl) { + return __riscv_vlseg8e16_v_f16m1x8(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_th_vlseg8e16_v_i16m1x8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.th.vlseg8e.nxv4i16.i64( poison, poison, poison, poison, poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP0]] +// +vint16m1x8_t test_th_vlseg8e16_v_i16m1x8(const int16_t *base, size_t vl) { + return __riscv_vlseg8e16_v_i16m1x8(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_th_vlseg8e16_v_u16m1x8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.th.vlseg8e.nxv4i16.i64( poison, poison, poison, poison, poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP0]] +// +vuint16m1x8_t test_th_vlseg8e16_v_u16m1x8(const uint16_t *base, size_t vl) { + return __riscv_vlseg8e16_v_u16m1x8(base, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg8e16ff.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg8e16ff.c new file mode 100644 index 00000000000000..273b2f3b405779 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg8e16ff.c @@ -0,0 +1,91 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_th_vlseg8e16ff_v_f16m1x8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.th.vlseg8eff.nxv4f16.i64( poison, poison, poison, poison, poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , , , } [[TMP8]], [[TMP9]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , , , } [[TMP10]], [[TMP11]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = insertvalue { , , , , , , , } [[TMP12]], [[TMP13]], 6 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 7 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = insertvalue { , , , , , , , } [[TMP14]], [[TMP15]], 7 +// CHECK-RV64-NEXT: [[TMP17:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 8 +// CHECK-RV64-NEXT: store i64 [[TMP17]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP16]] +// +vfloat16m1x8_t test_th_vlseg8e16ff_v_f16m1x8(const _Float16 *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg8e16ff_v_f16m1x8(base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_th_vlseg8e16ff_v_i16m1x8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.th.vlseg8eff.nxv4i16.i64( poison, poison, poison, poison, poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , , , } [[TMP8]], [[TMP9]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , , , } [[TMP10]], [[TMP11]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = insertvalue { , , , , , , , } [[TMP12]], [[TMP13]], 6 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 7 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = insertvalue { , , , , , , , } [[TMP14]], [[TMP15]], 7 +// CHECK-RV64-NEXT: [[TMP17:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 8 +// CHECK-RV64-NEXT: store i64 [[TMP17]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP16]] +// +vint16m1x8_t test_th_vlseg8e16ff_v_i16m1x8(const int16_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg8e16ff_v_i16m1x8(base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_th_vlseg8e16ff_v_u16m1x8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.th.vlseg8eff.nxv4i16.i64( poison, poison, poison, poison, poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , , , } [[TMP8]], [[TMP9]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , , , } [[TMP10]], [[TMP11]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = insertvalue { , , , , , , , } [[TMP12]], [[TMP13]], 6 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 7 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = insertvalue { , , , , , , , } [[TMP14]], [[TMP15]], 7 +// CHECK-RV64-NEXT: [[TMP17:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 8 +// CHECK-RV64-NEXT: store i64 [[TMP17]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP16]] +// +vuint16m1x8_t test_th_vlseg8e16ff_v_u16m1x8(const uint16_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg8e16ff_v_u16m1x8(base, new_vl, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg8e32.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg8e32.c new file mode 100644 index 00000000000000..d1462faf7d56dd --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg8e32.c @@ -0,0 +1,37 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_th_vlseg8e32_v_f32m1x8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.th.vlseg8e.nxv2f32.i64( poison, poison, poison, poison, poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP0]] +// +vfloat32m1x8_t test_th_vlseg8e32_v_f32m1x8(const float *base, size_t vl) { + return __riscv_vlseg8e32_v_f32m1x8(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_th_vlseg8e32_v_i32m1x8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.th.vlseg8e.nxv2i32.i64( poison, poison, poison, poison, poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP0]] +// +vint32m1x8_t test_th_vlseg8e32_v_i32m1x8(const int32_t *base, size_t vl) { + return __riscv_vlseg8e32_v_i32m1x8(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_th_vlseg8e32_v_u32m1x8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.th.vlseg8e.nxv2i32.i64( poison, poison, poison, poison, poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP0]] +// +vuint32m1x8_t test_th_vlseg8e32_v_u32m1x8(const uint32_t *base, size_t vl) { + return __riscv_vlseg8e32_v_u32m1x8(base, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg8e32ff.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg8e32ff.c new file mode 100644 index 00000000000000..284014b4bc7715 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg8e32ff.c @@ -0,0 +1,91 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_th_vlseg8e32ff_v_f32m1x8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.th.vlseg8eff.nxv2f32.i64( poison, poison, poison, poison, poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , , , } [[TMP8]], [[TMP9]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , , , } [[TMP10]], [[TMP11]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = insertvalue { , , , , , , , } [[TMP12]], [[TMP13]], 6 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 7 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = insertvalue { , , , , , , , } [[TMP14]], [[TMP15]], 7 +// CHECK-RV64-NEXT: [[TMP17:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 8 +// CHECK-RV64-NEXT: store i64 [[TMP17]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP16]] +// +vfloat32m1x8_t test_th_vlseg8e32ff_v_f32m1x8(const float *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg8e32ff_v_f32m1x8(base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_th_vlseg8e32ff_v_i32m1x8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.th.vlseg8eff.nxv2i32.i64( poison, poison, poison, poison, poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , , , } [[TMP8]], [[TMP9]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , , , } [[TMP10]], [[TMP11]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = insertvalue { , , , , , , , } [[TMP12]], [[TMP13]], 6 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 7 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = insertvalue { , , , , , , , } [[TMP14]], [[TMP15]], 7 +// CHECK-RV64-NEXT: [[TMP17:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 8 +// CHECK-RV64-NEXT: store i64 [[TMP17]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP16]] +// +vint32m1x8_t test_th_vlseg8e32ff_v_i32m1x8(const int32_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg8e32ff_v_i32m1x8(base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_th_vlseg8e32ff_v_u32m1x8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.th.vlseg8eff.nxv2i32.i64( poison, poison, poison, poison, poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , , , } [[TMP8]], [[TMP9]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , , , } [[TMP10]], [[TMP11]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = insertvalue { , , , , , , , } [[TMP12]], [[TMP13]], 6 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 7 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = insertvalue { , , , , , , , } [[TMP14]], [[TMP15]], 7 +// CHECK-RV64-NEXT: [[TMP17:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 8 +// CHECK-RV64-NEXT: store i64 [[TMP17]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP16]] +// +vuint32m1x8_t test_th_vlseg8e32ff_v_u32m1x8(const uint32_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg8e32ff_v_u32m1x8(base, new_vl, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg8e64.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg8e64.c new file mode 100644 index 00000000000000..9add693d1738d1 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg8e64.c @@ -0,0 +1,37 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_th_vlseg8e64_v_f64m1x8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.th.vlseg8e.nxv1f64.i64( poison, poison, poison, poison, poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP0]] +// +vfloat64m1x8_t test_th_vlseg8e64_v_f64m1x8(const double *base, size_t vl) { + return __riscv_vlseg8e64_v_f64m1x8(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_th_vlseg8e64_v_i64m1x8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.th.vlseg8e.nxv1i64.i64( poison, poison, poison, poison, poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP0]] +// +vint64m1x8_t test_th_vlseg8e64_v_i64m1x8(const int64_t *base, size_t vl) { + return __riscv_vlseg8e64_v_i64m1x8(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_th_vlseg8e64_v_u64m1x8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.th.vlseg8e.nxv1i64.i64( poison, poison, poison, poison, poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP0]] +// +vuint64m1x8_t test_th_vlseg8e64_v_u64m1x8(const uint64_t *base, size_t vl) { + return __riscv_vlseg8e64_v_u64m1x8(base, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg8e64ff.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg8e64ff.c new file mode 100644 index 00000000000000..13d6633b56989c --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg8e64ff.c @@ -0,0 +1,91 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_th_vlseg8e64ff_v_f64m1x8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.th.vlseg8eff.nxv1f64.i64( poison, poison, poison, poison, poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , , , } [[TMP8]], [[TMP9]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , , , } [[TMP10]], [[TMP11]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = insertvalue { , , , , , , , } [[TMP12]], [[TMP13]], 6 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 7 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = insertvalue { , , , , , , , } [[TMP14]], [[TMP15]], 7 +// CHECK-RV64-NEXT: [[TMP17:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 8 +// CHECK-RV64-NEXT: store i64 [[TMP17]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP16]] +// +vfloat64m1x8_t test_th_vlseg8e64ff_v_f64m1x8(const double *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg8e64ff_v_f64m1x8(base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_th_vlseg8e64ff_v_i64m1x8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.th.vlseg8eff.nxv1i64.i64( poison, poison, poison, poison, poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , , , } [[TMP8]], [[TMP9]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , , , } [[TMP10]], [[TMP11]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = insertvalue { , , , , , , , } [[TMP12]], [[TMP13]], 6 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 7 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = insertvalue { , , , , , , , } [[TMP14]], [[TMP15]], 7 +// CHECK-RV64-NEXT: [[TMP17:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 8 +// CHECK-RV64-NEXT: store i64 [[TMP17]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP16]] +// +vint64m1x8_t test_th_vlseg8e64ff_v_i64m1x8(const int64_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg8e64ff_v_i64m1x8(base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_th_vlseg8e64ff_v_u64m1x8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.th.vlseg8eff.nxv1i64.i64( poison, poison, poison, poison, poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , , , } [[TMP8]], [[TMP9]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , , , } [[TMP10]], [[TMP11]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = insertvalue { , , , , , , , } [[TMP12]], [[TMP13]], 6 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 7 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = insertvalue { , , , , , , , } [[TMP14]], [[TMP15]], 7 +// CHECK-RV64-NEXT: [[TMP17:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 8 +// CHECK-RV64-NEXT: store i64 [[TMP17]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP16]] +// +vuint64m1x8_t test_th_vlseg8e64ff_v_u64m1x8(const uint64_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg8e64ff_v_u64m1x8(base, new_vl, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg8e8.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg8e8.c new file mode 100644 index 00000000000000..4bf833887eb887 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg8e8.c @@ -0,0 +1,28 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_th_vlseg8e8_v_i8m1x8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.th.vlseg8e.nxv8i8.i64( poison, poison, poison, poison, poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP0]] +// +vint8m1x8_t test_th_vlseg8e8_v_i8m1x8(const int8_t *base, size_t vl) { + return __riscv_vlseg8e8_v_i8m1x8(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_th_vlseg8e8_v_u8m1x8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.th.vlseg8e.nxv8i8.i64( poison, poison, poison, poison, poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP0]] +// +vuint8m1x8_t test_th_vlseg8e8_v_u8m1x8(const uint8_t *base, size_t vl) { + return __riscv_vlseg8e8_v_u8m1x8(base, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg8e8ff.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg8e8ff.c new file mode 100644 index 00000000000000..528fc62bc8bebe --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vlseg8e8ff.c @@ -0,0 +1,63 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_th_vlseg8e8ff_v_i8m1x8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.th.vlseg8eff.nxv8i8.i64( poison, poison, poison, poison, poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , , , } [[TMP8]], [[TMP9]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , , , } [[TMP10]], [[TMP11]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = insertvalue { , , , , , , , } [[TMP12]], [[TMP13]], 6 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 7 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = insertvalue { , , , , , , , } [[TMP14]], [[TMP15]], 7 +// CHECK-RV64-NEXT: [[TMP17:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 8 +// CHECK-RV64-NEXT: store i64 [[TMP17]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP16]] +// +vint8m1x8_t test_th_vlseg8e8ff_v_i8m1x8(const int8_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg8e8ff_v_i8m1x8(base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_th_vlseg8e8ff_v_u8m1x8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.th.vlseg8eff.nxv8i8.i64( poison, poison, poison, poison, poison, poison, poison, poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , , , } [[TMP8]], [[TMP9]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , , , } [[TMP10]], [[TMP11]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = insertvalue { , , , , , , , } [[TMP12]], [[TMP13]], 6 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 7 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = insertvalue { , , , , , , , } [[TMP14]], [[TMP15]], 7 +// CHECK-RV64-NEXT: [[TMP17:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 8 +// CHECK-RV64-NEXT: store i64 [[TMP17]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP16]] +// +vuint8m1x8_t test_th_vlseg8e8ff_v_u8m1x8(const uint8_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg8e8ff_v_u8m1x8(base, new_vl, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg2e16.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg2e16.c new file mode 100644 index 00000000000000..802e96f1c8754e --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg2e16.c @@ -0,0 +1,260 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e16_v_f16m1x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.nxv4f16.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e16_v_f16m1x2(_Float16 *base, vfloat16m1x2_t v_tuple, size_t vl) { + return __riscv_vsseg2e16_v_f16m1x2(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e16_v_f16m2x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.nxv8f16.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e16_v_f16m2x2(_Float16 *base, vfloat16m2x2_t v_tuple, size_t vl) { + return __riscv_vsseg2e16_v_f16m2x2(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e16_v_f16m4x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.nxv16f16.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e16_v_f16m4x2(_Float16 *base, vfloat16m4x2_t v_tuple, size_t vl) { + return __riscv_vsseg2e16_v_f16m4x2(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e16_v_i16m1x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.nxv4i16.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e16_v_i16m1x2(int16_t *base, vint16m1x2_t v_tuple, size_t vl) { + return __riscv_vsseg2e16_v_i16m1x2(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e16_v_i16m2x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.nxv8i16.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e16_v_i16m2x2(int16_t *base, vint16m2x2_t v_tuple, size_t vl) { + return __riscv_vsseg2e16_v_i16m2x2(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e16_v_i16m4x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.nxv16i16.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e16_v_i16m4x2(int16_t *base, vint16m4x2_t v_tuple, size_t vl) { + return __riscv_vsseg2e16_v_i16m4x2(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e16_v_u16m1x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.nxv4i16.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e16_v_u16m1x2(uint16_t *base, vuint16m1x2_t v_tuple, size_t vl) { + return __riscv_vsseg2e16_v_u16m1x2(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e16_v_u16m2x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.nxv8i16.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e16_v_u16m2x2(uint16_t *base, vuint16m2x2_t v_tuple, size_t vl) { + return __riscv_vsseg2e16_v_u16m2x2(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e16_v_u16m4x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.nxv16i16.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e16_v_u16m4x2(uint16_t *base, vuint16m4x2_t v_tuple, size_t vl) { + return __riscv_vsseg2e16_v_u16m4x2(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e16_v_f16m1x2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.mask.nxv4f16.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e16_v_f16m1x2_m(vbool16_t mask, _Float16 *base, vfloat16m1x2_t v_tuple, size_t vl) { + return __riscv_vsseg2e16_v_f16m1x2_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e16_v_f16m2x2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.mask.nxv8f16.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e16_v_f16m2x2_m(vbool8_t mask, _Float16 *base, vfloat16m2x2_t v_tuple, size_t vl) { + return __riscv_vsseg2e16_v_f16m2x2_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e16_v_f16m4x2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.mask.nxv16f16.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e16_v_f16m4x2_m(vbool4_t mask, _Float16 *base, vfloat16m4x2_t v_tuple, size_t vl) { + return __riscv_vsseg2e16_v_f16m4x2_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e16_v_i16m1x2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.mask.nxv4i16.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e16_v_i16m1x2_m(vbool16_t mask, int16_t *base, vint16m1x2_t v_tuple, size_t vl) { + return __riscv_vsseg2e16_v_i16m1x2_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e16_v_i16m2x2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.mask.nxv8i16.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e16_v_i16m2x2_m(vbool8_t mask, int16_t *base, vint16m2x2_t v_tuple, size_t vl) { + return __riscv_vsseg2e16_v_i16m2x2_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e16_v_i16m4x2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.mask.nxv16i16.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e16_v_i16m4x2_m(vbool4_t mask, int16_t *base, vint16m4x2_t v_tuple, size_t vl) { + return __riscv_vsseg2e16_v_i16m4x2_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e16_v_u16m1x2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.mask.nxv4i16.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e16_v_u16m1x2_m(vbool16_t mask, uint16_t *base, vuint16m1x2_t v_tuple, size_t vl) { + return __riscv_vsseg2e16_v_u16m1x2_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e16_v_u16m2x2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.mask.nxv8i16.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e16_v_u16m2x2_m(vbool8_t mask, uint16_t *base, vuint16m2x2_t v_tuple, size_t vl) { + return __riscv_vsseg2e16_v_u16m2x2_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e16_v_u16m4x2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.mask.nxv16i16.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e16_v_u16m4x2_m(vbool4_t mask, uint16_t *base, vuint16m4x2_t v_tuple, size_t vl) { + return __riscv_vsseg2e16_v_u16m4x2_m(mask, base, v_tuple, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg2e32.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg2e32.c new file mode 100644 index 00000000000000..c1a90b7952552e --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg2e32.c @@ -0,0 +1,260 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e32_v_f32m1x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.nxv2f32.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e32_v_f32m1x2(float *base, vfloat32m1x2_t v_tuple, size_t vl) { + return __riscv_vsseg2e32_v_f32m1x2(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e32_v_f32m2x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.nxv4f32.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e32_v_f32m2x2(float *base, vfloat32m2x2_t v_tuple, size_t vl) { + return __riscv_vsseg2e32_v_f32m2x2(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e32_v_f32m4x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.nxv8f32.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e32_v_f32m4x2(float *base, vfloat32m4x2_t v_tuple, size_t vl) { + return __riscv_vsseg2e32_v_f32m4x2(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e32_v_i32m1x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.nxv2i32.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e32_v_i32m1x2(int32_t *base, vint32m1x2_t v_tuple, size_t vl) { + return __riscv_vsseg2e32_v_i32m1x2(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e32_v_i32m2x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.nxv4i32.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e32_v_i32m2x2(int32_t *base, vint32m2x2_t v_tuple, size_t vl) { + return __riscv_vsseg2e32_v_i32m2x2(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e32_v_i32m4x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.nxv8i32.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e32_v_i32m4x2(int32_t *base, vint32m4x2_t v_tuple, size_t vl) { + return __riscv_vsseg2e32_v_i32m4x2(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e32_v_u32m1x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.nxv2i32.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e32_v_u32m1x2(uint32_t *base, vuint32m1x2_t v_tuple, size_t vl) { + return __riscv_vsseg2e32_v_u32m1x2(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e32_v_u32m2x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.nxv4i32.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e32_v_u32m2x2(uint32_t *base, vuint32m2x2_t v_tuple, size_t vl) { + return __riscv_vsseg2e32_v_u32m2x2(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e32_v_u32m4x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.nxv8i32.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e32_v_u32m4x2(uint32_t *base, vuint32m4x2_t v_tuple, size_t vl) { + return __riscv_vsseg2e32_v_u32m4x2(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e32_v_f32m1x2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.mask.nxv2f32.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e32_v_f32m1x2_m(vbool32_t mask, float *base, vfloat32m1x2_t v_tuple, size_t vl) { + return __riscv_vsseg2e32_v_f32m1x2_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e32_v_f32m2x2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.mask.nxv4f32.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e32_v_f32m2x2_m(vbool16_t mask, float *base, vfloat32m2x2_t v_tuple, size_t vl) { + return __riscv_vsseg2e32_v_f32m2x2_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e32_v_f32m4x2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.mask.nxv8f32.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e32_v_f32m4x2_m(vbool8_t mask, float *base, vfloat32m4x2_t v_tuple, size_t vl) { + return __riscv_vsseg2e32_v_f32m4x2_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e32_v_i32m1x2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.mask.nxv2i32.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e32_v_i32m1x2_m(vbool32_t mask, int32_t *base, vint32m1x2_t v_tuple, size_t vl) { + return __riscv_vsseg2e32_v_i32m1x2_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e32_v_i32m2x2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.mask.nxv4i32.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e32_v_i32m2x2_m(vbool16_t mask, int32_t *base, vint32m2x2_t v_tuple, size_t vl) { + return __riscv_vsseg2e32_v_i32m2x2_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e32_v_i32m4x2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.mask.nxv8i32.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e32_v_i32m4x2_m(vbool8_t mask, int32_t *base, vint32m4x2_t v_tuple, size_t vl) { + return __riscv_vsseg2e32_v_i32m4x2_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e32_v_u32m1x2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.mask.nxv2i32.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e32_v_u32m1x2_m(vbool32_t mask, uint32_t *base, vuint32m1x2_t v_tuple, size_t vl) { + return __riscv_vsseg2e32_v_u32m1x2_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e32_v_u32m2x2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.mask.nxv4i32.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e32_v_u32m2x2_m(vbool16_t mask, uint32_t *base, vuint32m2x2_t v_tuple, size_t vl) { + return __riscv_vsseg2e32_v_u32m2x2_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e32_v_u32m4x2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.mask.nxv8i32.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e32_v_u32m4x2_m(vbool8_t mask, uint32_t *base, vuint32m4x2_t v_tuple, size_t vl) { + return __riscv_vsseg2e32_v_u32m4x2_m(mask, base, v_tuple, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg2e64.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg2e64.c new file mode 100644 index 00000000000000..5a9721c573e36a --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg2e64.c @@ -0,0 +1,260 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e64_v_f64m1x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.nxv1f64.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e64_v_f64m1x2(double *base, vfloat64m1x2_t v_tuple, size_t vl) { + return __riscv_vsseg2e64_v_f64m1x2(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e64_v_f64m2x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.nxv2f64.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e64_v_f64m2x2(double *base, vfloat64m2x2_t v_tuple, size_t vl) { + return __riscv_vsseg2e64_v_f64m2x2(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e64_v_f64m4x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.nxv4f64.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e64_v_f64m4x2(double *base, vfloat64m4x2_t v_tuple, size_t vl) { + return __riscv_vsseg2e64_v_f64m4x2(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e64_v_i64m1x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.nxv1i64.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e64_v_i64m1x2(int64_t *base, vint64m1x2_t v_tuple, size_t vl) { + return __riscv_vsseg2e64_v_i64m1x2(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e64_v_i64m2x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.nxv2i64.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e64_v_i64m2x2(int64_t *base, vint64m2x2_t v_tuple, size_t vl) { + return __riscv_vsseg2e64_v_i64m2x2(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e64_v_i64m4x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.nxv4i64.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e64_v_i64m4x2(int64_t *base, vint64m4x2_t v_tuple, size_t vl) { + return __riscv_vsseg2e64_v_i64m4x2(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e64_v_u64m1x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.nxv1i64.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e64_v_u64m1x2(uint64_t *base, vuint64m1x2_t v_tuple, size_t vl) { + return __riscv_vsseg2e64_v_u64m1x2(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e64_v_u64m2x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.nxv2i64.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e64_v_u64m2x2(uint64_t *base, vuint64m2x2_t v_tuple, size_t vl) { + return __riscv_vsseg2e64_v_u64m2x2(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e64_v_u64m4x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.nxv4i64.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e64_v_u64m4x2(uint64_t *base, vuint64m4x2_t v_tuple, size_t vl) { + return __riscv_vsseg2e64_v_u64m4x2(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e64_v_f64m1x2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.mask.nxv1f64.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e64_v_f64m1x2_m(vbool64_t mask, double *base, vfloat64m1x2_t v_tuple, size_t vl) { + return __riscv_vsseg2e64_v_f64m1x2_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e64_v_f64m2x2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.mask.nxv2f64.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e64_v_f64m2x2_m(vbool32_t mask, double *base, vfloat64m2x2_t v_tuple, size_t vl) { + return __riscv_vsseg2e64_v_f64m2x2_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e64_v_f64m4x2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.mask.nxv4f64.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e64_v_f64m4x2_m(vbool16_t mask, double *base, vfloat64m4x2_t v_tuple, size_t vl) { + return __riscv_vsseg2e64_v_f64m4x2_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e64_v_i64m1x2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.mask.nxv1i64.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e64_v_i64m1x2_m(vbool64_t mask, int64_t *base, vint64m1x2_t v_tuple, size_t vl) { + return __riscv_vsseg2e64_v_i64m1x2_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e64_v_i64m2x2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.mask.nxv2i64.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e64_v_i64m2x2_m(vbool32_t mask, int64_t *base, vint64m2x2_t v_tuple, size_t vl) { + return __riscv_vsseg2e64_v_i64m2x2_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e64_v_i64m4x2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.mask.nxv4i64.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e64_v_i64m4x2_m(vbool16_t mask, int64_t *base, vint64m4x2_t v_tuple, size_t vl) { + return __riscv_vsseg2e64_v_i64m4x2_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e64_v_u64m1x2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.mask.nxv1i64.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e64_v_u64m1x2_m(vbool64_t mask, uint64_t *base, vuint64m1x2_t v_tuple, size_t vl) { + return __riscv_vsseg2e64_v_u64m1x2_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e64_v_u64m2x2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.mask.nxv2i64.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e64_v_u64m2x2_m(vbool32_t mask, uint64_t *base, vuint64m2x2_t v_tuple, size_t vl) { + return __riscv_vsseg2e64_v_u64m2x2_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e64_v_u64m4x2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.mask.nxv4i64.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e64_v_u64m4x2_m(vbool16_t mask, uint64_t *base, vuint64m4x2_t v_tuple, size_t vl) { + return __riscv_vsseg2e64_v_u64m4x2_m(mask, base, v_tuple, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg2e8.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg2e8.c new file mode 100644 index 00000000000000..8788f4e06dd03b --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg2e8.c @@ -0,0 +1,176 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e8_v_i8m1x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.nxv8i8.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e8_v_i8m1x2(int8_t *base, vint8m1x2_t v_tuple, size_t vl) { + return __riscv_vsseg2e8_v_i8m1x2(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e8_v_i8m2x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.nxv16i8.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e8_v_i8m2x2(int8_t *base, vint8m2x2_t v_tuple, size_t vl) { + return __riscv_vsseg2e8_v_i8m2x2(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e8_v_i8m4x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.nxv32i8.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e8_v_i8m4x2(int8_t *base, vint8m4x2_t v_tuple, size_t vl) { + return __riscv_vsseg2e8_v_i8m4x2(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e8_v_u8m1x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.nxv8i8.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e8_v_u8m1x2(uint8_t *base, vuint8m1x2_t v_tuple, size_t vl) { + return __riscv_vsseg2e8_v_u8m1x2(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e8_v_u8m2x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.nxv16i8.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e8_v_u8m2x2(uint8_t *base, vuint8m2x2_t v_tuple, size_t vl) { + return __riscv_vsseg2e8_v_u8m2x2(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e8_v_u8m4x2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.nxv32i8.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e8_v_u8m4x2(uint8_t *base, vuint8m4x2_t v_tuple, size_t vl) { + return __riscv_vsseg2e8_v_u8m4x2(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e8_v_i8m1x2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.mask.nxv8i8.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e8_v_i8m1x2_m(vbool8_t mask, int8_t *base, vint8m1x2_t v_tuple, size_t vl) { + return __riscv_vsseg2e8_v_i8m1x2_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e8_v_i8m2x2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.mask.nxv16i8.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e8_v_i8m2x2_m(vbool4_t mask, int8_t *base, vint8m2x2_t v_tuple, size_t vl) { + return __riscv_vsseg2e8_v_i8m2x2_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e8_v_i8m4x2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.mask.nxv32i8.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e8_v_i8m4x2_m(vbool2_t mask, int8_t *base, vint8m4x2_t v_tuple, size_t vl) { + return __riscv_vsseg2e8_v_i8m4x2_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e8_v_u8m1x2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.mask.nxv8i8.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e8_v_u8m1x2_m(vbool8_t mask, uint8_t *base, vuint8m1x2_t v_tuple, size_t vl) { + return __riscv_vsseg2e8_v_u8m1x2_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e8_v_u8m2x2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.mask.nxv16i8.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e8_v_u8m2x2_m(vbool4_t mask, uint8_t *base, vuint8m2x2_t v_tuple, size_t vl) { + return __riscv_vsseg2e8_v_u8m2x2_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg2e8_v_u8m4x2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP1]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg2e.mask.nxv32i8.i64( [[TMP2]], [[TMP3]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg2e8_v_u8m4x2_m(vbool2_t mask, uint8_t *base, vuint8m4x2_t v_tuple, size_t vl) { + return __riscv_vsseg2e8_v_u8m4x2_m(mask, base, v_tuple, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg3e16.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg3e16.c new file mode 100644 index 00000000000000..5509b4eaec2063 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg3e16.c @@ -0,0 +1,200 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg3e16_v_f16m1x3 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , } [[TMP2]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg3e.nxv4f16.i64( [[TMP3]], [[TMP4]], [[TMP5]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg3e16_v_f16m1x3(_Float16 *base, vfloat16m1x3_t v_tuple, size_t vl) { + return __riscv_vsseg3e16_v_f16m1x3(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg3e16_v_f16m2x3 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , } [[TMP2]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg3e.nxv8f16.i64( [[TMP3]], [[TMP4]], [[TMP5]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg3e16_v_f16m2x3(_Float16 *base, vfloat16m2x3_t v_tuple, size_t vl) { + return __riscv_vsseg3e16_v_f16m2x3(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg3e16_v_i16m1x3 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , } [[TMP2]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg3e.nxv4i16.i64( [[TMP3]], [[TMP4]], [[TMP5]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg3e16_v_i16m1x3(int16_t *base, vint16m1x3_t v_tuple, size_t vl) { + return __riscv_vsseg3e16_v_i16m1x3(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg3e16_v_i16m2x3 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , } [[TMP2]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg3e.nxv8i16.i64( [[TMP3]], [[TMP4]], [[TMP5]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg3e16_v_i16m2x3(int16_t *base, vint16m2x3_t v_tuple, size_t vl) { + return __riscv_vsseg3e16_v_i16m2x3(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg3e16_v_u16m1x3 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , } [[TMP2]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg3e.nxv4i16.i64( [[TMP3]], [[TMP4]], [[TMP5]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg3e16_v_u16m1x3(uint16_t *base, vuint16m1x3_t v_tuple, size_t vl) { + return __riscv_vsseg3e16_v_u16m1x3(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg3e16_v_u16m2x3 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , } [[TMP2]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg3e.nxv8i16.i64( [[TMP3]], [[TMP4]], [[TMP5]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg3e16_v_u16m2x3(uint16_t *base, vuint16m2x3_t v_tuple, size_t vl) { + return __riscv_vsseg3e16_v_u16m2x3(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg3e16_v_f16m1x3_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , } [[TMP2]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg3e.mask.nxv4f16.i64( [[TMP3]], [[TMP4]], [[TMP5]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg3e16_v_f16m1x3_m(vbool16_t mask, _Float16 *base, vfloat16m1x3_t v_tuple, size_t vl) { + return __riscv_vsseg3e16_v_f16m1x3_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg3e16_v_f16m2x3_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , } [[TMP2]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg3e.mask.nxv8f16.i64( [[TMP3]], [[TMP4]], [[TMP5]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg3e16_v_f16m2x3_m(vbool8_t mask, _Float16 *base, vfloat16m2x3_t v_tuple, size_t vl) { + return __riscv_vsseg3e16_v_f16m2x3_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg3e16_v_i16m1x3_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , } [[TMP2]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg3e.mask.nxv4i16.i64( [[TMP3]], [[TMP4]], [[TMP5]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg3e16_v_i16m1x3_m(vbool16_t mask, int16_t *base, vint16m1x3_t v_tuple, size_t vl) { + return __riscv_vsseg3e16_v_i16m1x3_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg3e16_v_i16m2x3_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , } [[TMP2]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg3e.mask.nxv8i16.i64( [[TMP3]], [[TMP4]], [[TMP5]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg3e16_v_i16m2x3_m(vbool8_t mask, int16_t *base, vint16m2x3_t v_tuple, size_t vl) { + return __riscv_vsseg3e16_v_i16m2x3_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg3e16_v_u16m1x3_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , } [[TMP2]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg3e.mask.nxv4i16.i64( [[TMP3]], [[TMP4]], [[TMP5]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg3e16_v_u16m1x3_m(vbool16_t mask, uint16_t *base, vuint16m1x3_t v_tuple, size_t vl) { + return __riscv_vsseg3e16_v_u16m1x3_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg3e16_v_u16m2x3_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , } [[TMP2]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg3e.mask.nxv8i16.i64( [[TMP3]], [[TMP4]], [[TMP5]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg3e16_v_u16m2x3_m(vbool8_t mask, uint16_t *base, vuint16m2x3_t v_tuple, size_t vl) { + return __riscv_vsseg3e16_v_u16m2x3_m(mask, base, v_tuple, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg3e32.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg3e32.c new file mode 100644 index 00000000000000..3fa1656680888d --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg3e32.c @@ -0,0 +1,200 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg3e32_v_f32m1x3 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , } [[TMP2]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg3e.nxv2f32.i64( [[TMP3]], [[TMP4]], [[TMP5]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg3e32_v_f32m1x3(float *base, vfloat32m1x3_t v_tuple, size_t vl) { + return __riscv_vsseg3e32_v_f32m1x3(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg3e32_v_f32m2x3 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , } [[TMP2]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg3e.nxv4f32.i64( [[TMP3]], [[TMP4]], [[TMP5]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg3e32_v_f32m2x3(float *base, vfloat32m2x3_t v_tuple, size_t vl) { + return __riscv_vsseg3e32_v_f32m2x3(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg3e32_v_i32m1x3 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , } [[TMP2]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg3e.nxv2i32.i64( [[TMP3]], [[TMP4]], [[TMP5]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg3e32_v_i32m1x3(int32_t *base, vint32m1x3_t v_tuple, size_t vl) { + return __riscv_vsseg3e32_v_i32m1x3(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg3e32_v_i32m2x3 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , } [[TMP2]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg3e.nxv4i32.i64( [[TMP3]], [[TMP4]], [[TMP5]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg3e32_v_i32m2x3(int32_t *base, vint32m2x3_t v_tuple, size_t vl) { + return __riscv_vsseg3e32_v_i32m2x3(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg3e32_v_u32m1x3 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , } [[TMP2]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg3e.nxv2i32.i64( [[TMP3]], [[TMP4]], [[TMP5]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg3e32_v_u32m1x3(uint32_t *base, vuint32m1x3_t v_tuple, size_t vl) { + return __riscv_vsseg3e32_v_u32m1x3(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg3e32_v_u32m2x3 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , } [[TMP2]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg3e.nxv4i32.i64( [[TMP3]], [[TMP4]], [[TMP5]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg3e32_v_u32m2x3(uint32_t *base, vuint32m2x3_t v_tuple, size_t vl) { + return __riscv_vsseg3e32_v_u32m2x3(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg3e32_v_f32m1x3_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , } [[TMP2]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg3e.mask.nxv2f32.i64( [[TMP3]], [[TMP4]], [[TMP5]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg3e32_v_f32m1x3_m(vbool32_t mask, float *base, vfloat32m1x3_t v_tuple, size_t vl) { + return __riscv_vsseg3e32_v_f32m1x3_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg3e32_v_f32m2x3_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , } [[TMP2]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg3e.mask.nxv4f32.i64( [[TMP3]], [[TMP4]], [[TMP5]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg3e32_v_f32m2x3_m(vbool16_t mask, float *base, vfloat32m2x3_t v_tuple, size_t vl) { + return __riscv_vsseg3e32_v_f32m2x3_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg3e32_v_i32m1x3_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , } [[TMP2]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg3e.mask.nxv2i32.i64( [[TMP3]], [[TMP4]], [[TMP5]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg3e32_v_i32m1x3_m(vbool32_t mask, int32_t *base, vint32m1x3_t v_tuple, size_t vl) { + return __riscv_vsseg3e32_v_i32m1x3_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg3e32_v_i32m2x3_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , } [[TMP2]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg3e.mask.nxv4i32.i64( [[TMP3]], [[TMP4]], [[TMP5]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg3e32_v_i32m2x3_m(vbool16_t mask, int32_t *base, vint32m2x3_t v_tuple, size_t vl) { + return __riscv_vsseg3e32_v_i32m2x3_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg3e32_v_u32m1x3_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , } [[TMP2]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg3e.mask.nxv2i32.i64( [[TMP3]], [[TMP4]], [[TMP5]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg3e32_v_u32m1x3_m(vbool32_t mask, uint32_t *base, vuint32m1x3_t v_tuple, size_t vl) { + return __riscv_vsseg3e32_v_u32m1x3_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg3e32_v_u32m2x3_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , } [[TMP2]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg3e.mask.nxv4i32.i64( [[TMP3]], [[TMP4]], [[TMP5]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg3e32_v_u32m2x3_m(vbool16_t mask, uint32_t *base, vuint32m2x3_t v_tuple, size_t vl) { + return __riscv_vsseg3e32_v_u32m2x3_m(mask, base, v_tuple, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg3e64.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg3e64.c new file mode 100644 index 00000000000000..b2f676918387d1 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg3e64.c @@ -0,0 +1,200 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg3e64_v_f64m1x3 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , } [[TMP2]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg3e.nxv1f64.i64( [[TMP3]], [[TMP4]], [[TMP5]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg3e64_v_f64m1x3(double *base, vfloat64m1x3_t v_tuple, size_t vl) { + return __riscv_vsseg3e64_v_f64m1x3(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg3e64_v_f64m2x3 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , } [[TMP2]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg3e.nxv2f64.i64( [[TMP3]], [[TMP4]], [[TMP5]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg3e64_v_f64m2x3(double *base, vfloat64m2x3_t v_tuple, size_t vl) { + return __riscv_vsseg3e64_v_f64m2x3(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg3e64_v_i64m1x3 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , } [[TMP2]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg3e.nxv1i64.i64( [[TMP3]], [[TMP4]], [[TMP5]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg3e64_v_i64m1x3(int64_t *base, vint64m1x3_t v_tuple, size_t vl) { + return __riscv_vsseg3e64_v_i64m1x3(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg3e64_v_i64m2x3 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , } [[TMP2]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg3e.nxv2i64.i64( [[TMP3]], [[TMP4]], [[TMP5]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg3e64_v_i64m2x3(int64_t *base, vint64m2x3_t v_tuple, size_t vl) { + return __riscv_vsseg3e64_v_i64m2x3(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg3e64_v_u64m1x3 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , } [[TMP2]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg3e.nxv1i64.i64( [[TMP3]], [[TMP4]], [[TMP5]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg3e64_v_u64m1x3(uint64_t *base, vuint64m1x3_t v_tuple, size_t vl) { + return __riscv_vsseg3e64_v_u64m1x3(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg3e64_v_u64m2x3 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , } [[TMP2]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg3e.nxv2i64.i64( [[TMP3]], [[TMP4]], [[TMP5]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg3e64_v_u64m2x3(uint64_t *base, vuint64m2x3_t v_tuple, size_t vl) { + return __riscv_vsseg3e64_v_u64m2x3(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg3e64_v_f64m1x3_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , } [[TMP2]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg3e.mask.nxv1f64.i64( [[TMP3]], [[TMP4]], [[TMP5]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg3e64_v_f64m1x3_m(vbool64_t mask, double *base, vfloat64m1x3_t v_tuple, size_t vl) { + return __riscv_vsseg3e64_v_f64m1x3_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg3e64_v_f64m2x3_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , } [[TMP2]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg3e.mask.nxv2f64.i64( [[TMP3]], [[TMP4]], [[TMP5]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg3e64_v_f64m2x3_m(vbool32_t mask, double *base, vfloat64m2x3_t v_tuple, size_t vl) { + return __riscv_vsseg3e64_v_f64m2x3_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg3e64_v_i64m1x3_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , } [[TMP2]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg3e.mask.nxv1i64.i64( [[TMP3]], [[TMP4]], [[TMP5]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg3e64_v_i64m1x3_m(vbool64_t mask, int64_t *base, vint64m1x3_t v_tuple, size_t vl) { + return __riscv_vsseg3e64_v_i64m1x3_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg3e64_v_i64m2x3_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , } [[TMP2]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg3e.mask.nxv2i64.i64( [[TMP3]], [[TMP4]], [[TMP5]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg3e64_v_i64m2x3_m(vbool32_t mask, int64_t *base, vint64m2x3_t v_tuple, size_t vl) { + return __riscv_vsseg3e64_v_i64m2x3_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg3e64_v_u64m1x3_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , } [[TMP2]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg3e.mask.nxv1i64.i64( [[TMP3]], [[TMP4]], [[TMP5]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg3e64_v_u64m1x3_m(vbool64_t mask, uint64_t *base, vuint64m1x3_t v_tuple, size_t vl) { + return __riscv_vsseg3e64_v_u64m1x3_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg3e64_v_u64m2x3_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , } [[TMP2]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg3e.mask.nxv2i64.i64( [[TMP3]], [[TMP4]], [[TMP5]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg3e64_v_u64m2x3_m(vbool32_t mask, uint64_t *base, vuint64m2x3_t v_tuple, size_t vl) { + return __riscv_vsseg3e64_v_u64m2x3_m(mask, base, v_tuple, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg3e8.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg3e8.c new file mode 100644 index 00000000000000..266e385be71cef --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg3e8.c @@ -0,0 +1,136 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg3e8_v_i8m1x3 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , } [[TMP2]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg3e.nxv8i8.i64( [[TMP3]], [[TMP4]], [[TMP5]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg3e8_v_i8m1x3(int8_t *base, vint8m1x3_t v_tuple, size_t vl) { + return __riscv_vsseg3e8_v_i8m1x3(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg3e8_v_i8m2x3 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , } [[TMP2]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg3e.nxv16i8.i64( [[TMP3]], [[TMP4]], [[TMP5]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg3e8_v_i8m2x3(int8_t *base, vint8m2x3_t v_tuple, size_t vl) { + return __riscv_vsseg3e8_v_i8m2x3(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg3e8_v_u8m1x3 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , } [[TMP2]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg3e.nxv8i8.i64( [[TMP3]], [[TMP4]], [[TMP5]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg3e8_v_u8m1x3(uint8_t *base, vuint8m1x3_t v_tuple, size_t vl) { + return __riscv_vsseg3e8_v_u8m1x3(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg3e8_v_u8m2x3 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , } [[TMP2]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg3e.nxv16i8.i64( [[TMP3]], [[TMP4]], [[TMP5]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg3e8_v_u8m2x3(uint8_t *base, vuint8m2x3_t v_tuple, size_t vl) { + return __riscv_vsseg3e8_v_u8m2x3(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg3e8_v_i8m1x3_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , } [[TMP2]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg3e.mask.nxv8i8.i64( [[TMP3]], [[TMP4]], [[TMP5]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg3e8_v_i8m1x3_m(vbool8_t mask, int8_t *base, vint8m1x3_t v_tuple, size_t vl) { + return __riscv_vsseg3e8_v_i8m1x3_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg3e8_v_i8m2x3_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , } [[TMP2]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg3e.mask.nxv16i8.i64( [[TMP3]], [[TMP4]], [[TMP5]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg3e8_v_i8m2x3_m(vbool4_t mask, int8_t *base, vint8m2x3_t v_tuple, size_t vl) { + return __riscv_vsseg3e8_v_i8m2x3_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg3e8_v_u8m1x3_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , } [[TMP2]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg3e.mask.nxv8i8.i64( [[TMP3]], [[TMP4]], [[TMP5]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg3e8_v_u8m1x3_m(vbool8_t mask, uint8_t *base, vuint8m1x3_t v_tuple, size_t vl) { + return __riscv_vsseg3e8_v_u8m1x3_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg3e8_v_u8m2x3_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , } [[TMP2]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg3e.mask.nxv16i8.i64( [[TMP3]], [[TMP4]], [[TMP5]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg3e8_v_u8m2x3_m(vbool4_t mask, uint8_t *base, vuint8m2x3_t v_tuple, size_t vl) { + return __riscv_vsseg3e8_v_u8m2x3_m(mask, base, v_tuple, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg4e16.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg4e16.c new file mode 100644 index 00000000000000..80c2eac6cef54c --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg4e16.c @@ -0,0 +1,224 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg4e16_v_f16m1x4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg4e.nxv4f16.i64( [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg4e16_v_f16m1x4(_Float16 *base, vfloat16m1x4_t v_tuple, size_t vl) { + return __riscv_vsseg4e16_v_f16m1x4(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg4e16_v_f16m2x4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg4e.nxv8f16.i64( [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg4e16_v_f16m2x4(_Float16 *base, vfloat16m2x4_t v_tuple, size_t vl) { + return __riscv_vsseg4e16_v_f16m2x4(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg4e16_v_i16m1x4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg4e.nxv4i16.i64( [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg4e16_v_i16m1x4(int16_t *base, vint16m1x4_t v_tuple, size_t vl) { + return __riscv_vsseg4e16_v_i16m1x4(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg4e16_v_i16m2x4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg4e.nxv8i16.i64( [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg4e16_v_i16m2x4(int16_t *base, vint16m2x4_t v_tuple, size_t vl) { + return __riscv_vsseg4e16_v_i16m2x4(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg4e16_v_u16m1x4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg4e.nxv4i16.i64( [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg4e16_v_u16m1x4(uint16_t *base, vuint16m1x4_t v_tuple, size_t vl) { + return __riscv_vsseg4e16_v_u16m1x4(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg4e16_v_u16m2x4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg4e.nxv8i16.i64( [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg4e16_v_u16m2x4(uint16_t *base, vuint16m2x4_t v_tuple, size_t vl) { + return __riscv_vsseg4e16_v_u16m2x4(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg4e16_v_f16m1x4_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg4e.mask.nxv4f16.i64( [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg4e16_v_f16m1x4_m(vbool16_t mask, _Float16 *base, vfloat16m1x4_t v_tuple, size_t vl) { + return __riscv_vsseg4e16_v_f16m1x4_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg4e16_v_f16m2x4_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg4e.mask.nxv8f16.i64( [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg4e16_v_f16m2x4_m(vbool8_t mask, _Float16 *base, vfloat16m2x4_t v_tuple, size_t vl) { + return __riscv_vsseg4e16_v_f16m2x4_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg4e16_v_i16m1x4_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg4e.mask.nxv4i16.i64( [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg4e16_v_i16m1x4_m(vbool16_t mask, int16_t *base, vint16m1x4_t v_tuple, size_t vl) { + return __riscv_vsseg4e16_v_i16m1x4_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg4e16_v_i16m2x4_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg4e.mask.nxv8i16.i64( [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg4e16_v_i16m2x4_m(vbool8_t mask, int16_t *base, vint16m2x4_t v_tuple, size_t vl) { + return __riscv_vsseg4e16_v_i16m2x4_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg4e16_v_u16m1x4_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg4e.mask.nxv4i16.i64( [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg4e16_v_u16m1x4_m(vbool16_t mask, uint16_t *base, vuint16m1x4_t v_tuple, size_t vl) { + return __riscv_vsseg4e16_v_u16m1x4_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg4e16_v_u16m2x4_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg4e.mask.nxv8i16.i64( [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg4e16_v_u16m2x4_m(vbool8_t mask, uint16_t *base, vuint16m2x4_t v_tuple, size_t vl) { + return __riscv_vsseg4e16_v_u16m2x4_m(mask, base, v_tuple, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg4e32.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg4e32.c new file mode 100644 index 00000000000000..5fcf09a0233c73 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg4e32.c @@ -0,0 +1,224 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg4e32_v_f32m1x4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg4e.nxv2f32.i64( [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg4e32_v_f32m1x4(float *base, vfloat32m1x4_t v_tuple, size_t vl) { + return __riscv_vsseg4e32_v_f32m1x4(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg4e32_v_f32m2x4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg4e.nxv4f32.i64( [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg4e32_v_f32m2x4(float *base, vfloat32m2x4_t v_tuple, size_t vl) { + return __riscv_vsseg4e32_v_f32m2x4(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg4e32_v_i32m1x4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg4e.nxv2i32.i64( [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg4e32_v_i32m1x4(int32_t *base, vint32m1x4_t v_tuple, size_t vl) { + return __riscv_vsseg4e32_v_i32m1x4(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg4e32_v_i32m2x4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg4e.nxv4i32.i64( [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg4e32_v_i32m2x4(int32_t *base, vint32m2x4_t v_tuple, size_t vl) { + return __riscv_vsseg4e32_v_i32m2x4(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg4e32_v_u32m1x4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg4e.nxv2i32.i64( [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg4e32_v_u32m1x4(uint32_t *base, vuint32m1x4_t v_tuple, size_t vl) { + return __riscv_vsseg4e32_v_u32m1x4(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg4e32_v_u32m2x4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg4e.nxv4i32.i64( [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg4e32_v_u32m2x4(uint32_t *base, vuint32m2x4_t v_tuple, size_t vl) { + return __riscv_vsseg4e32_v_u32m2x4(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg4e32_v_f32m1x4_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg4e.mask.nxv2f32.i64( [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg4e32_v_f32m1x4_m(vbool32_t mask, float *base, vfloat32m1x4_t v_tuple, size_t vl) { + return __riscv_vsseg4e32_v_f32m1x4_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg4e32_v_f32m2x4_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg4e.mask.nxv4f32.i64( [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg4e32_v_f32m2x4_m(vbool16_t mask, float *base, vfloat32m2x4_t v_tuple, size_t vl) { + return __riscv_vsseg4e32_v_f32m2x4_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg4e32_v_i32m1x4_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg4e.mask.nxv2i32.i64( [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg4e32_v_i32m1x4_m(vbool32_t mask, int32_t *base, vint32m1x4_t v_tuple, size_t vl) { + return __riscv_vsseg4e32_v_i32m1x4_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg4e32_v_i32m2x4_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg4e.mask.nxv4i32.i64( [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg4e32_v_i32m2x4_m(vbool16_t mask, int32_t *base, vint32m2x4_t v_tuple, size_t vl) { + return __riscv_vsseg4e32_v_i32m2x4_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg4e32_v_u32m1x4_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg4e.mask.nxv2i32.i64( [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg4e32_v_u32m1x4_m(vbool32_t mask, uint32_t *base, vuint32m1x4_t v_tuple, size_t vl) { + return __riscv_vsseg4e32_v_u32m1x4_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg4e32_v_u32m2x4_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg4e.mask.nxv4i32.i64( [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg4e32_v_u32m2x4_m(vbool16_t mask, uint32_t *base, vuint32m2x4_t v_tuple, size_t vl) { + return __riscv_vsseg4e32_v_u32m2x4_m(mask, base, v_tuple, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg4e64.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg4e64.c new file mode 100644 index 00000000000000..bd780e75d97333 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg4e64.c @@ -0,0 +1,224 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg4e64_v_f64m1x4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg4e.nxv1f64.i64( [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg4e64_v_f64m1x4(double *base, vfloat64m1x4_t v_tuple, size_t vl) { + return __riscv_vsseg4e64_v_f64m1x4(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg4e64_v_f64m2x4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg4e.nxv2f64.i64( [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg4e64_v_f64m2x4(double *base, vfloat64m2x4_t v_tuple, size_t vl) { + return __riscv_vsseg4e64_v_f64m2x4(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg4e64_v_i64m1x4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg4e.nxv1i64.i64( [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg4e64_v_i64m1x4(int64_t *base, vint64m1x4_t v_tuple, size_t vl) { + return __riscv_vsseg4e64_v_i64m1x4(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg4e64_v_i64m2x4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg4e.nxv2i64.i64( [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg4e64_v_i64m2x4(int64_t *base, vint64m2x4_t v_tuple, size_t vl) { + return __riscv_vsseg4e64_v_i64m2x4(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg4e64_v_u64m1x4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg4e.nxv1i64.i64( [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg4e64_v_u64m1x4(uint64_t *base, vuint64m1x4_t v_tuple, size_t vl) { + return __riscv_vsseg4e64_v_u64m1x4(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg4e64_v_u64m2x4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg4e.nxv2i64.i64( [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg4e64_v_u64m2x4(uint64_t *base, vuint64m2x4_t v_tuple, size_t vl) { + return __riscv_vsseg4e64_v_u64m2x4(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg4e64_v_f64m1x4_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg4e.mask.nxv1f64.i64( [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg4e64_v_f64m1x4_m(vbool64_t mask, double *base, vfloat64m1x4_t v_tuple, size_t vl) { + return __riscv_vsseg4e64_v_f64m1x4_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg4e64_v_f64m2x4_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg4e.mask.nxv2f64.i64( [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg4e64_v_f64m2x4_m(vbool32_t mask, double *base, vfloat64m2x4_t v_tuple, size_t vl) { + return __riscv_vsseg4e64_v_f64m2x4_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg4e64_v_i64m1x4_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg4e.mask.nxv1i64.i64( [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg4e64_v_i64m1x4_m(vbool64_t mask, int64_t *base, vint64m1x4_t v_tuple, size_t vl) { + return __riscv_vsseg4e64_v_i64m1x4_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg4e64_v_i64m2x4_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg4e.mask.nxv2i64.i64( [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg4e64_v_i64m2x4_m(vbool32_t mask, int64_t *base, vint64m2x4_t v_tuple, size_t vl) { + return __riscv_vsseg4e64_v_i64m2x4_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg4e64_v_u64m1x4_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg4e.mask.nxv1i64.i64( [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg4e64_v_u64m1x4_m(vbool64_t mask, uint64_t *base, vuint64m1x4_t v_tuple, size_t vl) { + return __riscv_vsseg4e64_v_u64m1x4_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg4e64_v_u64m2x4_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg4e.mask.nxv2i64.i64( [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg4e64_v_u64m2x4_m(vbool32_t mask, uint64_t *base, vuint64m2x4_t v_tuple, size_t vl) { + return __riscv_vsseg4e64_v_u64m2x4_m(mask, base, v_tuple, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg4e8.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg4e8.c new file mode 100644 index 00000000000000..b8f4b3ef62b2dd --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg4e8.c @@ -0,0 +1,152 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg4e8_v_i8m1x4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg4e.nxv8i8.i64( [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg4e8_v_i8m1x4(int8_t *base, vint8m1x4_t v_tuple, size_t vl) { + return __riscv_vsseg4e8_v_i8m1x4(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg4e8_v_i8m2x4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg4e.nxv16i8.i64( [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg4e8_v_i8m2x4(int8_t *base, vint8m2x4_t v_tuple, size_t vl) { + return __riscv_vsseg4e8_v_i8m2x4(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg4e8_v_u8m1x4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg4e.nxv8i8.i64( [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg4e8_v_u8m1x4(uint8_t *base, vuint8m1x4_t v_tuple, size_t vl) { + return __riscv_vsseg4e8_v_u8m1x4(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg4e8_v_u8m2x4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg4e.nxv16i8.i64( [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg4e8_v_u8m2x4(uint8_t *base, vuint8m2x4_t v_tuple, size_t vl) { + return __riscv_vsseg4e8_v_u8m2x4(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg4e8_v_i8m1x4_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg4e.mask.nxv8i8.i64( [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg4e8_v_i8m1x4_m(vbool8_t mask, int8_t *base, vint8m1x4_t v_tuple, size_t vl) { + return __riscv_vsseg4e8_v_i8m1x4_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg4e8_v_i8m2x4_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg4e.mask.nxv16i8.i64( [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg4e8_v_i8m2x4_m(vbool4_t mask, int8_t *base, vint8m2x4_t v_tuple, size_t vl) { + return __riscv_vsseg4e8_v_i8m2x4_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg4e8_v_u8m1x4_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg4e.mask.nxv8i8.i64( [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg4e8_v_u8m1x4_m(vbool8_t mask, uint8_t *base, vuint8m1x4_t v_tuple, size_t vl) { + return __riscv_vsseg4e8_v_u8m1x4_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg4e8_v_u8m2x4_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg4e.mask.nxv16i8.i64( [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg4e8_v_u8m2x4_m(vbool4_t mask, uint8_t *base, vuint8m2x4_t v_tuple, size_t vl) { + return __riscv_vsseg4e8_v_u8m2x4_m(mask, base, v_tuple, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg5e16.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg5e16.c new file mode 100644 index 00000000000000..9a33cb1a86c7de --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg5e16.c @@ -0,0 +1,128 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg5e16_v_f16m1x5 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , } [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , } [[TMP4]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , } [[TMP4]], 2 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , } [[TMP4]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , } [[TMP4]], 4 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg5e.nxv4f16.i64( [[TMP5]], [[TMP6]], [[TMP7]], [[TMP8]], [[TMP9]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg5e16_v_f16m1x5(_Float16 *base, vfloat16m1x5_t v_tuple, size_t vl) { + return __riscv_vsseg5e16_v_f16m1x5(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg5e16_v_i16m1x5 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , } [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , } [[TMP4]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , } [[TMP4]], 2 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , } [[TMP4]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , } [[TMP4]], 4 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg5e.nxv4i16.i64( [[TMP5]], [[TMP6]], [[TMP7]], [[TMP8]], [[TMP9]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg5e16_v_i16m1x5(int16_t *base, vint16m1x5_t v_tuple, size_t vl) { + return __riscv_vsseg5e16_v_i16m1x5(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg5e16_v_u16m1x5 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , } [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , } [[TMP4]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , } [[TMP4]], 2 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , } [[TMP4]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , } [[TMP4]], 4 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg5e.nxv4i16.i64( [[TMP5]], [[TMP6]], [[TMP7]], [[TMP8]], [[TMP9]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg5e16_v_u16m1x5(uint16_t *base, vuint16m1x5_t v_tuple, size_t vl) { + return __riscv_vsseg5e16_v_u16m1x5(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg5e16_v_f16m1x5_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , } [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , } [[TMP4]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , } [[TMP4]], 2 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , } [[TMP4]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , } [[TMP4]], 4 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg5e.mask.nxv4f16.i64( [[TMP5]], [[TMP6]], [[TMP7]], [[TMP8]], [[TMP9]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg5e16_v_f16m1x5_m(vbool16_t mask, _Float16 *base, vfloat16m1x5_t v_tuple, size_t vl) { + return __riscv_vsseg5e16_v_f16m1x5_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg5e16_v_i16m1x5_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , } [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , } [[TMP4]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , } [[TMP4]], 2 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , } [[TMP4]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , } [[TMP4]], 4 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg5e.mask.nxv4i16.i64( [[TMP5]], [[TMP6]], [[TMP7]], [[TMP8]], [[TMP9]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg5e16_v_i16m1x5_m(vbool16_t mask, int16_t *base, vint16m1x5_t v_tuple, size_t vl) { + return __riscv_vsseg5e16_v_i16m1x5_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg5e16_v_u16m1x5_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , } [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , } [[TMP4]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , } [[TMP4]], 2 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , } [[TMP4]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , } [[TMP4]], 4 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg5e.mask.nxv4i16.i64( [[TMP5]], [[TMP6]], [[TMP7]], [[TMP8]], [[TMP9]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg5e16_v_u16m1x5_m(vbool16_t mask, uint16_t *base, vuint16m1x5_t v_tuple, size_t vl) { + return __riscv_vsseg5e16_v_u16m1x5_m(mask, base, v_tuple, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg5e32.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg5e32.c new file mode 100644 index 00000000000000..53a18b667d444a --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg5e32.c @@ -0,0 +1,128 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg5e32_v_f32m1x5 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , } [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , } [[TMP4]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , } [[TMP4]], 2 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , } [[TMP4]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , } [[TMP4]], 4 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg5e.nxv2f32.i64( [[TMP5]], [[TMP6]], [[TMP7]], [[TMP8]], [[TMP9]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg5e32_v_f32m1x5(float *base, vfloat32m1x5_t v_tuple, size_t vl) { + return __riscv_vsseg5e32_v_f32m1x5(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg5e32_v_i32m1x5 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , } [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , } [[TMP4]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , } [[TMP4]], 2 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , } [[TMP4]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , } [[TMP4]], 4 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg5e.nxv2i32.i64( [[TMP5]], [[TMP6]], [[TMP7]], [[TMP8]], [[TMP9]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg5e32_v_i32m1x5(int32_t *base, vint32m1x5_t v_tuple, size_t vl) { + return __riscv_vsseg5e32_v_i32m1x5(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg5e32_v_u32m1x5 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , } [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , } [[TMP4]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , } [[TMP4]], 2 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , } [[TMP4]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , } [[TMP4]], 4 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg5e.nxv2i32.i64( [[TMP5]], [[TMP6]], [[TMP7]], [[TMP8]], [[TMP9]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg5e32_v_u32m1x5(uint32_t *base, vuint32m1x5_t v_tuple, size_t vl) { + return __riscv_vsseg5e32_v_u32m1x5(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg5e32_v_f32m1x5_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , } [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , } [[TMP4]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , } [[TMP4]], 2 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , } [[TMP4]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , } [[TMP4]], 4 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg5e.mask.nxv2f32.i64( [[TMP5]], [[TMP6]], [[TMP7]], [[TMP8]], [[TMP9]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg5e32_v_f32m1x5_m(vbool32_t mask, float *base, vfloat32m1x5_t v_tuple, size_t vl) { + return __riscv_vsseg5e32_v_f32m1x5_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg5e32_v_i32m1x5_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , } [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , } [[TMP4]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , } [[TMP4]], 2 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , } [[TMP4]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , } [[TMP4]], 4 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg5e.mask.nxv2i32.i64( [[TMP5]], [[TMP6]], [[TMP7]], [[TMP8]], [[TMP9]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg5e32_v_i32m1x5_m(vbool32_t mask, int32_t *base, vint32m1x5_t v_tuple, size_t vl) { + return __riscv_vsseg5e32_v_i32m1x5_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg5e32_v_u32m1x5_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , } [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , } [[TMP4]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , } [[TMP4]], 2 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , } [[TMP4]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , } [[TMP4]], 4 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg5e.mask.nxv2i32.i64( [[TMP5]], [[TMP6]], [[TMP7]], [[TMP8]], [[TMP9]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg5e32_v_u32m1x5_m(vbool32_t mask, uint32_t *base, vuint32m1x5_t v_tuple, size_t vl) { + return __riscv_vsseg5e32_v_u32m1x5_m(mask, base, v_tuple, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg5e64.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg5e64.c new file mode 100644 index 00000000000000..e0edcfd61e261a --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg5e64.c @@ -0,0 +1,128 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg5e64_v_f64m1x5 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , } [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , } [[TMP4]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , } [[TMP4]], 2 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , } [[TMP4]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , } [[TMP4]], 4 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg5e.nxv1f64.i64( [[TMP5]], [[TMP6]], [[TMP7]], [[TMP8]], [[TMP9]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg5e64_v_f64m1x5(double *base, vfloat64m1x5_t v_tuple, size_t vl) { + return __riscv_vsseg5e64_v_f64m1x5(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg5e64_v_i64m1x5 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , } [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , } [[TMP4]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , } [[TMP4]], 2 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , } [[TMP4]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , } [[TMP4]], 4 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg5e.nxv1i64.i64( [[TMP5]], [[TMP6]], [[TMP7]], [[TMP8]], [[TMP9]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg5e64_v_i64m1x5(int64_t *base, vint64m1x5_t v_tuple, size_t vl) { + return __riscv_vsseg5e64_v_i64m1x5(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg5e64_v_u64m1x5 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , } [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , } [[TMP4]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , } [[TMP4]], 2 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , } [[TMP4]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , } [[TMP4]], 4 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg5e.nxv1i64.i64( [[TMP5]], [[TMP6]], [[TMP7]], [[TMP8]], [[TMP9]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg5e64_v_u64m1x5(uint64_t *base, vuint64m1x5_t v_tuple, size_t vl) { + return __riscv_vsseg5e64_v_u64m1x5(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg5e64_v_f64m1x5_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , } [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , } [[TMP4]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , } [[TMP4]], 2 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , } [[TMP4]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , } [[TMP4]], 4 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg5e.mask.nxv1f64.i64( [[TMP5]], [[TMP6]], [[TMP7]], [[TMP8]], [[TMP9]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg5e64_v_f64m1x5_m(vbool64_t mask, double *base, vfloat64m1x5_t v_tuple, size_t vl) { + return __riscv_vsseg5e64_v_f64m1x5_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg5e64_v_i64m1x5_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , } [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , } [[TMP4]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , } [[TMP4]], 2 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , } [[TMP4]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , } [[TMP4]], 4 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg5e.mask.nxv1i64.i64( [[TMP5]], [[TMP6]], [[TMP7]], [[TMP8]], [[TMP9]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg5e64_v_i64m1x5_m(vbool64_t mask, int64_t *base, vint64m1x5_t v_tuple, size_t vl) { + return __riscv_vsseg5e64_v_i64m1x5_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg5e64_v_u64m1x5_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , } [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , } [[TMP4]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , } [[TMP4]], 2 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , } [[TMP4]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , } [[TMP4]], 4 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg5e.mask.nxv1i64.i64( [[TMP5]], [[TMP6]], [[TMP7]], [[TMP8]], [[TMP9]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg5e64_v_u64m1x5_m(vbool64_t mask, uint64_t *base, vuint64m1x5_t v_tuple, size_t vl) { + return __riscv_vsseg5e64_v_u64m1x5_m(mask, base, v_tuple, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg5e8.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg5e8.c new file mode 100644 index 00000000000000..3fd601eae4fef9 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg5e8.c @@ -0,0 +1,88 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg5e8_v_i8m1x5 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , } [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , } [[TMP4]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , } [[TMP4]], 2 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , } [[TMP4]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , } [[TMP4]], 4 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg5e.nxv8i8.i64( [[TMP5]], [[TMP6]], [[TMP7]], [[TMP8]], [[TMP9]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg5e8_v_i8m1x5(int8_t *base, vint8m1x5_t v_tuple, size_t vl) { + return __riscv_vsseg5e8_v_i8m1x5(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg5e8_v_u8m1x5 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , } [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , } [[TMP4]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , } [[TMP4]], 2 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , } [[TMP4]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , } [[TMP4]], 4 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg5e.nxv8i8.i64( [[TMP5]], [[TMP6]], [[TMP7]], [[TMP8]], [[TMP9]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg5e8_v_u8m1x5(uint8_t *base, vuint8m1x5_t v_tuple, size_t vl) { + return __riscv_vsseg5e8_v_u8m1x5(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg5e8_v_i8m1x5_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , } [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , } [[TMP4]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , } [[TMP4]], 2 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , } [[TMP4]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , } [[TMP4]], 4 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg5e.mask.nxv8i8.i64( [[TMP5]], [[TMP6]], [[TMP7]], [[TMP8]], [[TMP9]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg5e8_v_i8m1x5_m(vbool8_t mask, int8_t *base, vint8m1x5_t v_tuple, size_t vl) { + return __riscv_vsseg5e8_v_i8m1x5_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg5e8_v_u8m1x5_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , } [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , } [[TMP4]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , } [[TMP4]], 2 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , } [[TMP4]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , } [[TMP4]], 4 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg5e.mask.nxv8i8.i64( [[TMP5]], [[TMP6]], [[TMP7]], [[TMP8]], [[TMP9]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg5e8_v_u8m1x5_m(vbool8_t mask, uint8_t *base, vuint8m1x5_t v_tuple, size_t vl) { + return __riscv_vsseg5e8_v_u8m1x5_m(mask, base, v_tuple, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg6e16.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg6e16.c new file mode 100644 index 00000000000000..7782bf2bd016a4 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg6e16.c @@ -0,0 +1,140 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg6e16_v_f16m1x6 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , } [[TMP5]], 0 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , } [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , } [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , } [[TMP5]], 3 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , } [[TMP5]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , } [[TMP5]], 5 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg6e.nxv4f16.i64( [[TMP6]], [[TMP7]], [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg6e16_v_f16m1x6(_Float16 *base, vfloat16m1x6_t v_tuple, size_t vl) { + return __riscv_vsseg6e16_v_f16m1x6(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg6e16_v_i16m1x6 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , } [[TMP5]], 0 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , } [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , } [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , } [[TMP5]], 3 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , } [[TMP5]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , } [[TMP5]], 5 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg6e.nxv4i16.i64( [[TMP6]], [[TMP7]], [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg6e16_v_i16m1x6(int16_t *base, vint16m1x6_t v_tuple, size_t vl) { + return __riscv_vsseg6e16_v_i16m1x6(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg6e16_v_u16m1x6 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , } [[TMP5]], 0 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , } [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , } [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , } [[TMP5]], 3 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , } [[TMP5]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , } [[TMP5]], 5 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg6e.nxv4i16.i64( [[TMP6]], [[TMP7]], [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg6e16_v_u16m1x6(uint16_t *base, vuint16m1x6_t v_tuple, size_t vl) { + return __riscv_vsseg6e16_v_u16m1x6(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg6e16_v_f16m1x6_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , } [[TMP5]], 0 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , } [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , } [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , } [[TMP5]], 3 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , } [[TMP5]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , } [[TMP5]], 5 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg6e.mask.nxv4f16.i64( [[TMP6]], [[TMP7]], [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg6e16_v_f16m1x6_m(vbool16_t mask, _Float16 *base, vfloat16m1x6_t v_tuple, size_t vl) { + return __riscv_vsseg6e16_v_f16m1x6_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg6e16_v_i16m1x6_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , } [[TMP5]], 0 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , } [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , } [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , } [[TMP5]], 3 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , } [[TMP5]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , } [[TMP5]], 5 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg6e.mask.nxv4i16.i64( [[TMP6]], [[TMP7]], [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg6e16_v_i16m1x6_m(vbool16_t mask, int16_t *base, vint16m1x6_t v_tuple, size_t vl) { + return __riscv_vsseg6e16_v_i16m1x6_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg6e16_v_u16m1x6_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , } [[TMP5]], 0 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , } [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , } [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , } [[TMP5]], 3 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , } [[TMP5]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , } [[TMP5]], 5 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg6e.mask.nxv4i16.i64( [[TMP6]], [[TMP7]], [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg6e16_v_u16m1x6_m(vbool16_t mask, uint16_t *base, vuint16m1x6_t v_tuple, size_t vl) { + return __riscv_vsseg6e16_v_u16m1x6_m(mask, base, v_tuple, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg6e32.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg6e32.c new file mode 100644 index 00000000000000..cf65fa949333f7 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg6e32.c @@ -0,0 +1,140 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg6e32_v_f32m1x6 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , } [[TMP5]], 0 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , } [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , } [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , } [[TMP5]], 3 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , } [[TMP5]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , } [[TMP5]], 5 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg6e.nxv2f32.i64( [[TMP6]], [[TMP7]], [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg6e32_v_f32m1x6(float *base, vfloat32m1x6_t v_tuple, size_t vl) { + return __riscv_vsseg6e32_v_f32m1x6(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg6e32_v_i32m1x6 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , } [[TMP5]], 0 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , } [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , } [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , } [[TMP5]], 3 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , } [[TMP5]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , } [[TMP5]], 5 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg6e.nxv2i32.i64( [[TMP6]], [[TMP7]], [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg6e32_v_i32m1x6(int32_t *base, vint32m1x6_t v_tuple, size_t vl) { + return __riscv_vsseg6e32_v_i32m1x6(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg6e32_v_u32m1x6 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , } [[TMP5]], 0 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , } [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , } [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , } [[TMP5]], 3 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , } [[TMP5]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , } [[TMP5]], 5 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg6e.nxv2i32.i64( [[TMP6]], [[TMP7]], [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg6e32_v_u32m1x6(uint32_t *base, vuint32m1x6_t v_tuple, size_t vl) { + return __riscv_vsseg6e32_v_u32m1x6(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg6e32_v_f32m1x6_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , } [[TMP5]], 0 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , } [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , } [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , } [[TMP5]], 3 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , } [[TMP5]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , } [[TMP5]], 5 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg6e.mask.nxv2f32.i64( [[TMP6]], [[TMP7]], [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg6e32_v_f32m1x6_m(vbool32_t mask, float *base, vfloat32m1x6_t v_tuple, size_t vl) { + return __riscv_vsseg6e32_v_f32m1x6_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg6e32_v_i32m1x6_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , } [[TMP5]], 0 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , } [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , } [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , } [[TMP5]], 3 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , } [[TMP5]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , } [[TMP5]], 5 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg6e.mask.nxv2i32.i64( [[TMP6]], [[TMP7]], [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg6e32_v_i32m1x6_m(vbool32_t mask, int32_t *base, vint32m1x6_t v_tuple, size_t vl) { + return __riscv_vsseg6e32_v_i32m1x6_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg6e32_v_u32m1x6_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , } [[TMP5]], 0 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , } [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , } [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , } [[TMP5]], 3 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , } [[TMP5]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , } [[TMP5]], 5 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg6e.mask.nxv2i32.i64( [[TMP6]], [[TMP7]], [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg6e32_v_u32m1x6_m(vbool32_t mask, uint32_t *base, vuint32m1x6_t v_tuple, size_t vl) { + return __riscv_vsseg6e32_v_u32m1x6_m(mask, base, v_tuple, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg6e64.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg6e64.c new file mode 100644 index 00000000000000..3c6c03bae82db8 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg6e64.c @@ -0,0 +1,140 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg6e64_v_f64m1x6 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , } [[TMP5]], 0 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , } [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , } [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , } [[TMP5]], 3 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , } [[TMP5]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , } [[TMP5]], 5 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg6e.nxv1f64.i64( [[TMP6]], [[TMP7]], [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg6e64_v_f64m1x6(double *base, vfloat64m1x6_t v_tuple, size_t vl) { + return __riscv_vsseg6e64_v_f64m1x6(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg6e64_v_i64m1x6 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , } [[TMP5]], 0 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , } [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , } [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , } [[TMP5]], 3 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , } [[TMP5]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , } [[TMP5]], 5 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg6e.nxv1i64.i64( [[TMP6]], [[TMP7]], [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg6e64_v_i64m1x6(int64_t *base, vint64m1x6_t v_tuple, size_t vl) { + return __riscv_vsseg6e64_v_i64m1x6(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg6e64_v_u64m1x6 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , } [[TMP5]], 0 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , } [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , } [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , } [[TMP5]], 3 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , } [[TMP5]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , } [[TMP5]], 5 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg6e.nxv1i64.i64( [[TMP6]], [[TMP7]], [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg6e64_v_u64m1x6(uint64_t *base, vuint64m1x6_t v_tuple, size_t vl) { + return __riscv_vsseg6e64_v_u64m1x6(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg6e64_v_f64m1x6_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , } [[TMP5]], 0 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , } [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , } [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , } [[TMP5]], 3 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , } [[TMP5]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , } [[TMP5]], 5 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg6e.mask.nxv1f64.i64( [[TMP6]], [[TMP7]], [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg6e64_v_f64m1x6_m(vbool64_t mask, double *base, vfloat64m1x6_t v_tuple, size_t vl) { + return __riscv_vsseg6e64_v_f64m1x6_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg6e64_v_i64m1x6_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , } [[TMP5]], 0 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , } [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , } [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , } [[TMP5]], 3 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , } [[TMP5]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , } [[TMP5]], 5 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg6e.mask.nxv1i64.i64( [[TMP6]], [[TMP7]], [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg6e64_v_i64m1x6_m(vbool64_t mask, int64_t *base, vint64m1x6_t v_tuple, size_t vl) { + return __riscv_vsseg6e64_v_i64m1x6_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg6e64_v_u64m1x6_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , } [[TMP5]], 0 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , } [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , } [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , } [[TMP5]], 3 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , } [[TMP5]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , } [[TMP5]], 5 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg6e.mask.nxv1i64.i64( [[TMP6]], [[TMP7]], [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg6e64_v_u64m1x6_m(vbool64_t mask, uint64_t *base, vuint64m1x6_t v_tuple, size_t vl) { + return __riscv_vsseg6e64_v_u64m1x6_m(mask, base, v_tuple, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg6e8.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg6e8.c new file mode 100644 index 00000000000000..58939237a0dc27 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg6e8.c @@ -0,0 +1,96 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg6e8_v_i8m1x6 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , } [[TMP5]], 0 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , } [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , } [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , } [[TMP5]], 3 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , } [[TMP5]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , } [[TMP5]], 5 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg6e.nxv8i8.i64( [[TMP6]], [[TMP7]], [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg6e8_v_i8m1x6(int8_t *base, vint8m1x6_t v_tuple, size_t vl) { + return __riscv_vsseg6e8_v_i8m1x6(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg6e8_v_u8m1x6 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , } [[TMP5]], 0 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , } [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , } [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , } [[TMP5]], 3 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , } [[TMP5]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , } [[TMP5]], 5 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg6e.nxv8i8.i64( [[TMP6]], [[TMP7]], [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg6e8_v_u8m1x6(uint8_t *base, vuint8m1x6_t v_tuple, size_t vl) { + return __riscv_vsseg6e8_v_u8m1x6(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg6e8_v_i8m1x6_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , } [[TMP5]], 0 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , } [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , } [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , } [[TMP5]], 3 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , } [[TMP5]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , } [[TMP5]], 5 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg6e.mask.nxv8i8.i64( [[TMP6]], [[TMP7]], [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg6e8_v_i8m1x6_m(vbool8_t mask, int8_t *base, vint8m1x6_t v_tuple, size_t vl) { + return __riscv_vsseg6e8_v_i8m1x6_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg6e8_v_u8m1x6_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , } [[TMP5]], 0 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , } [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , } [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , } [[TMP5]], 3 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , } [[TMP5]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , } [[TMP5]], 5 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg6e.mask.nxv8i8.i64( [[TMP6]], [[TMP7]], [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg6e8_v_u8m1x6_m(vbool8_t mask, uint8_t *base, vuint8m1x6_t v_tuple, size_t vl) { + return __riscv_vsseg6e8_v_u8m1x6_m(mask, base, v_tuple, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg7e16.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg7e16.c new file mode 100644 index 00000000000000..e8f47cc39def00 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg7e16.c @@ -0,0 +1,152 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg7e16_v_f16m1x7 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], [[V_TUPLE_COERCE6:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , } [[TMP5]], [[V_TUPLE_COERCE6]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , } [[TMP6]], 0 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , } [[TMP6]], 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , } [[TMP6]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , } [[TMP6]], 3 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , } [[TMP6]], 4 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , } [[TMP6]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , } [[TMP6]], 6 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg7e.nxv4f16.i64( [[TMP7]], [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], [[TMP12]], [[TMP13]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg7e16_v_f16m1x7(_Float16 *base, vfloat16m1x7_t v_tuple, size_t vl) { + return __riscv_vsseg7e16_v_f16m1x7(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg7e16_v_i16m1x7 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], [[V_TUPLE_COERCE6:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , } [[TMP5]], [[V_TUPLE_COERCE6]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , } [[TMP6]], 0 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , } [[TMP6]], 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , } [[TMP6]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , } [[TMP6]], 3 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , } [[TMP6]], 4 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , } [[TMP6]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , } [[TMP6]], 6 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg7e.nxv4i16.i64( [[TMP7]], [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], [[TMP12]], [[TMP13]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg7e16_v_i16m1x7(int16_t *base, vint16m1x7_t v_tuple, size_t vl) { + return __riscv_vsseg7e16_v_i16m1x7(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg7e16_v_u16m1x7 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], [[V_TUPLE_COERCE6:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , } [[TMP5]], [[V_TUPLE_COERCE6]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , } [[TMP6]], 0 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , } [[TMP6]], 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , } [[TMP6]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , } [[TMP6]], 3 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , } [[TMP6]], 4 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , } [[TMP6]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , } [[TMP6]], 6 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg7e.nxv4i16.i64( [[TMP7]], [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], [[TMP12]], [[TMP13]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg7e16_v_u16m1x7(uint16_t *base, vuint16m1x7_t v_tuple, size_t vl) { + return __riscv_vsseg7e16_v_u16m1x7(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg7e16_v_f16m1x7_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], [[V_TUPLE_COERCE6:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , } [[TMP5]], [[V_TUPLE_COERCE6]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , } [[TMP6]], 0 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , } [[TMP6]], 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , } [[TMP6]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , } [[TMP6]], 3 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , } [[TMP6]], 4 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , } [[TMP6]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , } [[TMP6]], 6 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg7e.mask.nxv4f16.i64( [[TMP7]], [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], [[TMP12]], [[TMP13]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg7e16_v_f16m1x7_m(vbool16_t mask, _Float16 *base, vfloat16m1x7_t v_tuple, size_t vl) { + return __riscv_vsseg7e16_v_f16m1x7_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg7e16_v_i16m1x7_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], [[V_TUPLE_COERCE6:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , } [[TMP5]], [[V_TUPLE_COERCE6]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , } [[TMP6]], 0 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , } [[TMP6]], 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , } [[TMP6]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , } [[TMP6]], 3 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , } [[TMP6]], 4 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , } [[TMP6]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , } [[TMP6]], 6 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg7e.mask.nxv4i16.i64( [[TMP7]], [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], [[TMP12]], [[TMP13]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg7e16_v_i16m1x7_m(vbool16_t mask, int16_t *base, vint16m1x7_t v_tuple, size_t vl) { + return __riscv_vsseg7e16_v_i16m1x7_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg7e16_v_u16m1x7_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], [[V_TUPLE_COERCE6:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , } [[TMP5]], [[V_TUPLE_COERCE6]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , } [[TMP6]], 0 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , } [[TMP6]], 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , } [[TMP6]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , } [[TMP6]], 3 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , } [[TMP6]], 4 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , } [[TMP6]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , } [[TMP6]], 6 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg7e.mask.nxv4i16.i64( [[TMP7]], [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], [[TMP12]], [[TMP13]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg7e16_v_u16m1x7_m(vbool16_t mask, uint16_t *base, vuint16m1x7_t v_tuple, size_t vl) { + return __riscv_vsseg7e16_v_u16m1x7_m(mask, base, v_tuple, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg7e32.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg7e32.c new file mode 100644 index 00000000000000..fea5ff41165e41 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg7e32.c @@ -0,0 +1,152 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg7e32_v_f32m1x7 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], [[V_TUPLE_COERCE6:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , } [[TMP5]], [[V_TUPLE_COERCE6]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , } [[TMP6]], 0 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , } [[TMP6]], 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , } [[TMP6]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , } [[TMP6]], 3 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , } [[TMP6]], 4 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , } [[TMP6]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , } [[TMP6]], 6 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg7e.nxv2f32.i64( [[TMP7]], [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], [[TMP12]], [[TMP13]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg7e32_v_f32m1x7(float *base, vfloat32m1x7_t v_tuple, size_t vl) { + return __riscv_vsseg7e32_v_f32m1x7(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg7e32_v_i32m1x7 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], [[V_TUPLE_COERCE6:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , } [[TMP5]], [[V_TUPLE_COERCE6]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , } [[TMP6]], 0 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , } [[TMP6]], 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , } [[TMP6]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , } [[TMP6]], 3 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , } [[TMP6]], 4 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , } [[TMP6]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , } [[TMP6]], 6 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg7e.nxv2i32.i64( [[TMP7]], [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], [[TMP12]], [[TMP13]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg7e32_v_i32m1x7(int32_t *base, vint32m1x7_t v_tuple, size_t vl) { + return __riscv_vsseg7e32_v_i32m1x7(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg7e32_v_u32m1x7 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], [[V_TUPLE_COERCE6:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , } [[TMP5]], [[V_TUPLE_COERCE6]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , } [[TMP6]], 0 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , } [[TMP6]], 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , } [[TMP6]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , } [[TMP6]], 3 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , } [[TMP6]], 4 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , } [[TMP6]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , } [[TMP6]], 6 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg7e.nxv2i32.i64( [[TMP7]], [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], [[TMP12]], [[TMP13]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg7e32_v_u32m1x7(uint32_t *base, vuint32m1x7_t v_tuple, size_t vl) { + return __riscv_vsseg7e32_v_u32m1x7(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg7e32_v_f32m1x7_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], [[V_TUPLE_COERCE6:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , } [[TMP5]], [[V_TUPLE_COERCE6]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , } [[TMP6]], 0 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , } [[TMP6]], 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , } [[TMP6]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , } [[TMP6]], 3 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , } [[TMP6]], 4 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , } [[TMP6]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , } [[TMP6]], 6 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg7e.mask.nxv2f32.i64( [[TMP7]], [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], [[TMP12]], [[TMP13]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg7e32_v_f32m1x7_m(vbool32_t mask, float *base, vfloat32m1x7_t v_tuple, size_t vl) { + return __riscv_vsseg7e32_v_f32m1x7_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg7e32_v_i32m1x7_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], [[V_TUPLE_COERCE6:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , } [[TMP5]], [[V_TUPLE_COERCE6]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , } [[TMP6]], 0 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , } [[TMP6]], 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , } [[TMP6]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , } [[TMP6]], 3 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , } [[TMP6]], 4 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , } [[TMP6]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , } [[TMP6]], 6 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg7e.mask.nxv2i32.i64( [[TMP7]], [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], [[TMP12]], [[TMP13]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg7e32_v_i32m1x7_m(vbool32_t mask, int32_t *base, vint32m1x7_t v_tuple, size_t vl) { + return __riscv_vsseg7e32_v_i32m1x7_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg7e32_v_u32m1x7_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], [[V_TUPLE_COERCE6:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , } [[TMP5]], [[V_TUPLE_COERCE6]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , } [[TMP6]], 0 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , } [[TMP6]], 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , } [[TMP6]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , } [[TMP6]], 3 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , } [[TMP6]], 4 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , } [[TMP6]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , } [[TMP6]], 6 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg7e.mask.nxv2i32.i64( [[TMP7]], [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], [[TMP12]], [[TMP13]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg7e32_v_u32m1x7_m(vbool32_t mask, uint32_t *base, vuint32m1x7_t v_tuple, size_t vl) { + return __riscv_vsseg7e32_v_u32m1x7_m(mask, base, v_tuple, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg7e64.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg7e64.c new file mode 100644 index 00000000000000..addf9eb6373586 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg7e64.c @@ -0,0 +1,152 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg7e64_v_f64m1x7 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], [[V_TUPLE_COERCE6:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , } [[TMP5]], [[V_TUPLE_COERCE6]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , } [[TMP6]], 0 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , } [[TMP6]], 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , } [[TMP6]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , } [[TMP6]], 3 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , } [[TMP6]], 4 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , } [[TMP6]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , } [[TMP6]], 6 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg7e.nxv1f64.i64( [[TMP7]], [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], [[TMP12]], [[TMP13]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg7e64_v_f64m1x7(double *base, vfloat64m1x7_t v_tuple, size_t vl) { + return __riscv_vsseg7e64_v_f64m1x7(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg7e64_v_i64m1x7 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], [[V_TUPLE_COERCE6:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , } [[TMP5]], [[V_TUPLE_COERCE6]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , } [[TMP6]], 0 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , } [[TMP6]], 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , } [[TMP6]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , } [[TMP6]], 3 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , } [[TMP6]], 4 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , } [[TMP6]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , } [[TMP6]], 6 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg7e.nxv1i64.i64( [[TMP7]], [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], [[TMP12]], [[TMP13]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg7e64_v_i64m1x7(int64_t *base, vint64m1x7_t v_tuple, size_t vl) { + return __riscv_vsseg7e64_v_i64m1x7(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg7e64_v_u64m1x7 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], [[V_TUPLE_COERCE6:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , } [[TMP5]], [[V_TUPLE_COERCE6]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , } [[TMP6]], 0 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , } [[TMP6]], 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , } [[TMP6]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , } [[TMP6]], 3 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , } [[TMP6]], 4 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , } [[TMP6]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , } [[TMP6]], 6 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg7e.nxv1i64.i64( [[TMP7]], [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], [[TMP12]], [[TMP13]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg7e64_v_u64m1x7(uint64_t *base, vuint64m1x7_t v_tuple, size_t vl) { + return __riscv_vsseg7e64_v_u64m1x7(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg7e64_v_f64m1x7_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], [[V_TUPLE_COERCE6:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , } [[TMP5]], [[V_TUPLE_COERCE6]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , } [[TMP6]], 0 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , } [[TMP6]], 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , } [[TMP6]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , } [[TMP6]], 3 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , } [[TMP6]], 4 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , } [[TMP6]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , } [[TMP6]], 6 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg7e.mask.nxv1f64.i64( [[TMP7]], [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], [[TMP12]], [[TMP13]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg7e64_v_f64m1x7_m(vbool64_t mask, double *base, vfloat64m1x7_t v_tuple, size_t vl) { + return __riscv_vsseg7e64_v_f64m1x7_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg7e64_v_i64m1x7_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], [[V_TUPLE_COERCE6:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , } [[TMP5]], [[V_TUPLE_COERCE6]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , } [[TMP6]], 0 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , } [[TMP6]], 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , } [[TMP6]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , } [[TMP6]], 3 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , } [[TMP6]], 4 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , } [[TMP6]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , } [[TMP6]], 6 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg7e.mask.nxv1i64.i64( [[TMP7]], [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], [[TMP12]], [[TMP13]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg7e64_v_i64m1x7_m(vbool64_t mask, int64_t *base, vint64m1x7_t v_tuple, size_t vl) { + return __riscv_vsseg7e64_v_i64m1x7_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg7e64_v_u64m1x7_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], [[V_TUPLE_COERCE6:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , } [[TMP5]], [[V_TUPLE_COERCE6]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , } [[TMP6]], 0 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , } [[TMP6]], 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , } [[TMP6]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , } [[TMP6]], 3 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , } [[TMP6]], 4 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , } [[TMP6]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , } [[TMP6]], 6 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg7e.mask.nxv1i64.i64( [[TMP7]], [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], [[TMP12]], [[TMP13]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg7e64_v_u64m1x7_m(vbool64_t mask, uint64_t *base, vuint64m1x7_t v_tuple, size_t vl) { + return __riscv_vsseg7e64_v_u64m1x7_m(mask, base, v_tuple, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg7e8.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg7e8.c new file mode 100644 index 00000000000000..5545d7de2043ee --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg7e8.c @@ -0,0 +1,104 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg7e8_v_i8m1x7 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], [[V_TUPLE_COERCE6:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , } [[TMP5]], [[V_TUPLE_COERCE6]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , } [[TMP6]], 0 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , } [[TMP6]], 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , } [[TMP6]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , } [[TMP6]], 3 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , } [[TMP6]], 4 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , } [[TMP6]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , } [[TMP6]], 6 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg7e.nxv8i8.i64( [[TMP7]], [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], [[TMP12]], [[TMP13]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg7e8_v_i8m1x7(int8_t *base, vint8m1x7_t v_tuple, size_t vl) { + return __riscv_vsseg7e8_v_i8m1x7(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg7e8_v_u8m1x7 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], [[V_TUPLE_COERCE6:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , } [[TMP5]], [[V_TUPLE_COERCE6]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , } [[TMP6]], 0 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , } [[TMP6]], 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , } [[TMP6]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , } [[TMP6]], 3 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , } [[TMP6]], 4 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , } [[TMP6]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , } [[TMP6]], 6 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg7e.nxv8i8.i64( [[TMP7]], [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], [[TMP12]], [[TMP13]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg7e8_v_u8m1x7(uint8_t *base, vuint8m1x7_t v_tuple, size_t vl) { + return __riscv_vsseg7e8_v_u8m1x7(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg7e8_v_i8m1x7_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], [[V_TUPLE_COERCE6:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , } [[TMP5]], [[V_TUPLE_COERCE6]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , } [[TMP6]], 0 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , } [[TMP6]], 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , } [[TMP6]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , } [[TMP6]], 3 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , } [[TMP6]], 4 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , } [[TMP6]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , } [[TMP6]], 6 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg7e.mask.nxv8i8.i64( [[TMP7]], [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], [[TMP12]], [[TMP13]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg7e8_v_i8m1x7_m(vbool8_t mask, int8_t *base, vint8m1x7_t v_tuple, size_t vl) { + return __riscv_vsseg7e8_v_i8m1x7_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg7e8_v_u8m1x7_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], [[V_TUPLE_COERCE6:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , } [[TMP5]], [[V_TUPLE_COERCE6]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , } [[TMP6]], 0 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , } [[TMP6]], 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , } [[TMP6]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , } [[TMP6]], 3 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , } [[TMP6]], 4 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , } [[TMP6]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , } [[TMP6]], 6 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg7e.mask.nxv8i8.i64( [[TMP7]], [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], [[TMP12]], [[TMP13]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg7e8_v_u8m1x7_m(vbool8_t mask, uint8_t *base, vuint8m1x7_t v_tuple, size_t vl) { + return __riscv_vsseg7e8_v_u8m1x7_m(mask, base, v_tuple, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg8e16.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg8e16.c new file mode 100644 index 00000000000000..547f9790920752 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg8e16.c @@ -0,0 +1,164 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg8e16_v_f16m1x8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], [[V_TUPLE_COERCE6:%.*]], [[V_TUPLE_COERCE7:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , , } [[TMP5]], [[V_TUPLE_COERCE6]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , , , , , , } [[TMP6]], [[V_TUPLE_COERCE7]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 0 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 1 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 2 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 4 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 5 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 6 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 7 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg8e.nxv4f16.i64( [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], [[TMP12]], [[TMP13]], [[TMP14]], [[TMP15]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg8e16_v_f16m1x8(_Float16 *base, vfloat16m1x8_t v_tuple, size_t vl) { + return __riscv_vsseg8e16_v_f16m1x8(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg8e16_v_i16m1x8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], [[V_TUPLE_COERCE6:%.*]], [[V_TUPLE_COERCE7:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , , } [[TMP5]], [[V_TUPLE_COERCE6]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , , , , , , } [[TMP6]], [[V_TUPLE_COERCE7]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 0 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 1 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 2 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 4 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 5 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 6 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 7 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg8e.nxv4i16.i64( [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], [[TMP12]], [[TMP13]], [[TMP14]], [[TMP15]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg8e16_v_i16m1x8(int16_t *base, vint16m1x8_t v_tuple, size_t vl) { + return __riscv_vsseg8e16_v_i16m1x8(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg8e16_v_u16m1x8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], [[V_TUPLE_COERCE6:%.*]], [[V_TUPLE_COERCE7:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , , } [[TMP5]], [[V_TUPLE_COERCE6]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , , , , , , } [[TMP6]], [[V_TUPLE_COERCE7]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 0 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 1 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 2 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 4 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 5 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 6 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 7 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg8e.nxv4i16.i64( [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], [[TMP12]], [[TMP13]], [[TMP14]], [[TMP15]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg8e16_v_u16m1x8(uint16_t *base, vuint16m1x8_t v_tuple, size_t vl) { + return __riscv_vsseg8e16_v_u16m1x8(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg8e16_v_f16m1x8_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], [[V_TUPLE_COERCE6:%.*]], [[V_TUPLE_COERCE7:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , , } [[TMP5]], [[V_TUPLE_COERCE6]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , , , , , , } [[TMP6]], [[V_TUPLE_COERCE7]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 0 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 1 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 2 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 4 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 5 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 6 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 7 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg8e.mask.nxv4f16.i64( [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], [[TMP12]], [[TMP13]], [[TMP14]], [[TMP15]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg8e16_v_f16m1x8_m(vbool16_t mask, _Float16 *base, vfloat16m1x8_t v_tuple, size_t vl) { + return __riscv_vsseg8e16_v_f16m1x8_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg8e16_v_i16m1x8_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], [[V_TUPLE_COERCE6:%.*]], [[V_TUPLE_COERCE7:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , , } [[TMP5]], [[V_TUPLE_COERCE6]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , , , , , , } [[TMP6]], [[V_TUPLE_COERCE7]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 0 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 1 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 2 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 4 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 5 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 6 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 7 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg8e.mask.nxv4i16.i64( [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], [[TMP12]], [[TMP13]], [[TMP14]], [[TMP15]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg8e16_v_i16m1x8_m(vbool16_t mask, int16_t *base, vint16m1x8_t v_tuple, size_t vl) { + return __riscv_vsseg8e16_v_i16m1x8_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg8e16_v_u16m1x8_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], [[V_TUPLE_COERCE6:%.*]], [[V_TUPLE_COERCE7:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , , } [[TMP5]], [[V_TUPLE_COERCE6]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , , , , , , } [[TMP6]], [[V_TUPLE_COERCE7]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 0 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 1 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 2 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 4 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 5 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 6 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 7 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg8e.mask.nxv4i16.i64( [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], [[TMP12]], [[TMP13]], [[TMP14]], [[TMP15]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg8e16_v_u16m1x8_m(vbool16_t mask, uint16_t *base, vuint16m1x8_t v_tuple, size_t vl) { + return __riscv_vsseg8e16_v_u16m1x8_m(mask, base, v_tuple, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg8e32.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg8e32.c new file mode 100644 index 00000000000000..3e3d5b5b821892 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg8e32.c @@ -0,0 +1,164 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg8e32_v_f32m1x8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], [[V_TUPLE_COERCE6:%.*]], [[V_TUPLE_COERCE7:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , , } [[TMP5]], [[V_TUPLE_COERCE6]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , , , , , , } [[TMP6]], [[V_TUPLE_COERCE7]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 0 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 1 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 2 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 4 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 5 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 6 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 7 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg8e.nxv2f32.i64( [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], [[TMP12]], [[TMP13]], [[TMP14]], [[TMP15]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg8e32_v_f32m1x8(float *base, vfloat32m1x8_t v_tuple, size_t vl) { + return __riscv_vsseg8e32_v_f32m1x8(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg8e32_v_i32m1x8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], [[V_TUPLE_COERCE6:%.*]], [[V_TUPLE_COERCE7:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , , } [[TMP5]], [[V_TUPLE_COERCE6]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , , , , , , } [[TMP6]], [[V_TUPLE_COERCE7]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 0 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 1 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 2 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 4 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 5 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 6 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 7 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg8e.nxv2i32.i64( [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], [[TMP12]], [[TMP13]], [[TMP14]], [[TMP15]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg8e32_v_i32m1x8(int32_t *base, vint32m1x8_t v_tuple, size_t vl) { + return __riscv_vsseg8e32_v_i32m1x8(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg8e32_v_u32m1x8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], [[V_TUPLE_COERCE6:%.*]], [[V_TUPLE_COERCE7:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , , } [[TMP5]], [[V_TUPLE_COERCE6]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , , , , , , } [[TMP6]], [[V_TUPLE_COERCE7]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 0 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 1 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 2 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 4 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 5 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 6 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 7 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg8e.nxv2i32.i64( [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], [[TMP12]], [[TMP13]], [[TMP14]], [[TMP15]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg8e32_v_u32m1x8(uint32_t *base, vuint32m1x8_t v_tuple, size_t vl) { + return __riscv_vsseg8e32_v_u32m1x8(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg8e32_v_f32m1x8_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], [[V_TUPLE_COERCE6:%.*]], [[V_TUPLE_COERCE7:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , , } [[TMP5]], [[V_TUPLE_COERCE6]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , , , , , , } [[TMP6]], [[V_TUPLE_COERCE7]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 0 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 1 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 2 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 4 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 5 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 6 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 7 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg8e.mask.nxv2f32.i64( [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], [[TMP12]], [[TMP13]], [[TMP14]], [[TMP15]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg8e32_v_f32m1x8_m(vbool32_t mask, float *base, vfloat32m1x8_t v_tuple, size_t vl) { + return __riscv_vsseg8e32_v_f32m1x8_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg8e32_v_i32m1x8_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], [[V_TUPLE_COERCE6:%.*]], [[V_TUPLE_COERCE7:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , , } [[TMP5]], [[V_TUPLE_COERCE6]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , , , , , , } [[TMP6]], [[V_TUPLE_COERCE7]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 0 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 1 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 2 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 4 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 5 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 6 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 7 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg8e.mask.nxv2i32.i64( [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], [[TMP12]], [[TMP13]], [[TMP14]], [[TMP15]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg8e32_v_i32m1x8_m(vbool32_t mask, int32_t *base, vint32m1x8_t v_tuple, size_t vl) { + return __riscv_vsseg8e32_v_i32m1x8_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg8e32_v_u32m1x8_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], [[V_TUPLE_COERCE6:%.*]], [[V_TUPLE_COERCE7:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , , } [[TMP5]], [[V_TUPLE_COERCE6]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , , , , , , } [[TMP6]], [[V_TUPLE_COERCE7]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 0 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 1 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 2 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 4 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 5 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 6 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 7 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg8e.mask.nxv2i32.i64( [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], [[TMP12]], [[TMP13]], [[TMP14]], [[TMP15]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg8e32_v_u32m1x8_m(vbool32_t mask, uint32_t *base, vuint32m1x8_t v_tuple, size_t vl) { + return __riscv_vsseg8e32_v_u32m1x8_m(mask, base, v_tuple, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg8e64.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg8e64.c new file mode 100644 index 00000000000000..93dbcd2477d10f --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg8e64.c @@ -0,0 +1,164 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg8e64_v_f64m1x8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], [[V_TUPLE_COERCE6:%.*]], [[V_TUPLE_COERCE7:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , , } [[TMP5]], [[V_TUPLE_COERCE6]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , , , , , , } [[TMP6]], [[V_TUPLE_COERCE7]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 0 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 1 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 2 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 4 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 5 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 6 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 7 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg8e.nxv1f64.i64( [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], [[TMP12]], [[TMP13]], [[TMP14]], [[TMP15]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg8e64_v_f64m1x8(double *base, vfloat64m1x8_t v_tuple, size_t vl) { + return __riscv_vsseg8e64_v_f64m1x8(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg8e64_v_i64m1x8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], [[V_TUPLE_COERCE6:%.*]], [[V_TUPLE_COERCE7:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , , } [[TMP5]], [[V_TUPLE_COERCE6]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , , , , , , } [[TMP6]], [[V_TUPLE_COERCE7]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 0 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 1 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 2 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 4 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 5 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 6 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 7 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg8e.nxv1i64.i64( [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], [[TMP12]], [[TMP13]], [[TMP14]], [[TMP15]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg8e64_v_i64m1x8(int64_t *base, vint64m1x8_t v_tuple, size_t vl) { + return __riscv_vsseg8e64_v_i64m1x8(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg8e64_v_u64m1x8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], [[V_TUPLE_COERCE6:%.*]], [[V_TUPLE_COERCE7:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , , } [[TMP5]], [[V_TUPLE_COERCE6]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , , , , , , } [[TMP6]], [[V_TUPLE_COERCE7]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 0 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 1 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 2 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 4 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 5 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 6 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 7 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg8e.nxv1i64.i64( [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], [[TMP12]], [[TMP13]], [[TMP14]], [[TMP15]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg8e64_v_u64m1x8(uint64_t *base, vuint64m1x8_t v_tuple, size_t vl) { + return __riscv_vsseg8e64_v_u64m1x8(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg8e64_v_f64m1x8_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], [[V_TUPLE_COERCE6:%.*]], [[V_TUPLE_COERCE7:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , , } [[TMP5]], [[V_TUPLE_COERCE6]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , , , , , , } [[TMP6]], [[V_TUPLE_COERCE7]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 0 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 1 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 2 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 4 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 5 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 6 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 7 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg8e.mask.nxv1f64.i64( [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], [[TMP12]], [[TMP13]], [[TMP14]], [[TMP15]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg8e64_v_f64m1x8_m(vbool64_t mask, double *base, vfloat64m1x8_t v_tuple, size_t vl) { + return __riscv_vsseg8e64_v_f64m1x8_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg8e64_v_i64m1x8_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], [[V_TUPLE_COERCE6:%.*]], [[V_TUPLE_COERCE7:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , , } [[TMP5]], [[V_TUPLE_COERCE6]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , , , , , , } [[TMP6]], [[V_TUPLE_COERCE7]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 0 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 1 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 2 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 4 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 5 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 6 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 7 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg8e.mask.nxv1i64.i64( [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], [[TMP12]], [[TMP13]], [[TMP14]], [[TMP15]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg8e64_v_i64m1x8_m(vbool64_t mask, int64_t *base, vint64m1x8_t v_tuple, size_t vl) { + return __riscv_vsseg8e64_v_i64m1x8_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg8e64_v_u64m1x8_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], [[V_TUPLE_COERCE6:%.*]], [[V_TUPLE_COERCE7:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , , } [[TMP5]], [[V_TUPLE_COERCE6]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , , , , , , } [[TMP6]], [[V_TUPLE_COERCE7]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 0 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 1 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 2 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 4 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 5 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 6 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 7 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg8e.mask.nxv1i64.i64( [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], [[TMP12]], [[TMP13]], [[TMP14]], [[TMP15]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg8e64_v_u64m1x8_m(vbool64_t mask, uint64_t *base, vuint64m1x8_t v_tuple, size_t vl) { + return __riscv_vsseg8e64_v_u64m1x8_m(mask, base, v_tuple, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg8e8.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg8e8.c new file mode 100644 index 00000000000000..39d74b781e2a43 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/zvlsseg/unit-stride/wrappers/vsseg8e8.c @@ -0,0 +1,112 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg8e8_v_i8m1x8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], [[V_TUPLE_COERCE6:%.*]], [[V_TUPLE_COERCE7:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , , } [[TMP5]], [[V_TUPLE_COERCE6]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , , , , , , } [[TMP6]], [[V_TUPLE_COERCE7]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 0 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 1 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 2 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 4 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 5 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 6 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 7 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg8e.nxv8i8.i64( [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], [[TMP12]], [[TMP13]], [[TMP14]], [[TMP15]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg8e8_v_i8m1x8(int8_t *base, vint8m1x8_t v_tuple, size_t vl) { + return __riscv_vsseg8e8_v_i8m1x8(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg8e8_v_u8m1x8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], [[V_TUPLE_COERCE6:%.*]], [[V_TUPLE_COERCE7:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , , } [[TMP5]], [[V_TUPLE_COERCE6]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , , , , , , } [[TMP6]], [[V_TUPLE_COERCE7]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 0 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 1 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 2 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 4 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 5 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 6 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 7 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg8e.nxv8i8.i64( [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], [[TMP12]], [[TMP13]], [[TMP14]], [[TMP15]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg8e8_v_u8m1x8(uint8_t *base, vuint8m1x8_t v_tuple, size_t vl) { + return __riscv_vsseg8e8_v_u8m1x8(base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg8e8_v_i8m1x8_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], [[V_TUPLE_COERCE6:%.*]], [[V_TUPLE_COERCE7:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , , } [[TMP5]], [[V_TUPLE_COERCE6]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , , , , , , } [[TMP6]], [[V_TUPLE_COERCE7]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 0 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 1 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 2 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 4 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 5 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 6 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 7 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg8e.mask.nxv8i8.i64( [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], [[TMP12]], [[TMP13]], [[TMP14]], [[TMP15]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg8e8_v_i8m1x8_m(vbool8_t mask, int8_t *base, vint8m1x8_t v_tuple, size_t vl) { + return __riscv_vsseg8e8_v_i8m1x8_m(mask, base, v_tuple, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_th_vsseg8e8_v_u8m1x8_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]], [[V_TUPLE_COERCE0:%.*]], [[V_TUPLE_COERCE1:%.*]], [[V_TUPLE_COERCE2:%.*]], [[V_TUPLE_COERCE3:%.*]], [[V_TUPLE_COERCE4:%.*]], [[V_TUPLE_COERCE5:%.*]], [[V_TUPLE_COERCE6:%.*]], [[V_TUPLE_COERCE7:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , , } poison, [[V_TUPLE_COERCE0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , , , } [[TMP0]], [[V_TUPLE_COERCE1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , , } [[TMP1]], [[V_TUPLE_COERCE2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , , , } [[TMP2]], [[V_TUPLE_COERCE3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , , } [[TMP3]], [[V_TUPLE_COERCE4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , , , } [[TMP4]], [[V_TUPLE_COERCE5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , , } [[TMP5]], [[V_TUPLE_COERCE6]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , , , , , , } [[TMP6]], [[V_TUPLE_COERCE7]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 0 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 1 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 2 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 4 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 5 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 6 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , } [[TMP7]], 7 +// CHECK-RV64-NEXT: call void @llvm.riscv.th.vsseg8e.mask.nxv8i8.i64( [[TMP8]], [[TMP9]], [[TMP10]], [[TMP11]], [[TMP12]], [[TMP13]], [[TMP14]], [[TMP15]], ptr [[BASE]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_th_vsseg8e8_v_u8m1x8_m(vbool8_t mask, uint8_t *base, vuint8m1x8_t v_tuple, size_t vl) { + return __riscv_vsseg8e8_v_u8m1x8_m(mask, base, v_tuple, vl); +} +