From 181198650e385812cddbf2ce8fff0115e8d46edf Mon Sep 17 00:00:00 2001 From: Min M Xu Date: Thu, 23 May 2024 21:21:44 -0400 Subject: [PATCH] Enable test config of Selective IDE for Configuration Request Signed-off-by: Min Xu --- teeio-validator/include/ide_test_config.h | 6 + teeio-validator/include/utils.h | 2 + .../teeio_validator/CMakeLists.txt | 1 + teeio-validator/teeio_validator/ide_test.c | 7 +- teeio-validator/teeio_validator/pci_ide.c | 48 ++++++ .../test_config_sel_ide_for_cfg_req.c | 140 ++++++++++++++++++ teeio-validator/teeio_validator/utils.c | 16 +- 7 files changed, 218 insertions(+), 2 deletions(-) create mode 100644 teeio-validator/teeio_validator/test_config/test_config_sel_ide_for_cfg_req.c diff --git a/teeio-validator/include/ide_test_config.h b/teeio-validator/include/ide_test_config.h index c0f6af1..24c8ce8 100644 --- a/teeio-validator/include/ide_test_config.h +++ b/teeio-validator/include/ide_test_config.h @@ -39,4 +39,10 @@ bool test_config_pcrc_disable_sel_link(void *test_context); bool test_config_pcrc_support_sel_link(void *test_context); bool test_config_pcrc_check_sel_link(void *test_context); +// seleceive ide for configuration request +bool test_config_sel_ide_for_cfg_req_enable(void *test_context); +bool test_config_sel_ide_for_cfg_req_disable(void *test_context); +bool test_config_sel_ide_for_cfg_req_support(void *test_context); +bool test_config_sel_ide_for_cfg_req_check(void *test_context); + #endif diff --git a/teeio-validator/include/utils.h b/teeio-validator/include/utils.h index 1257d57..58422c4 100644 --- a/teeio-validator/include/utils.h +++ b/teeio-validator/include/utils.h @@ -85,4 +85,6 @@ void dump_hex_array(uint8_t* data, int size); **/ extern void libspdm_sleep(uint64_t microseconds); +TEST_IDE_TYPE map_top_type_to_ide_type(IDE_TEST_TOPOLOGY_TYPE top_type); + #endif diff --git a/teeio-validator/teeio_validator/CMakeLists.txt b/teeio-validator/teeio_validator/CMakeLists.txt index de9758b..7e8f69b 100644 --- a/teeio-validator/teeio_validator/CMakeLists.txt +++ b/teeio-validator/teeio_validator/CMakeLists.txt @@ -53,6 +53,7 @@ SET(src_teeio_validator test_config/test_config_common.c test_config/test_config_pcrc.c test_config/test_config_default.c + test_config/test_config_sel_ide_for_cfg_req.c ## test groups test_group/test_group.c scan_pci.c diff --git a/teeio-validator/teeio_validator/ide_test.c b/teeio-validator/teeio_validator/ide_test.c index cad0ce0..ff67497 100644 --- a/teeio-validator/teeio_validator/ide_test.c +++ b/teeio-validator/teeio_validator/ide_test.c @@ -89,7 +89,12 @@ ide_test_config_funcs_t m_config_funcs[IDE_TEST_TOPOLOGY_TYPE_NUM][IDE_TEST_CONF test_config_pcrc_check_sel }, {NULL, NULL, NULL, NULL}, // aggregation - {NULL, NULL, NULL, NULL}, // selective_ide_for_configuration + { // selective_ide for configuration request + test_config_sel_ide_for_cfg_req_enable, + test_config_sel_ide_for_cfg_req_disable, + test_config_sel_ide_for_cfg_req_support, + test_config_sel_ide_for_cfg_req_check + }, {NULL, NULL, NULL, NULL} // tee_limited_stream }, { // link_ide diff --git a/teeio-validator/teeio_validator/pci_ide.c b/teeio-validator/teeio_validator/pci_ide.c index f401963..6ed0bda 100644 --- a/teeio-validator/teeio_validator/pci_ide.c +++ b/teeio-validator/teeio_validator/pci_ide.c @@ -1005,6 +1005,54 @@ bool set_pcrc_in_ecap( return true; } +/** + * Set Selective IDE for Configuration Req (bit9) in ide_stream ctrl +*/ +bool set_sel_ide_for_cfg_req_in_ecap( + int fd, + TEST_IDE_TYPE ide_type, + uint8_t ide_id, + uint32_t ide_ecap_offset, + bool enable +) +{ + uint32_t offset = get_ide_reg_block_offset(fd, ide_type, ide_id, ide_ecap_offset); + + // For sel_ide, ide_ctrl is preceded by ide_cap. + if(ide_type == TEST_IDE_TYPE_SEL_IDE) { + offset += 4; + } + PCIE_SEL_IDE_STREAM_CTRL ide_stream_ctrl = {.raw = 0}; + ide_stream_ctrl.raw = device_pci_read_32(offset, fd); + + ide_stream_ctrl.cfg_sel_ide = enable ? 1 : 0; + device_pci_write_32(offset, ide_stream_ctrl.raw, fd); + + return true; +} + +/** + * read ide_stream_ctrl register in ecap +*/ +uint32_t read_ide_stream_ctrl_in_ecap( + int fd, + TEST_IDE_TYPE ide_type, + uint8_t ide_id, + uint32_t ide_ecap_offset +) +{ + uint32_t offset = get_ide_reg_block_offset(fd, ide_type, ide_id, ide_ecap_offset); + + // For sel_ide, ide_stream_ctrl is preceded by ide_cap. + if(ide_type == TEST_IDE_TYPE_SEL_IDE) { + offset += 4; + } + uint32_t ide_stream_ctrl = device_pci_read_32(offset, fd); + + return ide_stream_ctrl; +} + + // setup the ide ecap regs // IDE Extended Capability is defined in [PCI-SIG IDE] Sec 7.9.99 bool setup_ide_ecap_regs ( diff --git a/teeio-validator/teeio_validator/test_config/test_config_sel_ide_for_cfg_req.c b/teeio-validator/teeio_validator/test_config/test_config_sel_ide_for_cfg_req.c new file mode 100644 index 0000000..10793f1 --- /dev/null +++ b/teeio-validator/teeio_validator/test_config/test_config_sel_ide_for_cfg_req.c @@ -0,0 +1,140 @@ +/** + * Copyright Notice: + * Copyright 2023-2024 Intel. All rights reserved. + * License: BSD 3-Clause License. + **/ + +#include +#include + +#include "hal/base.h" +#include "hal/library/debuglib.h" +#include "ide_test.h" +#include "utils.h" +#include "teeio_debug.h" + +extern const char *m_ide_type_name[]; +const char* m_config_name = "Selective IDE for Configuration Request"; + +bool set_sel_ide_for_cfg_req_in_ecap( + int fd, + TEST_IDE_TYPE ide_type, + uint8_t ide_id, + uint32_t ide_ecap_offset, + bool enable +); + +uint32_t read_ide_stream_ctrl_in_ecap( + int fd, + TEST_IDE_TYPE ide_type, + uint8_t ide_id, + uint32_t ide_ecap_offset +); + +/** + * Enable/Disable Selective_IDE for Configuration +*/ +static bool test_config_set_sel_ide_for_cfg_req(void* test_context, bool enable) +{ + ide_common_test_config_context_t *config_context = (ide_common_test_config_context_t *)test_context; + TEEIO_ASSERT(config_context->signature == CONFIG_CONTEXT_SIGNATURE); + + ide_common_test_group_context_t *group_context = config_context->group_context; + TEEIO_ASSERT(group_context->signature == GROUP_CONTEXT_SIGNATURE); + + TEST_IDE_TYPE ide_type = map_top_type_to_ide_type(group_context->top->type); + + // enable cfg_sel_ide bit in upper port and lower port + ide_common_test_port_context_t* port_context = &group_context->upper_port; + set_sel_ide_for_cfg_req_in_ecap(port_context->cfg_space_fd, + ide_type, + port_context->ide_id, + port_context->ecap_offset, + enable); + + port_context = &group_context->lower_port; + set_sel_ide_for_cfg_req_in_ecap(port_context->cfg_space_fd, + ide_type, + port_context->ide_id, + port_context->ecap_offset, + enable); + + return true; +} + +/** + * Check if Selective_IDE for Configuration Request is supported. +*/ +static bool test_config_check_sel_ide_for_cfg_req_support(void* test_context) +{ + ide_common_test_config_context_t *config_context = (ide_common_test_config_context_t *)test_context; + TEEIO_ASSERT(config_context->signature == CONFIG_CONTEXT_SIGNATURE); + + ide_common_test_group_context_t *group_context = config_context->group_context; + TEEIO_ASSERT(group_context->signature == GROUP_CONTEXT_SIGNATURE); + + TEST_IDE_TYPE ide_type = map_top_type_to_ide_type(group_context->top->type); + if(ide_type != TEST_IDE_TYPE_SEL_IDE) { + TEEIO_DEBUG((TEEIO_DEBUG_ERROR, "\"%s\" is not avaible in %s\n", m_config_name, m_ide_type_name[ide_type])); + return false; + } + + PCIE_IDE_CAP *upper_cap = &group_context->upper_port.ide_cap; + PCIE_IDE_CAP *lower_cap = &group_context->lower_port.ide_cap; + bool supported = upper_cap->sel_ide_cfg_req_supported && lower_cap->sel_ide_cfg_req_supported; + TEEIO_DEBUG((TEEIO_DEBUG_INFO, "%s is %s.\n", m_config_name, supported ? "supported" : "NOT supported")); + return supported; +} + +// selective_ide test sel_ide_for_cfg_req +bool test_config_sel_ide_for_cfg_req_enable(void *test_context) +{ + return test_config_set_sel_ide_for_cfg_req(test_context, true); +} + +bool test_config_sel_ide_for_cfg_req_disable(void *test_context) +{ + return test_config_set_sel_ide_for_cfg_req(test_context, false); +} + +bool test_config_sel_ide_for_cfg_req_support(void *test_context) +{ + return test_config_check_sel_ide_for_cfg_req_support(test_context); +} + +bool test_config_sel_ide_for_cfg_req_check(void *test_context) +{ + ide_common_test_config_context_t *config_context = (ide_common_test_config_context_t *)test_context; + TEEIO_ASSERT(config_context->signature == CONFIG_CONTEXT_SIGNATURE); + + ide_common_test_group_context_t *group_context = config_context->group_context; + TEEIO_ASSERT(group_context->signature == GROUP_CONTEXT_SIGNATURE); + + TEST_IDE_TYPE ide_type = map_top_type_to_ide_type(group_context->top->type); + TEEIO_ASSERT(ide_type == TEST_IDE_TYPE_SEL_IDE); + + ide_common_test_port_context_t* port_context = &group_context->upper_port; + uint32_t data1 =read_ide_stream_ctrl_in_ecap(port_context->cfg_space_fd, + ide_type, + port_context->ide_id, + port_context->ecap_offset); + + port_context = &group_context->lower_port; + uint32_t data2 = read_ide_stream_ctrl_in_ecap(port_context->cfg_space_fd, + ide_type, + port_context->ide_id, + port_context->ecap_offset); + + TEEIO_DEBUG((TEEIO_DEBUG_INFO, "Read ide_stream_ctrl : rootport = 0x%08x, dev = 0x%08x\n", data1, data2)); + + PCIE_SEL_IDE_STREAM_CTRL rp_ide_stream_ctrl = {.raw = data1}; + PCIE_SEL_IDE_STREAM_CTRL dev_ide_stream_ctrl = {.raw = data2}; + bool pass = rp_ide_stream_ctrl.cfg_sel_ide == 1 && dev_ide_stream_ctrl.cfg_sel_ide; + if(pass) { + TEEIO_DEBUG((TEEIO_DEBUG_INFO, "Check %s pass\n", m_config_name)); + } else { + TEEIO_DEBUG((TEEIO_DEBUG_ERROR, "Check %s failed\n", m_config_name)); + } + + return pass; +} diff --git a/teeio-validator/teeio_validator/utils.c b/teeio-validator/teeio_validator/utils.c index 51da91e..416dc34 100644 --- a/teeio-validator/teeio_validator/utils.c +++ b/teeio-validator/teeio_validator/utils.c @@ -865,4 +865,18 @@ void dump_hex_array(uint8_t* data, int size) dump_hex_array_to_str(data + i * COLUME_SIZE, left, one_line_buffer, COLUME_SIZE * 3); TEEIO_DEBUG((TEEIO_DEBUG_INFO, "%04x: %s\n", i * COLUME_SIZE, one_line_buffer)); } -} \ No newline at end of file +} + +TEST_IDE_TYPE map_top_type_to_ide_type(IDE_TEST_TOPOLOGY_TYPE top_type) +{ + TEST_IDE_TYPE ide_type = TEST_IDE_TYPE_SEL_IDE; + + if(top_type == IDE_TEST_TOPOLOGY_TYPE_LINK_IDE) { + ide_type = TEST_IDE_TYPE_LNK_IDE; + } else if (top_type == IDE_TEST_TOPOLOGY_TYPE_SEL_LINK_IDE){ + NOT_IMPLEMENTED("selective_and_link_ide topology"); + ide_type = TEST_IDE_TYPE_NA; + } + + return ide_type; +}