From 2f0efe35f7486d2e7f5393086369cf8623c06218 Mon Sep 17 00:00:00 2001 From: Min M Xu Date: Wed, 12 Jun 2024 04:26:05 -0400 Subject: [PATCH 01/11] Add CXL spec definition Based on Compute Express Link (CXL) Spec, August 2023, Revision 3.1 Signed-off-by: Min Xu --- teeio-validator/include/cxl.h | 239 ++++++++++++++++++++++++++++++++++ 1 file changed, 239 insertions(+) create mode 100644 teeio-validator/include/cxl.h diff --git a/teeio-validator/include/cxl.h b/teeio-validator/include/cxl.h new file mode 100644 index 0000000..54c2929 --- /dev/null +++ b/teeio-validator/include/cxl.h @@ -0,0 +1,239 @@ +/** + * Copyright Notice: + * Copyright 2023-2024 Intel. All rights reserved. + * License: BSD 3-Clause License. + **/ + +#ifndef __CXL_H__ +#define __CXL_H__ + +#include +#include "pcie.h" +// +// Compute Express Link (CXL) Spec +// August 2023, Revision 3.1 +// + +#pragma pack(1) + +typedef union { + struct { + uint16_t vendor_id; + uint16_t revision:4; + uint16_t length:12; + }; + uint32_t raw; +} CXL_DVS_HEADER1; + +typedef union { + struct { + uint16_t id; + }; + uint16_t raw; +} CXL_DVS_HEADER2; + +typedef union { + struct { + uint8_t cache_capable:1; + uint8_t io_capable:1; + uint8_t mem_capable:1; + uint8_t mem_hwinit_mode:1; + uint8_t hdm_count:2; + uint8_t cache_writeback_and_invalidate_capable:1; + uint8_t cxl_reset_capable:1; + + uint8_t cxl_reset_timeout:3; + uint8_t cxl_mem_clr_capable:1; + uint8_t tsp_capable:1; + uint8_t multiple_logical_device:1; + uint8_t viral_capable:1; + uint8_t pm_init_completion_reporting_capable:1; + }; + uint16_t raw; +} CXL_CAPABILITY; + +typedef union { + struct { + uint8_t cache_enable:1; + uint8_t io_enable:1; + uint8_t mem_enable:1; + uint8_t cache_sf_coverage:5; + + uint8_t cache_sf_granularity:3; + uint8_t cache_clean_eviction:1; + uint8_t direct_p2p_mem_enable:1; + uint8_t rsvd0:1; + uint8_t viral_enable:1; + uint8_t rsvd1:1; + }; + uint16_t raw; +} CXL_CONTROL; + +typedef union { + struct { + uint16_t rsvd0:14; + uint16_t viral_status:1; + uint16_t rsvd1:1; + }; + uint16_t raw; +} CXL_STATUS; + +typedef union { + struct { + uint16_t disable_caching:1; + uint16_t initiate_cache_write_back_and_invalidation:1; + uint16_t initiate_cxl_reset:1; + uint16_t cxl_reset_mem_clr_enable:1; + uint16_t desired_volatile_hdm_state_after_hot_reset:1; + uint16_t modified_completion_enable:1; + uint16_t rsvd:10; + }; + uint16_t raw; +} CXL_CONTROL2; + +typedef union { + struct { + uint16_t cache_invalid:1; + uint16_t cxl_reset_complete:1; + uint16_t cxl_reset_error:1; + uint16_t volatile_hdm_preservation_error:1; + uint16_t rsvd:11; + uint16_t power_management_initialization_complete:1; + }; + uint16_t raw; +} CXL_STATUS2; + +typedef union { + struct { + uint16_t config_lock:15; + uint16_t rsvd:1; + }; + uint16_t raw; +} CXL_LOCK; + +typedef union { + struct { + uint8_t cache_size_unit:4; + uint8_t fallback_capability:2; + uint8_t modified_completion_capable:1; + uint8_t no_clean_writeback:1; + + uint8_t cache_size; + }; + uint16_t raw; +} CXL_CAPABILITY2; + +typedef union { + struct { + uint32_t memory_size_high; + }; + uint32_t raw; +} CXL_RANGE_SIZE_HIGH; + +typedef union { + struct { + uint8_t memory_info_valid:1; + uint8_t memory_active:1; + uint8_t media_type:3; + uint8_t memory_class:3; + + uint8_t desired_interleave:5; + uint8_t memory_active_timeout:3; + + uint16_t memory_active_degraded:1; + uint16_t rsvd:11; + uint16_t memory_size_low:4; + }; + uint32_t raw; +} CXL_RANGE_SIZE_LOW; + +typedef union { + struct { + uint32_t memory_base_high; + }; + uint32_t raw; +} CXL_RANGE_BASE_HIGH; + +typedef union { + struct { + uint32_t rsvd:28; + uint32_t memory_base_low:4; + }; + uint32_t raw; +} CXL_RANGE_BASE_LOW; + +typedef union { + struct { + uint16_t default_volatile_hdm_state_after_cold_reset:1; + uint16_t default_volatile_hdm_state_after_warm_reset:1; + uint16_t default_volatile_hdm_state_after_hot_reset:1; + uint16_t volatile_hdm_state_after_hot_reset:1; + uint16_t direct_p2p_mem_capable:1; + uint16_t rsvd:11; + }; + uint16_t raw; +} CXL_CAPABILITY3; + +typedef struct { + CXL_RANGE_SIZE_HIGH high; + CXL_RANGE_SIZE_LOW low; +} CXL_RANGE_SIZE; + +typedef struct { + CXL_RANGE_BASE_HIGH high; + CXL_RANGE_BASE_LOW low; +} CXL_RANGE_BASE; + +// Figure 8-1 +typedef struct { + PCIE_CAP_ID ide_ecap; + CXL_DVS_HEADER1 header1; + CXL_DVS_HEADER2 header2; + CXL_CAPABILITY capability; + CXL_CONTROL control; + CXL_STATUS status; + CXL_CONTROL2 control2; + CXL_STATUS2 status2; + CXL_LOCK lock; + CXL_CAPABILITY2 capability2; + + CXL_RANGE_SIZE range1_size; + CXL_RANGE_BASE range1_base; + CXL_RANGE_SIZE range2_size; + CXL_RANGE_BASE range2_base; + + CXL_CAPABILITY3 capability3; + uint16_t rsvd; +} CXL_DVSEC; + +#pragma pack(0) + +typedef enum { + CXL_IDE_STREAM_DIRECTION_RX = 0, + CXL_IDE_STREAM_DIRECTION_TX, + CXL_IDE_STREAM_DIRECTION_NUM +} CXL_IDE_STREAM_DIRECTION ; + +#define CXL_DVS_HEADER1_OFFSET (sizeof(PCIE_CAP_ID)) +#define CXL_DVS_HEADER2_OFFSET (CXL_DVS_HEADER1_OFFSET + sizeof(CXL_DVS_HEADER1)) +#define CXL_CAPABILITY_OFFSET (CXL_DVS_HEADER2_OFFSET + sizeof(CXL_DVS_HEADER2)) +#define CXL_CONTROL_OFFSET (CXL_CAPABILITY_OFFSET + sizeof(CXL_CAPABILITY)) +#define CXL_STATUS_OFFSET (CXL_CONTROL_OFFSET + sizeof(CXL_CONTROL)) +#define CXL_CONTROL2_OFFSET (CXL_STATUS_OFFSET + sizeof(CXL_STATUS)) +#define CXL_STATUS2_OFFSET (CXL_CONTROL2_OFFSET + sizeof(CXL_CONTROL2)) +#define CXL_LOCK_OFFSET (CXL_STATUS2_OFFSET + sizeof(CXL_STATUS2)) +#define CXL_CAPABILITY2_OFFSET (CXL_LOCK_OFFSET + sizeof(CXL_LOCK)) + +#define CXL_RANGE1_SIZE_HIGH_OFFSET (CXL_CAPABILITY2_OFFSET + sizeof(CXL_CAPABILITY2)) +#define CXL_RANGE1_SIZE_LOW_OFFSET (CXL_RANGE1_SIZE_HIGH_OFFSET + sizeof(CXL_RANGE_SIZE_HIGH)) +#define CXL_RANGE1_BASE_HIGH_OFFSET (CXL_RANGE1_SIZE_LOW_OFFSET + sizeof(CXL_RANGE_SIZE_LOW)) +#define CXL_RANGE1_BASE_LOW_OFFSET (CXL_RANGE1_BASE_HIGH_OFFSET + sizeof(CXL_RANGE_BASE_HIGH)) + +#define CXL_RANGE2_SIZE_HIGH_OFFSET (CXL_RANGE1_BASE_LOW_OFFSET + sizeof(CXL_RANGE_BASE_LOW)) +#define CXL_RANGE2_SIZE_LOW_OFFSET (CXL_RANGE2_SIZE_HIGH_OFFSET + sizeof(CXL_RANGE_SIZE_HIGH)) +#define CXL_RANGE2_BASE_HIGH_OFFSET (CXL_RANGE2_SIZE_LOW_OFFSET + sizeof(CXL_RANGE_SIZE_LOW)) +#define CXL_RANGE2_BASE_LOW_OFFSET (CXL_RANGE2_BASE_HIGH_OFFSET + sizeof(CXL_RANGE_BASE_HIGH)) + +#define CXL_CAPABILITY3_OFFSET (CXL_RANGE2_BASE_LOW_OFFSET + sizeof(CXL_RANGE_BASE_LOW)) + +#endif \ No newline at end of file From 78fadcd70c25cd072c2f2969d30358e109f89fd0 Mon Sep 17 00:00:00 2001 From: Min M Xu Date: Thu, 13 Jun 2024 04:09:52 -0400 Subject: [PATCH 02/11] Add CXL.memcache Key Configuration Registers definition It is based on Root Complex IDE Programming Guide April 2023, Revision 1.01. Signed-off-by: Min Xu --- teeio-validator/include/intel_keyp.h | 67 ++++++++++++++++++++++++++++ 1 file changed, 67 insertions(+) diff --git a/teeio-validator/include/intel_keyp.h b/teeio-validator/include/intel_keyp.h index ed62049..1ee27a5 100644 --- a/teeio-validator/include/intel_keyp.h +++ b/teeio-validator/include/intel_keyp.h @@ -13,6 +13,18 @@ // Below defitions are based on Root Complex IDE Programming Guide +// Table 2-2. Protocol Type +typedef enum { + INTEL_KEYP_PROTOCOL_TYPE_PCIE_CXLIO = 1, + INTEL_KEYP_PROTOCOL_TYPE_CXL_MEMCACHE = 2 +} INTEL_KEYP_PROTOCOL_TYPE; + +#define CXL_LINK_ENC_KEYS_SLOT_NUM 4 + +// +// PCIE & CXL.IO IDE +// + // Table 2-1. Key Programming Table Reporting Structure typedef struct { uint8_t signature[4]; @@ -192,6 +204,61 @@ typedef union uint32_t dwords[PCIE_IDE_IV_SIZE_IN_DWORDS]; } INTEL_KEYP_IV_SLOT; +// +// CXL.memcache IDE +// + +typedef union { + struct { + uint32_t link_enc_enable:1; + uint32_t mode:5; + uint32_t algorithm:6; + uint32_t rsvd:20; + }; + uint32_t raw; +} INTEL_KEYP_CXL_LINK_ENC_GLOBAL_CONFIG; + +typedef union { + struct { + uint32_t start_trigger:1; + uint32_t rxkey_valid:1; + uint32_t txkey_valid:1; + uint32_t rsvd:29; + }; + uint32_t raw; +} INTEL_KEYP_CXL_LINK_ENC_CONTROL; + +typedef struct { + uint64_t link_enc_key; +} INTEL_KEYP_CXL_TXRX_ENCRYPTION_KEY; + +typedef struct { + uint64_t iv; +} INTEL_KEYP_CXL_TXRX_IV; + +typedef struct { + INTEL_KEYP_CXL_TXRX_ENCRYPTION_KEY keys[CXL_LINK_ENC_KEYS_SLOT_NUM]; +} INTEL_KEYP_CXL_TXRX_ENC_KEYS_BLOCK; + +// Figure 2-5 +typedef struct { + INTEL_KEYP_CXL_LINK_ENC_GLOBAL_CONFIG link_enc_global_config; + uint32_t rsvd0; + INTEL_KEYP_CXL_LINK_ENC_CONTROL link_enc_control; + uint32_t rsvd1; + INTEL_KEYP_CXL_TXRX_ENC_KEYS_BLOCK tx_enc_keys; + INTEL_KEYP_CXL_TXRX_IV tx_iv; + INTEL_KEYP_CXL_TXRX_ENC_KEYS_BLOCK rx_enc_keys; + INTEL_KEYP_CXL_TXRX_IV rx_iv; +} INTEL_KEYP_CXL_ROOT_COMPLEX_KCBAR; + #pragma pack() +#define CXL_LINK_ENC_GLOBAL_CONFIG_OFFSET 0 +#define CXL_LINK_ENC_CONTROL_OFFSET (CXL_LINK_ENC_GLOBAL_CONFIG_OFFSET + sizeof(INTEL_KEYP_CXL_LINK_ENC_GLOBAL_CONFIG) + sizeof(uint32_t)) +#define CXL_TX_ENC_KEYS_BLOCK_OFFSET (CXL_LINK_ENC_CONTROL_OFFSET + sizeof(INTEL_KEYP_CXL_LINK_ENC_CONTROL) + sizeof(uint32_t)) +#define CXL_TX_IV_OFFSET (CXL_TX_ENC_KEYS_BLOCK_OFFSET + sizeof(INTEL_KEYP_CXL_TXRX_ENC_KEYS_BLOCK)) +#define CXL_RX_ENC_KEYS_BLOCK_OFFSET (CXL_TX_IV_OFFSET + sizeof(INTEL_KEYP_CXL_TXRX_IV)) +#define CXL_RX_IV_OFFSET (CXL_RX_ENC_KEYS_BLOCK_OFFSET + sizeof(INTEL_KEYP_CXL_TXRX_ENC_KEYS_BLOCK)) + #endif \ No newline at end of file From 75d3fd78e943b81ac8bbc5afb4351aa0299f1de8 Mon Sep 17 00:00:00 2001 From: Min M Xu Date: Sun, 16 Jun 2024 21:12:09 -0400 Subject: [PATCH 03/11] Add cxl_ide_lib Signed-off-by: Min Xu --- teeio-validator/include/cxl_ide_lib.h | 74 +++ .../library/cxl_ide_lib/CMakeLists.txt | 33 ++ teeio-validator/library/cxl_ide_lib/cxl_ide.c | 444 ++++++++++++++++++ 3 files changed, 551 insertions(+) create mode 100644 teeio-validator/include/cxl_ide_lib.h create mode 100644 teeio-validator/library/cxl_ide_lib/CMakeLists.txt create mode 100644 teeio-validator/library/cxl_ide_lib/cxl_ide.c diff --git a/teeio-validator/include/cxl_ide_lib.h b/teeio-validator/include/cxl_ide_lib.h new file mode 100644 index 0000000..b96b15d --- /dev/null +++ b/teeio-validator/include/cxl_ide_lib.h @@ -0,0 +1,74 @@ +/** + * Copyright Notice: + * Copyright 2024 Intel. All rights reserved. + * License: BSD 3-Clause License. + **/ + +#ifndef __CXL_IDE_LIB_H__ +#define __CXL_IDE_LIB_H__ + +#include "ide_test.h" + +/** + * Initialize rootcomplex port + * root_port and upper_port is the same port + */ +bool cxl_init_root_port(ide_common_test_group_context_t *group_context); + +/* + * Open rootcomplex port + */ +bool cxl_open_root_port(ide_common_test_port_context_t *port_context); + +/* + * Close rootcomplex port + */ +bool cxl_close_root_port(ide_common_test_group_context_t *group_context); + +/* + * Initialize device port + */ +bool cxl_init_dev_port(ide_common_test_group_context_t *group_context); + +/* + * Open device port + */ +bool cxl_open_dev_port(ide_common_test_port_context_t *port_context); + +/* + * Close device port + */ +bool cxl_close_dev_port(ide_common_test_port_context_t *port_context, IDE_TEST_TOPOLOGY_TYPE top_type); + +/** + * enable/disable cache_enable bit in CXL_CONTROL + */ +void cxl_cfg_cache_enable(int fd, uint32_t ecap_offset, bool enable); + +/** + * enable/disable mem_enable bit in CXL_CONTROL + */ +void cxl_cfg_mem_enable(int fd, uint32_t ecap_offset, bool enable); + +void cxl_cfg_rp_link_enc_key_iv( + INTEL_KEYP_CXL_ROOT_COMPLEX_KCBAR *kcbar_ptr, + CXL_IDE_STREAM_DIRECTION direction, // RX TX + const uint8_t key_slot, // key 0, 1, 2, 3 + uint8_t* key, uint32_t key_size, // key + uint8_t* iv, uint32_t iv_size // iv vals + ); + +void cxl_cfg_rp_txrx_key_valid( + INTEL_KEYP_CXL_ROOT_COMPLEX_KCBAR *kcbar_ptr, + bool valid + ); + +void cxl_cfg_rp_start_trigger( + INTEL_KEYP_CXL_ROOT_COMPLEX_KCBAR *kcbar_ptr, + bool start + ); + +void cxl_dump_kcbar(INTEL_KEYP_CXL_ROOT_COMPLEX_KCBAR *kcbar_ptr); + +void cxl_dump_ecap(int fd, uint32_t ecap_offset); +#endif diff --git a/teeio-validator/library/cxl_ide_lib/CMakeLists.txt b/teeio-validator/library/cxl_ide_lib/CMakeLists.txt new file mode 100644 index 0000000..dafda02 --- /dev/null +++ b/teeio-validator/library/cxl_ide_lib/CMakeLists.txt @@ -0,0 +1,33 @@ +cmake_minimum_required(VERSION 2.8.12) + +ADD_COMPILE_OPTIONS(-Wno-unused-result -Werror=format-overflow -Werror) + +if(CMAKE_BUILD_TYPE STREQUAL "Release") + ADD_COMPILE_OPTIONS(-Wno-error=unused-variable -Wno-error=unused-but-set-variable) +endif() + +SET(BUILD_SHARED_LIBS OFF) +SET(CMAKE_EXE_LINKER_FLAGS "-static") + +INCLUDE_DIRECTORIES(${SPDM_DEVICE_DIR}/include + ${LIBSPDM_DIR}/os_stub/spdm_device_secret_lib_sample + ${LIBSPDM_DIR}/include + ${LIBSPDM_DIR}/os_stub/include + ${LIBSPDM_DIR}/os_stub + ${SPDM_EMU_DIR}/include + ${PROJECT_SOURCE_DIR}/include + ${TEEIO_VALIDATOR_LIB_DIR}/cxl_ide_lib/include +) + +SET(src_cxl_ide_lib + cxl_ide.c +) + +SET(cxl_ide_lib_LIBRARY + debuglib + helperlib + pcie_ide_lib +) + +ADD_LIBRARY(cxl_ide_lib STATIC ${src_cxl_ide_lib}) +TARGET_LINK_LIBRARIES(cxl_ide_lib ${cxl_ide_lib_LIBRARY}) diff --git a/teeio-validator/library/cxl_ide_lib/cxl_ide.c b/teeio-validator/library/cxl_ide_lib/cxl_ide.c new file mode 100644 index 0000000..0d29d13 --- /dev/null +++ b/teeio-validator/library/cxl_ide_lib/cxl_ide.c @@ -0,0 +1,444 @@ +/** + * Copyright Notice: + * Copyright 2023-2024 Intel. All rights reserved. + * License: BSD 3-Clause License. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "teeio_validator.h" +#include "hal/library/debuglib.h" +#include "teeio_debug.h" +#include "ide_test.h" +#include "pcie_ide_lib.h" +#include "cxl_ide_lib.h" + +extern uint32_t g_doe_extended_offset; +extern uint32_t g_ide_extended_offset; +extern uint32_t g_aer_extended_offset; +extern int m_dev_fp; + +/** + * Initialize rootcomplex port + * root_port and upper_port is the same port + */ +bool cxl_init_root_port(ide_common_test_group_context_t *group_context) +{ + TEEIO_ASSERT(group_context != NULL); + TEEIO_ASSERT(group_context->top != NULL); + TEEIO_ASSERT(group_context->top->type == IDE_TEST_TOPOLOGY_TYPE_SEL_IDE); + + ide_common_test_port_context_t *port_context = &group_context->upper_port; + TEEIO_ASSERT(port_context != NULL); + TEEIO_ASSERT(port_context->port != NULL); + TEEIO_ASSERT(port_context->port->port_type == IDE_PORT_TYPE_ROOTPORT); + TEEIO_ASSERT(group_context->upper_port.port->id == group_context->root_port.port->id); + + if(!cxl_open_root_port(port_context)) { + return false; + } + + return true; +} + +/* + * Open rootcomplex port + */ +bool cxl_open_root_port(ide_common_test_port_context_t *port_context) +{ + char str[MAX_NAME_LENGTH] = {0}; + + IDE_PORT *port = port_context->port; + TEEIO_ASSERT(port->port_type == IDE_PORT_TYPE_ROOTPORT); + + // open configuration space and get ecap offset + int fd = open_configuration_space(port->bdf); + if (fd == -1) { + return false; + } + + port_context->cfg_space_fd = fd; + sprintf(str, "cxl.host : %s", port->bdf); + set_deivce_info(fd, str); + + uint32_t ecap_offset = get_extended_cap_offset(fd, PCI_IDE_EXT_CAPABILITY_ID); + if (ecap_offset == 0) + { + TEEIO_DEBUG((TEEIO_DEBUG_ERROR, "ECAP Offset of CXL IDE is NOT found\n")); + goto InitRootPortFail; + } + else + { + TEEIO_DEBUG((TEEIO_DEBUG_INFO, "ECAP Offset of CXL IDE: 0x%016x\n", ecap_offset)); + } + + port_context->ecap_offset = ecap_offset; + + // parse KEYP table and map the kcbar to user space + if (!parse_keyp_table(port_context, INTEL_KEYP_PROTOCOL_TYPE_CXL_MEMCACHE)) + { + TEEIO_DEBUG((TEEIO_DEBUG_ERROR, "parse_keyp_table failed.\n")); + goto InitRootPortFail; + } + + // store the Link_Enc_Global_Config in kcbar and cxl_cap/cxl_cap2/cxl_cap3 in ecap(@configuration space) + INTEL_KEYP_CXL_ROOT_COMPLEX_KCBAR *kcbar = (INTEL_KEYP_CXL_ROOT_COMPLEX_KCBAR *)port_context->mapped_kcbar_addr; + CXL_PRIV_DATA * cxl_data = &port_context->priv_data.cxl; + cxl_data->link_enc_global_config.raw = mmio_read_reg32(&kcbar->link_enc_global_config); + + // check CXL_DVS_HEADER1 CXL_DVS_HEADER2 + CXL_DVS_HEADER1 header1 = {.raw = device_pci_read_32(ecap_offset + CXL_DVS_HEADER1_OFFSET, fd)}; + CXL_DVS_HEADER2 header2 = {.raw = device_pci_read_16(ecap_offset + CXL_DVS_HEADER2_OFFSET, fd)}; + TEEIO_DEBUG((TEEIO_DEBUG_INFO, "CXL Rootport (%s) header1=0x%08x, header2=0x%04x\n", port->bdf, header1.raw, header2.raw)); + + // read and save cap/cap2/cap3 + cxl_data->cap.raw = device_pci_read_16(ecap_offset + CXL_CAPABILITY_OFFSET, fd); + cxl_data->cap2.raw = device_pci_read_16(ecap_offset + CXL_CAPABILITY2_OFFSET, fd); + cxl_data->cap3.raw = device_pci_read_16(ecap_offset + CXL_CAPABILITY3_OFFSET, fd); + TEEIO_DEBUG((TEEIO_DEBUG_INFO, "CXL Rootport (%s) cap=0x%04x, cap2=0x%04x, cap3=0x%04x\n", port->bdf, cxl_data->cap.raw, cxl_data->cap2.raw, cxl_data->cap3.raw)); + + return true; + +InitRootPortFail: + close(fd); + unset_device_info(fd); + return false; +} + +bool cxl_reset_ecap_registers(ide_common_test_port_context_t *port_context) +{ + return true; +} + +bool cxl_reset_kcbar_registers(ide_common_test_port_context_t *port_context) +{ + return true; +} + +/* + * Close rootcomplex port + */ +bool cxl_close_root_port(ide_common_test_group_context_t *group_context) +{ + // clean Control Registers @ecap and KCBar corresponding registers + ide_common_test_port_context_t* port_context = &group_context->upper_port; + TEEIO_DEBUG((TEEIO_DEBUG_INFO, "close cxl rootport %s(%s)\n", port_context->port->port_name, port_context->port->bdf)); + + cxl_reset_ecap_registers(port_context); + cxl_reset_kcbar_registers(port_context); + + CXL_PRIV_DATA* cxl_data = &port_context->priv_data.cxl; + cxl_data->cap.raw = 0; + cxl_data->cap2.raw = 0; + cxl_data->cap3.raw = 0; + cxl_data->link_enc_global_config.raw = 0; + + if(group_context->upper_port.kcbar_fd > 0) { + unmap_kcbar_addr(group_context->upper_port.kcbar_fd, group_context->upper_port.mapped_kcbar_addr); + } + group_context->upper_port.kcbar_fd = 0; + group_context->upper_port.mapped_kcbar_addr = 0; + + if(group_context->upper_port.cfg_space_fd > 0) { + close(group_context->upper_port.cfg_space_fd); + unset_device_info(group_context->upper_port.cfg_space_fd); + } + group_context->upper_port.cfg_space_fd = 0; + + return true; +} + +/* + * Initialize device port + */ +bool cxl_init_dev_port(ide_common_test_group_context_t *group_context) +{ + TEEIO_ASSERT(group_context != NULL); + TEEIO_ASSERT(group_context->top != NULL); + + IDE_TEST_TOPOLOGY *top = group_context->top; + TEEIO_ASSERT(top->type == IDE_TEST_TOPOLOGY_TYPE_SEL_IDE); + TEEIO_ASSERT(top->ide_type == IDE_HW_TYPE_CXL_MEM); + + // IDE_TEST_TOPOLOGY_TYPE top_type = top->type; + + ide_common_test_port_context_t *port_context = &group_context->lower_port; + TEEIO_ASSERT(port_context != NULL); + + if(!cxl_open_dev_port(port_context)) { + return false; + } + + // prepare range registers? + + return true; + +// InitDevFailed: +// close(port_context->cfg_space_fd); +// unset_device_info(port_context->cfg_space_fd); +// return false; +} + +/* + * Open device port + */ +bool cxl_open_dev_port(ide_common_test_port_context_t *port_context) +{ + TEEIO_ASSERT(port_context != NULL); + IDE_PORT *port = port_context->port; + TEEIO_ASSERT(port != NULL); + TEEIO_ASSERT(port->port_type == IDE_PORT_TYPE_ENDPOINT); + + char str[MAX_NAME_LENGTH] = {0}; + + // open configuration space and get ecap offset + int fd = open_configuration_space(port->bdf); + if (fd == -1) + { + return false; + } + port_context->cfg_space_fd = fd; + sprintf(str, "cxl.dev : %s", port->bdf); + set_deivce_info(fd, str); + + uint32_t ecap_offset = get_extended_cap_offset(fd, PCI_IDE_EXT_CAPABILITY_ID); + if (ecap_offset == 0) + { + TEEIO_DEBUG((TEEIO_DEBUG_ERROR, "ECAP Offset of CXL IDE is NOT found\n")); + goto OpenDevFail; + } + else + { + TEEIO_DEBUG((TEEIO_DEBUG_INFO, "ECAP Offset of CXL IDE: 0x%016x\n", ecap_offset)); + } + port_context->ecap_offset = ecap_offset; + + // TODO + // m_dev_fp indicates the device ide card. It is used in doe_read_write.c. + // It will be removed later. + m_dev_fp = fd; + + // initialize pci doe + if(!init_pci_doe(fd)) { + goto OpenDevFail; + } + port_context->doe_offset = g_doe_extended_offset; + + // TODO + // check CXL_DVS_HEADER1 CXL_DVS_HEADER2 + CXL_DVS_HEADER1 header1 = {.raw = device_pci_read_32(ecap_offset + CXL_DVS_HEADER1_OFFSET, fd)}; + CXL_DVS_HEADER2 header2 = {.raw = device_pci_read_16(ecap_offset + CXL_DVS_HEADER2_OFFSET, fd)}; + TEEIO_DEBUG((TEEIO_DEBUG_INFO, "CXL Dev (%s) header1=0x%08x, header2=0x%04x\n", port->bdf, header1.raw, header2.raw)); + + // read and save cap/cap2/cap3 + CXL_PRIV_DATA* cxl_data = &port_context->priv_data.cxl; + + cxl_data->cap.raw = device_pci_read_16(ecap_offset + CXL_CAPABILITY_OFFSET, fd); + cxl_data->cap2.raw = device_pci_read_16(ecap_offset + CXL_CAPABILITY2_OFFSET, fd); + cxl_data->cap3.raw = device_pci_read_16(ecap_offset + CXL_CAPABILITY3_OFFSET, fd); + TEEIO_DEBUG((TEEIO_DEBUG_INFO, "CXL Dev (%s) cap=0x%04x, cap2=0x%04x, cap3=0x%04x\n", port->bdf, cxl_data->cap.raw, cxl_data->cap2.raw, cxl_data->cap3.raw)); + + return true; + +OpenDevFail: + close(fd); + unset_device_info(fd); + return false; +} + +/* + * Close device port + */ +bool cxl_close_dev_port(ide_common_test_port_context_t *port_context, IDE_TEST_TOPOLOGY_TYPE top_type) +{ + TEEIO_DEBUG((TEEIO_DEBUG_INFO, "close cxl dev %s(%s)\n", port_context->port->port_name, port_context->port->bdf)); + + cxl_reset_ecap_registers(port_context); + + CXL_PRIV_DATA* cxl_data = &port_context->priv_data.cxl; + cxl_data->cap.raw = 0; + cxl_data->cap2.raw = 0; + cxl_data->cap3.raw = 0; + cxl_data->link_enc_global_config.raw = 0; + + if(port_context->cfg_space_fd > 0) { + close(port_context->cfg_space_fd); + unset_device_info(port_context->cfg_space_fd); + } + port_context->cfg_space_fd = 0; + + m_dev_fp = 0; + return true; +} + +void cxl_cfg_rp_link_enc_key_iv( + INTEL_KEYP_CXL_ROOT_COMPLEX_KCBAR *kcbar_ptr, + CXL_IDE_STREAM_DIRECTION direction, // RX TX + const uint8_t key_slot, // key 0, 1, 2, 3 + uint8_t* key, uint32_t key_size, // key + uint8_t* iv, uint32_t iv_size // iv vals + ) +{ + INTEL_KEYP_CXL_TXRX_ENC_KEYS_BLOCK* enc_keys = NULL; + INTEL_KEYP_CXL_TXRX_IV* txrx_iv = NULL; + TEEIO_ASSERT(key_slot < CXL_LINK_ENC_KEYS_SLOT_NUM); + TEEIO_ASSERT(key_size == 32); + // TODO iv_size == 8? + // in cxl_ide_common_lib.h, + // uint32_t iv[3] + TEEIO_ASSERT(iv_size == 8); + + if(direction == CXL_IDE_STREAM_DIRECTION_RX) { + enc_keys = &kcbar_ptr->tx_enc_keys; + txrx_iv = &kcbar_ptr->tx_iv; + } else { + enc_keys = &kcbar_ptr->rx_enc_keys; + txrx_iv = &kcbar_ptr->tx_iv; + } + + reg_memcpy_dw(enc_keys, key_size, key, key_size); + reg_memcpy_dw(txrx_iv, iv_size, iv, iv_size); +} + +void cxl_cfg_cache_enable(int fd, uint32_t ecap_offset, bool enable) +{ + CXL_CONTROL ctrl = {.raw = device_pci_read_16(ecap_offset + CXL_CONTROL_OFFSET, fd)}; + TEEIO_DEBUG((TEEIO_DEBUG_INFO, "cxl_cfg_cache_enable(%d) cxl_control.raw=0x%04x\n", enable, ctrl.raw)); + ctrl.cache_enable = enable ? 1 : 0; + device_pci_write_16(ecap_offset + CXL_CONTROL_OFFSET, ctrl.raw, fd); +} + +void cxl_cfg_mem_enable(int fd, uint32_t ecap_offset, bool enable) +{ + CXL_CONTROL ctrl = {.raw = device_pci_read_16(ecap_offset + CXL_CONTROL_OFFSET, fd)}; + TEEIO_DEBUG((TEEIO_DEBUG_INFO, "cxl_cfg_mem_enable(%d) cxl_control.raw=0x%04x\n", enable, ctrl.raw)); + ctrl.mem_enable = enable ? 1 : 0; + device_pci_write_16(ecap_offset + CXL_CONTROL_OFFSET, ctrl.raw, fd); +} + +void cxl_cfg_rp_txrx_key_valid( + INTEL_KEYP_CXL_ROOT_COMPLEX_KCBAR *kcbar_ptr, + bool valid + ) +{ + INTEL_KEYP_CXL_LINK_ENC_CONTROL enc_ctrl = {.raw = mmio_read_reg32(&kcbar_ptr->link_enc_control)}; + TEEIO_DEBUG((TEEIO_DEBUG_INFO, "link_enc_control = 0x%08x\n", enc_ctrl.raw)); + + enc_ctrl.rxkey_valid = valid ? 1 : 0; + enc_ctrl.txkey_valid = valid ? 1 : 0; + + mmio_write_reg32(&kcbar_ptr->link_enc_control, enc_ctrl.raw); +} + +void cxl_cfg_rp_start_trigger( + INTEL_KEYP_CXL_ROOT_COMPLEX_KCBAR *kcbar_ptr, + bool start + ) +{ + INTEL_KEYP_CXL_LINK_ENC_CONTROL enc_ctrl = {.raw = mmio_read_reg32(&kcbar_ptr->link_enc_control)}; + TEEIO_DEBUG((TEEIO_DEBUG_INFO, "link_enc_control = 0x%08x\n", enc_ctrl.raw)); + + enc_ctrl.start_trigger = start ? 1 : 0; + + mmio_write_reg32(&kcbar_ptr->link_enc_control, enc_ctrl.raw); +} + + +void cxl_dump_kcbar(INTEL_KEYP_CXL_ROOT_COMPLEX_KCBAR *kcbar_ptr) +{ + TEEIO_PRINT(("Dump Key Programming Register Block:\n")); + INTEL_KEYP_CXL_LINK_ENC_GLOBAL_CONFIG global_config = {.raw = mmio_read_reg32(&kcbar_ptr->link_enc_global_config)}; + TEEIO_PRINT(("global_config : %08x\n", global_config.raw)); + TEEIO_PRINT((" link_enc_enable=%d, mode=%02x, algorithm=%02x\n", + global_config.link_enc_enable, global_config.mode, global_config.algorithm)); + + INTEL_KEYP_CXL_LINK_ENC_CONTROL enc_control = {.raw = mmio_read_reg32(&kcbar_ptr->link_enc_control)}; + TEEIO_PRINT(("enc_control : %08x\n", enc_control.raw)); + TEEIO_PRINT((" start_trigger=%d, rxkey_valid=%d, txkey_valid=%d\n", + enc_control.start_trigger, enc_control.rxkey_valid, enc_control.txkey_valid)); + +} + +void cxl_dump_ecap(int fd, uint32_t ecap_offset) +{ + uint32_t offset = ecap_offset; + TEEIO_PRINT(("CXL IDE Extended Cap:\n")); + + // refer to PCIE_IDE_ECAP + PCIE_CAP_ID cap_id = {.raw = device_pci_read_32(offset, fd)}; + TEEIO_PRINT((" cap_id : %08x\n", cap_id.raw)); + + // DVS_HEADER1 + offset += 4; + CXL_DVS_HEADER1 header1 = {.raw = device_pci_read_32(offset, fd)}; + TEEIO_PRINT((" dvs header1 : %08x\n", header1.raw)); + TEEIO_PRINT((" : vendor_id=%04x, revision=%02x, length=%04x\n", + header1.vendor_id, header1.revision, header1.length)); + + // DVS_HEADER2 + offset += 4; + CXL_DVS_HEADER2 header2 = {.raw = device_pci_read_16(offset, fd)}; + TEEIO_PRINT((" dvs header2 : %04x\n", header2.raw)); + TEEIO_PRINT((" : id=%04x\n", + header2.id)); + + // CXL_CAPABILITY + offset += 2; + CXL_CAPABILITY cap = {.raw = device_pci_read_16(offset, fd)}; + TEEIO_PRINT((" CXL Capability: %04x\n", cap)); + TEEIO_PRINT((" : cache_capable=%d, io_capable=%d, mem_capable=%d\n", + cap.cache_capable, cap.io_capable, cap.mem_capable)); + TEEIO_PRINT((" : mem_hwinit_mode=%d, hdm_count=%d, cache_writeback_and_invalidate_capable=%d, cxl_reset_capable=%d\n", + cap.mem_hwinit_mode, cap.hdm_count, cap.cache_writeback_and_invalidate_capable, cap.cxl_reset_capable)); + TEEIO_PRINT((" : cxl_reset_timeout=%d, cxl_mem_clr_capable=%d, tsp_capable=%d\n", + cap.cxl_reset_timeout, cap.cxl_mem_clr_capable, cap.tsp_capable)); + TEEIO_PRINT((" : multiple_logical_device=%d, viral_capable=%d, pm_init_capable=%d\n", + cap.multiple_logical_device, cap.viral_capable, cap.pm_init_completion_reporting_capable)); + + // CXL Control + offset += 2; + CXL_CONTROL control = {.raw = device_pci_read_16(offset, fd)}; + TEEIO_PRINT((" CXL Control : %04x\n", control)); + TEEIO_PRINT((" : cache_enable=%d, io_enable=%d, mem_enable=%d\n", + control.cache_enable, control.io_enable, control.mem_enable)); + TEEIO_PRINT((" : cache_sf_coverage=%d, cache_sf_granularity=%d, cache_clean_eviction=%d\n", + control.cache_sf_coverage, control.cache_sf_granularity, control.cache_clean_eviction)); + TEEIO_PRINT((" : direct_p2p_mem_enable=%d, viral_enable=%d\n", + control.direct_p2p_mem_enable, control.viral_enable)); + + // CXL Status + offset += 2; + CXL_STATUS status = {.raw = device_pci_read_16(offset, fd)}; + TEEIO_PRINT((" CXL Status : %04x\n", status)); + TEEIO_PRINT((" : viral_status=%d\n", + status.viral_status)); + + // CXL Control2 + offset += 2; + + // CXL Status2 + offset += 2; + + // CXL Lock + offset += 2; + + // CXL Capability2 + offset += 2; + + // Range1 + offset += 2; + + // Range2 + offset += 4 * 4; + + // CXL Capability3 + offset += 4 * 4; + +} \ No newline at end of file From e052c172b05d3b7e405d6ea68d89b8535478a779 Mon Sep 17 00:00:00 2001 From: Min M Xu Date: Sun, 16 Jun 2024 21:12:44 -0400 Subject: [PATCH 04/11] Add cxl_ide_test_lib Signed-off-by: Min Xu --- teeio-validator/include/cxl_ide_test_lib.h | 42 ++++ .../library/cxl_ide_test_lib/CMakeLists.txt | 55 ++++ .../test_case/ide_km_common.c | 234 ++++++++++++++++++ .../test_case/test_case_full.c | 121 +++++++++ .../test_config/test_config_default.c | 78 ++++++ .../cxl_ide_test_lib/test_group/test_group.c | 128 ++++++++++ 6 files changed, 658 insertions(+) create mode 100644 teeio-validator/include/cxl_ide_test_lib.h create mode 100644 teeio-validator/library/cxl_ide_test_lib/CMakeLists.txt create mode 100644 teeio-validator/library/cxl_ide_test_lib/test_case/ide_km_common.c create mode 100644 teeio-validator/library/cxl_ide_test_lib/test_case/test_case_full.c create mode 100644 teeio-validator/library/cxl_ide_test_lib/test_config/test_config_default.c create mode 100644 teeio-validator/library/cxl_ide_test_lib/test_group/test_group.c diff --git a/teeio-validator/include/cxl_ide_test_lib.h b/teeio-validator/include/cxl_ide_test_lib.h new file mode 100644 index 0000000..74a8442 --- /dev/null +++ b/teeio-validator/include/cxl_ide_test_lib.h @@ -0,0 +1,42 @@ +/** + * Copyright Notice: + * Copyright 2024 Intel. All rights reserved. + * License: BSD 3-Clause License. + **/ + +#ifndef __CXL_IDE_TEST_LIB_H__ +#define __CXL_IDE_TEST_LIB_H__ + +// cxl_ide_test_lib header file + +// +// CXL_IDE Test Cases +// +// Full case +bool cxl_ide_test_full_ide_stream_setup(void *test_context); +bool cxl_ide_test_full_ide_stream_run(void *test_context); +bool cxl_ide_test_full_ide_stream_teardown(void *test_context); + +// +// CXL_IDE Test Config +// +// common function +bool cxl_ide_test_config_enable_common(void *test_context); +bool cxl_ide_test_config_check_common(void *test_context); +bool cxl_ide_test_config_support_common(void *test_context); + +// default config +bool cxl_ide_test_config_default_enable(void *test_context); +bool cxl_ide_test_config_default_disable(void *test_context); +bool cxl_ide_test_config_default_support(void *test_context); +bool cxl_ide_test_config_default_check(void *test_context); + +// +// CXL_IDE Test Group +// + +// test group +bool cxl_ide_test_group_setup(void *test_context); +bool cxl_ide_test_group_teardown(void *test_context); + +#endif diff --git a/teeio-validator/library/cxl_ide_test_lib/CMakeLists.txt b/teeio-validator/library/cxl_ide_test_lib/CMakeLists.txt new file mode 100644 index 0000000..9a0f712 --- /dev/null +++ b/teeio-validator/library/cxl_ide_test_lib/CMakeLists.txt @@ -0,0 +1,55 @@ +cmake_minimum_required(VERSION 2.8.12) + +ADD_COMPILE_OPTIONS(-Wno-unused-result -Werror=format-overflow -Werror) + +if(CMAKE_BUILD_TYPE STREQUAL "Release") + ADD_COMPILE_OPTIONS(-Wno-error=unused-variable -Wno-error=unused-but-set-variable) +endif() + +SET(BUILD_SHARED_LIBS OFF) +SET(CMAKE_EXE_LINKER_FLAGS "-static") + +INCLUDE_DIRECTORIES(${SPDM_DEVICE_DIR}/include + ${LIBSPDM_DIR}/os_stub/spdm_device_secret_lib_sample + ${LIBSPDM_DIR}/include + ${LIBSPDM_DIR}/os_stub/include + ${LIBSPDM_DIR}/os_stub + ${SPDM_EMU_DIR}/include + ${TEEIO_VALIDATOR_LIB_DIR}/cxl_ide_test_lib/include +) + +SET(src_cxl_ide_test_lib + # test_case + test_case/ide_km_common.c + test_case/test_case_full.c + ## test configs + test_config/test_config_default.c + ## test groups + test_group/test_group.c +) + +SET(cxl_ide_test_lib_LIBRARY + memlib + debuglib + helperlib + spdmlib + cxl_ide_lib + spdm_requester_lib + spdm_common_lib + ${CRYPTO_LIB_PATHS} + rnglib + cryptlib_${CRYPTO} + malloclib + spdm_crypt_lib + spdm_crypt_ext_lib + spdm_secured_message_lib + spdm_transport_pcidoe_lib + spdm_device_secret_lib_sample + pci_doe_requester_lib + cxl_ide_km_requester_lib + # pci_tdisp_requester_lib + platform_lib +) + +ADD_LIBRARY(cxl_ide_test_lib STATIC ${src_cxl_ide_test_lib}) +TARGET_LINK_LIBRARIES(cxl_ide_test_lib ${cxl_ide_test_lib_LIBRARY}) diff --git a/teeio-validator/library/cxl_ide_test_lib/test_case/ide_km_common.c b/teeio-validator/library/cxl_ide_test_lib/test_case/ide_km_common.c new file mode 100644 index 0000000..a5bfd30 --- /dev/null +++ b/teeio-validator/library/cxl_ide_test_lib/test_case/ide_km_common.c @@ -0,0 +1,234 @@ +/** + * Copyright Notice: + * Copyright 2023-2024 Intel. All rights reserved. + * License: BSD 3-Clause License. + **/ + +#include +#include + +#include "assert.h" +#include "hal/base.h" +#include "hal/library/debuglib.h" + +#include "hal/library/memlib.h" +#include "library/spdm_transport_pcidoe_lib.h" +#include "library/cxl_ide_km_requester_lib.h" +#include "library/spdm_crypt_lib.h" +#include "ide_test.h" +#include "helperlib.h" +#include "teeio_debug.h" +#include "pcie_ide_lib.h" +#include "cxl_ide_lib.h" +#include "cxl_ide_test_lib.h" + +void cxl_dump_key_iv(cxl_ide_km_aes_256_gcm_key_buffer_t *key_buffer) +{ + TEEIO_DEBUG((TEEIO_DEBUG_INFO, "Key:\n")); + dump_hex_array((uint8_t *)key_buffer->key, sizeof(key_buffer->key)); + TEEIO_DEBUG((TEEIO_DEBUG_INFO, "IV:\n")); + dump_hex_array((uint8_t *)key_buffer->iv, sizeof(key_buffer->iv)); +} + +// setup cxl ide stream +bool cxl_stop_ide_stream(void *doe_context, void *spdm_context, + uint32_t *session_id, uint8_t *kcbar_addr, + uint8_t stream_id, + uint8_t port_index, + ide_common_test_port_context_t *upper_port, + ide_common_test_port_context_t *lower_port) +{ + libspdm_return_t status; + + TEEIO_DEBUG((TEEIO_DEBUG_INFO, "cxl_stop_ide_stream")); + + status = cxl_ide_km_key_set_stop(doe_context, spdm_context, + session_id, stream_id, + CXL_IDE_KM_KEY_DIRECTION_RX | CXL_IDE_KM_KEY_SUB_STREAM_CXL, + port_index); + if (LIBSPDM_STATUS_IS_ERROR(status)) + { + TEEIO_DEBUG((TEEIO_DEBUG_ERROR, "cxl_ide_km_key_set_stop RX failed with status=%08x\n", status)); + return false; + } + TEEIO_DEBUG((TEEIO_DEBUG_INFO, "key_set_stop RX\n")); + + status = cxl_ide_km_key_set_stop(doe_context, spdm_context, + session_id, stream_id, + CXL_IDE_KM_KEY_DIRECTION_TX | CXL_IDE_KM_KEY_SUB_STREAM_CXL, + port_index); + if (LIBSPDM_STATUS_IS_ERROR(status)) + { + TEEIO_DEBUG((TEEIO_DEBUG_ERROR, "cxl_ide_km_key_set_stop TX failed with status=%08x\n", status)); + return false; + } + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "key_set_stop TX\n")); + + return true; +} + +// setup cxl ide stream +bool cxl_setup_ide_stream(void *doe_context, void *spdm_context, + uint32_t *session_id, uint8_t *kcbar_addr, + uint8_t stream_id, + uint8_t port_index, + ide_common_test_port_context_t *upper_port, + ide_common_test_port_context_t *lower_port, + bool skip_ksetgo) +{ + bool result; + uint8_t index; + uint8_t kp_ack_status; + libspdm_return_t status; + + uint8_t caps; + uint8_t bus_num; + uint8_t segment; + uint8_t dev_func_num; + uint8_t max_port_index; + uint32_t ide_reg_block[CXL_IDE_KM_IDE_CAP_REG_BLOCK_MAX_COUNT] = {0}; + uint32_t ide_reg_block_count; + INTEL_KEYP_CXL_ROOT_COMPLEX_KCBAR *kcbar_ptr; + + cxl_ide_km_aes_256_gcm_key_buffer_t rx_key_buffer; + cxl_ide_km_aes_256_gcm_key_buffer_t tx_key_buffer; + + INTEL_KEYP_KEY_SLOT keys = {0}; + // INTEL_KEYP_IV_SLOT iv = {0}; + + // query + caps = 0; + ide_reg_block_count = CXL_IDE_KM_IDE_CAP_REG_BLOCK_MAX_COUNT; + status = cxl_ide_km_query(doe_context, + spdm_context, + session_id, + port_index, + &dev_func_num, + &bus_num, + &segment, + &max_port_index, + &caps, + ide_reg_block, + &ide_reg_block_count); + if (LIBSPDM_STATUS_IS_ERROR(status)) + { + TEEIO_DEBUG((TEEIO_DEBUG_ERROR, "cxl_ide_km_query failed with status=0x%x\n", status)); + return false; + } + TEEIO_DEBUG((TEEIO_DEBUG_INFO, "max_port_index - 0x%02x\n", max_port_index)); + TEEIO_DEBUG((TEEIO_DEBUG_INFO, "caps - 0x%02x\n", caps)); + TEEIO_DEBUG((TEEIO_DEBUG_INFO, "ide_reg_block:\n")); + for (index = 0; index < ide_reg_block_count; index++) + { + TEEIO_DEBUG((TEEIO_DEBUG_INFO, "%04x: 0x%08x\n", index, ide_reg_block[index])); + } + + // get_key + // status = cxl_ide_km_get_key(doe_context, spdm_context, + // &session_id, stream_id, + // CXL_IDE_KM_KEY_SUB_STREAM_CXL, port_index, + // &key_buffer); + // if (LIBSPDM_STATUS_IS_ERROR(status)) { + // TEEIO_DEBUG((TEEIO_DEBUG_ERROR, "cxl_ide_km_get_key failed with status=0x%08x\n", status)); + // return false; + // } + // TEEIO_DEBUG((TEEIO_DEBUG_INFO, "get_key\n")); + + // ide_km_key_prog in RX + result = libspdm_get_random_number(sizeof(rx_key_buffer.key), (void *)rx_key_buffer.key); + if (!result) + { + TEEIO_DEBUG((TEEIO_DEBUG_ERROR, "libspdm_get_random_number for rx_key_buffer failed.\n")); + ; + return false; + } + rx_key_buffer.iv[0] = 0; + rx_key_buffer.iv[1] = 1; + rx_key_buffer.iv[2] = 2; + cxl_dump_key_iv(&rx_key_buffer); + + status = cxl_ide_km_key_prog( + doe_context, spdm_context, + session_id, stream_id, + CXL_IDE_KM_KEY_DIRECTION_RX | CXL_IDE_KM_KEY_IV_INITIAL | CXL_IDE_KM_KEY_SUB_STREAM_CXL, + port_index, // port_index + &rx_key_buffer, &kp_ack_status); + + if (LIBSPDM_STATUS_IS_ERROR(status)) + { + TEEIO_DEBUG((TEEIO_DEBUG_ERROR, "cxl_ide_km_key_prog RX failed with status=0x%08x\n", status)); + return false; + } + TEEIO_DEBUG((TEEIO_DEBUG_INFO, "key_prog RX - %02x\n", kp_ack_status)); + + // ide_km_key_prog in TX + result = libspdm_get_random_number(sizeof(tx_key_buffer.key), (void *)tx_key_buffer.key); + if (!result) + { + TEEIO_DEBUG((TEEIO_DEBUG_ERROR, "libspdm_get_random_number for tx_key_buffer failed.\n")); + ; + return false; + } + tx_key_buffer.iv[0] = 0; + tx_key_buffer.iv[1] = 1; + tx_key_buffer.iv[2] = 2; + cxl_dump_key_iv(&tx_key_buffer); + + status = cxl_ide_km_key_prog( + doe_context, spdm_context, + session_id, stream_id, + CXL_IDE_KM_KEY_DIRECTION_TX | CXL_IDE_KM_KEY_IV_INITIAL | CXL_IDE_KM_KEY_SUB_STREAM_CXL, + port_index, + &tx_key_buffer, &kp_ack_status); + if (LIBSPDM_STATUS_IS_ERROR(status)) + { + TEEIO_DEBUG((TEEIO_DEBUG_ERROR, "cxl_ide_km_key_prog TX failed with status=0x%08x\n", status)); + return false; + } + TEEIO_DEBUG((TEEIO_DEBUG_INFO, "key_prog TX - %02x\n", kp_ack_status)); + + // TODO + // Program TX/RX pending keys into Link_Enc_Key_Tx and Link_Enc_Key_Rx registers + // Program TX/RX IV values + kcbar_ptr = (INTEL_KEYP_CXL_ROOT_COMPLEX_KCBAR *)kcbar_addr; + revert_copy_by_dw(tx_key_buffer.key, sizeof(tx_key_buffer.key), keys.bytes, sizeof(keys.bytes)); + cxl_cfg_rp_link_enc_key_iv(kcbar_ptr, CXL_IDE_KM_KEY_DIRECTION_TX, 0, keys.bytes, sizeof(keys.bytes), (uint8_t *)tx_key_buffer.iv, sizeof(tx_key_buffer.iv)); + + revert_copy_by_dw(rx_key_buffer.key, sizeof(rx_key_buffer.key), keys.bytes, sizeof(keys.bytes)); + cxl_cfg_rp_link_enc_key_iv(kcbar_ptr, CXL_IDE_KM_KEY_DIRECTION_RX, 0, keys.bytes, sizeof(keys.bytes), (uint8_t *)rx_key_buffer.iv, sizeof(rx_key_buffer.iv)); + + // Set TxKeyValid and RxKeyValid bit + cxl_cfg_rp_txrx_key_valid(kcbar_ptr, true); + + // KSetGo in RX + status = cxl_ide_km_key_set_go(doe_context, spdm_context, + session_id, stream_id, + CXL_IDE_KM_KEY_DIRECTION_RX | CXL_IDE_KM_KEY_MODE_SKID | CXL_IDE_KM_KEY_SUB_STREAM_CXL, + port_index); + if (LIBSPDM_STATUS_IS_ERROR(status)) + { + TEEIO_DEBUG((TEEIO_DEBUG_ERROR, "cxl_ide_km_key_set_go RX failed with status=0x%08x\n", status)); + return false; + } + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "key_set_go RX\n")); + + // Set StartTrigger bit + cxl_cfg_rp_start_trigger(kcbar_ptr, true); + + // KSetGo in TX + status = cxl_ide_km_key_set_go(doe_context, spdm_context, + session_id, stream_id, + CXL_IDE_KM_KEY_DIRECTION_TX | CXL_IDE_KM_KEY_MODE_SKID | CXL_IDE_KM_KEY_SUB_STREAM_CXL, + port_index); + if (LIBSPDM_STATUS_IS_ERROR(status)) + { + TEEIO_DEBUG((TEEIO_DEBUG_ERROR, "cxl_ide_km_key_set_go TX failed with status=0x%08x\n", status)); + return false; + } + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "key_set_go TX\n")); + + // wait for 10 ms for device to get ide ready + libspdm_sleep(10 * 1000); + + return true; +} \ No newline at end of file diff --git a/teeio-validator/library/cxl_ide_test_lib/test_case/test_case_full.c b/teeio-validator/library/cxl_ide_test_lib/test_case/test_case_full.c new file mode 100644 index 0000000..ceadcac --- /dev/null +++ b/teeio-validator/library/cxl_ide_test_lib/test_case/test_case_full.c @@ -0,0 +1,121 @@ +/** + * Copyright Notice: + * Copyright 2023-2024 Intel. All rights reserved. + * License: BSD 3-Clause License. + **/ + +#include +#include +#include + +#include "assert.h" +#include "hal/base.h" +#include "hal/library/debuglib.h" + +#include "hal/library/memlib.h" +#include "library/spdm_requester_lib.h" +#include "library/cxl_ide_km_requester_lib.h" +#include "ide_test.h" +#include "helperlib.h" +#include "teeio_debug.h" +#include "cxl_ide_lib.h" +#include "cxl_ide_test_lib.h" + +// setup cxl ide stream +bool cxl_setup_ide_stream(void *doe_context, void *spdm_context, + uint32_t *session_id, uint8_t *kcbar_addr, + uint8_t stream_id, uint8_t port_index, + ide_common_test_port_context_t *upper_port, + ide_common_test_port_context_t *lower_port, + bool skip_ksetgo); +bool cxl_stop_ide_stream(void *doe_context, void *spdm_context, + uint32_t *session_id, uint8_t *kcbar_addr, + uint8_t stream_id, + uint8_t port_index, + ide_common_test_port_context_t *upper_port, + ide_common_test_port_context_t *lower_port); + +bool cxl_reset_ecap_registers(ide_common_test_port_context_t *port_context); +bool cxl_reset_kcbar_registers(ide_common_test_port_context_t *port_context); + +bool cxl_ide_test_full_ide_stream_setup(void *test_context) +{ + ide_common_test_case_context_t *case_context = (ide_common_test_case_context_t *)test_context; + TEEIO_ASSERT(case_context); + TEEIO_ASSERT(case_context->signature == CASE_CONTEXT_SIGNATURE); + + ide_common_test_group_context_t *group_context = case_context->group_context; + TEEIO_ASSERT(group_context); + TEEIO_ASSERT(group_context->signature == GROUP_CONTEXT_SIGNATURE); + + ide_common_test_port_context_t *upper_port = &group_context->upper_port; + ide_common_test_port_context_t *lower_port = &group_context->lower_port; + + return cxl_setup_ide_stream(group_context->doe_context, group_context->spdm_context, + &group_context->session_id, upper_port->mapped_kcbar_addr, + group_context->stream_id, 0, + upper_port, lower_port, false); +} + +bool cxl_ide_test_full_ide_stream_run(void *test_context) +{ + ide_common_test_case_context_t *case_context = (ide_common_test_case_context_t *)test_context; + TEEIO_ASSERT(case_context); + TEEIO_ASSERT(case_context->signature == CASE_CONTEXT_SIGNATURE); + + ide_common_test_group_context_t *group_context = (ide_common_test_group_context_t *)case_context->group_context; + TEEIO_ASSERT(group_context); + TEEIO_ASSERT(group_context->signature == GROUP_CONTEXT_SIGNATURE); + + int upper_port_cfg_space_fd = group_context->upper_port.cfg_space_fd; + uint32_t upper_port_ecap_offset = group_context->upper_port.ecap_offset; + INTEL_KEYP_CXL_ROOT_COMPLEX_KCBAR *kcbar_ptr = (INTEL_KEYP_CXL_ROOT_COMPLEX_KCBAR *)group_context->upper_port.mapped_kcbar_addr; + + int lower_port_cfg_space_fd = group_context->lower_port.cfg_space_fd; + uint32_t lower_port_ecap_offset = group_context->lower_port.ecap_offset; + + // Now ide stream shall be in secure state + // Dump registers to check + TEEIO_PRINT(("\n")); + TEEIO_PRINT(("Print host registers.\n")); + + cxl_dump_ecap(upper_port_cfg_space_fd, upper_port_ecap_offset); + cxl_dump_kcbar(kcbar_ptr); + + TEEIO_PRINT(("\n")); + TEEIO_PRINT(("Print device registers.\n")); + cxl_dump_ecap(lower_port_cfg_space_fd, lower_port_ecap_offset); + + TEEIO_PRINT(("ide_stream is setup. Press any key to continue.\n")); + getchar(); + + case_context->result = IDE_COMMON_TEST_CASE_RESULT_SUCCESS; + return true; +} + +bool cxl_ide_test_full_ide_stream_teardown(void *test_context) +{ + bool ret = false; + + ide_common_test_case_context_t *case_context = (ide_common_test_case_context_t *)test_context; + TEEIO_ASSERT(case_context); + TEEIO_ASSERT(case_context->signature == CASE_CONTEXT_SIGNATURE); + + ide_common_test_group_context_t *group_context = case_context->group_context; + TEEIO_ASSERT(group_context); + TEEIO_ASSERT(group_context->signature == GROUP_CONTEXT_SIGNATURE); + + ide_common_test_port_context_t *upper_port = &group_context->upper_port; + ide_common_test_port_context_t *lower_port = &group_context->lower_port; + + // TODO + // disable mem_enable bit in CXL_CONTROL + + // send KSetStop + ret = cxl_stop_ide_stream(group_context->doe_context, group_context->spdm_context, + &group_context->session_id, upper_port->mapped_kcbar_addr, + group_context->stream_id, 0, + upper_port, lower_port); + + return ret; +} diff --git a/teeio-validator/library/cxl_ide_test_lib/test_config/test_config_default.c b/teeio-validator/library/cxl_ide_test_lib/test_config/test_config_default.c new file mode 100644 index 0000000..d469d75 --- /dev/null +++ b/teeio-validator/library/cxl_ide_test_lib/test_config/test_config_default.c @@ -0,0 +1,78 @@ +/** + * Copyright Notice: + * Copyright 2023-2024 Intel. All rights reserved. + * License: BSD 3-Clause License. + **/ + +#include +#include + +#include "hal/base.h" +#include "hal/library/debuglib.h" + +#include "ide_test.h" +#include "helperlib.h" +#include "teeio_debug.h" +#include "cxl_ide_lib.h" +#include "cxl_ide_test_lib.h" + +// test selective_ide and link_ide with default config +bool cxl_ide_test_config_default_enable(void *test_context) +{ + return true; +} + +bool cxl_ide_test_config_default_disable(void *test_context) +{ + return true; +} + +bool cxl_ide_test_config_default_support(void *test_context) +{ + return true; +} + +bool cxl_ide_test_config_default_check(void *test_context) +{ + return true; +} + +// common function +bool cxl_ide_test_config_enable_common(void *test_context) +{ + return true; +} + +bool cxl_ide_test_config_check_common(void *test_context) +{ + // ide_common_test_config_context_t *config_context = (ide_common_test_config_context_t *)test_context; + // TEEIO_ASSERT(config_context->signature == CONFIG_CONTEXT_SIGNATURE); + + // ide_common_test_group_context_t *group_context = config_context->group_context; + // TEEIO_ASSERT(group_context->signature == GROUP_CONTEXT_SIGNATURE); + + // IDE_TEST_TOPOLOGY* top = group_context->top; + // TEEIO_ASSERT(top->connection == IDE_TEST_TOPOLOGY_TYPE_SEL_IDE); + + return true; +} + +bool cxl_ide_test_config_support_common(void *test_context) +{ + ide_common_test_config_context_t *config_context = (ide_common_test_config_context_t *)test_context; + TEEIO_ASSERT(config_context->signature == CONFIG_CONTEXT_SIGNATURE); + + ide_common_test_group_context_t *group_context = config_context->group_context; + TEEIO_ASSERT(group_context->signature == GROUP_CONTEXT_SIGNATURE); + + CXL_PRIV_DATA* rp_cxl_data = &group_context->upper_port.priv_data.cxl; + CXL_PRIV_DATA* ep_cxl_data = &group_context->lower_port.priv_data.cxl; + + TEEIO_DEBUG((TEEIO_DEBUG_INFO, "cxl_ide_test_config_support_common cxl_rp.cap=0x%04x, ep_cxl.cap=0x%04x\n", rp_cxl_data->cap.raw, ep_cxl_data->cap.raw)); + + // TODO + bool supported = rp_cxl_data->cap.mem_capable == 1 && ep_cxl_data->cap.mem_capable; + + return supported; +} + diff --git a/teeio-validator/library/cxl_ide_test_lib/test_group/test_group.c b/teeio-validator/library/cxl_ide_test_lib/test_group/test_group.c new file mode 100644 index 0000000..5dec4f6 --- /dev/null +++ b/teeio-validator/library/cxl_ide_test_lib/test_group/test_group.c @@ -0,0 +1,128 @@ +/** + * Copyright Notice: + * Copyright 2023-2024 Intel. All rights reserved. + * License: BSD 3-Clause License. + **/ + +#include +#include +#include +#include + +#include "hal/base.h" +#include "hal/library/debuglib.h" + +#include "library/spdm_requester_lib.h" +#include "library/spdm_crypt_lib.h" +#include "ide_test.h" +#include "helperlib.h" +#include "teeio_debug.h" +#include "cxl_ide_lib.h" +#include "pcie_ide_lib.h" +#include "teeio_spdmlib.h" + +bool cxl_scan_devices(void *test_context) +{ + bool ret = false; + ide_common_test_group_context_t *context = (ide_common_test_group_context_t *)test_context; + TEEIO_ASSERT(context->signature == GROUP_CONTEXT_SIGNATURE); + + IDE_TEST_TOPOLOGY *top = context->top; + + TEEIO_ASSERT(top->ide_type == IDE_HW_TYPE_CXL_MEM); + TEEIO_ASSERT(top->connection == IDE_TEST_CONNECT_DIRECT || top->connection == IDE_TEST_CONNECT_SWITCH); + + ret = scan_devices_at_bus(context->root_port.port, context->lower_port.port, context->sw_conn1, context->top->bus); + if(ret) { + context->upper_port.port->bus = context->root_port.port->bus; + strncpy(context->upper_port.port->bdf, context->root_port.port->bdf, BDF_LENGTH); + } + + return ret; +} + +// selective_ide test group + +/** + * This function works to setup selective_ide and link_ide + * + * 1. open cofiguration_space and find the ecap_offset + * 2. map kcbar to user space + * 3. initialize spdm_context and doe_context + * 4. setup spdm_session + */ +static bool common_test_group_setup(void *test_context) +{ + bool ret = false; + + ide_common_test_group_context_t *context = (ide_common_test_group_context_t *)test_context; + TEEIO_ASSERT(context->signature == GROUP_CONTEXT_SIGNATURE); + + // first scan devices + if(!cxl_scan_devices(test_context)) { + return false; + } + + // initialize lower_port + ret = cxl_init_dev_port(context); + if(!ret) { + return false; + } + + IDE_TEST_TOPOLOGY *top = context->top; + TEEIO_ASSERT(top->connection == IDE_TEST_CONNECT_DIRECT || top->connection == IDE_TEST_CONNECT_SWITCH); + + ret = cxl_init_root_port(context); + if (!ret) { + return false; + } + + // init spdm_context + void *spdm_context = spdm_client_init(); + TEEIO_ASSERT(spdm_context != NULL); + + uint32_t session_id = 0; + ret = spdm_connect(spdm_context, &session_id); + if (!ret) { + TEEIO_DEBUG((TEEIO_DEBUG_ERROR, "spdm_connect failed.\n")); + return false; + } + + context->spdm_context = spdm_context; + context->session_id = session_id; + + return true; +} + +static bool common_test_group_teardown(void *test_context) +{ + ide_common_test_group_context_t *context = (ide_common_test_group_context_t *)test_context; + TEEIO_ASSERT(context->signature == GROUP_CONTEXT_SIGNATURE); + + // close spdm_session and free spdm_context + if(context->spdm_context != NULL) { + spdm_stop(context->spdm_context, context->session_id); + free(context->spdm_context); + context->spdm_context = NULL; + context->session_id = 0; + } + + IDE_TEST_TOPOLOGY *top = context->top; + TEEIO_ASSERT(top->connection == IDE_TEST_CONNECT_DIRECT || top->connection == IDE_TEST_CONNECT_SWITCH); + + // close ports + cxl_close_dev_port(&context->lower_port, top->type); + cxl_close_root_port(context); + + return true; +} + +bool cxl_ide_test_group_setup(void *test_context) +{ + return common_test_group_setup(test_context); +} + +bool cxl_ide_test_group_teardown(void *test_context) +{ + return common_test_group_teardown(test_context); +} From 0e040375d87e060e1c7a8df64f9697ed34e6a16b Mon Sep 17 00:00:00 2001 From: Min M Xu Date: Sun, 16 Jun 2024 21:13:47 -0400 Subject: [PATCH 05/11] Add test_factory Signed-off-by: Min Xu --- .../include/teeio_validator_internal.h | 13 + .../teeio_validator/include/test_factory.h | 48 +++ .../teeio_validator/test_factory.c | 393 ++++++++++++++++++ 3 files changed, 454 insertions(+) create mode 100644 teeio-validator/teeio_validator/include/teeio_validator_internal.h create mode 100644 teeio-validator/teeio_validator/include/test_factory.h create mode 100644 teeio-validator/teeio_validator/test_factory.c diff --git a/teeio-validator/teeio_validator/include/teeio_validator_internal.h b/teeio-validator/teeio_validator/include/teeio_validator_internal.h new file mode 100644 index 0000000..48a1323 --- /dev/null +++ b/teeio-validator/teeio_validator/include/teeio_validator_internal.h @@ -0,0 +1,13 @@ +/** + * Copyright Notice: + * Copyright 2024 Intel. All rights reserved. + * License: BSD 3-Clause License. + **/ + +#ifndef __TEEIO_VAILDATOR_INTERNAL_H__ +#define __TEEIO_VAILDATOR_INTERNAL_H__ + +// ide_test_case_name_t* get_test_case_from_string(const char* test_case_name, int* index, IDE_HW_TYPE ide_type); +bool is_valid_test_case(const char* test_case_name, IDE_HW_TYPE ide_type); + +#endif \ No newline at end of file diff --git a/teeio-validator/teeio_validator/include/test_factory.h b/teeio-validator/teeio_validator/include/test_factory.h new file mode 100644 index 0000000..17df552 --- /dev/null +++ b/teeio-validator/teeio_validator/include/test_factory.h @@ -0,0 +1,48 @@ +/** + * Copyright Notice: + * Copyright 2023-2024 Intel. All rights reserved. + * License: BSD 3-Clause License. + **/ + +#ifndef __IDE_FACTORY_H__ +#define __IDE_FACTORY_H__ + +#include "ide_test.h" +#include "pcie_ide_test_lib.h" +#include "cxl_ide_test_lib.h" + +ide_test_config_funcs_t* +test_factory_get_test_config_funcs ( + IDE_HW_TYPE ide, + IDE_TEST_TOPOLOGY_TYPE top_type, + IDE_TEST_CONFIGURATION_TYPE config_type); + +ide_test_group_funcs_t* +test_factory_get_test_group_funcs ( + IDE_HW_TYPE ide, + IDE_TEST_TOPOLOGY_TYPE top_type +); + +ide_test_case_funcs_t* +test_factory_get_test_case_funcs ( + IDE_HW_TYPE ide, + IDE_COMMON_TEST_CASE test_case, + int case_id +); + +ide_common_test_config_enable_func_t +test_factory_get_common_test_config_enable_func( + IDE_HW_TYPE ide +); + +ide_common_test_config_check_func_t +test_factory_get_common_test_config_check_func( + IDE_HW_TYPE ide +); + +ide_common_test_config_support_func_t +test_factory_get_common_test_config_support_func( + IDE_HW_TYPE ide +); + +#endif diff --git a/teeio-validator/teeio_validator/test_factory.c b/teeio-validator/teeio_validator/test_factory.c new file mode 100644 index 0000000..bcdbc15 --- /dev/null +++ b/teeio-validator/teeio_validator/test_factory.c @@ -0,0 +1,393 @@ +/** + * Copyright Notice: + * Copyright 2023-2024 Intel. All rights reserved. + * License: BSD 3-Clause License. + **/ + +#include +#include "ide_test.h" +#include "helperlib.h" +#include "test_factory.h" + +#define PCIE_CLASS_CASE_NAMES "IdeStream,KeyRefresh" +#define CXL_MEM_CLASS_CASE_NAMES "IdeStream" + +extern const char *IDE_HW_TYPE_NAMES[]; + +ide_test_case_name_t m_pcie_ide_test_case_names[IDE_COMMON_TEST_CASE_NUM] = { + {"Query", "1,2", IDE_COMMON_TEST_CASE_QUERY , IDE_HW_TYPE_PCIE}, + {"KeyProg", "1,2,3,4,5,6", IDE_COMMON_TEST_CASE_KEYPROG , IDE_HW_TYPE_PCIE}, + {"KSetGo", "1,2,3,4", IDE_COMMON_TEST_CASE_KSETGO , IDE_HW_TYPE_PCIE}, + {"KSetStop", "1,2,3,4", IDE_COMMON_TEST_CASE_KSETSTOP , IDE_HW_TYPE_PCIE}, + {"SpdmSession", "1,2", IDE_COMMON_TEST_CASE_SPDMSESSION , IDE_HW_TYPE_PCIE}, + {"Test", PCIE_CLASS_CASE_NAMES, IDE_COMMON_TEST_CASE_TEST , IDE_HW_TYPE_PCIE} +}; + +ide_test_case_name_t m_cxl_mem_ide_test_case_names[CXL_MEM_IDE_TEST_CASE_NUM] = { + {"Query", "1,2", CXL_MEM_IDE_TEST_CASE_QUERY , IDE_HW_TYPE_CXL_MEM}, + {"KeyProg", "1,2,3,4,5,6,7,8,9", CXL_MEM_IDE_TEST_CASE_KEYPROG , IDE_HW_TYPE_CXL_MEM}, + {"KSetGo", "1", CXL_MEM_IDE_TEST_CASE_KSETGO , IDE_HW_TYPE_CXL_MEM}, + {"KSetStop", "1", CXL_MEM_IDE_TEST_CASE_KSETSTOP , IDE_HW_TYPE_CXL_MEM}, + {"GetKey", "1", CXL_MEM_IDE_TEST_CASE_GETKEY , IDE_HW_TYPE_CXL_MEM}, + {"Test", CXL_MEM_CLASS_CASE_NAMES, CXL_MEM_IDE_TEST_CASE_TEST , IDE_HW_TYPE_CXL_MEM} +}; + +ide_test_case_name_t* get_test_case_from_string(const char* test_case_name, int* index, IDE_HW_TYPE ide_type) +{ + if(test_case_name == NULL) { + return NULL; + } + + TEEIO_ASSERT(ide_type < IDE_HW_TYPE_NUM); + + ide_test_case_name_t* test_case_names = NULL; + int test_case_names_cnt = 0; + + if(ide_type == IDE_HW_TYPE_PCIE) { + test_case_names = m_pcie_ide_test_case_names; + test_case_names_cnt = IDE_COMMON_TEST_CASE_NUM; + } else if(ide_type == IDE_HW_TYPE_CXL_MEM) { + test_case_names = m_cxl_mem_ide_test_case_names; + test_case_names_cnt = CXL_MEM_IDE_TEST_CASE_NUM; + } else { + TEEIO_DEBUG((TEEIO_DEBUG_ERROR, "%s is not supported.\n", IDE_HW_TYPE_NAMES[(int)ide_type])); + return NULL; + } + + char buf1[MAX_LINE_LENGTH] = {0}; + char buf2[MAX_LINE_LENGTH] = {0}; + strncpy(buf1, test_case_name, MAX_LINE_LENGTH); + + int pos = find_char_in_str(buf1, '.'); + if(pos == -1) { + return NULL; + } + + buf1[pos] = '\0'; + char* ptr1 = buf1 + pos + 1; + + int i = 0; + for(; i < test_case_names_cnt; i++) { + if(strcmp(buf1, test_case_names[i].class) == 0) { + break; + } + } + if(i == test_case_names_cnt) { + return NULL; + } + + bool hit = false; + strncpy(buf2, test_case_names[i].names, MAX_LINE_LENGTH); + char *ptr2 = buf2; + int j = 0; + + pos = find_char_in_str(ptr2, ','); + + do { + if(pos != -1) { + ptr2[pos] = '\0'; + } + if(strcmp(ptr1, ptr2) == 0) { + hit = true; + break; + } + + if(pos == -1) { + break; + } + + ptr2 += (pos + 1); + pos = find_char_in_str(ptr2, ','); + j++; + } while(true); + + if(index != NULL) { + *index = j; + } + + return hit ? test_case_names + i : NULL; +} + +bool is_valid_test_case(const char* test_case_name, IDE_HW_TYPE ide_type) +{ + return get_test_case_from_string(test_case_name, NULL, ide_type) != NULL; +} + +ide_test_config_funcs_t m_cxl_ide_config_funcs[CXL_IDE_CONFIGURATION_TYPE_NUM] = { + { // Default Config + cxl_ide_test_config_default_enable, + cxl_ide_test_config_default_disable, + cxl_ide_test_config_default_support, + cxl_ide_test_config_default_check + }, + {}, // pcrc + {} // ide.stop +}; + +ide_test_group_funcs_t m_cxl_ide_group_funcs = { + cxl_ide_test_group_setup, + cxl_ide_test_group_teardown +}; + +ide_test_case_funcs_t m_cxl_ide_test_case_funcs[CXL_MEM_IDE_TEST_CASE_NUM][MAX_CXL_CASE_ID] = { + // Query + {}, + // KeyProg + {}, + // KSetGo + {}, + // KSetStop + {}, + // GetKey + {}, + // Test + { + { cxl_ide_test_full_ide_stream_setup, cxl_ide_test_full_ide_stream_run, cxl_ide_test_full_ide_stream_teardown, false }, // IdeStream + {} + } +}; + +ide_test_config_funcs_t m_pcie_ide_config_funcs[IDE_TEST_TOPOLOGY_TYPE_NUM][IDE_TEST_CONFIGURATION_TYPE_NUM] = { + { // selective_ide + { // Default Config + pcie_ide_test_config_default_enable_common, + pcie_ide_test_config_default_disable_common, + pcie_ide_test_config_default_support_common, + pcie_ide_test_config_default_check_common + }, + {NULL, NULL, NULL, NULL}, // switch + {NULL, NULL, NULL, NULL}, // partial header encryption + { // pcrc + pcie_ide_test_config_pcrc_enable_sel, + pcie_ide_test_config_pcrc_disable_sel, + pcie_ide_test_config_pcrc_support_sel, + pcie_ide_test_config_pcrc_check_sel + }, + {NULL, NULL, NULL, NULL}, // aggregation + { // selective_ide for configuration request + pcie_ide_test_config_enable_sel_ide_for_cfg_req, + pcie_ide_test_config_disable_sel_ide_for_cfg_req, + pcie_ide_test_config_support_sel_ide_for_cfg_req, + pcie_ide_test_config_check_sel_ide_for_cfg_req + }, + {NULL, NULL, NULL, NULL} // tee_limited_stream + }, + { // link_ide + { + // Default Config + pcie_ide_test_config_default_enable_common, + pcie_ide_test_config_default_disable_common, + pcie_ide_test_config_default_support_common, + pcie_ide_test_config_default_check_common + }, + + {NULL, NULL, NULL, NULL}, + {NULL, NULL, NULL, NULL}, + + { + // pcrc + pcie_ide_test_config_pcrc_enable_link, + pcie_ide_test_config_pcrc_disable_link, + pcie_ide_test_config_pcrc_support_link, + pcie_ide_test_config_pcrc_check_link + }, + + {NULL, NULL, NULL, NULL}, + {NULL, NULL, NULL, NULL}, + {NULL, NULL, NULL, NULL} + }, + { // selective_and_link_ide + { + // Default Config + pcie_ide_test_config_default_enable_sel_link, + pcie_ide_test_config_default_disable_sel_link, + pcie_ide_test_config_default_support_sel_link, + pcie_ide_test_config_default_check_sel_link + }, + {NULL, NULL, NULL, NULL}, + {NULL, NULL, NULL, NULL}, + { + // pcrc + pcie_ide_test_config_pcrc_enable_sel_link, + pcie_ide_test_config_pcrc_disable_sel_link, + pcie_ide_test_config_pcrc_support_sel_link, + pcie_ide_test_config_pcrc_check_sel_link + }, + {NULL, NULL, NULL, NULL}, + {NULL, NULL, NULL, NULL}, + {NULL, NULL, NULL, NULL} + } +}; + +ide_test_group_funcs_t m_pcie_ide_group_funcs[] = { + { // selective_ide + pcie_ide_test_group_setup_sel, + pcie_ide_test_group_teardown_sel + }, + { // link_ide + pcie_ide_test_group_setup_link, + pcie_ide_test_group_teardown_link + }, + { // selective_link_ide + pcie_ide_test_group_setup_sel_link, + pcie_ide_test_group_teardown_sel_link + } +}; + +ide_test_case_funcs_t m_pcie_ide_test_case_funcs[IDE_COMMON_TEST_CASE_NUM][MAX_PCIE_CASE_ID] = { + // Query + { + { pcie_ide_test_query_1_setup, pcie_ide_test_query_1_run, pcie_ide_test_query_1_teardown, false }, + { pcie_ide_test_query_2_setup, pcie_ide_test_query_2_run, pcie_ide_test_query_2_teardown, false }, + {NULL, NULL, NULL, false}, + {NULL, NULL, NULL, false}, + {NULL, NULL, NULL, false}, + {NULL, NULL, NULL, false}, + }, + // KeyProg + { + {pcie_ide_test_keyprog_1_setup, pcie_ide_test_keyprog_1_run, pcie_ide_test_keyprog_1_teardown, false}, + {pcie_ide_test_keyprog_2_setup, pcie_ide_test_keyprog_2_run, pcie_ide_test_keyprog_2_teardown, false}, + {pcie_ide_test_keyprog_3_setup, pcie_ide_test_keyprog_3_run, pcie_ide_test_keyprog_3_teardown, false}, + {pcie_ide_test_keyprog_4_setup, pcie_ide_test_keyprog_4_run, pcie_ide_test_keyprog_4_teardown, false}, + {pcie_ide_test_keyprog_5_setup, pcie_ide_test_keyprog_5_run, pcie_ide_test_keyprog_5_teardown, false}, + {pcie_ide_test_keyprog_6_setup, pcie_ide_test_keyprog_6_run, pcie_ide_test_keyprog_6_teardown, false} + }, + // KSetGo + { + { pcie_ide_test_ksetgo_1_setup, pcie_ide_test_ksetgo_1_run, pcie_ide_test_ksetgo_1_teardown, true }, + { pcie_ide_test_ksetgo_2_setup, pcie_ide_test_ksetgo_2_run, pcie_ide_test_ksetgo_2_teardown, true }, + { pcie_ide_test_ksetgo_3_setup, pcie_ide_test_ksetgo_3_run, pcie_ide_test_ksetgo_3_teardown, true }, + { pcie_ide_test_ksetgo_4_setup, pcie_ide_test_ksetgo_4_run, pcie_ide_test_ksetgo_4_teardown, true }, + {NULL, NULL, NULL, false}, + {NULL, NULL, NULL, false} + }, + // KSetStop + { + { pcie_ide_test_ksetstop_1_setup, pcie_ide_test_ksetstop_1_run, pcie_ide_test_ksetstop_1_teardown, false }, + { pcie_ide_test_ksetstop_2_setup, pcie_ide_test_ksetstop_2_run, pcie_ide_test_ksetstop_2_teardown, false }, + { pcie_ide_test_ksetstop_3_setup, pcie_ide_test_ksetstop_3_run, pcie_ide_test_ksetstop_3_teardown, false }, + { pcie_ide_test_ksetstop_4_setup, pcie_ide_test_ksetstop_4_run, pcie_ide_test_ksetstop_4_teardown, false }, + {NULL, NULL, NULL, false}, + {NULL, NULL, NULL, false} + }, + // SpdmSession + { + {NULL, NULL, NULL}, + {NULL, NULL, NULL}, + {NULL, NULL, NULL}, + {NULL, NULL, NULL}, + {NULL, NULL, NULL}, + {NULL, NULL, NULL} + }, + // Test Full + { + { pcie_ide_test_full_1_setup, pcie_ide_test_full_1_run, pcie_ide_test_full_1_teardown, false }, // IdeStream + { pcie_ide_test_full_keyrefresh_setup, pcie_ide_test_full_keyrefresh_run, pcie_ide_test_full_keyrefresh_teardown, false }, // KeyRefresh + {NULL, NULL, NULL}, + {NULL, NULL, NULL}, + {NULL, NULL, NULL}, + {NULL, NULL, NULL} + } +}; + +ide_test_config_funcs_t* +test_factory_get_test_config_funcs ( + IDE_HW_TYPE ide, + IDE_TEST_TOPOLOGY_TYPE top_type, + IDE_TEST_CONFIGURATION_TYPE config_type) +{ + if(ide == IDE_HW_TYPE_PCIE) { + return &m_pcie_ide_config_funcs[top_type][config_type]; + } else if(ide == IDE_HW_TYPE_CXL_MEM) { + return &m_cxl_ide_config_funcs[config_type]; + } else { + TEEIO_DEBUG((TEEIO_DEBUG_ERROR, "%s is not supported yet.\n", IDE_HW_TYPE_NAMES[ide])); + return NULL; + } +} + +ide_test_group_funcs_t* +test_factory_get_test_group_funcs ( + IDE_HW_TYPE ide, + IDE_TEST_TOPOLOGY_TYPE top_type +) +{ + if(ide == IDE_HW_TYPE_PCIE) { + return &m_pcie_ide_group_funcs[top_type]; + } else if(ide == IDE_HW_TYPE_CXL_MEM) { + // CXL only supports selective_ide + TEEIO_ASSERT(top_type == IDE_TEST_TOPOLOGY_TYPE_SEL_IDE); + return &m_cxl_ide_group_funcs; + } else { + TEEIO_DEBUG((TEEIO_DEBUG_ERROR, "%s is not supported yet.\n", IDE_HW_TYPE_NAMES[ide])); + return NULL; + } +} + +ide_test_case_funcs_t* +test_factory_get_test_case_funcs ( + IDE_HW_TYPE ide, + IDE_COMMON_TEST_CASE test_case, + int case_id +) +{ + if(ide == IDE_HW_TYPE_PCIE) { + return &m_pcie_ide_test_case_funcs[test_case][case_id]; + } else if(ide == IDE_HW_TYPE_CXL_MEM) { + return &m_cxl_ide_test_case_funcs[test_case][case_id]; + } else { + TEEIO_DEBUG((TEEIO_DEBUG_ERROR, "%s is not supported yet.\n", IDE_HW_TYPE_NAMES[ide])); + return NULL; + } +} + +bool not_supported_ide_test_config_common_func(void *test_context) +{ + return false; +} + +ide_common_test_config_enable_func_t +test_factory_get_common_test_config_enable_func( + IDE_HW_TYPE ide +) +{ + if(ide == IDE_HW_TYPE_PCIE) { + return pcie_ide_test_config_enable_common; + } else if(ide == IDE_HW_TYPE_CXL_MEM) { + return cxl_ide_test_config_enable_common; + } else { + TEEIO_DEBUG((TEEIO_DEBUG_ERROR, "%s is not supported yet.\n", IDE_HW_TYPE_NAMES[ide])); + return not_supported_ide_test_config_common_func; + } +} + +ide_common_test_config_check_func_t +test_factory_get_common_test_config_check_func( + IDE_HW_TYPE ide +) +{ + if(ide == IDE_HW_TYPE_PCIE) { + return pcie_ide_test_config_check_common; + } else if(ide == IDE_HW_TYPE_CXL_MEM) { + return cxl_ide_test_config_check_common; + } else { + TEEIO_DEBUG((TEEIO_DEBUG_ERROR, "%s is not supported yet.\n", IDE_HW_TYPE_NAMES[ide])); + return not_supported_ide_test_config_common_func; + } +} + +ide_common_test_config_support_func_t +test_factory_get_common_test_config_support_func( + IDE_HW_TYPE ide +) +{ + if(ide == IDE_HW_TYPE_PCIE) { + return pcie_ide_test_config_support_common; + } else if(ide == IDE_HW_TYPE_CXL_MEM) { + return cxl_ide_test_config_support_common; + } else { + TEEIO_DEBUG((TEEIO_DEBUG_ERROR, "%s is not supported yet.\n", IDE_HW_TYPE_NAMES[ide])); + return not_supported_ide_test_config_common_func; + } +} From 14d7e1ea0330d349539bdb41527707bc5fa6eef5 Mon Sep 17 00:00:00 2001 From: Min M Xu Date: Sun, 16 Jun 2024 21:15:48 -0400 Subject: [PATCH 06/11] Update ide_test.ini to support CXL.memcache Signed-off-by: Min Xu --- doc/ide_test.ini | 1 + teeio-validator/include/ide_test.h | 79 ++++++++++++++++--- .../teeio_validator/ide_test_ini.c | 25 +++++- 3 files changed, 93 insertions(+), 12 deletions(-) diff --git a/doc/ide_test.ini b/doc/ide_test.ini index 648f817..a8eef65 100644 --- a/doc/ide_test.ini +++ b/doc/ide_test.ini @@ -23,6 +23,7 @@ port_5=07.0 [Topology_1] type = selective_ide ; refer to IdeKmTestTopology.SelectiveIDE.md connection = direct ; connect directly +ide = pcie ; pcie cxl.io cxl.mem bus = 0x1a path1 = rootport_1,endpoint_1 stream_id = 1 diff --git a/teeio-validator/include/ide_test.h b/teeio-validator/include/ide_test.h index 467ad35..aa8a404 100644 --- a/teeio-validator/include/ide_test.h +++ b/teeio-validator/include/ide_test.h @@ -11,6 +11,7 @@ #include #include #include "pcie.h" +#include "cxl.h" #include "intel_keyp.h" #define NOT_IMPLEMENTED(msg) \ @@ -53,9 +54,21 @@ #define MAX_KSETSTOP_CASE_ID 4 #define MAX_SPDMSESSION_CASE_ID 2 #define MAX_FULL_CASE_ID 1 -#define MAX_CASE_ID \ +#define MAX_PCIE_CASE_ID \ (MAX(MAX_QUERY_CASE_ID, MAX(MAX_KEYPROG_CASE_ID, MAX(MAX_KSETGO_CASE_ID, MAX(MAX_KSETSTOP_CASE_ID, MAX(MAX_SPDMSESSION_CASE_ID, MAX_FULL_CASE_ID)))))) +#define MAX_CXL_QUERY_CASE_ID 2 +#define MAX_CXL_KEYPROG_CASE_ID 9 +#define MAX_CXL_KSETGO_CASE_ID 1 +#define MAX_CXL_KSETSTOP_CASE_ID 1 +#define MAX_CXL_GETKEY_CASE_ID 1 +#define MAX_CXL_FULL_CASE_ID 2 +#define MAX_CXL_CASE_ID \ + (MAX(MAX_CXL_QUERY_CASE_ID, MAX(MAX_CXL_KEYPROG_CASE_ID, MAX(MAX_CXL_KSETGO_CASE_ID, MAX(MAX_CXL_KSETSTOP_CASE_ID, MAX(MAX_CXL_GETKEY_CASE_ID, MAX_CXL_FULL_CASE_ID)))))) + +#define MAX_CASE_ID \ + (MAX(MAX_PCIE_CASE_ID, MAX_CXL_CASE_ID)) + #define INVALID_PORT_ID 0 #define MAIN_SECION "Main" @@ -100,6 +113,13 @@ typedef enum { IDE_TEST_TOPOLOGY_TYPE_NUM } IDE_TEST_TOPOLOGY_TYPE; +typedef enum { + IDE_HW_TYPE_PCIE = 0, + IDE_HW_TYPE_CXL_IO, + IDE_HW_TYPE_CXL_MEM, + IDE_HW_TYPE_NUM +} IDE_HW_TYPE; + typedef enum { IDE_COMMON_TEST_CASE_QUERY = 0, IDE_COMMON_TEST_CASE_KEYPROG, @@ -110,6 +130,16 @@ typedef enum { IDE_COMMON_TEST_CASE_NUM } IDE_COMMON_TEST_CASE; +typedef enum { + CXL_MEM_IDE_TEST_CASE_QUERY = 0, + CXL_MEM_IDE_TEST_CASE_KEYPROG, + CXL_MEM_IDE_TEST_CASE_KSETGO, + CXL_MEM_IDE_TEST_CASE_KSETSTOP, + CXL_MEM_IDE_TEST_CASE_GETKEY, + CXL_MEM_IDE_TEST_CASE_TEST, + CXL_MEM_IDE_TEST_CASE_NUM +} CXL_MEM_IDE_TEST_CASE; + typedef struct { int id; @@ -161,6 +191,7 @@ typedef struct typedef struct { int id; bool enabled; + IDE_HW_TYPE ide_type; IDE_TEST_TOPOLOGY_TYPE type; IDE_TEST_CONNECT_TYPE connection; int root_port; @@ -244,6 +275,13 @@ typedef enum { IDE_TEST_CONFIGURATION_TYPE_NUM } IDE_TEST_CONFIGURATION_TYPE; +typedef enum { + CXL_IDE_CONFIGURATION_TYPE_DEFAULT = 0, + CXL_IDE_CONFIGURATION_TYPE_PCRC, + CXL_IDE_CONFIGURATION_TYPE_IDE_STOP, + CXL_IDE_CONFIGURATION_TYPE_NUM +} CXL_IDE_CONFIGURATION_TYPE; + #define BIT_MASK(n) ((uint32_t)(1<type = get_topology_type_from_name(entry_value); + sprintf(entry_name, "ide"); + if (GetStringFromDataFile(context, (uint8_t *)section_name, (uint8_t *)entry_name, &entry_value)) + { + if (!is_valid_ide_hw_type(entry_value)) + { + TEEIO_DEBUG((TEEIO_DEBUG_ERROR, "[%s] Invalid ide type. %s\n", section_name, entry_value)); + return false; + } + topology->ide_type = get_ide_hw_type_from_name((const char*)entry_value); + } + else + { + topology->ide_type = IDE_HW_TYPE_PCIE; + } + // connection sprintf(entry_name, "connection"); if (!GetStringFromDataFile(context, (uint8_t *)section_name, (uint8_t *)entry_name, &entry_value)) @@ -2575,7 +2596,7 @@ bool update_test_config_with_given_top_config_id(IDE_TEST_CONFIG *test_config, i } int index = 0; - ide_test_case_name_t* tcn = get_test_case_from_string(test_case, &index); + ide_test_case_name_t* tcn = get_test_case_from_string(test_case, &index, IDE_HW_TYPE_PCIE); if(tcn == NULL) { return false; } From 0e803fa8045dec589b85e8177b6e41973f26e39f Mon Sep 17 00:00:00 2001 From: Min M Xu Date: Sun, 16 Jun 2024 21:16:55 -0400 Subject: [PATCH 07/11] Update CMakeLists.txt Signed-off-by: Min Xu --- teeio-validator/CMakeLists.txt | 7 ++++++- teeio-validator/teeio_validator/CMakeLists.txt | 3 +++ 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/teeio-validator/CMakeLists.txt b/teeio-validator/CMakeLists.txt index 66c3d60..c8c0b3f 100644 --- a/teeio-validator/CMakeLists.txt +++ b/teeio-validator/CMakeLists.txt @@ -201,6 +201,8 @@ if(ENABLE_CODEQL STREQUAL "ON") ADD_SUBDIRECTORY(${TEEIO_VALIDATOR_DIR}/library/spdmlib) ADD_SUBDIRECTORY(${TEEIO_VALIDATOR_DIR}/library/pcie_ide_lib) ADD_SUBDIRECTORY(${TEEIO_VALIDATOR_DIR}/library/pcie_ide_test_lib) + ADD_SUBDIRECTORY(${TEEIO_VALIDATOR_DIR}/library/cxl_ide_lib) + ADD_SUBDIRECTORY(${TEEIO_VALIDATOR_DIR}/library/cxl_ide_test_lib) ADD_SUBDIRECTORY(${LIBSPDM_DIR}/os_stub/rnglib) ADD_SUBDIRECTORY(${LIBSPDM_DIR}/os_stub/platform_lib) ADD_SUBDIRECTORY(${LIBSPDM_DIR}/os_stub/platform_lib_null) @@ -241,6 +243,8 @@ ADD_COMPILE_OPTIONS(-DLIBSPDM_CONFIG="${PROJECT_SOURCE_DIR}/include/spdm_lib_con ADD_SUBDIRECTORY(${PROJECT_SOURCE_DIR}/library/spdmlib out/spdmlib.lib) ADD_SUBDIRECTORY(${PROJECT_SOURCE_DIR}/library/pcie_ide_lib out/pcie_ide_lib.lib) ADD_SUBDIRECTORY(${PROJECT_SOURCE_DIR}/library/pcie_ide_test_lib out/pcie_ide_test_lib.lib) + ADD_SUBDIRECTORY(${PROJECT_SOURCE_DIR}/library/cxl_ide_lib out/cxl_ide_lib.lib) + ADD_SUBDIRECTORY(${PROJECT_SOURCE_DIR}/library/cxl_ide_test_lib out/cxl_ide_test_lib.lib) ADD_SUBDIRECTORY(${LIBSPDM_DIR}/os_stub/rnglib out/spdm_rnglib.lib) ADD_SUBDIRECTORY(${LIBSPDM_DIR}/os_stub/platform_lib out/spdm_platform_lib.lib) ADD_SUBDIRECTORY(${LIBSPDM_DIR}/os_stub/platform_lib_null out/spdm_platform_lib_null.lib) @@ -252,9 +256,10 @@ ADD_COMPILE_OPTIONS(-DLIBSPDM_CONFIG="${PROJECT_SOURCE_DIR}/include/spdm_lib_con ADD_SUBDIRECTORY(${SPDM_EMU_DIR}/library/pci_doe_requester_lib out/pci_doe_requester_lib.lib) ADD_SUBDIRECTORY(${SPDM_EMU_DIR}/library/pci_ide_km_requester_lib out/pci_ide_km_requester_lib.lib) + ADD_SUBDIRECTORY(${SPDM_EMU_DIR}/library/cxl_ide_km_requester_lib out/cxl_ide_km_requester_lib.lib) ADD_SUBDIRECTORY(${SPDM_EMU_DIR}/library/pci_tdisp_requester_lib out/pci_tdisp_requester_lib.lib) ADD_SUBDIRECTORY(teeio_validator) - ADD_SUBDIRECTORY(tools) + # ADD_SUBDIRECTORY(tools) endif() \ No newline at end of file diff --git a/teeio-validator/teeio_validator/CMakeLists.txt b/teeio-validator/teeio_validator/CMakeLists.txt index d8e702d..75f1f89 100644 --- a/teeio-validator/teeio_validator/CMakeLists.txt +++ b/teeio-validator/teeio_validator/CMakeLists.txt @@ -16,6 +16,7 @@ INCLUDE_DIRECTORIES(${SPDM_DEVICE_DIR}/include ${LIBSPDM_DIR}/os_stub ${SPDM_EMU_DIR}/include ${SPDM_EMU_DIR}/spdm_emu/spdm_emu_common + ${TEEIO_VALIDATOR_DIR}/include ) SET(src_teeio_validator @@ -23,6 +24,7 @@ SET(src_teeio_validator cmdline.c ide_test_ini.c ide_test.c + test_factory.c ) SET(teeio_validator_LIBRARY @@ -30,6 +32,7 @@ SET(teeio_validator_LIBRARY helperlib spdmlib pcie_ide_test_lib + cxl_ide_test_lib ) ADD_EXECUTABLE(teeio_validator ${src_teeio_validator}) From 59a0101875eccbe05451208f1d2d364dcfda021c Mon Sep 17 00:00:00 2001 From: Min M Xu Date: Sun, 16 Jun 2024 21:18:19 -0400 Subject: [PATCH 08/11] Update pcie_ide_lib and pcie_ide_test_lib Signed-off-by: Min Xu --- .../pcie_ide_lib/include/pcie_ide_internal.h | 2 - .../library/pcie_ide_lib/intel_rp_pcie.c | 4 +- .../library/pcie_ide_lib/pcie_ide.c | 78 +++++++++++-------- .../test_case/ide_km_common.c | 10 +-- .../test_case/test_case_full.c | 8 +- .../test_case/test_case_full_keyrefresh.c | 6 +- .../test_case/test_case_ksetgo_1.c | 6 +- .../test_case/test_case_ksetgo_2.c | 6 +- .../test_case/test_case_ksetgo_3.c | 10 +-- .../test_case/test_case_ksetgo_4.c | 10 +-- .../test_case/test_case_ksetstop_1.c | 4 +- .../test_case/test_case_ksetstop_2.c | 4 +- .../test_case/test_case_ksetstop_3.c | 6 +- .../test_case/test_case_ksetstop_4.c | 6 +- .../test_config/test_config_common.c | 14 ++-- .../test_config/test_config_pcrc.c | 8 +- .../test_config_sel_ide_for_cfg_req.c | 12 +-- 17 files changed, 103 insertions(+), 91 deletions(-) diff --git a/teeio-validator/library/pcie_ide_lib/include/pcie_ide_internal.h b/teeio-validator/library/pcie_ide_lib/include/pcie_ide_internal.h index ff17212..ba1d52f 100644 --- a/teeio-validator/library/pcie_ide_lib/include/pcie_ide_internal.h +++ b/teeio-validator/library/pcie_ide_lib/include/pcie_ide_internal.h @@ -11,8 +11,6 @@ uint32_t get_ide_reg_block_offset(int fd, TEST_IDE_TYPE ide_type, uint8_t ide_id, uint32_t ide_ecap_offset); -bool init_pci_doe(int fd); - void enable_ide_stream_in_kcbar( INTEL_KEYP_ROOT_COMPLEX_KCBAR *const kcbar_ptr, const uint8_t rp_stream_index, diff --git a/teeio-validator/library/pcie_ide_lib/intel_rp_pcie.c b/teeio-validator/library/pcie_ide_lib/intel_rp_pcie.c index f451e0e..5eb9a57 100644 --- a/teeio-validator/library/pcie_ide_lib/intel_rp_pcie.c +++ b/teeio-validator/library/pcie_ide_lib/intel_rp_pcie.c @@ -223,7 +223,7 @@ bool unmap_kcbar_addr(int kcbar_mem_fd, uint8_t* mapped_kcbar_addr) // Parse the KEYP table and map the kcbar address -bool parse_keyp_table(ide_common_test_port_context_t *port_context) +bool parse_keyp_table(ide_common_test_port_context_t *port_context, INTEL_KEYP_PROTOCOL_TYPE keyp_protocol) { const char *keyp_table = "/sys/firmware/acpi/tables/KEYP"; const char KEYP_SIGNATURE[] = {'K', 'E', 'Y', 'P'}; @@ -278,7 +278,7 @@ bool parse_keyp_table(ide_common_test_port_context_t *port_context) { kcu = (INTEL_KEYP_KEY_CONFIGURATION_UNIT *)(buffer + offset); TEEIO_ASSERT(offset + kcu->Length <= size); - if (kcu->ProtocolType != 1) + if (kcu->ProtocolType != keyp_protocol) { offset += kcu->Length; continue; diff --git a/teeio-validator/library/pcie_ide_lib/pcie_ide.c b/teeio-validator/library/pcie_ide_lib/pcie_ide.c index 39e50cf..d11a889 100644 --- a/teeio-validator/library/pcie_ide_lib/pcie_ide.c +++ b/teeio-validator/library/pcie_ide_lib/pcie_ide.c @@ -184,10 +184,12 @@ bool close_root_port(ide_common_test_group_context_t *group_context) TEEIO_DEBUG((TEEIO_DEBUG_INFO, "close_root_port %s(%s)\n", port_context->port->port_name, port_context->port->bdf)); - port_context->addr_assoc_reg_block.addr_assoc1.raw = 0; - port_context->addr_assoc_reg_block.addr_assoc2.raw = 0; - port_context->rid_assoc_reg_block.rid_assoc1.raw = 0; - port_context->rid_assoc_reg_block.rid_assoc2.raw = 0; + PCIE_PRIV_DATA* pcie_data = &port_context->priv_data.pcie; + + pcie_data->addr_assoc_reg_block.addr_assoc1.raw = 0; + pcie_data->addr_assoc_reg_block.addr_assoc2.raw = 0; + pcie_data->rid_assoc_reg_block.rid_assoc1.raw = 0; + pcie_data->rid_assoc_reg_block.rid_assoc2.raw = 0; reset_ide_registers(port_context, group_context->top->type, 0, group_context->rp_stream_index, true); @@ -252,7 +254,7 @@ bool open_root_port(ide_common_test_port_context_t *port_context) port_context->ecap_offset = ecap_offset; // parse KEYP table and map the kcbar to user space - if (!parse_keyp_table(port_context)) + if (!parse_keyp_table(port_context, INTEL_KEYP_PROTOCOL_TYPE_PCIE_CXLIO)) { TEEIO_DEBUG((TEEIO_DEBUG_ERROR, "parse_keyp_table failed.\n")); goto InitRootPortFail; @@ -260,10 +262,11 @@ bool open_root_port(ide_common_test_port_context_t *port_context) // store the stream_cap in kcbar and pci_ide_cap in ecap(@configuration space) INTEL_KEYP_ROOT_COMPLEX_KCBAR *kcbar = (INTEL_KEYP_ROOT_COMPLEX_KCBAR *)port_context->mapped_kcbar_addr; - port_context->stream_cap.raw = mmio_read_reg32(&kcbar->capabilities); + PCIE_PRIV_DATA* pcie_data = &port_context->priv_data.pcie; + pcie_data->stream_cap.raw = mmio_read_reg32(&kcbar->capabilities); uint32_t offset = ecap_offset + 4; - port_context->ide_cap.raw = device_pci_read_32(offset, fd); + pcie_data->ide_cap.raw = device_pci_read_32(offset, fd); return true; @@ -333,7 +336,8 @@ bool find_free_rp_stream_index_and_ide_id(ide_common_test_port_context_t* port_c TEEIO_DEBUG((TEEIO_DEBUG_INFO, "find_free_rp_stream_index_and_ide_id for %s\n", port_context->port->port_name)); - PCIE_IDE_CAP ide_cap = {.raw = port_context->ide_cap.raw}; + PCIE_PRIV_DATA* pcie_data = &port_context->priv_data.pcie; + PCIE_IDE_CAP ide_cap = {.raw = pcie_data->ide_cap.raw}; int num_lnk_ide = ide_cap.lnk_ide_supported == 1 ? ide_cap.num_lnk_ide + 1 : 0; int num_sel_ide = ide_cap.sel_ide_supported == 1 ? ide_cap.num_sel_ide + 1 : 0; @@ -542,11 +546,12 @@ bool init_root_port(ide_common_test_group_context_t *group_context) TEEIO_DEBUG((TEEIO_DEBUG_INFO, "Host ide_id=%d, rp_stream_index=%d\n", ide_id, rp_stream_index)); group_context->rp_stream_index = rp_stream_index; - port_context->ide_id = ide_id; + PCIE_PRIV_DATA* pcie_data = &port_context->priv_data.pcie; + pcie_data->ide_id = ide_id; // rid & addr assoc_reg_block ide_common_test_port_context_t *lower_port_context = &group_context->lower_port; - populate_rid_assoc_reg_block(&port_context->rid_assoc_reg_block, lower_port_context->port->bus, lower_port_context->port->device, lower_port_context->port->function); + populate_rid_assoc_reg_block(&pcie_data->rid_assoc_reg_block, lower_port_context->port->bus, lower_port_context->port->device, lower_port_context->port->function); ide_common_test_switch_internal_conn_context_t *itr = NULL; char* bdf = NULL; @@ -568,17 +573,17 @@ bool init_root_port(ide_common_test_group_context_t *group_context) bdf = port_context->port->bdf; } - if(!populate_addr_assoc_reg_block(bdf, &port_context->addr_assoc_reg_block)) { + if(!populate_addr_assoc_reg_block(bdf, &pcie_data->addr_assoc_reg_block)) { goto InitHostFail; } TEEIO_DEBUG((TEEIO_DEBUG_INFO, "dump host assoc_reg_block:\n")); - dump_rid_assoc_reg_block(&port_context->rid_assoc_reg_block); - dump_addr_assoc_reg_block(&port_context->addr_assoc_reg_block); + dump_rid_assoc_reg_block(&pcie_data->rid_assoc_reg_block); + dump_addr_assoc_reg_block(&pcie_data->addr_assoc_reg_block); // kset // pre-allocate the slot_ids - if(!pre_alloc_slot_ids(group_context->rp_stream_index, group_context->k_set, port_context->stream_cap.num_rx_key_slots, false)) { + if(!pre_alloc_slot_ids(group_context->rp_stream_index, group_context->k_set, pcie_data->stream_cap.num_rx_key_slots, false)) { goto InitHostFail; } @@ -622,11 +627,13 @@ bool close_dev_port(ide_common_test_port_context_t *port_context, IDE_TEST_TOPOL { TEEIO_DEBUG((TEEIO_DEBUG_INFO, "close_dev_port %s(%s)\n", port_context->port->port_name, port_context->port->bdf)); + PCIE_PRIV_DATA* pcie_data = &port_context->priv_data.pcie; + // clean Link/Selective IDE Stream Control Registers - port_context->addr_assoc_reg_block.addr_assoc1.raw = 0; - port_context->addr_assoc_reg_block.addr_assoc2.raw = 0; - port_context->rid_assoc_reg_block.rid_assoc1.raw = 0; - port_context->rid_assoc_reg_block.rid_assoc2.raw = 0; + pcie_data->addr_assoc_reg_block.addr_assoc1.raw = 0; + pcie_data->addr_assoc_reg_block.addr_assoc2.raw = 0; + pcie_data->rid_assoc_reg_block.rid_assoc1.raw = 0; + pcie_data->rid_assoc_reg_block.rid_assoc2.raw = 0; reset_ide_registers(port_context, top_type, 0, 0, false); @@ -683,7 +690,8 @@ bool open_dev_port(ide_common_test_port_context_t *port_context) port_context->doe_offset = g_doe_extended_offset; uint32_t offset = ecap_offset + 4; - port_context->ide_cap.raw = device_pci_read_32(offset, fd); + PCIE_PRIV_DATA* pcie_data = &port_context->priv_data.pcie; + pcie_data->ide_cap.raw = device_pci_read_32(offset, fd); return true; @@ -714,19 +722,21 @@ bool init_dev_port(ide_common_test_group_context_t *group_context) if(!find_free_rp_stream_index_and_ide_id(port_context, NULL, &ide_id, top_type, false)) { goto InitDevFailed; } + + PCIE_PRIV_DATA* pcie_data = &port_context->priv_data.pcie; TEEIO_DEBUG((TEEIO_DEBUG_INFO, "Device ide_id = %d\n", ide_id)); - port_context->ide_id = ide_id; + pcie_data->ide_id = ide_id; // rid&addr assoc_reg_block - port_context->rid_assoc_reg_block.rid_assoc1.raw = m_rid_assoc_reg_block.rid_assoc1.raw; - port_context->rid_assoc_reg_block.rid_assoc2.raw = m_rid_assoc_reg_block.rid_assoc2.raw; - port_context->addr_assoc_reg_block.addr_assoc1.raw = m_addr_assoc_reg_block.addr_assoc1.raw; - port_context->addr_assoc_reg_block.addr_assoc2.raw = m_addr_assoc_reg_block.addr_assoc2.raw; - port_context->addr_assoc_reg_block.addr_assoc3.raw = m_addr_assoc_reg_block.addr_assoc3.raw; + pcie_data->rid_assoc_reg_block.rid_assoc1.raw = m_rid_assoc_reg_block.rid_assoc1.raw; + pcie_data->rid_assoc_reg_block.rid_assoc2.raw = m_rid_assoc_reg_block.rid_assoc2.raw; + pcie_data->addr_assoc_reg_block.addr_assoc1.raw = m_addr_assoc_reg_block.addr_assoc1.raw; + pcie_data->addr_assoc_reg_block.addr_assoc2.raw = m_addr_assoc_reg_block.addr_assoc2.raw; + pcie_data->addr_assoc_reg_block.addr_assoc3.raw = m_addr_assoc_reg_block.addr_assoc3.raw; TEEIO_DEBUG((TEEIO_DEBUG_INFO, "dump dev assoc_reg_block:\n")); - dump_rid_assoc_reg_block(&port_context->rid_assoc_reg_block); - dump_addr_assoc_reg_block(&port_context->addr_assoc_reg_block); + dump_rid_assoc_reg_block(&pcie_data->rid_assoc_reg_block); + dump_addr_assoc_reg_block(&pcie_data->addr_assoc_reg_block); return true; @@ -926,17 +936,19 @@ bool reset_ide_registers( PCIE_SEL_IDE_STREAM_CTRL stream_ctrl_reg = {.raw = 0}; stream_ctrl_reg.stream_id = stream_id; + PCIE_PRIV_DATA* pcie_data = &port_context->priv_data.pcie; + return setup_ide_ecap_regs( port_context->cfg_space_fd, ide_type, - port_context->ide_id, + pcie_data->ide_id, port_context->ecap_offset, stream_ctrl_reg, - port_context->rid_assoc_reg_block.rid_assoc1, - port_context->rid_assoc_reg_block.rid_assoc2, - port_context->addr_assoc_reg_block.addr_assoc1, - port_context->addr_assoc_reg_block.addr_assoc2, - port_context->addr_assoc_reg_block.addr_assoc3); + pcie_data->rid_assoc_reg_block.rid_assoc1, + pcie_data->rid_assoc_reg_block.rid_assoc2, + pcie_data->addr_assoc_reg_block.addr_assoc1, + pcie_data->addr_assoc_reg_block.addr_assoc2, + pcie_data->addr_assoc_reg_block.addr_assoc3); } void prime_rp_ide_key_set( diff --git a/teeio-validator/library/pcie_ide_test_lib/test_case/ide_km_common.c b/teeio-validator/library/pcie_ide_test_lib/test_case/ide_km_common.c index 2441658..5310b26 100644 --- a/teeio-validator/library/pcie_ide_test_lib/test_case/ide_km_common.c +++ b/teeio-validator/library/pcie_ide_test_lib/test_case/ide_km_common.c @@ -375,12 +375,12 @@ bool setup_ide_stream(void* doe_context, void* spdm_context, { NOT_IMPLEMENTED("selective_and_link_ide topoplogy"); } - enable_ide_stream_in_ecap(lower_port_cfg_space_fd, lower_port_ecap_offset, ide_type, lower_port->ide_id, true); + enable_ide_stream_in_ecap(lower_port_cfg_space_fd, lower_port_ecap_offset, ide_type, lower_port->priv_data.pcie.ide_id, true); // enable host ide stream enable_rootport_ide_stream(upper_port_cfg_space_fd, upper_port_ecap_offset, - ide_type, upper_port->ide_id, + ide_type, upper_port->priv_data.pcie.ide_id, kcbar_addr, rp_stream_index, true); @@ -388,7 +388,7 @@ bool setup_ide_stream(void* doe_context, void* spdm_context, libspdm_sleep(10 * 1000); // Now ide stream shall be in secure state - uint32_t data = read_stream_status_in_rp_ecap(upper_port_cfg_space_fd, upper_port_ecap_offset, ide_type, upper_port->ide_id); + uint32_t data = read_stream_status_in_rp_ecap(upper_port_cfg_space_fd, upper_port_ecap_offset, ide_type, upper_port->priv_data.pcie.ide_id); PCIE_SEL_IDE_STREAM_STATUS stream_status = {.raw = data}; if (stream_status.state != IDE_STREAM_STATUS_SECURE) { @@ -416,11 +416,11 @@ bool ide_key_switch_to(void* doe_context, void* spdm_context, } // step1: ensure host_ide and dev_ide is enabled - if(!is_ide_enabled(upper_port->cfg_space_fd, ide_type, upper_port->ide_id, upper_port->ecap_offset)) { + if(!is_ide_enabled(upper_port->cfg_space_fd, ide_type, upper_port->priv_data.pcie.ide_id, upper_port->ecap_offset)) { TEEIO_DEBUG((TEEIO_DEBUG_ERROR, "upper_port ide is not enabled.\n")); return false; } - if(!is_ide_enabled(lower_port->cfg_space_fd, ide_type, lower_port->ide_id, lower_port->ecap_offset)) { + if(!is_ide_enabled(lower_port->cfg_space_fd, ide_type, lower_port->priv_data.pcie.ide_id, lower_port->ecap_offset)) { TEEIO_DEBUG((TEEIO_DEBUG_ERROR, "lower_port ide is not enabled.\n")); return false; } diff --git a/teeio-validator/library/pcie_ide_test_lib/test_case/test_case_full.c b/teeio-validator/library/pcie_ide_test_lib/test_case/test_case_full.c index 0c81599..be90287 100644 --- a/teeio-validator/library/pcie_ide_test_lib/test_case/test_case_full.c +++ b/teeio-validator/library/pcie_ide_test_lib/test_case/test_case_full.c @@ -70,14 +70,14 @@ bool pcie_ide_test_full_1_run(void *test_context) dump_rootport_registers(group_context->upper_port.mapped_kcbar_addr, group_context->rp_stream_index, group_context->upper_port.cfg_space_fd, - group_context->upper_port.ide_id, + group_context->upper_port.priv_data.pcie.ide_id, group_context->upper_port.ecap_offset, ide_type); TEEIO_PRINT(("\n")); TEEIO_PRINT(("Print device registers.\n")); dump_dev_registers(group_context->lower_port.cfg_space_fd, - group_context->lower_port.ide_id, + group_context->lower_port.priv_data.pcie.ide_id, group_context->lower_port.ecap_offset, ide_type); @@ -181,12 +181,12 @@ bool test_full_teardown_common(void *test_context) NOT_IMPLEMENTED("selective_and_link_ide topoplogy"); } - enable_ide_stream_in_ecap(lower_port->cfg_space_fd, lower_port->ecap_offset, ide_type, lower_port->ide_id, false); + enable_ide_stream_in_ecap(lower_port->cfg_space_fd, lower_port->ecap_offset, ide_type, lower_port->priv_data.pcie.ide_id, false); // disable host ide stream enable_rootport_ide_stream(upper_port->cfg_space_fd, upper_port->ecap_offset, - ide_type, upper_port->ide_id, + ide_type, upper_port->priv_data.pcie.ide_id, upper_port->mapped_kcbar_addr, group_context->rp_stream_index, false); diff --git a/teeio-validator/library/pcie_ide_test_lib/test_case/test_case_full_keyrefresh.c b/teeio-validator/library/pcie_ide_test_lib/test_case/test_case_full_keyrefresh.c index 97f6b14..b0c9ba6 100644 --- a/teeio-validator/library/pcie_ide_test_lib/test_case/test_case_full_keyrefresh.c +++ b/teeio-validator/library/pcie_ide_test_lib/test_case/test_case_full_keyrefresh.c @@ -57,7 +57,7 @@ bool pcie_ide_test_full_keyrefresh_setup(void *test_context) // by default slot_ids are not allocated for key_refresh. // this case need to re-allocate slot_ids for key_refresh - if(!pre_alloc_slot_ids(group_context->rp_stream_index, group_context->k_set, upper_port->stream_cap.num_rx_key_slots, true)) { + if(!pre_alloc_slot_ids(group_context->rp_stream_index, group_context->k_set, upper_port->priv_data.pcie.stream_cap.num_rx_key_slots, true)) { return false; } @@ -108,14 +108,14 @@ bool pcie_ide_test_full_keyrefresh_run(void *test_context) dump_rootport_registers(group_context->upper_port.mapped_kcbar_addr, group_context->rp_stream_index, group_context->upper_port.cfg_space_fd, - group_context->upper_port.ide_id, + group_context->upper_port.priv_data.pcie.ide_id, group_context->upper_port.ecap_offset, ide_type); TEEIO_PRINT(("\n")); TEEIO_PRINT(("Print device registers.\n")); dump_dev_registers(group_context->lower_port.cfg_space_fd, - group_context->lower_port.ide_id, + group_context->lower_port.priv_data.pcie.ide_id, group_context->lower_port.ecap_offset, ide_type); diff --git a/teeio-validator/library/pcie_ide_test_lib/test_case/test_case_ksetgo_1.c b/teeio-validator/library/pcie_ide_test_lib/test_case/test_case_ksetgo_1.c index 1eda6d5..eb53501 100644 --- a/teeio-validator/library/pcie_ide_test_lib/test_case/test_case_ksetgo_1.c +++ b/teeio-validator/library/pcie_ide_test_lib/test_case/test_case_ksetgo_1.c @@ -223,7 +223,7 @@ bool pcie_ide_test_ksetgo_1_setup(void *test_context) return test_ksetgo_setup_common(group_context->doe_context, group_context->spdm_context, &group_context->session_id, group_context->upper_port.mapped_kcbar_addr, group_context->stream_id, group_context->rp_stream_index, - group_context->upper_port.ide_id, group_context->k_set, 0, PCIE_IDE_STREAM_KS0); + group_context->upper_port.priv_data.pcie.ide_id, group_context->k_set, 0, PCIE_IDE_STREAM_KS0); } bool pcie_ide_test_ksetgo_1_run(void *test_context) @@ -306,12 +306,12 @@ bool pcie_ide_test_ksetgo_1_run(void *test_context) { NOT_IMPLEMENTED("selective_and_link_ide topoplogy"); } - enable_ide_stream_in_ecap(group_context->lower_port.cfg_space_fd, group_context->lower_port.ecap_offset, ide_type, group_context->lower_port.ide_id, true); + enable_ide_stream_in_ecap(group_context->lower_port.cfg_space_fd, group_context->lower_port.ecap_offset, ide_type, group_context->lower_port.priv_data.pcie.ide_id, true); // enable host ide stream enable_rootport_ide_stream(group_context->upper_port.cfg_space_fd, group_context->upper_port.ecap_offset, - ide_type, group_context->upper_port.ide_id, + ide_type, group_context->upper_port.priv_data.pcie.ide_id, group_context->upper_port.mapped_kcbar_addr, group_context->rp_stream_index, true); diff --git a/teeio-validator/library/pcie_ide_test_lib/test_case/test_case_ksetgo_2.c b/teeio-validator/library/pcie_ide_test_lib/test_case/test_case_ksetgo_2.c index 9b2f5e9..a4806e1 100644 --- a/teeio-validator/library/pcie_ide_test_lib/test_case/test_case_ksetgo_2.c +++ b/teeio-validator/library/pcie_ide_test_lib/test_case/test_case_ksetgo_2.c @@ -39,7 +39,7 @@ bool pcie_ide_test_ksetgo_2_setup(void *test_context) return test_ksetgo_setup_common(group_context->doe_context, group_context->spdm_context, &group_context->session_id, group_context->upper_port.mapped_kcbar_addr, group_context->stream_id, group_context->rp_stream_index, - group_context->upper_port.ide_id, group_context->k_set, 0, PCIE_IDE_STREAM_KS1); + group_context->upper_port.priv_data.pcie.ide_id, group_context->k_set, 0, PCIE_IDE_STREAM_KS1); } bool pcie_ide_test_ksetgo_2_run(void *test_context) @@ -122,12 +122,12 @@ bool pcie_ide_test_ksetgo_2_run(void *test_context) { NOT_IMPLEMENTED("selective_and_link_ide topoplogy"); } - enable_ide_stream_in_ecap(group_context->lower_port.cfg_space_fd, group_context->lower_port.ecap_offset, ide_type, group_context->lower_port.ide_id, true); + enable_ide_stream_in_ecap(group_context->lower_port.cfg_space_fd, group_context->lower_port.ecap_offset, ide_type, group_context->lower_port.priv_data.pcie.ide_id, true); // enable host ide stream enable_rootport_ide_stream(group_context->upper_port.cfg_space_fd, group_context->upper_port.ecap_offset, - ide_type, group_context->upper_port.ide_id, + ide_type, group_context->upper_port.priv_data.pcie.ide_id, group_context->upper_port.mapped_kcbar_addr, group_context->rp_stream_index, true); diff --git a/teeio-validator/library/pcie_ide_test_lib/test_case/test_case_ksetgo_3.c b/teeio-validator/library/pcie_ide_test_lib/test_case/test_case_ksetgo_3.c index c067cf4..fee9792 100644 --- a/teeio-validator/library/pcie_ide_test_lib/test_case/test_case_ksetgo_3.c +++ b/teeio-validator/library/pcie_ide_test_lib/test_case/test_case_ksetgo_3.c @@ -44,7 +44,7 @@ bool pcie_ide_test_ksetgo_3_setup(void *test_context) // by default slot_ids are not allocated for key_refresh. // this case need to re-allocate slot_ids for key_refresh - if(!pre_alloc_slot_ids(group_context->rp_stream_index, group_context->k_set, upper_port->stream_cap.num_rx_key_slots, true)) { + if(!pre_alloc_slot_ids(group_context->rp_stream_index, group_context->k_set, upper_port->priv_data.pcie.stream_cap.num_rx_key_slots, true)) { return false; } @@ -142,12 +142,12 @@ bool test_ksetgo_3_run_phase1(void* doe_context, void* spdm_context, uint32_t* s { NOT_IMPLEMENTED("selective_and_link_ide topoplogy"); } - enable_ide_stream_in_ecap(lower_port->cfg_space_fd, lower_port->ecap_offset, ide_type, lower_port->ide_id, true); + enable_ide_stream_in_ecap(lower_port->cfg_space_fd, lower_port->ecap_offset, ide_type, lower_port->priv_data.pcie.ide_id, true); // enable host ide stream enable_rootport_ide_stream(upper_port->cfg_space_fd, upper_port->ecap_offset, - ide_type, upper_port->ide_id, + ide_type, upper_port->priv_data.pcie.ide_id, kcbar_addr, rp_stream_index, true); @@ -155,7 +155,7 @@ bool test_ksetgo_3_run_phase1(void* doe_context, void* spdm_context, uint32_t* s libspdm_sleep(10 * 1000); // Now ide stream shall be in secure state - uint32_t data = read_stream_status_in_rp_ecap(upper_port->cfg_space_fd, upper_port->ecap_offset, ide_type, upper_port->ide_id); + uint32_t data = read_stream_status_in_rp_ecap(upper_port->cfg_space_fd, upper_port->ecap_offset, ide_type, upper_port->priv_data.pcie.ide_id); PCIE_SEL_IDE_STREAM_STATUS stream_status = {.raw = data}; if (stream_status.state != IDE_STREAM_STATUS_SECURE) { @@ -275,7 +275,7 @@ bool pcie_ide_test_ksetgo_3_run(void *test_context) // phase 2 res = test_ksetgo_3_run_phase2(doe_context, spdm_context, &session_id, - stream_id, group_context->rp_stream_index, upper_port->ide_id, + stream_id, group_context->rp_stream_index, upper_port->priv_data.pcie.ide_id, upper_port->mapped_kcbar_addr, group_context->top->type); Done: diff --git a/teeio-validator/library/pcie_ide_test_lib/test_case/test_case_ksetgo_4.c b/teeio-validator/library/pcie_ide_test_lib/test_case/test_case_ksetgo_4.c index 3a4db19..140fbc2 100644 --- a/teeio-validator/library/pcie_ide_test_lib/test_case/test_case_ksetgo_4.c +++ b/teeio-validator/library/pcie_ide_test_lib/test_case/test_case_ksetgo_4.c @@ -44,7 +44,7 @@ bool pcie_ide_test_ksetgo_4_setup(void *test_context) // by default slot_ids are not allocated for key_refresh. // this case need to re-allocate slot_ids for key_refresh - if(!pre_alloc_slot_ids(group_context->rp_stream_index, group_context->k_set, upper_port->stream_cap.num_rx_key_slots, true)) { + if(!pre_alloc_slot_ids(group_context->rp_stream_index, group_context->k_set, upper_port->priv_data.pcie.stream_cap.num_rx_key_slots, true)) { return false; } @@ -141,12 +141,12 @@ bool test_ksetgo_4_run_phase1(void* doe_context, void* spdm_context, uint32_t* s { NOT_IMPLEMENTED("selective_and_link_ide topoplogy"); } - enable_ide_stream_in_ecap(lower_port->cfg_space_fd, lower_port->ecap_offset, ide_type, lower_port->ide_id, true); + enable_ide_stream_in_ecap(lower_port->cfg_space_fd, lower_port->ecap_offset, ide_type, lower_port->priv_data.pcie.ide_id, true); // enable host ide stream enable_rootport_ide_stream(upper_port->cfg_space_fd, upper_port->ecap_offset, - ide_type, upper_port->ide_id, + ide_type, upper_port->priv_data.pcie.ide_id, kcbar_addr, rp_stream_index, true); @@ -154,7 +154,7 @@ bool test_ksetgo_4_run_phase1(void* doe_context, void* spdm_context, uint32_t* s libspdm_sleep(10 * 1000); // Now ide stream shall be in secure state - uint32_t data = read_stream_status_in_rp_ecap(upper_port->cfg_space_fd, upper_port->ecap_offset, ide_type, upper_port->ide_id); + uint32_t data = read_stream_status_in_rp_ecap(upper_port->cfg_space_fd, upper_port->ecap_offset, ide_type, upper_port->priv_data.pcie.ide_id); PCIE_SEL_IDE_STREAM_STATUS stream_status = {.raw = data}; if (stream_status.state != IDE_STREAM_STATUS_SECURE) { @@ -275,7 +275,7 @@ bool pcie_ide_test_ksetgo_4_run(void *test_context) // phase 2 res = test_ksetgo_4_run_phase2(doe_context, spdm_context, &session_id, - stream_id, group_context->rp_stream_index, upper_port->ide_id, + stream_id, group_context->rp_stream_index, upper_port->priv_data.pcie.ide_id, upper_port->mapped_kcbar_addr, group_context->top->type); Done: diff --git a/teeio-validator/library/pcie_ide_test_lib/test_case/test_case_ksetstop_1.c b/teeio-validator/library/pcie_ide_test_lib/test_case/test_case_ksetstop_1.c index f23558f..e073342 100644 --- a/teeio-validator/library/pcie_ide_test_lib/test_case/test_case_ksetstop_1.c +++ b/teeio-validator/library/pcie_ide_test_lib/test_case/test_case_ksetstop_1.c @@ -148,12 +148,12 @@ bool pcie_ide_test_ksetstop_1_run(void *test_context) { NOT_IMPLEMENTED("selective_and_link_ide topoplogy"); } - enable_ide_stream_in_ecap(lower_port->cfg_space_fd, lower_port->ecap_offset, ide_type, lower_port->ide_id, false); + enable_ide_stream_in_ecap(lower_port->cfg_space_fd, lower_port->ecap_offset, ide_type, lower_port->priv_data.pcie.ide_id, false); // disable host ide stream enable_rootport_ide_stream(upper_port->cfg_space_fd, upper_port->ecap_offset, - ide_type, upper_port->ide_id, + ide_type, upper_port->priv_data.pcie.ide_id, upper_port->mapped_kcbar_addr, group_context->rp_stream_index, false); diff --git a/teeio-validator/library/pcie_ide_test_lib/test_case/test_case_ksetstop_2.c b/teeio-validator/library/pcie_ide_test_lib/test_case/test_case_ksetstop_2.c index e60f2c4..0faeca5 100644 --- a/teeio-validator/library/pcie_ide_test_lib/test_case/test_case_ksetstop_2.c +++ b/teeio-validator/library/pcie_ide_test_lib/test_case/test_case_ksetstop_2.c @@ -69,12 +69,12 @@ bool pcie_ide_test_ksetstop_2_run(void *test_context) { NOT_IMPLEMENTED("selective_and_link_ide topoplogy"); } - enable_ide_stream_in_ecap(lower_port->cfg_space_fd, lower_port->ecap_offset, ide_type, lower_port->ide_id, false); + enable_ide_stream_in_ecap(lower_port->cfg_space_fd, lower_port->ecap_offset, ide_type, lower_port->priv_data.pcie.ide_id, false); // disable host ide stream enable_rootport_ide_stream(upper_port->cfg_space_fd, upper_port->ecap_offset, - ide_type, upper_port->ide_id, + ide_type, upper_port->priv_data.pcie.ide_id, upper_port->mapped_kcbar_addr, group_context->rp_stream_index, false); diff --git a/teeio-validator/library/pcie_ide_test_lib/test_case/test_case_ksetstop_3.c b/teeio-validator/library/pcie_ide_test_lib/test_case/test_case_ksetstop_3.c index 1cfe334..173f196 100644 --- a/teeio-validator/library/pcie_ide_test_lib/test_case/test_case_ksetstop_3.c +++ b/teeio-validator/library/pcie_ide_test_lib/test_case/test_case_ksetstop_3.c @@ -38,7 +38,7 @@ bool pcie_ide_test_ksetstop_3_setup(void *test_context) // by default slot_ids are not allocated for key_refresh. // this case need to re-allocate slot_ids for key_refresh - if(!pre_alloc_slot_ids(group_context->rp_stream_index, group_context->k_set, upper_port->stream_cap.num_rx_key_slots, true)) { + if(!pre_alloc_slot_ids(group_context->rp_stream_index, group_context->k_set, upper_port->priv_data.pcie.stream_cap.num_rx_key_slots, true)) { return false; } @@ -85,12 +85,12 @@ bool pcie_ide_test_ksetstop_3_run(void *test_context) { NOT_IMPLEMENTED("selective_and_link_ide topoplogy"); } - enable_ide_stream_in_ecap(lower_port->cfg_space_fd, lower_port->ecap_offset, ide_type, lower_port->ide_id, false); + enable_ide_stream_in_ecap(lower_port->cfg_space_fd, lower_port->ecap_offset, ide_type, lower_port->priv_data.pcie.ide_id, false); // disable host ide stream enable_rootport_ide_stream(upper_port->cfg_space_fd, upper_port->ecap_offset, - ide_type, upper_port->ide_id, + ide_type, upper_port->priv_data.pcie.ide_id, upper_port->mapped_kcbar_addr, group_context->rp_stream_index, false); diff --git a/teeio-validator/library/pcie_ide_test_lib/test_case/test_case_ksetstop_4.c b/teeio-validator/library/pcie_ide_test_lib/test_case/test_case_ksetstop_4.c index 347e88a..cf48d72 100644 --- a/teeio-validator/library/pcie_ide_test_lib/test_case/test_case_ksetstop_4.c +++ b/teeio-validator/library/pcie_ide_test_lib/test_case/test_case_ksetstop_4.c @@ -38,7 +38,7 @@ bool pcie_ide_test_ksetstop_4_setup(void *test_context) // by default slot_ids are not allocated for key_refresh. // this case need to re-allocate slot_ids for key_refresh - if(!pre_alloc_slot_ids(group_context->rp_stream_index, group_context->k_set, upper_port->stream_cap.num_rx_key_slots, true)) { + if(!pre_alloc_slot_ids(group_context->rp_stream_index, group_context->k_set, upper_port->priv_data.pcie.stream_cap.num_rx_key_slots, true)) { return false; } @@ -87,12 +87,12 @@ bool pcie_ide_test_ksetstop_4_run(void *test_context) { NOT_IMPLEMENTED("selective_and_link_ide topoplogy"); } - enable_ide_stream_in_ecap(lower_port->cfg_space_fd, lower_port->ecap_offset, ide_type, lower_port->ide_id, false); + enable_ide_stream_in_ecap(lower_port->cfg_space_fd, lower_port->ecap_offset, ide_type, lower_port->priv_data.pcie.ide_id, false); // disable host ide stream enable_rootport_ide_stream(upper_port->cfg_space_fd, upper_port->ecap_offset, - ide_type, upper_port->ide_id, + ide_type, upper_port->priv_data.pcie.ide_id, upper_port->mapped_kcbar_addr, group_context->rp_stream_index, false); diff --git a/teeio-validator/library/pcie_ide_test_lib/test_config/test_config_common.c b/teeio-validator/library/pcie_ide_test_lib/test_config/test_config_common.c index fdee1b0..b5ec809 100644 --- a/teeio-validator/library/pcie_ide_test_lib/test_config/test_config_common.c +++ b/teeio-validator/library/pcie_ide_test_lib/test_config/test_config_common.c @@ -35,7 +35,7 @@ typedef enum } IDE_STREAM_STATUS_TYPE; // check if the ide_stream is secure or insecure -bool test_config_check_common(void *test_context, const char* assertion_msg) +bool pcie_ide_test_config_check_common(void *test_context) { ide_common_test_config_context_t *config_context = (ide_common_test_config_context_t *)test_context; TEEIO_ASSERT(config_context->signature == CONFIG_CONTEXT_SIGNATURE); @@ -44,6 +44,8 @@ bool test_config_check_common(void *test_context, const char* assertion_msg) TEEIO_ASSERT(group_context); TEEIO_ASSERT(group_context->signature == GROUP_CONTEXT_SIGNATURE); + const char* assertion_msg = "Check Common Assertion"; + ide_common_test_port_context_t *port = &group_context->upper_port; TEST_IDE_TYPE ide_type = TEST_IDE_TYPE_SEL_IDE; if (group_context->top->type == IDE_TEST_TOPOLOGY_TYPE_LINK_IDE) @@ -55,7 +57,7 @@ bool test_config_check_common(void *test_context, const char* assertion_msg) NOT_IMPLEMENTED("selective_and_link_ide topology"); } - uint32_t data = read_stream_status_in_rp_ecap(port->cfg_space_fd, port->ecap_offset, ide_type, port->ide_id); + uint32_t data = read_stream_status_in_rp_ecap(port->cfg_space_fd, port->ecap_offset, ide_type, port->priv_data.pcie.ide_id); PCIE_SEL_IDE_STREAM_STATUS stream_status = {.raw = data}; uint8_t state = stream_status.state; IDE_STREAM_STATUS_TYPE status = IDE_STREAM_STATUS_TYPE_UNKNOWN; @@ -146,7 +148,7 @@ static bool test_config_reset_ide_registers(ide_common_test_group_context_t *gro return true; } -bool test_config_enable_common(void *test_context) +bool pcie_ide_test_config_enable_common(void *test_context) { bool res = true; ide_common_test_config_context_t *config_context = (ide_common_test_config_context_t *)test_context; @@ -232,7 +234,7 @@ bool check_ft_supported_in_switch_port(char* bdf) return supported; } -bool test_config_support_common(void *test_context) +bool pcie_ide_test_config_support_common(void *test_context) { ide_common_test_config_context_t *config_context = (ide_common_test_config_context_t *)test_context; TEEIO_ASSERT(config_context->signature == CONFIG_CONTEXT_SIGNATURE); @@ -240,8 +242,8 @@ bool test_config_support_common(void *test_context) ide_common_test_group_context_t *group_context = config_context->group_context; TEEIO_ASSERT(group_context->signature == GROUP_CONTEXT_SIGNATURE); - PCIE_IDE_CAP *host_cap = &group_context->upper_port.ide_cap; - PCIE_IDE_CAP *dev_cap = &group_context->lower_port.ide_cap; + PCIE_IDE_CAP *host_cap = &group_context->upper_port.priv_data.pcie.ide_cap; + PCIE_IDE_CAP *dev_cap = &group_context->lower_port.priv_data.pcie.ide_cap; bool supported = false; if(group_context->top->type == IDE_TEST_TOPOLOGY_TYPE_SEL_IDE) { diff --git a/teeio-validator/library/pcie_ide_test_lib/test_config/test_config_pcrc.c b/teeio-validator/library/pcie_ide_test_lib/test_config/test_config_pcrc.c index bc67128..aa75270 100644 --- a/teeio-validator/library/pcie_ide_test_lib/test_config/test_config_pcrc.c +++ b/teeio-validator/library/pcie_ide_test_lib/test_config/test_config_pcrc.c @@ -39,9 +39,9 @@ static bool test_config_set_pcrc_common(void *test_context, bool enable) TEEIO_DEBUG((TEEIO_DEBUG_INFO, "%s pcrc for %s\n", enable ? "enable" : "disable", m_ide_test_topology_name[top->type])); ide_common_test_port_context_t *port_context = &group_context->upper_port; - set_pcrc_in_ecap(port_context->cfg_space_fd, ide_type, port_context->ide_id, port_context->ecap_offset, enable); + set_pcrc_in_ecap(port_context->cfg_space_fd, ide_type, port_context->priv_data.pcie.ide_id, port_context->ecap_offset, enable); port_context = &group_context->lower_port; - set_pcrc_in_ecap(port_context->cfg_space_fd, ide_type, port_context->ide_id, port_context->ecap_offset, enable); + set_pcrc_in_ecap(port_context->cfg_space_fd, ide_type, port_context->priv_data.pcie.ide_id, port_context->ecap_offset, enable); return true; } @@ -54,8 +54,8 @@ static bool test_config_check_pcrc_support_common(void *test_context) ide_common_test_group_context_t *group_context = config_context->group_context; TEEIO_ASSERT(group_context->signature == GROUP_CONTEXT_SIGNATURE); - PCIE_IDE_CAP *host_cap = &group_context->upper_port.ide_cap; - PCIE_IDE_CAP *dev_cap = &group_context->lower_port.ide_cap; + PCIE_IDE_CAP *host_cap = &group_context->upper_port.priv_data.pcie.ide_cap; + PCIE_IDE_CAP *dev_cap = &group_context->lower_port.priv_data.pcie.ide_cap; if(!host_cap->pcrc_supported || !dev_cap->pcrc_supported) { TEEIO_DEBUG((TEEIO_DEBUG_WARN, "check pcrc and it is NOT supported. host=%d, device=%d\n", host_cap->pcrc_supported, dev_cap->pcrc_supported)); return false; diff --git a/teeio-validator/library/pcie_ide_test_lib/test_config/test_config_sel_ide_for_cfg_req.c b/teeio-validator/library/pcie_ide_test_lib/test_config/test_config_sel_ide_for_cfg_req.c index de696bd..d543ddd 100644 --- a/teeio-validator/library/pcie_ide_test_lib/test_config/test_config_sel_ide_for_cfg_req.c +++ b/teeio-validator/library/pcie_ide_test_lib/test_config/test_config_sel_ide_for_cfg_req.c @@ -43,14 +43,14 @@ static bool test_config_set_sel_ide_for_cfg_req(void* test_context, bool enable) ide_common_test_port_context_t* port_context = &group_context->upper_port; set_sel_ide_for_cfg_req_in_ecap(port_context->cfg_space_fd, ide_type, - port_context->ide_id, + port_context->priv_data.pcie.ide_id, port_context->ecap_offset, enable); port_context = &group_context->lower_port; set_sel_ide_for_cfg_req_in_ecap(port_context->cfg_space_fd, ide_type, - port_context->ide_id, + port_context->priv_data.pcie.ide_id, port_context->ecap_offset, enable); @@ -74,8 +74,8 @@ static bool test_config_check_sel_ide_for_cfg_req_support(void* test_context) return false; } - PCIE_IDE_CAP *upper_cap = &group_context->upper_port.ide_cap; - PCIE_IDE_CAP *lower_cap = &group_context->lower_port.ide_cap; + PCIE_IDE_CAP *upper_cap = &group_context->upper_port.priv_data.pcie.ide_cap; + PCIE_IDE_CAP *lower_cap = &group_context->lower_port.priv_data.pcie.ide_cap; bool supported = upper_cap->sel_ide_cfg_req_supported && lower_cap->sel_ide_cfg_req_supported; TEEIO_DEBUG((TEEIO_DEBUG_INFO, "%s is %s.\n", m_config_name, supported ? "supported" : "NOT supported")); return supported; @@ -111,13 +111,13 @@ bool pcie_ide_test_config_check_sel_ide_for_cfg_req(void *test_context) ide_common_test_port_context_t* port_context = &group_context->upper_port; uint32_t data1 =read_ide_stream_ctrl_in_ecap(port_context->cfg_space_fd, ide_type, - port_context->ide_id, + port_context->priv_data.pcie.ide_id, port_context->ecap_offset); port_context = &group_context->lower_port; uint32_t data2 = read_ide_stream_ctrl_in_ecap(port_context->cfg_space_fd, ide_type, - port_context->ide_id, + port_context->priv_data.pcie.ide_id, port_context->ecap_offset); TEEIO_DEBUG((TEEIO_DEBUG_INFO, "Read ide_stream_ctrl : rootport = 0x%08x, dev = 0x%08x\n", data1, data2)); From 9fb52405fafb1ff1356c5872a7c0e2fd0c82376e Mon Sep 17 00:00:00 2001 From: Min M Xu Date: Sun, 16 Jun 2024 21:18:58 -0400 Subject: [PATCH 09/11] Update helperlib Signed-off-by: Min Xu --- teeio-validator/include/helperlib.h | 12 +++++ .../library/helperlib/ide_ini_helper.c | 29 ++++++++++ .../library/helperlib/pcie_helper.c | 53 ++++++++++++++++++- 3 files changed, 92 insertions(+), 2 deletions(-) diff --git a/teeio-validator/include/helperlib.h b/teeio-validator/include/helperlib.h index 5ec2083..787e3cb 100644 --- a/teeio-validator/include/helperlib.h +++ b/teeio-validator/include/helperlib.h @@ -18,8 +18,16 @@ void libspdm_sleep(uint64_t microseconds); // PCIE & MMIO helper APIs uint32_t device_pci_read_32 (uint32_t offset, int fp); void device_pci_write_32 (uint32_t offset, uint32_t data, int fp); + +uint16_t device_pci_read_16 (uint32_t offset, int fp); +void device_pci_write_16 (uint32_t offset, uint16_t data, int fp); + void mmio_write_reg32(void *const reg_ptr, const uint32_t reg_val); uint32_t mmio_read_reg32(void *reg_ptr); + +void mmio_write_reg64(void *const reg_ptr, const uint64_t reg_val); +uint64_t mmio_read_reg64(void *reg_ptr); + void reg_memcpy_dw(void *dst, uint64_t dst_bytes, void *src, uint64_t nbytes); bool parse_bdf_string(uint8_t* bdf, uint8_t* bus, uint8_t* device, uint8_t* function); bool is_valid_dev_func(uint8_t *df); @@ -30,6 +38,10 @@ uint8_t calculate_checksum(uint8_t *table, size_t length); // ide_test.ini helper APIs bool is_valid_topology_type(uint8_t *type); IDE_TEST_TOPOLOGY_TYPE get_topology_type_from_name(uint8_t* name); + +bool is_valid_ide_hw_type(uint8_t *type); +IDE_HW_TYPE get_ide_hw_type_from_name(const char* name); + bool is_valid_topology_connection(uint8_t *connection); IDE_TEST_CONNECT_TYPE get_connection_from_name(uint8_t* name); bool is_valid_port(IDE_TEST_PORTS_CONFIG *ports, uint8_t* port); diff --git a/teeio-validator/library/helperlib/ide_ini_helper.c b/teeio-validator/library/helperlib/ide_ini_helper.c index b57a64e..9b49d3b 100644 --- a/teeio-validator/library/helperlib/ide_ini_helper.c +++ b/teeio-validator/library/helperlib/ide_ini_helper.c @@ -22,6 +22,7 @@ extern const char *IDE_PORT_TYPE_NAMES[]; extern const char *IDE_TEST_IDE_TYPE_NAMES[]; extern const char *IDE_TEST_CONNECT_TYPE_NAMES[]; extern const char *IDE_TEST_TOPOLOGY_TYPE_NAMES[]; +extern const char *IDE_HW_TYPE_NAMES[]; bool is_valid_topology_connection(uint8_t *connection) { @@ -78,6 +79,34 @@ int get_port_id_from_name(IDE_TEST_PORTS_CONFIG *ports, uint8_t* port) return INVALID_PORT_ID; } +// IDE_HW_TYPE_NAMES +bool is_valid_ide_hw_type(uint8_t *type) +{ + if(type == NULL) { + return false; + } + for(int i = 0; i < IDE_HW_TYPE_NUM; i++) { + if(strcmp((const char*)type, IDE_HW_TYPE_NAMES[i]) == 0) { + return true; + } + } + return false; +} + +IDE_HW_TYPE get_ide_hw_type_from_name(const char* name) +{ + if(name == NULL) { + return IDE_HW_TYPE_NUM; + } + + for(int i = 0; i < IDE_HW_TYPE_NUM; i++) { + if(strcmp(name, IDE_HW_TYPE_NAMES[i]) == 0) { + return i; + } + } + return IDE_HW_TYPE_NUM; +} + // IDE_TEST_TOPOLOGY_TYPE_NAMES bool is_valid_topology_type(uint8_t *type) { diff --git a/teeio-validator/library/helperlib/pcie_helper.c b/teeio-validator/library/helperlib/pcie_helper.c index a1b9ec8..92211de 100644 --- a/teeio-validator/library/helperlib/pcie_helper.c +++ b/teeio-validator/library/helperlib/pcie_helper.c @@ -158,7 +158,7 @@ uint32_t device_pci_read_32(uint32_t off_to_the_cfg_start, int fd){ if(g_pci_log) { device = get_device_info_by_fd(fd); if(device) { - TEEIO_DEBUG((TEEIO_DEBUG_VERBOSE, "PCI_READ : 0x%04x => 0x%08x (%s)\n", off_to_the_cfg_start, data, device->device_name)); + TEEIO_DEBUG((TEEIO_DEBUG_VERBOSE, "PCI_READ32 : 0x%04x => 0x%08x (%s)\n", off_to_the_cfg_start, data, device->device_name)); } } @@ -176,11 +176,60 @@ void device_pci_write_32(uint32_t off_to_the_cfg_start, uint32_t value, int fd){ if(g_pci_log) { device = get_device_info_by_fd(fd); if(device) { - TEEIO_DEBUG((TEEIO_DEBUG_VERBOSE, "PCI_WRITE : 0x%04x <= 0x%08x (%s)\n", off_to_the_cfg_start, value, device->device_name)); + TEEIO_DEBUG((TEEIO_DEBUG_VERBOSE, "PCI_WRITE32 : 0x%04x <= 0x%08x (%s)\n", off_to_the_cfg_start, value, device->device_name)); } } } +uint16_t device_pci_read_16(uint32_t off_to_the_cfg_start, int fd){ + uint16_t data; + IDE_TEST_DEVICES_INFO *device = NULL; + + TEEIO_ASSERT (fd > 0); + + lseek(fd,off_to_the_cfg_start,SEEK_SET); + read(fd, &data, 2); + + if(g_pci_log) { + device = get_device_info_by_fd(fd); + if(device) { + TEEIO_DEBUG((TEEIO_DEBUG_VERBOSE, "PCI_READ16 : 0x%04x => 0x%04x (%s)\n", off_to_the_cfg_start, data, device->device_name)); + } + } + + return data; +} + +void device_pci_write_16(uint32_t off_to_the_cfg_start, uint16_t value, int fd){ + IDE_TEST_DEVICES_INFO *device = NULL; + + TEEIO_ASSERT (fd > 0); + + lseek(fd,off_to_the_cfg_start,SEEK_SET); + write(fd, &value, 2); + + if(g_pci_log) { + device = get_device_info_by_fd(fd); + if(device) { + TEEIO_DEBUG((TEEIO_DEBUG_VERBOSE, "PCI_WRITE16 : 0x%04x <= 0x%04x (%s)\n", off_to_the_cfg_start, value, device->device_name)); + } + } +} + +void mmio_write_reg64( + void *const reg_ptr, + const uint64_t reg_val) +{ + *(volatile uint64_t *)reg_ptr = reg_val; +} + +uint64_t mmio_read_reg64(void *reg_ptr) +{ + uint64_t data = 0; + data = *(volatile uint64_t *)reg_ptr; + return data; +} + void mmio_write_reg32( void *const reg_ptr, const uint32_t reg_val) From be6826ca3acaae76053b1623d1915d522d8399e7 Mon Sep 17 00:00:00 2001 From: Min M Xu Date: Sun, 16 Jun 2024 21:19:40 -0400 Subject: [PATCH 10/11] Other updates Signed-off-by: Min Xu --- teeio-validator/include/ide_tools.h | 2 +- teeio-validator/include/pcie_ide_lib.h | 7 +- teeio-validator/include/pcie_ide_test_lib.h | 5 + teeio-validator/teeio_validator/cmdline.c | 34 ++- teeio-validator/teeio_validator/ide_test.c | 252 ++------------------ teeio-validator/tools/ide_common.c | 2 +- 6 files changed, 62 insertions(+), 240 deletions(-) diff --git a/teeio-validator/include/ide_tools.h b/teeio-validator/include/ide_tools.h index 40124be..86ef2bb 100644 --- a/teeio-validator/include/ide_tools.h +++ b/teeio-validator/include/ide_tools.h @@ -36,6 +36,6 @@ ide_common_test_switch_internal_conn_context_t *alloc_switch_internal_conn_conte bool scan_open_devices_in_top(IDE_TEST_CONFIG *test_config, int top_id, DEVCIES_CONTEXT *devices_context); bool read_ide_cap_ctrl_register(IDE_PORT* port, uint32_t *ide_cap, uint32_t *ide_ctrl); bool parse_ide_test_init(IDE_TEST_CONFIG *test_config, const char *ide_test_ini); -ide_test_case_name_t *get_test_case_from_string(const char *test_case_name, int *index); +// ide_test_case_name_t *get_test_case_from_string(const char *test_case_name, int *index, IDE_HW_TYPE ide_type); #endif diff --git a/teeio-validator/include/pcie_ide_lib.h b/teeio-validator/include/pcie_ide_lib.h index a5f43fd..50c1942 100644 --- a/teeio-validator/include/pcie_ide_lib.h +++ b/teeio-validator/include/pcie_ide_lib.h @@ -15,6 +15,11 @@ // PCIE APIs // +/** + * initialize pcie doe +*/ +bool init_pci_doe(int fd); + /** * open PCIE's configuration space */ @@ -170,7 +175,7 @@ get_stream_cfg_reg_block( /** * parse KEYP table */ -bool parse_keyp_table(ide_common_test_port_context_t *port_context); +bool parse_keyp_table(ide_common_test_port_context_t *port_context, INTEL_KEYP_PROTOCOL_TYPE keyp_protocol); /** * map KCBAR into memory diff --git a/teeio-validator/include/pcie_ide_test_lib.h b/teeio-validator/include/pcie_ide_test_lib.h index d01e308..ef56d3a 100644 --- a/teeio-validator/include/pcie_ide_test_lib.h +++ b/teeio-validator/include/pcie_ide_test_lib.h @@ -107,6 +107,11 @@ bool pcie_ide_test_full_keyrefresh_teardown(void *test_context); // PCIE_IDE Test Config // +// common function +bool pcie_ide_test_config_enable_common(void *test_context); +bool pcie_ide_test_config_check_common(void *test_context); +bool pcie_ide_test_config_support_common(void *test_context); + // default config bool pcie_ide_test_config_default_enable_common(void *test_context); bool pcie_ide_test_config_default_disable_common(void *test_context); diff --git a/teeio-validator/teeio_validator/cmdline.c b/teeio-validator/teeio_validator/cmdline.c index e080650..61fe151 100644 --- a/teeio-validator/teeio_validator/cmdline.c +++ b/teeio-validator/teeio_validator/cmdline.c @@ -16,6 +16,7 @@ #include "helperlib.h" #include "ide_test.h" +#include "teeio_validator_internal.h" extern const char *IDE_PORT_TYPE_NAMES[]; extern const char *IDE_TEST_IDE_TYPE_NAMES[]; @@ -37,7 +38,7 @@ extern bool g_libspdm_log; extern uint8_t g_scan_bus; extern bool g_run_test_suite; -bool is_valid_test_case(const char* test_case_name); +bool is_valid_test_case(const char* test_case_name, IDE_HW_TYPE ide_type); void print_usage() { @@ -54,6 +55,7 @@ void print_usage() TEEIO_PRINT((" -s : Test case to be tested. For example Test.IdeStream\n")); TEEIO_PRINT((" -l : Set debug level. error/warn/info/verbose\n")); TEEIO_PRINT((" -b : Bus number in hex format. For example 0x1a\n")); + TEEIO_PRINT((" -i : ide type. pcie/cxl.io/cxl.mem\n")); TEEIO_PRINT((" -h : Display this usage\n")); } @@ -65,7 +67,9 @@ bool parse_cmdline_option(int argc, char *argv[], char* file_name, IDE_TEST_CONF int opt, v; uint8_t data8; char buf[MAX_LINE_LENGTH] = {0}; + char test_case_name[MAX_CASE_NAME_LENGTH] = {0}; int pos = 0; + IDE_HW_TYPE ide_type = IDE_HW_TYPE_PCIE; TEEIO_ASSERT(argc > 0); TEEIO_ASSERT(argv != NULL); @@ -85,7 +89,7 @@ bool parse_cmdline_option(int argc, char *argv[], char* file_name, IDE_TEST_CONF } TEEIO_PRINT(("%s\n", buf)); - while ((opt = getopt(argc, argv, "f:t:c:s:l:b:h")) != -1) { + while ((opt = getopt(argc, argv, "f:t:c:s:l:i:b:h")) != -1) { switch (opt) { case 'f': if(!validate_file_name(optarg)) { @@ -96,12 +100,8 @@ bool parse_cmdline_option(int argc, char *argv[], char* file_name, IDE_TEST_CONF break; case 's': - if(!is_valid_test_case(optarg)) { - TEEIO_DEBUG((TEEIO_DEBUG_ERROR, "Invalid -f parameter. %s\n", optarg)); - return false; - } - sprintf(g_test_case, "%s", optarg); - g_run_test_suite = false; + strncpy(test_case_name, optarg, MAX_CASE_NAME_LENGTH); + // we will check the test_case_name later because it depends on ide_type which is designated by -i break; case 't': @@ -135,6 +135,14 @@ bool parse_cmdline_option(int argc, char *argv[], char* file_name, IDE_TEST_CONF case 'l': *debug_level = get_ide_log_level_from_string(optarg); break; + + case 'i': + ide_type = get_ide_hw_type_from_name(optarg); + if(ide_type == IDE_HW_TYPE_NUM) { + TEEIO_DEBUG((TEEIO_DEBUG_ERROR, "Invalid -i parameter. %s\n", optarg)); + return false; + } + break; case 'h': *print_usage = true; @@ -145,5 +153,15 @@ bool parse_cmdline_option(int argc, char *argv[], char* file_name, IDE_TEST_CONF } } + if(strlen(test_case_name) > 0) { + // test_case is designated in command line + if(!is_valid_test_case(test_case_name, ide_type)) { + TEEIO_DEBUG((TEEIO_DEBUG_ERROR, "Invalid -f parameter. %s\n", test_case_name)); + return false; + } + sprintf(g_test_case, "%s", test_case_name); + g_run_test_suite = false; + } + return true; } diff --git a/teeio-validator/teeio_validator/ide_test.c b/teeio-validator/teeio_validator/ide_test.c index 217ce54..6a0b2c2 100644 --- a/teeio-validator/teeio_validator/ide_test.c +++ b/teeio-validator/teeio_validator/ide_test.c @@ -11,10 +11,8 @@ #include "helperlib.h" #include "ide_test.h" #include "pcie_ide_test_lib.h" - -bool test_config_enable_common(void *test_context); -bool test_config_check_common(void *test_context, const char* assertion_msg); -bool test_config_support_common(void *test_context); +#include "cxl_ide_test_lib.h" +#include "test_factory.h" void append_config_item(ide_run_test_config_item_t **head, ide_run_test_config_item_t* new) { @@ -70,225 +68,6 @@ uint32_t m_top_config_bitmasks[] = { (uint32_t)SELECTIVE_LINK_IDE_CONFIGURATION_BITMASK }; -ide_test_config_funcs_t m_config_funcs[IDE_TEST_TOPOLOGY_TYPE_NUM][IDE_TEST_CONFIGURATION_TYPE_NUM] = { - { // selective_ide - { // Default Config - pcie_ide_test_config_default_enable_common, - pcie_ide_test_config_default_disable_common, - pcie_ide_test_config_default_support_common, - pcie_ide_test_config_default_check_common - }, - {NULL, NULL, NULL, NULL}, // switch - {NULL, NULL, NULL, NULL}, // partial header encryption - { // pcrc - pcie_ide_test_config_pcrc_enable_sel, - pcie_ide_test_config_pcrc_disable_sel, - pcie_ide_test_config_pcrc_support_sel, - pcie_ide_test_config_pcrc_check_sel - }, - {NULL, NULL, NULL, NULL}, // aggregation - { // selective_ide for configuration request - pcie_ide_test_config_enable_sel_ide_for_cfg_req, - pcie_ide_test_config_disable_sel_ide_for_cfg_req, - pcie_ide_test_config_support_sel_ide_for_cfg_req, - pcie_ide_test_config_check_sel_ide_for_cfg_req - }, - {NULL, NULL, NULL, NULL} // tee_limited_stream - }, - { // link_ide - { - // Default Config - pcie_ide_test_config_default_enable_common, - pcie_ide_test_config_default_disable_common, - pcie_ide_test_config_default_support_common, - pcie_ide_test_config_default_check_common - }, - - {NULL, NULL, NULL, NULL}, - {NULL, NULL, NULL, NULL}, - - { - // pcrc - pcie_ide_test_config_pcrc_enable_link, - pcie_ide_test_config_pcrc_disable_link, - pcie_ide_test_config_pcrc_support_link, - pcie_ide_test_config_pcrc_check_link - }, - - {NULL, NULL, NULL, NULL}, - {NULL, NULL, NULL, NULL}, - {NULL, NULL, NULL, NULL} - }, - { // selective_and_link_ide - { - // Default Config - pcie_ide_test_config_default_enable_sel_link, - pcie_ide_test_config_default_disable_sel_link, - pcie_ide_test_config_default_support_sel_link, - pcie_ide_test_config_default_check_sel_link - }, - {NULL, NULL, NULL, NULL}, - {NULL, NULL, NULL, NULL}, - { - // pcrc - pcie_ide_test_config_pcrc_enable_sel_link, - pcie_ide_test_config_pcrc_disable_sel_link, - pcie_ide_test_config_pcrc_support_sel_link, - pcie_ide_test_config_pcrc_check_sel_link - }, - {NULL, NULL, NULL, NULL}, - {NULL, NULL, NULL, NULL}, - {NULL, NULL, NULL, NULL} - } -}; - -ide_test_group_funcs_t m_group_funcs[] = { - { // selective_ide - pcie_ide_test_group_setup_sel, - pcie_ide_test_group_teardown_sel - }, - { // link_ide - pcie_ide_test_group_setup_link, - pcie_ide_test_group_teardown_link - }, - { // selective_link_ide - pcie_ide_test_group_setup_sel_link, - pcie_ide_test_group_teardown_sel_link - } -}; - -#define TEST_CLASS_CASE_NAMES "IdeStream,KeyRefresh" - -ide_test_case_name_t m_test_case_names[IDE_COMMON_TEST_CASE_NUM] = { - {"Query", "1,2", IDE_COMMON_TEST_CASE_QUERY}, - {"KeyProg", "1,2,3,4,5,6", IDE_COMMON_TEST_CASE_KEYPROG}, - {"KSetGo", "1,2,3,4", IDE_COMMON_TEST_CASE_KSETGO}, - {"KSetStop", "1,2,3,4", IDE_COMMON_TEST_CASE_KSETSTOP}, - {"SpdmSession", "1,2", IDE_COMMON_TEST_CASE_SPDMSESSION}, - {"Test", TEST_CLASS_CASE_NAMES, IDE_COMMON_TEST_CASE_TEST} -}; - -ide_test_case_funcs_t m_test_case_funcs[IDE_COMMON_TEST_CASE_NUM][MAX_CASE_ID] = { - // Query - { - { pcie_ide_test_query_1_setup, pcie_ide_test_query_1_run, pcie_ide_test_query_1_teardown, false }, - { pcie_ide_test_query_2_setup, pcie_ide_test_query_2_run, pcie_ide_test_query_2_teardown, false }, - {NULL, NULL, NULL, false}, - {NULL, NULL, NULL, false}, - {NULL, NULL, NULL, false}, - {NULL, NULL, NULL, false}, - }, - // KeyProg - { - {pcie_ide_test_keyprog_1_setup, pcie_ide_test_keyprog_1_run, pcie_ide_test_keyprog_1_teardown, false}, - {pcie_ide_test_keyprog_2_setup, pcie_ide_test_keyprog_2_run, pcie_ide_test_keyprog_2_teardown, false}, - {pcie_ide_test_keyprog_3_setup, pcie_ide_test_keyprog_3_run, pcie_ide_test_keyprog_3_teardown, false}, - {pcie_ide_test_keyprog_4_setup, pcie_ide_test_keyprog_4_run, pcie_ide_test_keyprog_4_teardown, false}, - {pcie_ide_test_keyprog_5_setup, pcie_ide_test_keyprog_5_run, pcie_ide_test_keyprog_5_teardown, false}, - {pcie_ide_test_keyprog_6_setup, pcie_ide_test_keyprog_6_run, pcie_ide_test_keyprog_6_teardown, false} - }, - // KSetGo - { - { pcie_ide_test_ksetgo_1_setup, pcie_ide_test_ksetgo_1_run, pcie_ide_test_ksetgo_1_teardown, true }, - { pcie_ide_test_ksetgo_2_setup, pcie_ide_test_ksetgo_2_run, pcie_ide_test_ksetgo_2_teardown, true }, - { pcie_ide_test_ksetgo_3_setup, pcie_ide_test_ksetgo_3_run, pcie_ide_test_ksetgo_3_teardown, true }, - { pcie_ide_test_ksetgo_4_setup, pcie_ide_test_ksetgo_4_run, pcie_ide_test_ksetgo_4_teardown, true }, - {NULL, NULL, NULL, false}, - {NULL, NULL, NULL, false} - }, - // KSetStop - { - { pcie_ide_test_ksetstop_1_setup, pcie_ide_test_ksetstop_1_run, pcie_ide_test_ksetstop_1_teardown, false }, - { pcie_ide_test_ksetstop_2_setup, pcie_ide_test_ksetstop_2_run, pcie_ide_test_ksetstop_2_teardown, false }, - { pcie_ide_test_ksetstop_3_setup, pcie_ide_test_ksetstop_3_run, pcie_ide_test_ksetstop_3_teardown, false }, - { pcie_ide_test_ksetstop_4_setup, pcie_ide_test_ksetstop_4_run, pcie_ide_test_ksetstop_4_teardown, false }, - {NULL, NULL, NULL, false}, - {NULL, NULL, NULL, false} - }, - // SpdmSession - { - {NULL, NULL, NULL}, - {NULL, NULL, NULL}, - {NULL, NULL, NULL}, - {NULL, NULL, NULL}, - {NULL, NULL, NULL}, - {NULL, NULL, NULL} - }, - // Test Full - { - { pcie_ide_test_full_1_setup, pcie_ide_test_full_1_run, pcie_ide_test_full_1_teardown, false }, // IdeStream - { pcie_ide_test_full_keyrefresh_setup, pcie_ide_test_full_keyrefresh_run, pcie_ide_test_full_keyrefresh_teardown, false }, // KeyRefresh - {NULL, NULL, NULL}, - {NULL, NULL, NULL}, - {NULL, NULL, NULL}, - {NULL, NULL, NULL} - } -}; - -ide_test_case_name_t* get_test_case_from_string(const char* test_case_name, int* index) -{ - if(test_case_name == NULL) { - return NULL; - } - char buf1[MAX_LINE_LENGTH] = {0}; - char buf2[MAX_LINE_LENGTH] = {0}; - strncpy(buf1, test_case_name, MAX_LINE_LENGTH); - - int pos = find_char_in_str(buf1, '.'); - if(pos == -1) { - return NULL; - } - - buf1[pos] = '\0'; - char* ptr1 = buf1 + pos + 1; - - int i = 0; - for(; i < IDE_COMMON_TEST_CASE_NUM; i++) { - if(strcmp(buf1, m_test_case_names[i].class) == 0) { - break; - } - } - if(i == IDE_COMMON_TEST_CASE_NUM) { - return NULL; - } - - bool hit = false; - strncpy(buf2, m_test_case_names[i].names, MAX_LINE_LENGTH); - char *ptr2 = buf2; - int j = 0; - - pos = find_char_in_str(ptr2, ','); - - do { - if(pos != -1) { - ptr2[pos] = '\0'; - } - if(strcmp(ptr1, ptr2) == 0) { - hit = true; - break; - } - - if(pos == -1) { - break; - } - - ptr2 += (pos + 1); - pos = find_char_in_str(ptr2, ','); - j++; - } while(true); - - if(index != NULL) { - *index = j; - } - - return hit ? m_test_case_names + i : NULL; -} - -bool is_valid_test_case(const char* test_case_name) -{ - return get_test_case_from_string(test_case_name, NULL) != NULL; -} - ide_run_test_suite_t *alloc_run_test_suite(IDE_TEST_SUITE *suite, IDE_TEST_CONFIG *test_config) { ide_run_test_suite_t *rts = (ide_run_test_suite_t *)malloc(sizeof(ide_run_test_suite_t)); @@ -314,7 +93,8 @@ bool alloc_run_test_config_item(ide_run_test_config_t *rtc, int config_type, IDE TEEIO_ASSERT(top_type < IDE_TEST_TOPOLOGY_TYPE_NUM); TEEIO_ASSERT(config_type < IDE_TEST_CONFIGURATION_TYPE_NUM); - ide_test_config_funcs_t *config_func = &m_config_funcs[top_type][config_type]; + // ide_test_config_funcs_t *config_func = &m_config_funcs[top_type][config_type]; + ide_test_config_funcs_t *config_func = test_factory_get_test_config_funcs(IDE_HW_TYPE_PCIE, top_type, config_type); ide_run_test_config_item_t *config_item = (ide_run_test_config_item_t*)malloc(sizeof(ide_run_test_config_item_t)); TEEIO_ASSERT(config_item != NULL); @@ -457,7 +237,8 @@ ide_run_test_group_t *alloc_run_test_group(ide_run_test_suite_t *rts, IDE_TEST_C sprintf(run_test_group->name, "%s", m_ide_test_topology_name[top->type]); - ide_test_group_funcs_t *group_funcs = &m_group_funcs[top->type]; + // ide_test_group_funcs_t *group_funcs = &m_group_funcs[top->type]; + ide_test_group_funcs_t *group_funcs = test_factory_get_test_group_funcs(IDE_HW_TYPE_PCIE, top->type); run_test_group->setup_func = group_funcs->setup; run_test_group->teardown_func = group_funcs->teardown; @@ -516,7 +297,8 @@ bool alloc_run_test_case(ide_run_test_group_t *run_test_group, IDE_COMMON_TEST_C sprintf(run_test_case->name, "%s.%d", m_ide_test_case_name[(int)test_case], case_id); // run_test_case->action = IDE_COMMON_TEST_ACTION_RUN; - ide_test_case_funcs_t* case_funcs = &m_test_case_funcs[test_case][case_id - 1]; + // ide_test_case_funcs_t* case_funcs = &m_test_case_funcs[test_case][case_id - 1]; + ide_test_case_funcs_t* case_funcs = test_factory_get_test_case_funcs(IDE_HW_TYPE_PCIE, test_case, case_id - 1); run_test_case->run_func = case_funcs->run; run_test_case->setup_func = case_funcs->setup; run_test_case->teardown_func = case_funcs->teardown; @@ -702,7 +484,11 @@ static bool do_run_test_config_support(ide_run_test_config_t *run_test_config) { bool ret = false; - if(!test_config_support_common(run_test_config->test_context)) { + // if(!test_config_support_common(run_test_config->test_context)) { + // return false; + // } + ide_common_test_config_support_func_t support_func = test_factory_get_common_test_config_support_func(IDE_HW_TYPE_PCIE); + if(!support_func(run_test_config->test_context)) { return false; } @@ -721,7 +507,11 @@ static bool do_run_test_config_enable(ide_run_test_config_t *run_test_config) { bool ret = false; - if(!test_config_enable_common(run_test_config->test_context)) { + // if(!test_config_enable_common(run_test_config->test_context)) { + // return false; + // } + ide_common_test_config_enable_func_t enable_func = test_factory_get_common_test_config_enable_func(IDE_HW_TYPE_PCIE); + if(!enable_func(run_test_config->test_context)) { return false; } @@ -740,7 +530,11 @@ static bool do_run_test_config_check(ide_run_test_config_t *run_test_config) { bool ret = false; - if(!test_config_check_common(run_test_config->test_context, "Check Common Assertion")) { + // if(!test_config_check_common(run_test_config->test_context)) { + // return false; + // } + ide_common_test_config_check_func_t check_func = test_factory_get_common_test_config_check_func(IDE_HW_TYPE_PCIE); + if(!check_func(run_test_config->test_context)) { return false; } diff --git a/teeio-validator/tools/ide_common.c b/teeio-validator/tools/ide_common.c index b66f80b..5c5517f 100644 --- a/teeio-validator/tools/ide_common.c +++ b/teeio-validator/tools/ide_common.c @@ -202,7 +202,7 @@ bool read_ide_cap_ctrl_register(IDE_PORT* port, uint32_t *ide_cap, uint32_t *ide return ret; } -ide_test_case_name_t *get_test_case_from_string(const char *test_case_name, int *index) +ide_test_case_name_t *get_test_case_from_string(const char *test_case_name, int *index, IDE_HW_TYPE ide_type) { return NULL; } From 92bf3c48b27db43861df60f1ac0ca0a83edd8fec Mon Sep 17 00:00:00 2001 From: Min M Xu Date: Wed, 19 Jun 2024 21:50:45 -0400 Subject: [PATCH 11/11] Update code for CXL.mem test Signed-off-by: Min Xu --- teeio-validator/include/cxl.h | 386 ++++++++++++------ teeio-validator/include/ide_test.h | 9 + teeio-validator/include/pcie.h | 10 +- teeio-validator/library/cxl_ide_lib/cxl_ide.c | 218 ++++++++-- .../cxl_ide_test_lib/test_group/test_group.c | 9 + .../library/pcie_ide_lib/pcie_ide.c | 6 +- teeio-validator/library/spdmlib/spdm.c | 13 +- teeio-validator/teeio_validator/ide_test.c | 34 +- 8 files changed, 490 insertions(+), 195 deletions(-) diff --git a/teeio-validator/include/cxl.h b/teeio-validator/include/cxl.h index 54c2929..4f0c42f 100644 --- a/teeio-validator/include/cxl.h +++ b/teeio-validator/include/cxl.h @@ -16,224 +16,340 @@ #pragma pack(1) -typedef union { - struct { - uint16_t vendor_id; - uint16_t revision:4; - uint16_t length:12; +typedef union +{ + struct + { + uint16_t vendor_id; + uint16_t revision : 4; + uint16_t length : 12; }; uint32_t raw; } CXL_DVS_HEADER1; -typedef union { - struct { +typedef union +{ + struct + { uint16_t id; }; uint16_t raw; } CXL_DVS_HEADER2; -typedef union { - struct { - uint8_t cache_capable:1; - uint8_t io_capable:1; - uint8_t mem_capable:1; - uint8_t mem_hwinit_mode:1; - uint8_t hdm_count:2; - uint8_t cache_writeback_and_invalidate_capable:1; - uint8_t cxl_reset_capable:1; - - uint8_t cxl_reset_timeout:3; - uint8_t cxl_mem_clr_capable:1; - uint8_t tsp_capable:1; - uint8_t multiple_logical_device:1; - uint8_t viral_capable:1; - uint8_t pm_init_completion_reporting_capable:1; +typedef union +{ + struct + { + uint8_t cache_capable : 1; + uint8_t io_capable : 1; + uint8_t mem_capable : 1; + uint8_t mem_hwinit_mode : 1; + uint8_t hdm_count : 2; + uint8_t cache_writeback_and_invalidate_capable : 1; + uint8_t cxl_reset_capable : 1; + + uint8_t cxl_reset_timeout : 3; + uint8_t cxl_mem_clr_capable : 1; + uint8_t tsp_capable : 1; + uint8_t multiple_logical_device : 1; + uint8_t viral_capable : 1; + uint8_t pm_init_completion_reporting_capable : 1; }; uint16_t raw; } CXL_CAPABILITY; -typedef union { - struct { - uint8_t cache_enable:1; - uint8_t io_enable:1; - uint8_t mem_enable:1; - uint8_t cache_sf_coverage:5; - - uint8_t cache_sf_granularity:3; - uint8_t cache_clean_eviction:1; - uint8_t direct_p2p_mem_enable:1; - uint8_t rsvd0:1; - uint8_t viral_enable:1; - uint8_t rsvd1:1; +typedef union +{ + struct + { + uint8_t cache_enable : 1; + uint8_t io_enable : 1; + uint8_t mem_enable : 1; + uint8_t cache_sf_coverage : 5; + + uint8_t cache_sf_granularity : 3; + uint8_t cache_clean_eviction : 1; + uint8_t direct_p2p_mem_enable : 1; + uint8_t rsvd0 : 1; + uint8_t viral_enable : 1; + uint8_t rsvd1 : 1; }; uint16_t raw; } CXL_CONTROL; -typedef union { - struct { - uint16_t rsvd0:14; - uint16_t viral_status:1; - uint16_t rsvd1:1; +typedef union +{ + struct + { + uint16_t rsvd0 : 14; + uint16_t viral_status : 1; + uint16_t rsvd1 : 1; }; uint16_t raw; } CXL_STATUS; -typedef union { - struct { - uint16_t disable_caching:1; - uint16_t initiate_cache_write_back_and_invalidation:1; - uint16_t initiate_cxl_reset:1; - uint16_t cxl_reset_mem_clr_enable:1; - uint16_t desired_volatile_hdm_state_after_hot_reset:1; - uint16_t modified_completion_enable:1; - uint16_t rsvd:10; +typedef union +{ + struct + { + uint16_t disable_caching : 1; + uint16_t initiate_cache_write_back_and_invalidation : 1; + uint16_t initiate_cxl_reset : 1; + uint16_t cxl_reset_mem_clr_enable : 1; + uint16_t desired_volatile_hdm_state_after_hot_reset : 1; + uint16_t modified_completion_enable : 1; + uint16_t rsvd : 10; }; uint16_t raw; } CXL_CONTROL2; -typedef union { - struct { - uint16_t cache_invalid:1; - uint16_t cxl_reset_complete:1; - uint16_t cxl_reset_error:1; - uint16_t volatile_hdm_preservation_error:1; - uint16_t rsvd:11; - uint16_t power_management_initialization_complete:1; +typedef union +{ + struct + { + uint16_t cache_invalid : 1; + uint16_t cxl_reset_complete : 1; + uint16_t cxl_reset_error : 1; + uint16_t volatile_hdm_preservation_error : 1; + uint16_t rsvd : 11; + uint16_t power_management_initialization_complete : 1; }; uint16_t raw; } CXL_STATUS2; -typedef union { - struct { - uint16_t config_lock:15; - uint16_t rsvd:1; +typedef union +{ + struct + { + uint16_t config_lock : 15; + uint16_t rsvd : 1; }; uint16_t raw; } CXL_LOCK; -typedef union { - struct { - uint8_t cache_size_unit:4; - uint8_t fallback_capability:2; - uint8_t modified_completion_capable:1; - uint8_t no_clean_writeback:1; +typedef union +{ + struct + { + uint8_t cache_size_unit : 4; + uint8_t fallback_capability : 2; + uint8_t modified_completion_capable : 1; + uint8_t no_clean_writeback : 1; uint8_t cache_size; }; uint16_t raw; } CXL_CAPABILITY2; -typedef union { - struct { +typedef union +{ + struct + { uint32_t memory_size_high; }; uint32_t raw; } CXL_RANGE_SIZE_HIGH; -typedef union { - struct { - uint8_t memory_info_valid:1; - uint8_t memory_active:1; - uint8_t media_type:3; - uint8_t memory_class:3; - - uint8_t desired_interleave:5; - uint8_t memory_active_timeout:3; - - uint16_t memory_active_degraded:1; - uint16_t rsvd:11; - uint16_t memory_size_low:4; +typedef union +{ + struct + { + uint8_t memory_info_valid : 1; + uint8_t memory_active : 1; + uint8_t media_type : 3; + uint8_t memory_class : 3; + + uint8_t desired_interleave : 5; + uint8_t memory_active_timeout : 3; + + uint16_t memory_active_degraded : 1; + uint16_t rsvd : 11; + uint16_t memory_size_low : 4; }; uint32_t raw; } CXL_RANGE_SIZE_LOW; -typedef union { - struct { +typedef union +{ + struct + { uint32_t memory_base_high; }; uint32_t raw; } CXL_RANGE_BASE_HIGH; -typedef union { - struct { - uint32_t rsvd:28; - uint32_t memory_base_low:4; +typedef union +{ + struct + { + uint32_t rsvd : 28; + uint32_t memory_base_low : 4; }; uint32_t raw; } CXL_RANGE_BASE_LOW; -typedef union { - struct { - uint16_t default_volatile_hdm_state_after_cold_reset:1; - uint16_t default_volatile_hdm_state_after_warm_reset:1; - uint16_t default_volatile_hdm_state_after_hot_reset:1; - uint16_t volatile_hdm_state_after_hot_reset:1; - uint16_t direct_p2p_mem_capable:1; - uint16_t rsvd:11; +typedef union +{ + struct + { + uint16_t default_volatile_hdm_state_after_cold_reset : 1; + uint16_t default_volatile_hdm_state_after_warm_reset : 1; + uint16_t default_volatile_hdm_state_after_hot_reset : 1; + uint16_t volatile_hdm_state_after_hot_reset : 1; + uint16_t direct_p2p_mem_capable : 1; + uint16_t rsvd : 11; }; uint16_t raw; } CXL_CAPABILITY3; -typedef struct { +typedef struct +{ CXL_RANGE_SIZE_HIGH high; - CXL_RANGE_SIZE_LOW low; + CXL_RANGE_SIZE_LOW low; } CXL_RANGE_SIZE; -typedef struct { +typedef struct +{ CXL_RANGE_BASE_HIGH high; - CXL_RANGE_BASE_LOW low; + CXL_RANGE_BASE_LOW low; } CXL_RANGE_BASE; -// Figure 8-1 -typedef struct { - PCIE_CAP_ID ide_ecap; +typedef struct +{ + PCIE_CAP_ID ide_ecap; CXL_DVS_HEADER1 header1; CXL_DVS_HEADER2 header2; - CXL_CAPABILITY capability; - CXL_CONTROL control; - CXL_STATUS status; - CXL_CONTROL2 control2; - CXL_STATUS2 status2; - CXL_LOCK lock; +} CXL_DVSEC_COMMON_HEADER; + +// Section 8.1.3 +// PCIe DVSEC for CXL Device +// D2 mandatory +typedef struct +{ + CXL_DVSEC_COMMON_HEADER common_header; + CXL_CAPABILITY capability; + CXL_CONTROL control; + CXL_STATUS status; + CXL_CONTROL2 control2; + CXL_STATUS2 status2; + CXL_LOCK lock; CXL_CAPABILITY2 capability2; - CXL_RANGE_SIZE range1_size; - CXL_RANGE_BASE range1_base; - CXL_RANGE_SIZE range2_size; - CXL_RANGE_BASE range2_base; + CXL_RANGE_SIZE range1_size; + CXL_RANGE_BASE range1_base; + CXL_RANGE_SIZE range2_size; + CXL_RANGE_BASE range2_base; CXL_CAPABILITY3 capability3; - uint16_t rsvd; -} CXL_DVSEC; + uint16_t rsvd; +} CXL_DVSEC_FOR_DEVICE; + +// Section 8.1.5 +// CXL Extensions DVSEC for Ports +// R/DSP/USP mandatory +typedef struct { + CXL_DVSEC_COMMON_HEADER common_header; + // other fields +} CXL_DVSEC_FOR_PORTS; + +// Section 8.1.6 +// GPF DVSEC for CXL Ports +// R/DSP mandatory +typedef struct { + CXL_DVSEC_COMMON_HEADER common_header; + // other fields +} CXL_GPF_DVSEC_FOR_PORTS; + +// Section 8.1.7 +// GPF DVSEC for CXL Devices +// D2 mandatory +typedef struct { + CXL_DVSEC_COMMON_HEADER common_header; + // other fields +} CXL_GPF_DVSEC_FOR_DEVICES; + +// Section 8.1.8 +// PCIe DVSEC for Flex Bus Port +// D2/R mandatory +typedef struct { + CXL_DVSEC_COMMON_HEADER common_header; + // other fields +} CXL_DVSEC_FOR_FLEX_BUS_PORT; + +// Section 8.1.9 +// Register Locator DVSEC +// D2/R mandatory +typedef union { + struct { + uint8_t register_bir:3; + uint8_t rsvd:5; + uint8_t register_block_id; + uint16_t register_block_offset_low; + }; + uint32_t raw; +} CXL_REGISTER_OFFSET_LOW; + +typedef struct { + uint32_t register_block_offset_high; +} CXL_REGISTER_OFFSET_HIGH; + +typedef struct { + CXL_REGISTER_OFFSET_LOW low; + CXL_REGISTER_OFFSET_HIGH high; +} CXL_REGISTER_BLOCK; + +typedef struct { + CXL_DVSEC_COMMON_HEADER common_header; + uint16_t rsvd; + // variable count of reg_blocks + // CXL_REGISTER_BLOCK reg_block; +} CXL_DVSEC_REGISTER_LOCATOR; #pragma pack(0) +#define DVSEC_VENDOR_ID_CXL 0x1E98 + +typedef enum +{ + CXL_IDE_STREAM_DIRECTION_RX = 0, + CXL_IDE_STREAM_DIRECTION_TX, + CXL_IDE_STREAM_DIRECTION_NUM +} CXL_IDE_STREAM_DIRECTION; + +// Table 8-2 typedef enum { - CXL_IDE_STREAM_DIRECTION_RX = 0, - CXL_IDE_STREAM_DIRECTION_TX, - CXL_IDE_STREAM_DIRECTION_NUM -} CXL_IDE_STREAM_DIRECTION ; - -#define CXL_DVS_HEADER1_OFFSET (sizeof(PCIE_CAP_ID)) -#define CXL_DVS_HEADER2_OFFSET (CXL_DVS_HEADER1_OFFSET + sizeof(CXL_DVS_HEADER1)) -#define CXL_CAPABILITY_OFFSET (CXL_DVS_HEADER2_OFFSET + sizeof(CXL_DVS_HEADER2)) -#define CXL_CONTROL_OFFSET (CXL_CAPABILITY_OFFSET + sizeof(CXL_CAPABILITY)) -#define CXL_STATUS_OFFSET (CXL_CONTROL_OFFSET + sizeof(CXL_CONTROL)) -#define CXL_CONTROL2_OFFSET (CXL_STATUS_OFFSET + sizeof(CXL_STATUS)) -#define CXL_STATUS2_OFFSET (CXL_CONTROL2_OFFSET + sizeof(CXL_CONTROL2)) -#define CXL_LOCK_OFFSET (CXL_STATUS2_OFFSET + sizeof(CXL_STATUS2)) -#define CXL_CAPABILITY2_OFFSET (CXL_LOCK_OFFSET + sizeof(CXL_LOCK)) + CXL_DVSEC_ID_PCIE_DVSEC_FOR_CXL_DEVICES = 0, + CXL_DVSEC_ID_NON_CXL_FUNCTION_MAP_DVSEC = 0x2, + CXL_DVSEC_ID_CXL_EXTENSIONS_DVSEC_FOR_PORTS = 0x3, + CXL_DVSEC_ID_GPF_DVSEC_FOR_CXL_PORTS = 0x4, + CXL_DVSEC_ID_GPF_DVSEC_FOR_CXL_DEVICES = 0x5, + CXL_DVSEC_ID_PCIE_DVSEC_FOR_FLEX_BUS_PORT = 0x7, + CXL_DVSEC_ID_REGISTER_LOCATOR_DVSEC = 0x8, + CXL_DVSEC_ID_MLD_DVSEC = 0x09, + CXL_DVSEC_ID_PCIE_DVSEC_FOR_TEST_CAP = 0xA, + CXL_DVSEC_IN_INVALID = 0xFF +} CXL_DVSEC_ID; + +#define CXL_DVS_HEADER1_OFFSET (sizeof(PCIE_CAP_ID)) +#define CXL_DVS_HEADER2_OFFSET (CXL_DVS_HEADER1_OFFSET + sizeof(CXL_DVS_HEADER1)) +#define CXL_CAPABILITY_OFFSET (CXL_DVS_HEADER2_OFFSET + sizeof(CXL_DVS_HEADER2)) +#define CXL_CONTROL_OFFSET (CXL_CAPABILITY_OFFSET + sizeof(CXL_CAPABILITY)) +#define CXL_STATUS_OFFSET (CXL_CONTROL_OFFSET + sizeof(CXL_CONTROL)) +#define CXL_CONTROL2_OFFSET (CXL_STATUS_OFFSET + sizeof(CXL_STATUS)) +#define CXL_STATUS2_OFFSET (CXL_CONTROL2_OFFSET + sizeof(CXL_CONTROL2)) +#define CXL_LOCK_OFFSET (CXL_STATUS2_OFFSET + sizeof(CXL_STATUS2)) +#define CXL_CAPABILITY2_OFFSET (CXL_LOCK_OFFSET + sizeof(CXL_LOCK)) #define CXL_RANGE1_SIZE_HIGH_OFFSET (CXL_CAPABILITY2_OFFSET + sizeof(CXL_CAPABILITY2)) -#define CXL_RANGE1_SIZE_LOW_OFFSET (CXL_RANGE1_SIZE_HIGH_OFFSET + sizeof(CXL_RANGE_SIZE_HIGH)) +#define CXL_RANGE1_SIZE_LOW_OFFSET (CXL_RANGE1_SIZE_HIGH_OFFSET + sizeof(CXL_RANGE_SIZE_HIGH)) #define CXL_RANGE1_BASE_HIGH_OFFSET (CXL_RANGE1_SIZE_LOW_OFFSET + sizeof(CXL_RANGE_SIZE_LOW)) -#define CXL_RANGE1_BASE_LOW_OFFSET (CXL_RANGE1_BASE_HIGH_OFFSET + sizeof(CXL_RANGE_BASE_HIGH)) +#define CXL_RANGE1_BASE_LOW_OFFSET (CXL_RANGE1_BASE_HIGH_OFFSET + sizeof(CXL_RANGE_BASE_HIGH)) #define CXL_RANGE2_SIZE_HIGH_OFFSET (CXL_RANGE1_BASE_LOW_OFFSET + sizeof(CXL_RANGE_BASE_LOW)) -#define CXL_RANGE2_SIZE_LOW_OFFSET (CXL_RANGE2_SIZE_HIGH_OFFSET + sizeof(CXL_RANGE_SIZE_HIGH)) +#define CXL_RANGE2_SIZE_LOW_OFFSET (CXL_RANGE2_SIZE_HIGH_OFFSET + sizeof(CXL_RANGE_SIZE_HIGH)) #define CXL_RANGE2_BASE_HIGH_OFFSET (CXL_RANGE2_SIZE_LOW_OFFSET + sizeof(CXL_RANGE_SIZE_LOW)) -#define CXL_RANGE2_BASE_LOW_OFFSET (CXL_RANGE2_BASE_HIGH_OFFSET + sizeof(CXL_RANGE_BASE_HIGH)) +#define CXL_RANGE2_BASE_LOW_OFFSET (CXL_RANGE2_BASE_HIGH_OFFSET + sizeof(CXL_RANGE_BASE_HIGH)) -#define CXL_CAPABILITY3_OFFSET (CXL_RANGE2_BASE_LOW_OFFSET + sizeof(CXL_RANGE_BASE_LOW)) +#define CXL_CAPABILITY3_OFFSET (CXL_RANGE2_BASE_LOW_OFFSET + sizeof(CXL_RANGE_BASE_LOW)) #endif \ No newline at end of file diff --git a/teeio-validator/include/ide_test.h b/teeio-validator/include/ide_test.h index aa8a404..545dbd6 100644 --- a/teeio-validator/include/ide_test.h +++ b/teeio-validator/include/ide_test.h @@ -336,6 +336,12 @@ typedef struct { PCIE_SEL_IDE_ADDR_ASSOC_REG_BLOCK addr_assoc_reg_block; } PCIE_PRIV_DATA; +#define MAX_IDE_TEST_DVSEC_COUNT 16 +typedef struct { + uint32_t offset; // offset in configuration space + CXL_DVSEC_ID dvsec_id; // DVSEC ID. 0xff is invalid DVSEC +} IDE_TEST_CXL_PCIE_DVSEC; + typedef struct { // ecap data CXL_CAPABILITY cap; @@ -344,6 +350,9 @@ typedef struct { // key programming data INTEL_KEYP_CXL_LINK_ENC_GLOBAL_CONFIG link_enc_global_config; + + // DVSECs in Configuration Space + IDE_TEST_CXL_PCIE_DVSEC desecs[MAX_IDE_TEST_DVSEC_COUNT]; } CXL_PRIV_DATA; typedef union { diff --git a/teeio-validator/include/pcie.h b/teeio-validator/include/pcie.h index 1fa8d3b..2b51554 100644 --- a/teeio-validator/include/pcie.h +++ b/teeio-validator/include/pcie.h @@ -259,8 +259,12 @@ enum PCIE_IDE_STREAM_KEY_SUB_STREAM_ENUM { #define IDE_STREAM_STATUS_SECURE 2 #define IDE_STREAM_STATUS_INSECURE 0 -#define PCI_DOE_EXT_CAPABILITY_ID 0x002E -#define PCI_IDE_EXT_CAPABILITY_ID 0x0030 -#define PCI_AER_EXT_CAPABILITY_ID 0x0001 +#define PCIE_CONFIG_SPACE_SIZE 0x1000 +#define PCIE_EXT_CAP_START 0x100 + +#define PCI_DOE_EXT_CAPABILITY_ID 0x002E +#define PCI_IDE_EXT_CAPABILITY_ID 0x0030 +#define PCI_AER_EXT_CAPABILITY_ID 0x0001 +#define PCI_DVSCE_EXT_CAPABILITY_ID 0x0023 #endif \ No newline at end of file diff --git a/teeio-validator/library/cxl_ide_lib/cxl_ide.c b/teeio-validator/library/cxl_ide_lib/cxl_ide.c index 0d29d13..c99f2f6 100644 --- a/teeio-validator/library/cxl_ide_lib/cxl_ide.c +++ b/teeio-validator/library/cxl_ide_lib/cxl_ide.c @@ -48,6 +48,119 @@ bool cxl_init_root_port(ide_common_test_group_context_t *group_context) return true; } +// walk thru configuration space to find out all CXL DVSEC +bool cxl_find_dvsec_in_config_space(int fd, IDE_TEST_CXL_PCIE_DVSEC* dvsec, int* count) +{ + uint32_t walker = PCIE_EXT_CAP_START; + uint32_t cap_ext_header = 0; + int dvsec_cnt = 0; + CXL_DVSEC_COMMON_HEADER header = {0}; + + TEEIO_ASSERT(dvsec != NULL); + TEEIO_ASSERT(count != NULL); + + TEEIO_DEBUG((TEEIO_DEBUG_INFO, "cxl_find_dvsec_in_config_space\n")); + + while (walker < PCIE_CONFIG_SPACE_SIZE && walker != 0) + { + cap_ext_header = device_pci_read_32(walker, fd); + + if (((PCIE_CAP_ID *)&cap_ext_header)->id == PCI_DVSCE_EXT_CAPABILITY_ID) + { + header.ide_ecap.raw = device_pci_read_32(walker, fd); + header.header1.raw = device_pci_read_32(walker + 4, fd); + header.header2.raw = device_pci_read_16(walker + 8, fd); + + if(header.header1.vendor_id == DVSEC_VENDOR_ID_CXL) { + // This is CXL DVSEC block + TEEIO_ASSERT(dvsec_cnt < *count); + dvsec->offset = walker; + dvsec->dvsec_id = header.header2.id; + dvsec += 1; + dvsec_cnt += 1; + } + } + + walker = ((PCIE_CAP_ID *)&cap_ext_header)->next_cap_offset; + } + + *count = dvsec_cnt; + + return true; +} + +static CXL_DVSEC_ID mandatory_rootport_dvsec_id[] = { + CXL_DVSEC_ID_CXL_EXTENSIONS_DVSEC_FOR_PORTS, + CXL_DVSEC_ID_GPF_DVSEC_FOR_CXL_PORTS, + CXL_DVSEC_ID_PCIE_DVSEC_FOR_FLEX_BUS_PORT, + CXL_DVSEC_ID_REGISTER_LOCATOR_DVSEC, + CXL_DVSEC_IN_INVALID +}; + +static CXL_DVSEC_ID mandatory_endpoint_dvsec_id[] = { + CXL_DVSEC_ID_PCIE_DVSEC_FOR_CXL_DEVICES, + CXL_DVSEC_ID_GPF_DVSEC_FOR_CXL_DEVICES, + CXL_DVSEC_ID_PCIE_DVSEC_FOR_FLEX_BUS_PORT, + CXL_DVSEC_ID_REGISTER_LOCATOR_DVSEC, + CXL_DVSEC_IN_INVALID +}; + +// check if CXL DVSECs in rootport are valid +bool cxl_check_rootport_dvsecs(IDE_TEST_CXL_PCIE_DVSEC* dvsec, int count) +{ + bool valid = false; + int i = 0; + + while(mandatory_rootport_dvsec_id[i] != CXL_DVSEC_IN_INVALID) { + valid = false; + + for(int j = 0; j < count; j++) { + if(mandatory_rootport_dvsec_id[i] == dvsec[j].dvsec_id) { + valid = true; + break; + } + } + if(!valid) { + break; + } + i++; + } + + return valid; +} + +// check if CXL DVSECs in endpoint are valid +bool cxl_check_ep_dvsec(IDE_TEST_CXL_PCIE_DVSEC* dvsec, int count) +{ + bool valid = false; + int i = 0; + + while(mandatory_endpoint_dvsec_id[i] != CXL_DVSEC_IN_INVALID) { + valid = false; + + for(int j = 0; j < count; j++) { + if(mandatory_endpoint_dvsec_id[i] == dvsec[j].dvsec_id) { + valid = true; + break; + } + } + if(!valid) { + break; + } + i++; + } + + return valid; +} + +void cxl_dump_dvsecs(IDE_TEST_CXL_PCIE_DVSEC* dvsec, int count) +{ + TEEIO_DEBUG((TEEIO_DEBUG_INFO, "Dump CXL DVSECs\n")); + for(int i = 0; i < count; i++) { + TEEIO_DEBUG((TEEIO_DEBUG_INFO, " DVSEC %04x, offset = 0x%04x\n", dvsec[i].dvsec_id, dvsec[i].offset)); + } +} + /* * Open rootcomplex port */ @@ -68,18 +181,33 @@ bool cxl_open_root_port(ide_common_test_port_context_t *port_context) sprintf(str, "cxl.host : %s", port->bdf); set_deivce_info(fd, str); - uint32_t ecap_offset = get_extended_cap_offset(fd, PCI_IDE_EXT_CAPABILITY_ID); - if (ecap_offset == 0) - { - TEEIO_DEBUG((TEEIO_DEBUG_ERROR, "ECAP Offset of CXL IDE is NOT found\n")); + int dvsec_cnt = MAX_IDE_TEST_DVSEC_COUNT; + if(!cxl_find_dvsec_in_config_space(fd, port_context->priv_data.cxl.desecs, &dvsec_cnt)) { + TEEIO_DEBUG((TEEIO_DEBUG_ERROR, "Find CXL DVSECs failed.\n")); goto InitRootPortFail; } - else - { - TEEIO_DEBUG((TEEIO_DEBUG_INFO, "ECAP Offset of CXL IDE: 0x%016x\n", ecap_offset)); + + cxl_dump_dvsecs(port_context->priv_data.cxl.desecs, dvsec_cnt); + + // check CXL DVSECs + if(!cxl_check_rootport_dvsecs(port_context->priv_data.cxl.desecs, dvsec_cnt)) { + TEEIO_DEBUG((TEEIO_DEBUG_ERROR, "Check CXL DVSECs failed.\n")); + goto InitRootPortFail; } - port_context->ecap_offset = ecap_offset; + + // uint32_t ecap_offset = get_extended_cap_offset(fd, PCI_IDE_EXT_CAPABILITY_ID); + // if (ecap_offset == 0) + // { + // TEEIO_DEBUG((TEEIO_DEBUG_ERROR, "ECAP Offset of CXL IDE is NOT found\n")); + // goto InitRootPortFail; + // } + // else + // { + // TEEIO_DEBUG((TEEIO_DEBUG_INFO, "ECAP Offset of CXL IDE: 0x%016x\n", ecap_offset)); + // } + + port_context->ecap_offset = 0; // parse KEYP table and map the kcbar to user space if (!parse_keyp_table(port_context, INTEL_KEYP_PROTOCOL_TYPE_CXL_MEMCACHE)) @@ -93,16 +221,16 @@ bool cxl_open_root_port(ide_common_test_port_context_t *port_context) CXL_PRIV_DATA * cxl_data = &port_context->priv_data.cxl; cxl_data->link_enc_global_config.raw = mmio_read_reg32(&kcbar->link_enc_global_config); - // check CXL_DVS_HEADER1 CXL_DVS_HEADER2 - CXL_DVS_HEADER1 header1 = {.raw = device_pci_read_32(ecap_offset + CXL_DVS_HEADER1_OFFSET, fd)}; - CXL_DVS_HEADER2 header2 = {.raw = device_pci_read_16(ecap_offset + CXL_DVS_HEADER2_OFFSET, fd)}; - TEEIO_DEBUG((TEEIO_DEBUG_INFO, "CXL Rootport (%s) header1=0x%08x, header2=0x%04x\n", port->bdf, header1.raw, header2.raw)); + // // check CXL_DVS_HEADER1 CXL_DVS_HEADER2 + // CXL_DVS_HEADER1 header1 = {.raw = device_pci_read_32(ecap_offset + CXL_DVS_HEADER1_OFFSET, fd)}; + // CXL_DVS_HEADER2 header2 = {.raw = device_pci_read_16(ecap_offset + CXL_DVS_HEADER2_OFFSET, fd)}; + // TEEIO_DEBUG((TEEIO_DEBUG_INFO, "CXL Rootport (%s) header1=0x%08x, header2=0x%04x\n", port->bdf, header1.raw, header2.raw)); - // read and save cap/cap2/cap3 - cxl_data->cap.raw = device_pci_read_16(ecap_offset + CXL_CAPABILITY_OFFSET, fd); - cxl_data->cap2.raw = device_pci_read_16(ecap_offset + CXL_CAPABILITY2_OFFSET, fd); - cxl_data->cap3.raw = device_pci_read_16(ecap_offset + CXL_CAPABILITY3_OFFSET, fd); - TEEIO_DEBUG((TEEIO_DEBUG_INFO, "CXL Rootport (%s) cap=0x%04x, cap2=0x%04x, cap3=0x%04x\n", port->bdf, cxl_data->cap.raw, cxl_data->cap2.raw, cxl_data->cap3.raw)); + // // read and save cap/cap2/cap3 + // cxl_data->cap.raw = device_pci_read_16(ecap_offset + CXL_CAPABILITY_OFFSET, fd); + // cxl_data->cap2.raw = device_pci_read_16(ecap_offset + CXL_CAPABILITY2_OFFSET, fd); + // cxl_data->cap3.raw = device_pci_read_16(ecap_offset + CXL_CAPABILITY3_OFFSET, fd); + // TEEIO_DEBUG((TEEIO_DEBUG_INFO, "CXL Rootport (%s) cap=0x%04x, cap2=0x%04x, cap3=0x%04x\n", port->bdf, cxl_data->cap.raw, cxl_data->cap2.raw, cxl_data->cap3.raw)); return true; @@ -198,6 +326,8 @@ bool cxl_open_dev_port(ide_common_test_port_context_t *port_context) char str[MAX_NAME_LENGTH] = {0}; + TEEIO_DEBUG((TEEIO_DEBUG_INFO, "cxl_open_dev_port %s\n", port->bdf)); + // open configuration space and get ecap offset int fd = open_configuration_space(port->bdf); if (fd == -1) @@ -208,17 +338,31 @@ bool cxl_open_dev_port(ide_common_test_port_context_t *port_context) sprintf(str, "cxl.dev : %s", port->bdf); set_deivce_info(fd, str); - uint32_t ecap_offset = get_extended_cap_offset(fd, PCI_IDE_EXT_CAPABILITY_ID); - if (ecap_offset == 0) - { - TEEIO_DEBUG((TEEIO_DEBUG_ERROR, "ECAP Offset of CXL IDE is NOT found\n")); + int dvsec_cnt = MAX_IDE_TEST_DVSEC_COUNT; + if(!cxl_find_dvsec_in_config_space(fd, &port_context->priv_data.cxl.desecs[0], &dvsec_cnt)) { + TEEIO_DEBUG((TEEIO_DEBUG_ERROR, "Find CXL DVSECs failed.\n")); goto OpenDevFail; } - else - { - TEEIO_DEBUG((TEEIO_DEBUG_INFO, "ECAP Offset of CXL IDE: 0x%016x\n", ecap_offset)); + + cxl_dump_dvsecs(port_context->priv_data.cxl.desecs, dvsec_cnt); + + // check CXL DVSECs + if(!cxl_check_ep_dvsec(port_context->priv_data.cxl.desecs, dvsec_cnt)) { + TEEIO_DEBUG((TEEIO_DEBUG_ERROR, "Check CXL DVSECs failed.\n")); + goto OpenDevFail; } - port_context->ecap_offset = ecap_offset; + + // uint32_t ecap_offset = get_extended_cap_offset(fd, PCI_IDE_EXT_CAPABILITY_ID); + // if (ecap_offset == 0) + // { + // TEEIO_DEBUG((TEEIO_DEBUG_ERROR, "ECAP Offset of CXL IDE is NOT found\n")); + // goto OpenDevFail; + // } + // else + // { + // TEEIO_DEBUG((TEEIO_DEBUG_INFO, "ECAP Offset of CXL IDE: 0x%016x\n", ecap_offset)); + // } + // port_context->ecap_offset = ecap_offset; // TODO // m_dev_fp indicates the device ide card. It is used in doe_read_write.c. @@ -232,18 +376,18 @@ bool cxl_open_dev_port(ide_common_test_port_context_t *port_context) port_context->doe_offset = g_doe_extended_offset; // TODO - // check CXL_DVS_HEADER1 CXL_DVS_HEADER2 - CXL_DVS_HEADER1 header1 = {.raw = device_pci_read_32(ecap_offset + CXL_DVS_HEADER1_OFFSET, fd)}; - CXL_DVS_HEADER2 header2 = {.raw = device_pci_read_16(ecap_offset + CXL_DVS_HEADER2_OFFSET, fd)}; - TEEIO_DEBUG((TEEIO_DEBUG_INFO, "CXL Dev (%s) header1=0x%08x, header2=0x%04x\n", port->bdf, header1.raw, header2.raw)); - - // read and save cap/cap2/cap3 - CXL_PRIV_DATA* cxl_data = &port_context->priv_data.cxl; - - cxl_data->cap.raw = device_pci_read_16(ecap_offset + CXL_CAPABILITY_OFFSET, fd); - cxl_data->cap2.raw = device_pci_read_16(ecap_offset + CXL_CAPABILITY2_OFFSET, fd); - cxl_data->cap3.raw = device_pci_read_16(ecap_offset + CXL_CAPABILITY3_OFFSET, fd); - TEEIO_DEBUG((TEEIO_DEBUG_INFO, "CXL Dev (%s) cap=0x%04x, cap2=0x%04x, cap3=0x%04x\n", port->bdf, cxl_data->cap.raw, cxl_data->cap2.raw, cxl_data->cap3.raw)); + // // check CXL_DVS_HEADER1 CXL_DVS_HEADER2 + // CXL_DVS_HEADER1 header1 = {.raw = device_pci_read_32(ecap_offset + CXL_DVS_HEADER1_OFFSET, fd)}; + // CXL_DVS_HEADER2 header2 = {.raw = device_pci_read_16(ecap_offset + CXL_DVS_HEADER2_OFFSET, fd)}; + // TEEIO_DEBUG((TEEIO_DEBUG_INFO, "CXL Dev (%s) header1=0x%08x, header2=0x%04x\n", port->bdf, header1.raw, header2.raw)); + + // // read and save cap/cap2/cap3 + // CXL_PRIV_DATA* cxl_data = &port_context->priv_data.cxl; + + // cxl_data->cap.raw = device_pci_read_16(ecap_offset + CXL_CAPABILITY_OFFSET, fd); + // cxl_data->cap2.raw = device_pci_read_16(ecap_offset + CXL_CAPABILITY2_OFFSET, fd); + // cxl_data->cap3.raw = device_pci_read_16(ecap_offset + CXL_CAPABILITY3_OFFSET, fd); + // TEEIO_DEBUG((TEEIO_DEBUG_INFO, "CXL Dev (%s) cap=0x%04x, cap2=0x%04x, cap3=0x%04x\n", port->bdf, cxl_data->cap.raw, cxl_data->cap2.raw, cxl_data->cap3.raw)); return true; diff --git a/teeio-validator/library/cxl_ide_test_lib/test_group/test_group.c b/teeio-validator/library/cxl_ide_test_lib/test_group/test_group.c index 5dec4f6..49ad7a5 100644 --- a/teeio-validator/library/cxl_ide_test_lib/test_group/test_group.c +++ b/teeio-validator/library/cxl_ide_test_lib/test_group/test_group.c @@ -58,14 +58,18 @@ static bool common_test_group_setup(void *test_context) ide_common_test_group_context_t *context = (ide_common_test_group_context_t *)test_context; TEEIO_ASSERT(context->signature == GROUP_CONTEXT_SIGNATURE); + TEEIO_DEBUG((TEEIO_DEBUG_INFO, "test_group_setup start\n")); + // first scan devices if(!cxl_scan_devices(test_context)) { + TEEIO_ASSERT(false); return false; } // initialize lower_port ret = cxl_init_dev_port(context); if(!ret) { + TEEIO_ASSERT(false); return false; } @@ -74,6 +78,7 @@ static bool common_test_group_setup(void *test_context) ret = cxl_init_root_port(context); if (!ret) { + TEEIO_ASSERT(false); return false; } @@ -85,12 +90,16 @@ static bool common_test_group_setup(void *test_context) ret = spdm_connect(spdm_context, &session_id); if (!ret) { TEEIO_DEBUG((TEEIO_DEBUG_ERROR, "spdm_connect failed.\n")); + TEEIO_ASSERT(false); return false; } context->spdm_context = spdm_context; context->session_id = session_id; + TEEIO_DEBUG((TEEIO_DEBUG_INFO, "test_group_setup done\n")); + TEEIO_ASSERT(false); + return true; } diff --git a/teeio-validator/library/pcie_ide_lib/pcie_ide.c b/teeio-validator/library/pcie_ide_lib/pcie_ide.c index d11a889..fc0796b 100644 --- a/teeio-validator/library/pcie_ide_lib/pcie_ide.c +++ b/teeio-validator/library/pcie_ide_lib/pcie_ide.c @@ -22,9 +22,9 @@ #include "pcie_ide_internal.h" #include "pcie_ide_lib.h" -#define PCI_DOE_EXT_CAPABILITY_ID 0x002E -#define PCI_IDE_EXT_CAPABILITY_ID 0x0030 -#define PCI_AER_EXT_CAPABILITY_ID 0x0001 +// #define PCI_DOE_EXT_CAPABILITY_ID 0x002E +// #define PCI_IDE_EXT_CAPABILITY_ID 0x0030 +// #define PCI_AER_EXT_CAPABILITY_ID 0x0001 #define MAX_PCI_DOE_CNT 32 diff --git a/teeio-validator/library/spdmlib/spdm.c b/teeio-validator/library/spdmlib/spdm.c index 8475d2e..bcfebce 100644 --- a/teeio-validator/library/spdmlib/spdm.c +++ b/teeio-validator/library/spdmlib/spdm.c @@ -54,6 +54,8 @@ void *spdm_client_init(void) uint32_t data32; size_t scratch_buffer_size; + TEEIO_DEBUG((TEEIO_DEBUG_INFO, "spdm_client_init start.\n")); + TEEIO_DEBUG((TEEIO_DEBUG_INFO, "context_size - 0x%x\n", (uint32_t)libspdm_get_context_size())); m_spdm_context = (void *)malloc(libspdm_get_context_size()); @@ -143,14 +145,19 @@ void *spdm_client_init(void) libspdm_set_data(spdm_context, LIBSPDM_DATA_OTHER_PARAMS_SUPPORT, ¶meter, &data8, sizeof(data8)); + TEEIO_DEBUG((TEEIO_DEBUG_INFO, "libspdm_init_connection start.\n")); status = libspdm_init_connection(spdm_context, false); if (LIBSPDM_STATUS_IS_ERROR(status)) { - TEEIO_DEBUG((TEEIO_DEBUG_INFO, "libspdm_init_connection - 0x%x\n", (uint32_t)status)); + TEEIO_DEBUG((TEEIO_DEBUG_ERROR, "libspdm_init_connection failed with status = 0x%x\n", (uint32_t)status)); free(m_spdm_context); m_spdm_context = NULL; return NULL; + } else { + TEEIO_DEBUG((TEEIO_DEBUG_INFO, "libspdm_init_connection done.\n")); } + TEEIO_DEBUG((TEEIO_DEBUG_INFO, "spdm_client_init done.\n")); + return m_spdm_context; } @@ -263,6 +270,8 @@ bool spdm_connect (void *spdm_context, uint32_t *session_id) char cert_chain_name[] = "device_cert_chain_0.bin"; char measurement_name[] = "device_measurement.bin"; + TEEIO_DEBUG((TEEIO_DEBUG_INFO, "spdm_connect start.\n")); + /* get cert_chain 0 */ slot_id = 0; cert_chain.cert_chain_size = sizeof(cert_chain.cert_chain); @@ -337,6 +346,8 @@ bool spdm_connect (void *spdm_context, uint32_t *session_id) cert_chain.cert_chain_size); } + TEEIO_DEBUG((TEEIO_DEBUG_INFO, "spdm_connect done.\n")); + return true; } diff --git a/teeio-validator/teeio_validator/ide_test.c b/teeio-validator/teeio_validator/ide_test.c index 6a0b2c2..85ab23d 100644 --- a/teeio-validator/teeio_validator/ide_test.c +++ b/teeio-validator/teeio_validator/ide_test.c @@ -88,13 +88,13 @@ ide_run_test_suite_t *alloc_run_test_suite(IDE_TEST_SUITE *suite, IDE_TEST_CONFI return rts; } -bool alloc_run_test_config_item(ide_run_test_config_t *rtc, int config_type, IDE_TEST_TOPOLOGY_TYPE top_type) +bool alloc_run_test_config_item(ide_run_test_config_t *rtc, int config_type, IDE_TEST_TOPOLOGY_TYPE top_type, IDE_HW_TYPE ide_type) { TEEIO_ASSERT(top_type < IDE_TEST_TOPOLOGY_TYPE_NUM); TEEIO_ASSERT(config_type < IDE_TEST_CONFIGURATION_TYPE_NUM); // ide_test_config_funcs_t *config_func = &m_config_funcs[top_type][config_type]; - ide_test_config_funcs_t *config_func = test_factory_get_test_config_funcs(IDE_HW_TYPE_PCIE, top_type, config_type); + ide_test_config_funcs_t *config_func = test_factory_get_test_config_funcs(ide_type, top_type, config_type); ide_run_test_config_item_t *config_item = (ide_run_test_config_item_t*)malloc(sizeof(ide_run_test_config_item_t)); TEEIO_ASSERT(config_item != NULL); @@ -150,7 +150,7 @@ bool alloc_run_test_config(ide_run_test_suite_t *rts, IDE_TEST_CONFIG *test_conf int offset = 0; for(int i = 0; i < IDE_TEST_CONFIGURATION_TYPE_NUM; i++) { if(config_bits & BIT_MASK(i)) { - alloc_run_test_config_item(run_test_config, i, top->type); + alloc_run_test_config_item(run_test_config, i, top->type, top->ide_type); TEEIO_ASSERT(offset + strlen(m_ide_test_configuration_name[i]) + 1 < MAX_NAME_LENGTH); sprintf(name_buf + offset, "%s+", m_ide_test_configuration_name[i]); offset = strlen(name_buf); @@ -238,7 +238,7 @@ ide_run_test_group_t *alloc_run_test_group(ide_run_test_suite_t *rts, IDE_TEST_C sprintf(run_test_group->name, "%s", m_ide_test_topology_name[top->type]); // ide_test_group_funcs_t *group_funcs = &m_group_funcs[top->type]; - ide_test_group_funcs_t *group_funcs = test_factory_get_test_group_funcs(IDE_HW_TYPE_PCIE, top->type); + ide_test_group_funcs_t *group_funcs = test_factory_get_test_group_funcs(top->ide_type, top->type); run_test_group->setup_func = group_funcs->setup; run_test_group->teardown_func = group_funcs->teardown; @@ -284,7 +284,7 @@ ide_run_test_group_t *alloc_run_test_group(ide_run_test_suite_t *rts, IDE_TEST_C /** * allocate run_test_case. After that it is insert into @run_test_group */ -bool alloc_run_test_case(ide_run_test_group_t *run_test_group, IDE_COMMON_TEST_CASE test_case, uint32_t case_id) +bool alloc_run_test_case(ide_run_test_group_t *run_test_group, IDE_COMMON_TEST_CASE test_case, uint32_t case_id, IDE_HW_TYPE ide_type) { TEEIO_ASSERT(test_case < IDE_COMMON_TEST_CASE_NUM); TEEIO_ASSERT(case_id <= MAX_CASE_ID); @@ -298,7 +298,7 @@ bool alloc_run_test_case(ide_run_test_group_t *run_test_group, IDE_COMMON_TEST_C // run_test_case->action = IDE_COMMON_TEST_ACTION_RUN; // ide_test_case_funcs_t* case_funcs = &m_test_case_funcs[test_case][case_id - 1]; - ide_test_case_funcs_t* case_funcs = test_factory_get_test_case_funcs(IDE_HW_TYPE_PCIE, test_case, case_id - 1); + ide_test_case_funcs_t* case_funcs = test_factory_get_test_case_funcs(ide_type, test_case, case_id - 1); run_test_case->run_func = case_funcs->run; run_test_case->setup_func = case_funcs->setup; run_test_case->teardown_func = case_funcs->teardown; @@ -348,7 +348,7 @@ bool alloc_run_test_cases( for (int j = 0; j < tc->cases_cnt; j++) { - alloc_run_test_case(run_test_group, i, tc->cases_id[j]); + alloc_run_test_case(run_test_group, i, tc->cases_id[j], top->ide_type); } } @@ -480,14 +480,14 @@ ide_run_test_case_result_t *alloc_run_test_case_result(ide_run_test_group_result return case_result; } -static bool do_run_test_config_support(ide_run_test_config_t *run_test_config) +static bool do_run_test_config_support(ide_run_test_config_t *run_test_config, IDE_HW_TYPE ide_type) { bool ret = false; // if(!test_config_support_common(run_test_config->test_context)) { // return false; // } - ide_common_test_config_support_func_t support_func = test_factory_get_common_test_config_support_func(IDE_HW_TYPE_PCIE); + ide_common_test_config_support_func_t support_func = test_factory_get_common_test_config_support_func(ide_type); if(!support_func(run_test_config->test_context)) { return false; } @@ -503,14 +503,14 @@ static bool do_run_test_config_support(ide_run_test_config_t *run_test_config) return ret; } -static bool do_run_test_config_enable(ide_run_test_config_t *run_test_config) +static bool do_run_test_config_enable(ide_run_test_config_t *run_test_config, IDE_HW_TYPE ide_type) { bool ret = false; // if(!test_config_enable_common(run_test_config->test_context)) { // return false; // } - ide_common_test_config_enable_func_t enable_func = test_factory_get_common_test_config_enable_func(IDE_HW_TYPE_PCIE); + ide_common_test_config_enable_func_t enable_func = test_factory_get_common_test_config_enable_func(ide_type); if(!enable_func(run_test_config->test_context)) { return false; } @@ -526,14 +526,14 @@ static bool do_run_test_config_enable(ide_run_test_config_t *run_test_config) return ret; } -static bool do_run_test_config_check(ide_run_test_config_t *run_test_config) +static bool do_run_test_config_check(ide_run_test_config_t *run_test_config, IDE_HW_TYPE ide_type) { bool ret = false; // if(!test_config_check_common(run_test_config->test_context)) { // return false; // } - ide_common_test_config_check_func_t check_func = test_factory_get_common_test_config_check_func(IDE_HW_TYPE_PCIE); + ide_common_test_config_check_func_t check_func = test_factory_get_common_test_config_check_func(ide_type); if(!check_func(run_test_config->test_context)) { return false; } @@ -564,6 +564,8 @@ bool do_run_test_group(ide_run_test_group_t *run_test_group, ide_run_test_config TEEIO_ASSERT(config_context->signature == CONFIG_CONTEXT_SIGNATURE); config_context->group_context = group_context; + IDE_HW_TYPE ide_type = group_context->top->ide_type; + if(run_test_group->test_case == NULL) { TEEIO_DEBUG((TEEIO_DEBUG_ERROR, "test_case is not set in test_group.\n")); return true; @@ -591,7 +593,7 @@ bool do_run_test_group(ide_run_test_group_t *run_test_group, ide_run_test_config } else { // check if the test_config is supported. // if not supported, this test_group is done. - if(!do_run_test_config_support(run_test_config)) { + if(!do_run_test_config_support(run_test_config, ide_type)) { config_context->test_result = IDE_COMMON_TEST_CONFIG_RESULT_NA; TEEIO_PRINT((" %s is not supported. Skip the TestConfig.\n", run_test_config->name)); run_test_config_failed = true; @@ -610,7 +612,7 @@ bool do_run_test_group(ide_run_test_group_t *run_test_group, ide_run_test_config } // call test_config's enable function - ret = do_run_test_config_enable(run_test_config); + ret = do_run_test_config_enable(run_test_config, ide_type); TEEIO_ASSERT(ret); // run the test_case @@ -618,7 +620,7 @@ bool do_run_test_group(ide_run_test_group_t *run_test_group, ide_run_test_config if(test_case->complete_ide_stream) { // check config - ret = do_run_test_config_check(run_test_config); + ret = do_run_test_config_check(run_test_config, ide_type); case_result->config_result = config_context->test_result; TEEIO_ASSERT(ret); }