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Layout and the contributor of each subblock/subsystem
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Block Diagrams
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Interface and Area
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| File | Purpose/Function | Remark |
|---|---|---|
| SW_CDAC.sch | switch component for each CDAC bit which is based on the https://github.com/ishi-kai/Chipathon2023_ADC/blob/main/transmission-gate/sw.sch | The only difference from the base sw.sch is the NMOS connected to the Vout port |
| SW_CDAC.sym | symbol file made from the Sw_CDAC.sch | |
| user_proj_sarlogic.sym | symbol file used for the simulation of user_proj_sarlogic_pex_extracted.spice | |
| user_proj_sarlogic.sch | blackbox module for making the symbol file of user_proj_sarlogic | |
| tran_sar_logic.sch | schematic file for the unit-level verification of SAR logic | |
| tran_sar_adc.sch | Testbench for the integration of the overall SAR A/D converter as shown in the figure below |
- Top-level schematic of the A/D converter integrating all subblocks
- Design of the MIM capacitor array
- Design of the latch components
- Design of the comparator
- Unused/Tentative design material
