From c6df54c14fd0166f6147605796a493cfe4a8cbfc Mon Sep 17 00:00:00 2001
From: Toshinari Itoko <itoko@jp.ibm.com>
Date: Tue, 31 Jan 2023 11:14:21 +0900
Subject: [PATCH] Update tests for InterleavedRB

---
 .../test_interleaved_rb.py                    | 47 +++++++++++++++++--
 1 file changed, 44 insertions(+), 3 deletions(-)

diff --git a/test/library/randomized_benchmarking/test_interleaved_rb.py b/test/library/randomized_benchmarking/test_interleaved_rb.py
index f635117fbb..c573d0538b 100644
--- a/test/library/randomized_benchmarking/test_interleaved_rb.py
+++ b/test/library/randomized_benchmarking/test_interleaved_rb.py
@@ -266,15 +266,15 @@ def test_interleaved_circuit_is_decomposed(self):
             self.assertTrue(all(not inst.operation.name.startswith("Clifford") for inst in qc))
 
     def test_interleaving_cnot_gate_with_non_supported_direction(self):
-        """Test if cx(0, 1) can be interleaved for backend that support only cx(1, 0)."""
+        """Test if, for backend that support only cx(1, 0), cx(1, 0) can be interleaved
+        but cx(0, 1) cannot."""
         my_backend = FakeManilaV2()
         del my_backend.target["cx"][(0, 1)]  # make support only cx(1, 0)
 
         exp = rb.InterleavedRB(
             interleaved_element=CXGate(),
-            physical_qubits=(0, 1),
+            physical_qubits=(1, 0),  # supported
             lengths=[3],
-            num_samples=4,
             backend=my_backend,
             seed=1234,
         )
@@ -286,6 +286,47 @@ def test_interleaving_cnot_gate_with_non_supported_direction(self):
                 if inst.operation.name == "cx":
                     self.assertEqual(inst.qubits, expected_qubits)
 
+        exp = rb.InterleavedRB(
+            interleaved_element=CXGate(),
+            physical_qubits=(0, 1),  # not supported
+            lengths=[3],
+            backend=my_backend,
+        )
+        with self.assertRaises(QiskitError):
+            exp._transpiled_circuits()
+
+    def test_interleaving_circuit_with_gates_with_non_supported_direction(self):
+        """Test if, for backend that support only cx(2, 1),
+        circuit only with cx(2, 1) can be interleaved but circuit with cx(1, 2) cannot."""
+        my_backend = FakeManilaV2()
+        del my_backend.target["cx"][(1, 2)]  # make support only cx(2, 1)
+
+        circ = QuantumCircuit(2)
+        circ.sx(0)
+        circ.cx(0, 1)
+        exp = rb.InterleavedRB(
+            interleaved_element=circ,
+            physical_qubits=(2, 1),  # supported
+            lengths=[3],
+            backend=my_backend,
+        )
+        transpiled = exp._transpiled_circuits()
+        for qc in transpiled:
+            self.assertTrue(qc.count_ops().get("cx", 0) > 0)
+            expected_qubits = (qc.qubits[2], qc.qubits[1])
+            for inst in qc:
+                if inst.operation.name == "cx":
+                    self.assertEqual(inst.qubits, expected_qubits)
+
+        exp = rb.InterleavedRB(
+            interleaved_element=circ,
+            physical_qubits=(1, 2),  # not supported
+            lengths=[3],
+            backend=my_backend,
+        )
+        with self.assertRaises(QiskitError):
+            exp._transpiled_circuits()
+
     def test_interleaved_element_contains_non_basis_gates(self):
         """Raise if interleaved_element contains any non basis gate"""
         with self.assertRaises(QiskitError):