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lpc802.svd
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lpc802.svd
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<?xml version="1.0" encoding="UTF-8"?>
<device schemaVersion="1.3" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance"
xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd">
<vendor>nxp.com</vendor>
<name>lpc802</name>
<version>1.0</version>
<description>LPC802M001JDH16,LPC802M001JDH20,LPC802M001JHI33,LPC802M011JDH20,LPC802UK</description>
<licenseText>
Copyright 2016-2019 NXP
All rights reserved.
SPDX-License-Identifier: BSD-3-Clause
</licenseText>
<cpu>
<name>CM0PLUS</name>
<revision>r0p0</revision>
<endian>little</endian>
<mpuPresent>false</mpuPresent>
<fpuPresent>false</fpuPresent>
<vtorPresent>true</vtorPresent>
<nvicPrioBits>2</nvicPrioBits>
<vendorSystickConfig>false</vendorSystickConfig>
</cpu>
<addressUnitBits>8</addressUnitBits>
<width>32</width>
<peripherals>
<peripheral>
<name>WWDT</name>
<description>Windowed Watchdog Timer (WWDT)</description>
<groupName>WWDT</groupName>
<baseAddress>0x40000000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x1C</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>MOD</name>
<description>Watchdog mode register. This register contains the basic mode and
status of the Watchdog Timer.</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x3F</resetMask>
<fields>
<field>
<name>WDEN</name>
<description>Watchdog enable bit. Once this bit is set to one and a
watchdog feed is performed, the watchdog timer will run permanently.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>STOP</name>
<description>Stop. The watchdog timer is stopped.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>RUN</name>
<description>Run. The watchdog timer is running.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WDRESET</name>
<description>Watchdog reset enable bit. Once this bit has been written
with a 1 it cannot be re-written with a 0.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>INTERRUPT</name>
<description>Interrupt. A watchdog time-out will not cause a
chip reset.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>RESET</name>
<description>Reset. A watchdog time-out will cause a chip reset.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WDTOF</name>
<description>Watchdog time-out flag. Set when the watchdog timer times
out, by a feed error, or by events associated with WDPROTECT.
Cleared by software writing a 0 to this bit position. Causes a chip
reset if WDRESET = 1.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>WDINT</name>
<description>Warning interrupt flag. Set when the timer is at or below
the value in WDWARNINT. Cleared by software writing a 1 to this bit
position. Note that this bit cannot be cleared while the WARNINT
value is equal to the value of the TV register. This can occur if
the value of WARNINT is 0 and the WDRESET bit is 0 when TV
decrements to 0.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>WDPROTECT</name>
<description>Watchdog update mode. This bit can be set once by software
and is only cleared by a reset.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>FLEXIBLE</name>
<description>Flexible. The watchdog time-out value (TC) can be
changed at any time.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>THRESHOLD</name>
<description>Threshold. The watchdog time-out value (TC) can be
changed only after the counter is below the value of
WDWARNINT and WDWINDOW.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LOCK</name>
<description>Once this bit is set to one and a watchdog feed is
performed, disabling or powering down the watchdog oscillator is
prevented by hardware. This bit can be set once by software and is
only cleared by any reset.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>TC</name>
<description>Watchdog timer constant register. This 24-bit register determines
the time-out value.</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xFF</resetValue>
<resetMask>0xFFFFFF</resetMask>
<fields>
<field>
<name>COUNT</name>
<description>Watchdog time-out value.</description>
<bitOffset>0</bitOffset>
<bitWidth>24</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>FEED</name>
<description>Watchdog feed sequence register. Writing 0xAA followed by 0x55 to
this register reloads the Watchdog timer with the value contained in TC.</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>FEED</name>
<description>Feed value should be 0xAA followed by 0x55.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>write-only</access>
</field>
</fields>
</register>
<register>
<name>TV</name>
<description>Watchdog timer value register. This 24-bit register reads out the
current value of the Watchdog timer.</description>
<addressOffset>0xC</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0xFF</resetValue>
<resetMask>0xFFFFFF</resetMask>
<fields>
<field>
<name>COUNT</name>
<description>Counter timer value.</description>
<bitOffset>0</bitOffset>
<bitWidth>24</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>WARNINT</name>
<description>Watchdog Warning Interrupt compare value.</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x3FF</resetMask>
<fields>
<field>
<name>WARNINT</name>
<description>Watchdog warning interrupt compare value.</description>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>WINDOW</name>
<description>Watchdog Window compare value.</description>
<addressOffset>0x18</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xFFFFFF</resetValue>
<resetMask>0xFFFFFF</resetMask>
<fields>
<field>
<name>WINDOW</name>
<description>Watchdog window value.</description>
<bitOffset>0</bitOffset>
<bitWidth>24</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>MRT0</name>
<description>Multi-Rate Timer (MRT)</description>
<groupName>MRT</groupName>
<baseAddress>0x40004000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0xFC</size>
<usage>registers</usage>
</addressBlock>
<registers>
<cluster>
<dim>2</dim>
<dimIncrement>0x10</dimIncrement>
<name>CHANNEL[%s]</name>
<description>no description available</description>
<addressOffset>0x0</addressOffset>
<register>
<name>INTVAL</name>
<description>MRT Time interval value register. This value is loaded into the
TIMER register.</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x80FFFFFF</resetMask>
<fields>
<field>
<name>IVALUE</name>
<description>Time interval load value. This value is loaded into the
TIMERn register and the MRT channel n starts counting down from
IVALUE -1. If the timer is idle, writing a non-zero value to
this bit field starts the timer immediately. If the timer is
running, writing a zero to this bit field does the following: If
LOAD = 1, the timer stops immediately. If LOAD = 0, the timer
stops at the end of the time interval.</description>
<bitOffset>0</bitOffset>
<bitWidth>31</bitWidth>
<access>read-write</access>
</field>
<field>
<name>LOAD</name>
<description>Determines how the timer interval value IVALUE -1 is
loaded into the TIMERn register. This bit is write-only. Reading
this bit always returns 0.</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>NO_FORCE_LOAD</name>
<description>No force load. The load from the INTVALn
register to the TIMERn register is processed at the end
of the time interval if the repeat mode is selected.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>FORCE_LOAD</name>
<description>Force load. The INTVALn interval value IVALUE
-1 is immediately loaded into the TIMERn register while
TIMERn is running.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>TIMER</name>
<description>MRT Timer register. This register reads the value of the
down-counter.</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0xFFFFFF</resetValue>
<resetMask>0xFFFFFF</resetMask>
<fields>
<field>
<name>VALUE</name>
<description>Holds the current timer value of the down-counter. The
initial value of the TIMERn register is loaded as IVALUE - 1
from the INTVALn register either at the end of the time interval
or immediately in the following cases: INTVALn register is
updated in the idle state. INTVALn register is updated with LOAD
= 1. When the timer is in idle state, reading this bit fields
returns -1 (0x00FF FFFF).</description>
<bitOffset>0</bitOffset>
<bitWidth>31</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>CTRL</name>
<description>MRT Control register. This register controls the MRT modes.</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x7</resetMask>
<fields>
<field>
<name>INTEN</name>
<description>Enable the TIMERn interrupt.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DISABLED</name>
<description>Disabled. TIMERn interrupt is disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. TIMERn interrupt is enabled.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>MODE</name>
<description>Selects timer mode.</description>
<bitOffset>1</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>REPEAT_INTERRUPT_MODE</name>
<description>Repeat interrupt mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ONE_SHOT_INTERRUPT_MODE</name>
<description>One-shot interrupt mode.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>ONE_SHOT_STALL_MODE</name>
<description>One-shot stall mode.</description>
<value>0x2</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>STAT</name>
<description>MRT Status register.</description>
<addressOffset>0xC</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0x3</resetMask>
<fields>
<field>
<name>INTFLAG</name>
<description>Monitors the interrupt flag.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>NO_PENDING_INTERRUPT</name>
<description>No pending interrupt. Writing a zero is
equivalent to no operation.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>PENDING_INTERRUPT</name>
<description>Pending interrupt. The interrupt is pending
because TIMERn has reached the end of the time interval.
If the INTEN bit in the CONTROLn is also set to 1, the
interrupt for timer channel n and the global interrupt
are raised. Writing a 1 to this bit clears the interrupt
request.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RUN</name>
<description>Indicates the state of TIMERn. This bit is read-only.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>IDLE_STATE</name>
<description>Idle state. TIMERn is stopped.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>RUNNING</name>
<description>Running. TIMERn is running.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</cluster>
<register>
<name>MODCFG</name>
<description>Module Configuration register. This register provides information
about this particular MRT instance.</description>
<addressOffset>0xF0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x1F4</resetValue>
<resetMask>0x1FF</resetMask>
<fields>
<field>
<name>NOC</name>
<description>Identifies the number of channels in this MRT.(4 channels
on this device.)</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
</field>
<field>
<name>NOB</name>
<description>Identifies the number of timer bits in this MRT. (31 bits
wide on this device.)</description>
<bitOffset>4</bitOffset>
<bitWidth>5</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>IDLE_CH</name>
<description>Idle channel register. This register returns the number of the
first idle channel.</description>
<addressOffset>0xF4</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0</resetValue>
<resetMask>0xF0</resetMask>
<fields>
<field>
<name>CHAN</name>
<description>Idle channel. Reading the CHAN bits, returns the lowest
idle timer channel. The number is positioned such that it can be
used as an offset from the MRT base address in order to access the
registers for the allocated channel. If all timer channels are
running, CHAN = 0xF. See text above for more details.</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>IRQ_FLAG</name>
<description>Global interrupt flag register</description>
<addressOffset>0xF8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xF</resetMask>
<fields>
<field>
<name>GFLAG0</name>
<description>Monitors the interrupt flag of TIMER0.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>NO_PENDING_INTERRUPT</name>
<description>No pending interrupt. Writing a zero is equivalent
to no operation.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>PENDING_INTERRUPT</name>
<description>Pending interrupt. The interrupt is pending because
TIMER0 has reached the end of the time interval. If the
INTEN bit in the CONTROL0 register is also set to 1, the
interrupt for timer channel 0 and the global interrupt are
raised. Writing a 1 to this bit clears the interrupt
request.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>GFLAG1</name>
<description>Monitors the interrupt flag of TIMER1. See description of
channel 0.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>WKT</name>
<description>Wake Up Timer(WKT)</description>
<groupName>WKT</groupName>
<baseAddress>0x40008000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x10</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>WKT</name>
<value>15</value>
</interrupt>
<registers>
<register>
<name>CTRL</name>
<description>Self wake-up timer control register.</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0xF</resetMask>
<fields>
<field>
<name>CLKSEL</name>
<description>Select the self wake-up timer clock source. Remark: This
bit only has an effect if the SEL_EXTCLK bit is not set.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>DIVIDED_IRC_CLOCK</name>
<description>Divided IRC clock. This clock runs at 750 kHz and
provides time-out periods of up to approximately 95 minutes
in 1.33 us increments. Remark: This clock is not available
in not available in Deep-sleep, power-down, deep power-down
modes. Do not select this option if the timer is to be used
to wake up from one of these modes.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>LOW_POWER_CLOCK</name>
<description>This is the (nominally) 10 kHz clock and provides
time-out periods of up to approximately 119 hours in 100 us
increments. The accuracy of this clock is limited to +/- 40
% over temperature and processing. Remark: This clock is
available in all power modes. Prior to use, the low-power
oscillator must be enabled. The oscillator must also be set
to remain active in Deep power-down if needed.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ALARMFLAG</name>
<description>Wake-up or alarm timer flag.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>NO_TIME_OUT</name>
<description>No time-out. The self wake-up timer has not timed
out. Writing a 0 to has no effect.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>TIME_OUT</name>
<description>Time-out. The self wake-up timer has timed out.
This flag generates an interrupt request which can wake up
the part from any reduced power mode including Deep
power-down if the clock source is the low power oscillator.
Writing a 1 clears this status bit.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CLEARCTR</name>
<description>Clears the self wake-up timer.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>NO_EFFECT</name>
<description>No effect. Reading this bit always returns 0.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CLEAR_THE_COUNTER</name>
<description>Clear the counter. Counting is halted until a new
count value is loaded.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SEL_EXTCLK</name>
<description>Select external or internal clock source for the self
wake-up timer. The internal clock source is selected by the CLKSEL
bit in this register if SET_EXTCLK is set to internal.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>INTERNAL</name>
<description>Internal. The clock source is the internal clock
selected by the CLKSEL bit.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>EXTERNAL</name>
<description>External. The self wake-up timer uses the external
WKTCLKIN pin.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>COUNT</name>
<description>Counter register.</description>
<addressOffset>0xC</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
<name>VALUE</name>
<description>A write to this register pre-loads start count value into
the timer and starts the count-down sequence. A read reflects the
current value of the timer.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>SWM0</name>
<description>SWM</description>
<groupName>SWM</groupName>
<baseAddress>0x4000C000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x1C4</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>PINASSIGN0</name>
<description>Pin assign register 0. Assign movable functions U0_TXD, U0_RXD,
U0_RTS, U0_CTS.</description>
<alternateGroup>PINASSIGN_PINASSIGN_DATA</alternateGroup>
<addressOffset>0x0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xFFFFFFFF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>U0_TXD_O</name>
<description>U0_TXD function assignment. The value is the pin number to
be assigned to this function. The following pins are available:
PIO0_0 (= 0) to PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (=
0x7) to PIO0_17 (= 0x11).</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>U0_RXD_I</name>
<description>U0_RXD function assignment. The value is the pin number to
be assigned to this function. The following pins are available:
PIO0_0 (= 0) to PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (=
0x7) to PIO0_17 (= 0x11).</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>U0_RTS_O</name>
<description>U0_RTS function assignment. The value is the pin number to
be assigned to this function. The following pins are available:
PIO0_0 (= 0) to PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (=
0x7) to PIO0_17 (= 0x11).</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>U0_CTS_I</name>
<description>U0_CTS function assignment. The value is the pin number to
be assigned to this function. The following pins are available:
PIO0_0 (= 0) to PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (=
0x7) to PIO0_17 (= 0x11).</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PINASSIGN_DATA0</name>
<description>Pin assign register</description>
<alternateGroup>PINASSIGN_PINASSIGN_DATA</alternateGroup>
<addressOffset>0x0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xFFFFFFFF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DATA0</name>
<description>T0_MAT3 function assignment. The value is the pin number to
be assigned to this function. The following pins are available:
PIO0_0 (= 0) to PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (=
0x7) to PIO0_17 (= 0x11).</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DATA1</name>
<description>T0_CAP0 function assignment. The value is the pin number to
be assigned to this function. The following pins are available:
PIO0_0 (= 0) to PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (=
0x7) to PIO0_17 (= 0x11).</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DATA2</name>
<description>T0_CAP1 function assignment. The value is the pin number to
be assigned to this function. The following pins are available:
PIO0_0 (= 0) to PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (=
0x7) to PIO0_17 (= 0x11).</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DATA3</name>
<description>T0_CAP2 function assignment. The value is the pin number to
be assigned to this function. The following pins are available:
PIO0_0 (= 0) to PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (=
0x7) to PIO0_17 (= 0x11).</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PINASSIGN1</name>
<description>Pin assign register 1. Assign movable functions U0_SCLK, U1_TXD,
U1_RXD, U1_SCLK.</description>
<alternateGroup>PINASSIGN_PINASSIGN_DATA</alternateGroup>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xFFFFFFFF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>U0_SCLK_IO</name>
<description>U0_SCLK function assignment. The value is the pin number to
be assigned to this function. The following pins are available:
PIO0_0 (= 0) to PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (=
0x7) to PIO0_17 (= 0x11).</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>U1_TXD_O</name>
<description>U1_TXD function assignment. The value is the pin number to
be assigned to this function. The following pins are available:
PIO0_0 (= 0) to PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (=
0x7) to PIO0_17 (= 0x11).</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>U1_RXD_I</name>
<description>U1_RXD function assignment. The value is the pin number to
be assigned to this function. The following pins are available:
PIO0_0 (= 0) to PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (=
0x7) to PIO0_17 (= 0x11).</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>U1_SCLK_IO</name>
<description>U1_SCLK function assignment. The value is the pin number to
be assigned to this function. The following pins are available:
PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_17 (=
0x11).</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PINASSIGN_DATA1</name>
<description>Pin assign register</description>
<alternateGroup>PINASSIGN_PINASSIGN_DATA</alternateGroup>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xFFFFFFFF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DATA0</name>
<description>T0_MAT3 function assignment. The value is the pin number to
be assigned to this function. The following pins are available:
PIO0_0 (= 0) to PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (=
0x7) to PIO0_17 (= 0x11).</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DATA1</name>
<description>T0_CAP0 function assignment. The value is the pin number to
be assigned to this function. The following pins are available:
PIO0_0 (= 0) to PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (=
0x7) to PIO0_17 (= 0x11).</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DATA2</name>
<description>T0_CAP1 function assignment. The value is the pin number to
be assigned to this function. The following pins are available:
PIO0_0 (= 0) to PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (=
0x7) to PIO0_17 (= 0x11).</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DATA3</name>
<description>T0_CAP2 function assignment. The value is the pin number to
be assigned to this function. The following pins are available:
PIO0_0 (= 0) to PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (=
0x7) to PIO0_17 (= 0x11).</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PINASSIGN2</name>
<description>Pin assign register 2. Assign movable functions SPI0_SCK,
SPI0_MOSI, SPI0_MISO, SPI0_SSEL0.</description>
<alternateGroup>PINASSIGN_PINASSIGN_DATA</alternateGroup>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xFFFFFFFF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SPI0_SCK_IO</name>
<description>SPI0_SCK function assignment. The value is the pin number
to be assigned to this function. The following pins are available:
PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_17 (=
0x11).</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SPI0_MOSI_IO</name>
<description>SPI0_MOSI function assignment. The value is the pin number
to be assigned to this function. The following pins are available:
PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_17 (=
0x11).</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SPI0_MISO_IO</name>
<description>SPI0_MISO function assignment. The value is the pin number
to be assigned to this function. The following pins are available:
PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_17 (=
0x11).</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SPI0_SSEL0_IO</name>
<description>SPI0_SSEL0 function assignment. The value is the pin number
to be assigned to this function. The following pins are available:
PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) to PIO0_17 (=
0x11).</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PINASSIGN_DATA2</name>
<description>Pin assign register</description>
<alternateGroup>PINASSIGN_PINASSIGN_DATA</alternateGroup>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xFFFFFFFF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DATA0</name>
<description>T0_MAT3 function assignment. The value is the pin number to
be assigned to this function. The following pins are available:
PIO0_0 (= 0) to PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (=
0x7) to PIO0_17 (= 0x11).</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DATA1</name>
<description>T0_CAP0 function assignment. The value is the pin number to
be assigned to this function. The following pins are available:
PIO0_0 (= 0) to PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (=
0x7) to PIO0_17 (= 0x11).</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DATA2</name>
<description>T0_CAP1 function assignment. The value is the pin number to
be assigned to this function. The following pins are available:
PIO0_0 (= 0) to PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (=
0x7) to PIO0_17 (= 0x11).</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>