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CPU.py
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from Memory import Memory
INSTRUCTION_INDEX = 0
LENGTH_INDEX = 1
CYCLES_INDEX = 2
DEBUG_INDEX = 3
class CPU:
def __init__(self, memory):
# Instruction Set
# [function, length in bytes of opcode + arguments, clock cycles, assembly string]
# Opcodes: http://pastraiser.com/cpu/gameboy/gameboy_opcodes.html
# Gameboy CPU Manual: http://marc.rawer.de/Gameboy/Docs/GBCPUman.pdf
self.instructions = {
0x00: [self.NOP, 1, 4, "NOP"],
0x01: [self.LD_BC_d16, 3, 12, "LD BC,d16"],
0x02: [self.LD_M_BC_A, 1, 8, "LD (BC),A"],
0x03: [self.INC_BC, 1, 8, "INC BC"],
0x04: [self.INC_B, 1, 4, "INC B"],
0x05: [self.DEC_B, 1, 4, "DEC B"],
0x06: [self.LD_B, 2, 8, "LD B,d8"],
0x07: [self.RLCA, 1, 4, "RLCA"],
0x08: [self.LD_M_d16_SP, 3, 20, "LD (a16),SP"],
0x09: [self.ADD_HL_BC, 1, 8, "ADD HL,BC"],
0x0A: [self.LD_A_M_BC, 1, 8, "LD A,(BC)"],
0x0B: [self.DEC_BC, 1, 8, "DEC BC"],
0x0C: [self.INC_C, 1, 4, "INC C"],
0x0D: [self.DEC_C, 1, 4, "DEC C"],
0x0E: [self.LD_C, 2, 8, "LD C,d8"],
0x0F: [self.RRCA, 1, 4, "RRCA"],
0x10: [self.STOP, 2, 4, "STOP 0"],
0x11: [self.LD_DE_d16, 3, 12, "LD DE,d16"],
0x12: [self.LD_M_DE_A, 1, 8, "LD (DE),A"],
0x13: [self.INC_DE, 1, 8, "INC DE"],
0x14: [self.INC_D, 1, 4, "INC D"],
0x15: [self.DEC_D, 1, 4, "DEC D"],
0x16: [self.LD_D, 2, 8, "LD D,d8"],
0x17: [self.RLA, 1, 4, "RLA"],
0x18: [self.JR_r8, 2, 12, "JR r8"],
0x19: [self.ADD_HL_DE, 1, 8, "ADD HL,DE"],
0x1A: [self.LD_A_M_DE, 1, 8, "LD A,(DE)"],
0x1B: [self.DEC_DE, 1, 8, "DEC DE"],
0x1C: [self.INC_E, 1, 4, "INC E"],
0x1D: [self.DEC_E, 1, 4, "DEC E"],
0x1E: [self.LD_E, 2, 8, "LD E"],
0x1F: [self.RRA, 1, 4, "RRA"],
0x20: [self.JR_NZ_r8, 2, 8, "JR NZ,r8"],
0x21: [self.LD_HL_d16, 3, 12, "LD HL,d16"],
0x22: [self.LD_M_HLP_A, 1, 8, "LD (HL+),A"],
0x23: [self.INC_HL, 1, 8, "INC HL"],
0x24: [self.INC_H, 1, 4, "INC H"],
0x25: [self.DEC_H, 1, 4, "DEC H"],
0x26: [self.LD_H, 2, 8, "LD H,d8"],
0x27: [self.DAA, 1, 4, "DAA"],
0x28: [self.JR_Z_r8, 2, 8, "JR Z,r8"],
0x29: [self.ADD_HL_HL, 1, 8, "ADD HL,HL"],
0x2A: [self.LD_A_M_HLP, 1, 8, "LD A,(HL+)"],
0x2B: [self.DEC_HL, 1, 8, "DEC HL"],
0x2C: [self.INC_L, 1, 4, "INC L"],
0x2D: [self.DEC_L, 1, 4, "DEC L"],
0x2E: [self.LD_L, 2, 8, "LD L,d8"],
0x2F: [self.CPL, 1, 4, "CPL"],
0x30: [self.JR_NC_r8, 2, 8, "JR NC,r8"],
0x31: [self.LD_SP_d16, 3, 12, "LD SP,d16"],
0x32: [self.LD_M_HLM_A, 1, 8, "LD (HL-),A"],
0x33: [self.INC_SP, 1, 8, "INC SP"],
0x34: [self.INC_M_HL, 1, 12, "INC (HL)"],
0x35: [self.DEC_M_HL, 1, 12, "DEC (HL)"],
0x36: [self.LD_M_HL_d8, 2, 12, "LD (HL),d8"],
0x37: [self.SCF, 1, 4, "SCF"],
0x38: [self.JR_C_r8, 2, 8, "JR C,r8"],
0x39: [self.ADD_HL_SP, 1, 8, "ADD HL,SP"],
0x3A: [self.LD_A_M_HLM, 1, 8, "LD A,(HL-)"],
0x3B: [self.DEC_SP, 1, 8, "DEC SP"],
0x3C: [self.INC_A, 1, 4, "INC A"],
0x3D: [self.DEC_A, 1, 4, "DEC A"],
0x3E: [self.LD_A, 2, 8, "LD A,d8"],
0x3F: [self.CCF, 1, 4, "CCF"],
0x40: [self.LD_B_B, 1, 4, "LD B,B"],
0x41: [self.LD_B_C, 1, 4, "LD B,C"],
0x42: [self.LD_B_D, 1, 4, "LD B,D"],
0x43: [self.LD_B_E, 1, 4, "LD B,E"],
0x44: [self.LD_B_H, 1, 4, "LD B,H"],
0x45: [self.LD_B_L, 1, 4, "LD B,L"],
0x46: [self.LD_B_M_HL, 1, 8, "LD B,(HL)"],
0x47: [self.LD_B_A, 1, 4, "LD B,A"],
0x48: [self.LD_C_B, 1, 4, "LD C,B"],
0x49: [self.LD_C_C, 1, 4, "LD C,C"],
0x4A: [self.LD_C_D, 1, 4, "LD C,D"],
0x4B: [self.LD_C_E, 1, 4, "LD C,E"],
0x4C: [self.LD_C_H, 1, 4, "LD C,H"],
0x4D: [self.LD_C_L, 1, 4, "LD C,L"],
0x4E: [self.LD_C_M_HL, 1, 8, "LD C,(HL)"],
0x4F: [self.LD_C_A, 1, 4, "LD C,A"],
0x50: [self.LD_D_B, 1, 4, "LD D,B"],
0x51: [self.LD_D_C, 1, 4, "LD D,C"],
0x52: [self.LD_D_D, 1, 4, "LD D,D"],
0x53: [self.LD_D_E, 1, 4, "LD D,E"],
0x54: [self.LD_D_H, 1, 4, "LD D,H"],
0x55: [self.LD_D_L, 1, 4, "LD D,L"],
0x56: [self.LD_D_M_HL, 1, 8, "LD D,(HL)"],
0x57: [self.LD_D_A, 1, 4, "LD D,A"],
0x58: [self.LD_E_B, 1, 4, "LD E,B"],
0x59: [self.LD_E_C, 1, 4, "LD E,C"],
0x5A: [self.LD_E_D, 1, 4, "LD E,D"],
0x5B: [self.LD_E_E, 1, 4, "LD E,E"],
0x5C: [self.LD_E_H, 1, 4, "LD E,H"],
0x5D: [self.LD_E_L, 1, 4, "LD E,L"],
0x5E: [self.LD_E_M_HL, 1, 8, "LD E,(HL)"],
0x5F: [self.LD_E_A, 1, 4, "LD C,A"],
0x60: [self.LD_H_B, 1, 4, "LD H,B"],
0x61: [self.LD_H_C, 1, 4, "LD H,C"],
0x62: [self.LD_H_D, 1, 4, "LD H,D"],
0x63: [self.LD_H_E, 1, 4, "LD H,E"],
0x64: [self.LD_H_H, 1, 4, "LD H,H"],
0x65: [self.LD_H_L, 1, 4, "LD H,L"],
0x66: [self.LD_H_M_HL, 1, 8, "LD H,(HL)"],
0x67: [self.LD_H_A, 1, 4, "LD H,A"],
0x68: [self.LD_L_B, 1, 4, "LD L,B"],
0x69: [self.LD_L_C, 1, 4, "LD L,C"],
0x6A: [self.LD_L_D, 1, 4, "LD L,D"],
0x6B: [self.LD_L_E, 1, 4, "LD L,E"],
0x6C: [self.LD_L_H, 1, 4, "LD L,H"],
0x6D: [self.LD_L_L, 1, 4, "LD L,L"],
0x6E: [self.LD_L_M_HL, 1, 8, "LD L,(HL)"],
0x6F: [self.LD_L_A, 1, 4, "LD C,A"],
0x70: [self.LD_M_HL_B, 1, 8, "LD (HL),B"],
0x71: [self.LD_M_HL_C, 1, 8, "LD (HL),C"],
0x72: [self.LD_M_HL_D, 1, 8, "LD (HL),D"],
0x73: [self.LD_M_HL_E, 1, 8, "LD (HL),E"],
0x74: [self.LD_M_HL_H, 1, 8, "LD (HL),H"],
0x75: [self.LD_M_HL_L, 1, 8, "LD (HL),L"],
0x76: [self.HALT, 1, 8, "HALT"],
0x77: [self.LD_M_HL_A, 1, 8, "LD (HL),A"],
0x78: [self.LD_A_B, 1, 4, "LD A,B"],
0x79: [self.LD_A_C, 1, 4, "LD A,C"],
0x7A: [self.LD_A_D, 1, 4, "LD A,D"],
0x7B: [self.LD_A_E, 1, 4, "LD A,E"],
0x7C: [self.LD_A_H, 1, 4, "LD A,H"],
0x7D: [self.LD_A_L, 1, 4, "LD A,L"],
0x7E: [self.LD_A_M_HL, 1, 8, "LD A,(HL)"],
0x7F: [self.LD_A_A, 1, 4, "LD A,A"],
0x80: [self.ADD_A_B, 1, 4, "ADD A,B"],
0x81: [self.ADD_A_C, 1, 4, "ADD A,C"],
0x82: [self.ADD_A_D, 1, 4, "ADD A,D"],
0x83: [self.ADD_A_E, 1, 4, "ADD A,E"],
0x84: [self.ADD_A_H, 1, 4, "ADD A,H"],
0x85: [self.ADD_A_L, 1, 4, "ADD A,L"],
0x86: [self.ADD_A_M_HL, 1, 8, "ADD A,(HL)"],
0x87: [self.ADD_A_A, 1, 4, "ADD A,A"],
0x88: [self.ADC_A_B, 1, 4, "ADC A,B"],
0x89: [self.ADC_A_C, 1, 4, "ADD A,C"],
0x8A: [self.ADC_A_D, 1, 4, "ADD A,D"],
0x8B: [self.ADC_A_E, 1, 4, "ADD A,E"],
0x8C: [self.ADC_A_H, 1, 4, "ADD A,H"],
0x8D: [self.ADC_A_L, 1, 4, "ADD A,L"],
0x8E: [self.ADC_A_M_HL, 1, 8, "ADD A,(HL)"],
0x8F: [self.ADC_A_A, 1, 4, "ADC A,A"],
0x90: [self.SUB_B, 1, 4, "SUB B"],
0x91: [self.SUB_C, 1, 4, "SUB C"],
0x92: [self.SUB_D, 1, 4, "SUB D"],
0x93: [self.SUB_E, 1, 4, "SUB E"],
0x94: [self.SUB_H, 1, 4, "SUB H"],
0x95: [self.SUB_L, 1, 4, "SUB L"],
0x96: [self.SUB_M_HL, 1, 8, "SUB (HL)"],
0x97: [self.SUB_A, 1, 4, "SUB A"],
0x98: [self.SBC_A_B, 1, 4, "SBC A,B"],
0x99: [self.SBC_A_C, 1, 4, "SBC A,C"],
0x9A: [self.SBC_A_D, 1, 4, "SBC A,D"],
0x9B: [self.SBC_A_E, 1, 4, "SBC A,E"],
0x9C: [self.SBC_A_H, 1, 4, "SBC A,H"],
0x9D: [self.SBC_A_L, 1, 4, "SBC A,L"],
0x9E: [self.SBC_A_M_HL, 1, 8, "SBC A,(HL)"],
0x9F: [self.SBC_A_A, 1, 4, "SBC A,A"],
0xA0: [self.AND_B, 1, 4, "AND B"],
0xA1: [self.AND_C, 1, 4, "AND C"],
0xA2: [self.AND_D, 1, 4, "AND D"],
0xA3: [self.AND_E, 1, 4, "AND E"],
0xA4: [self.AND_H, 1, 4, "AND H"],
0xA5: [self.AND_L, 1, 4, "AND L"],
0xA6: [self.AND_M_HL, 1, 8, "AND (HL)"],
0xA7: [self.AND_A, 1, 4, "AND A"],
0xA8: [self.XOR_B, 1, 4, "XOR B"],
0xA9: [self.XOR_C, 1, 4, "XOR C"],
0xAA: [self.XOR_D, 1, 4, "XOR D"],
0xAB: [self.XOR_E, 1, 4, "XOR E"],
0xAC: [self.XOR_H, 1, 4, "XOR H"],
0xAD: [self.XOR_L, 1, 4, "XOR L"],
0xAE: [self.XOR_M_HL, 1, 8, "XOR (HL)"],
0xAF: [self.XOR_A, 1, 4, "XOR A"],
0xB0: [self.OR_B, 1, 4, "OR B"],
0xB1: [self.OR_C, 1, 4, "OR C"],
0xB2: [self.OR_D, 1, 4, "OR D"],
0xB3: [self.OR_E, 1, 4, "OR E"],
0xB4: [self.OR_H, 1, 4, "OR H"],
0xB5: [self.OR_L, 1, 4, "OR L"],
0xB6: [self.OR_M_HL, 1, 8, "OR (HL)"],
0xB7: [self.OR_A, 1, 4, "OR A"],
0xB8: [self.CP_B, 1, 4, "CP B"],
0xB9: [self.CP_C, 1, 4, "CP C"],
0xBA: [self.CP_D, 1, 4, "CP D"],
0xBB: [self.CP_E, 1, 4, "CP E"],
0xBC: [self.CP_H, 1, 4, "CP H"],
0xBD: [self.CP_L, 1, 4, "CP L"],
0xBE: [self.CP_M_HL, 1, 8, "CP (HL)"],
0xBF: [self.CP_A, 1, 4, "CP A"],
0xC0: [self.RET_NZ, 1, 8, "RET NZ"],
0xC1: [self.POP_BC, 1, 12, "POP BC"],
0xC2: [self.JP_NZ_a16, 3, 12, "JP NZ,a16"],
0xC3: [self.JP_a16, 3, 16, "JP a16"],
0xC4: [self.CALL_NZ_a16, 3, 12, "CALL NZ,a16"],
0xC5: [self.PUSH_BC, 1, 16, "PUSH BC"],
0xC6: [self.ADD_A_d8, 2, 8, "ADD A,d8"],
0xC7: [self.RST_00H, 1, 16, "RST 00H"],
0xC8: [self.RET_Z, 1, 8, "RET Z"],
0xC9: [self.RET, 1, 16, "RET"],
0xCA: [self.JP_Z_a16, 3, 12, "JP Z,a16"],
0xCB: [self.PREFIX_CB, 1, 4, "PREFIX CB"],
0xCC: [self.CALL_Z_a16, 3, 12, "CALL Z,a16"],
0xCD: [self.CALL_a16, 3, 24, "CALL a16"],
0xCE: [self.ADC_A_d8, 2, 8, "ADC A,d8"],
0xCF: [self.RST_08H, 1, 16, "RST 08H"],
0xD0: [self.RET_NC, 1, 8, "RET NC"],
0xD1: [self.POP_DE, 1, 12, "POP DE"],
0xD2: [self.JP_NC_a16, 3, 12, "JP NC,a16"],
0xD3: [self.KILL, 1, 4, "KILL"],
0xD4: [self.CALL_NC_a16, 3, 12, "CALL NC,a16"],
0xD5: [self.PUSH_DE, 1, 16, "PUSH DE"],
0xD6: [self.SUB_d8, 2, 8, "SUB d8"],
0xD7: [self.RST_10H, 1, 16, "RST 10H"],
0xD8: [self.RET_C, 1, 8, "RET C"],
0xD9: [self.RETI, 1, 16, "RETI"],
0xDA: [self.JP_C_a16, 3, 12, "JP C,a16"],
0xDB: [self.KILL, 1, 4, "KILL"],
0xDC: [self.CALL_C_a16, 3, 12, "CALL C,a16"],
0xDD: [self.KILL, 1, 4, "KILL"],
0xDE: [self.SBC_A_d8, 2, 8, "SBC A,d8"],
0xDF: [self.RST_18H, 1, 16, "RST 18H"],
0xE0: [self.LDH_M_a8_A, 2, 12, "LDH (a8),A"],
0xE1: [self.POP_HL, 1, 12, "POP HL"],
0xE2: [self.LD_M_C_A, 1, 8, "LD (C),A"], #
0xE3: [self.KILL, 1, 4, "KILL"],
0xE4: [self.KILL, 1, 4, "KILL"],
0xE5: [self.PUSH_HL, 1, 16, "PUSH HL"],
0xE6: [self.AND_d8, 2, 8, "AND d8"],
0xE7: [self.RST_20H, 1, 16, "RST 20H"],
0xE8: [self.ADD_SP_r8, 2, 16, "ADD SP,r8"],
0xE9: [self.JP_M_HL, 1, 4, "JP (HL)"],
0xEA: [self.LD_M_a16_A, 3, 16, "LD (a16),A"],
0xEB: [self.KILL, 1, 4, "KILL"],
0xEC: [self.KILL, 1, 4, "KILL"],
0xED: [self.KILL, 1, 4, "KILL"],
0xEE: [self.XOR_d8, 2, 8, "XOR d8"],
0xEF: [self.RST_28H, 1, 16, "RST 28H"],
0xF0: [self.LDH_A_M_a8, 2, 12, "LDH A,(a8)"],
0xF1: [self.POP_AF, 1, 12, "POP AF"],
0xF2: [self.LD_A_M_C, 1, 8, "LD A,(C)"], #
0xF3: [self.DI, 1, 4, "DI"],
0xF4: [self.KILL, 1, 4, "KILL"],
0xF5: [self.PUSH_AF, 1, 16, "PUSH AF"],
0xF6: [self.OR_d8, 2, 8, "OR d8"],
0xF7: [self.RST_30H, 1, 16, "RST 30H"],
0xF8: [self.LD_HL_SP_r8, 2, 12, "LD HL,SP+r8"],
0xF9: [self.LD_SP_HL, 1, 8, "LD SP,HL"],
0xFA: [self.LD_A_M_a16, 3, 16, "LD A,(a16)"],
0xFB: [self.EI, 1, 4, "EI"],
0xFC: [self.KILL, 1, 4, "KILL"],
0xFD: [self.KILL, 1, 4, "KILL"],
0xFE: [self.CP_d8, 2, 8, "CP d8"],
0xFF: [self.RST_38H, 1, 16, "RST 38H"]
}
# 8-bit registers
self.A = 0x00
self.B = 0x00
self.C = 0x00
self.D = 0x00
self.E = 0x00
self.F = 0x00
self.H = 0x00
self.L = 0x00
# 16-bit registers
self.PC = 0x0000
self.SP = 0xFFFE
# Flags
self.flags = {
"Z": 0,
"N": 0,
"H": 0,
"C": 0
}
# Keep track of cycles
self.cycles = 0
# Interupts
self.INT_ENABLE = True
# The current operational code
self.opcode = 0x00
# Default instruction
self.instruction_params = [self.NOP, 1, 4]
self.instruction_function = self.NOP
self.instruction_length = 1
self.instruction_cycles = 4
self.debug_string = "NOP"
self.args = [0x00, 0x00, 0x00]
# Initialize the memory (loads ROM into memory map)
self.memory = memory
self.DEBUG = True
self.PREFIX_CB = False
def print_registers(self):
A = "A=" + hex(self.A)[2:].zfill(2).upper()
B = "B=" + hex(self.B)[2:].zfill(2).upper()
C = "C=" + hex(self.C)[2:].zfill(2).upper()
D = "D=" + hex(self.D)[2:].zfill(2).upper()
E = "E=" + hex(self.E)[2:].zfill(2).upper()
H = "H=" + hex(self.H)[2:].zfill(2).upper()
L = "L=" + hex(self.L)[2:].zfill(2).upper()
SP = "SP=" + hex(self.SP)[2:].zfill(4).upper()
PC = "PC=" + hex(self.PC)[2:].zfill(4).upper()
Fl = "Z N H C"
F = str(self.flags["Z"]) + " " + str(self.flags["N"]) + " " + str(self.flags["H"]) + " " + str(self.flags["C"])
print(" " + A + " " + B + " " + C + " " + D + " " + E + " " + H + " " + L)
print(" " + SP)
print(" " + PC)
print(" " + Fl)
print(" " + F)
# Get 16-bit AF
def get_AF(self):
return ((self.A << 8) | (self.F)) & 0xFFFF
# Get 16-bit BC
def get_BC(self):
return ((self.B << 8) | (self.C)) & 0xFFFF
# Get 16-bit DE
def get_DE(self):
return ((self.D << 8) | (self.E)) & 0xFFFF
# Get 16-bit HL
def get_HL(self):
return ((self.H << 8) | (self.L)) & 0xFFFF
# Increment 8-bit register
def INC_REGISTER_8(self, register=""):
if register == "A": reg = self.A
if register == "B": reg = self.B
if register == "C": reg = self.C
if register == "D": reg = self.D
if register == "E": reg = self.E
if register == "H": reg = self.H
if register == "L": reg = self.L
# H - Set if carry from bit 3
if reg & 0x0F == 0x0F:
self.flags["H"] = 1
else:
self.flags["H"] = 0
reg = (reg + 1) & 0xFF
# Z - Set if result is zero
if reg == 0:
self.flags["Z"] = 1
else:
self.flags["Z"] = 0
# N - Reset
self.flags["N"] = 0
if register == "A": self.A = reg
if register == "B": self.B = reg
if register == "C": self.C = reg
if register == "D": self.D = reg
if register == "E": self.E = reg
if register == "H": self.H = reg
if register == "L": self.L = reg
# Decrement 8-bit register
def DEC_REGISTER_8(self, register=""):
if register == "A": reg = self.A
if register == "B": reg = self.B
if register == "C": reg = self.C
if register == "D": reg = self.D
if register == "E": reg = self.E
if register == "H": reg = self.H
if register == "L": reg = self.L
# H - Set if not borrow from bit 4
if (reg & 0x0F) > 0x01:
self.flags["H"] = 1
else:
self.flags["H"] = 0
reg = (reg - 1) & 0xFF
# Z - Set if result is zero
if reg == 0:
self.flags["Z"] = 1
else:
self.flags["Z"] = 0
# N - Set
self.flags["N"] = 1
if register == "A": self.A = reg
if register == "B": self.B = reg
if register == "C": self.C = reg
if register == "D": self.D = reg
if register == "E": self.E = reg
if register == "H": self.H = reg
if register == "L": self.L = reg
# Increment 16-bit registers
def INC_REGISTER_16(self, register=""):
if register == "BC": reg = self.get_BC()
if register == "DE": reg = self.get_DE()
if register == "HL": reg = self.get_HL()
if register == "SP": reg = self.SP
reg = (reg + 1) & 0xFFFF
if register == "BC":
self.C = reg & 0x00FF
self.B = (reg & 0xFF00) >> 8
if register == "DE":
self.E = reg & 0x00FF
self.D = (reg & 0xFF00) >> 8
if register == "HL":
self.L = reg & 0x00FF
self.H = (reg & 0xFF00) >> 8
if register == "SP":
self.SP = reg
# Decrement 16-bit registers
def DEC_REGISTER_16(self, register = ""):
if register == "BC": reg = self.get_BC()
if register == "DE": reg = self.get_DE()
if register == "HL": reg = self.get_HL()
if register == "SP": reg = self.SP
reg = (reg - 1) & 0xFFFF
if register == "BC":
self.C = reg & 0x00FF
self.B = (reg & 0xFF00) >> 8
if register == "DE":
self.E = reg & 0x00FF
self.D = (reg & 0xFF00) >> 8
if register == "HL":
self.L = reg & 0x00FF
self.H = (reg & 0xFF00) >> 8
if register == "SP":
self.SP = reg
# Pop a byte from the stack
def POP(self):
self.SP += 1
val = self.memory.read(self.SP)
return val
# Push a byte to the stack
def PUSH(self, byte):
self.memory.write(self.SP, byte)
self.SP -= 1
# Fetch the next opcode
def fetch(self):
self.opcode = self.memory.read(self.PC)
# Decode and acquire the arguments
def decode(self):
# Attempt to get the instruction
try:
self.instruction_params = self.instructions[self.opcode]
except:
print("***NOT IN INSTRUCTION SET***")
print("Opcode : 0x" + hex(self.opcode)[2:].zfill(2).upper())
# Get the parameters of the instruction
self.instruction_function = self.instruction_params[INSTRUCTION_INDEX]
self.instruction_length = self.instruction_params[LENGTH_INDEX]
self.instruction_cycles = self.instruction_params[CYCLES_INDEX]
self.debug_string = self.instruction_params[DEBUG_INDEX]
# Get the arguments of the instruction and increment PC
for i in range(0, self.instruction_length-1):
self.args[i] = self.memory.read(self.PC + 1 + i)
# Increment the PC accordingly
self.PC += self.instruction_length
# Execute the next instruction
def execute(self):
# Execute the desired instruction with the arguments obtained
self.instruction_function()
# Increment the cycle counter
# Will increment more other places for opcodes with variant cycle counts
self.cycles += self.instruction_cycles
if self.PREFIX_CB == True:
self.fetch()
self.CB_execute()
if self.DEBUG:
print("CB OPCODE : " + hex(self.opcode)[2:].zfill(2).upper())
# The last two bytes read were Prefix CB and the special opcode
# With this, we are pointing to the next instruction
self.PC += 1
# Cycles handled within CB_execute()
self.PREFIX_CB = False
# 0xXX - Kill operation
# - - - -
def KILL(self):
print("***KILL***")
while True: pass
# 0x00 - No operation
# - - - -
def NOP(self):
pass
# 0x01 - Load into registers BC immediate 16-bit data
# - - - -
def LD_BC_d16(self):
self.C = self.args[0]
self.B = self.args[1]
# 0x02 - Load into memory address (BC) register A
# - - - -
def LD_M_BC_A(self):
self.memory.write(self.get_BC(), self.A)
# 0x03 - Increment registers BC
# - - - -
def INC_BC(self):
self.INC_REGISTER_16("BC")
# 0x04 - Increment register B
# Z 0 H -
def INC_B(self):
self.INC_REGISTER_8("B")
# 0x05 - Decrement register B
# Z 1 H -
def DEC_B(self):
self.DEC_REGISTER_8("B")
# 0x06 - Load register B immediate 8-bit data
# - - - -
def LD_B(self):
self.B = self.args[0]
# 0x07 - Rotate A left, old bit 7 to carry flag
# Z 0 0 C
def RLCA(self):
# C - Contains old bit 7 data
self.flags["C"] = (self.A & 0x80) >> 8
self.A = (self.A << 1) & 0xFF
self.A |= self.flags["C"]
# Z - Set if result is zero
if self.A == 0:
self.flags["Z"] = 1
else:
self.flags["Z"] = 0
# N - Reset
self.flags["N"] = 0
# H - Reset
self.flags["H"] = 0
# 0x08 - Load into memory address (16-bit data) register SP
# - - - -
def LD_M_d16_SP(self):
self.memory.write((self.args[1] << 8) | self.args[0], self.SP & 0x00FF)
self.memory.write(((self.args[1] << 8) | self.args[0]) + 1, (self.SP & 0xFF00) >> 8)
# 0x09 - Add into registers HL, HL+BC
# - 0 H C
def ADD_HL_BC(self):
# H - Set if carry from bit 11
if (((self.get_HL() & 0xFFFF) + (self.get_BC() & 0xFFFF)) & 0x1000) == 0x1000:
self.flags["H"] = 1
else:
self.flags["H"] = 0
# C - Set if carry from bit 15
if (((self.get_HL() & 0xFFFF) + (self.get_BC() & 0xFFFF)) & 0x8000) == 0x8000:
self.flags["C"] = 1
else:
self.flags["H"] = 0
HL = self.get_HL()
HL = (HL + self.get_BC()) & 0xFFFF
self.L = HL & 0x00FF;
self.H = (HL & 0xFF00) >> 8
# N - Reset
self.flags["N"] = 0
# 0x0A - Load register A data at memory address (BC)
# - - - -
def LD_A_M_BC(self):
self.A = self.memory.read(self.get_BC())
# 0x0B - Decrement registers BC
# - - - -
def DEC_BC(self):
self.DEC_REGISTER_16("BC")
# 0x0C - Increment register C
# Z 0 H -
def INC_C(self):
self.INC_REGISTER_8("C")
# 0x0D - Decrement register C
# Z 1 H -
def DEC_C(self):
self.DEC_REGISTER_8("C")
# 0x0E - Load register C immediate 8-bit data
# - - - -
def LD_C(self):
self.C = self.args[0]
# 0x0F - Rotate A right, old bit 0 to carry flag
# 0 0 0 C
def RRCA(self):
# C - Contains old bit 0 data
self.flags["C"] = self.A & 0x01
self.A = (self.A >> 1)
self.A |= (self.flags["C"] << 8)
# Z - Set if result is zero
if self.A == 0:
self.flags["Z"] = 1
else:
self.flags["Z"] = 0
# N - Reset
self.flags["N"] = 0
# H - Reset
self.flags["H"] = 0
# 0x10 - Halt CPU & LCD display until button pressed
# - - - -
def STOP():
print("***STOP***")
while True: pass
# 0x11 - Load into registers DE immediate 16-bit data
# - - - -
def LD_DE_d16(self):
self.E = self.args[0]
self.D = self.args[1]
# 0x12 - Load into memory address (DE) register A
# - - - -
def LD_M_DE_A(self):
self.memory.write(self.get_DE(), self.A)
# 0x13 - Increment registers DE
# - - - -
def INC_DE(self):
self.INC_REGISTER_16("DE")
# 0x14 - Increment register D
# Z 0 H -
def INC_D(self):
self.INC_REGISTER_8("D")
# 0x15 - Decrement register B
# Z 1 H -
def DEC_D(self):
self.DEC_REGISTER_8("D")
# 0x16 - Load register D immediate 8-bit data
# - - - -
def LD_D(self):
self.D = self.args[0]
# 0x17 - Rotate A left through carry flag
# 0 0 0 C
def RLA(self):
C = self.flags["C"]
# C - Contains old bit 7 data
self.flags["C"] = (self.A & 0x80) >> 7
self.A = (self.A << 1) & 0xFF
self.A |= C
# Z - Set if result is zero
if self.A == 0:
self.flags["Z"] = 1
else:
self.flags["Z"] = 0
# N - Reset
self.flags["N"] = 0
# H - Reset
self.flags["H"] = 0
# 0x18 - Add signed data to current address and jump to it
# - - - -
def JR_r8(self):
if self.args[0] & 0x80:
val = -0x100 + self.args[0]
self.PC += val
else:
self.PC += self.args[0]
# 0x19 - Add into registers HL, HL+DE
# - 0 H C
def ADD_HL_DE(self):
# H - Set if carry from bit 11
if (((self.get_HL() & 0xFFFF) + (self.get_DE() & 0xFFFF)) & 0x1000) == 0x1000:
self.flags["H"] = 1
else:
self.flags["H"] = 0
# H - Set if carry from bit 15
if (((self.get_HL() & 0xFFFF) + (self.get_DE() & 0xFFFF)) & 0x8000) == 0x8000:
self.flags["C"] = 1
else:
self.flags["C"] = 0
HL = self.get_HL()
HL = (HL + self.get_DE()) & 0xFFFF
self.L = HL & 0x00FF;
self.H = (HL & 0xFF00) >> 8
# N - Reset
self.flags["N"] = 0
# 0x1A - Load register A data at memory address (DE)
# - - - -
def LD_A_M_DE(self):
self.A = self.memory.read(self.get_DE())
# 0x1B - Decrement registers DE
# - - - -
def DEC_DE(self):
self.DEC_REGISTER_16("DE")
# 0x1C - Increment register E
# Z 0 H -
def INC_E(self):
self.INC_REGISTER_8("E")
# 0x1D - Decrement register E
# Z 1 H -
def DEC_E(self):
self.DEC_REGISTER_8("E")
# 0x1E - Load register E immediate 8-bit data
# - - - -
def LD_E(self):
self.E = self.args[0]
# 0x1F - Rotate A right through carry flag
# 0 0 0 C
def RRA(self):
C = self.flags["C"]
# C - Contains old bit 0 data
self.flags["C"] = self.A & 0x01
self.A = (self.A >> 1) & 0xFF
self.A |= (C << 8)
# Z - Set if result is zero
if self.A == 0:
self.flags["Z"] = 1
else:
self.flags["Z"] = 0
# N - Reset
self.flags["N"] = 0
# H - Reset
self.flags["H"] = 0
# 0x20 - Jump if Z flag is 0
# - - - -
def JR_NZ_r8(self):
if self.flags["Z"] == 0:
if self.args[0] & 0x80:
val = -0x100 + self.args[0]
self.PC += val
else:
self.PC += self.args[0]
# 0x21 - Load into registers HL immediate 16-bit data
# - - - -
def LD_HL_d16(self):
self.L = self.args[0]
self.H = self.args[1]
# 0x22 - Load into memory address HL, increment HL
# - - - -
def LD_M_HLP_A(self):
self.memory.write(self.get_HL(), self.A)
self.INC_REGISTER_16("HL")
# 0x23 - Increment registers HL
# - - - -
def INC_HL(self):
self.INC_REGISTER_16("HL")
# 0x24 - Increment register H
# Z 0 H -
def INC_H(self):
self.INC_REGISTER_8("H")
# 0x25 - Decrement register H
# Z 1 H -
def DEC_H(self):
self.DEC_REGISTER_8("H")
# 0x26 - Load register H immediate 8-bit data
# - - - -
def LD_H(self):
self.H = self.args[0]
# 0x27 - Decimal adjust register A
# Z - 0 C
def DAA(self):
# http://forums.nesdev.com/viewtopic.php?t=9088
A = self.A
if self.flags["N"]:
if self.flags["H"] or ((A & 0x0F) > 9):
A += 0x06
if self.flags["C"] or (A > 0x9F):
A += 0x60
else:
if self.flags["H"]:
A = (A - 6) & 0xFF
if self.flags["C"]:
A -= 0x60
self.flags["H"] = 0
self.flags["Z"] = 0
if ((A & 0x100) == 0x100):
self.flags["C"] = 1
self.A = A & 0xFF
if self.A == 0:
self.flags["Z"] = 1
# 0x28 - Jump if Z flag is 1
# - - - -
def JR_Z_r8(self):
if self.flags["Z"] == 1:
if self.args[0] & 0x80:
val = -0x100 + args[0]
self.PC += val
else:
self.PC += self.args[0]
# 0x29 - Add into registers HL, HL+HL
#- 0 H C
def ADD_HL_HL(self):
# H - Set if carry from bit 11
if (((self.get_HL() & 0xFFFF) + (self.get_HL() & 0xFFFF)) & 0x1000) == 0x1000:
self.flags["H"] = 1
else:
self.flags["H"] = 0
# H - Set if carry from bit 15
if (((self.get_HL() & 0xFFFF) + (self.get_HL() & 0xFFFF)) & 0x8000) == 0x8000:
self.flags["C"] = 1
else:
self.flags["C"] = 0
HL = self.get_HL()
HL = (HL + HL) & 0xFFFF
self.L = HL & 0x00FF;
self.H = (HL & 0xFF00) >> 8
# N - Reset
self.flags["N"] = 0
# 0x2A - Load register A data at memory address (HL), increment HL
# - - - -
def LD_A_M_HLP(self):
self.A = self.memory.read(self.get_HL())
self.INC_REGISTER_16("HL")
# 0x2B - Decrement registers HL
# - - - -
def DEC_HL(self):
self.DEC_REGISTER_16("HL")
# 0x2C - Increment register L
# Z 0 H -
def INC_L(self):
self.INC_REGISTER_8("L")
# 0x2D - Decrement register L
# Z 1 H -
def DEC_L(self):