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Reading design: top_avr_core_v8.prj
ERROR:Xst:439 - No write access in xst/projnav.tmp\
Command Line: C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\ngdbuild.exe
-intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc BPC3013_Papilio_DUO.ucf
-bm top_avr_core_V8.bmm -p xc6slx9-tqg144-2 top_avr_core_v8.ngc
top_avr_core_v8.ngd
Reading NGO file
"D:/Dropbox/GadgetFactory/archive/AVR8/svn/trunk/top_avr_core_v8.ngc" ...
Gathering constraint information from source properties...
Done.
Annotating constraints to design from ucf file "BPC3013_Papilio_DUO.ucf" ...
Resolving constraint associations...
Checking Constraint Associations...
Done...
Processing BMM file "top_avr_core_V8.bmm" ...
Checking expanded design ...
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 0
Writing NGD file "top_avr_core_v8.ngd" ...
Total REAL time to NGDBUILD completion: 10 sec
Total CPU time to NGDBUILD completion: 10 sec
Writing NGDBUILD log file "top_avr_core_v8.bld"...
NGDBUILD done.
Using target part "6slx9tqg144-2".
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Updating timing models...
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
Running timing-driven placement...
Total REAL time at the beginning of Placer: 13 secs
Total CPU time at the beginning of Placer: 12 secs
Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:87dbc934) REAL time: 14 secs
Phase 2.7 Design Feasibility Check
WARNING:Place:837 - Partially locked IO Bus is found.
Following components of the bus are not locked:
Comp: porta<0>
WARNING:Place:838 - An IO Bus with more than one IO standard is found.
Components associated with this bus are as follows:
Comp: porta<0> IOSTANDARD = LVCMOS25
Comp: porta<1> IOSTANDARD = LVCMOS33
Comp: porta<2> IOSTANDARD = LVCMOS33
Comp: porta<3> IOSTANDARD = LVCMOS33
Comp: porta<4> IOSTANDARD = LVCMOS33
Comp: porta<5> IOSTANDARD = LVCMOS33
Comp: porta<6> IOSTANDARD = LVCMOS33
Comp: porta<7> IOSTANDARD = LVCMOS33
INFO:Place:834 - Only a subset of IOs are locked. Out of 51 IOs, 50 are locked
and 1 are not locked. If you would like to print the names of these IOs,
please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1.
Phase 2.7 Design Feasibility Check (Checksum:87dbc934) REAL time: 15 secs
Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:87dbc934) REAL time: 15 secs
Phase 4.2 Initial Placement for Architecture Specific Features
...
Phase 4.2 Initial Placement for Architecture Specific Features
(Checksum:7868fb70) REAL time: 22 secs
Phase 5.36 Local Placement Optimization
Phase 5.36 Local Placement Optimization (Checksum:7868fb70) REAL time: 22 secs
Phase 6.30 Global Clock Region Assignment
Phase 6.30 Global Clock Region Assignment (Checksum:7868fb70) REAL time: 22 secs
Phase 7.3 Local Placement Optimization
...
Phase 7.3 Local Placement Optimization (Checksum:74fbcf08) REAL time: 22 secs
Phase 8.5 Local Placement Optimization
Phase 8.5 Local Placement Optimization (Checksum:786e08e8) REAL time: 23 secs
Phase 9.8 Global Placement
....................
..........................................
.............................................
...........................................................
......................
Phase 9.8 Global Placement (Checksum:d236f596) REAL time: 47 secs
Phase 10.5 Local Placement Optimization
Phase 10.5 Local Placement Optimization (Checksum:d236f596) REAL time: 47 secs
Phase 11.18 Placement Optimization
Phase 11.18 Placement Optimization (Checksum:36f0b4de) REAL time: 53 secs
Phase 12.5 Local Placement Optimization
Phase 12.5 Local Placement Optimization (Checksum:36f0b4de) REAL time: 53 secs
Phase 13.34 Placement Validation
Phase 13.34 Placement Validation (Checksum:41e8474) REAL time: 53 secs
Total REAL time to Placer completion: 54 secs
Total CPU time to Placer completion: 51 secs
Running post-placement packing...
Writing output files...
Design Summary:
Number of errors: 0
Number of warnings: 3
Slice Logic Utilization:
Number of Slice Registers: 936 out of 11,440 8%
Number used as Flip Flops: 935
Number used as Latches: 1
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 2,780 out of 5,720 48%
Number used as logic: 2,769 out of 5,720 48%
Number using O6 output only: 2,366
Number using O5 output only: 43
Number using O5 and O6: 360
Number used as ROM: 0
Number used as Memory: 5 out of 1,440 1%
Number used as Dual Port RAM: 0
Number used as Single Port RAM: 0
Number used as Shift Register: 5
Number using O6 output only: 5
Number using O5 output only: 0
Number using O5 and O6: 0
Number used exclusively as route-thrus: 6
Number with same-slice register load: 4
Number with same-slice carry load: 2
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 935 out of 1,430 65%
Number of MUXCYs used: 872 out of 2,860 30%
Number of LUT Flip Flop pairs used: 2,953
Number with an unused Flip Flop: 2,062 out of 2,953 69%
Number with an unused LUT: 173 out of 2,953 5%
Number of fully used LUT-FF pairs: 718 out of 2,953 24%
Number of unique control sets: 103
Number of slice register sites lost
to control set restrictions: 187 out of 11,440 1%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 51 out of 102 50%
Number of LOCed IOBs: 50 out of 51 98%
Specific Feature Utilization:
Number of RAMB16BWERs: 10 out of 32 31%
Number of RAMB8BWERs: 0 out of 64 0%
Number of BUFIO2/BUFIO2_2CLKs: 1 out of 32 3%
Number used as BUFIO2s: 1
Number used as BUFIO2_2CLKs: 0
Number of BUFIO2FB/BUFIO2FB_2CLKs: 1 out of 32 3%
Number used as BUFIO2FBs: 1
Number used as BUFIO2FB_2CLKs: 0
Number of BUFG/BUFGMUXs: 2 out of 16 12%
Number used as BUFGs: 2
Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 1 out of 4 25%
Number used as DCMs: 1
Number used as DCM_CLKGENs: 0
Number of ILOGIC2/ISERDES2s: 0 out of 200 0%
Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 200 0%
Number of OLOGIC2/OSERDES2s: 0 out of 200 0%
Number of BSCANs: 0 out of 4 0%
Number of BUFHs: 0 out of 128 0%
Number of BUFPLLs: 0 out of 8 0%
Number of BUFPLL_MCBs: 0 out of 4 0%
Number of DSP48A1s: 0 out of 16 0%
Number of ICAPs: 0 out of 1 0%
Number of MCBs: 0 out of 2 0%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 0 out of 2 0%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 3.18
Peak Memory Usage: 438 MB
Total REAL time to MAP completion: 57 secs
Total CPU time to MAP completion: 55 secs
Mapping completed.
See MAP report file "top_avr_core_v8_map.mrp" for details.
Reading design: top_avr_core_v8.prj
ERROR:Xst:439 - No write access in xst/projnav.tmp\
Command Line: C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\ngdbuild.exe
-intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc BPC3013_Papilio_DUO.ucf
-bm top_avr_core_V8.bmm -p xc6slx9-tqg144-2 top_avr_core_v8.ngc
top_avr_core_v8.ngd
Reading NGO file
"D:/Dropbox/GadgetFactory/archive/AVR8/svn/trunk/top_avr_core_v8.ngc" ...
Gathering constraint information from source properties...
Done.
Annotating constraints to design from ucf file "BPC3013_Papilio_DUO.ucf" ...
Resolving constraint associations...
Checking Constraint Associations...
Done...
Processing BMM file "top_avr_core_V8.bmm" ...
Checking expanded design ...
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 0
Writing NGD file "top_avr_core_v8.ngd" ...
Total REAL time to NGDBUILD completion: 11 sec
Total CPU time to NGDBUILD completion: 10 sec
Writing NGDBUILD log file "top_avr_core_v8.bld"...
NGDBUILD done.
Using target part "6slx9tqg144-2".
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Updating timing models...
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
Running timing-driven placement...
Total REAL time at the beginning of Placer: 12 secs
Total CPU time at the beginning of Placer: 12 secs
Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:87dbc934) REAL time: 13 secs
Phase 2.7 Design Feasibility Check
WARNING:Place:837 - Partially locked IO Bus is found.
Following components of the bus are not locked:
Comp: porta<0>
WARNING:Place:838 - An IO Bus with more than one IO standard is found.
Components associated with this bus are as follows:
Comp: porta<0> IOSTANDARD = LVCMOS25
Comp: porta<1> IOSTANDARD = LVCMOS33
Comp: porta<2> IOSTANDARD = LVCMOS33
Comp: porta<3> IOSTANDARD = LVCMOS33
Comp: porta<4> IOSTANDARD = LVCMOS33
Comp: porta<5> IOSTANDARD = LVCMOS33
Comp: porta<6> IOSTANDARD = LVCMOS33
Comp: porta<7> IOSTANDARD = LVCMOS33
INFO:Place:834 - Only a subset of IOs are locked. Out of 51 IOs, 50 are locked
and 1 are not locked. If you would like to print the names of these IOs,
please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1.
Phase 2.7 Design Feasibility Check (Checksum:87dbc934) REAL time: 14 secs
Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:87dbc934) REAL time: 14 secs
Phase 4.2 Initial Placement for Architecture Specific Features
...
Phase 4.2 Initial Placement for Architecture Specific Features
(Checksum:7868fb70) REAL time: 21 secs
Phase 5.36 Local Placement Optimization
Phase 5.36 Local Placement Optimization (Checksum:7868fb70) REAL time: 21 secs
Phase 6.30 Global Clock Region Assignment
Phase 6.30 Global Clock Region Assignment (Checksum:7868fb70) REAL time: 21 secs
Phase 7.3 Local Placement Optimization
...
Phase 7.3 Local Placement Optimization (Checksum:74fbcf08) REAL time: 21 secs
Phase 8.5 Local Placement Optimization
Phase 8.5 Local Placement Optimization (Checksum:786e08e8) REAL time: 22 secs
Phase 9.8 Global Placement
....................
..........................................
.............................................
...........................................................
......................
Phase 9.8 Global Placement (Checksum:d236f596) REAL time: 46 secs
Phase 10.5 Local Placement Optimization
Phase 10.5 Local Placement Optimization (Checksum:d236f596) REAL time: 47 secs
Phase 11.18 Placement Optimization
Phase 11.18 Placement Optimization (Checksum:36f0b4de) REAL time: 53 secs
Phase 12.5 Local Placement Optimization
Phase 12.5 Local Placement Optimization (Checksum:36f0b4de) REAL time: 53 secs
Phase 13.34 Placement Validation
Phase 13.34 Placement Validation (Checksum:41e8474) REAL time: 53 secs
Total REAL time to Placer completion: 54 secs
Total CPU time to Placer completion: 51 secs
Running post-placement packing...
Writing output files...
Design Summary:
Number of errors: 0
Number of warnings: 3
Slice Logic Utilization:
Number of Slice Registers: 936 out of 11,440 8%
Number used as Flip Flops: 935
Number used as Latches: 1
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 2,780 out of 5,720 48%
Number used as logic: 2,769 out of 5,720 48%
Number using O6 output only: 2,366
Number using O5 output only: 43
Number using O5 and O6: 360
Number used as ROM: 0
Number used as Memory: 5 out of 1,440 1%
Number used as Dual Port RAM: 0
Number used as Single Port RAM: 0
Number used as Shift Register: 5
Number using O6 output only: 5
Number using O5 output only: 0
Number using O5 and O6: 0
Number used exclusively as route-thrus: 6
Number with same-slice register load: 4
Number with same-slice carry load: 2
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 935 out of 1,430 65%
Number of MUXCYs used: 872 out of 2,860 30%
Number of LUT Flip Flop pairs used: 2,953
Number with an unused Flip Flop: 2,062 out of 2,953 69%
Number with an unused LUT: 173 out of 2,953 5%
Number of fully used LUT-FF pairs: 718 out of 2,953 24%
Number of unique control sets: 103
Number of slice register sites lost
to control set restrictions: 187 out of 11,440 1%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 51 out of 102 50%
Number of LOCed IOBs: 50 out of 51 98%
Specific Feature Utilization:
Number of RAMB16BWERs: 10 out of 32 31%
Number of RAMB8BWERs: 0 out of 64 0%
Number of BUFIO2/BUFIO2_2CLKs: 1 out of 32 3%
Number used as BUFIO2s: 1
Number used as BUFIO2_2CLKs: 0
Number of BUFIO2FB/BUFIO2FB_2CLKs: 1 out of 32 3%
Number used as BUFIO2FBs: 1
Number used as BUFIO2FB_2CLKs: 0
Number of BUFG/BUFGMUXs: 2 out of 16 12%
Number used as BUFGs: 2
Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 1 out of 4 25%
Number used as DCMs: 1
Number used as DCM_CLKGENs: 0
Number of ILOGIC2/ISERDES2s: 0 out of 200 0%
Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 200 0%
Number of OLOGIC2/OSERDES2s: 0 out of 200 0%
Number of BSCANs: 0 out of 4 0%
Number of BUFHs: 0 out of 128 0%
Number of BUFPLLs: 0 out of 8 0%
Number of BUFPLL_MCBs: 0 out of 4 0%
Number of DSP48A1s: 0 out of 16 0%
Number of ICAPs: 0 out of 1 0%
Number of MCBs: 0 out of 2 0%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 0 out of 2 0%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 3.18
Peak Memory Usage: 438 MB
Total REAL time to MAP completion: 57 secs
Total CPU time to MAP completion: 55 secs
Mapping completed.
See MAP report file "top_avr_core_v8_map.mrp" for details.
Constraints file: top_avr_core_v8.pcf.
Loading device for application Rf_Device from file '6slx9.nph' in environment C:\Xilinx\14.7\ISE_DS\ISE\.
"top_avr_core_v8" is an NCD, version 3.2, device xc6slx9, package tqg144, speed -2
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
Device speed data version: "PRODUCTION 1.23 2013-10-13".
Device Utilization Summary:
Slice Logic Utilization:
Number of Slice Registers: 936 out of 11,440 8%
Number used as Flip Flops: 935
Number used as Latches: 1
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 2,780 out of 5,720 48%
Number used as logic: 2,769 out of 5,720 48%
Number using O6 output only: 2,366
Number using O5 output only: 43
Number using O5 and O6: 360
Number used as ROM: 0
Number used as Memory: 5 out of 1,440 1%
Number used as Dual Port RAM: 0
Number used as Single Port RAM: 0
Number used as Shift Register: 5
Number using O6 output only: 5
Number using O5 output only: 0
Number using O5 and O6: 0
Number used exclusively as route-thrus: 6
Number with same-slice register load: 4
Number with same-slice carry load: 2
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 935 out of 1,430 65%
Number of MUXCYs used: 872 out of 2,860 30%
Number of LUT Flip Flop pairs used: 2,953
Number with an unused Flip Flop: 2,062 out of 2,953 69%
Number with an unused LUT: 173 out of 2,953 5%
Number of fully used LUT-FF pairs: 718 out of 2,953 24%
Number of slice register sites lost
to control set restrictions: 0 out of 11,440 0%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 51 out of 102 50%
Number of LOCed IOBs: 50 out of 51 98%
Specific Feature Utilization:
Number of RAMB16BWERs: 10 out of 32 31%
Number of RAMB8BWERs: 0 out of 64 0%
Number of BUFIO2/BUFIO2_2CLKs: 1 out of 32 3%
Number used as BUFIO2s: 1
Number used as BUFIO2_2CLKs: 0
Number of BUFIO2FB/BUFIO2FB_2CLKs: 1 out of 32 3%
Number used as BUFIO2FBs: 1
Number used as BUFIO2FB_2CLKs: 0
Number of BUFG/BUFGMUXs: 2 out of 16 12%
Number used as BUFGs: 2
Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 1 out of 4 25%
Number used as DCMs: 1
Number used as DCM_CLKGENs: 0
Number of ILOGIC2/ISERDES2s: 0 out of 200 0%
Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 200 0%
Number of OLOGIC2/OSERDES2s: 0 out of 200 0%
Number of BSCANs: 0 out of 4 0%
Number of BUFHs: 0 out of 128 0%
Number of BUFPLLs: 0 out of 8 0%
Number of BUFPLL_MCBs: 0 out of 4 0%
Number of DSP48A1s: 0 out of 16 0%
Number of ICAPs: 0 out of 1 0%
Number of MCBs: 0 out of 2 0%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 0 out of 2 0%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Overall effort level (-ol): High
Router effort level (-rl): High
Starting initial Timing Analysis. REAL time: 7 secs
Finished initial Timing Analysis. REAL time: 7 secs
Starting Router
Phase 1 : 13240 unrouted; REAL time: 7 secs
Phase 2 : 12260 unrouted; REAL time: 8 secs
Phase 3 : 6292 unrouted; REAL time: 16 secs
Phase 4 : 6292 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 16 secs
Updating file: top_avr_core_v8.ncd with current fully routed design.
Phase 5 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 32 secs
Phase 6 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 32 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 32 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 32 secs
Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 32 secs
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 34 secs
Total REAL time to Router completion: 34 secs
Total CPU time to Router completion: 34 secs
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
Generating "PAR" statistics.
**************************
Generating Clock Report
**************************
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
| clk16M | BUFGMUX_X3Y13| No | 345 | 0.117 | 1.508 |
+---------------------+--------------+------+------+------------+-------------+
|GND_13_o_GND_13_o_OR | | | | | |
| _1256_o | Local| | 1 | 0.000 | 0.589 |
+---------------------+--------------+------+------+------------+-------------+
* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.
* The fanout is the number of component pins not the individual BEL loads,
for example SLICE loads not FF loads.
Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)
Number of Timing Constraints that were not applied: 1
Asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.
----------------------------------------------------------------------------------------------------------
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
NET "Inst_clk32to16/clkin1" PERIOD = 31.2 | MINLOWPULSE | 15.250ns| 16.000ns| 0| 0
5 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
PERIOD analysis for net "Inst_clk32to16/c | SETUP | 20.249ns| 21.100ns| 0| 0
lkdv" derived from NET "Inst_clk32to16/c | HOLD | 0.320ns| | 0| 0
lkin1" PERIOD = 31.25 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
Derived Constraint Report
Review Timing Report for more details on the following derived constraints.
To create a Timing Report, run "trce -v 12 -fastpaths -o design_timing_report design.ncd design.pcf"
or "Run Timing Analysis" from Timing Analyzer (timingan).
Derived Constraints for Inst_clk32to16/clkin1
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
| | Period | Actual Period | Timing Errors | Paths Analyzed |
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|Inst_clk32to16/clkin1 | 31.250ns| 16.000ns| 10.550ns| 0| 0| 0| 391673054|
| Inst_clk32to16/clkdv | 62.500ns| 21.100ns| N/A| 0| 0| 391673054| 0|
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
All constraints were met.
Generating Pad Report.
All signals are completely routed.
Total REAL time to PAR completion: 38 secs
Total CPU time to PAR completion: 37 secs
Peak Memory Usage: 382 MB
Placer: Placement generated during map.
Routing: Completed - No errors found.
Timing: Completed - No errors found.
Number of error messages: 0
Number of warning messages: 0
Number of info messages: 0
Writing design to file top_avr_core_v8.ncd
PAR done!
Loading device for application Rf_Device from file '6slx9.nph' in environment
C:\Xilinx\14.7\ISE_DS\ISE\.
"top_avr_core_v8" is an NCD, version 3.2, device xc6slx9, package tqg144,
speed -2
Analysis completed Mon Sep 08 16:42:08 2014
--------------------------------------------------------------------------------
Generating Report ...
Number of warnings: 0
Total time: 17 secs
WARNING:PhysDesignRules:372 - Gated clock. Clock net GND_13_o_GND_13_o_OR_1256_o
is sourced by a combinatorial pin. This is not good design practice. Use the
CE pin to control the loading of data into the flip-flop.
INFO:WebTalk:4 -
D:/Dropbox/GadgetFactory/archive/AVR8/svn/trunk/usage_statistics_webtalk.html
WebTalk report has been successfully sent to Xilinx. For additional details
about this file, please refer to the WebTalk log file at
D:/Dropbox/GadgetFactory/archive/AVR8/svn/trunk/webtalk.log
WebTalk is complete.