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graphics_hw.tcl
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graphics_hw.tcl
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# TCL File Generated by Component Editor 15.0
# Thu Feb 15 01:44:56 PST 2018
# DO NOT MODIFY
#
# graphics_controller "graphics_controller" v1.0
# 2018.02.15.01:44:56
#
#
#
# request TCL package from ACDS 15.0
#
package require -exact qsys 15.0
#
# module graphics_controller
#
set_module_property DESCRIPTION ""
set_module_property NAME graphics_controller
set_module_property VERSION 1.0
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property AUTHOR ""
set_module_property DISPLAY_NAME graphics_controller
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property REPORT_TO_TALKBACK false
set_module_property ALLOW_GREYBOX_GENERATION false
set_module_property REPORT_HIERARCHY false
#
# file sets
#
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
set_fileset_property QUARTUS_SYNTH TOP_LEVEL signal_control
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
add_fileset_file signal_control.sv SYSTEM_VERILOG PATH signal_control.sv TOP_LEVEL_FILE
#
# parameters
#
add_parameter pixel_idle STD_LOGIC_VECTOR 0 ""
set_parameter_property pixel_idle DEFAULT_VALUE 0
set_parameter_property pixel_idle DISPLAY_NAME pixel_idle
set_parameter_property pixel_idle WIDTH 32
set_parameter_property pixel_idle TYPE STD_LOGIC_VECTOR
set_parameter_property pixel_idle ENABLED false
set_parameter_property pixel_idle UNITS None
set_parameter_property pixel_idle DESCRIPTION ""
set_parameter_property pixel_idle HDL_PARAMETER true
add_parameter pixel_write STD_LOGIC_VECTOR 1
set_parameter_property pixel_write DEFAULT_VALUE 1
set_parameter_property pixel_write DISPLAY_NAME pixel_write
set_parameter_property pixel_write WIDTH 2
set_parameter_property pixel_write TYPE STD_LOGIC_VECTOR
set_parameter_property pixel_write ENABLED false
set_parameter_property pixel_write UNITS None
set_parameter_property pixel_write ALLOWED_RANGES 0:3
set_parameter_property pixel_write HDL_PARAMETER true
add_parameter rec_idle STD_LOGIC_VECTOR 0
set_parameter_property rec_idle DEFAULT_VALUE 0
set_parameter_property rec_idle DISPLAY_NAME rec_idle
set_parameter_property rec_idle WIDTH 6
set_parameter_property rec_idle TYPE STD_LOGIC_VECTOR
set_parameter_property rec_idle ENABLED false
set_parameter_property rec_idle UNITS None
set_parameter_property rec_idle ALLOWED_RANGES 0:63
set_parameter_property rec_idle HDL_PARAMETER true
add_parameter rec_init STD_LOGIC_VECTOR 1
set_parameter_property rec_init DEFAULT_VALUE 1
set_parameter_property rec_init DISPLAY_NAME rec_init
set_parameter_property rec_init WIDTH 6
set_parameter_property rec_init TYPE STD_LOGIC_VECTOR
set_parameter_property rec_init ENABLED false
set_parameter_property rec_init UNITS None
set_parameter_property rec_init ALLOWED_RANGES 0:63
set_parameter_property rec_init HDL_PARAMETER true
add_parameter rec_write STD_LOGIC_VECTOR 34 ""
set_parameter_property rec_write DEFAULT_VALUE 34
set_parameter_property rec_write DISPLAY_NAME rec_write
set_parameter_property rec_write WIDTH 6
set_parameter_property rec_write TYPE STD_LOGIC_VECTOR
set_parameter_property rec_write ENABLED false
set_parameter_property rec_write UNITS None
set_parameter_property rec_write DESCRIPTION ""
set_parameter_property rec_write HDL_PARAMETER true
add_parameter rec_cmp_x STD_LOGIC_VECTOR 3
set_parameter_property rec_cmp_x DEFAULT_VALUE 3
set_parameter_property rec_cmp_x DISPLAY_NAME rec_cmp_x
set_parameter_property rec_cmp_x WIDTH 6
set_parameter_property rec_cmp_x TYPE STD_LOGIC_VECTOR
set_parameter_property rec_cmp_x ENABLED false
set_parameter_property rec_cmp_x UNITS None
set_parameter_property rec_cmp_x ALLOWED_RANGES 0:63
set_parameter_property rec_cmp_x HDL_PARAMETER true
add_parameter rec_inc_x STD_LOGIC_VECTOR 12
set_parameter_property rec_inc_x DEFAULT_VALUE 12
set_parameter_property rec_inc_x DISPLAY_NAME rec_inc_x
set_parameter_property rec_inc_x WIDTH 6
set_parameter_property rec_inc_x TYPE STD_LOGIC_VECTOR
set_parameter_property rec_inc_x ENABLED false
set_parameter_property rec_inc_x UNITS None
set_parameter_property rec_inc_x ALLOWED_RANGES 0:63
set_parameter_property rec_inc_x HDL_PARAMETER true
add_parameter rec_cmp_y STD_LOGIC_VECTOR 5
set_parameter_property rec_cmp_y DEFAULT_VALUE 5
set_parameter_property rec_cmp_y DISPLAY_NAME rec_cmp_y
set_parameter_property rec_cmp_y WIDTH 6
set_parameter_property rec_cmp_y TYPE STD_LOGIC_VECTOR
set_parameter_property rec_cmp_y ENABLED false
set_parameter_property rec_cmp_y UNITS None
set_parameter_property rec_cmp_y ALLOWED_RANGES 0:63
set_parameter_property rec_cmp_y HDL_PARAMETER true
add_parameter rec_inc_y STD_LOGIC_VECTOR 22
set_parameter_property rec_inc_y DEFAULT_VALUE 22
set_parameter_property rec_inc_y DISPLAY_NAME rec_inc_y
set_parameter_property rec_inc_y WIDTH 6
set_parameter_property rec_inc_y TYPE STD_LOGIC_VECTOR
set_parameter_property rec_inc_y ENABLED false
set_parameter_property rec_inc_y UNITS None
set_parameter_property rec_inc_y ALLOWED_RANGES 0:63
set_parameter_property rec_inc_y HDL_PARAMETER true
#
# display items
#
#
# connection point clock
#
add_interface clock clock end
set_interface_property clock clockRate 0
set_interface_property clock ENABLED true
set_interface_property clock EXPORT_OF ""
set_interface_property clock PORT_NAME_MAP ""
set_interface_property clock CMSIS_SVD_VARIABLES ""
set_interface_property clock SVD_ADDRESS_GROUP ""
add_interface_port clock clk clk Input 1
#
# connection point reset
#
add_interface reset reset end
set_interface_property reset associatedClock clock
set_interface_property reset synchronousEdges DEASSERT
set_interface_property reset ENABLED true
set_interface_property reset EXPORT_OF ""
set_interface_property reset PORT_NAME_MAP ""
set_interface_property reset CMSIS_SVD_VARIABLES ""
set_interface_property reset SVD_ADDRESS_GROUP ""
add_interface_port reset reset reset Input 1
#
# connection point mm
#
add_interface mm avalon end
set_interface_property mm addressUnits WORDS
set_interface_property mm associatedClock clock
set_interface_property mm associatedReset reset
set_interface_property mm bitsPerSymbol 8
set_interface_property mm burstOnBurstBoundariesOnly false
set_interface_property mm burstcountUnits WORDS
set_interface_property mm explicitAddressSpan 0
set_interface_property mm holdTime 0
set_interface_property mm linewrapBursts false
set_interface_property mm maximumPendingReadTransactions 0
set_interface_property mm maximumPendingWriteTransactions 0
set_interface_property mm readLatency 0
set_interface_property mm readWaitTime 1
set_interface_property mm setupTime 0
set_interface_property mm timingUnits Cycles
set_interface_property mm writeWaitTime 0
set_interface_property mm ENABLED true
set_interface_property mm EXPORT_OF ""
set_interface_property mm PORT_NAME_MAP ""
set_interface_property mm CMSIS_SVD_VARIABLES ""
set_interface_property mm SVD_ADDRESS_GROUP ""
add_interface_port mm mm_writedata writedata Input 32
add_interface_port mm mm_address address Input 24
add_interface_port mm mm_write write Input 1
add_interface_port mm mm_readdata readdata Output 32
add_interface_port mm mm_read read Input 1
set_interface_assignment mm embeddedsw.configuration.isFlash 0
set_interface_assignment mm embeddedsw.configuration.isMemoryDevice 0
set_interface_assignment mm embeddedsw.configuration.isNonVolatileStorage 0
set_interface_assignment mm embeddedsw.configuration.isPrintableDevice 0
#
# connection point avalon_master
#
add_interface avalon_master avalon start
set_interface_property avalon_master addressUnits SYMBOLS
set_interface_property avalon_master associatedClock clock
set_interface_property avalon_master associatedReset reset
set_interface_property avalon_master bitsPerSymbol 8
set_interface_property avalon_master burstOnBurstBoundariesOnly false
set_interface_property avalon_master burstcountUnits WORDS
set_interface_property avalon_master doStreamReads false
set_interface_property avalon_master doStreamWrites false
set_interface_property avalon_master holdTime 0
set_interface_property avalon_master linewrapBursts false
set_interface_property avalon_master maximumPendingReadTransactions 0
set_interface_property avalon_master maximumPendingWriteTransactions 0
set_interface_property avalon_master readLatency 0
set_interface_property avalon_master readWaitTime 1
set_interface_property avalon_master setupTime 0
set_interface_property avalon_master timingUnits Cycles
set_interface_property avalon_master writeWaitTime 0
set_interface_property avalon_master ENABLED true
set_interface_property avalon_master EXPORT_OF ""
set_interface_property avalon_master PORT_NAME_MAP ""
set_interface_property avalon_master CMSIS_SVD_VARIABLES ""
set_interface_property avalon_master SVD_ADDRESS_GROUP ""
add_interface_port avalon_master write_master write Output 1
add_interface_port avalon_master wait_request waitrequest Input 1
add_interface_port avalon_master byteenable byteenable Output 2
add_interface_port avalon_master address_out address Output 32
add_interface_port avalon_master data_out writedata Output 16
#
# connection point interrupt_sender
#
add_interface interrupt_sender interrupt end
set_interface_property interrupt_sender associatedAddressablePoint mm
set_interface_property interrupt_sender associatedClock clock
set_interface_property interrupt_sender associatedReset reset
set_interface_property interrupt_sender bridgedReceiverOffset ""
set_interface_property interrupt_sender bridgesToReceiver ""
set_interface_property interrupt_sender ENABLED true
set_interface_property interrupt_sender EXPORT_OF ""
set_interface_property interrupt_sender PORT_NAME_MAP ""
set_interface_property interrupt_sender CMSIS_SVD_VARIABLES ""
set_interface_property interrupt_sender SVD_ADDRESS_GROUP ""
add_interface_port interrupt_sender irq irq Output 1