From 4252f3009b169db250559d6a197b399375f89b27 Mon Sep 17 00:00:00 2001 From: Dominic Chen Date: Thu, 10 Sep 2020 01:02:13 -0400 Subject: [PATCH 01/10] [WebAssembly] Set unreachable as canonical to permit disassembly Currently, using llvm-objdump to disassemble a function containing unreachable will trigger an assertion while decoding the opcode, since both unreachable and debug_unreachable have the same encoding. To avoid this, set unreachable as the canonical decoding. Differential Revision: https://reviews.llvm.org/D87431 --- llvm/lib/Target/WebAssembly/WebAssemblyInstrControl.td | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyInstrControl.td b/llvm/lib/Target/WebAssembly/WebAssemblyInstrControl.td index 171dd9a67beb5c..63aeb1b4673795 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyInstrControl.td +++ b/llvm/lib/Target/WebAssembly/WebAssemblyInstrControl.td @@ -103,7 +103,7 @@ defm FALLTHROUGH_RETURN : I<(outs), (ins variable_ops), (outs), (ins), []>; } // isReturn = 1 -let isTrap = 1 in +let IsCanonical = 1, isTrap = 1 in defm UNREACHABLE : NRI<(outs), (ins), [(trap)], "unreachable", 0x00>; } // isTerminator = 1 From a39423084cbbeb59e81002e741190dccf08b5c82 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Federico=20Lebr=C3=B3n?= Date: Thu, 10 Sep 2020 19:00:49 +0000 Subject: [PATCH 02/10] Make struct dialects have the same field name as everything else, 'dialect'. Also make the behavior of getting a dialect more forgiving, in the case where there isn't a dialect associated with an attribute. Depends On D86807 Reviewed By: mehdi_amini Differential Revision: https://reviews.llvm.org/D86809 --- mlir/include/mlir/IR/OpBase.td | 4 ++-- mlir/lib/TableGen/Attribute.cpp | 9 +++++++-- 2 files changed, 9 insertions(+), 4 deletions(-) diff --git a/mlir/include/mlir/IR/OpBase.td b/mlir/include/mlir/IR/OpBase.td index b0f08e93666a31..29f139f25069bc 100644 --- a/mlir/include/mlir/IR/OpBase.td +++ b/mlir/include/mlir/IR/OpBase.td @@ -1443,7 +1443,7 @@ class StructFieldAttr { // Structured attribute that wraps a DictionaryAttr and provides both a // validation method and set of accessors for a fixed set of fields. This is // useful when representing data that would normally be in a structure. -class StructAttr attributes> : DictionaryAttrBase()">, "DictionaryAttr with field(s): " # @@ -1459,7 +1459,7 @@ class StructAttr fields = attributes; diff --git a/mlir/lib/TableGen/Attribute.cpp b/mlir/lib/TableGen/Attribute.cpp index e489174a38d917..f34d9c00b43880 100644 --- a/mlir/lib/TableGen/Attribute.cpp +++ b/mlir/lib/TableGen/Attribute.cpp @@ -126,7 +126,12 @@ StringRef Attribute::getDerivedCodeBody() const { } Dialect Attribute::getDialect() const { - return Dialect(def->getValueAsDef("dialect")); + const llvm::RecordVal *record = def->getValue("dialect"); + if (record && record->getValue()) { + if (DefInit *init = dyn_cast(record->getValue())) + return Dialect(init->getDef()); + } + return Dialect(nullptr); } ConstantAttr::ConstantAttr(const DefInit *init) : def(init->getDef()) { @@ -255,7 +260,7 @@ StringRef StructAttr::getStructClassName() const { } StringRef StructAttr::getCppNamespace() const { - Dialect dialect(def->getValueAsDef("structDialect")); + Dialect dialect(def->getValueAsDef("dialect")); return dialect.getCppNamespace(); } From d867be5de389f18cf3c1a61c8b9cbf8bfda8fe28 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Federico=20Lebr=C3=B3n?= Date: Thu, 10 Sep 2020 19:14:42 +0000 Subject: [PATCH 03/10] Allow Dialects to be initialized via nullptr. This allows Dialect to follow the MLIR style of nullable objects, and in fact is expected by `Dialect::operator bool() const` which already tests whether `def == nullptr`. This just wasn't a reachable situation, because the constructor was dereferencing the pointer unconditionally. Reviewed By: rriddle Differential Revision: https://reviews.llvm.org/D86807 --- mlir/lib/TableGen/Dialect.cpp | 2 ++ 1 file changed, 2 insertions(+) diff --git a/mlir/lib/TableGen/Dialect.cpp b/mlir/lib/TableGen/Dialect.cpp index 2b5f7e534ecc7b..c17180c204833f 100644 --- a/mlir/lib/TableGen/Dialect.cpp +++ b/mlir/lib/TableGen/Dialect.cpp @@ -16,6 +16,8 @@ using namespace mlir; using namespace mlir::tblgen; Dialect::Dialect(const llvm::Record *def) : def(def) { + if (def == nullptr) + return; for (StringRef dialect : def->getValueAsListOfStrings("dependentDialects")) dependentDialects.push_back(dialect); } From 5692497aef08ab4810f125669bc2f6aa79d9ec7e Mon Sep 17 00:00:00 2001 From: Nico Weber Date: Thu, 10 Sep 2020 15:10:12 -0400 Subject: [PATCH 04/10] [gn build] (semi-manually) port 009cd4e4910 --- .../llvm/lib/Target/PowerPC/BUILD.gn | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/llvm/utils/gn/secondary/llvm/lib/Target/PowerPC/BUILD.gn b/llvm/utils/gn/secondary/llvm/lib/Target/PowerPC/BUILD.gn index 3a452fc6e06019..9adb514705d442 100644 --- a/llvm/utils/gn/secondary/llvm/lib/Target/PowerPC/BUILD.gn +++ b/llvm/utils/gn/secondary/llvm/lib/Target/PowerPC/BUILD.gn @@ -18,17 +18,32 @@ tablegen("PPCGenFastISel") { td_file = "PPC.td" } +tablegen("PPCGenGlobalISel") { + visibility = [ ":LLVMPowerPCCodeGen" ] + args = [ "-gen-global-isel" ] + td_file = "PPC.td" +} + +tablegen("PPCGenRegisterBank") { + visibility = [ ":LLVMPowerPCCodeGen" ] + args = [ "-gen-register-bank" ] + td_file = "PPC.td" +} + static_library("LLVMPowerPCCodeGen") { deps = [ ":PPCGenCallingConv", ":PPCGenDAGISel", ":PPCGenFastISel", + ":PPCGenGlobalISel", + ":PPCGenRegisterBank", "MCTargetDesc", "TargetInfo", "//llvm/include/llvm/Config:llvm-config", "//llvm/lib/Analysis", "//llvm/lib/CodeGen", "//llvm/lib/CodeGen/AsmPrinter", + "//llvm/lib/CodeGen/GlobalISel", "//llvm/lib/CodeGen/SelectionDAG", "//llvm/lib/IR", "//llvm/lib/MC", @@ -38,6 +53,10 @@ static_library("LLVMPowerPCCodeGen") { ] include_dirs = [ "." ] sources = [ + "GISel/PPCCallLowering.cpp", + "GISel/PPCInstructionSelector.cpp", + "GISel/PPCLegalizerInfo.cpp", + "GISel/PPCRegisterBankInfo.cpp", "PPCAsmPrinter.cpp", "PPCBoolRetToInt.cpp", "PPCBranchCoalescing.cpp", From 2141705337989195b448e292955f08884babbcbd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Federico=20Lebr=C3=B3n?= Date: Thu, 10 Sep 2020 19:18:07 +0000 Subject: [PATCH 05/10] Fix operator!= for Dialects. Currently the global operator!=(bool, bool) is selected due to the implicit bool conversion operator. Since this is never the desired semantics, we give it a standard operator!= and make the bool conversion explicit. Depends On D86809 Reviewed By: rriddle Differential Revision: https://reviews.llvm.org/D86810 --- mlir/include/mlir/TableGen/Dialect.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/mlir/include/mlir/TableGen/Dialect.h b/mlir/include/mlir/TableGen/Dialect.h index 623d614d26d384..ee86a2504b3c92 100644 --- a/mlir/include/mlir/TableGen/Dialect.h +++ b/mlir/include/mlir/TableGen/Dialect.h @@ -67,11 +67,13 @@ class Dialect { // underlying record. bool operator==(const Dialect &other) const; + bool operator!=(const Dialect &other) const { return !(*this == other); } + // Compares two dialects by comparing the names of the dialects. bool operator<(const Dialect &other) const; // Returns whether the dialect is defined. - operator bool() const { return def != nullptr; } + explicit operator bool() const { return def != nullptr; } private: const llvm::Record *def; From 783e28a50839e045b72ec11946295fba104642fc Mon Sep 17 00:00:00 2001 From: Krzysztof Parzyszek Date: Thu, 10 Sep 2020 14:15:37 -0500 Subject: [PATCH 06/10] [Hexagon] Split pair-based masked memops --- .../Target/Hexagon/HexagonISelLoweringHVX.cpp | 2 ++ .../Hexagon/autohvx/isel-split-masked.ll | 32 +++++++++++++++++++ 2 files changed, 34 insertions(+) create mode 100644 llvm/test/CodeGen/Hexagon/autohvx/isel-split-masked.ll diff --git a/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp b/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp index 22561691f0e027..e63cb50a0fb84b 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp @@ -1985,6 +1985,8 @@ HexagonTargetLowering::LowerHvxOperation(SDValue Op, SelectionDAG &DAG) const { break; case ISD::LOAD: case ISD::STORE: + case ISD::MLOAD: + case ISD::MSTORE: return SplitHvxMemOp(Op, DAG); case ISD::CTPOP: case ISD::CTLZ: diff --git a/llvm/test/CodeGen/Hexagon/autohvx/isel-split-masked.ll b/llvm/test/CodeGen/Hexagon/autohvx/isel-split-masked.ll new file mode 100644 index 00000000000000..61bcbce6e64223 --- /dev/null +++ b/llvm/test/CodeGen/Hexagon/autohvx/isel-split-masked.ll @@ -0,0 +1,32 @@ +; RUN: llc -march=hexagon < %s | FileCheck %s + +; Check that this compiles successfully. +; CHECK: vmem + +target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048" +target triple = "hexagon" + +define void @f0() #0 { +b0: + %v0 = call <64 x i32> @llvm.masked.load.v64i32.p0v64i32(<64 x i32>* nonnull undef, i32 4, <64 x i1> , <64 x i32> undef) + %v1 = icmp sgt <64 x i32> %v0, zeroinitializer + %v2 = sext <64 x i1> %v1 to <64 x i32> + %v3 = add nsw <64 x i32> zeroinitializer, %v2 + %v4 = add nsw <64 x i32> %v3, zeroinitializer + %v5 = icmp sgt <64 x i32> %v4, zeroinitializer + %v6 = select <64 x i1> %v5, <64 x i32> %v4, <64 x i32> zeroinitializer + %v7 = select <64 x i1> zeroinitializer, <64 x i32> undef, <64 x i32> %v6 + %v8 = trunc <64 x i32> %v7 to <64 x i16> + call void @llvm.masked.store.v64i16.p0v64i16(<64 x i16> %v8, <64 x i16>* undef, i32 2, <64 x i1> ) + ret void +} + +; Function Attrs: argmemonly nounwind readonly willreturn +declare <64 x i32> @llvm.masked.load.v64i32.p0v64i32(<64 x i32>*, i32 immarg, <64 x i1>, <64 x i32>) #1 + +; Function Attrs: argmemonly nounwind willreturn +declare void @llvm.masked.store.v64i16.p0v64i16(<64 x i16>, <64 x i16>*, i32 immarg, <64 x i1>) #2 + +attributes #0 = { "target-features"="+hvx-length128b,+hvxv67,+v67,-long-calls" } +attributes #1 = { argmemonly nounwind readonly willreturn } +attributes #2 = { argmemonly nounwind willreturn } From 7ddfd9b3ebfd3f3db7c6c2e8c72308ff3a3426f2 Mon Sep 17 00:00:00 2001 From: Christopher Tetreault Date: Thu, 10 Sep 2020 11:29:16 -0700 Subject: [PATCH 07/10] [SVE] Bail from VectorUtils heuristics for scalable vectors Bail from maskIsAllZeroOrUndef and maskIsAllOneOrUndef prior to iterating over the number of elements for scalable vectors. Assert that the mask type is not scalable in possiblyDemandedEltsInMask . Assert that the types are correct in all three functions. Reviewed By: efriedma Differential Revision: https://reviews.llvm.org/D87424 --- llvm/include/llvm/Analysis/VectorUtils.h | 14 ++++++------- llvm/lib/Analysis/VectorUtils.cpp | 21 +++++++++++++++++++ .../InstCombine/InstCombineCalls.cpp | 18 ++++++++++------ .../AArch64/VectorUtils_heuristics.ll | 21 +++++++++++++++++++ 4 files changed, 61 insertions(+), 13 deletions(-) create mode 100644 llvm/test/Transforms/InstCombine/AArch64/VectorUtils_heuristics.ll diff --git a/llvm/include/llvm/Analysis/VectorUtils.h b/llvm/include/llvm/Analysis/VectorUtils.h index 8498335bf78e65..c570bf25e92b5b 100644 --- a/llvm/include/llvm/Analysis/VectorUtils.h +++ b/llvm/include/llvm/Analysis/VectorUtils.h @@ -544,20 +544,20 @@ createSequentialMask(unsigned Start, unsigned NumInts, unsigned NumUndefs); /// elements, it will be padded with undefs. Value *concatenateVectors(IRBuilderBase &Builder, ArrayRef Vecs); -/// Given a mask vector of the form , Return true if all of the -/// elements of this predicate mask are false or undef. That is, return true -/// if all lanes can be assumed inactive. +/// Given a mask vector of i1, Return true if all of the elements of this +/// predicate mask are known to be false or undef. That is, return true if all +/// lanes can be assumed inactive. bool maskIsAllZeroOrUndef(Value *Mask); -/// Given a mask vector of the form , Return true if all of the -/// elements of this predicate mask are true or undef. That is, return true -/// if all lanes can be assumed active. +/// Given a mask vector of i1, Return true if all of the elements of this +/// predicate mask are known to be true or undef. That is, return true if all +/// lanes can be assumed active. bool maskIsAllOneOrUndef(Value *Mask); /// Given a mask vector of the form , return an APInt (of bitwidth Y) /// for each lane which may be active. APInt possiblyDemandedEltsInMask(Value *Mask); - + /// The group of interleaved loads/stores sharing the same stride and /// close to each other. /// diff --git a/llvm/lib/Analysis/VectorUtils.cpp b/llvm/lib/Analysis/VectorUtils.cpp index e241300dd2e7c1..0b10983442e200 100644 --- a/llvm/lib/Analysis/VectorUtils.cpp +++ b/llvm/lib/Analysis/VectorUtils.cpp @@ -863,11 +863,19 @@ Value *llvm::concatenateVectors(IRBuilderBase &Builder, } bool llvm::maskIsAllZeroOrUndef(Value *Mask) { + assert(isa(Mask->getType()) && + isa(Mask->getType()->getScalarType()) && + cast(Mask->getType()->getScalarType())->getBitWidth() == + 1 && + "Mask must be a vector of i1"); + auto *ConstMask = dyn_cast(Mask); if (!ConstMask) return false; if (ConstMask->isNullValue() || isa(ConstMask)) return true; + if (isa(ConstMask->getType())) + return false; for (unsigned I = 0, E = cast(ConstMask->getType())->getNumElements(); @@ -882,11 +890,19 @@ bool llvm::maskIsAllZeroOrUndef(Value *Mask) { bool llvm::maskIsAllOneOrUndef(Value *Mask) { + assert(isa(Mask->getType()) && + isa(Mask->getType()->getScalarType()) && + cast(Mask->getType()->getScalarType())->getBitWidth() == + 1 && + "Mask must be a vector of i1"); + auto *ConstMask = dyn_cast(Mask); if (!ConstMask) return false; if (ConstMask->isAllOnesValue() || isa(ConstMask)) return true; + if (isa(ConstMask->getType())) + return false; for (unsigned I = 0, E = cast(ConstMask->getType())->getNumElements(); @@ -902,6 +918,11 @@ bool llvm::maskIsAllOneOrUndef(Value *Mask) { /// TODO: This is a lot like known bits, but for /// vectors. Is there something we can common this with? APInt llvm::possiblyDemandedEltsInMask(Value *Mask) { + assert(isa(Mask->getType()) && + isa(Mask->getType()->getScalarType()) && + cast(Mask->getType()->getScalarType())->getBitWidth() == + 1 && + "Mask must be a fixed width vector of i1"); const unsigned VWidth = cast(Mask->getType())->getNumElements(); diff --git a/llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp b/llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp index 11c2367d1608e9..334e4e3e74abb1 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp @@ -319,11 +319,14 @@ Instruction *InstCombinerImpl::simplifyMaskedStore(IntrinsicInst &II) { return new StoreInst(II.getArgOperand(0), StorePtr, false, Alignment); } + if (isa(ConstMask->getType())) + return nullptr; + // Use masked off lanes to simplify operands via SimplifyDemandedVectorElts APInt DemandedElts = possiblyDemandedEltsInMask(ConstMask); APInt UndefElts(DemandedElts.getBitWidth(), 0); - if (Value *V = SimplifyDemandedVectorElts(II.getOperand(0), - DemandedElts, UndefElts)) + if (Value *V = + SimplifyDemandedVectorElts(II.getOperand(0), DemandedElts, UndefElts)) return replaceOperand(II, 0, V); return nullptr; @@ -355,14 +358,17 @@ Instruction *InstCombinerImpl::simplifyMaskedScatter(IntrinsicInst &II) { if (ConstMask->isNullValue()) return eraseInstFromFunction(II); + if (isa(ConstMask->getType())) + return nullptr; + // Use masked off lanes to simplify operands via SimplifyDemandedVectorElts APInt DemandedElts = possiblyDemandedEltsInMask(ConstMask); APInt UndefElts(DemandedElts.getBitWidth(), 0); - if (Value *V = SimplifyDemandedVectorElts(II.getOperand(0), - DemandedElts, UndefElts)) + if (Value *V = + SimplifyDemandedVectorElts(II.getOperand(0), DemandedElts, UndefElts)) return replaceOperand(II, 0, V); - if (Value *V = SimplifyDemandedVectorElts(II.getOperand(1), - DemandedElts, UndefElts)) + if (Value *V = + SimplifyDemandedVectorElts(II.getOperand(1), DemandedElts, UndefElts)) return replaceOperand(II, 1, V); return nullptr; diff --git a/llvm/test/Transforms/InstCombine/AArch64/VectorUtils_heuristics.ll b/llvm/test/Transforms/InstCombine/AArch64/VectorUtils_heuristics.ll new file mode 100644 index 00000000000000..b3a166d10b6961 --- /dev/null +++ b/llvm/test/Transforms/InstCombine/AArch64/VectorUtils_heuristics.ll @@ -0,0 +1,21 @@ +; RUN: opt -S -instcombine < %s | FileCheck %s + +target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" +target triple = "aarch64-unknown-linux-gnu" + +; This test checks that instcombine does not crash while invoking +; maskIsAllOneOrUndef, maskIsAllZeroOrUndef, or possiblyDemandedEltsInMask. + +; CHECK-LABEL: novel_algorithm +; CHECK: unreachable +define void @novel_algorithm() { +entry: + %a = call @llvm.masked.load.nxv16i8.p0nxv16i8(* undef, i32 1, shufflevector ( insertelement ( undef, i1 true, i32 0), undef, zeroinitializer), undef) + %b = add undef, %a + call void @llvm.masked.store.nxv16i8.p0nxv16i8( %b, * undef, i32 1, shufflevector ( insertelement ( undef, i1 true, i32 0), undef, zeroinitializer)) + unreachable +} + +declare @llvm.masked.load.nxv16i8.p0nxv16i8(*, i32 immarg, , ) + +declare void @llvm.masked.store.nxv16i8.p0nxv16i8(, *, i32 immarg, ) From b1b9806370196234a62304d308a9f8873759ec28 Mon Sep 17 00:00:00 2001 From: Anna Thomas Date: Thu, 10 Sep 2020 15:30:42 -0400 Subject: [PATCH 08/10] [ImplicitNullChecks] NFC: Remove unused PointerReg arg in dep analysis The PointerReg arg was passed into the dependence function for an assertion which no longer exists. So, this patch updates the dependence functions to avoid the PointerReg in the signature. Tests-Run: make check --- llvm/lib/CodeGen/ImplicitNullChecks.cpp | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-) diff --git a/llvm/lib/CodeGen/ImplicitNullChecks.cpp b/llvm/lib/CodeGen/ImplicitNullChecks.cpp index 8e1f9c36c7fecd..9030f32268377e 100644 --- a/llvm/lib/CodeGen/ImplicitNullChecks.cpp +++ b/llvm/lib/CodeGen/ImplicitNullChecks.cpp @@ -204,13 +204,12 @@ class ImplicitNullChecks : public MachineFunctionPass { /// if it was hoisted to the NullCheck block. This is used by caller /// canHoistInst to decide if DependenceMI can be hoisted safely. bool canDependenceHoistingClobberLiveIns(MachineInstr *DependenceMI, - MachineBasicBlock *NullSucc, - unsigned PointerReg); + MachineBasicBlock *NullSucc); /// Return true if \p FaultingMI can be hoisted from after the /// instructions in \p InstsSeenSoFar to before them. Set \p Dependence to a /// non-null value if we also need to (and legally can) hoist a depedency. - bool canHoistInst(MachineInstr *FaultingMI, unsigned PointerReg, + bool canHoistInst(MachineInstr *FaultingMI, ArrayRef InstsSeenSoFar, MachineBasicBlock *NullSucc, MachineInstr *&Dependence); @@ -409,8 +408,7 @@ ImplicitNullChecks::isSuitableMemoryOp(const MachineInstr &MI, } bool ImplicitNullChecks::canDependenceHoistingClobberLiveIns( - MachineInstr *DependenceMI, MachineBasicBlock *NullSucc, - unsigned PointerReg) { + MachineInstr *DependenceMI, MachineBasicBlock *NullSucc) { for (auto &DependenceMO : DependenceMI->operands()) { if (!(DependenceMO.isReg() && DependenceMO.getReg())) continue; @@ -442,7 +440,6 @@ bool ImplicitNullChecks::canDependenceHoistingClobberLiveIns( } bool ImplicitNullChecks::canHoistInst(MachineInstr *FaultingMI, - unsigned PointerReg, ArrayRef InstsSeenSoFar, MachineBasicBlock *NullSucc, MachineInstr *&Dependence) { @@ -467,7 +464,7 @@ bool ImplicitNullChecks::canHoistInst(MachineInstr *FaultingMI, if (DependenceMI->mayLoadOrStore()) return false; - if (canDependenceHoistingClobberLiveIns(DependenceMI, NullSucc, PointerReg)) + if (canDependenceHoistingClobberLiveIns(DependenceMI, NullSucc)) return false; auto DepDepResult = @@ -616,7 +613,7 @@ bool ImplicitNullChecks::analyzeBlockForNullChecks( if (SR == SR_Impossible) return false; if (SR == SR_Suitable && - canHoistInst(&MI, PointerReg, InstsSeenSoFar, NullSucc, Dependence)) { + canHoistInst(&MI, InstsSeenSoFar, NullSucc, Dependence)) { NullCheckList.emplace_back(&MI, MBP.ConditionDef, &MBB, NotNullSucc, NullSucc, Dependence); return true; From 878cb5170de9bf03798a40185952bdf50fe4a15e Mon Sep 17 00:00:00 2001 From: Siva Chandra Reddy Date: Thu, 10 Sep 2020 11:45:21 -0700 Subject: [PATCH 09/10] [libc][NFC][obvious] Remove a redudant dep of strcmp implementation. --- libc/src/string/CMakeLists.txt | 2 -- 1 file changed, 2 deletions(-) diff --git a/libc/src/string/CMakeLists.txt b/libc/src/string/CMakeLists.txt index 8efe8c89e9e7fd..a347f2bf52675c 100644 --- a/libc/src/string/CMakeLists.txt +++ b/libc/src/string/CMakeLists.txt @@ -48,8 +48,6 @@ add_entrypoint_object( strcmp.cpp HDRS strcmp.h - DEPENDS - libc.include.string ) add_entrypoint_object( From 4934127e627d7c58342be15bc9230a7cbdf5273f Mon Sep 17 00:00:00 2001 From: "Yaxun (Sam) Liu" Date: Thu, 10 Sep 2020 11:51:31 -0400 Subject: [PATCH 10/10] Diable sanitizer options for amdgpu Currently AMDGPU does not support sanitizer. Disable sanitizer options for now until they are supported. Differential Revision: https://reviews.llvm.org/D87461 --- clang/lib/Driver/SanitizerArgs.cpp | 8 ++++---- clang/test/Driver/hip-sanitize-options.hip | 9 +++++++++ 2 files changed, 13 insertions(+), 4 deletions(-) create mode 100644 clang/test/Driver/hip-sanitize-options.hip diff --git a/clang/lib/Driver/SanitizerArgs.cpp b/clang/lib/Driver/SanitizerArgs.cpp index 0f51443010ca44..0cb1e7b5282b61 100644 --- a/clang/lib/Driver/SanitizerArgs.cpp +++ b/clang/lib/Driver/SanitizerArgs.cpp @@ -929,10 +929,10 @@ static bool hasTargetFeatureMTE(const llvm::opt::ArgStringList &CmdArgs) { void SanitizerArgs::addArgs(const ToolChain &TC, const llvm::opt::ArgList &Args, llvm::opt::ArgStringList &CmdArgs, types::ID InputType) const { - // NVPTX doesn't currently support sanitizers. Bailing out here means that - // e.g. -fsanitize=address applies only to host code, which is what we want - // for now. - if (TC.getTriple().isNVPTX()) + // NVPTX/AMDGPU doesn't currently support sanitizers. Bailing out here means + // that e.g. -fsanitize=address applies only to host code, which is what we + // want for now. + if (TC.getTriple().isNVPTX() || TC.getTriple().isAMDGPU()) return; // Translate available CoverageFeatures to corresponding clang-cc1 flags. diff --git a/clang/test/Driver/hip-sanitize-options.hip b/clang/test/Driver/hip-sanitize-options.hip new file mode 100644 index 00000000000000..908e02136cada3 --- /dev/null +++ b/clang/test/Driver/hip-sanitize-options.hip @@ -0,0 +1,9 @@ +// REQUIRES: clang-driver, x86-registered-target, amdgpu-registered-target + +// RUN: %clang -### -target x86_64-unknown-linux-gnu --offload-arch=gfx906 \ +// RUN: -fsanitize=address \ +// RUN: -nogpuinc -nogpulib \ +// RUN: %s 2>&1 | FileCheck %s + +// CHECK-NOT: {{"[^"]*clang[^"]*".* "-fcuda-is-device".* "-fsanitize=address"}} +// CHECK: {{"[^"]*clang[^"]*".* "-triple" "x86_64-unknown-linux-gnu".* "-fsanitize=address"}}