From b7ff218f1c0443aca4cd621ff01e44428b88e85f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Lu=C3=ADs=20Marques?= Date: Sat, 17 Oct 2020 16:52:29 +0100 Subject: [PATCH 1/3] [RISCV][ASAN] Fix passing XFAIL tests These tests pass for RV64 Linux, but they are marked as XFAIL. This patch fixes that. Differential Revision: https://reviews.llvm.org/D89299 --- compiler-rt/test/asan/TestCases/Linux/odr-violation.cpp | 2 +- compiler-rt/test/asan/TestCases/Linux/odr-vtable.cpp | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/compiler-rt/test/asan/TestCases/Linux/odr-violation.cpp b/compiler-rt/test/asan/TestCases/Linux/odr-violation.cpp index a14b59b67f1145..4861220b11bbb9 100644 --- a/compiler-rt/test/asan/TestCases/Linux/odr-violation.cpp +++ b/compiler-rt/test/asan/TestCases/Linux/odr-violation.cpp @@ -1,7 +1,7 @@ // FIXME: https://code.google.com/p/address-sanitizer/issues/detail?id=316 // XFAIL: android // Fails with debug checks: https://bugs.llvm.org/show_bug.cgi?id=46862 -// XFAIL: !compiler-rt-optimized +// XFAIL: !compiler-rt-optimized && !riscv64 // // We use fast_unwind_on_malloc=0 to have full unwinding even w/o frame // pointers. This setting is not on by default because it's too expensive. diff --git a/compiler-rt/test/asan/TestCases/Linux/odr-vtable.cpp b/compiler-rt/test/asan/TestCases/Linux/odr-vtable.cpp index eb0805784df1a2..024c488acda5ae 100644 --- a/compiler-rt/test/asan/TestCases/Linux/odr-vtable.cpp +++ b/compiler-rt/test/asan/TestCases/Linux/odr-vtable.cpp @@ -1,5 +1,5 @@ // Fails with debug checks: https://bugs.llvm.org/show_bug.cgi?id=46862 -// XFAIL: !compiler-rt-optimized +// XFAIL: !compiler-rt-optimized && !riscv64 // RUN: %clangxx_asan -fno-rtti -DBUILD_SO1 -fPIC -shared %s -o %dynamiclib1 // RUN: %clangxx_asan -fno-rtti -DBUILD_SO2 -fPIC -shared %s -o %dynamiclib2 From 57d3e9cd9bca9d71699abc9fb81862e2d80533dd Mon Sep 17 00:00:00 2001 From: Mircea Trofin Date: Sat, 17 Oct 2020 09:06:24 -0700 Subject: [PATCH 2/3] [NFC][ML] Avoid source of some signed/unsigned warnings in TFUtilsTest --- llvm/unittests/Analysis/TFUtilsTest.cpp | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/llvm/unittests/Analysis/TFUtilsTest.cpp b/llvm/unittests/Analysis/TFUtilsTest.cpp index 3b62e33999d9cf..d2ad977545adc7 100644 --- a/llvm/unittests/Analysis/TFUtilsTest.cpp +++ b/llvm/unittests/Analysis/TFUtilsTest.cpp @@ -57,7 +57,7 @@ TEST(TFUtilsTest, LoadAndExecuteTest) { auto ER = Evaluator.evaluate(); EXPECT_TRUE(ER.hasValue()); float Ret = *ER->getTensorValue(0); - EXPECT_EQ(static_cast(Ret), 80); + EXPECT_EQ(static_cast(Ret), 80); EXPECT_EQ(ER->getUntypedTensorValue(0), reinterpret_cast(ER->getTensorValue(0))); } @@ -72,7 +72,7 @@ TEST(TFUtilsTest, LoadAndExecuteTest) { auto ER = Evaluator.evaluate(); EXPECT_TRUE(ER.hasValue()); float Ret = *ER->getTensorValue(0); - EXPECT_EQ(static_cast(Ret), 80); + EXPECT_EQ(static_cast(Ret), 80); } } @@ -135,10 +135,10 @@ TEST(TFUtilsTest, TensorSpecSizesAndTypes) { auto Spec3DLarge = TensorSpec::createSpec("Hi3", {2, 4, 10}); EXPECT_TRUE(Spec1D.isElementType()); EXPECT_FALSE(Spec3DLarge.isElementType()); - EXPECT_EQ(Spec1D.getElementCount(), 1); - EXPECT_EQ(Spec2D.getElementCount(), 1); - EXPECT_EQ(Spec1DLarge.getElementCount(), 10); - EXPECT_EQ(Spec3DLarge.getElementCount(), 80); + EXPECT_EQ(Spec1D.getElementCount(), 1U); + EXPECT_EQ(Spec2D.getElementCount(), 1U); + EXPECT_EQ(Spec1DLarge.getElementCount(), 10U); + EXPECT_EQ(Spec3DLarge.getElementCount(), 80U); EXPECT_EQ(Spec3DLarge.getElementByteSize(), sizeof(float)); EXPECT_EQ(Spec1D.getElementByteSize(), sizeof(int16_t)); } From 53e92b4c0efc95c8d9471f44829c86b6c9240ef4 Mon Sep 17 00:00:00 2001 From: Sanjay Patel Date: Sat, 17 Oct 2020 12:19:04 -0400 Subject: [PATCH 3/3] [InstCombine] (~A & B) ^ A -> A | B Differential Revision: https://reviews.llvm.org/D86395 --- .../InstCombine/InstCombineAndOrXor.cpp | 4 ++++ llvm/test/Transforms/InstCombine/xor.ll | 16 ++++------------ 2 files changed, 8 insertions(+), 12 deletions(-) diff --git a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp index 1b83de2c3150ad..b9b73a46189f40 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp @@ -3335,6 +3335,10 @@ Instruction *InstCombinerImpl::visitXor(BinaryOperator &I) { match(Op1, m_Not(m_Specific(A)))) return BinaryOperator::CreateNot(Builder.CreateAnd(A, B)); + // (~A & B) ^ A --> A | B -- There are 4 commuted variants. + if (match(&I, m_c_Xor(m_c_And(m_Not(m_Value(A)), m_Value(B)), m_Deferred(A)))) + return BinaryOperator::CreateOr(A, B); + // (A | B) ^ (A | C) --> (B ^ C) & ~A -- There are 4 commuted variants. // TODO: Loosen one-use restriction if common operand is a constant. Value *D; diff --git a/llvm/test/Transforms/InstCombine/xor.ll b/llvm/test/Transforms/InstCombine/xor.ll index c37983829fbba3..569ca46145ebc9 100644 --- a/llvm/test/Transforms/InstCombine/xor.ll +++ b/llvm/test/Transforms/InstCombine/xor.ll @@ -1176,9 +1176,7 @@ define i8 @not_ashr_wrong_const(i8 %x) { define <2 x i32> @xor_andn_commute1(<2 x i32> %a, <2 x i32> %b) { ; CHECK-LABEL: @xor_andn_commute1( -; CHECK-NEXT: [[NOTA:%.*]] = xor <2 x i32> [[A:%.*]], -; CHECK-NEXT: [[R:%.*]] = and <2 x i32> [[NOTA]], [[B:%.*]] -; CHECK-NEXT: [[Z:%.*]] = xor <2 x i32> [[R]], [[A]] +; CHECK-NEXT: [[Z:%.*]] = or <2 x i32> [[A:%.*]], [[B:%.*]] ; CHECK-NEXT: ret <2 x i32> [[Z]] ; %nota = xor <2 x i32> %a, @@ -1192,9 +1190,7 @@ define <2 x i32> @xor_andn_commute1(<2 x i32> %a, <2 x i32> %b) { define i33 @xor_andn_commute2(i33 %a, i33 %pb) { ; CHECK-LABEL: @xor_andn_commute2( ; CHECK-NEXT: [[B:%.*]] = udiv i33 42, [[PB:%.*]] -; CHECK-NEXT: [[NOTA:%.*]] = xor i33 [[A:%.*]], -1 -; CHECK-NEXT: [[R:%.*]] = and i33 [[B]], [[NOTA]] -; CHECK-NEXT: [[Z:%.*]] = xor i33 [[R]], [[A]] +; CHECK-NEXT: [[Z:%.*]] = or i33 [[B]], [[A:%.*]] ; CHECK-NEXT: ret i33 [[Z]] ; %b = udiv i33 42, %pb ; thwart complexity-based canonicalization @@ -1209,9 +1205,7 @@ define i33 @xor_andn_commute2(i33 %a, i33 %pb) { define i32 @xor_andn_commute3(i32 %pa, i32 %b) { ; CHECK-LABEL: @xor_andn_commute3( ; CHECK-NEXT: [[A:%.*]] = udiv i32 42, [[PA:%.*]] -; CHECK-NEXT: [[NOTA:%.*]] = xor i32 [[A]], -1 -; CHECK-NEXT: [[R:%.*]] = and i32 [[NOTA]], [[B:%.*]] -; CHECK-NEXT: [[Z:%.*]] = xor i32 [[A]], [[R]] +; CHECK-NEXT: [[Z:%.*]] = or i32 [[A]], [[B:%.*]] ; CHECK-NEXT: ret i32 [[Z]] ; %a = udiv i32 42, %pa ; thwart complexity-based canonicalization @@ -1227,9 +1221,7 @@ define i32 @xor_andn_commute4(i32 %pa, i32 %pb) { ; CHECK-LABEL: @xor_andn_commute4( ; CHECK-NEXT: [[A:%.*]] = udiv i32 42, [[PA:%.*]] ; CHECK-NEXT: [[B:%.*]] = udiv i32 42, [[PB:%.*]] -; CHECK-NEXT: [[NOTA:%.*]] = xor i32 [[A]], -1 -; CHECK-NEXT: [[R:%.*]] = and i32 [[B]], [[NOTA]] -; CHECK-NEXT: [[Z:%.*]] = xor i32 [[A]], [[R]] +; CHECK-NEXT: [[Z:%.*]] = or i32 [[A]], [[B]] ; CHECK-NEXT: ret i32 [[Z]] ; %a = udiv i32 42, %pa ; thwart complexity-based canonicalization