From 9fc814ed59669d8f1d06cde5714c17fac652f2a1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?D=C3=A1vid=20Bolvansk=C3=BD?= Date: Sat, 16 Jan 2021 15:04:54 +0100 Subject: [PATCH 1/5] [Tests] Added tests for new instcombine or simplification; NFC --- llvm/test/Transforms/InstCombine/or.ll | 109 +++++++++++++++++++++++++ 1 file changed, 109 insertions(+) diff --git a/llvm/test/Transforms/InstCombine/or.ll b/llvm/test/Transforms/InstCombine/or.ll index ff624452656326..0fc75fe082f82c 100644 --- a/llvm/test/Transforms/InstCombine/or.ll +++ b/llvm/test/Transforms/InstCombine/or.ll @@ -1370,3 +1370,112 @@ define i32 @test5_use3(i32 %x, i32 %y) { ret i32 %or1 } +define i32 @test6(i32 %A, i32 %B) { +; CHECK-LABEL: @test6( +; CHECK-NEXT: [[I:%.*]] = xor i32 [[B:%.*]], -1 +; CHECK-NEXT: [[I2:%.*]] = and i32 [[I]], [[A:%.*]] +; CHECK-NEXT: [[I3:%.*]] = or i32 [[B]], [[A]] +; CHECK-NEXT: [[I4:%.*]] = xor i32 [[I3]], -1 +; CHECK-NEXT: [[I5:%.*]] = or i32 [[I2]], [[I4]] +; CHECK-NEXT: ret i32 [[I5]] +; + %i = xor i32 %B, -1 + %i2 = and i32 %i, %A + %i3 = or i32 %B, %A + %i4 = xor i32 %i3, -1 + %i5 = or i32 %i2, %i4 + ret i32 %i5 +} + +define i32 @test7(i32 %A, i32 %B) { +; CHECK-LABEL: @test7( +; CHECK-NEXT: [[I:%.*]] = xor i32 [[A:%.*]], -1 +; CHECK-NEXT: [[I2:%.*]] = and i32 [[I]], [[B:%.*]] +; CHECK-NEXT: [[I3:%.*]] = or i32 [[B]], [[A]] +; CHECK-NEXT: [[I4:%.*]] = xor i32 [[I3]], -1 +; CHECK-NEXT: [[I5:%.*]] = or i32 [[I2]], [[I4]] +; CHECK-NEXT: ret i32 [[I5]] +; + %i = xor i32 %A, -1 + %i2 = and i32 %i, %B + %i3 = or i32 %B, %A + %i4 = xor i32 %i3, -1 + %i5 = or i32 %i2, %i4 + ret i32 %i5 +} + +define <4 x i32> @test8_vec(<4 x i32> %A, <4 x i32> %B) { +; CHECK-LABEL: @test8_vec( +; CHECK-NEXT: [[I:%.*]] = xor <4 x i32> [[A:%.*]], +; CHECK-NEXT: [[I2:%.*]] = and <4 x i32> [[I]], [[B:%.*]] +; CHECK-NEXT: [[I3:%.*]] = or <4 x i32> [[B]], [[A]] +; CHECK-NEXT: [[I4:%.*]] = xor <4 x i32> [[I3]], +; CHECK-NEXT: [[I5:%.*]] = or <4 x i32> [[I2]], [[I4]] +; CHECK-NEXT: ret <4 x i32> [[I5]] +; + %i = xor <4 x i32> %A, + %i2 = and <4 x i32> %i, %B + %i3 = or <4 x i32> %B, %A + %i4 = xor <4 x i32> %i3, + %i5 = or <4 x i32> %i2, %i4 + ret <4 x i32> %i5 +} + +define i32 @test9_use(i32 %A, i32 %B) { +; CHECK-LABEL: @test9_use( +; CHECK-NEXT: [[I:%.*]] = xor i32 [[A:%.*]], -1 +; CHECK-NEXT: [[I2:%.*]] = and i32 [[I]], [[B:%.*]] +; CHECK-NEXT: tail call void @use(i32 [[I2]]) +; CHECK-NEXT: [[I3:%.*]] = or i32 [[B]], [[A]] +; CHECK-NEXT: [[I4:%.*]] = xor i32 [[I3]], -1 +; CHECK-NEXT: [[I5:%.*]] = or i32 [[I2]], [[I4]] +; CHECK-NEXT: ret i32 [[I5]] +; + %i = xor i32 %A, -1 + %i2 = and i32 %i, %B + tail call void @use(i32 %i2) + %i3 = or i32 %B, %A + %i4 = xor i32 %i3, -1 + %i5 = or i32 %i2, %i4 + ret i32 %i5 +} + +define i32 @test9_use2(i32 %A, i32 %B) { +; CHECK-LABEL: @test9_use2( +; CHECK-NEXT: [[I:%.*]] = or i32 [[B:%.*]], [[A:%.*]] +; CHECK-NEXT: [[I2:%.*]] = xor i32 [[I]], -1 +; CHECK-NEXT: tail call void @use(i32 [[I2]]) +; CHECK-NEXT: [[I3:%.*]] = xor i32 [[A]], -1 +; CHECK-NEXT: [[I4:%.*]] = and i32 [[I3]], [[B]] +; CHECK-NEXT: [[I5:%.*]] = or i32 [[I4]], [[I2]] +; CHECK-NEXT: ret i32 [[I5]] +; + %i = or i32 %B, %A + %i2 = xor i32 %i, -1 + tail call void @use(i32 %i2) + %i3 = xor i32 %A, -1 + %i4 = and i32 %i3, %B + %i5 = or i32 %i4, %i2 + ret i32 %i5 +} + +define i32 @test9_use3(i32 %A, i32 %B) { +; CHECK-LABEL: @test9_use3( +; CHECK-NEXT: [[I:%.*]] = or i32 [[B:%.*]], [[A:%.*]] +; CHECK-NEXT: [[I2:%.*]] = xor i32 [[I]], -1 +; CHECK-NEXT: tail call void @use(i32 [[I2]]) +; CHECK-NEXT: [[I3:%.*]] = xor i32 [[A]], -1 +; CHECK-NEXT: [[I4:%.*]] = and i32 [[I3]], [[B]] +; CHECK-NEXT: tail call void @use(i32 [[I4]]) +; CHECK-NEXT: [[I5:%.*]] = or i32 [[I4]], [[I2]] +; CHECK-NEXT: ret i32 [[I5]] +; + %i = or i32 %B, %A + %i2 = xor i32 %i, -1 + tail call void @use(i32 %i2) + %i3 = xor i32 %A, -1 + %i4 = and i32 %i3, %B + tail call void @use(i32 %i4) + %i5 = or i32 %i4, %i2 + ret i32 %i5 +} From a4e2a5145a29af678139f33e94ab3df0fc973e59 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?D=C3=A1vid=20Bolvansk=C3=BD?= Date: Sat, 16 Jan 2021 15:43:07 +0100 Subject: [PATCH 2/5] [InstSimplify] Add (~A & B) | ~(A | B) --> ~A --- llvm/lib/Analysis/InstructionSimplify.cpp | 6 ++ llvm/test/Transforms/InstSimplify/or.ll | 94 +++++++++++++++++++++++ 2 files changed, 100 insertions(+) diff --git a/llvm/lib/Analysis/InstructionSimplify.cpp b/llvm/lib/Analysis/InstructionSimplify.cpp index 2ae4228495e349..6266e922f8c9c4 100644 --- a/llvm/lib/Analysis/InstructionSimplify.cpp +++ b/llvm/lib/Analysis/InstructionSimplify.cpp @@ -2262,6 +2262,12 @@ static Value *SimplifyOrInst(Value *Op0, Value *Op1, const SimplifyQuery &Q, match(Op0, m_c_Xor(m_Not(m_Specific(A)), m_Specific(B))))) return Op0; + // (~A & B) | ~(A | B) --> ~A + // (~A & B) | ~(B | A) --> ~A + if (match(Op0, m_And(m_Not(m_Value(A)), m_Value(B))) && + match(Op1, m_Not(m_c_Or(m_Specific(A), m_Specific(B))))) + return cast(Op0)->getOperand(0); + if (Value *V = simplifyAndOrOfCmps(Q, Op0, Op1, false)) return V; diff --git a/llvm/test/Transforms/InstSimplify/or.ll b/llvm/test/Transforms/InstSimplify/or.ll index e8284264c612c4..7e7361d1239523 100644 --- a/llvm/test/Transforms/InstSimplify/or.ll +++ b/llvm/test/Transforms/InstSimplify/or.ll @@ -301,3 +301,97 @@ define i32 @poison(i32 %x) { %v = or i32 %x, poison ret i32 %v } + +declare void @use(i32) + +define i32 @and_or_not_or(i32 %A, i32 %B) { +; CHECK-LABEL: @and_or_not_or( +; CHECK-NEXT: [[I:%.*]] = xor i32 [[B:%.*]], -1 +; CHECK-NEXT: ret i32 [[I]] +; + %i = xor i32 %B, -1 + %i2 = and i32 %i, %A + %i3 = or i32 %B, %A + %i4 = xor i32 %i3, -1 + %i5 = or i32 %i2, %i4 + ret i32 %i5 +} + +define i32 @and_or_not_or2(i32 %A, i32 %B) { +; CHECK-LABEL: @and_or_not_or2( +; CHECK-NEXT: [[I:%.*]] = xor i32 [[A:%.*]], -1 +; CHECK-NEXT: ret i32 [[I]] +; + %i = xor i32 %A, -1 + %i2 = and i32 %i, %B + %i3 = or i32 %B, %A + %i4 = xor i32 %i3, -1 + %i5 = or i32 %i2, %i4 + ret i32 %i5 +} + +define <4 x i32> @and_or_not_or3_vec(<4 x i32> %A, <4 x i32> %B) { +; CHECK-LABEL: @and_or_not_or3_vec( +; CHECK-NEXT: [[I:%.*]] = xor <4 x i32> [[A:%.*]], +; CHECK-NEXT: ret <4 x i32> [[I]] +; + %i = xor <4 x i32> %A, + %i2 = and <4 x i32> %i, %B + %i3 = or <4 x i32> %B, %A + %i4 = xor <4 x i32> %i3, + %i5 = or <4 x i32> %i2, %i4 + ret <4 x i32> %i5 +} + +define i32 @and_or_not_or4_use(i32 %A, i32 %B) { +; CHECK-LABEL: @and_or_not_or4_use( +; CHECK-NEXT: [[I:%.*]] = xor i32 [[A:%.*]], -1 +; CHECK-NEXT: [[I2:%.*]] = and i32 [[I]], [[B:%.*]] +; CHECK-NEXT: tail call void @use(i32 [[I2]]) +; CHECK-NEXT: ret i32 [[I]] +; + %i = xor i32 %A, -1 + %i2 = and i32 %i, %B + tail call void @use(i32 %i2) + %i3 = or i32 %B, %A + %i4 = xor i32 %i3, -1 + %i5 = or i32 %i2, %i4 + ret i32 %i5 +} + +define i32 @and_or_not_or4_use2(i32 %A, i32 %B) { +; CHECK-LABEL: @and_or_not_or4_use2( +; CHECK-NEXT: [[I:%.*]] = or i32 [[B:%.*]], [[A:%.*]] +; CHECK-NEXT: [[I2:%.*]] = xor i32 [[I]], -1 +; CHECK-NEXT: tail call void @use(i32 [[I2]]) +; CHECK-NEXT: [[I3:%.*]] = xor i32 [[A]], -1 +; CHECK-NEXT: ret i32 [[I3]] +; + %i = or i32 %B, %A + %i2 = xor i32 %i, -1 + tail call void @use(i32 %i2) + %i3 = xor i32 %A, -1 + %i4 = and i32 %i3, %B + %i5 = or i32 %i4, %i2 + ret i32 %i5 +} + +define i32 @and_or_not_or4_use3(i32 %A, i32 %B) { +; CHECK-LABEL: @and_or_not_or4_use3( +; CHECK-NEXT: [[I:%.*]] = or i32 [[B:%.*]], [[A:%.*]] +; CHECK-NEXT: [[I2:%.*]] = xor i32 [[I]], -1 +; CHECK-NEXT: tail call void @use(i32 [[I2]]) +; CHECK-NEXT: [[I3:%.*]] = xor i32 [[A]], -1 +; CHECK-NEXT: [[I4:%.*]] = and i32 [[I3]], [[B]] +; CHECK-NEXT: tail call void @use(i32 [[I4]]) +; CHECK-NEXT: ret i32 [[I3]] +; + %i = or i32 %B, %A + %i2 = xor i32 %i, -1 + tail call void @use(i32 %i2) + %i3 = xor i32 %A, -1 + %i4 = and i32 %i3, %B + tail call void @use(i32 %i4) + %i5 = or i32 %i4, %i2 + ret i32 %i5 +} From 098dbf190a5586d02f48b84eb41b93b701cdeb97 Mon Sep 17 00:00:00 2001 From: Hsiangkai Wang Date: Fri, 15 Jan 2021 11:27:11 +0800 Subject: [PATCH 3/5] [RISCV] Correct alignment settings for vector registers. According to "9. Vector Memory Alignment Constraints" in V specification, the alignment of vector memory access is aligned to the size of the element. In our current implementation, we support ELEN up to 64. We could assume the alignment of vector registers is 64 under the assumption. Differential Revision: https://reviews.llvm.org/D94751 --- llvm/lib/Target/RISCV/RISCVRegisterInfo.td | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td index 99f74bfc2a09e2..75615fd334b78c 100644 --- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td +++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td @@ -386,11 +386,10 @@ let RegAltNameIndices = [ABIRegAltName] in { class VReg regTypes, dag regList, int Vlmul> : RegisterClass<"RISCV", regTypes, - // FIXME: Spill alignment set to 16 bytes. - 128, + 64, // The maximum supported ELEN is 64. regList> { int VLMul = Vlmul; - int Size = !mul(Vlmul, 64); // FIXME: assuming ELEN=64 + int Size = !mul(Vlmul, 64); } def VR : VReg<[vint8mf2_t, vint8mf4_t, vint8mf8_t, From bdd4dda58b0de08bd3474fb8d4589a9ba9349e88 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?D=C3=A1vid=20Bolvansk=C3=BD?= Date: Sat, 16 Jan 2021 16:31:02 +0100 Subject: [PATCH 4/5] [InstSimplify] Update comments, remove redundant tests --- llvm/lib/Analysis/InstructionSimplify.cpp | 2 + llvm/test/Transforms/InstCombine/or.ll | 110 ---------------------- 2 files changed, 2 insertions(+), 110 deletions(-) diff --git a/llvm/lib/Analysis/InstructionSimplify.cpp b/llvm/lib/Analysis/InstructionSimplify.cpp index 6266e922f8c9c4..73f046dcb8deb0 100644 --- a/llvm/lib/Analysis/InstructionSimplify.cpp +++ b/llvm/lib/Analysis/InstructionSimplify.cpp @@ -2264,6 +2264,8 @@ static Value *SimplifyOrInst(Value *Op0, Value *Op1, const SimplifyQuery &Q, // (~A & B) | ~(A | B) --> ~A // (~A & B) | ~(B | A) --> ~A + // (B & ~A) | ~(A | B) --> ~A + // (B & ~A) | ~(B | A) --> ~A if (match(Op0, m_And(m_Not(m_Value(A)), m_Value(B))) && match(Op1, m_Not(m_c_Or(m_Specific(A), m_Specific(B))))) return cast(Op0)->getOperand(0); diff --git a/llvm/test/Transforms/InstCombine/or.ll b/llvm/test/Transforms/InstCombine/or.ll index 0fc75fe082f82c..22ba395ebe9f61 100644 --- a/llvm/test/Transforms/InstCombine/or.ll +++ b/llvm/test/Transforms/InstCombine/or.ll @@ -1369,113 +1369,3 @@ define i32 @test5_use3(i32 %x, i32 %y) { %or1 = or i32 %xor, %neg ret i32 %or1 } - -define i32 @test6(i32 %A, i32 %B) { -; CHECK-LABEL: @test6( -; CHECK-NEXT: [[I:%.*]] = xor i32 [[B:%.*]], -1 -; CHECK-NEXT: [[I2:%.*]] = and i32 [[I]], [[A:%.*]] -; CHECK-NEXT: [[I3:%.*]] = or i32 [[B]], [[A]] -; CHECK-NEXT: [[I4:%.*]] = xor i32 [[I3]], -1 -; CHECK-NEXT: [[I5:%.*]] = or i32 [[I2]], [[I4]] -; CHECK-NEXT: ret i32 [[I5]] -; - %i = xor i32 %B, -1 - %i2 = and i32 %i, %A - %i3 = or i32 %B, %A - %i4 = xor i32 %i3, -1 - %i5 = or i32 %i2, %i4 - ret i32 %i5 -} - -define i32 @test7(i32 %A, i32 %B) { -; CHECK-LABEL: @test7( -; CHECK-NEXT: [[I:%.*]] = xor i32 [[A:%.*]], -1 -; CHECK-NEXT: [[I2:%.*]] = and i32 [[I]], [[B:%.*]] -; CHECK-NEXT: [[I3:%.*]] = or i32 [[B]], [[A]] -; CHECK-NEXT: [[I4:%.*]] = xor i32 [[I3]], -1 -; CHECK-NEXT: [[I5:%.*]] = or i32 [[I2]], [[I4]] -; CHECK-NEXT: ret i32 [[I5]] -; - %i = xor i32 %A, -1 - %i2 = and i32 %i, %B - %i3 = or i32 %B, %A - %i4 = xor i32 %i3, -1 - %i5 = or i32 %i2, %i4 - ret i32 %i5 -} - -define <4 x i32> @test8_vec(<4 x i32> %A, <4 x i32> %B) { -; CHECK-LABEL: @test8_vec( -; CHECK-NEXT: [[I:%.*]] = xor <4 x i32> [[A:%.*]], -; CHECK-NEXT: [[I2:%.*]] = and <4 x i32> [[I]], [[B:%.*]] -; CHECK-NEXT: [[I3:%.*]] = or <4 x i32> [[B]], [[A]] -; CHECK-NEXT: [[I4:%.*]] = xor <4 x i32> [[I3]], -; CHECK-NEXT: [[I5:%.*]] = or <4 x i32> [[I2]], [[I4]] -; CHECK-NEXT: ret <4 x i32> [[I5]] -; - %i = xor <4 x i32> %A, - %i2 = and <4 x i32> %i, %B - %i3 = or <4 x i32> %B, %A - %i4 = xor <4 x i32> %i3, - %i5 = or <4 x i32> %i2, %i4 - ret <4 x i32> %i5 -} - -define i32 @test9_use(i32 %A, i32 %B) { -; CHECK-LABEL: @test9_use( -; CHECK-NEXT: [[I:%.*]] = xor i32 [[A:%.*]], -1 -; CHECK-NEXT: [[I2:%.*]] = and i32 [[I]], [[B:%.*]] -; CHECK-NEXT: tail call void @use(i32 [[I2]]) -; CHECK-NEXT: [[I3:%.*]] = or i32 [[B]], [[A]] -; CHECK-NEXT: [[I4:%.*]] = xor i32 [[I3]], -1 -; CHECK-NEXT: [[I5:%.*]] = or i32 [[I2]], [[I4]] -; CHECK-NEXT: ret i32 [[I5]] -; - %i = xor i32 %A, -1 - %i2 = and i32 %i, %B - tail call void @use(i32 %i2) - %i3 = or i32 %B, %A - %i4 = xor i32 %i3, -1 - %i5 = or i32 %i2, %i4 - ret i32 %i5 -} - -define i32 @test9_use2(i32 %A, i32 %B) { -; CHECK-LABEL: @test9_use2( -; CHECK-NEXT: [[I:%.*]] = or i32 [[B:%.*]], [[A:%.*]] -; CHECK-NEXT: [[I2:%.*]] = xor i32 [[I]], -1 -; CHECK-NEXT: tail call void @use(i32 [[I2]]) -; CHECK-NEXT: [[I3:%.*]] = xor i32 [[A]], -1 -; CHECK-NEXT: [[I4:%.*]] = and i32 [[I3]], [[B]] -; CHECK-NEXT: [[I5:%.*]] = or i32 [[I4]], [[I2]] -; CHECK-NEXT: ret i32 [[I5]] -; - %i = or i32 %B, %A - %i2 = xor i32 %i, -1 - tail call void @use(i32 %i2) - %i3 = xor i32 %A, -1 - %i4 = and i32 %i3, %B - %i5 = or i32 %i4, %i2 - ret i32 %i5 -} - -define i32 @test9_use3(i32 %A, i32 %B) { -; CHECK-LABEL: @test9_use3( -; CHECK-NEXT: [[I:%.*]] = or i32 [[B:%.*]], [[A:%.*]] -; CHECK-NEXT: [[I2:%.*]] = xor i32 [[I]], -1 -; CHECK-NEXT: tail call void @use(i32 [[I2]]) -; CHECK-NEXT: [[I3:%.*]] = xor i32 [[A]], -1 -; CHECK-NEXT: [[I4:%.*]] = and i32 [[I3]], [[B]] -; CHECK-NEXT: tail call void @use(i32 [[I4]]) -; CHECK-NEXT: [[I5:%.*]] = or i32 [[I4]], [[I2]] -; CHECK-NEXT: ret i32 [[I5]] -; - %i = or i32 %B, %A - %i2 = xor i32 %i, -1 - tail call void @use(i32 %i2) - %i3 = xor i32 %A, -1 - %i4 = and i32 %i3, %B - tail call void @use(i32 %i4) - %i5 = or i32 %i4, %i2 - ret i32 %i5 -} From bca16e2fbb451f125c13f811f9f5a37bb38e54e2 Mon Sep 17 00:00:00 2001 From: Florian Hahn Date: Sat, 16 Jan 2021 16:28:05 +0000 Subject: [PATCH 5/5] [LTO] Remove options to disable inlining, vectorization & GVNLoadPRE. This patch removes some ancient options as a clean-up before moving code-gen to use LTOBackend in D94487. I think it would preferable to remove those ancient options, because 1. There are no corresponding options in LTOBackend based tools, 2. There are no unit tests for them, 3. They are not passed through by Clang, 4. At least for GNVLoadPRE, users could just use GVN's `enable-load-pre`. Alternatively we could add support for those options to lto::Config & co, but I think it would be better to remove them, unless they are actually used in practice. Reviewed By: steven_wu, tejohnson Differential Revision: https://reviews.llvm.org/D94783 --- .../llvm/LTO/legacy/LTOCodeGenerator.h | 11 +++----- llvm/lib/LTO/LTOCodeGenerator.cpp | 27 ++++++------------- llvm/tools/llvm-lto/llvm-lto.cpp | 17 ++---------- llvm/tools/lto/lto.cpp | 23 +++------------- 4 files changed, 16 insertions(+), 62 deletions(-) diff --git a/llvm/include/llvm/LTO/legacy/LTOCodeGenerator.h b/llvm/include/llvm/LTO/legacy/LTOCodeGenerator.h index d7ccc0d5a6c537..a817969abc5821 100644 --- a/llvm/include/llvm/LTO/legacy/LTOCodeGenerator.h +++ b/llvm/include/llvm/LTO/legacy/LTOCodeGenerator.h @@ -145,9 +145,7 @@ struct LTOCodeGenerator { /// \note It is up to the linker to remove the intermediate output file. Do /// not try to remove the object file in LTOCodeGenerator's destructor as we /// don't who (LTOCodeGenerator or the output file) will last longer. - bool compile_to_file(const char **Name, bool DisableVerify, - bool DisableInline, bool DisableGVNLoadPRE, - bool DisableVectorization); + bool compile_to_file(const char **Name, bool DisableVerify); /// As with compile_to_file(), this function compiles the merged module into /// single output file. Instead of returning the output file path to the @@ -155,15 +153,12 @@ struct LTOCodeGenerator { /// to the caller. This function should delete the intermediate file once /// its content is brought to memory. Return NULL if the compilation was not /// successful. - std::unique_ptr compile(bool DisableVerify, bool DisableInline, - bool DisableGVNLoadPRE, - bool DisableVectorization); + std::unique_ptr compile(bool DisableVerify); /// Optimizes the merged module. Returns true on success. /// /// Calls \a verifyMergedModuleOnce(). - bool optimize(bool DisableVerify, bool DisableInline, bool DisableGVNLoadPRE, - bool DisableVectorization); + bool optimize(bool DisableVerify); /// Compiles the merged optimized module into a single output file. It brings /// the output to a buffer, and returns the buffer to the caller. Return NULL diff --git a/llvm/lib/LTO/LTOCodeGenerator.cpp b/llvm/lib/LTO/LTOCodeGenerator.cpp index 890e9adf17e52a..cb30db1932596c 100644 --- a/llvm/lib/LTO/LTOCodeGenerator.cpp +++ b/llvm/lib/LTO/LTOCodeGenerator.cpp @@ -326,22 +326,15 @@ LTOCodeGenerator::compileOptimized() { return std::move(*BufferOrErr); } -bool LTOCodeGenerator::compile_to_file(const char **Name, bool DisableVerify, - bool DisableInline, - bool DisableGVNLoadPRE, - bool DisableVectorization) { - if (!optimize(DisableVerify, DisableInline, DisableGVNLoadPRE, - DisableVectorization)) +bool LTOCodeGenerator::compile_to_file(const char **Name, bool DisableVerify) { + if (!optimize(DisableVerify)) return false; return compileOptimizedToFile(Name); } -std::unique_ptr -LTOCodeGenerator::compile(bool DisableVerify, bool DisableInline, - bool DisableGVNLoadPRE, bool DisableVectorization) { - if (!optimize(DisableVerify, DisableInline, DisableGVNLoadPRE, - DisableVectorization)) +std::unique_ptr LTOCodeGenerator::compile(bool DisableVerify) { + if (!optimize(DisableVerify)) return nullptr; return compileOptimized(); @@ -534,9 +527,7 @@ void LTOCodeGenerator::finishOptimizationRemarks() { } /// Optimize merged modules using various IPO passes -bool LTOCodeGenerator::optimize(bool DisableVerify, bool DisableInline, - bool DisableGVNLoadPRE, - bool DisableVectorization) { +bool LTOCodeGenerator::optimize(bool DisableVerify) { if (!this->determineTarget()) return false; @@ -585,11 +576,9 @@ bool LTOCodeGenerator::optimize(bool DisableVerify, bool DisableInline, Triple TargetTriple(TargetMach->getTargetTriple()); PassManagerBuilder PMB; - PMB.DisableGVNLoadPRE = DisableGVNLoadPRE; - PMB.LoopVectorize = !DisableVectorization; - PMB.SLPVectorize = !DisableVectorization; - if (!DisableInline) - PMB.Inliner = createFunctionInliningPass(); + PMB.LoopVectorize = true; + PMB.SLPVectorize = true; + PMB.Inliner = createFunctionInliningPass(); PMB.LibraryInfo = new TargetLibraryInfoImpl(TargetTriple); if (Freestanding) PMB.LibraryInfo->disableAllFunctions(); diff --git a/llvm/tools/llvm-lto/llvm-lto.cpp b/llvm/tools/llvm-lto/llvm-lto.cpp index 6052d6c962f7b1..ad6b78bc46a6b8 100644 --- a/llvm/tools/llvm-lto/llvm-lto.cpp +++ b/llvm/tools/llvm-lto/llvm-lto.cpp @@ -78,17 +78,6 @@ static cl::opt DisableVerify( "disable-verify", cl::init(false), cl::desc("Do not run the verifier during the optimization pipeline")); -static cl::opt DisableInline("disable-inlining", cl::init(false), - cl::desc("Do not run the inliner pass")); - -static cl::opt - DisableGVNLoadPRE("disable-gvn-loadpre", cl::init(false), - cl::desc("Do not run the GVN load PRE pass")); - -static cl::opt DisableLTOVectorization( - "disable-lto-vectorization", cl::init(false), - cl::desc("Do not run loop or slp vectorization during LTO")); - static cl::opt EnableFreestanding( "lto-freestanding", cl::init(false), cl::desc("Enable Freestanding (disable builtins / TLI) during LTO")); @@ -1042,8 +1031,7 @@ int main(int argc, char **argv) { error("writing linked module failed."); } - if (!CodeGen.optimize(DisableVerify, DisableInline, DisableGVNLoadPRE, - DisableLTOVectorization)) { + if (!CodeGen.optimize(DisableVerify)) { // Diagnostic messages should have been printed by the handler. error("error optimizing the code"); } @@ -1084,8 +1072,7 @@ int main(int argc, char **argv) { error(": -save-merged-module must be specified with -o"); const char *OutputName = nullptr; - if (!CodeGen.compile_to_file(&OutputName, DisableVerify, DisableInline, - DisableGVNLoadPRE, DisableLTOVectorization)) + if (!CodeGen.compile_to_file(&OutputName, DisableVerify)) error("error compiling the code"); // Diagnostic messages should have been printed by the handler. diff --git a/llvm/tools/lto/lto.cpp b/llvm/tools/lto/lto.cpp index 0ea7b4942e32ed..81f64df403ab9b 100644 --- a/llvm/tools/lto/lto.cpp +++ b/llvm/tools/lto/lto.cpp @@ -41,18 +41,6 @@ OptLevel("O", cl::ZeroOrMore, cl::init('2')); -static cl::opt -DisableInline("disable-inlining", cl::init(false), - cl::desc("Do not run the inliner pass")); - -static cl::opt -DisableGVNLoadPRE("disable-gvn-loadpre", cl::init(false), - cl::desc("Do not run the GVN load PRE pass")); - -static cl::opt DisableLTOVectorization( - "disable-lto-vectorization", cl::init(false), - cl::desc("Do not run loop or slp vectorization during LTO")); - static cl::opt EnableFreestanding( "lto-freestanding", cl::init(false), cl::desc("Enable Freestanding (disable builtins / TLI) during LTO")); @@ -448,9 +436,7 @@ bool lto_codegen_write_merged_modules(lto_code_gen_t cg, const char *path) { const void *lto_codegen_compile(lto_code_gen_t cg, size_t *length) { maybeParseOptions(cg); LibLTOCodeGenerator *CG = unwrap(cg); - CG->NativeObjectFile = - CG->compile(DisableVerify, DisableInline, DisableGVNLoadPRE, - DisableLTOVectorization); + CG->NativeObjectFile = CG->compile(DisableVerify); if (!CG->NativeObjectFile) return nullptr; *length = CG->NativeObjectFile->getBufferSize(); @@ -459,8 +445,7 @@ const void *lto_codegen_compile(lto_code_gen_t cg, size_t *length) { bool lto_codegen_optimize(lto_code_gen_t cg) { maybeParseOptions(cg); - return !unwrap(cg)->optimize(DisableVerify, DisableInline, DisableGVNLoadPRE, - DisableLTOVectorization); + return !unwrap(cg)->optimize(DisableVerify); } const void *lto_codegen_compile_optimized(lto_code_gen_t cg, size_t *length) { @@ -475,9 +460,7 @@ const void *lto_codegen_compile_optimized(lto_code_gen_t cg, size_t *length) { bool lto_codegen_compile_to_file(lto_code_gen_t cg, const char **name) { maybeParseOptions(cg); - return !unwrap(cg)->compile_to_file( - name, DisableVerify, DisableInline, DisableGVNLoadPRE, - DisableLTOVectorization); + return !unwrap(cg)->compile_to_file(name, DisableVerify); } void lto_codegen_debug_options(lto_code_gen_t cg, const char *opt) {