From 6f10998ad80687a85633d8dda84146c57c49ca25 Mon Sep 17 00:00:00 2001 From: Andrzej Warzynski Date: Fri, 25 Sep 2020 09:52:49 +0100 Subject: [PATCH 1/6] [flang][driver] Add missing dependency (shared library builds, NFC) `FlangFrontendTests` depends on libclangFrontend (it uses DiagnosticConsumer classes from there). This patch adds the missing dependency in CMake. The missing dependency manifests itself only with BUILD_SHARED_LIBS=ON. This symbol is linked in statically with libflangFrontend when BUILD_SHARED_LIBS=OFF. --- flang/unittests/Frontend/CMakeLists.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/flang/unittests/Frontend/CMakeLists.txt b/flang/unittests/Frontend/CMakeLists.txt index dd5cbedb0f91d5..54853a59adfeb8 100644 --- a/flang/unittests/Frontend/CMakeLists.txt +++ b/flang/unittests/Frontend/CMakeLists.txt @@ -6,5 +6,6 @@ target_link_libraries(FlangFrontendTests PRIVATE LLVMSupport clangBasic + clangFrontend flangFrontend flangFrontendTool) From ade6fa46f94b31e89c8a488264ac79e319d1ccdb Mon Sep 17 00:00:00 2001 From: Amara Emerson Date: Thu, 24 Sep 2020 13:06:03 -0700 Subject: [PATCH 2/6] [AArch64][GlobalISel] Make <8 x s16> for G_INSERT_VECTOR_ELT legal. --- .../AArch64/GISel/AArch64LegalizerInfo.cpp | 6 +- .../GlobalISel/legalize-insert-vector-elt.mir | 79 +++++++++++++++++++ .../GlobalISel/select-insert-vector-elt.mir | 27 +++++++ 3 files changed, 107 insertions(+), 5 deletions(-) create mode 100644 llvm/test/CodeGen/AArch64/GlobalISel/legalize-insert-vector-elt.mir diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp index 43f3c1d31da5f8..5274d643e62477 100644 --- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp +++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp @@ -597,11 +597,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST) .minScalarOrElt(0, s8); // Worst case, we need at least s8. getActionDefinitionsBuilder(G_INSERT_VECTOR_ELT) - .legalIf([=](const LegalityQuery &Query) { - const LLT &VecTy = Query.Types[0]; - // TODO: Support s8 and s16 - return VecTy == v2s32 || VecTy == v4s32 || VecTy == v2s64; - }); + .legalIf(typeInSet(0, {v8s16, v2s32, v4s32, v2s64})); getActionDefinitionsBuilder(G_BUILD_VECTOR) .legalFor({{v8s8, s8}, diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-insert-vector-elt.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-insert-vector-elt.mir new file mode 100644 index 00000000000000..328935b1a6ca1c --- /dev/null +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-insert-vector-elt.mir @@ -0,0 +1,79 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=aarch64-linux-gnu -O0 -run-pass=legalizer %s -o - -global-isel-abort=1 | FileCheck %s + +--- +name: v8s16 +body: | + bb.0: + liveins: $q0 + ; CHECK-LABEL: name: v8s16 + ; CHECK: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0 + ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK: %val:_(s16) = G_CONSTANT i16 42 + ; CHECK: [[IVEC:%[0-9]+]]:_(<8 x s16>) = G_INSERT_VECTOR_ELT [[COPY]], %val(s16), [[C]](s32) + ; CHECK: $q0 = COPY [[IVEC]](<8 x s16>) + ; CHECK: RET_ReallyLR + %0:_(<8 x s16>) = COPY $q0 + %1:_(s32) = G_CONSTANT i32 1 + %val:_(s16) = G_CONSTANT i16 42 + %2:_(<8 x s16>) = G_INSERT_VECTOR_ELT %0(<8 x s16>), %val(s16), %1(s32) + $q0 = COPY %2(<8 x s16>) + RET_ReallyLR +... +--- +name: v2s32 +body: | + bb.0: + liveins: $q0 + ; CHECK-LABEL: name: v2s32 + ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0 + ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK: %val:_(s32) = G_CONSTANT i32 42 + ; CHECK: [[IVEC:%[0-9]+]]:_(<2 x s32>) = G_INSERT_VECTOR_ELT [[COPY]], %val(s32), [[C]](s32) + ; CHECK: $d0 = COPY [[IVEC]](<2 x s32>) + ; CHECK: RET_ReallyLR + %0:_(<2 x s32>) = COPY $d0 + %1:_(s32) = G_CONSTANT i32 1 + %val:_(s32) = G_CONSTANT i32 42 + %2:_(<2 x s32>) = G_INSERT_VECTOR_ELT %0(<2 x s32>), %val(s32), %1(s32) + $d0 = COPY %2(<2 x s32>) + RET_ReallyLR +... +--- +name: v4s32 +body: | + bb.0: + liveins: $q0 + ; CHECK-LABEL: name: v4s32 + ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0 + ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK: %val:_(s32) = G_CONSTANT i32 42 + ; CHECK: [[IVEC:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[COPY]], %val(s32), [[C]](s32) + ; CHECK: $q0 = COPY [[IVEC]](<4 x s32>) + ; CHECK: RET_ReallyLR + %0:_(<4 x s32>) = COPY $q0 + %1:_(s32) = G_CONSTANT i32 1 + %val:_(s32) = G_CONSTANT i32 42 + %2:_(<4 x s32>) = G_INSERT_VECTOR_ELT %0(<4 x s32>), %val(s32), %1(s32) + $q0 = COPY %2(<4 x s32>) + RET_ReallyLR +... +--- +name: v2s64 +body: | + bb.0: + liveins: $q0 + ; CHECK-LABEL: name: v2s64 + ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0 + ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK: %val:_(s64) = G_CONSTANT i64 42 + ; CHECK: [[IVEC:%[0-9]+]]:_(<2 x s64>) = G_INSERT_VECTOR_ELT [[COPY]], %val(s64), [[C]](s32) + ; CHECK: $q0 = COPY [[IVEC]](<2 x s64>) + ; CHECK: RET_ReallyLR + %0:_(<2 x s64>) = COPY $q0 + %1:_(s32) = G_CONSTANT i32 1 + %val:_(s64) = G_CONSTANT i64 42 + %2:_(<2 x s64>) = G_INSERT_VECTOR_ELT %0(<2 x s64>), %val(s64), %1(s32) + $q0 = COPY %2(<2 x s64>) + RET_ReallyLR +... diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-insert-vector-elt.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-insert-vector-elt.mir index 7890a4c846ad05..5c4a2e1c3544f5 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-insert-vector-elt.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-insert-vector-elt.mir @@ -1,6 +1,33 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -verify-machineinstrs -mtriple aarch64-unknown-unknown -run-pass=instruction-select %s -o - | FileCheck %s +--- +name: v8s16_fpr +alignment: 4 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $q1, $h0 + ; CHECK-LABEL: name: v8s16_fpr + ; CHECK: liveins: $q1, $h0 + ; CHECK: [[COPY:%[0-9]+]]:fpr16 = COPY $h0 + ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 + ; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF + ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.hsub + ; CHECK: [[INSvi16lane:%[0-9]+]]:fpr128 = INSvi16lane [[COPY1]], 1, [[INSERT_SUBREG]], 0 + ; CHECK: $q0 = COPY [[INSvi16lane]] + ; CHECK: RET_ReallyLR implicit $q0 + %0:fpr(s16) = COPY $h0 + %1:fpr(<8 x s16>) = COPY $q1 + %3:gpr(s32) = G_CONSTANT i32 1 + %2:fpr(<8 x s16>) = G_INSERT_VECTOR_ELT %1, %0(s16), %3(s32) + $q0 = COPY %2(<8 x s16>) + RET_ReallyLR implicit $q0 + +... +--- name: v4s32_fpr alignment: 4 legalized: true From f7b36b35b69a3f100c740ac4bcd933fcdce58798 Mon Sep 17 00:00:00 2001 From: Amara Emerson Date: Fri, 25 Sep 2020 01:28:50 -0700 Subject: [PATCH 3/6] [AArch64][GlobalISel] Manually select G_DUP with s8/s16 gpr scalar operands. These don't get selected by the imported patterns, and avoiding generating them is a whole load of not-worth-it-hassle (until we have fp types in GlobalISel). --- .../GISel/AArch64InstructionSelector.cpp | 18 ++++++++ .../CodeGen/AArch64/GlobalISel/select-dup.mir | 46 +++++++++++++++++++ 2 files changed, 64 insertions(+) diff --git a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp index d5cdfc35899766..01bd05a2b9880e 100644 --- a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp +++ b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp @@ -2971,6 +2971,24 @@ bool AArch64InstructionSelector::select(MachineInstr &I) { return constrainSelectedInstRegOperands(*MovMI, TII, TRI, RBI); } } + case AArch64::G_DUP: { + // When the scalar of G_DUP is an s8/s16 gpr, they can't be selected by + // imported patterns. Do it manually here. Avoiding generating s16 gpr is + // difficult because at RBS we may end up pessimizing the fpr case if we + // decided to add an anyextend to fix this. Manual selection is the most + // robust solution for now. + Register SrcReg = I.getOperand(1).getReg(); + if (RBI.getRegBank(SrcReg, MRI, TRI)->getID() != AArch64::GPRRegBankID) + return false; // We expect the fpr regbank case to be imported. + LLT SrcTy = MRI.getType(SrcReg); + if (SrcTy.getSizeInBits() == 16) + I.setDesc(TII.get(AArch64::DUPv8i16gpr)); + else if (SrcTy.getSizeInBits() == 8) + I.setDesc(TII.get(AArch64::DUPv16i8gpr)); + else + return false; + return constrainSelectedInstRegOperands(I, TII, TRI, RBI); + } case TargetOpcode::G_INTRINSIC_TRUNC: return selectIntrinsicTrunc(I, MRI); case TargetOpcode::G_INTRINSIC_ROUND: diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-dup.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-dup.mir index 1848e338b7aa6e..182bba1ae38423 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-dup.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-dup.mir @@ -223,6 +223,29 @@ body: | $q0 = COPY %dup(<8 x s16>) RET_ReallyLR implicit $q0 +... +--- +name: DUPv8i16gpr_s16_src +alignment: 4 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $w0 + ; Checks that we can still select the gpr variant if the scalar is an s16. + ; CHECK-LABEL: name: DUPv8i16gpr_s16_src + ; CHECK: liveins: $w0 + ; CHECK: %copy:gpr32 = COPY $w0 + ; CHECK: %dup:fpr128 = DUPv8i16gpr %copy + ; CHECK: $q0 = COPY %dup + ; CHECK: RET_ReallyLR implicit $q0 + %copy:gpr(s32) = COPY $w0 + %trunc:gpr(s16) = G_TRUNC %copy + %dup:fpr(<8 x s16>) = G_DUP %trunc(s16) + $q0 = COPY %dup(<8 x s16>) + RET_ReallyLR implicit $q0 + ... --- name: DUPv8i8gpr @@ -264,3 +287,26 @@ body: | %dup:fpr(<16 x s8>) = G_DUP %copy(s32) $q0 = COPY %dup(<16 x s8>) RET_ReallyLR implicit $q0 +... +--- +name: DUPv16i8gpr_s8_src +alignment: 4 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $w0 + ; Check we still select the gpr variant when scalar is an s8. + ; CHECK-LABEL: name: DUPv16i8gpr_s8_src + ; CHECK: liveins: $w0 + ; CHECK: %copy:gpr32 = COPY $w0 + ; CHECK: %dup:fpr128 = DUPv16i8gpr %copy + ; CHECK: $q0 = COPY %dup + ; CHECK: RET_ReallyLR implicit $q0 + %copy:gpr(s32) = COPY $w0 + %trunc:gpr(s8) = G_TRUNC %copy + %dup:fpr(<16 x s8>) = G_DUP %trunc(s8) + $q0 = COPY %dup(<16 x s8>) + RET_ReallyLR implicit $q0 +... From 64f878db5022cf9258ff308f15ad07d27c9ca4d9 Mon Sep 17 00:00:00 2001 From: Georgii Rymar Date: Thu, 24 Sep 2020 17:39:11 +0300 Subject: [PATCH 4/6] [Object/yaml2obj/obj2yaml][test] - Split, cleanup and move MIPS abi-flags.yaml test. NFCI. We have the `Object/Mips/abi-flags.yaml` which tests how yaml2obj/obj2yaml handle `SHT_MIPS_ABIFLAGS` sections. This patch splits it into two tests: one for obj2yaml and one for yaml2obj and moves the result to right places. Differential revision: https://reviews.llvm.org/D88231 --- llvm/test/Object/Mips/abi-flags.yaml | 64 ------------------- .../tools/obj2yaml/ELF/mips-abi-flags.yaml | 41 ++++++++++++ .../tools/yaml2obj/ELF/mips-abi-flags.yaml | 45 +++++++++++++ 3 files changed, 86 insertions(+), 64 deletions(-) delete mode 100644 llvm/test/Object/Mips/abi-flags.yaml create mode 100644 llvm/test/tools/obj2yaml/ELF/mips-abi-flags.yaml create mode 100644 llvm/test/tools/yaml2obj/ELF/mips-abi-flags.yaml diff --git a/llvm/test/Object/Mips/abi-flags.yaml b/llvm/test/Object/Mips/abi-flags.yaml deleted file mode 100644 index 4fa09d179da04d..00000000000000 --- a/llvm/test/Object/Mips/abi-flags.yaml +++ /dev/null @@ -1,64 +0,0 @@ -# RUN: yaml2obj %s -o %t -# RUN: llvm-readobj -A %t | FileCheck -check-prefix=OBJ %s -# RUN: obj2yaml %t | FileCheck -check-prefix=YAML %s - -# OBJ: MIPS ABI Flags { -# OBJ-NEXT: Version: 0 -# OBJ-NEXT: ISA: MIPS64r5 -# OBJ-NEXT: ISA Extension: Cavium Networks Octeon3 (0x13) -# OBJ-NEXT: ASEs [ (0x103) -# OBJ-NEXT: DSP (0x1) -# OBJ-NEXT: DSPR2 (0x2) -# OBJ-NEXT: VZ (0x100) -# OBJ-NEXT: ] -# OBJ-NEXT: FP ABI: Hard float (double precision) (0x1) -# OBJ-NEXT: GPR size: 64 -# OBJ-NEXT: CPR1 size: 64 -# OBJ-NEXT: CPR2 size: 0 -# OBJ-NEXT: Flags 1 [ (0x1) -# OBJ-NEXT: ODDSPREG (0x1) -# OBJ-NEXT: ] -# OBJ-NEXT: Flags 2: 0x0 -# OBJ-NEXT: } - -# YAML: Sections: -# YAML-NEXT: - Name: .MIPS.abiflags -# YAML-NEXT: Type: SHT_MIPS_ABIFLAGS -# YAML-NEXT: AddressAlign: 0x0000000000000008 -# YAML-NEXT: EntSize: 0x0000000000000018 -# YAML-NEXT: ISA: MIPS64 -# YAML-NEXT: ISARevision: 0x05 -# YAML-NEXT: ISAExtension: EXT_OCTEON3 -# YAML-NEXT: ASEs: [ DSP, DSPR2, VIRT ] -# YAML-NEXT: FpABI: FP_DOUBLE -# YAML-NEXT: GPRSize: REG_64 -# YAML-NEXT: CPR1Size: REG_64 -# YAML-NEXT: Flags1: [ ODDSPREG ] - -!ELF -FileHeader: - Class: ELFCLASS64 - Data: ELFDATA2MSB - Type: ET_REL - Machine: EM_MIPS - -Sections: -- Name: .MIPS.abiflags - Type: SHT_MIPS_ABIFLAGS - AddressAlign: 8 - Version: 0 - ISA: MIPS64 - ISARevision: 5 - ISAExtension: EXT_OCTEON3 - ASEs: [ DSP, DSPR2, VIRT ] - FpABI: FP_DOUBLE - GPRSize: REG_64 - CPR1Size: REG_64 - CPR2Size: REG_NONE - Flags1: [ ODDSPREG ] - Flags2: 0x0 - -Symbols: - - Name: .MIPS.abiflags - Type: STT_SECTION - Section: .MIPS.abiflags diff --git a/llvm/test/tools/obj2yaml/ELF/mips-abi-flags.yaml b/llvm/test/tools/obj2yaml/ELF/mips-abi-flags.yaml new file mode 100644 index 00000000000000..e51e1c214ce74b --- /dev/null +++ b/llvm/test/tools/obj2yaml/ELF/mips-abi-flags.yaml @@ -0,0 +1,41 @@ +## Check how obj2yaml dumps SHT_MIPS_ABIFLAGS sections. + +# RUN: yaml2obj %s -o %t +# RUN: obj2yaml %t | FileCheck %s + +# CHECK: Sections: +# CHECK-NEXT: - Name: .MIPS.abiflags +# CHECK-NEXT: Type: SHT_MIPS_ABIFLAGS +# CHECK-NEXT: AddressAlign: 0x0000000000000008 +# CHECK-NEXT: EntSize: 0x0000000000000018 +# CHECK-NEXT: ISA: MIPS64 +# CHECK-NEXT: ISARevision: 0x05 +# CHECK-NEXT: ISAExtension: EXT_OCTEON3 +# CHECK-NEXT: ASEs: [ DSP, DSPR2, VIRT ] +# CHECK-NEXT: FpABI: FP_DOUBLE +# CHECK-NEXT: GPRSize: REG_64 +# CHECK-NEXT: CPR1Size: REG_64 +# CHECK-NEXT: Flags1: [ ODDSPREG ] +# CHECK-NEXT: ... + +--- !ELF +FileHeader: + Class: ELFCLASS64 + Data: ELFDATA2MSB + Type: ET_REL + Machine: EM_MIPS +Sections: + - Name: .MIPS.abiflags + Type: SHT_MIPS_ABIFLAGS + AddressAlign: 8 + Version: 0 + ISA: MIPS64 + ISARevision: 5 + ISAExtension: EXT_OCTEON3 + ASEs: [ DSP, DSPR2, VIRT ] + FpABI: FP_DOUBLE + GPRSize: REG_64 + CPR1Size: REG_64 + CPR2Size: REG_NONE + Flags1: [ ODDSPREG ] + Flags2: 0x0 diff --git a/llvm/test/tools/yaml2obj/ELF/mips-abi-flags.yaml b/llvm/test/tools/yaml2obj/ELF/mips-abi-flags.yaml new file mode 100644 index 00000000000000..b635e7161502c9 --- /dev/null +++ b/llvm/test/tools/yaml2obj/ELF/mips-abi-flags.yaml @@ -0,0 +1,45 @@ +## Test how yaml2obj creates SHT_MIPS_ABIFLAGS sections. + +# RUN: yaml2obj %s -o %t +# RUN: llvm-readobj -A %t | FileCheck %s + +# CHECK: MIPS ABI Flags { +# CHECK-NEXT: Version: 0 +# CHECK-NEXT: ISA: MIPS64r5 +# CHECK-NEXT: ISA Extension: Cavium Networks Octeon3 (0x13) +# CHECK-NEXT: ASEs [ (0x103) +# CHECK-NEXT: DSP (0x1) +# CHECK-NEXT: DSPR2 (0x2) +# CHECK-NEXT: VZ (0x100) +# CHECK-NEXT: ] +# CHECK-NEXT: FP ABI: Hard float (double precision) (0x1) +# CHECK-NEXT: GPR size: 64 +# CHECK-NEXT: CPR1 size: 64 +# CHECK-NEXT: CPR2 size: 0 +# CHECK-NEXT: Flags 1 [ (0x1) +# CHECK-NEXT: ODDSPREG (0x1) +# CHECK-NEXT: ] +# CHECK-NEXT: Flags 2: 0x0 +# CHECK-NEXT: } + +--- !ELF +FileHeader: + Class: ELFCLASS64 + Data: ELFDATA2MSB + Type: ET_REL + Machine: EM_MIPS +Sections: + - Name: .MIPS.abiflags + Type: SHT_MIPS_ABIFLAGS + AddressAlign: 8 + Version: 0 + ISA: MIPS64 + ISARevision: 5 + ISAExtension: EXT_OCTEON3 + ASEs: [ DSP, DSPR2, VIRT ] + FpABI: FP_DOUBLE + GPRSize: REG_64 + CPR1Size: REG_64 + CPR2Size: REG_NONE + Flags1: [ ODDSPREG ] + Flags2: 0x0 From 3a98f4dca7ada4c50ebca646f2cdd7385cd778af Mon Sep 17 00:00:00 2001 From: Vitaly Buka Date: Fri, 25 Sep 2020 01:28:23 -0700 Subject: [PATCH 5/6] [msan] Fix gethostent tests gethostent should follow sethostent. --- compiler-rt/lib/msan/tests/msan_test.cpp | 2 ++ 1 file changed, 2 insertions(+) diff --git a/compiler-rt/lib/msan/tests/msan_test.cpp b/compiler-rt/lib/msan/tests/msan_test.cpp index 6306b3dbfb82df..318a355312a57b 100644 --- a/compiler-rt/lib/msan/tests/msan_test.cpp +++ b/compiler-rt/lib/msan/tests/msan_test.cpp @@ -1114,6 +1114,7 @@ TEST_P(MemorySanitizerIpTest, recvmsg) { } while (0) TEST(MemorySanitizer, gethostent) { + sethostent(0); struct hostent *he = gethostent(); ASSERT_NE((void *)NULL, he); EXPECT_HOSTENT_NOT_POISONED(he); @@ -1177,6 +1178,7 @@ TEST(MemorySanitizer, gethostbyaddr) { #if !defined(__NetBSD__) TEST(MemorySanitizer, gethostent_r) { + sethostent(0); char buf[2000]; struct hostent he; struct hostent *result; From 7af12015ad44bccb23bd61820c8f34212467e71c Mon Sep 17 00:00:00 2001 From: Vitaly Buka Date: Fri, 25 Sep 2020 02:20:33 -0700 Subject: [PATCH 6/6] [msan] Remove redundant test The test needs to control intercept_strcmp option. It's already implemented as lit.test strcmp.c. --- compiler-rt/lib/msan/tests/msan_test.cpp | 14 -------------- 1 file changed, 14 deletions(-) diff --git a/compiler-rt/lib/msan/tests/msan_test.cpp b/compiler-rt/lib/msan/tests/msan_test.cpp index 318a355312a57b..1ece56e665715e 100644 --- a/compiler-rt/lib/msan/tests/msan_test.cpp +++ b/compiler-rt/lib/msan/tests/msan_test.cpp @@ -587,20 +587,6 @@ LargeStruct LargeRetTest() { return res; } -TEST(MemorySanitizer, strcmp) { - char s1[10]; - char s2[10]; - strncpy(s1, "foo", 10); - s2[0] = 'f'; - s2[1] = 'n'; - EXPECT_GT(strcmp(s1, s2), 0); - s2[1] = 'o'; - int res; - EXPECT_UMR(res = strcmp(s1, s2)); - EXPECT_NOT_POISONED(res); - EXPECT_EQ(strncmp(s1, s2, 1), 0); -} - TEST(MemorySanitizer, LargeRet) { LargeStruct a = LargeRetTest(); EXPECT_POISONED(a.x[0]);