From 5ad0302ed8924fc73db495f30c50e5ced0114a09 Mon Sep 17 00:00:00 2001
From: dstuttar <david.stuttard@amd.com>
Date: Fri, 14 Aug 2020 15:05:35 +0100
Subject: [PATCH] Revert "AMDGPU: Fix verifier error on spilling partially
 defined SGPRs"

This reverts commit 592f2e8d1ceb8ecec6f8b54eeb9fd7e0a099c0fe.

Change-Id: I0045c5ed660ee6664267593a89051b8d363b5ef4
---
 llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp     |  8 +--
 .../AMDGPU/sgpr-spill-partially-undef.mir     | 52 -------------------
 2 files changed, 1 insertion(+), 59 deletions(-)
 delete mode 100644 llvm/test/CodeGen/AMDGPU/sgpr-spill-partially-undef.mir

diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
index 5768cc7f17cd00..c6f3930db03984 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -1041,19 +1041,13 @@ bool SIRegisterInfo::spillSGPR(MachineBasicBlock::iterator MI,
 
       // Mark the "old value of vgpr" input undef only if this is the first sgpr
       // spill to this specific vgpr in the first basic block.
-      auto MIB = BuildMI(*MBB, MI, DL,
+      BuildMI(*MBB, MI, DL,
               TII->getMCOpcodeFromPseudo(AMDGPU::V_WRITELANE_B32),
               Spill.VGPR)
         .addReg(SubReg, getKillRegState(IsKill))
         .addImm(Spill.Lane)
         .addReg(Spill.VGPR, VGPRDefined ? 0 : RegState::Undef);
 
-      if (i == 0 && NumSubRegs > 1) {
-        // We may be spilling a super-register which is only partially defined,
-        // and need to ensure later spills think the value is defined.
-        MIB.addReg(SuperReg, RegState::ImplicitDefine);
-      }
-
       // FIXME: Since this spills to another register instead of an actual
       // frame index, we should delete the frame index when all references to
       // it are fixed.
diff --git a/llvm/test/CodeGen/AMDGPU/sgpr-spill-partially-undef.mir b/llvm/test/CodeGen/AMDGPU/sgpr-spill-partially-undef.mir
deleted file mode 100644
index 777a692affca0a..00000000000000
--- a/llvm/test/CodeGen/AMDGPU/sgpr-spill-partially-undef.mir
+++ /dev/null
@@ -1,52 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs -run-pass=si-lower-sgpr-spills -o - %s  | FileCheck %s
-#
-# Check for liveness errors when spilling partially defined super registers.
-
----
-name:  sgpr_spill_s64_undef_high32
-tracksRegLiveness: true
-machineFunctionInfo:
-  isEntryFunction: true
-  hasSpilledSGPRs:     true
-  scratchRSrcReg:  '$sgpr96_sgpr97_sgpr98_sgpr99'
-  stackPtrOffsetReg: '$sgpr32'
-
-stack:
-  - { id: 0, type: spill-slot, size: 8, alignment: 4, stack-id: sgpr-spill }
-
-body:             |
-  bb.0:
-    liveins: $sgpr4
-
-    ; CHECK-LABEL: name: sgpr_spill_s64_undef_high32
-    ; CHECK: liveins: $sgpr4, $vgpr0
-    ; CHECK: $vgpr0 = V_WRITELANE_B32_gfx6_gfx7 $sgpr4, 0, undef $vgpr0, implicit-def $sgpr4_sgpr5
-    ; CHECK: $vgpr0 = V_WRITELANE_B32_gfx6_gfx7 $sgpr5, 1, $vgpr0
-    SI_SPILL_S64_SAVE renamable $sgpr4_sgpr5, %stack.0, implicit $exec, implicit $sgpr96_sgpr97_sgpr98_sgpr99, implicit $sgpr32 :: (store 8 into %stack.0, align 4, addrspace 5)
-
-...
-
----
-name:  sgpr_spill_s64_undef_low32
-tracksRegLiveness: true
-machineFunctionInfo:
-  isEntryFunction: true
-  hasSpilledSGPRs:     true
-  scratchRSrcReg:  '$sgpr96_sgpr97_sgpr98_sgpr99'
-  stackPtrOffsetReg: '$sgpr32'
-
-stack:
-  - { id: 0, type: spill-slot, size: 8, alignment: 4, stack-id: sgpr-spill }
-
-body:             |
-  bb.0:
-    liveins: $sgpr5
-
-    ; CHECK-LABEL: name: sgpr_spill_s64_undef_low32
-    ; CHECK: liveins: $sgpr5, $vgpr0
-    ; CHECK: $vgpr0 = V_WRITELANE_B32_gfx6_gfx7 $sgpr4, 0, undef $vgpr0, implicit-def $sgpr4_sgpr5
-    ; CHECK: $vgpr0 = V_WRITELANE_B32_gfx6_gfx7 $sgpr5, 1, $vgpr0
-    SI_SPILL_S64_SAVE renamable $sgpr4_sgpr5, %stack.0, implicit $exec, implicit $sgpr96_sgpr97_sgpr98_sgpr99, implicit $sgpr32 :: (store 8 into %stack.0, align 4, addrspace 5)
-
-...