From 9caf12e8495c1106dd3d1079892ce4f39f91b7d2 Mon Sep 17 00:00:00 2001 From: Dmitri Gribenko Date: Fri, 20 Dec 2019 14:34:56 +0100 Subject: [PATCH 01/10] Use isa instead of dyn_cast --- clang/lib/Tooling/Syntax/Mutations.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/clang/lib/Tooling/Syntax/Mutations.cpp b/clang/lib/Tooling/Syntax/Mutations.cpp index a34598c99f7f01..7278aff5f18b10 100644 --- a/clang/lib/Tooling/Syntax/Mutations.cpp +++ b/clang/lib/Tooling/Syntax/Mutations.cpp @@ -71,7 +71,7 @@ class syntax::MutationsImpl { void syntax::removeStatement(syntax::Arena &A, syntax::Statement *S) { assert(S->canModify()); - if (auto *Parent = llvm::dyn_cast(S->parent())) { + if (isa(S->parent())) { // A child of CompoundStatement can just be safely removed. MutationsImpl::remove(S); return; From 73f423e739bcb9bee7b73f05d4bcd50782013a8c Mon Sep 17 00:00:00 2001 From: Dmitri Gribenko Date: Fri, 20 Dec 2019 14:35:10 +0100 Subject: [PATCH 02/10] Parenthesized a logical expression. This change fixes a warning on the ppc64be buildbot. --- clang/lib/Tooling/Syntax/Tokens.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/clang/lib/Tooling/Syntax/Tokens.cpp b/clang/lib/Tooling/Syntax/Tokens.cpp index 39d6dba99ec313..3df1c064923a14 100644 --- a/clang/lib/Tooling/Syntax/Tokens.cpp +++ b/clang/lib/Tooling/Syntax/Tokens.cpp @@ -67,7 +67,7 @@ FileRange syntax::Token::range(const SourceManager &SM, auto F = First.range(SM); auto L = Last.range(SM); assert(F.file() == L.file() && "tokens from different files"); - assert(F == L || F.endOffset() <= L.beginOffset() && "wrong order of tokens"); + assert((F == L || F.endOffset() <= L.beginOffset()) && "wrong order of tokens"); return FileRange(F.file(), F.beginOffset(), L.endOffset()); } From 5f78b1d648240ba188d08ac1ce62fb7f68d41149 Mon Sep 17 00:00:00 2001 From: Raphael Isemann Date: Fri, 20 Dec 2019 14:18:02 +0100 Subject: [PATCH 03/10] [lldb] Add tests for ClangASTImporter's DeportType and DeportDecl methods --- .../unittests/Symbol/TestClangASTImporter.cpp | 93 ++++++++++++++++--- 1 file changed, 82 insertions(+), 11 deletions(-) diff --git a/lldb/unittests/Symbol/TestClangASTImporter.cpp b/lldb/unittests/Symbol/TestClangASTImporter.cpp index 2a5900c8da5597..11749a4189c394 100644 --- a/lldb/unittests/Symbol/TestClangASTImporter.cpp +++ b/lldb/unittests/Symbol/TestClangASTImporter.cpp @@ -43,6 +43,22 @@ class TestClangASTImporter : public testing::Test { lldb::AccessType::eAccessPublic, name, 0, lldb::LanguageType::eLanguageTypeC); } + + /// Create a record with the given name and a field with the given type + /// and name. + CompilerType createRecordWithField(ClangASTContext &ast, + llvm::StringRef record_name, + CompilerType field_type, + llvm::StringRef field_name) { + CompilerType t = createRecord(ast, record_name); + + ClangASTContext::StartTagDeclarationDefinition(t); + ast.AddFieldToRecordType(t, field_name, field_type, + lldb::AccessType::eAccessPublic, 7); + ClangASTContext::CompleteTagDeclarationDefinition(t); + + return t; + } }; TEST_F(TestClangASTImporter, CanImportInvalidType) { @@ -58,7 +74,9 @@ TEST_F(TestClangASTImporter, ImportInvalidType) { TEST_F(TestClangASTImporter, CopyDeclTagDecl) { // Tests that the ClangASTImporter::CopyDecl can copy TagDecls. std::unique_ptr source_ast = createAST(); - CompilerType source_type = createRecord(*source_ast, "Source"); + CompilerType source_type = createRecordWithField( + *source_ast, "Source", + source_ast->GetBasicType(lldb::BasicType::eBasicTypeChar), "a_field"); clang::TagDecl *source = ClangUtil::GetAsTagDecl(source_type); std::unique_ptr target_ast = createAST(); @@ -72,6 +90,8 @@ TEST_F(TestClangASTImporter, CopyDeclTagDecl) { clang::TagDecl *imported_tag_decl = llvm::cast(imported); EXPECT_EQ(source->getQualifiedNameAsString(), imported_tag_decl->getQualifiedNameAsString()); + // We did a minimal import of the tag decl. + EXPECT_TRUE(imported_tag_decl->hasExternalLexicalStorage()); // Check that origin was set for the imported declaration. ClangASTImporter::DeclOrigin origin = importer.GetDeclOrigin(imported); @@ -83,7 +103,9 @@ TEST_F(TestClangASTImporter, CopyDeclTagDecl) { TEST_F(TestClangASTImporter, CopyTypeTagDecl) { // Tests that the ClangASTImporter::CopyType can copy TagDecls types. std::unique_ptr source_ast = createAST(); - CompilerType source_type = createRecord(*source_ast, "Source"); + CompilerType source_type = createRecordWithField( + *source_ast, "Source", + source_ast->GetBasicType(lldb::BasicType::eBasicTypeChar), "a_field"); clang::TagDecl *source = ClangUtil::GetAsTagDecl(source_type); std::unique_ptr target_ast = createAST(); @@ -96,6 +118,8 @@ TEST_F(TestClangASTImporter, CopyTypeTagDecl) { clang::TagDecl *imported_tag_decl = ClangUtil::GetAsTagDecl(imported); EXPECT_EQ(source->getQualifiedNameAsString(), imported_tag_decl->getQualifiedNameAsString()); + // We did a minimal import of the tag decl. + EXPECT_TRUE(imported_tag_decl->hasExternalLexicalStorage()); // Check that origin was set for the imported declaration. ClangASTImporter::DeclOrigin origin = @@ -105,6 +129,57 @@ TEST_F(TestClangASTImporter, CopyTypeTagDecl) { EXPECT_EQ(origin.decl, source); } +TEST_F(TestClangASTImporter, DeportDeclTagDecl) { + // Tests that the ClangASTImporter::DeportDecl completely copies TagDecls. + std::unique_ptr source_ast = createAST(); + CompilerType source_type = createRecordWithField( + *source_ast, "Source", + source_ast->GetBasicType(lldb::BasicType::eBasicTypeChar), "a_field"); + clang::TagDecl *source = ClangUtil::GetAsTagDecl(source_type); + + std::unique_ptr target_ast = createAST(); + + ClangASTImporter importer; + clang::Decl *imported = importer.DeportDecl( + target_ast->getASTContext(), source_ast->getASTContext(), source); + ASSERT_NE(nullptr, imported); + + // Check that we got the correct decl by just comparing their qualified name. + clang::TagDecl *imported_tag_decl = llvm::cast(imported); + EXPECT_EQ(source->getQualifiedNameAsString(), + imported_tag_decl->getQualifiedNameAsString()); + // The record should be completed as we deported it. + EXPECT_FALSE(imported_tag_decl->hasExternalLexicalStorage()); + + // Deporting doesn't update the origin map. + EXPECT_FALSE(importer.GetDeclOrigin(imported_tag_decl).Valid()); +} + +TEST_F(TestClangASTImporter, DeportTypeTagDecl) { + // Tests that the ClangASTImporter::CopyType can deport TagDecl types. + std::unique_ptr source_ast = createAST(); + CompilerType source_type = createRecordWithField( + *source_ast, "Source", + source_ast->GetBasicType(lldb::BasicType::eBasicTypeChar), "a_field"); + clang::TagDecl *source = ClangUtil::GetAsTagDecl(source_type); + + std::unique_ptr target_ast = createAST(); + + ClangASTImporter importer; + CompilerType imported = importer.DeportType(*target_ast, source_type); + ASSERT_TRUE(imported.IsValid()); + + // Check that we got the correct decl by just comparing their qualified name. + clang::TagDecl *imported_tag_decl = ClangUtil::GetAsTagDecl(imported); + EXPECT_EQ(source->getQualifiedNameAsString(), + imported_tag_decl->getQualifiedNameAsString()); + // The record should be completed as we deported it. + EXPECT_FALSE(imported_tag_decl->hasExternalLexicalStorage()); + + // Deporting doesn't update the origin map. + EXPECT_FALSE(importer.GetDeclOrigin(imported_tag_decl).Valid()); +} + TEST_F(TestClangASTImporter, MetadataPropagation) { // Tests that AST metadata is propagated when copying declarations. @@ -185,13 +260,9 @@ TEST_F(TestClangASTImporter, RecordLayout) { // correctly retrieve them. std::unique_ptr source_ast = createAST(); - CompilerType source_type = createRecord(*source_ast, "Source"); - ClangASTContext::StartTagDeclarationDefinition(source_type); - clang::FieldDecl *field = source_ast->AddFieldToRecordType( - source_type, "a_field", - source_ast->GetBasicType(lldb::BasicType::eBasicTypeChar), - lldb::AccessType::eAccessPublic, 7); - ClangASTContext::CompleteTagDeclarationDefinition(source_type); + CompilerType source_type = createRecordWithField( + *source_ast, "Source", + source_ast->GetBasicType(lldb::BasicType::eBasicTypeChar), "a_field"); clang::TagDecl *source_tag = ClangUtil::GetAsTagDecl(source_type); clang::RecordDecl *source_record = llvm::cast(source_tag); @@ -200,7 +271,7 @@ TEST_F(TestClangASTImporter, RecordLayout) { ClangASTImporter::LayoutInfo layout_info; layout_info.bit_size = 15; layout_info.alignment = 2; - layout_info.field_offsets[field] = 1; + layout_info.field_offsets[*source_record->fields().begin()] = 1; importer.SetRecordLayout(source_record, layout_info); uint64_t bit_size; @@ -214,7 +285,7 @@ TEST_F(TestClangASTImporter, RecordLayout) { EXPECT_EQ(15U, bit_size); EXPECT_EQ(2U, alignment); EXPECT_EQ(1U, field_offsets.size()); - EXPECT_EQ(1U, field_offsets[field]); + EXPECT_EQ(1U, field_offsets[*source_record->fields().begin()]); EXPECT_EQ(0U, base_offsets.size()); EXPECT_EQ(0U, vbase_offsets.size()); } From 59811f454df08924fc35f7e8fb8cb61e8f40e869 Mon Sep 17 00:00:00 2001 From: Sanjay Patel Date: Thu, 19 Dec 2019 17:12:19 -0500 Subject: [PATCH 04/10] [AArch64] add more tests for extract-bitcast-splat; NFC Goes with D71672 - we should be able to handle casting to a wider type as well as casting to a narrower type. --- .../test/CodeGen/AArch64/arm64-neon-2velem.ll | 46 ++++++++++++++++++- 1 file changed, 44 insertions(+), 2 deletions(-) diff --git a/llvm/test/CodeGen/AArch64/arm64-neon-2velem.ll b/llvm/test/CodeGen/AArch64/arm64-neon-2velem.ll index 5eec06f552d131..47d82a174853b4 100644 --- a/llvm/test/CodeGen/AArch64/arm64-neon-2velem.ll +++ b/llvm/test/CodeGen/AArch64/arm64-neon-2velem.ll @@ -1686,8 +1686,8 @@ define <2 x float> @test_vmul_laneq2_f32_bitcast(<2 x float> %a, <2 x double> %v ret <2 x float> %mul } -define <4 x i16> @test_vmul_laneq5_i16_bitcast(<4 x i16> %a, <2 x double> %v) { -; CHECK-LABEL: test_vmul_laneq5_i16_bitcast: +define <4 x i16> @test_vadd_laneq5_i16_bitcast(<4 x i16> %a, <2 x double> %v) { +; CHECK-LABEL: test_vadd_laneq5_i16_bitcast: ; CHECK: // %bb.0: ; CHECK-NEXT: ext v1.16b, v1.16b, v1.16b, #8 ; CHECK-NEXT: dup v1.4h, v1.h[1] @@ -1700,6 +1700,48 @@ define <4 x i16> @test_vmul_laneq5_i16_bitcast(<4 x i16> %a, <2 x double> %v) { ret <4 x i16> %r } +define <4 x i16> @test_vadd_lane2_i16_bitcast_bigger_aligned(<4 x i16> %a, <16 x i8> %v) { +; CHECK-LABEL: test_vadd_lane2_i16_bitcast_bigger_aligned: +; CHECK: // %bb.0: +; CHECK-NEXT: ext v1.8b, v1.8b, v0.8b, #2 +; CHECK-NEXT: dup v1.4h, v1.h[1] +; CHECK-NEXT: add v0.4h, v1.4h, v0.4h +; CHECK-NEXT: ret + %extract = shufflevector <16 x i8> %v, <16 x i8> undef, <8 x i32> + %bc = bitcast <8 x i8> %extract to <4 x i16> + %splat = shufflevector <4 x i16> %bc, <4 x i16> undef, <4 x i32> + %r = add <4 x i16> %splat, %a + ret <4 x i16> %r +} + +define <4 x i16> @test_vadd_lane5_i16_bitcast_bigger_aligned(<4 x i16> %a, <16 x i8> %v) { +; CHECK-LABEL: test_vadd_lane5_i16_bitcast_bigger_aligned: +; CHECK: // %bb.0: +; CHECK-NEXT: ext v1.16b, v1.16b, v1.16b, #8 +; CHECK-NEXT: dup v1.4h, v1.h[1] +; CHECK-NEXT: add v0.4h, v1.4h, v0.4h +; CHECK-NEXT: ret + %extract = shufflevector <16 x i8> %v, <16 x i8> undef, <8 x i32> + %bc = bitcast <8 x i8> %extract to <4 x i16> + %splat = shufflevector <4 x i16> %bc, <4 x i16> undef, <4 x i32> + %r = add <4 x i16> %splat, %a + ret <4 x i16> %r +} + +define <4 x i16> @test_vadd_lane_i16_bitcast_bigger_unaligned(<4 x i16> %a, <16 x i8> %v) { +; CHECK-LABEL: test_vadd_lane_i16_bitcast_bigger_unaligned: +; CHECK: // %bb.0: +; CHECK-NEXT: ext v1.8b, v1.8b, v0.8b, #1 +; CHECK-NEXT: dup v1.4h, v1.h[1] +; CHECK-NEXT: add v0.4h, v1.4h, v0.4h +; CHECK-NEXT: ret + %extract = shufflevector <16 x i8> %v, <16 x i8> undef, <8 x i32> + %bc = bitcast <8 x i8> %extract to <4 x i16> + %splat = shufflevector <4 x i16> %bc, <4 x i16> undef, <4 x i32> + %r = add <4 x i16> %splat, %a + ret <4 x i16> %r +} + define <1 x double> @test_vmul_laneq_f64(<1 x double> %a, <2 x double> %v) { ; CHECK-LABEL: test_vmul_laneq_f64: ; CHECK: // %bb.0: // %entry From 453dc4d7ec5a3c3d8f54fc358bc5673834516d48 Mon Sep 17 00:00:00 2001 From: Tom Weaver Date: Fri, 20 Dec 2019 14:03:34 +0000 Subject: [PATCH 05/10] [OPT-DBG] Teach DbgEntityHistoryCalculator about meta-instructions. The calculator was considering instructions such as KILLs as clobbers of a physical address. This is wrong as meta instructions such as KILLs produce no output in the final program and thus don't clobber or change any physical location's value. As a result they're safe to ignore whilst calculating location list ranges. reviewers: aprantl, vsk diff revision: https://reviews.llvm.org/D70497 fixes: https://bugs.llvm.org/show_bug.cgi?id=38753 --- .../AsmPrinter/DbgEntityHistoryCalculator.cpp | 4 +- llvm/test/DebugInfo/COFF/pieces.ll | 6 +- ...alc_ignores_KILL_instruction_at_return.mir | 76 ++++++++++++++++++ ...gnores_KILL_instruction_still_clobbers.mir | 79 +++++++++++++++++++ llvm/test/DebugInfo/X86/pieces-3.ll | 5 +- 5 files changed, 165 insertions(+), 5 deletions(-) create mode 100644 llvm/test/DebugInfo/X86/dbg_entity_calc_ignores_KILL_instruction_at_return.mir create mode 100644 llvm/test/DebugInfo/X86/dbg_entity_calc_ignores_KILL_instruction_still_clobbers.mir diff --git a/llvm/lib/CodeGen/AsmPrinter/DbgEntityHistoryCalculator.cpp b/llvm/lib/CodeGen/AsmPrinter/DbgEntityHistoryCalculator.cpp index 7f9d6c618ad33f..170fc8b6d49f52 100644 --- a/llvm/lib/CodeGen/AsmPrinter/DbgEntityHistoryCalculator.cpp +++ b/llvm/lib/CodeGen/AsmPrinter/DbgEntityHistoryCalculator.cpp @@ -262,7 +262,9 @@ void llvm::calculateDbgEntityHistory(const MachineFunction *MF, DbgLabels.addInstr(L, MI); } - if (MI.isDebugInstr()) + // Meta Instructions have no output and do not change any values and so + // can be safely ignored. + if (MI.isMetaInstruction()) continue; // Not a DBG_VALUE instruction. It may clobber registers which describe diff --git a/llvm/test/DebugInfo/COFF/pieces.ll b/llvm/test/DebugInfo/COFF/pieces.ll index 70101b5acc6c77..64000301fd8493 100644 --- a/llvm/test/DebugInfo/COFF/pieces.ll +++ b/llvm/test/DebugInfo/COFF/pieces.ll @@ -76,6 +76,7 @@ ; ASM: [[pad_right_tmp:\.Ltmp[0-9]+]]: ; ASM: #DEBUG_VALUE: pad_right:o <- [DW_OP_LLVM_fragment 32 32] $eax ; ASM: retq +; ASM: [[pad_right_end:\.Lfunc_end1]]: ; ASM-LABEL: pad_left: # @pad_left @@ -84,6 +85,7 @@ ; ASM: [[pad_left_tmp:\.Ltmp[0-9]+]]: ; ASM: #DEBUG_VALUE: pad_left:o <- [DW_OP_LLVM_fragment 0 32] $eax ; ASM: retq +; ASM: [[pad_left_end:\.Lfunc_end2]]: ; ASM-LABEL: nested: # @nested @@ -146,7 +148,7 @@ ; ASM: .asciz "pad_right" # Function name ; ASM: .short 4414 # Record kind: S_LOCAL ; ASM: .asciz "o" -; ASM: .cv_def_range [[pad_right_tmp]] [[pad_right_tmp]], subfield_reg, 17, 4 +; ASM: .cv_def_range [[pad_right_tmp]] [[pad_right_end]], subfield_reg, 17, 4 ; OBJ-LABEL: GlobalProcIdSym { ; OBJ: Kind: S_GPROC32_ID (0x1147) @@ -169,7 +171,7 @@ ; ASM: .asciz "pad_left" # Function name ; ASM: .short 4414 # Record kind: S_LOCAL ; ASM: .asciz "o" -; ASM: .cv_def_range [[pad_left_tmp]] [[pad_left_tmp]], subfield_reg, 17, 0 +; ASM: .cv_def_range [[pad_left_tmp]] [[pad_left_end]], subfield_reg, 17, 0 ; OBJ-LABEL: GlobalProcIdSym { ; OBJ: Kind: S_GPROC32_ID (0x1147) diff --git a/llvm/test/DebugInfo/X86/dbg_entity_calc_ignores_KILL_instruction_at_return.mir b/llvm/test/DebugInfo/X86/dbg_entity_calc_ignores_KILL_instruction_at_return.mir new file mode 100644 index 00000000000000..bfc9df5695e88c --- /dev/null +++ b/llvm/test/DebugInfo/X86/dbg_entity_calc_ignores_KILL_instruction_at_return.mir @@ -0,0 +1,76 @@ +--- | + ; RUN: llc %s -start-before=cfi-instr-inserter -filetype=obj -o - | llvm-dwarfdump - | FileCheck %s + + ; Test that KILL instructions no longer terminate the instruction range of a + ; Debug Intrinsic calculated by DbgEntityHistoryCalculator. + + source_filename = ".\\test.cpp" + target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" + target triple = "x86_64-scei-ps4" + + define hidden i32 @main(i32 %arg, i8** nocapture readnone %argv) local_unnamed_addr !dbg !8 { + entry: + call void @llvm.dbg.value(metadata i32 %arg, metadata !19, metadata !DIExpression()), !dbg !22 + call void @llvm.dbg.value(metadata i8** %argv, metadata !20, metadata !DIExpression()), !dbg !22 + %add = shl nsw i32 %arg, 1, !dbg !23 + call void @llvm.dbg.value(metadata i32 %add, metadata !21, metadata !DIExpression()), !dbg !22 + ret i32 %add, !dbg !24 + } + + declare void @llvm.dbg.value(metadata, metadata, metadata) + + + !llvm.dbg.cu = !{!0} + !llvm.module.flags = !{!3, !4, !5, !6} + !llvm.ident = !{!7} + + !0 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus_14, file: !1, producer: "clang version 10.0.0", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2, debugInfoForProfiling: true, nameTableKind: None) + !1 = !DIFile(filename: "test.cpp", directory: "F:\\test") + !2 = !{} + !3 = !{i32 2, !"Dwarf Version", i32 4} + !4 = !{i32 2, !"Debug Info Version", i32 3} + !5 = !{i32 1, !"wchar_size", i32 2} + !6 = !{i32 7, !"PIC Level", i32 2} + !7 = !{!"clang version 10.0.0"} + !8 = distinct !DISubprogram(name: "main", scope: !9, file: !9, line: 1, type: !10, scopeLine: 1, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !18) + !9 = !DIFile(filename: ".\\test.cpp", directory: "F:\\test") + !10 = !DISubroutineType(types: !11) + !11 = !{!12, !13, !14} + !12 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) + !13 = !DIDerivedType(tag: DW_TAG_const_type, baseType: !12) + !14 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !15, size: 64) + !15 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !16, size: 64) + !16 = !DIDerivedType(tag: DW_TAG_const_type, baseType: !17) + !17 = !DIBasicType(name: "char", size: 8, encoding: DW_ATE_signed_char) + !18 = !{!19, !20, !21} + !19 = !DILocalVariable(name: "arg", arg: 1, scope: !8, file: !9, line: 1, type: !13) + !20 = !DILocalVariable(name: "argv", arg: 2, scope: !8, file: !9, line: 1, type: !14) + !21 = !DILocalVariable(name: "result", scope: !8, file: !9, line: 2, type: !12) + !22 = !DILocation(line: 0, scope: !8) + !23 = !DILocation(line: 2, scope: !8) + !24 = !DILocation(line: 3, scope: !8) + +... +--- +name: main +alignment: 16 +tracksRegLiveness: true +liveins: + - { reg: '$edi', virtual-reg: '' } +frameInfo: + maxAlignment: 1 +body: | + bb.0.entry: + liveins: $edi + + renamable $edi = KILL killed $edi, implicit-def $rdi + renamable $eax = LEA64_32r killed renamable $rdi, 1, renamable $rdi, 0, $noreg, debug-location !23 + DBG_VALUE $eax, $noreg, !21, !DIExpression(), debug-location !22 + ; CHECK-LABEL: DW_TAG_variable + ; CHECK: DW_AT_location (0x00000000: + ; CHECK: [0x0000000000000003, 0x0000000000000004): DW_OP_reg0 RAX) + ; CHECK-NEXT: DW_AT_name ("result") + renamable $eax = KILL killed $eax, implicit-def $rax + RETQ killed $eax, debug-location !24 + +... diff --git a/llvm/test/DebugInfo/X86/dbg_entity_calc_ignores_KILL_instruction_still_clobbers.mir b/llvm/test/DebugInfo/X86/dbg_entity_calc_ignores_KILL_instruction_still_clobbers.mir new file mode 100644 index 00000000000000..0f01a51a482f54 --- /dev/null +++ b/llvm/test/DebugInfo/X86/dbg_entity_calc_ignores_KILL_instruction_still_clobbers.mir @@ -0,0 +1,79 @@ +--- | + ; RUN: llc %s -start-before=cfi-instr-inserter -filetype=obj -o - | llvm-dwarfdump - | FileCheck %s + + ; Test that KILL instructions do not interfere with debug entity history + ; liveness ranges. Check that a physical address clobber after KILL still + ; closes a debug entites range. + + source_filename = ".\\test.cpp" + target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" + target triple = "x86_64-scei-ps4" + + define hidden i32 @main(i32 %arg, i8** nocapture readnone %argv) local_unnamed_addr !dbg !8 { + entry: + call void @llvm.dbg.value(metadata i32 %arg, metadata !19, metadata !DIExpression()), !dbg !22 + call void @llvm.dbg.value(metadata i8** %argv, metadata !20, metadata !DIExpression()), !dbg !22 + %add = shl nsw i32 %arg, 1, !dbg !23 + call void @llvm.dbg.value(metadata i32 %add, metadata !21, metadata !DIExpression()), !dbg !22 + ret i32 %add, !dbg !24 + } + + declare void @llvm.dbg.value(metadata, metadata, metadata) + + !llvm.dbg.cu = !{!0} + !llvm.module.flags = !{!3, !4, !5, !6} + !llvm.ident = !{!7} + + !0 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus_14, file: !1, producer: "clang version 10.0.0", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2, debugInfoForProfiling: true, nameTableKind: None) + !1 = !DIFile(filename: "test.cpp", directory: "F:\\test") + !2 = !{} + !3 = !{i32 2, !"Dwarf Version", i32 4} + !4 = !{i32 2, !"Debug Info Version", i32 3} + !5 = !{i32 1, !"wchar_size", i32 2} + !6 = !{i32 7, !"PIC Level", i32 2} + !7 = !{!"clang version 10.0.0"} + !8 = distinct !DISubprogram(name: "main", scope: !9, file: !9, line: 1, type: !10, scopeLine: 1, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !18) + !9 = !DIFile(filename: ".\\test.cpp", directory: "F:\\test") + !10 = !DISubroutineType(types: !11) + !11 = !{!12, !13, !14} + !12 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) + !13 = !DIDerivedType(tag: DW_TAG_const_type, baseType: !12) + !14 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !15, size: 64) + !15 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !16, size: 64) + !16 = !DIDerivedType(tag: DW_TAG_const_type, baseType: !17) + !17 = !DIBasicType(name: "char", size: 8, encoding: DW_ATE_signed_char) + !18 = !{!19, !20, !21} + !19 = !DILocalVariable(name: "arg", arg: 1, scope: !8, file: !9, line: 1, type: !13) + !20 = !DILocalVariable(name: "argv", arg: 2, scope: !8, file: !9, line: 1, type: !14) + !21 = !DILocalVariable(name: "result", scope: !8, file: !9, line: 2, type: !12) + !22 = !DILocation(line: 0, scope: !8) + !23 = !DILocation(line: 2, scope: !8) + !24 = !DILocation(line: 3, scope: !8) + +... +--- +name: main +alignment: 16 +tracksRegLiveness: true +liveins: + - { reg: '$edi', virtual-reg: '' } +frameInfo: + maxAlignment: 1 +body: | + bb.0.entry: + liveins: $edi + + renamable $edi = KILL killed $edi, implicit-def $rdi + renamable $eax = LEA64_32r killed renamable $rdi, 1, renamable $rdi, 0, $noreg, debug-location !23 + DBG_VALUE $eax, $noreg, !21, !DIExpression(), debug-location !22 + ; CHECK-LABEL: DW_TAG_variable + ; CHECK: DW_AT_location (0x00000000: + ; CHECK: [0x0000000000000003, 0x0000000000000007): DW_OP_reg0 RAX) + ; CHECK-NEXT: DW_AT_name ("result") + renamable $eax = KILL killed $eax, implicit-def $rax + $edi = MOV32rr $eax, debug-location !24 + $eax = MOV32rr $eax, debug-location !24 + $edi = MOV32rr $eax, debug-location !24 + RETQ killed $eax, debug-location !24 + +... diff --git a/llvm/test/DebugInfo/X86/pieces-3.ll b/llvm/test/DebugInfo/X86/pieces-3.ll index 167fb37d125678..6fde29ff36e05f 100644 --- a/llvm/test/DebugInfo/X86/pieces-3.ll +++ b/llvm/test/DebugInfo/X86/pieces-3.ll @@ -21,8 +21,9 @@ ; CHECK-NEXT: [0x0000000000000007, 0x0000000000000009): DW_OP_reg5 RDI, DW_OP_piece 0x8 ; CHECK-NEXT: DW_AT_name {{.*}}"outer" ; CHECK: DW_TAG_variable -; CHECK-NEXT: DW_AT_name {{.*}}"i1" -; CHECK-NOT: DW_AT_location +; CHECK-NEXT: DW_AT_location [DW_FORM_data4] (0x00000044 +; CHECK-NEXT: [0x0000000000000007, 0x0000000000000009): DW_OP_reg0 RAX, DW_OP_piece 0x4) +; CHECK-NEXT: "i1" ; ModuleID = '/Volumes/Data/llvm/test/DebugInfo/X86/sroasplit-2.ll' target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128" From b04b92c3a4640417f2074e7e903df8c2b76eadfd Mon Sep 17 00:00:00 2001 From: Pavel Labath Date: Fri, 20 Dec 2019 15:11:49 +0100 Subject: [PATCH 06/10] [lldb/pexpect] Force-set the TERM environment variable In some environments (typically, buildbots), this variable may not be available. This can cause tests to behave differently. Explicitly set the variable to "vt100" to ensure consistent test behavior. It should not matter that we do not inherit the process TERM variable, as the child process runs in a new virtual terminal anyway. --- lldb/packages/Python/lldbsuite/test/lldbpexpect.py | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/lldb/packages/Python/lldbsuite/test/lldbpexpect.py b/lldb/packages/Python/lldbsuite/test/lldbpexpect.py index 13552dca7b9af3..d599bc397622ed 100644 --- a/lldb/packages/Python/lldbsuite/test/lldbpexpect.py +++ b/lldb/packages/Python/lldbsuite/test/lldbpexpect.py @@ -1,6 +1,7 @@ from __future__ import absolute_import # System modules +import os import sys # Third-party modules @@ -29,6 +30,7 @@ def expect_prompt(self): def launch(self, executable=None, extra_args=None, timeout=30, dimensions=None): logfile = getattr(sys.stdout, 'buffer', sys.stdout) if self.TraceOn() else None + args = ['--no-lldbinit', '--no-use-colors'] for cmd in self.setUpCommands(): args += ['-O', cmd] @@ -36,9 +38,13 @@ def launch(self, executable=None, extra_args=None, timeout=30, dimensions=None): args += ['--file', executable] if extra_args is not None: args.extend(extra_args) + + env = dict(os.environ) + env["TERM"]="vt100" + self.child = pexpect.spawn( lldbtest_config.lldbExec, args=args, logfile=logfile, - timeout=timeout, dimensions=dimensions) + timeout=timeout, dimensions=dimensions, env=env) self.expect_prompt() for cmd in self.setUpCommands(): self.child.expect_exact(cmd) From 05c3b36bc9a35a8aa3ddd6a912ddceab90c39b4d Mon Sep 17 00:00:00 2001 From: Pavel Labath Date: Fri, 20 Dec 2019 15:17:16 +0100 Subject: [PATCH 07/10] [lldb] Fix a -Wreturn-type warning on gcc --- lldb/source/Target/ThreadPlanStepRange.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/lldb/source/Target/ThreadPlanStepRange.cpp b/lldb/source/Target/ThreadPlanStepRange.cpp index 1db29652aa8b92..d1c56165da5008 100644 --- a/lldb/source/Target/ThreadPlanStepRange.cpp +++ b/lldb/source/Target/ThreadPlanStepRange.cpp @@ -250,6 +250,7 @@ bool ThreadPlanStepRange::StopOthers() { case lldb::eAllThreads: return false; } + llvm_unreachable("Unhandled run mode!"); } InstructionList *ThreadPlanStepRange::GetInstructionsForAddress( From 6cba90dc4de6427817bad763f018a502a9048f74 Mon Sep 17 00:00:00 2001 From: Paul Walker Date: Thu, 19 Dec 2019 13:34:37 +0000 Subject: [PATCH 08/10] [AArch64][SVE] Correct intrinsics and patterns for logical predicate instructions In general SVE intrinsics are considered predicated and merging with everything else having suitable decoration. For predicated zeroing operations (like the predicate logical instructions) we use the "_z" suffix. After this change all intrinsics use their expected names (i.e. orr instead of or and eor instead of xor). I've removed intrinsics and patterns for condition code setting instructions as that data is not returned as part of the intrinsic. The expectation is to ask for a cc flag explicitly. For example: a = and_z(pg, p1, p2) cc = ptest_(pg, a) With the code generator expected to use "s" variants of instructions when available. Differential Revision: https://reviews.llvm.org/D71715 --- llvm/include/llvm/IR/IntrinsicsAArch64.td | 31 +- .../lib/Target/AArch64/AArch64SVEInstrInfo.td | 34 +- llvm/test/CodeGen/AArch64/sve-int-log-pred.ll | 53 ++- llvm/test/CodeGen/AArch64/sve-int-log.ll | 42 -- llvm/test/CodeGen/AArch64/sve-pred-log.ll | 371 +++--------------- 5 files changed, 109 insertions(+), 422 deletions(-) diff --git a/llvm/include/llvm/IR/IntrinsicsAArch64.td b/llvm/include/llvm/IR/IntrinsicsAArch64.td index bfd28ee0b9d369..c12b69633b3519 100644 --- a/llvm/include/llvm/IR/IntrinsicsAArch64.td +++ b/llvm/include/llvm/IR/IntrinsicsAArch64.td @@ -1397,28 +1397,14 @@ def int_aarch64_sve_zip2 : AdvSIMD_2VectorArg_Intrinsic; // Logical operations // +def int_aarch64_sve_and : AdvSIMD_Pred2VectorArg_Intrinsic; +def int_aarch64_sve_bic : AdvSIMD_Pred2VectorArg_Intrinsic; def int_aarch64_sve_cnot : AdvSIMD_Merged1VectorArg_Intrinsic; +def int_aarch64_sve_eor : AdvSIMD_Pred2VectorArg_Intrinsic; def int_aarch64_sve_not : AdvSIMD_Merged1VectorArg_Intrinsic; +def int_aarch64_sve_orr : AdvSIMD_Pred2VectorArg_Intrinsic; -def int_aarch64_sve_and : AdvSIMD_Pred2VectorArg_Intrinsic; -def int_aarch64_sve_or : AdvSIMD_Pred2VectorArg_Intrinsic; -def int_aarch64_sve_xor : AdvSIMD_Pred2VectorArg_Intrinsic; -def int_aarch64_sve_bic_base : AdvSIMD_2VectorArg_Intrinsic; -def int_aarch64_sve_bic : AdvSIMD_Pred2VectorArg_Intrinsic; - -def int_aarch64_sve_eor : AdvSIMD_Pred2VectorArg_Intrinsic; -def int_aarch64_sve_ands : AdvSIMD_Pred2VectorArg_Intrinsic; -def int_aarch64_sve_bics : AdvSIMD_Pred2VectorArg_Intrinsic; -def int_aarch64_sve_eors : AdvSIMD_Pred2VectorArg_Intrinsic; -def int_aarch64_sve_orr : AdvSIMD_Pred2VectorArg_Intrinsic; -def int_aarch64_sve_orn : AdvSIMD_Pred2VectorArg_Intrinsic; -def int_aarch64_sve_nor : AdvSIMD_Pred2VectorArg_Intrinsic; -def int_aarch64_sve_nand : AdvSIMD_Pred2VectorArg_Intrinsic; -def int_aarch64_sve_orrs : AdvSIMD_Pred2VectorArg_Intrinsic; -def int_aarch64_sve_orns : AdvSIMD_Pred2VectorArg_Intrinsic; -def int_aarch64_sve_nors : AdvSIMD_Pred2VectorArg_Intrinsic; -def int_aarch64_sve_nands : AdvSIMD_Pred2VectorArg_Intrinsic; - +// TODO: Deprecated and will be replaced by isel patterns. def int_aarch64_sve_orr_imm : AdvSIMD_1VectorArg_Imm64_Intrinsic; def int_aarch64_sve_eor_imm : AdvSIMD_1VectorArg_Imm64_Intrinsic; def int_aarch64_sve_and_imm : AdvSIMD_1VectorArg_Imm64_Intrinsic; @@ -1578,6 +1564,13 @@ def int_aarch64_sve_ptrue : AdvSIMD_SVE_PTRUE_Intrinsic; // Predicate operations // +def int_aarch64_sve_and_z : AdvSIMD_Pred2VectorArg_Intrinsic; +def int_aarch64_sve_bic_z : AdvSIMD_Pred2VectorArg_Intrinsic; +def int_aarch64_sve_eor_z : AdvSIMD_Pred2VectorArg_Intrinsic; +def int_aarch64_sve_nand_z : AdvSIMD_Pred2VectorArg_Intrinsic; +def int_aarch64_sve_nor_z : AdvSIMD_Pred2VectorArg_Intrinsic; +def int_aarch64_sve_orn_z : AdvSIMD_Pred2VectorArg_Intrinsic; +def int_aarch64_sve_orr_z : AdvSIMD_Pred2VectorArg_Intrinsic; def int_aarch64_sve_pfirst : AdvSIMD_Pred1VectorArg_Intrinsic; def int_aarch64_sve_pnext : AdvSIMD_Pred1VectorArg_Intrinsic; def int_aarch64_sve_punpkhi : AdvSIMD_SVE_PUNPKHI_Intrinsic; diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td index 28cb5e7952d340..eae136f8a5d26e 100644 --- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td @@ -91,14 +91,14 @@ let Predicates = [HasSVE] in { defm AND_ZZZ : sve_int_bin_cons_log<0b00, "and", and>; defm ORR_ZZZ : sve_int_bin_cons_log<0b01, "orr", or>; defm EOR_ZZZ : sve_int_bin_cons_log<0b10, "eor", xor>; - defm BIC_ZZZ : sve_int_bin_cons_log<0b11, "bic", int_aarch64_sve_bic_base>; + defm BIC_ZZZ : sve_int_bin_cons_log<0b11, "bic", null_frag>; defm ADD_ZPmZ : sve_int_bin_pred_arit_0<0b000, "add", int_aarch64_sve_add>; defm SUB_ZPmZ : sve_int_bin_pred_arit_0<0b001, "sub", int_aarch64_sve_sub>; defm SUBR_ZPmZ : sve_int_bin_pred_arit_0<0b011, "subr", int_aarch64_sve_subr>; - defm ORR_ZPmZ : sve_int_bin_pred_log<0b000, "orr", int_aarch64_sve_or>; - defm EOR_ZPmZ : sve_int_bin_pred_log<0b001, "eor", int_aarch64_sve_xor>; + defm ORR_ZPmZ : sve_int_bin_pred_log<0b000, "orr", int_aarch64_sve_orr>; + defm EOR_ZPmZ : sve_int_bin_pred_log<0b001, "eor", int_aarch64_sve_eor>; defm AND_ZPmZ : sve_int_bin_pred_log<0b010, "and", int_aarch64_sve_and>; defm BIC_ZPmZ : sve_int_bin_pred_log<0b011, "bic", int_aarch64_sve_bic>; @@ -307,21 +307,21 @@ let Predicates = [HasSVE] in { defm PFIRST : sve_int_pfirst<0b00000, "pfirst", int_aarch64_sve_pfirst>; defm PNEXT : sve_int_pnext<0b00110, "pnext", int_aarch64_sve_pnext>; - defm AND_PPzPP : sve_int_pred_log<0b0000, "and", int_aarch64_sve_and>; - defm BIC_PPzPP : sve_int_pred_log<0b0001, "bic", int_aarch64_sve_bic>; - defm EOR_PPzPP : sve_int_pred_log<0b0010, "eor", int_aarch64_sve_eor>; + defm AND_PPzPP : sve_int_pred_log<0b0000, "and", int_aarch64_sve_and_z>; + defm BIC_PPzPP : sve_int_pred_log<0b0001, "bic", int_aarch64_sve_bic_z>; + defm EOR_PPzPP : sve_int_pred_log<0b0010, "eor", int_aarch64_sve_eor_z>; defm SEL_PPPP : sve_int_pred_log<0b0011, "sel", vselect>; - defm ANDS_PPzPP : sve_int_pred_log<0b0100, "ands", int_aarch64_sve_ands>; - defm BICS_PPzPP : sve_int_pred_log<0b0101, "bics", int_aarch64_sve_bics>; - defm EORS_PPzPP : sve_int_pred_log<0b0110, "eors", int_aarch64_sve_eors>; - defm ORR_PPzPP : sve_int_pred_log<0b1000, "orr", int_aarch64_sve_orr>; - defm ORN_PPzPP : sve_int_pred_log<0b1001, "orn", int_aarch64_sve_orn>; - defm NOR_PPzPP : sve_int_pred_log<0b1010, "nor", int_aarch64_sve_nor>; - defm NAND_PPzPP : sve_int_pred_log<0b1011, "nand", int_aarch64_sve_nand>; - defm ORRS_PPzPP : sve_int_pred_log<0b1100, "orrs", int_aarch64_sve_orrs>; - defm ORNS_PPzPP : sve_int_pred_log<0b1101, "orns", int_aarch64_sve_orns>; - defm NORS_PPzPP : sve_int_pred_log<0b1110, "nors", int_aarch64_sve_nors>; - defm NANDS_PPzPP : sve_int_pred_log<0b1111, "nands", int_aarch64_sve_nands>; + defm ANDS_PPzPP : sve_int_pred_log<0b0100, "ands", null_frag>; + defm BICS_PPzPP : sve_int_pred_log<0b0101, "bics", null_frag>; + defm EORS_PPzPP : sve_int_pred_log<0b0110, "eors", null_frag>; + defm ORR_PPzPP : sve_int_pred_log<0b1000, "orr", int_aarch64_sve_orr_z>; + defm ORN_PPzPP : sve_int_pred_log<0b1001, "orn", int_aarch64_sve_orn_z>; + defm NOR_PPzPP : sve_int_pred_log<0b1010, "nor", int_aarch64_sve_nor_z>; + defm NAND_PPzPP : sve_int_pred_log<0b1011, "nand", int_aarch64_sve_nand_z>; + defm ORRS_PPzPP : sve_int_pred_log<0b1100, "orrs", null_frag>; + defm ORNS_PPzPP : sve_int_pred_log<0b1101, "orns", null_frag>; + defm NORS_PPzPP : sve_int_pred_log<0b1110, "nors", null_frag>; + defm NANDS_PPzPP : sve_int_pred_log<0b1111, "nands", null_frag>; defm CLASTA_RPZ : sve_int_perm_clast_rz<0, "clasta", AArch64clasta_n>; defm CLASTB_RPZ : sve_int_perm_clast_rz<1, "clastb", AArch64clastb_n>; diff --git a/llvm/test/CodeGen/AArch64/sve-int-log-pred.ll b/llvm/test/CodeGen/AArch64/sve-int-log-pred.ll index ad6dc9c2d23a63..fc158d755e7341 100644 --- a/llvm/test/CodeGen/AArch64/sve-int-log-pred.ll +++ b/llvm/test/CodeGen/AArch64/sve-int-log-pred.ll @@ -5,8 +5,8 @@ define @and_pred_i8( %pg, @llvm.aarch64.sve.and.nxv2i8( %pg, - %a, - %b) + %a, + %b) ret %out } @@ -20,7 +20,6 @@ define @and_pred_i16( %pg, %out } - define @and_pred_i32( %pg, %a, %b) { ; CHECK-LABEL: and_pred_i32: ; CHECK: and z0.s, p0/m, z0.s, z1.s @@ -41,14 +40,13 @@ define @and_pred_i64( %pg, %out } - define @or_pred_i8( %pg, %a, %b) { ; CHECK-LABEL: or_pred_i8: ; CHECK: orr z0.b, p0/m, z0.b, z1.b ; CHECK-NEXT: ret - %out = call @llvm.aarch64.sve.or.nxv2i8( %pg, - %a, - %b) + %out = call @llvm.aarch64.sve.orr.nxv2i8( %pg, + %a, + %b) ret %out } @@ -56,18 +54,17 @@ define @or_pred_i16( %pg, ; CHECK-LABEL: or_pred_i16: ; CHECK: orr z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: ret - %out = call @llvm.aarch64.sve.or.nxv2i16( %pg, + %out = call @llvm.aarch64.sve.orr.nxv2i16( %pg, %a, %b) ret %out } - define @or_pred_i32( %pg, %a, %b) { ; CHECK-LABEL: or_pred_i32: ; CHECK: orr z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: ret - %out = call @llvm.aarch64.sve.or.nxv2i32( %pg, + %out = call @llvm.aarch64.sve.orr.nxv2i32( %pg, %a, %b) ret %out @@ -77,20 +74,19 @@ define @or_pred_i64( %pg, ; CHECK-LABEL: or_pred_i64: ; CHECK: orr z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: ret - %out = call @llvm.aarch64.sve.or.nxv2i64( %pg, + %out = call @llvm.aarch64.sve.orr.nxv2i64( %pg, %a, %b) ret %out } - define @xor_pred_i8( %pg, %a, %b) { ; CHECK-LABEL: xor_pred_i8: ; CHECK: eor z0.b, p0/m, z0.b, z1.b ; CHECK-NEXT: ret - %out = call @llvm.aarch64.sve.xor.nxv2i8( %pg, - %a, - %b) + %out = call @llvm.aarch64.sve.eor.nxv2i8( %pg, + %a, + %b) ret %out } @@ -98,18 +94,17 @@ define @xor_pred_i16( %pg, @llvm.aarch64.sve.xor.nxv2i16( %pg, + %out = call @llvm.aarch64.sve.eor.nxv2i16( %pg, %a, %b) ret %out } - define @xor_pred_i32( %pg, %a, %b) { ; CHECK-LABEL: xor_pred_i32: ; CHECK: eor z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: ret - %out = call @llvm.aarch64.sve.xor.nxv2i32( %pg, + %out = call @llvm.aarch64.sve.eor.nxv2i32( %pg, %a, %b) ret %out @@ -119,7 +114,7 @@ define @xor_pred_i64( %pg, @llvm.aarch64.sve.xor.nxv2i64( %pg, + %out = call @llvm.aarch64.sve.eor.nxv2i64( %pg, %a, %b) ret %out @@ -130,8 +125,8 @@ define @bic_pred_i8( %pg, @llvm.aarch64.sve.bic.nxv2i8( %pg, - %a, - %b) + %a, + %b) ret %out } @@ -170,14 +165,14 @@ declare @llvm.aarch64.sve.and.nxv2i8(, @llvm.aarch64.sve.and.nxv2i16(,,) declare @llvm.aarch64.sve.and.nxv2i32(,,) declare @llvm.aarch64.sve.and.nxv2i64(,,) -declare @llvm.aarch64.sve.or.nxv2i8(,,) -declare @llvm.aarch64.sve.or.nxv2i16(,,) -declare @llvm.aarch64.sve.or.nxv2i32(,,) -declare @llvm.aarch64.sve.or.nxv2i64(,,) -declare @llvm.aarch64.sve.xor.nxv2i8(,,) -declare @llvm.aarch64.sve.xor.nxv2i16(,,) -declare @llvm.aarch64.sve.xor.nxv2i32(,,) -declare @llvm.aarch64.sve.xor.nxv2i64(,,) +declare @llvm.aarch64.sve.orr.nxv2i8(,,) +declare @llvm.aarch64.sve.orr.nxv2i16(,,) +declare @llvm.aarch64.sve.orr.nxv2i32(,,) +declare @llvm.aarch64.sve.orr.nxv2i64(,,) +declare @llvm.aarch64.sve.eor.nxv2i8(,,) +declare @llvm.aarch64.sve.eor.nxv2i16(,,) +declare @llvm.aarch64.sve.eor.nxv2i32(,,) +declare @llvm.aarch64.sve.eor.nxv2i64(,,) declare @llvm.aarch64.sve.bic.nxv2i8(,,) declare @llvm.aarch64.sve.bic.nxv2i16(,,) declare @llvm.aarch64.sve.bic.nxv2i32(,,) diff --git a/llvm/test/CodeGen/AArch64/sve-int-log.ll b/llvm/test/CodeGen/AArch64/sve-int-log.ll index 3c45d0511f7a8b..2e958e79286e1e 100644 --- a/llvm/test/CodeGen/AArch64/sve-int-log.ll +++ b/llvm/test/CodeGen/AArch64/sve-int-log.ll @@ -94,45 +94,3 @@ define @xor_b( %a, %b) { %res = xor %a, %b ret %res } - -define @bic_d( %a, %b) { -; CHECK-LABEL: bic_d -; CHECK: bic z0.d, z0.d, z1.d -; CHECK-NEXT: ret - %res = call @llvm.aarch64.sve.bic.base.nxv2i64( %a, - %b) - ret %res -} - -define @bic_s( %a, %b) { -; CHECK-LABEL: bic_s -; CHECK: bic z0.d, z0.d, z1.d -; CHECK-NEXT: ret - %res = call @llvm.aarch64.sve.bic.base.nxv4i32( %a, - %b) - ret %res -} - -define @bic_h( %a, %b) { -; CHECK-LABEL: bic_h -; CHECK: bic z0.d, z0.d, z1.d -; CHECK-NEXT: ret - %res = call @llvm.aarch64.sve.bic.base.nxv8i16( %a, - %b) - - ret %res -} - -define @bic_b( %a, %b) { -; CHECK-LABEL: bic_b -; CHECK: bic z0.d, z0.d, z1.d -; CHECK-NEXT: ret - %res = call @llvm.aarch64.sve.bic.base.nxv16i8( %a, - %b) - ret %res -} - -declare @llvm.aarch64.sve.bic.base.nxv2i64(, ) -declare @llvm.aarch64.sve.bic.base.nxv4i32(, ) -declare @llvm.aarch64.sve.bic.base.nxv8i16(, ) -declare @llvm.aarch64.sve.bic.base.nxv16i8(, ) diff --git a/llvm/test/CodeGen/AArch64/sve-pred-log.ll b/llvm/test/CodeGen/AArch64/sve-pred-log.ll index 772e3f43b7c3d7..7116ccf8acfad3 100644 --- a/llvm/test/CodeGen/AArch64/sve-pred-log.ll +++ b/llvm/test/CodeGen/AArch64/sve-pred-log.ll @@ -36,7 +36,7 @@ define @and_16( %Pg, %Pn ; CHECK-LABEL: and_16: ; CHECK: and p0.b, p0/z, p1.b, p2.b ; CHECK-NEXT: ret - %res = call @llvm.aarch64.sve.and.nxv16i1( %Pg, %Pn, %Pd) + %res = call @llvm.aarch64.sve.and.z.nxv16i1( %Pg, %Pn, %Pd) ret %res; } @@ -44,7 +44,7 @@ define @and_8( %Pg, %Pn, @llvm.aarch64.sve.and.nxv8i1( %Pg, %Pn, %Pd) + %res = call @llvm.aarch64.sve.and.z.nxv8i1( %Pg, %Pn, %Pd) ret %res; } @@ -52,7 +52,7 @@ define @and_4( %Pg, %Pn, @llvm.aarch64.sve.and.nxv4i1( %Pg, %Pn, %Pd) + %res = call @llvm.aarch64.sve.and.z.nxv4i1( %Pg, %Pn, %Pd) ret %res; } @@ -60,16 +60,15 @@ define @and_2( %Pg, %Pn, @llvm.aarch64.sve.and.nxv2i1( %Pg, %Pn, %Pd) + %res = call @llvm.aarch64.sve.and.z.nxv2i1( %Pg, %Pn, %Pd) ret %res; } - define @bic_16( %Pg, %Pn, %Pd) { ; CHECK-LABEL: bic_16: ; CHECK: bic p0.b, p0/z, p1.b, p2.b ; CHECK-NEXT: ret - %res = call @llvm.aarch64.sve.bic.pred.nxv16i1( %Pg, %Pn, %Pd) + %res = call @llvm.aarch64.sve.bic.z.nxv16i1( %Pg, %Pn, %Pd) ret %res; } @@ -77,7 +76,7 @@ define @bic_8( %Pg, %Pn, @llvm.aarch64.sve.bic.pred.nxv8i1( %Pg, %Pn, %Pd) + %res = call @llvm.aarch64.sve.bic.z.nxv8i1( %Pg, %Pn, %Pd) ret %res; } @@ -85,7 +84,7 @@ define @bic_4( %Pg, %Pn, @llvm.aarch64.sve.bic.pred.nxv4i1( %Pg, %Pn, %Pd) + %res = call @llvm.aarch64.sve.bic.z.nxv4i1( %Pg, %Pn, %Pd) ret %res; } @@ -93,7 +92,7 @@ define @bic_2( %Pg, %Pn, @llvm.aarch64.sve.bic.pred.nxv2i1( %Pg, %Pn, %Pd) + %res = call @llvm.aarch64.sve.bic.z.nxv2i1( %Pg, %Pn, %Pd) ret %res; } @@ -101,7 +100,7 @@ define @eor_16( %Pg, %Pn ; CHECK-LABEL: eor_16: ; CHECK: eor p0.b, p0/z, p1.b, p2.b ; CHECK-NEXT: ret - %res = call @llvm.aarch64.sve.eor.nxv16i1( %Pg, %Pn, %Pd) + %res = call @llvm.aarch64.sve.eor.z.nxv16i1( %Pg, %Pn, %Pd) ret %res; } @@ -109,7 +108,7 @@ define @eor_8( %Pg, %Pn, @llvm.aarch64.sve.eor.nxv8i1( %Pg, %Pn, %Pd) + %res = call @llvm.aarch64.sve.eor.z.nxv8i1( %Pg, %Pn, %Pd) ret %res; } @@ -117,7 +116,7 @@ define @eor_4( %Pg, %Pn, @llvm.aarch64.sve.eor.nxv4i1( %Pg, %Pn, %Pd) + %res = call @llvm.aarch64.sve.eor.z.nxv4i1( %Pg, %Pn, %Pd) ret %res; } @@ -125,116 +124,15 @@ define @eor_2( %Pg, %Pn, @llvm.aarch64.sve.eor.nxv2i1( %Pg, %Pn, %Pd) - ret %res; -} - -define @ands_16( %Pg, %Pn, %Pd) { -; CHECK-LABEL: ands_16: -; CHECK: ands p0.b, p0/z, p1.b, p2.b -; CHECK-NEXT: ret - %res = call @llvm.aarch64.sve.ands.nxv16i1( %Pg, %Pn, %Pd) - ret %res; -} - -define @ands_8( %Pg, %Pn, %Pd) { -; CHECK-LABEL: ands_8: -; CHECK: ands p0.b, p0/z, p1.b, p2.b -; CHECK-NEXT: ret - %res = call @llvm.aarch64.sve.ands.nxv8i1( %Pg, %Pn, %Pd) - ret %res; -} - -define @ands_4( %Pg, %Pn, %Pd) { -; CHECK-LABEL: ands_4: -; CHECK: ands p0.b, p0/z, p1.b, p2.b -; CHECK-NEXT: ret - %res = call @llvm.aarch64.sve.ands.nxv4i1( %Pg, %Pn, %Pd) - ret %res; -} - -define @ands_2( %Pg, %Pn, %Pd) { -; CHECK-LABEL: ands_2: -; CHECK: ands p0.b, p0/z, p1.b, p2.b -; CHECK-NEXT: ret - %res = call @llvm.aarch64.sve.ands.nxv2i1( %Pg, %Pn, %Pd) + %res = call @llvm.aarch64.sve.eor.z.nxv2i1( %Pg, %Pn, %Pd) ret %res; } - -define @bics_16( %Pg, %Pn, %Pd) { -; CHECK-LABEL: bics_16: -; CHECK: bics p0.b, p0/z, p1.b, p2.b -; CHECK-NEXT: ret - %res = call @llvm.aarch64.sve.bics.nxv16i1( %Pg, %Pn, %Pd) - ret %res; -} - -define @bics_8( %Pg, %Pn, %Pd) { -; CHECK-LABEL: bics_8: -; CHECK: bics p0.b, p0/z, p1.b, p2.b -; CHECK-NEXT: ret - %res = call @llvm.aarch64.sve.bics.nxv8i1( %Pg, %Pn, %Pd) - ret %res; -} - -define @bics_4( %Pg, %Pn, %Pd) { -; CHECK-LABEL: bics_4: -; CHECK: bics p0.b, p0/z, p1.b, p2.b -; CHECK-NEXT: ret - %res = call @llvm.aarch64.sve.bics.nxv4i1( %Pg, %Pn, %Pd) - ret %res; -} - -define @bics_2( %Pg, %Pn, %Pd) { -; CHECK-LABEL: bics_2: -; CHECK: bics p0.b, p0/z, p1.b, p2.b -; CHECK-NEXT: ret - %res = call @llvm.aarch64.sve.bics.nxv2i1( %Pg, - %Pn, - %Pd) - ret %res; -} - - -define @eors_16( %Pg, %Pn, %Pd) { -; CHECK-LABEL: eors_16: -; CHECK: eors p0.b, p0/z, p1.b, p2.b -; CHECK-NEXT: ret - %res = call @llvm.aarch64.sve.eors.nxv16i1( %Pg, %Pn, %Pd) - ret %res; -} - -define @eors_8( %Pg, %Pn, %Pd) { -; CHECK-LABEL: eors_8: -; CHECK: eors p0.b, p0/z, p1.b, p2.b -; CHECK-NEXT: ret - %res = call @llvm.aarch64.sve.eors.nxv8i1( %Pg, %Pn, %Pd) - ret %res; -} - -define @eors_4( %Pg, %Pn, %Pd) { -; CHECK-LABEL: eors_4: -; CHECK: eors p0.b, p0/z, p1.b, p2.b -; CHECK-NEXT: ret - %res = call @llvm.aarch64.sve.eors.nxv4i1( %Pg, %Pn, %Pd) - ret %res; -} - -define @eors_2( %Pg, %Pn, %Pd) { -; CHECK-LABEL: eors_2: -; CHECK: eors p0.b, p0/z, p1.b, p2.b -; CHECK-NEXT: ret - %res = call @llvm.aarch64.sve.eors.nxv2i1( %Pg, %Pn, %Pd) - ret %res; -} - - define @orr_16( %Pg, %Pn, %Pd) { ; CHECK-LABEL: orr_16: ; CHECK: orr p0.b, p0/z, p1.b, p2.b ; CHECK-NEXT: ret - %res = call @llvm.aarch64.sve.orr.nxv16i1( %Pg, %Pn, %Pd) + %res = call @llvm.aarch64.sve.orr.z.nxv16i1( %Pg, %Pn, %Pd) ret %res; } @@ -242,7 +140,7 @@ define @orr_8( %Pg, %Pn, @llvm.aarch64.sve.orr.nxv8i1( %Pg, %Pn, %Pd) + %res = call @llvm.aarch64.sve.orr.z.nxv8i1( %Pg, %Pn, %Pd) ret %res; } @@ -250,7 +148,7 @@ define @orr_4( %Pg, %Pn, @llvm.aarch64.sve.orr.nxv4i1( %Pg, %Pn, %Pd) + %res = call @llvm.aarch64.sve.orr.z.nxv4i1( %Pg, %Pn, %Pd) ret %res; } @@ -258,16 +156,15 @@ define @orr_2( %Pg, %Pn, @llvm.aarch64.sve.orr.nxv2i1( %Pg, %Pn, %Pd) + %res = call @llvm.aarch64.sve.orr.z.nxv2i1( %Pg, %Pn, %Pd) ret %res; } - define @orn_16( %Pg, %Pn, %Pd) { ; CHECK-LABEL: orn_16: ; CHECK: orn p0.b, p0/z, p1.b, p2.b ; CHECK-NEXT: ret - %res = call @llvm.aarch64.sve.orn.nxv16i1( %Pg, %Pn, %Pd) + %res = call @llvm.aarch64.sve.orn.z.nxv16i1( %Pg, %Pn, %Pd) ret %res; } @@ -275,7 +172,7 @@ define @orn_8( %Pg, %Pn, @llvm.aarch64.sve.orn.nxv8i1( %Pg, %Pn, %Pd) + %res = call @llvm.aarch64.sve.orn.z.nxv8i1( %Pg, %Pn, %Pd) ret %res; } @@ -283,7 +180,7 @@ define @orn_4( %Pg, %Pn, @llvm.aarch64.sve.orn.nxv4i1( %Pg, %Pn, %Pd) + %res = call @llvm.aarch64.sve.orn.z.nxv4i1( %Pg, %Pn, %Pd) ret %res; } @@ -291,7 +188,7 @@ define @orn_2( %Pg, %Pn, @llvm.aarch64.sve.orn.nxv2i1( %Pg, %Pn, %Pd) + %res = call @llvm.aarch64.sve.orn.z.nxv2i1( %Pg, %Pn, %Pd) ret %res; } @@ -299,7 +196,7 @@ define @nor_16( %Pg, %Pn ; CHECK-LABEL: nor_16: ; CHECK: nor p0.b, p0/z, p1.b, p2.b ; CHECK-NEXT: ret - %res = call @llvm.aarch64.sve.nor.nxv16i1( %Pg, %Pn, %Pd) + %res = call @llvm.aarch64.sve.nor.z.nxv16i1( %Pg, %Pn, %Pd) ret %res; } @@ -307,7 +204,7 @@ define @nor_8( %Pg, %Pn, @llvm.aarch64.sve.nor.nxv8i1( %Pg, %Pn, %Pd) + %res = call @llvm.aarch64.sve.nor.z.nxv8i1( %Pg, %Pn, %Pd) ret %res; } @@ -315,7 +212,7 @@ define @nor_4( %Pg, %Pn, @llvm.aarch64.sve.nor.nxv4i1( %Pg, %Pn, %Pd) + %res = call @llvm.aarch64.sve.nor.z.nxv4i1( %Pg, %Pn, %Pd) ret %res; } @@ -323,7 +220,7 @@ define @nor_2( %Pg, %Pn, @llvm.aarch64.sve.nor.nxv2i1( %Pg, %Pn, %Pd) + %res = call @llvm.aarch64.sve.nor.z.nxv2i1( %Pg, %Pn, %Pd) ret %res; } @@ -331,7 +228,7 @@ define @nand_16( %Pg, %P ; CHECK-LABEL: nand_16: ; CHECK: nand p0.b, p0/z, p1.b, p2.b ; CHECK-NEXT: ret - %res = call @llvm.aarch64.sve.nand.nxv16i1( %Pg, %Pn, %Pd) + %res = call @llvm.aarch64.sve.nand.z.nxv16i1( %Pg, %Pn, %Pd) ret %res; } @@ -339,7 +236,7 @@ define @nand_8( %Pg, %Pn, < ; CHECK-LABEL: nand_8: ; CHECK: nand p0.b, p0/z, p1.b, p2.b ; CHECK-NEXT: ret - %res = call @llvm.aarch64.sve.nand.nxv8i1( %Pg, %Pn, %Pd) + %res = call @llvm.aarch64.sve.nand.z.nxv8i1( %Pg, %Pn, %Pd) ret %res; } @@ -347,7 +244,7 @@ define @nand_4( %Pg, %Pn, < ; CHECK-LABEL: nand_4: ; CHECK: nand p0.b, p0/z, p1.b, p2.b ; CHECK-NEXT: ret - %res = call @llvm.aarch64.sve.nand.nxv4i1( %Pg, %Pn, %Pd) + %res = call @llvm.aarch64.sve.nand.z.nxv4i1( %Pg, %Pn, %Pd) ret %res; } @@ -355,191 +252,35 @@ define @nand_2( %Pg, %Pn, < ; CHECK-LABEL: nand_2: ; CHECK: nand p0.b, p0/z, p1.b, p2.b ; CHECK-NEXT: ret - %res = call @llvm.aarch64.sve.nand.nxv2i1( %Pg, %Pn, %Pd) - ret %res; -} - -define @orrs_16( %Pg, %Pn, %Pd) { -; CHECK-LABEL: orrs_16: -; CHECK: orrs p0.b, p0/z, p1.b, p2.b -; CHECK-NEXT: ret - %res = call @llvm.aarch64.sve.orrs.nxv16i1( %Pg, %Pn, %Pd) - ret %res; -} - -define @orrs_8( %Pg, %Pn, %Pd) { -; CHECK-LABEL: orrs_8: -; CHECK: orrs p0.b, p0/z, p1.b, p2.b -; CHECK-NEXT: ret - %res = call @llvm.aarch64.sve.orrs.nxv8i1( %Pg, %Pn, %Pd) - ret %res; -} - -define @orrs_4( %Pg, %Pn, %Pd) { -; CHECK-LABEL: orrs_4: -; CHECK: orrs p0.b, p0/z, p1.b, p2.b -; CHECK-NEXT: ret - %res = call @llvm.aarch64.sve.orrs.nxv4i1( %Pg, %Pn, %Pd) - ret %res; -} - -define @orrs_2( %Pg, %Pn, %Pd) { -; CHECK-LABEL: orrs_2: -; CHECK: orrs p0.b, p0/z, p1.b, p2.b -; CHECK-NEXT: ret - %res = call @llvm.aarch64.sve.orrs.nxv2i1( %Pg, %Pn, %Pd) - ret %res; -} - -define @orns_16( %Pg, %Pn, %Pd) { -; CHECK-LABEL: orns_16: -; CHECK: orns p0.b, p0/z, p1.b, p2.b -; CHECK-NEXT: ret - %res = call @llvm.aarch64.sve.orns.nxv16i1( %Pg, %Pn, %Pd) - ret %res; -} - -define @orns_8( %Pg, %Pn, %Pd) { -; CHECK-LABEL: orns_8: -; CHECK: orns p0.b, p0/z, p1.b, p2.b -; CHECK-NEXT: ret - %res = call @llvm.aarch64.sve.orns.nxv8i1( %Pg, %Pn, %Pd) - ret %res; -} - -define @orns_4( %Pg, %Pn, %Pd) { -; CHECK-LABEL: orns_4: -; CHECK: orns p0.b, p0/z, p1.b, p2.b -; CHECK-NEXT: ret - %res = call @llvm.aarch64.sve.orns.nxv4i1( %Pg, %Pn, %Pd) - ret %res; -} - -define @orns_2( %Pg, %Pn, %Pd) { -; CHECK-LABEL: orns_2: -; CHECK: orns p0.b, p0/z, p1.b, p2.b -; CHECK-NEXT: ret - %res = call @llvm.aarch64.sve.orns.nxv2i1( %Pg, %Pn, %Pd) - ret %res; -} - -define @nors_16( %Pg, %Pn, %Pd) { -; CHECK-LABEL: nors_16: -; CHECK: nors p0.b, p0/z, p1.b, p2.b -; CHECK-NEXT: ret - %res = call @llvm.aarch64.sve.nors.nxv16i1( %Pg, %Pn, %Pd) - ret %res; -} - -define @nors_8( %Pg, %Pn, %Pd) { -; CHECK-LABEL: nors_8: -; CHECK: nors p0.b, p0/z, p1.b, p2.b -; CHECK-NEXT: ret - %res = call @llvm.aarch64.sve.nors.nxv8i1( %Pg, %Pn, %Pd) - ret %res; -} - -define @nors_4( %Pg, %Pn, %Pd) { -; CHECK-LABEL: nors_4: -; CHECK: nors p0.b, p0/z, p1.b, p2.b -; CHECK-NEXT: ret - %res = call @llvm.aarch64.sve.nors.nxv4i1( %Pg, %Pn, %Pd) - ret %res; -} - -define @nors_2( %Pg, %Pn, %Pd) { -; CHECK-LABEL: nors_2: -; CHECK: nors p0.b, p0/z, p1.b, p2.b -; CHECK-NEXT: ret - %res = call @llvm.aarch64.sve.nors.nxv2i1( %Pg, %Pn, %Pd) - ret %res; -} - -define @nands_16( %Pg, %Pn, %Pd) { -; CHECK-LABEL: nands_16: -; CHECK: nands p0.b, p0/z, p1.b, p2.b -; CHECK-NEXT: ret - %res = call @llvm.aarch64.sve.nands.nxv16i1( %Pg, %Pn, %Pd) - ret %res; -} - -define @nands_8( %Pg, %Pn, %Pd) { -; CHECK-LABEL: nands_8: -; CHECK: nands p0.b, p0/z, p1.b, p2.b -; CHECK-NEXT: ret - %res = call @llvm.aarch64.sve.nands.nxv8i1( %Pg, %Pn, %Pd) - ret %res; -} - -define @nands_4( %Pg, %Pn, %Pd) { -; CHECK-LABEL: nands_4: -; CHECK: nands p0.b, p0/z, p1.b, p2.b -; CHECK-NEXT: ret - %res = call @llvm.aarch64.sve.nands.nxv4i1( %Pg, %Pn, %Pd) - ret %res; -} - -define @nands_2( %Pg, %Pn, %Pd) { -; CHECK-LABEL: nands_2: -; CHECK: nands p0.b, p0/z, p1.b, p2.b -; CHECK-NEXT: ret - %res = call @llvm.aarch64.sve.nands.nxv2i1( %Pg, %Pn, %Pd) + %res = call @llvm.aarch64.sve.nand.z.nxv2i1( %Pg, %Pn, %Pd) ret %res; } -declare @llvm.aarch64.sve.and.nxv16i1(, , ) -declare @llvm.aarch64.sve.and.nxv8i1(, , ) -declare @llvm.aarch64.sve.and.nxv4i1(, , ) -declare @llvm.aarch64.sve.and.nxv2i1(, , ) -declare @llvm.aarch64.sve.bic.pred.nxv16i1(, , ) -declare @llvm.aarch64.sve.bic.pred.nxv8i1(, , ) -declare @llvm.aarch64.sve.bic.pred.nxv4i1(, , ) -declare @llvm.aarch64.sve.bic.pred.nxv2i1(, , ) -declare @llvm.aarch64.sve.eor.nxv16i1(, , ) -declare @llvm.aarch64.sve.eor.nxv8i1(, , ) -declare @llvm.aarch64.sve.eor.nxv4i1(, , ) -declare @llvm.aarch64.sve.eor.nxv2i1(, , ) -declare @llvm.aarch64.sve.ands.nxv16i1(, , ) -declare @llvm.aarch64.sve.ands.nxv8i1(, , ) -declare @llvm.aarch64.sve.ands.nxv4i1(, , ) -declare @llvm.aarch64.sve.ands.nxv2i1(, , ) -declare @llvm.aarch64.sve.bics.nxv16i1(, , ) -declare @llvm.aarch64.sve.bics.nxv8i1(, , ) -declare @llvm.aarch64.sve.bics.nxv4i1(, , ) -declare @llvm.aarch64.sve.bics.nxv2i1(, , ) -declare @llvm.aarch64.sve.eors.nxv16i1(, , ) -declare @llvm.aarch64.sve.eors.nxv8i1(, , ) -declare @llvm.aarch64.sve.eors.nxv4i1(, , ) -declare @llvm.aarch64.sve.eors.nxv2i1(, , ) -declare @llvm.aarch64.sve.orr.nxv16i1(, , ) -declare @llvm.aarch64.sve.orr.nxv8i1(, , ) -declare @llvm.aarch64.sve.orr.nxv4i1(, , ) -declare @llvm.aarch64.sve.orr.nxv2i1(, , ) -declare @llvm.aarch64.sve.orn.nxv16i1(, , ) -declare @llvm.aarch64.sve.orn.nxv8i1(, , ) -declare @llvm.aarch64.sve.orn.nxv4i1(, , ) -declare @llvm.aarch64.sve.orn.nxv2i1(, , ) -declare @llvm.aarch64.sve.nor.nxv16i1(, , ) -declare @llvm.aarch64.sve.nor.nxv8i1(, , ) -declare @llvm.aarch64.sve.nor.nxv4i1(, , ) -declare @llvm.aarch64.sve.nor.nxv2i1(, , ) -declare @llvm.aarch64.sve.nand.nxv16i1(, , ) -declare @llvm.aarch64.sve.nand.nxv8i1(, , ) -declare @llvm.aarch64.sve.nand.nxv4i1(, , ) -declare @llvm.aarch64.sve.nand.nxv2i1(, , ) -declare @llvm.aarch64.sve.orrs.nxv16i1(, , ) -declare @llvm.aarch64.sve.orrs.nxv8i1(, , ) -declare @llvm.aarch64.sve.orrs.nxv4i1(, , ) -declare @llvm.aarch64.sve.orrs.nxv2i1(, , ) -declare @llvm.aarch64.sve.orns.nxv16i1(, , ) -declare @llvm.aarch64.sve.orns.nxv8i1(, , ) -declare @llvm.aarch64.sve.orns.nxv4i1(, , ) -declare @llvm.aarch64.sve.orns.nxv2i1(, , ) -declare @llvm.aarch64.sve.nors.nxv16i1(, , ) -declare @llvm.aarch64.sve.nors.nxv8i1(, , ) -declare @llvm.aarch64.sve.nors.nxv4i1(, , ) -declare @llvm.aarch64.sve.nors.nxv2i1(, , ) -declare @llvm.aarch64.sve.nands.nxv16i1(, , ) -declare @llvm.aarch64.sve.nands.nxv8i1(, , ) -declare @llvm.aarch64.sve.nands.nxv4i1(, , ) -declare @llvm.aarch64.sve.nands.nxv2i1(, , ) +declare @llvm.aarch64.sve.and.z.nxv16i1(, , ) +declare @llvm.aarch64.sve.and.z.nxv8i1(, , ) +declare @llvm.aarch64.sve.and.z.nxv4i1(, , ) +declare @llvm.aarch64.sve.and.z.nxv2i1(, , ) +declare @llvm.aarch64.sve.bic.z.nxv16i1(, , ) +declare @llvm.aarch64.sve.bic.z.nxv8i1(, , ) +declare @llvm.aarch64.sve.bic.z.nxv4i1(, , ) +declare @llvm.aarch64.sve.bic.z.nxv2i1(, , ) +declare @llvm.aarch64.sve.eor.z.nxv16i1(, , ) +declare @llvm.aarch64.sve.eor.z.nxv8i1(, , ) +declare @llvm.aarch64.sve.eor.z.nxv4i1(, , ) +declare @llvm.aarch64.sve.eor.z.nxv2i1(, , ) +declare @llvm.aarch64.sve.orr.z.nxv16i1(, , ) +declare @llvm.aarch64.sve.orr.z.nxv8i1(, , ) +declare @llvm.aarch64.sve.orr.z.nxv4i1(, , ) +declare @llvm.aarch64.sve.orr.z.nxv2i1(, , ) +declare @llvm.aarch64.sve.orn.z.nxv16i1(, , ) +declare @llvm.aarch64.sve.orn.z.nxv8i1(, , ) +declare @llvm.aarch64.sve.orn.z.nxv4i1(, , ) +declare @llvm.aarch64.sve.orn.z.nxv2i1(, , ) +declare @llvm.aarch64.sve.nor.z.nxv16i1(, , ) +declare @llvm.aarch64.sve.nor.z.nxv8i1(, , ) +declare @llvm.aarch64.sve.nor.z.nxv4i1(, , ) +declare @llvm.aarch64.sve.nor.z.nxv2i1(, , ) +declare @llvm.aarch64.sve.nand.z.nxv16i1(, , ) +declare @llvm.aarch64.sve.nand.z.nxv8i1(, , ) +declare @llvm.aarch64.sve.nand.z.nxv4i1(, , ) +declare @llvm.aarch64.sve.nand.z.nxv2i1(, , ) From ede8293d7d9d4623be5a911cc076c1dfd7810b8c Mon Sep 17 00:00:00 2001 From: Ulrich Weigand Date: Fri, 20 Dec 2019 15:31:16 +0100 Subject: [PATCH 09/10] [SystemZ][FPEnv] Enable strict vector FP extends/truncations The back-end currently has special DAGCombine code to detect cases where two floating-point extend or truncate operations can be combined into a single vector operation. This patch extends that support to also handle strict FP operations. Note that currently only the case where both operations have the same input chain are supported. This already suffices to cover the common case where the operations result from scalarizing a non-legal vector type. More general cases can be supported in the future. --- .../Target/SystemZ/SystemZISelLowering.cpp | 68 ++++++++++++++++--- llvm/lib/Target/SystemZ/SystemZISelLowering.h | 4 +- llvm/lib/Target/SystemZ/SystemZInstrVector.td | 2 +- llvm/lib/Target/SystemZ/SystemZOperators.td | 5 ++ .../CodeGen/SystemZ/vec-strict-conv-02.ll | 61 +++++++++++++++++ .../vector-constrained-fp-intrinsics.ll | 21 +++--- 6 files changed, 136 insertions(+), 25 deletions(-) create mode 100644 llvm/test/CodeGen/SystemZ/vec-strict-conv-02.ll diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp index 14e15bad93302d..c73905d3357a5f 100644 --- a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp +++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp @@ -637,7 +637,9 @@ SystemZTargetLowering::SystemZTargetLowering(const TargetMachine &TM, setTargetDAGCombine(ISD::VECTOR_SHUFFLE); setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT); setTargetDAGCombine(ISD::FP_ROUND); + setTargetDAGCombine(ISD::STRICT_FP_ROUND); setTargetDAGCombine(ISD::FP_EXTEND); + setTargetDAGCombine(ISD::STRICT_FP_EXTEND); setTargetDAGCombine(ISD::BSWAP); setTargetDAGCombine(ISD::SDIV); setTargetDAGCombine(ISD::UDIV); @@ -5386,6 +5388,7 @@ const char *SystemZTargetLowering::getTargetNodeName(unsigned Opcode) const { OPCODE(VEXTEND); OPCODE(STRICT_VEXTEND); OPCODE(VROUND); + OPCODE(STRICT_VROUND); OPCODE(VTM); OPCODE(VFAE_CC); OPCODE(VFAEZ_CC); @@ -5908,6 +5911,19 @@ SDValue SystemZTargetLowering::combineJOIN_DWORDS( return SDValue(); } +static SDValue MergeInputChains(SDNode *N1, SDNode *N2) { + SDValue Chain1 = N1->getOperand(0); + SDValue Chain2 = N2->getOperand(0); + + // Trivial case: both nodes take the same chain. + if (Chain1 == Chain2) + return Chain1; + + // FIXME - we could handle more complex cases via TokenFactor, + // assuming we can verify that this would not create a cycle. + return SDValue(); +} + SDValue SystemZTargetLowering::combineFP_ROUND( SDNode *N, DAGCombinerInfo &DCI) const { @@ -5920,8 +5936,9 @@ SDValue SystemZTargetLowering::combineFP_ROUND( // (extract_vector_elt (VROUND X) 2) // // This is a special case since the target doesn't really support v2f32s. + unsigned OpNo = N->isStrictFPOpcode() ? 1 : 0; SelectionDAG &DAG = DCI.DAG; - SDValue Op0 = N->getOperand(0); + SDValue Op0 = N->getOperand(OpNo); if (N->getValueType(0) == MVT::f32 && Op0.hasOneUse() && Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT && @@ -5937,20 +5954,34 @@ SDValue SystemZTargetLowering::combineFP_ROUND( U->getOperand(1).getOpcode() == ISD::Constant && cast(U->getOperand(1))->getZExtValue() == 1) { SDValue OtherRound = SDValue(*U->use_begin(), 0); - if (OtherRound.getOpcode() == ISD::FP_ROUND && - OtherRound.getOperand(0) == SDValue(U, 0) && + if (OtherRound.getOpcode() == N->getOpcode() && + OtherRound.getOperand(OpNo) == SDValue(U, 0) && OtherRound.getValueType() == MVT::f32) { - SDValue VRound = DAG.getNode(SystemZISD::VROUND, SDLoc(N), - MVT::v4f32, Vec); + SDValue VRound, Chain; + if (N->isStrictFPOpcode()) { + Chain = MergeInputChains(N, OtherRound.getNode()); + if (!Chain) + continue; + VRound = DAG.getNode(SystemZISD::STRICT_VROUND, SDLoc(N), + {MVT::v4f32, MVT::Other}, {Chain, Vec}); + Chain = VRound.getValue(1); + } else + VRound = DAG.getNode(SystemZISD::VROUND, SDLoc(N), + MVT::v4f32, Vec); DCI.AddToWorklist(VRound.getNode()); SDValue Extract1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(U), MVT::f32, VRound, DAG.getConstant(2, SDLoc(U), MVT::i32)); DCI.AddToWorklist(Extract1.getNode()); DAG.ReplaceAllUsesOfValueWith(OtherRound, Extract1); + if (Chain) + DAG.ReplaceAllUsesOfValueWith(OtherRound.getValue(1), Chain); SDValue Extract0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op0), MVT::f32, VRound, DAG.getConstant(0, SDLoc(Op0), MVT::i32)); + if (Chain) + return DAG.getNode(ISD::MERGE_VALUES, SDLoc(Op0), + N->getVTList(), Extract0, Chain); return Extract0; } } @@ -5971,8 +6002,9 @@ SDValue SystemZTargetLowering::combineFP_EXTEND( // (extract_vector_elt (VEXTEND X) 1) // // This is a special case since the target doesn't really support v2f32s. + unsigned OpNo = N->isStrictFPOpcode() ? 1 : 0; SelectionDAG &DAG = DCI.DAG; - SDValue Op0 = N->getOperand(0); + SDValue Op0 = N->getOperand(OpNo); if (N->getValueType(0) == MVT::f64 && Op0.hasOneUse() && Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT && @@ -5988,20 +6020,34 @@ SDValue SystemZTargetLowering::combineFP_EXTEND( U->getOperand(1).getOpcode() == ISD::Constant && cast(U->getOperand(1))->getZExtValue() == 2) { SDValue OtherExtend = SDValue(*U->use_begin(), 0); - if (OtherExtend.getOpcode() == ISD::FP_EXTEND && - OtherExtend.getOperand(0) == SDValue(U, 0) && + if (OtherExtend.getOpcode() == N->getOpcode() && + OtherExtend.getOperand(OpNo) == SDValue(U, 0) && OtherExtend.getValueType() == MVT::f64) { - SDValue VExtend = DAG.getNode(SystemZISD::VEXTEND, SDLoc(N), - MVT::v2f64, Vec); + SDValue VExtend, Chain; + if (N->isStrictFPOpcode()) { + Chain = MergeInputChains(N, OtherExtend.getNode()); + if (!Chain) + continue; + VExtend = DAG.getNode(SystemZISD::STRICT_VEXTEND, SDLoc(N), + {MVT::v2f64, MVT::Other}, {Chain, Vec}); + Chain = VExtend.getValue(1); + } else + VExtend = DAG.getNode(SystemZISD::VEXTEND, SDLoc(N), + MVT::v2f64, Vec); DCI.AddToWorklist(VExtend.getNode()); SDValue Extract1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(U), MVT::f64, VExtend, DAG.getConstant(1, SDLoc(U), MVT::i32)); DCI.AddToWorklist(Extract1.getNode()); DAG.ReplaceAllUsesOfValueWith(OtherExtend, Extract1); + if (Chain) + DAG.ReplaceAllUsesOfValueWith(OtherExtend.getValue(1), Chain); SDValue Extract0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op0), MVT::f64, VExtend, DAG.getConstant(0, SDLoc(Op0), MVT::i32)); + if (Chain) + return DAG.getNode(ISD::MERGE_VALUES, SDLoc(Op0), + N->getVTList(), Extract0, Chain); return Extract0; } } @@ -6341,7 +6387,9 @@ SDValue SystemZTargetLowering::PerformDAGCombine(SDNode *N, case ISD::VECTOR_SHUFFLE: return combineVECTOR_SHUFFLE(N, DCI); case ISD::EXTRACT_VECTOR_ELT: return combineEXTRACT_VECTOR_ELT(N, DCI); case SystemZISD::JOIN_DWORDS: return combineJOIN_DWORDS(N, DCI); + case ISD::STRICT_FP_ROUND: case ISD::FP_ROUND: return combineFP_ROUND(N, DCI); + case ISD::STRICT_FP_EXTEND: case ISD::FP_EXTEND: return combineFP_EXTEND(N, DCI); case ISD::BSWAP: return combineBSWAP(N, DCI); case SystemZISD::BR_CCMASK: return combineBR_CCMASK(N, DCI); diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.h b/llvm/lib/Target/SystemZ/SystemZISelLowering.h index e49c47e379ef60..0ac07a12ab711f 100644 --- a/llvm/lib/Target/SystemZ/SystemZISelLowering.h +++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.h @@ -267,8 +267,8 @@ enum NodeType : unsigned { VEXTEND, STRICT_VEXTEND, // Round the f64 elements of vector operand 0 to f32s and store them in the - // even elements of the result. - VROUND, + // even elements of the result. Regular and strict versions. + VROUND, STRICT_VROUND, // AND the two vector operands together and set CC based on the result. VTM, diff --git a/llvm/lib/Target/SystemZ/SystemZInstrVector.td b/llvm/lib/Target/SystemZ/SystemZInstrVector.td index de6e473dd56bc5..c945122ee577ab 100644 --- a/llvm/lib/Target/SystemZ/SystemZInstrVector.td +++ b/llvm/lib/Target/SystemZ/SystemZInstrVector.td @@ -1156,7 +1156,7 @@ let Predicates = [FeatureVector] in { def VLEDB : TernaryVRRa<"vledb", 0xE7C5, null_frag, v128sb, v128db, 3, 0>; def WLEDB : TernaryVRRa<"wledb", 0xE7C5, null_frag, v32sb, v64db, 3, 8>; } - def : Pat<(v4f32 (z_vround (v2f64 VR128:$src))), (VLEDB VR128:$src, 0, 0)>; + def : Pat<(v4f32 (z_any_vround (v2f64 VR128:$src))), (VLEDB VR128:$src, 0, 0)>; def : FPConversion; let Predicates = [FeatureVectorEnhancements1] in { let Uses = [FPC], mayRaiseFPException = 1 in { diff --git a/llvm/lib/Target/SystemZ/SystemZOperators.td b/llvm/lib/Target/SystemZ/SystemZOperators.td index 0beefc4682a04d..a6a72903e5736e 100644 --- a/llvm/lib/Target/SystemZ/SystemZOperators.td +++ b/llvm/lib/Target/SystemZ/SystemZOperators.td @@ -353,6 +353,8 @@ def z_vextend : SDNode<"SystemZISD::VEXTEND", SDT_ZVecUnaryConv>; def z_strict_vextend : SDNode<"SystemZISD::STRICT_VEXTEND", SDT_ZVecUnaryConv, [SDNPHasChain]>; def z_vround : SDNode<"SystemZISD::VROUND", SDT_ZVecUnaryConv>; +def z_strict_vround : SDNode<"SystemZISD::STRICT_VROUND", + SDT_ZVecUnaryConv, [SDNPHasChain]>; def z_vtm : SDNode<"SystemZISD::VTM", SDT_ZCmp>; def z_vfae_cc : SDNode<"SystemZISD::VFAE_CC", SDT_ZVecTernaryIntCC>; def z_vfaez_cc : SDNode<"SystemZISD::VFAEZ_CC", SDT_ZVecTernaryIntCC>; @@ -741,6 +743,9 @@ def z_any_vfcmphe : PatFrags<(ops node:$lhs, node:$rhs), def z_any_vextend : PatFrags<(ops node:$src), [(z_strict_vextend node:$src), (z_vextend node:$src)]>; +def z_any_vround : PatFrags<(ops node:$src), + [(z_strict_vround node:$src), + (z_vround node:$src)]>; // Create a unary operator that loads from memory and then performs // the given operation on it. diff --git a/llvm/test/CodeGen/SystemZ/vec-strict-conv-02.ll b/llvm/test/CodeGen/SystemZ/vec-strict-conv-02.ll new file mode 100644 index 00000000000000..d4590a57d3edfa --- /dev/null +++ b/llvm/test/CodeGen/SystemZ/vec-strict-conv-02.ll @@ -0,0 +1,61 @@ +; Test conversions between different-sized float elements. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +declare <2 x float> @llvm.experimental.constrained.fptrunc.v2f32.v2f64(<2 x double>, metadata, metadata) +declare float @llvm.experimental.constrained.fptrunc.f32.f64(double, metadata, metadata) + +declare <2 x double> @llvm.experimental.constrained.fpext.v2f64.v2f32(<2 x float>, metadata) +declare double @llvm.experimental.constrained.fpext.f64.f32(float, metadata) + +; Test cases where both elements of a v2f64 are converted to f32s. +define void @f1(<2 x double> %val, <2 x float> *%ptr) { +; CHECK-LABEL: f1: +; CHECK: vledb {{%v[0-9]+}}, %v24, 0, 0 +; CHECK: br %r14 + %res = call <2 x float> @llvm.experimental.constrained.fptrunc.v2f32.v2f64( + <2 x double> %val, + metadata !"round.dynamic", + metadata !"fpexcept.strict") #0 + store <2 x float> %res, <2 x float> *%ptr + ret void +} + +; Test conversion of an f64 in a vector register to an f32. +define float @f2(<2 x double> %vec) #0 { +; CHECK-LABEL: f2: +; CHECK: wledb %f0, %v24, 0, 0 +; CHECK: br %r14 + %scalar = extractelement <2 x double> %vec, i32 0 + %ret = call float @llvm.experimental.constrained.fptrunc.f32.f64( + double %scalar, + metadata !"round.dynamic", + metadata !"fpexcept.strict") #0 + ret float %ret +} + +; Test cases where even elements of a v4f32 are converted to f64s. +define <2 x double> @f3(<4 x float> %vec) { +; CHECK-LABEL: f3: +; CHECK: vldeb %v24, {{%v[0-9]+}} +; CHECK: br %r14 + %shuffle = shufflevector <4 x float> %vec, <4 x float> undef, <2 x i32> + %res = call <2 x double> @llvm.experimental.constrained.fpext.v2f64.v2f32( + <2 x float> %shuffle, + metadata !"fpexcept.strict") #0 + ret <2 x double> %res +} + +; Test conversion of an f32 in a vector register to an f64. +define double @f4(<4 x float> %vec) { +; CHECK-LABEL: f4: +; CHECK: wldeb %f0, %v24 +; CHECK: br %r14 + %scalar = extractelement <4 x float> %vec, i32 0 + %ret = call double @llvm.experimental.constrained.fpext.f64.f32( + float %scalar, + metadata !"fpexcept.strict") #0 + ret double %ret +} + +attributes #0 = { strictfp } diff --git a/llvm/test/CodeGen/SystemZ/vector-constrained-fp-intrinsics.ll b/llvm/test/CodeGen/SystemZ/vector-constrained-fp-intrinsics.ll index e7c4e3a4466eee..348be4a9f14f80 100644 --- a/llvm/test/CodeGen/SystemZ/vector-constrained-fp-intrinsics.ll +++ b/llvm/test/CodeGen/SystemZ/vector-constrained-fp-intrinsics.ll @@ -5417,13 +5417,12 @@ define void @constrained_vector_fptrunc_v3f64(<3 x double>* %src, <3 x float>* % ; SZ13-LABEL: constrained_vector_fptrunc_v3f64: ; SZ13: # %bb.0: # %entry ; SZ13-NEXT: vl %v1, 0(%r2), 4 -; SZ13-NEXT: ledbra %f2, 0, %f1, 0 -; SZ13-NEXT: vrepg %v1, %v1, 1 +; SZ13-NEXT: vledb %v1, %v1, 0, 0 +; SZ13-NEXT: larl %r1, .LCPI97_0 ; SZ13-NEXT: ld %f0, 16(%r2) -; SZ13-NEXT: ledbra %f1, 0, %f1, 0 +; SZ13-NEXT: vl %v2, 0(%r1), 3 +; SZ13-NEXT: vperm %v1, %v1, %v0, %v2 ; SZ13-NEXT: ledbra %f0, 0, %f0, 0 -; SZ13-NEXT: vmrhf %v1, %v2, %v1 -; SZ13-NEXT: vmrhg %v1, %v1, %v1 ; SZ13-NEXT: ste %f0, 8(%r3) ; SZ13-NEXT: vsteg %v1, 0(%r3), 0 ; SZ13-NEXT: br %r14 @@ -5544,13 +5543,11 @@ define void @constrained_vector_fpext_v3f64(<3 x float>* %src, <3 x double>* %de ; SZ13-LABEL: constrained_vector_fpext_v3f64: ; SZ13: # %bb.0: # %entry ; SZ13-NEXT: vl %v0, 0(%r2), 4 -; SZ13-NEXT: vrepf %v2, %v0, 1 -; SZ13-NEXT: ldebr %f1, %f0 -; SZ13-NEXT: ldebr %f2, %f2 -; SZ13-NEXT: vrepf %v0, %v0, 2 -; SZ13-NEXT: ldebr %f0, %f0 -; SZ13-NEXT: vmrhg %v1, %v1, %v2 -; SZ13-NEXT: std %f0, 16(%r3) +; SZ13-NEXT: vrepf %v1, %v0, 1 +; SZ13-NEXT: vldeb %v0, %v0 +; SZ13-NEXT: ldebr %f1, %f1 +; SZ13-NEXT: vmrhg %v1, %v0, %v1 +; SZ13-NEXT: vsteg %v0, 16(%r3), 1 ; SZ13-NEXT: vst %v1, 0(%r3), 4 ; SZ13-NEXT: br %r14 entry: From a9c845395f827055b951532451df1ea50184c21d Mon Sep 17 00:00:00 2001 From: Raphael Isemann Date: Fri, 20 Dec 2019 15:43:53 +0100 Subject: [PATCH 10/10] [lldb] Put the headers in unittests/TestingSupport/ into modules --- lldb/unittests/TestingSupport/module.modulemap | 11 +++++++++++ 1 file changed, 11 insertions(+) create mode 100644 lldb/unittests/TestingSupport/module.modulemap diff --git a/lldb/unittests/TestingSupport/module.modulemap b/lldb/unittests/TestingSupport/module.modulemap new file mode 100644 index 00000000000000..542c0b11c78f39 --- /dev/null +++ b/lldb/unittests/TestingSupport/module.modulemap @@ -0,0 +1,11 @@ + +module lldb_TestingSupport { + requires cplusplus + module TestUtilities { header "TestUtilities.h" export * } + module MockTildeExpressionResolver { header "MockTildeExpressionResolver.h" export * } +} + +module lldb_TestingSupport_Host { + requires cplusplus + module NativeProcessTestUtils { header "Host/NativeProcessTestUtils.h" export * } +}