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RVA23 Profile

Table of Contents
Warning
This document is in the development state.

Do not use for implementations. Assume everything can change.

Introduction

This document captures the current proposal for the RVA23 profile family.

RVA23 is not intended to be a major release of the RISC-V Application Processor Profiles.

RVA23 Profiles

The RVA23 profiles are intended to align implementations of RISC-V 64-bit application processors to allow binary software ecosystems to rely on a a large set of guaranteed extensions and a small number of discoverable coarse-grain options. It is explicitly a non-goal of RVA23 to allow more hardware implementation flexibility by supporting only a minimal set of features and a large number of fine-grain extensions.

Only user-mode (RVA23U64) and supervisor-mode (RVA23S64) profiles are specified in this family.

RVA23U64 Profile

The RVA23U64 profile specifies the ISA features available to user-mode execution environments in 64-bit applications processors. This is the most important profile within the application processor family in terms of the amount of software that targets this profile.

RVA23U64 Mandatory Base

RV64I is the mandatory base ISA for RVA23U64 and is little-endian. As per the unprivileged architecture specification, the ecall instruction causes a requested trap to the execution environment.

RVA23U64 Mandatory Extensions

The following mandatory extensions were present in RVA22U64.

  • M Integer multiplication and division.

  • A Atomic instructions.

  • F Single-precision floating-point instructions.

  • D Double-precision floating-point instructions.

  • C Compressed Instructions.

  • Zicsr CSR instructions. These are implied by presence of F.

  • Zicntr Base counters and timers.

  • Zihpm Hardware performance counters.

  • Ziccif Main memory regions with both the cacheability and coherence PMAs must support instruction fetch, and any instruction fetches of naturally aligned power-of-2 sizes up to min(ILEN,XLEN) (i.e., 32 bits for RVA23) are atomic.

  • Ziccrse Main memory regions with both the cacheability and coherence PMAs must support RsrvEventual.

  • Ziccamoa Main memory regions with both the cacheability and coherence PMAs must support AMOArithmetic.

  • Zicclsm Misaligned loads and stores to main memory regions with both the cacheability and coherence PMAs must be supported.

  • Za64rs Reservation sets are contiguous, naturally aligned, and a maximum of 64 bytes.

  • Zihintpause Pause instruction.

  • Zba Address computation.

  • Zbb Basic bit manipulation.

  • Zbs Single-bit instructions.

  • Zic64b Cache blocks must be 64 bytes in size, naturally aligned in the address space.

  • Zicbom Cache-Block Management Operations.

  • Zicbop Cache-Block Prefetch Operations.

  • Zicboz Cache-Block Zero Operations.

  • Zfhmin Half-Precision Floating-point transfer and convert.

  • Zkt Data-independent execution time.

The following mandatory extensions are new in RVA23U64:

  • V Vector Extension.

Note
 V was optional in RVA22U64.

  • Zvfhmin Vector FP16 conversion instructions.

  • Zvbb Vector bit-manipulation instructions.

  • Zihintntl Non-temporal locality hints.

  • Zicond Conditional Zeroing instructions.

  • Zimop Maybe Operations.

  • Zcmop Compressed Maybe Operations.

  • Zcb Additional 16b compressed instructions.

  • Zfa Additional scalar FP instructions.

  • Zawrs Wait on reservation set.

RVA23U64 Optional Extensions

RVA23U64 has ten profile options (Zvkng, Zvksg, Zacas, Zvbc, Zfh, Zbc, Zvfh, Zfbfmin, Zvfbfmin, Zvfbfwma).

Localized Options

The following localized options are new in RVA23U64:

  • Zvkng Vector Crypto NIST Algorithms including GHASH.

  • Zvksg Vector Crypto ShangMi Algorithms including GHASH.

Note
 The scalar crypto extensions Zkn and Zks that were options in RVA22 are not options in RVA23. The goal is for both hardware and software vendors to move to use vector crypto, as vectors are now mandatory and vector crypto is substantially faster than scalar crypto.
Note
 We have included only the Zvkng/Zvksg options with GHASH to standardize on a higher performance crypto alternative. Zvbc is listed as a development option for use in other algorithms, and will become mandatory. Scalar Zbc is now listed as an expansion option, i.e., it will probably not become mandatory.
Development Options

The following are new development options intended to become mandatory in RVA24U64:

  • Zacas Compare-and-swap

  • Zvbc Vector carryless multiply.

Expansion Options

The following expansion options were also present in RVA22U64:

  • Zfh Scalar Half-Precision Floating-Point (FP16).

The following are new expansion options in RVA23U64:

  • Zbc Scalar carryless multiply.

  • Zvfh Vector half-precision floating-point (FP16).

  • Zfbfmin Scalar BF16 FP conversions.

  • Zvfbfmin Vector BF16 FP conversions.

  • Zvfbfwma Vector BF16 widening mul-add.

Transitory Options

There are no transitory options in RVA23U64.

Note
 Scalar crypto is no longer an option in RVA23U64, though the Zbc extension has now been exposed as an expansion option.

RVA23U64 Recommendations

Implementations are strongly recommended to raise illegal-instruction exceptions on attempts to execute unimplemented opcodes.

RVA23S64 Profile

The RVA23S64 profile specifies the ISA features available to a supervisor-mode execution environment in 64-bit applications processors. RVA23S64 is based on privileged architecture version 1.13.

Note
 Priv 1.13 is still being defined.

RVA23S64 Mandatory Base

RV64I is the mandatory base ISA for RVA23S64 and is little-endian. The ecall instruction operates as per the unprivileged architecture specification. An ecall in user mode causes a contained trap to supervisor mode. An ecall in supervisor mode causes a requested trap to the execution environment.

RVA23S64 Mandatory Extensions

The following unprivileged extensions are mandatory:

  • The RVA23S64 mandatory unprivileged extensions include all the mandatory unprivileged extensions in RVA23U64.

  • Zifencei Instruction-Fetch Fence.

Note
 Zifencei is mandated as it is the only standard way to support instruction-cache coherence in RVA23 application processors. A new instruction-cache coherence mechanism is under development (tentatively named Zjid) which might be added as an option in the future.

The following privileged extensions are mandatory:

  • Ss1p13 Privileged Architecture version 1.13.

Note
 Ss1p13 supersedes Ss1p12 but is not yet ratified.

The following privileged extensions were also mandatory in RVA22S64:

  • Svbare The satp mode Bare must be supported.

  • Sv39 Page-Based 39-bit Virtual-Memory System.

  • Svade Page-fault exceptions are raised when a page is accessed when A bit is clear, or written when D bit is clear.

  • Ssccptr Main memory regions with both the cacheability and coherence PMAs must support hardware page-table reads.

  • Sstvecd stvec.MODE must be capable of holding the value 0 (Direct). When stvec.MODE=Direct, stvec.BASE must be capable of holding any valid four-byte-aligned address.

  • Sstvala stval must be written with the faulting virtual address for load, store, and instruction page-fault, access-fault, and misaligned exceptions, and for breakpoint exceptions other than those caused by execution of the EBREAK or C.EBREAK instructions. For illegal-instruction exceptions, stval must be written with the faulting instruction.

  • Sscounterenw For any hpmcounter that is not read-only zero, the corresponding bit in scounteren must be writable.

  • Svpbmt Page-Based Memory Types

  • Svinval Fine-Grained Address-Translation Cache Invalidation

  • Ssu64xl sstatus.UXL must be capable of holding the value 2 (i.e., UXLEN=64 must be supported).

The following are new mandatory extensions:

  • Svnapot NAPOT Translation Contiguity

Note
 Svnapot was optional in RVA22.

  • Sstc supervisor-mode timer interrupts.

Note
 Sstc was optional in RVA22.

  • Sscofpmf Count Overflow and Mode-Based Filtering.

  • Ssnpm Pointer masking, with senvcfg.PME and henvcfg.PME supporting, at minimum, settings PMLEN=0 and PMLEN=7.

  • H The hypervisor extension.

Note
 The hypervisor was optional in RVA22.
Note
 The following extensions were required when the hypervisor was implemented in RVA22.

  • Ssstateen Supervisor-mode view of the state-enable extension. The supervisor-mode (sstateen0-3) and hypervisor-mode (hstateen0-3) state-enable registers must be provided.

  • Shcounterenw For any hpmcounter that is not read-only zero, the corresponding bit in hcounteren must be writable.

  • Shvstvala vstval must be written in all cases described above for stval.

  • Shtvala htval must be written with the faulting guest physical address in all circumstances permitted by the ISA.

  • Shvstvecd vstvec.MODE must be capable of holding the value 0 (Direct). When vstvec.MODE=Direct, vstvec.BASE must be capable of holding any valid four-byte-aligned address.

  • Shvsatpa All translation modes supported in satp must be supported in vsatp.

  • Shgatpa For each supported virtual memory scheme SvNN supported in satp, the corresponding hgatp SvNNx4 mode must be supported. The hgatp mode Bare must also be supported.

RVA23S64 Optional Extensions

RVA23S64 has ten unprivileged options (Zvkng, Zvksg, Zacas, Zvbc, Zfh, Zbc, Zvfh, Zfbfmin, Zvfbfmin, Zvfbfwma) from RVA23U64, and five privileged options (Sv48, Sv57, Svadu, Zkr, Sdext).

Localized Options

There are no privileged localized options in RVA23S64

Development Options

There are no privileged development options in RVA23S64.

Expansion Options

The following privileged expansion options were present in RVA22S64:

  • Sv48 Page-Based 48-bit Virtual-Memory System.

  • Sv57 Page-Based 57-bit Virtual-Memory System.

  • Zkr Entropy CSR.

The following are new privileged expansion options in RVA23S64

  • Svadu Hardware A/D bit updates.

  • Sdext Debug triggers

Transitory Options

There are no privileged transitory options in RVA23S64.

RVA23S64 Recommendations

  • Implementations are strongly recommended to raise illegal-instruction exceptions when attempting to execute unimplemented opcodes.

Glossary of ISA Extensions

The following unprivileged ISA extensions are defined in Volume I of the RISC-V Instruction Set Manual.

  • M Extension for Integer Multiplication and Division

  • A Extension for Atomic Memory Operations

  • F Extension for Single-Precision Floating-Point

  • D Extension for Double-Precision Floating-Point

  • Q Extension for Quad-Precision Floating-Point

  • C Extension for Compressed Instructions

  • Zifencei Instruction-Fetch Synchronization Extension

  • Zicsr Extension for Control and Status Register Access

  • Zicntr Extension for Basic Performance Counters

  • Zihpm Extension for Hardware Performance Counters

  • Zihintpause Pause Hint Extension

  • Zfh Extension for Half-Precision Floating-Point

  • Zfhmin Minimal Extension for Half-Precision Floating-Point

  • Zfinx Extension for Single-Precision Floating-Point in x-registers

  • Zdinx Extension for Double-Precision Floating-Point in x-registers

  • Zhinx Extension for Half-Precision Floating-Point in x-registers

  • Zhinxmin Minimal Extension for Half-Precision Floating-Point in x-registers

The following privileged ISA extensions are defined in Volume II of the RISC-V Instruction Set Manual.

  • Sv32 Page-based Virtual Memory Extension, 32-bit

  • Sv39 Page-based Virtual Memory Extension, 39-bit

  • Sv48 Page-based Virtual Memory Extension, 48-bit

  • Sv57 Page-based Virtual Memory Extension, 57-bit

  • Svpbmt, Page-Based Memory Types

  • Svnapot, NAPOT Translation Contiguity

  • Svinval, Fine-Grained Address-Translation Cache Invalidation

  • Hypervisor Extension

  • Sm1p11, Machine Architecture v1.11

  • Sm1p12, Machine Architecture v1.12

  • Ss1p11, Supervisor Architecture v1.11

  • Ss1p12, Supervisor Architecture v1.12

  • Ss1p13, Supervisor Architecture v1.13

The following extensions have not yet been incorporated into the RISC-V Instruction Set Manual; the hyperlinks lead to their separate specifications.