From 682fcd60e0004425072bac2da45597a44b7cd324 Mon Sep 17 00:00:00 2001 From: Stephan Date: Sun, 9 Jul 2023 16:01:23 +0200 Subject: [PATCH] add interrupt::wait() --- mips-mcu/Cargo.toml | 4 ++-- mips-mcu/bin/libmipsmcu.a | Bin 1976 -> 2028 bytes mips-mcu/bin/mips_irq.S | 11 +++++++++++ mips-mcu/src/interrupt.rs | 13 +++++++++++++ 4 files changed, 26 insertions(+), 2 deletions(-) diff --git a/mips-mcu/Cargo.toml b/mips-mcu/Cargo.toml index fd3eebb..4b0da74 100644 --- a/mips-mcu/Cargo.toml +++ b/mips-mcu/Cargo.toml @@ -2,8 +2,8 @@ name = "mips-mcu" description = "Low level access to MIPS MCU cores" categories = ["embedded", "hardware-support", "no-std"] -keywords = ["mips", "register", "peripheral"] -version = "0.3.0" +keywords = ["mips", "pic32", "register", "peripheral"] +version = "0.3.1" authors = ["Stephan "] repository = "https://github.com/kiffie/pic32-rs" license = "MIT OR Apache-2.0" diff --git a/mips-mcu/bin/libmipsmcu.a b/mips-mcu/bin/libmipsmcu.a index 11190df1974415e67e06e35d1c713a97ff9bb7ff..37214b2e0a44a230b626fcba38b1d53666707500 100644 GIT binary patch delta 204 zcmdnN|Av2prLl#D0t6&*F)%Q2GB7X(U}Ban3=9Z7*_*|LGdHuKIKDhFvt)7td-%jp z4a^n>=95bqH5qSAp3fL9puoW3#KG`@8E7Vh2s1;&1_lJ4m}5C{{Y7STGt0@(Su`2XOcrDn zo_v7OW3mWS50G5Qq|8_|`7M+9EwybmnWC7m@;$e8%*R<+kA&bfEfS-lqAdm diff --git a/mips-mcu/bin/mips_irq.S b/mips-mcu/bin/mips_irq.S index 1b9bbc3..6b41ad3 100644 --- a/mips-mcu/bin/mips_irq.S +++ b/mips-mcu/bin/mips_irq.S @@ -63,3 +63,14 @@ mips_restore_irq: nop .end mips_restore_irq +# wait for interrupts +# +# void mips_wait(void) +# +.global mips_wait +.ent mips_wait +mips_wait: + wait + jr ra + nop +.end mips_wait diff --git a/mips-mcu/src/interrupt.rs b/mips-mcu/src/interrupt.rs index 5974233..8d3e37b 100644 --- a/mips-mcu/src/interrupt.rs +++ b/mips-mcu/src/interrupt.rs @@ -48,3 +48,16 @@ pub unsafe fn restore(previous_status: IrqSave) { } mips_restore_irq(previous_status) } + +/// Wait for interrupts +/// +/// Use the MIPS `wait` instruction to wait for interrupts and to put the +/// processor in a power saving mode. +pub fn wait() { + extern "C" { + fn mips_wait(); + } + unsafe { + mips_wait(); + } +}