From a72741640e0012a6d8d36acef9aa8a361f85cb88 Mon Sep 17 00:00:00 2001 From: Stephan Date: Sat, 24 Jun 2023 23:00:53 +0200 Subject: [PATCH] add support PIC32MX330/350/370/430/450/470 and config sector for MX5xx/6xx/7xx (#12) --- examples/blinky/32MX270F256B_procdefs.ld | 2 +- examples/usb_serial/32MX270F256B_procdefs.ld | 2 +- pic32-config-sector/Cargo.toml | 2 +- pic32-config-sector/README.md | 3 + pic32-config-sector/create_src.sh | 18 +- pic32-config-sector/src/lib.rs | 9 + pic32-config-sector/src/pic32mx37x.rs | 954 +++++++++ pic32-config-sector/src/pic32mx47x.rs | 1032 ++++++++++ pic32-config-sector/src/pic32mx567.rs | 978 +++++++++ pic32-hal/Cargo.toml | 10 +- pic32-hal/check_all | 20 + pic32-hal/edc2ports.py | 109 + pic32-hal/edc2pps.py | 56 +- pic32-hal/src/clock.rs | 16 +- pic32-hal/src/clock/refclock.rs | 8 +- pic32-hal/src/gpio.rs | 83 +- pic32-hal/src/gpio_tables.rs | 345 ++++ pic32-hal/src/lib.rs | 20 +- pic32-hal/src/pps_tables.rs | 1868 +++++++++++++++++- 19 files changed, 5415 insertions(+), 120 deletions(-) create mode 100644 pic32-config-sector/src/pic32mx37x.rs create mode 100644 pic32-config-sector/src/pic32mx47x.rs create mode 100644 pic32-config-sector/src/pic32mx567.rs create mode 100755 pic32-hal/check_all create mode 100755 pic32-hal/edc2ports.py create mode 100644 pic32-hal/src/gpio_tables.rs diff --git a/examples/blinky/32MX270F256B_procdefs.ld b/examples/blinky/32MX270F256B_procdefs.ld index fb46aa7..858d8aa 100644 --- a/examples/blinky/32MX270F256B_procdefs.ld +++ b/examples/blinky/32MX270F256B_procdefs.ld @@ -1,5 +1,5 @@ /************************************************************************* - * Processor-specific object file for PIC32MX170 and PIC32MX270 + * Processor-specific linker script for PIC32MX170 and PIC32MX270 *************************************************************************/ /************************************************************************* diff --git a/examples/usb_serial/32MX270F256B_procdefs.ld b/examples/usb_serial/32MX270F256B_procdefs.ld index fb46aa7..858d8aa 100644 --- a/examples/usb_serial/32MX270F256B_procdefs.ld +++ b/examples/usb_serial/32MX270F256B_procdefs.ld @@ -1,5 +1,5 @@ /************************************************************************* - * Processor-specific object file for PIC32MX170 and PIC32MX270 + * Processor-specific linker script for PIC32MX170 and PIC32MX270 *************************************************************************/ /************************************************************************* diff --git a/pic32-config-sector/Cargo.toml b/pic32-config-sector/Cargo.toml index 2b68321..579674c 100644 --- a/pic32-config-sector/Cargo.toml +++ b/pic32-config-sector/Cargo.toml @@ -1,7 +1,7 @@ [package] name = "pic32-config-sector" description = "Calculate constant values for PIC32 configuration words" -version = "0.1.2" +version = "0.3.0" authors = ["Stephan "] repository = "https://github.com/kiffie/pic32-rs/tree/master/pic32-config-sector" license = "MIT OR Apache-2.0" diff --git a/pic32-config-sector/README.md b/pic32-config-sector/README.md index 9bc3979..9308ec5 100644 --- a/pic32-config-sector/README.md +++ b/pic32-config-sector/README.md @@ -43,6 +43,9 @@ The following modules exist: | pic32mx2xx | PIC32MX2xx | PIC32MX270F256B.PIC | | pic32mx1x4 | PIC32MX1x4 (XLP) | PIC32MX174F256B.PIC | | pic32mx2x4 | PIC32MX2x4 (XLP) | PIC32MX274F256B.PIC | +| pic32mx37x | PIC32MX330/350/370 | PIC32MX370F512L.PIC | +| pic32mx47x | PIC32MX430/450/470 | PIC32MX470F512L.PIC | +| pic32mx567 | PIC32MX5xx/6xx/7xx | PIC32MX695F512L.PIC | | pic32mzef | PIC32MZEF | PIC32MZ2048EFM144.PIC | The const builder structs are machine generated from XML files distributed by diff --git a/pic32-config-sector/create_src.sh b/pic32-config-sector/create_src.sh index 648a2c4..92f22b0 100755 --- a/pic32-config-sector/create_src.sh +++ b/pic32-config-sector/create_src.sh @@ -11,11 +11,19 @@ build_module() { ./pic2config.py -o "src/$module.rs" $edc || exit -1 } -URLBASE=https://raw.githubusercontent.com/kiffie/pic32-pac/master/pic32mx2xx +URLBASE=https://raw.githubusercontent.com/kiffie/pic32-pac/master +URLBASE_MX567=https://raw.githubusercontent.com/kiffie/pic32-pac/mx567 -build_module $URLBASE/pic32mx1xxfxxxb/PIC32MX170F256B.PIC pic32mx1xx -build_module $URLBASE/pic32mx2xxfxxxb/PIC32MX270F256B.PIC pic32mx2xx -build_module $URLBASE/pic32mx1x4fxxxb/PIC32MX174F256B.PIC pic32mx1x4 -build_module $URLBASE/pic32mx2x4fxxxb/PIC32MX274F256B.PIC pic32mx2x4 +build_module $URLBASE/pic32mx2xx/pic32mx1xxfxxxb/PIC32MX170F256B.PIC pic32mx1xx +build_module $URLBASE/pic32mx2xx/pic32mx2xxfxxxb/PIC32MX270F256B.PIC pic32mx2xx +build_module $URLBASE/pic32mx2xx/pic32mx1x4fxxxb/PIC32MX174F256B.PIC pic32mx1x4 +build_module $URLBASE/pic32mx2xx/pic32mx2x4fxxxb/PIC32MX274F256B.PIC pic32mx2x4 + +build_module $URLBASE/pic32mx470/pic32mx37xfxxxl/PIC32MX370F512L.PIC pic32mx37x +build_module $URLBASE/pic32mx470/pic32mx47xfxxxl/PIC32MX470F512L.PIC pic32mx47x + +build_module $URLBASE_MX567/pic32mx567/pic32mx695fxxxl/PIC32MX695F512L.PIC pic32mx567 build_module file:$(pwd)/PIC32MZ2048EFM144.PIC pic32mzef + +cargo fmt diff --git a/pic32-config-sector/src/lib.rs b/pic32-config-sector/src/lib.rs index 3ae6c6a..0d85aef 100644 --- a/pic32-config-sector/src/lib.rs +++ b/pic32-config-sector/src/lib.rs @@ -43,5 +43,14 @@ pub mod pic32mx1x4; /// Configuration sector struct and builder for PIC32MX2x4 (XLP) pub mod pic32mx2x4; +/// Configuration sector struct and builder for PIC32MX330/350/370 +pub mod pic32mx37x; + +/// Configuration sector struct and builder for PIC32MX430/450/470 +pub mod pic32mx47x; + +/// Configuration sector struct and builder for PIC32MX5xx/6xx/7xx +pub mod pic32mx567; + /// Configuration sector struct and builder for PIC32MZEF pub mod pic32mzef; diff --git a/pic32-config-sector/src/pic32mx37x.rs b/pic32-config-sector/src/pic32mx37x.rs new file mode 100644 index 0000000..822d425 --- /dev/null +++ b/pic32-config-sector/src/pic32mx37x.rs @@ -0,0 +1,954 @@ +#![allow(non_snake_case)] +#![allow(non_camel_case_types)] +#![allow(clippy::upper_case_acronyms)] +/// Length of config word sector in words +pub const CONFIG_SECTOR_LENGTH: usize = 4; + +type USERID = u16; + +/// Shadow Register Set Priority Select +pub enum FSRSSEL { + /// SRS Priority 0 + PRIORITY_0 = 0x0, + + /// SRS Priority 1 + PRIORITY_1 = 0x1, + + /// SRS Priority 2 + PRIORITY_2 = 0x2, + + /// SRS Priority 3 + PRIORITY_3 = 0x3, + + /// SRS Priority 4 + PRIORITY_4 = 0x4, + + /// SRS Priority 5 + PRIORITY_5 = 0x5, + + /// SRS Priority 6 + PRIORITY_6 = 0x6, + + /// SRS Priority 7 + PRIORITY_7 = 0x7, +} + +/// Peripheral Module Disable Configuration +pub enum PMDL1WAY { + /// Allow only one reconfiguration + ON = 0x1, + + /// Allow multiple reconfigurations + OFF = 0x0, +} + +/// Peripheral Pin Select Configuration +pub enum IOL1WAY { + /// Allow only one reconfiguration + ON = 0x1, + + /// Allow multiple reconfigurations + OFF = 0x0, +} + +/// PLL Input Divider +pub enum FPLLIDIV { + /// 1x Divider + DIV_1 = 0x0, + + /// 2x Divider + DIV_2 = 0x1, + + /// 3x Divider + DIV_3 = 0x2, + + /// 4x Divider + DIV_4 = 0x3, + + /// 5x Divider + DIV_5 = 0x4, + + /// 6x Divider + DIV_6 = 0x5, + + /// 10x Divider + DIV_10 = 0x6, + + /// 12x Divider + DIV_12 = 0x7, +} + +/// PLL Multiplier +pub enum FPLLMUL { + /// 15x Multiplier + MUL_15 = 0x0, + + /// 16x Multiplier + MUL_16 = 0x1, + + /// 17x Multiplier + MUL_17 = 0x2, + + /// 18x Multiplier + MUL_18 = 0x3, + + /// 19x Multiplier + MUL_19 = 0x4, + + /// 20x Multiplier + MUL_20 = 0x5, + + /// 21x Multiplier + MUL_21 = 0x6, + + /// 24x Multiplier + MUL_24 = 0x7, +} + +/// System PLL Output Clock Divider +pub enum FPLLODIV { + /// PLL Divide by 1 + DIV_1 = 0x0, + + /// PLL Divide by 2 + DIV_2 = 0x1, + + /// PLL Divide by 4 + DIV_4 = 0x2, + + /// PLL Divide by 8 + DIV_8 = 0x3, + + /// PLL Divide by 16 + DIV_16 = 0x4, + + /// PLL Divide by 32 + DIV_32 = 0x5, + + /// PLL Divide by 64 + DIV_64 = 0x6, + + /// PLL Divide by 256 + DIV_256 = 0x7, +} + +/// Oscillator Selection Bits +pub enum FNOSC { + /// Fast RC Osc (FRC) + FRC = 0x0, + + /// Fast RC Osc with PLL + FRCPLL = 0x1, + + /// Primary Osc (XT,HS,EC) + PRI = 0x2, + + /// Primary Osc w/PLL (XT+,HS+,EC+PLL) + PRIPLL = 0x3, + + /// Low Power Secondary Osc (SOSC) + SOSC = 0x4, + + /// Low Power RC Osc (LPRC) + LPRC = 0x5, + + /// Fast RC Osc w/Div-by-16 (FRC/16) + FRCDIV16 = 0x6, + + /// Fast RC Osc w/Div-by-N (FRCDIV) + FRCDIV = 0x7, +} + +/// Secondary Oscillator Enable +pub enum FSOSCEN { + /// Disabled + OFF = 0x0, + + /// Enabled + ON = 0x1, +} + +/// Internal/External Switch Over +pub enum IESO { + /// Disabled + OFF = 0x0, + + /// Enabled + ON = 0x1, +} + +/// Primary Oscillator Configuration +pub enum POSCMOD { + /// External clock mode + EC = 0x0, + + /// XT osc mode + XT = 0x1, + + /// HS osc mode + HS = 0x2, + + /// Primary osc disabled + OFF = 0x3, +} + +/// CLKO Output Signal Active on the OSCO Pin +pub enum OSCIOFNC { + /// Disabled + OFF = 0x1, + + /// Enabled + ON = 0x0, +} + +/// Peripheral Clock Divisor +pub enum FPBDIV { + /// Pb_Clk is Sys_Clk/1 + DIV_1 = 0x0, + + /// Pb_Clk is Sys_Clk/2 + DIV_2 = 0x1, + + /// Pb_Clk is Sys_Clk/4 + DIV_4 = 0x2, + + /// Pb_Clk is Sys_Clk/8 + DIV_8 = 0x3, +} + +/// Clock Switching and Monitor Selection +pub enum FCKSM { + /// Clock Switch Enable, FSCM Enabled + CSECME = 0x0, + + /// Clock Switch Enable, FSCM Disabled + CSECMD = 0x1, + + /// Clock Switch Disable, FSCM Disabled + CSDCMD = 0x3, +} + +/// Watchdog Timer Postscaler +pub enum WDTPS { + /// 1:1 + PS1 = 0x0, + + /// 1:2 + PS2 = 0x1, + + /// 1:4 + PS4 = 0x2, + + /// 1:8 + PS8 = 0x3, + + /// 1:16 + PS16 = 0x4, + + /// 1:32 + PS32 = 0x5, + + /// 1:64 + PS64 = 0x6, + + /// 1:128 + PS128 = 0x7, + + /// 1:256 + PS256 = 0x8, + + /// 1:512 + PS512 = 0x9, + + /// 1:1024 + PS1024 = 0xa, + + /// 1:2048 + PS2048 = 0xb, + + /// 1:4096 + PS4096 = 0xc, + + /// 1:8192 + PS8192 = 0xd, + + /// 1:16384 + PS16384 = 0xe, + + /// 1:32768 + PS32768 = 0xf, + + /// 1:65536 + PS65536 = 0x10, + + /// 1:131072 + PS131072 = 0x11, + + /// 1:262144 + PS262144 = 0x12, + + /// 1:524288 + PS524288 = 0x13, + + /// 1:1048576 + PS1048576 = 0x14, +} + +/// Watchdog Timer Window Enable +pub enum WINDIS { + /// Watchdog Timer is in Window Mode + ON = 0x0, + + /// Watchdog Timer is in Non-Window Mode + OFF = 0x1, +} + +/// Watchdog Timer Enable +pub enum FWDTEN { + /// WDT Disabled (SWDTEN Bit Controls) + OFF = 0x0, + + /// WDT Enabled + ON = 0x1, +} + +/// Watchdog Timer Window Size +pub enum FWDTWINSZ { + /// Window Size is 75% + WINSZ_75 = 0x0, + + /// Window Size is 50% + WINSZ_50 = 0x1, + + /// Window Size is 37.5% + WINSZ_37 = 0x2, + + /// Window Size is 25% + WINSZ_25 = 0x3, +} + +/// Background Debugger Enable +pub enum DEBUG { + /// Debugger is Enabled + ON = 0x0, + + /// Debugger is Disabled + OFF = 0x3, +} + +/// JTAG Enable +pub enum JTAGEN { + /// JTAG Port Enabled + ON = 0x1, + + /// JTAG Disabled + OFF = 0x0, +} + +/// ICE/ICD Comm Channel Select +pub enum ICESEL { + /// Communicate on PGEC1/PGED1 + ICS_PGx1 = 0x3, + + /// Communicate on PGEC2/PGED2 + ICS_PGx2 = 0x2, + + /// Communicate on PGEC3/PGED3 + ICS_PGx3 = 0x1, +} + +/// Program Flash Write Protect +pub enum PWP { + /// Disable + OFF = 0xff, + + /// First 4K + PWP4K = 0xfe, + + /// First 8K + PWP8K = 0xfd, + + /// First 12K + PWP12K = 0xfc, + + /// First 16K + PWP16K = 0xfb, + + /// First 20K + PWP20K = 0xfa, + + /// First 24K + PWP24K = 0xf9, + + /// First 28K + PWP28K = 0xf8, + + /// First 32K + PWP32K = 0xf7, + + /// First 36K + PWP36K = 0xf6, + + /// First 40K + PWP40K = 0xf5, + + /// First 44K + PWP44K = 0xf4, + + /// First 48K + PWP48K = 0xf3, + + /// First 52K + PWP52K = 0xf2, + + /// First 56K + PWP56K = 0xf1, + + /// First 60K + PWP60K = 0xf0, + + /// First 64K + PWP64K = 0xef, + + /// First 68K + PWP68K = 0xee, + + /// First 72K + PWP72K = 0xed, + + /// First 76K + PWP76K = 0xec, + + /// First 80K + PWP80K = 0xeb, + + /// First 84K + PWP84K = 0xea, + + /// First 88K + PWP88K = 0xe9, + + /// First 92K + PWP92K = 0xe8, + + /// First 96K + PWP96K = 0xe7, + + /// First 100K + PWP100K = 0xe6, + + /// First 104K + PWP104K = 0xe5, + + /// First 108K + PWP108K = 0xe4, + + /// First 112K + PWP112K = 0xe3, + + /// First 116K + PWP116K = 0xe2, + + /// First 120K + PWP120K = 0xe1, + + /// First 124K + PWP124K = 0xe0, + + /// First 128K + PWP128K = 0xdf, + + /// First 132K + PWP132K = 0xde, + + /// First 136K + PWP136K = 0xdd, + + /// First 140K + PWP140K = 0xdc, + + /// First 144K + PWP144K = 0xdb, + + /// First 148K + PWP148K = 0xda, + + /// First 152K + PWP152K = 0xd9, + + /// First 156K + PWP156K = 0xd8, + + /// First 160K + PWP160K = 0xd7, + + /// First 164K + PWP164K = 0xd6, + + /// First 168K + PWP168K = 0xd5, + + /// First 172K + PWP172K = 0xd4, + + /// First 176K + PWP176K = 0xd3, + + /// First 180K + PWP180K = 0xd2, + + /// First 184K + PWP184K = 0xd1, + + /// First 188K + PWP188K = 0xd0, + + /// First 192K + PWP192K = 0xcf, + + /// First 196K + PWP196K = 0xce, + + /// First 200K + PWP200K = 0xcd, + + /// First 204K + PWP204K = 0xcc, + + /// First 208K + PWP208K = 0xcb, + + /// First 212K + PWP212K = 0xca, + + /// First 216K + PWP216K = 0xc9, + + /// First 220K + PWP220K = 0xc8, + + /// First 224K + PWP224K = 0xc7, + + /// First 228K + PWP228K = 0xc6, + + /// First 232K + PWP232K = 0xc5, + + /// First 236K + PWP236K = 0xc4, + + /// First 240K + PWP240K = 0xc3, + + /// First 244K + PWP244K = 0xc2, + + /// First 248K + PWP248K = 0xc1, + + /// First 252K + PWP252K = 0xc0, + + /// First 256K + PWP256K = 0xbf, + + /// First 260K + PWP260K = 0xbe, + + /// First 264K + PWP264K = 0xbd, + + /// First 268K + PWP268K = 0xbc, + + /// First 272K + PWP272K = 0xbb, + + /// First 276K + PWP276K = 0xba, + + /// First 280K + PWP280K = 0xb9, + + /// First 284K + PWP284K = 0xb8, + + /// First 288K + PWP288K = 0xb7, + + /// First 292K + PWP292K = 0xb6, + + /// First 296K + PWP296K = 0xb5, + + /// First 300K + PWP300K = 0xb4, + + /// First 304K + PWP304K = 0xb3, + + /// First 308K + PWP308K = 0xb2, + + /// First 312K + PWP312K = 0xb1, + + /// First 316K + PWP316K = 0xb0, + + /// First 320K + PWP320K = 0xaf, + + /// First 324K + PWP324K = 0xae, + + /// First 328K + PWP328K = 0xad, + + /// First 332K + PWP332K = 0xac, + + /// First 336K + PWP336K = 0xab, + + /// First 340K + PWP340K = 0xaa, + + /// First 344K + PWP344K = 0xa9, + + /// First 348K + PWP348K = 0xa8, + + /// First 352K + PWP352K = 0xa7, + + /// First 356K + PWP356K = 0xa6, + + /// First 360K + PWP360K = 0xa5, + + /// First 364K + PWP364K = 0xa4, + + /// First 368K + PWP368K = 0xa3, + + /// First 372K + PWP372K = 0xa2, + + /// First 376K + PWP376K = 0xa1, + + /// First 380K + PWP380K = 0xa0, + + /// First 384K + PWP384K = 0x9f, + + /// First 388K + PWP388K = 0x9e, + + /// First 392K + PWP392K = 0x9d, + + /// First 396K + PWP396K = 0x9c, + + /// First 400K + PWP400K = 0x9b, + + /// First 404K + PWP404K = 0x9a, + + /// First 408K + PWP408K = 0x99, + + /// First 412K + PWP412K = 0x98, + + /// First 416K + PWP416K = 0x97, + + /// First 420K + PWP420K = 0x96, + + /// First 424K + PWP424K = 0x95, + + /// First 428K + PWP428K = 0x94, + + /// First 432K + PWP432K = 0x93, + + /// First 436K + PWP436K = 0x92, + + /// First 440K + PWP440K = 0x91, + + /// First 444K + PWP444K = 0x90, + + /// First 448K + PWP448K = 0x8f, + + /// First 452K + PWP452K = 0x8e, + + /// First 456K + PWP456K = 0x8d, + + /// First 460K + PWP460K = 0x8c, + + /// First 464K + PWP464K = 0x8b, + + /// First 468K + PWP468K = 0x8a, + + /// First 472K + PWP472K = 0x89, + + /// First 476K + PWP476K = 0x88, + + /// First 480K + PWP480K = 0x87, + + /// First 484K + PWP484K = 0x86, + + /// First 488K + PWP488K = 0x85, + + /// First 492K + PWP492K = 0x84, + + /// First 496K + PWP496K = 0x83, + + /// First 500K + PWP500K = 0x82, + + /// First 504K + PWP504K = 0x81, + + /// First 508K + PWP508K = 0x80, + + /// First 512K + PWP512K = 0x7f, +} + +/// Boot Flash Write Protect bit +pub enum BWP { + /// Protection Enabled + ON = 0x0, + + /// Protection Disabled + OFF = 0x1, +} + +/// Code Protect +pub enum CP { + /// Protection Enabled + ON = 0x0, + + /// Protection Disabled + OFF = 0x1, +} + +/// Configuration word sector +#[repr(C)] +pub struct ConfigSector { + DEVCFG3: u32, + DEVCFG2: u32, + DEVCFG1: u32, + DEVCFG0: u32, +} + +impl ConfigSector { + /// Create a builder + pub const fn default() -> ConfigSectorBuilder { + ConfigSectorBuilder { + DEVCFG3: 0xffffffff, + DEVCFG2: 0xffffffff, + DEVCFG1: 0xffffffff, + DEVCFG0: 0x7fffffff, + } + } + + /// Convert into a array of 32 bit words consuming this ConfigSector + pub const fn into_array(self) -> [u32; CONFIG_SECTOR_LENGTH] { + [self.DEVCFG3, self.DEVCFG2, self.DEVCFG1, self.DEVCFG0] + } +} +/// Configuration word sector builder +pub struct ConfigSectorBuilder { + DEVCFG3: u32, + DEVCFG2: u32, + DEVCFG1: u32, + DEVCFG0: u32, +} + +impl ConfigSectorBuilder { + pub const fn USERID(mut self, v: USERID) -> Self { + self.DEVCFG3 &= !0x0000ffff; + self.DEVCFG3 |= v as u32; + self + } + + pub const fn FSRSSEL(mut self, v: FSRSSEL) -> Self { + self.DEVCFG3 &= !0x00070000; + self.DEVCFG3 |= (v as u32) << 16; + self + } + + pub const fn PMDL1WAY(mut self, v: PMDL1WAY) -> Self { + self.DEVCFG3 &= !0x10000000; + self.DEVCFG3 |= (v as u32) << 28; + self + } + + pub const fn IOL1WAY(mut self, v: IOL1WAY) -> Self { + self.DEVCFG3 &= !0x20000000; + self.DEVCFG3 |= (v as u32) << 29; + self + } + + pub const fn FPLLIDIV(mut self, v: FPLLIDIV) -> Self { + self.DEVCFG2 &= !0x00000007; + self.DEVCFG2 |= v as u32; + self + } + + pub const fn FPLLMUL(mut self, v: FPLLMUL) -> Self { + self.DEVCFG2 &= !0x00000070; + self.DEVCFG2 |= (v as u32) << 4; + self + } + + pub const fn FPLLODIV(mut self, v: FPLLODIV) -> Self { + self.DEVCFG2 &= !0x00070000; + self.DEVCFG2 |= (v as u32) << 16; + self + } + + pub const fn FNOSC(mut self, v: FNOSC) -> Self { + self.DEVCFG1 &= !0x00000007; + self.DEVCFG1 |= v as u32; + self + } + + pub const fn FSOSCEN(mut self, v: FSOSCEN) -> Self { + self.DEVCFG1 &= !0x00000020; + self.DEVCFG1 |= (v as u32) << 5; + self + } + + pub const fn IESO(mut self, v: IESO) -> Self { + self.DEVCFG1 &= !0x00000080; + self.DEVCFG1 |= (v as u32) << 7; + self + } + + pub const fn POSCMOD(mut self, v: POSCMOD) -> Self { + self.DEVCFG1 &= !0x00000300; + self.DEVCFG1 |= (v as u32) << 8; + self + } + + pub const fn OSCIOFNC(mut self, v: OSCIOFNC) -> Self { + self.DEVCFG1 &= !0x00000400; + self.DEVCFG1 |= (v as u32) << 10; + self + } + + pub const fn FPBDIV(mut self, v: FPBDIV) -> Self { + self.DEVCFG1 &= !0x00003000; + self.DEVCFG1 |= (v as u32) << 12; + self + } + + pub const fn FCKSM(mut self, v: FCKSM) -> Self { + self.DEVCFG1 &= !0x0000c000; + self.DEVCFG1 |= (v as u32) << 14; + self + } + + pub const fn WDTPS(mut self, v: WDTPS) -> Self { + self.DEVCFG1 &= !0x001f0000; + self.DEVCFG1 |= (v as u32) << 16; + self + } + + pub const fn WINDIS(mut self, v: WINDIS) -> Self { + self.DEVCFG1 &= !0x00400000; + self.DEVCFG1 |= (v as u32) << 22; + self + } + + pub const fn FWDTEN(mut self, v: FWDTEN) -> Self { + self.DEVCFG1 &= !0x00800000; + self.DEVCFG1 |= (v as u32) << 23; + self + } + + pub const fn FWDTWINSZ(mut self, v: FWDTWINSZ) -> Self { + self.DEVCFG1 &= !0x03000000; + self.DEVCFG1 |= (v as u32) << 24; + self + } + + pub const fn DEBUG(mut self, v: DEBUG) -> Self { + self.DEVCFG0 &= !0x00000003; + self.DEVCFG0 |= v as u32; + self + } + + pub const fn JTAGEN(mut self, v: JTAGEN) -> Self { + self.DEVCFG0 &= !0x00000004; + self.DEVCFG0 |= (v as u32) << 2; + self + } + + pub const fn ICESEL(mut self, v: ICESEL) -> Self { + self.DEVCFG0 &= !0x00000018; + self.DEVCFG0 |= (v as u32) << 3; + self + } + + pub const fn PWP(mut self, v: PWP) -> Self { + self.DEVCFG0 &= !0x000ff000; + self.DEVCFG0 |= (v as u32) << 12; + self + } + + pub const fn BWP(mut self, v: BWP) -> Self { + self.DEVCFG0 &= !0x01000000; + self.DEVCFG0 |= (v as u32) << 24; + self + } + + pub const fn CP(mut self, v: CP) -> Self { + self.DEVCFG0 &= !0x10000000; + self.DEVCFG0 |= (v as u32) << 28; + self + } + + pub const fn build(self) -> ConfigSector { + ConfigSector { + DEVCFG3: self.DEVCFG3, + DEVCFG2: self.DEVCFG2, + DEVCFG1: self.DEVCFG1, + DEVCFG0: self.DEVCFG0, + } + } +} diff --git a/pic32-config-sector/src/pic32mx47x.rs b/pic32-config-sector/src/pic32mx47x.rs new file mode 100644 index 0000000..362fc0d --- /dev/null +++ b/pic32-config-sector/src/pic32mx47x.rs @@ -0,0 +1,1032 @@ +#![allow(non_snake_case)] +#![allow(non_camel_case_types)] +#![allow(clippy::upper_case_acronyms)] +/// Length of config word sector in words +pub const CONFIG_SECTOR_LENGTH: usize = 4; + +type USERID = u16; + +/// Shadow Register Set Priority Select +pub enum FSRSSEL { + /// SRS Priority 0 + PRIORITY_0 = 0x0, + + /// SRS Priority 1 + PRIORITY_1 = 0x1, + + /// SRS Priority 2 + PRIORITY_2 = 0x2, + + /// SRS Priority 3 + PRIORITY_3 = 0x3, + + /// SRS Priority 4 + PRIORITY_4 = 0x4, + + /// SRS Priority 5 + PRIORITY_5 = 0x5, + + /// SRS Priority 6 + PRIORITY_6 = 0x6, + + /// SRS Priority 7 + PRIORITY_7 = 0x7, +} + +/// Peripheral Module Disable Configuration +pub enum PMDL1WAY { + /// Allow only one reconfiguration + ON = 0x1, + + /// Allow multiple reconfigurations + OFF = 0x0, +} + +/// Peripheral Pin Select Configuration +pub enum IOL1WAY { + /// Allow only one reconfiguration + ON = 0x1, + + /// Allow multiple reconfigurations + OFF = 0x0, +} + +/// USB USID Selection +pub enum FUSBIDIO { + /// Controlled by Port Function + OFF = 0x0, + + /// Controlled by the USB Module + ON = 0x1, +} + +/// USB VBUS ON Selection +pub enum FVBUSONIO { + /// Controlled by Port Function + OFF = 0x0, + + /// Controlled by USB Module + ON = 0x1, +} + +/// PLL Input Divider +pub enum FPLLIDIV { + /// 1x Divider + DIV_1 = 0x0, + + /// 2x Divider + DIV_2 = 0x1, + + /// 3x Divider + DIV_3 = 0x2, + + /// 4x Divider + DIV_4 = 0x3, + + /// 5x Divider + DIV_5 = 0x4, + + /// 6x Divider + DIV_6 = 0x5, + + /// 10x Divider + DIV_10 = 0x6, + + /// 12x Divider + DIV_12 = 0x7, +} + +/// PLL Multiplier +pub enum FPLLMUL { + /// 15x Multiplier + MUL_15 = 0x0, + + /// 16x Multiplier + MUL_16 = 0x1, + + /// 17x Multiplier + MUL_17 = 0x2, + + /// 18x Multiplier + MUL_18 = 0x3, + + /// 19x Multiplier + MUL_19 = 0x4, + + /// 20x Multiplier + MUL_20 = 0x5, + + /// 21x Multiplier + MUL_21 = 0x6, + + /// 24x Multiplier + MUL_24 = 0x7, +} + +/// USB PLL Input Divider +pub enum UPLLIDIV { + /// 1x Divider + DIV_1 = 0x0, + + /// 2x Divider + DIV_2 = 0x1, + + /// 3x Divider + DIV_3 = 0x2, + + /// 4x Divider + DIV_4 = 0x3, + + /// 5x Divider + DIV_5 = 0x4, + + /// 6x Divider + DIV_6 = 0x5, + + /// 10x Divider + DIV_10 = 0x6, + + /// 12x Divider + DIV_12 = 0x7, +} + +/// USB PLL Enable +pub enum UPLLEN { + /// Enabled + ON = 0x0, + + /// Disabled and Bypassed + OFF = 0x1, +} + +/// System PLL Output Clock Divider +pub enum FPLLODIV { + /// PLL Divide by 1 + DIV_1 = 0x0, + + /// PLL Divide by 2 + DIV_2 = 0x1, + + /// PLL Divide by 4 + DIV_4 = 0x2, + + /// PLL Divide by 8 + DIV_8 = 0x3, + + /// PLL Divide by 16 + DIV_16 = 0x4, + + /// PLL Divide by 32 + DIV_32 = 0x5, + + /// PLL Divide by 64 + DIV_64 = 0x6, + + /// PLL Divide by 256 + DIV_256 = 0x7, +} + +/// Oscillator Selection Bits +pub enum FNOSC { + /// Fast RC Osc (FRC) + FRC = 0x0, + + /// Fast RC Osc with PLL + FRCPLL = 0x1, + + /// Primary Osc (XT,HS,EC) + PRI = 0x2, + + /// Primary Osc w/PLL (XT+,HS+,EC+PLL) + PRIPLL = 0x3, + + /// Low Power Secondary Osc (SOSC) + SOSC = 0x4, + + /// Low Power RC Osc (LPRC) + LPRC = 0x5, + + /// Fast RC Osc w/Div-by-16 (FRC/16) + FRCDIV16 = 0x6, + + /// Fast RC Osc w/Div-by-N (FRCDIV) + FRCDIV = 0x7, +} + +/// Secondary Oscillator Enable +pub enum FSOSCEN { + /// Disabled + OFF = 0x0, + + /// Enabled + ON = 0x1, +} + +/// Internal/External Switch Over +pub enum IESO { + /// Disabled + OFF = 0x0, + + /// Enabled + ON = 0x1, +} + +/// Primary Oscillator Configuration +pub enum POSCMOD { + /// External clock mode + EC = 0x0, + + /// XT osc mode + XT = 0x1, + + /// HS osc mode + HS = 0x2, + + /// Primary osc disabled + OFF = 0x3, +} + +/// CLKO Output Signal Active on the OSCO Pin +pub enum OSCIOFNC { + /// Disabled + OFF = 0x1, + + /// Enabled + ON = 0x0, +} + +/// Peripheral Clock Divisor +pub enum FPBDIV { + /// Pb_Clk is Sys_Clk/1 + DIV_1 = 0x0, + + /// Pb_Clk is Sys_Clk/2 + DIV_2 = 0x1, + + /// Pb_Clk is Sys_Clk/4 + DIV_4 = 0x2, + + /// Pb_Clk is Sys_Clk/8 + DIV_8 = 0x3, +} + +/// Clock Switching and Monitor Selection +pub enum FCKSM { + /// Clock Switch Enable, FSCM Enabled + CSECME = 0x0, + + /// Clock Switch Enable, FSCM Disabled + CSECMD = 0x1, + + /// Clock Switch Disable, FSCM Disabled + CSDCMD = 0x3, +} + +/// Watchdog Timer Postscaler +pub enum WDTPS { + /// 1:1 + PS1 = 0x0, + + /// 1:2 + PS2 = 0x1, + + /// 1:4 + PS4 = 0x2, + + /// 1:8 + PS8 = 0x3, + + /// 1:16 + PS16 = 0x4, + + /// 1:32 + PS32 = 0x5, + + /// 1:64 + PS64 = 0x6, + + /// 1:128 + PS128 = 0x7, + + /// 1:256 + PS256 = 0x8, + + /// 1:512 + PS512 = 0x9, + + /// 1:1024 + PS1024 = 0xa, + + /// 1:2048 + PS2048 = 0xb, + + /// 1:4096 + PS4096 = 0xc, + + /// 1:8192 + PS8192 = 0xd, + + /// 1:16384 + PS16384 = 0xe, + + /// 1:32768 + PS32768 = 0xf, + + /// 1:65536 + PS65536 = 0x10, + + /// 1:131072 + PS131072 = 0x11, + + /// 1:262144 + PS262144 = 0x12, + + /// 1:524288 + PS524288 = 0x13, + + /// 1:1048576 + PS1048576 = 0x14, +} + +/// Watchdog Timer Window Enable +pub enum WINDIS { + /// Watchdog Timer is in Window Mode + ON = 0x0, + + /// Watchdog Timer is in Non-Window Mode + OFF = 0x1, +} + +/// Watchdog Timer Enable +pub enum FWDTEN { + /// WDT Disabled (SWDTEN Bit Controls) + OFF = 0x0, + + /// WDT Enabled + ON = 0x1, +} + +/// Watchdog Timer Window Size +pub enum FWDTWINSZ { + /// Window Size is 75% + WINSZ_75 = 0x0, + + /// Window Size is 50% + WINSZ_50 = 0x1, + + /// Window Size is 37.5% + WINSZ_37 = 0x2, + + /// Window Size is 25% + WINSZ_25 = 0x3, +} + +/// Background Debugger Enable +pub enum DEBUG { + /// Debugger is Enabled + ON = 0x0, + + /// Debugger is Disabled + OFF = 0x3, +} + +/// JTAG Enable +pub enum JTAGEN { + /// JTAG Port Enabled + ON = 0x1, + + /// JTAG Disabled + OFF = 0x0, +} + +/// ICE/ICD Comm Channel Select +pub enum ICESEL { + /// Communicate on PGEC1/PGED1 + ICS_PGx1 = 0x3, + + /// Communicate on PGEC2/PGED2 + ICS_PGx2 = 0x2, + + /// Communicate on PGEC3/PGED3 + ICS_PGx3 = 0x1, +} + +/// Program Flash Write Protect +pub enum PWP { + /// Disable + OFF = 0xff, + + /// First 4K + PWP4K = 0xfe, + + /// First 8K + PWP8K = 0xfd, + + /// First 12K + PWP12K = 0xfc, + + /// First 16K + PWP16K = 0xfb, + + /// First 20K + PWP20K = 0xfa, + + /// First 24K + PWP24K = 0xf9, + + /// First 28K + PWP28K = 0xf8, + + /// First 32K + PWP32K = 0xf7, + + /// First 36K + PWP36K = 0xf6, + + /// First 40K + PWP40K = 0xf5, + + /// First 44K + PWP44K = 0xf4, + + /// First 48K + PWP48K = 0xf3, + + /// First 52K + PWP52K = 0xf2, + + /// First 56K + PWP56K = 0xf1, + + /// First 60K + PWP60K = 0xf0, + + /// First 64K + PWP64K = 0xef, + + /// First 68K + PWP68K = 0xee, + + /// First 72K + PWP72K = 0xed, + + /// First 76K + PWP76K = 0xec, + + /// First 80K + PWP80K = 0xeb, + + /// First 84K + PWP84K = 0xea, + + /// First 88K + PWP88K = 0xe9, + + /// First 92K + PWP92K = 0xe8, + + /// First 96K + PWP96K = 0xe7, + + /// First 100K + PWP100K = 0xe6, + + /// First 104K + PWP104K = 0xe5, + + /// First 108K + PWP108K = 0xe4, + + /// First 112K + PWP112K = 0xe3, + + /// First 116K + PWP116K = 0xe2, + + /// First 120K + PWP120K = 0xe1, + + /// First 124K + PWP124K = 0xe0, + + /// First 128K + PWP128K = 0xdf, + + /// First 132K + PWP132K = 0xde, + + /// First 136K + PWP136K = 0xdd, + + /// First 140K + PWP140K = 0xdc, + + /// First 144K + PWP144K = 0xdb, + + /// First 148K + PWP148K = 0xda, + + /// First 152K + PWP152K = 0xd9, + + /// First 156K + PWP156K = 0xd8, + + /// First 160K + PWP160K = 0xd7, + + /// First 164K + PWP164K = 0xd6, + + /// First 168K + PWP168K = 0xd5, + + /// First 172K + PWP172K = 0xd4, + + /// First 176K + PWP176K = 0xd3, + + /// First 180K + PWP180K = 0xd2, + + /// First 184K + PWP184K = 0xd1, + + /// First 188K + PWP188K = 0xd0, + + /// First 192K + PWP192K = 0xcf, + + /// First 196K + PWP196K = 0xce, + + /// First 200K + PWP200K = 0xcd, + + /// First 204K + PWP204K = 0xcc, + + /// First 208K + PWP208K = 0xcb, + + /// First 212K + PWP212K = 0xca, + + /// First 216K + PWP216K = 0xc9, + + /// First 220K + PWP220K = 0xc8, + + /// First 224K + PWP224K = 0xc7, + + /// First 228K + PWP228K = 0xc6, + + /// First 232K + PWP232K = 0xc5, + + /// First 236K + PWP236K = 0xc4, + + /// First 240K + PWP240K = 0xc3, + + /// First 244K + PWP244K = 0xc2, + + /// First 248K + PWP248K = 0xc1, + + /// First 252K + PWP252K = 0xc0, + + /// First 256K + PWP256K = 0xbf, + + /// First 260K + PWP260K = 0xbe, + + /// First 264K + PWP264K = 0xbd, + + /// First 268K + PWP268K = 0xbc, + + /// First 272K + PWP272K = 0xbb, + + /// First 276K + PWP276K = 0xba, + + /// First 280K + PWP280K = 0xb9, + + /// First 284K + PWP284K = 0xb8, + + /// First 288K + PWP288K = 0xb7, + + /// First 292K + PWP292K = 0xb6, + + /// First 296K + PWP296K = 0xb5, + + /// First 300K + PWP300K = 0xb4, + + /// First 304K + PWP304K = 0xb3, + + /// First 308K + PWP308K = 0xb2, + + /// First 312K + PWP312K = 0xb1, + + /// First 316K + PWP316K = 0xb0, + + /// First 320K + PWP320K = 0xaf, + + /// First 324K + PWP324K = 0xae, + + /// First 328K + PWP328K = 0xad, + + /// First 332K + PWP332K = 0xac, + + /// First 336K + PWP336K = 0xab, + + /// First 340K + PWP340K = 0xaa, + + /// First 344K + PWP344K = 0xa9, + + /// First 348K + PWP348K = 0xa8, + + /// First 352K + PWP352K = 0xa7, + + /// First 356K + PWP356K = 0xa6, + + /// First 360K + PWP360K = 0xa5, + + /// First 364K + PWP364K = 0xa4, + + /// First 368K + PWP368K = 0xa3, + + /// First 372K + PWP372K = 0xa2, + + /// First 376K + PWP376K = 0xa1, + + /// First 380K + PWP380K = 0xa0, + + /// First 384K + PWP384K = 0x9f, + + /// First 388K + PWP388K = 0x9e, + + /// First 392K + PWP392K = 0x9d, + + /// First 396K + PWP396K = 0x9c, + + /// First 400K + PWP400K = 0x9b, + + /// First 404K + PWP404K = 0x9a, + + /// First 408K + PWP408K = 0x99, + + /// First 412K + PWP412K = 0x98, + + /// First 416K + PWP416K = 0x97, + + /// First 420K + PWP420K = 0x96, + + /// First 424K + PWP424K = 0x95, + + /// First 428K + PWP428K = 0x94, + + /// First 432K + PWP432K = 0x93, + + /// First 436K + PWP436K = 0x92, + + /// First 440K + PWP440K = 0x91, + + /// First 444K + PWP444K = 0x90, + + /// First 448K + PWP448K = 0x8f, + + /// First 452K + PWP452K = 0x8e, + + /// First 456K + PWP456K = 0x8d, + + /// First 460K + PWP460K = 0x8c, + + /// First 464K + PWP464K = 0x8b, + + /// First 468K + PWP468K = 0x8a, + + /// First 472K + PWP472K = 0x89, + + /// First 476K + PWP476K = 0x88, + + /// First 480K + PWP480K = 0x87, + + /// First 484K + PWP484K = 0x86, + + /// First 488K + PWP488K = 0x85, + + /// First 492K + PWP492K = 0x84, + + /// First 496K + PWP496K = 0x83, + + /// First 500K + PWP500K = 0x82, + + /// First 504K + PWP504K = 0x81, + + /// First 508K + PWP508K = 0x80, + + /// First 512K + PWP512K = 0x7f, +} + +/// Boot Flash Write Protect bit +pub enum BWP { + /// Protection Enabled + ON = 0x0, + + /// Protection Disabled + OFF = 0x1, +} + +/// Code Protect +pub enum CP { + /// Protection Enabled + ON = 0x0, + + /// Protection Disabled + OFF = 0x1, +} + +/// Configuration word sector +#[repr(C)] +pub struct ConfigSector { + DEVCFG3: u32, + DEVCFG2: u32, + DEVCFG1: u32, + DEVCFG0: u32, +} + +impl ConfigSector { + /// Create a builder + pub const fn default() -> ConfigSectorBuilder { + ConfigSectorBuilder { + DEVCFG3: 0xffffffff, + DEVCFG2: 0xffffffff, + DEVCFG1: 0xffffffff, + DEVCFG0: 0x7fffffff, + } + } + + /// Convert into a array of 32 bit words consuming this ConfigSector + pub const fn into_array(self) -> [u32; CONFIG_SECTOR_LENGTH] { + [self.DEVCFG3, self.DEVCFG2, self.DEVCFG1, self.DEVCFG0] + } +} +/// Configuration word sector builder +pub struct ConfigSectorBuilder { + DEVCFG3: u32, + DEVCFG2: u32, + DEVCFG1: u32, + DEVCFG0: u32, +} + +impl ConfigSectorBuilder { + pub const fn USERID(mut self, v: USERID) -> Self { + self.DEVCFG3 &= !0x0000ffff; + self.DEVCFG3 |= v as u32; + self + } + + pub const fn FSRSSEL(mut self, v: FSRSSEL) -> Self { + self.DEVCFG3 &= !0x00070000; + self.DEVCFG3 |= (v as u32) << 16; + self + } + + pub const fn PMDL1WAY(mut self, v: PMDL1WAY) -> Self { + self.DEVCFG3 &= !0x10000000; + self.DEVCFG3 |= (v as u32) << 28; + self + } + + pub const fn IOL1WAY(mut self, v: IOL1WAY) -> Self { + self.DEVCFG3 &= !0x20000000; + self.DEVCFG3 |= (v as u32) << 29; + self + } + + pub const fn FUSBIDIO(mut self, v: FUSBIDIO) -> Self { + self.DEVCFG3 &= !0x40000000; + self.DEVCFG3 |= (v as u32) << 30; + self + } + + pub const fn FVBUSONIO(mut self, v: FVBUSONIO) -> Self { + self.DEVCFG3 &= !0x80000000; + self.DEVCFG3 |= (v as u32) << 31; + self + } + + pub const fn FPLLIDIV(mut self, v: FPLLIDIV) -> Self { + self.DEVCFG2 &= !0x00000007; + self.DEVCFG2 |= v as u32; + self + } + + pub const fn FPLLMUL(mut self, v: FPLLMUL) -> Self { + self.DEVCFG2 &= !0x00000070; + self.DEVCFG2 |= (v as u32) << 4; + self + } + + pub const fn UPLLIDIV(mut self, v: UPLLIDIV) -> Self { + self.DEVCFG2 &= !0x00000700; + self.DEVCFG2 |= (v as u32) << 8; + self + } + + pub const fn UPLLEN(mut self, v: UPLLEN) -> Self { + self.DEVCFG2 &= !0x00008000; + self.DEVCFG2 |= (v as u32) << 15; + self + } + + pub const fn FPLLODIV(mut self, v: FPLLODIV) -> Self { + self.DEVCFG2 &= !0x00070000; + self.DEVCFG2 |= (v as u32) << 16; + self + } + + pub const fn FNOSC(mut self, v: FNOSC) -> Self { + self.DEVCFG1 &= !0x00000007; + self.DEVCFG1 |= v as u32; + self + } + + pub const fn FSOSCEN(mut self, v: FSOSCEN) -> Self { + self.DEVCFG1 &= !0x00000020; + self.DEVCFG1 |= (v as u32) << 5; + self + } + + pub const fn IESO(mut self, v: IESO) -> Self { + self.DEVCFG1 &= !0x00000080; + self.DEVCFG1 |= (v as u32) << 7; + self + } + + pub const fn POSCMOD(mut self, v: POSCMOD) -> Self { + self.DEVCFG1 &= !0x00000300; + self.DEVCFG1 |= (v as u32) << 8; + self + } + + pub const fn OSCIOFNC(mut self, v: OSCIOFNC) -> Self { + self.DEVCFG1 &= !0x00000400; + self.DEVCFG1 |= (v as u32) << 10; + self + } + + pub const fn FPBDIV(mut self, v: FPBDIV) -> Self { + self.DEVCFG1 &= !0x00003000; + self.DEVCFG1 |= (v as u32) << 12; + self + } + + pub const fn FCKSM(mut self, v: FCKSM) -> Self { + self.DEVCFG1 &= !0x0000c000; + self.DEVCFG1 |= (v as u32) << 14; + self + } + + pub const fn WDTPS(mut self, v: WDTPS) -> Self { + self.DEVCFG1 &= !0x001f0000; + self.DEVCFG1 |= (v as u32) << 16; + self + } + + pub const fn WINDIS(mut self, v: WINDIS) -> Self { + self.DEVCFG1 &= !0x00400000; + self.DEVCFG1 |= (v as u32) << 22; + self + } + + pub const fn FWDTEN(mut self, v: FWDTEN) -> Self { + self.DEVCFG1 &= !0x00800000; + self.DEVCFG1 |= (v as u32) << 23; + self + } + + pub const fn FWDTWINSZ(mut self, v: FWDTWINSZ) -> Self { + self.DEVCFG1 &= !0x03000000; + self.DEVCFG1 |= (v as u32) << 24; + self + } + + pub const fn DEBUG(mut self, v: DEBUG) -> Self { + self.DEVCFG0 &= !0x00000003; + self.DEVCFG0 |= v as u32; + self + } + + pub const fn JTAGEN(mut self, v: JTAGEN) -> Self { + self.DEVCFG0 &= !0x00000004; + self.DEVCFG0 |= (v as u32) << 2; + self + } + + pub const fn ICESEL(mut self, v: ICESEL) -> Self { + self.DEVCFG0 &= !0x00000018; + self.DEVCFG0 |= (v as u32) << 3; + self + } + + pub const fn PWP(mut self, v: PWP) -> Self { + self.DEVCFG0 &= !0x000ff000; + self.DEVCFG0 |= (v as u32) << 12; + self + } + + pub const fn BWP(mut self, v: BWP) -> Self { + self.DEVCFG0 &= !0x01000000; + self.DEVCFG0 |= (v as u32) << 24; + self + } + + pub const fn CP(mut self, v: CP) -> Self { + self.DEVCFG0 &= !0x10000000; + self.DEVCFG0 |= (v as u32) << 28; + self + } + + pub const fn build(self) -> ConfigSector { + ConfigSector { + DEVCFG3: self.DEVCFG3, + DEVCFG2: self.DEVCFG2, + DEVCFG1: self.DEVCFG1, + DEVCFG0: self.DEVCFG0, + } + } +} diff --git a/pic32-config-sector/src/pic32mx567.rs b/pic32-config-sector/src/pic32mx567.rs new file mode 100644 index 0000000..fdc005b --- /dev/null +++ b/pic32-config-sector/src/pic32mx567.rs @@ -0,0 +1,978 @@ +#![allow(non_snake_case)] +#![allow(non_camel_case_types)] +#![allow(clippy::upper_case_acronyms)] +/// Length of config word sector in words +pub const CONFIG_SECTOR_LENGTH: usize = 4; + +type USERID = u16; + +/// SRS Select +pub enum FSRSSEL { + /// SRS Priority 0 + PRIORITY_0 = 0x0, + + /// SRS Priority 1 + PRIORITY_1 = 0x1, + + /// SRS Priority 2 + PRIORITY_2 = 0x2, + + /// SRS Priority 3 + PRIORITY_3 = 0x3, + + /// SRS Priority 4 + PRIORITY_4 = 0x4, + + /// SRS Priority 5 + PRIORITY_5 = 0x5, + + /// SRS Priority 6 + PRIORITY_6 = 0x6, + + /// SRS Priority 7 + PRIORITY_7 = 0x7, +} + +/// Ethernet RMII/MII Enable +pub enum FMIIEN { + /// RMII Enabled + OFF = 0x0, + + /// MII Enabled + ON = 0x1, +} + +/// Ethernet I/O Pin Select +pub enum FETHIO { + /// Alternate Ethernet I/O + OFF = 0x0, + + /// Default Ethernet I/O + ON = 0x1, +} + +/// USB USID Selection +pub enum FUSBIDIO { + /// Controlled by Port Function + OFF = 0x0, + + /// Controlled by the USB Module + ON = 0x1, +} + +/// USB VBUS ON Selection +pub enum FVBUSONIO { + /// Controlled by Port Function + OFF = 0x0, + + /// Controlled by USB Module + ON = 0x1, +} + +/// PLL Input Divider +pub enum FPLLIDIV { + /// 1x Divider + DIV_1 = 0x0, + + /// 2x Divider + DIV_2 = 0x1, + + /// 3x Divider + DIV_3 = 0x2, + + /// 4x Divider + DIV_4 = 0x3, + + /// 5x Divider + DIV_5 = 0x4, + + /// 6x Divider + DIV_6 = 0x5, + + /// 10x Divider + DIV_10 = 0x6, + + /// 12x Divider + DIV_12 = 0x7, +} + +/// PLL Multiplier +pub enum FPLLMUL { + /// 15x Multiplier + MUL_15 = 0x0, + + /// 16x Multiplier + MUL_16 = 0x1, + + /// 17x Multiplier + MUL_17 = 0x2, + + /// 18x Multiplier + MUL_18 = 0x3, + + /// 19x Multiplier + MUL_19 = 0x4, + + /// 20x Multiplier + MUL_20 = 0x5, + + /// 21x Multiplier + MUL_21 = 0x6, + + /// 24x Multiplier + MUL_24 = 0x7, +} + +/// USB PLL Input Divider +pub enum UPLLIDIV { + /// 1x Divider + DIV_1 = 0x0, + + /// 2x Divider + DIV_2 = 0x1, + + /// 3x Divider + DIV_3 = 0x2, + + /// 4x Divider + DIV_4 = 0x3, + + /// 5x Divider + DIV_5 = 0x4, + + /// 6x Divider + DIV_6 = 0x5, + + /// 10x Divider + DIV_10 = 0x6, + + /// 12x Divider + DIV_12 = 0x7, +} + +/// USB PLL Enable +pub enum UPLLEN { + /// Enabled + ON = 0x0, + + /// Disabled and Bypassed + OFF = 0x1, +} + +/// System PLL Output Clock Divider +pub enum FPLLODIV { + /// PLL Divide by 1 + DIV_1 = 0x0, + + /// PLL Divide by 2 + DIV_2 = 0x1, + + /// PLL Divide by 4 + DIV_4 = 0x2, + + /// PLL Divide by 8 + DIV_8 = 0x3, + + /// PLL Divide by 16 + DIV_16 = 0x4, + + /// PLL Divide by 32 + DIV_32 = 0x5, + + /// PLL Divide by 64 + DIV_64 = 0x6, + + /// PLL Divide by 256 + DIV_256 = 0x7, +} + +/// Oscillator Selection Bits +pub enum FNOSC { + /// Fast RC Osc (FRC) + FRC = 0x0, + + /// Fast RC Osc with PLL + FRCPLL = 0x1, + + /// Primary Osc (XT,HS,EC) + PRI = 0x2, + + /// Primary Osc w/PLL (XT+,HS+,EC+PLL) + PRIPLL = 0x3, + + /// Low Power Secondary Osc (SOSC) + SOSC = 0x4, + + /// Low Power RC Osc (LPRC) + LPRC = 0x5, + + /// Fast RC Osc w/Div-by-16 (FRC/16) + FRCDIV16 = 0x6, + + /// Fast RC Osc w/Div-by-N (FRCDIV) + FRCDIV = 0x7, +} + +/// Secondary Oscillator Enable +pub enum FSOSCEN { + /// Disabled + OFF = 0x0, + + /// Enabled + ON = 0x1, +} + +/// Internal/External Switch Over +pub enum IESO { + /// Disabled + OFF = 0x0, + + /// Enabled + ON = 0x1, +} + +/// Primary Oscillator Configuration +pub enum POSCMOD { + /// External clock mode + EC = 0x0, + + /// XT osc mode + XT = 0x1, + + /// HS osc mode + HS = 0x2, + + /// Primary osc disabled + OFF = 0x3, +} + +/// CLKO Output Signal Active on the OSCO Pin +pub enum OSCIOFNC { + /// Disabled + OFF = 0x1, + + /// Enabled + ON = 0x0, +} + +/// Peripheral Clock Divisor +pub enum FPBDIV { + /// Pb_Clk is Sys_Clk/1 + DIV_1 = 0x0, + + /// Pb_Clk is Sys_Clk/2 + DIV_2 = 0x1, + + /// Pb_Clk is Sys_Clk/4 + DIV_4 = 0x2, + + /// Pb_Clk is Sys_Clk/8 + DIV_8 = 0x3, +} + +/// Clock Switching and Monitor Selection +pub enum FCKSM { + /// Clock Switch Enable, FSCM Enabled + CSECME = 0x0, + + /// Clock Switch Enable, FSCM Disabled + CSECMD = 0x1, + + /// Clock Switch Disable, FSCM Disabled + CSDCMD = 0x3, +} + +/// Watchdog Timer Postscaler +pub enum WDTPS { + /// 1:1 + PS1 = 0x0, + + /// 1:2 + PS2 = 0x1, + + /// 1:4 + PS4 = 0x2, + + /// 1:8 + PS8 = 0x3, + + /// 1:16 + PS16 = 0x4, + + /// 1:32 + PS32 = 0x5, + + /// 1:64 + PS64 = 0x6, + + /// 1:128 + PS128 = 0x7, + + /// 1:256 + PS256 = 0x8, + + /// 1:512 + PS512 = 0x9, + + /// 1:1024 + PS1024 = 0xa, + + /// 1:2048 + PS2048 = 0xb, + + /// 1:4096 + PS4096 = 0xc, + + /// 1:8192 + PS8192 = 0xd, + + /// 1:16384 + PS16384 = 0xe, + + /// 1:32768 + PS32768 = 0xf, + + /// 1:65536 + PS65536 = 0x10, + + /// 1:131072 + PS131072 = 0x11, + + /// 1:262144 + PS262144 = 0x12, + + /// 1:524288 + PS524288 = 0x13, + + /// 1:1048576 + PS1048576 = 0x14, +} + +/// Watchdog Timer Enable +pub enum FWDTEN { + /// WDT Disabled (SWDTEN Bit Controls) + OFF = 0x0, + + /// WDT Enabled + ON = 0x1, +} + +/// Background Debugger Enable +pub enum DEBUG { + /// Debugger is enabled + ON = 0x2, + + /// Debugger is disabled + OFF = 0x3, +} + +/// ICE/ICD Comm Channel Select +pub enum ICESEL { + /// ICE EMUC1/EMUD1 pins shared with PGC1/PGD1 + ICS_PGx1 = 0x0, + + /// ICE EMUC2/EMUD2 pins shared with PGC2/PGD2 + ICS_PGx2 = 0x1, +} + +/// Program Flash Write Protect +pub enum PWP { + /// Disable + OFF = 0xff, + + /// First 4K + PWP4K = 0xfe, + + /// First 8K + PWP8K = 0xfd, + + /// First 12K + PWP12K = 0xfc, + + /// First 16K + PWP16K = 0xfb, + + /// First 20K + PWP20K = 0xfa, + + /// First 24K + PWP24K = 0xf9, + + /// First 28K + PWP28K = 0xf8, + + /// First 32K + PWP32K = 0xf7, + + /// First 36K + PWP36K = 0xf6, + + /// First 40K + PWP40K = 0xf5, + + /// First 44K + PWP44K = 0xf4, + + /// First 48K + PWP48K = 0xf3, + + /// First 52K + PWP52K = 0xf2, + + /// First 56K + PWP56K = 0xf1, + + /// First 60K + PWP60K = 0xf0, + + /// First 64K + PWP64K = 0xef, + + /// First 68K + PWP68K = 0xee, + + /// First 72K + PWP72K = 0xed, + + /// First 76K + PWP76K = 0xec, + + /// First 80K + PWP80K = 0xeb, + + /// First 84K + PWP84K = 0xea, + + /// First 88K + PWP88K = 0xe9, + + /// First 92K + PWP92K = 0xe8, + + /// First 96K + PWP96K = 0xe7, + + /// First 100K + PWP100K = 0xe6, + + /// First 104K + PWP104K = 0xe5, + + /// First 108K + PWP108K = 0xe4, + + /// First 112K + PWP112K = 0xe3, + + /// First 116K + PWP116K = 0xe2, + + /// First 120K + PWP120K = 0xe1, + + /// First 124K + PWP124K = 0xe0, + + /// First 128K + PWP128K = 0xdf, + + /// First 132K + PWP132K = 0xde, + + /// First 136K + PWP136K = 0xdd, + + /// First 140K + PWP140K = 0xdc, + + /// First 144K + PWP144K = 0xdb, + + /// First 148K + PWP148K = 0xda, + + /// First 152K + PWP152K = 0xd9, + + /// First 156K + PWP156K = 0xd8, + + /// First 160K + PWP160K = 0xd7, + + /// First 164K + PWP164K = 0xd6, + + /// First 168K + PWP168K = 0xd5, + + /// First 172K + PWP172K = 0xd4, + + /// First 176K + PWP176K = 0xd3, + + /// First 180K + PWP180K = 0xd2, + + /// First 184K + PWP184K = 0xd1, + + /// First 188K + PWP188K = 0xd0, + + /// First 192K + PWP192K = 0xcf, + + /// First 196K + PWP196K = 0xce, + + /// First 200K + PWP200K = 0xcd, + + /// First 204K + PWP204K = 0xcc, + + /// First 208K + PWP208K = 0xcb, + + /// First 212K + PWP212K = 0xca, + + /// First 216K + PWP216K = 0xc9, + + /// First 220K + PWP220K = 0xc8, + + /// First 224K + PWP224K = 0xc7, + + /// First 228K + PWP228K = 0xc6, + + /// First 232K + PWP232K = 0xc5, + + /// First 236K + PWP236K = 0xc4, + + /// First 240K + PWP240K = 0xc3, + + /// First 244K + PWP244K = 0xc2, + + /// First 248K + PWP248K = 0xc1, + + /// First 252K + PWP252K = 0xc0, + + /// First 256K + PWP256K = 0xbf, + + /// First 260K + PWP260K = 0xbe, + + /// First 264K + PWP264K = 0xbd, + + /// First 268K + PWP268K = 0xbc, + + /// First 272K + PWP272K = 0xbb, + + /// First 276K + PWP276K = 0xba, + + /// First 280K + PWP280K = 0xb9, + + /// First 284K + PWP284K = 0xb8, + + /// First 288K + PWP288K = 0xb7, + + /// First 292K + PWP292K = 0xb6, + + /// First 296K + PWP296K = 0xb5, + + /// First 300K + PWP300K = 0xb4, + + /// First 304K + PWP304K = 0xb3, + + /// First 308K + PWP308K = 0xb2, + + /// First 312K + PWP312K = 0xb1, + + /// First 316K + PWP316K = 0xb0, + + /// First 320K + PWP320K = 0xaf, + + /// First 324K + PWP324K = 0xae, + + /// First 328K + PWP328K = 0xad, + + /// First 332K + PWP332K = 0xac, + + /// First 336K + PWP336K = 0xab, + + /// First 340K + PWP340K = 0xaa, + + /// First 344K + PWP344K = 0xa9, + + /// First 348K + PWP348K = 0xa8, + + /// First 352K + PWP352K = 0xa7, + + /// First 356K + PWP356K = 0xa6, + + /// First 360K + PWP360K = 0xa5, + + /// First 364K + PWP364K = 0xa4, + + /// First 368K + PWP368K = 0xa3, + + /// First 372K + PWP372K = 0xa2, + + /// First 376K + PWP376K = 0xa1, + + /// First 380K + PWP380K = 0xa0, + + /// First 384K + PWP384K = 0x9f, + + /// First 388K + PWP388K = 0x9e, + + /// First 392K + PWP392K = 0x9d, + + /// First 396K + PWP396K = 0x9c, + + /// First 400K + PWP400K = 0x9b, + + /// First 404K + PWP404K = 0x9a, + + /// First 408K + PWP408K = 0x99, + + /// First 412K + PWP412K = 0x98, + + /// First 416K + PWP416K = 0x97, + + /// First 420K + PWP420K = 0x96, + + /// First 424K + PWP424K = 0x95, + + /// First 428K + PWP428K = 0x94, + + /// First 432K + PWP432K = 0x93, + + /// First 436K + PWP436K = 0x92, + + /// First 440K + PWP440K = 0x91, + + /// First 444K + PWP444K = 0x90, + + /// First 448K + PWP448K = 0x8f, + + /// First 452K + PWP452K = 0x8e, + + /// First 456K + PWP456K = 0x8d, + + /// First 460K + PWP460K = 0x8c, + + /// First 464K + PWP464K = 0x8b, + + /// First 468K + PWP468K = 0x8a, + + /// First 472K + PWP472K = 0x89, + + /// First 476K + PWP476K = 0x88, + + /// First 480K + PWP480K = 0x87, + + /// First 484K + PWP484K = 0x86, + + /// First 488K + PWP488K = 0x85, + + /// First 492K + PWP492K = 0x84, + + /// First 496K + PWP496K = 0x83, + + /// First 500K + PWP500K = 0x82, + + /// First 504K + PWP504K = 0x81, + + /// First 508K + PWP508K = 0x80, + + /// First 512K + PWP512K = 0x7f, +} + +/// Boot Flash Write Protect bit +pub enum BWP { + /// Protection Enabled + ON = 0x0, + + /// Protection Disabled + OFF = 0x1, +} + +/// Code Protect +pub enum CP { + /// Protection Enabled + ON = 0x0, + + /// Protection Disabled + OFF = 0x1, +} + +/// Configuration word sector +#[repr(C)] +pub struct ConfigSector { + DEVCFG3: u32, + DEVCFG2: u32, + DEVCFG1: u32, + DEVCFG0: u32, +} + +impl ConfigSector { + /// Create a builder + pub const fn default() -> ConfigSectorBuilder { + ConfigSectorBuilder { + DEVCFG3: 0xffffffff, + DEVCFG2: 0xffffffff, + DEVCFG1: 0xffffffff, + DEVCFG0: 0x7fffffff, + } + } + + /// Convert into a array of 32 bit words consuming this ConfigSector + pub const fn into_array(self) -> [u32; CONFIG_SECTOR_LENGTH] { + [self.DEVCFG3, self.DEVCFG2, self.DEVCFG1, self.DEVCFG0] + } +} +/// Configuration word sector builder +pub struct ConfigSectorBuilder { + DEVCFG3: u32, + DEVCFG2: u32, + DEVCFG1: u32, + DEVCFG0: u32, +} + +impl ConfigSectorBuilder { + pub const fn USERID(mut self, v: USERID) -> Self { + self.DEVCFG3 &= !0x0000ffff; + self.DEVCFG3 |= v as u32; + self + } + + pub const fn FSRSSEL(mut self, v: FSRSSEL) -> Self { + self.DEVCFG3 &= !0x00070000; + self.DEVCFG3 |= (v as u32) << 16; + self + } + + pub const fn FMIIEN(mut self, v: FMIIEN) -> Self { + self.DEVCFG3 &= !0x01000000; + self.DEVCFG3 |= (v as u32) << 24; + self + } + + pub const fn FETHIO(mut self, v: FETHIO) -> Self { + self.DEVCFG3 &= !0x02000000; + self.DEVCFG3 |= (v as u32) << 25; + self + } + + pub const fn FUSBIDIO(mut self, v: FUSBIDIO) -> Self { + self.DEVCFG3 &= !0x40000000; + self.DEVCFG3 |= (v as u32) << 30; + self + } + + pub const fn FVBUSONIO(mut self, v: FVBUSONIO) -> Self { + self.DEVCFG3 &= !0x80000000; + self.DEVCFG3 |= (v as u32) << 31; + self + } + + pub const fn FPLLIDIV(mut self, v: FPLLIDIV) -> Self { + self.DEVCFG2 &= !0x00000007; + self.DEVCFG2 |= v as u32; + self + } + + pub const fn FPLLMUL(mut self, v: FPLLMUL) -> Self { + self.DEVCFG2 &= !0x00000070; + self.DEVCFG2 |= (v as u32) << 4; + self + } + + pub const fn UPLLIDIV(mut self, v: UPLLIDIV) -> Self { + self.DEVCFG2 &= !0x00000700; + self.DEVCFG2 |= (v as u32) << 8; + self + } + + pub const fn UPLLEN(mut self, v: UPLLEN) -> Self { + self.DEVCFG2 &= !0x00008000; + self.DEVCFG2 |= (v as u32) << 15; + self + } + + pub const fn FPLLODIV(mut self, v: FPLLODIV) -> Self { + self.DEVCFG2 &= !0x00070000; + self.DEVCFG2 |= (v as u32) << 16; + self + } + + pub const fn FNOSC(mut self, v: FNOSC) -> Self { + self.DEVCFG1 &= !0x00000007; + self.DEVCFG1 |= v as u32; + self + } + + pub const fn FSOSCEN(mut self, v: FSOSCEN) -> Self { + self.DEVCFG1 &= !0x00000020; + self.DEVCFG1 |= (v as u32) << 5; + self + } + + pub const fn IESO(mut self, v: IESO) -> Self { + self.DEVCFG1 &= !0x00000080; + self.DEVCFG1 |= (v as u32) << 7; + self + } + + pub const fn POSCMOD(mut self, v: POSCMOD) -> Self { + self.DEVCFG1 &= !0x00000300; + self.DEVCFG1 |= (v as u32) << 8; + self + } + + pub const fn OSCIOFNC(mut self, v: OSCIOFNC) -> Self { + self.DEVCFG1 &= !0x00000400; + self.DEVCFG1 |= (v as u32) << 10; + self + } + + pub const fn FPBDIV(mut self, v: FPBDIV) -> Self { + self.DEVCFG1 &= !0x00003000; + self.DEVCFG1 |= (v as u32) << 12; + self + } + + pub const fn FCKSM(mut self, v: FCKSM) -> Self { + self.DEVCFG1 &= !0x0000c000; + self.DEVCFG1 |= (v as u32) << 14; + self + } + + pub const fn WDTPS(mut self, v: WDTPS) -> Self { + self.DEVCFG1 &= !0x001f0000; + self.DEVCFG1 |= (v as u32) << 16; + self + } + + pub const fn FWDTEN(mut self, v: FWDTEN) -> Self { + self.DEVCFG1 &= !0x00800000; + self.DEVCFG1 |= (v as u32) << 23; + self + } + + pub const fn DEBUG(mut self, v: DEBUG) -> Self { + self.DEVCFG0 &= !0x00000003; + self.DEVCFG0 |= v as u32; + self + } + + pub const fn ICESEL(mut self, v: ICESEL) -> Self { + self.DEVCFG0 &= !0x00000008; + self.DEVCFG0 |= (v as u32) << 3; + self + } + + pub const fn PWP(mut self, v: PWP) -> Self { + self.DEVCFG0 &= !0x000ff000; + self.DEVCFG0 |= (v as u32) << 12; + self + } + + pub const fn BWP(mut self, v: BWP) -> Self { + self.DEVCFG0 &= !0x01000000; + self.DEVCFG0 |= (v as u32) << 24; + self + } + + pub const fn CP(mut self, v: CP) -> Self { + self.DEVCFG0 &= !0x10000000; + self.DEVCFG0 |= (v as u32) << 28; + self + } + + pub const fn build(self) -> ConfigSector { + ConfigSector { + DEVCFG3: self.DEVCFG3, + DEVCFG2: self.DEVCFG2, + DEVCFG1: self.DEVCFG1, + DEVCFG0: self.DEVCFG0, + } + } +} diff --git a/pic32-hal/Cargo.toml b/pic32-hal/Cargo.toml index 3fe6467..2d4849e 100644 --- a/pic32-hal/Cargo.toml +++ b/pic32-hal/Cargo.toml @@ -1,6 +1,6 @@ [package] name = "pic32-hal" -version = "0.9.0" +version = "0.10.0" authors = ["Stephan "] edition = "2021" description = "Hardware Abstraction Layer (HAL) for PIC32 microcontrollers" @@ -14,6 +14,8 @@ include = ["README.md", "/src", "/build.rs"] pic32mx1xxfxxxb = ["pic32mx2xx/pic32mx1xxfxxxb", "device-selected"] pic32mx2xxfxxxb = ["pic32mx2xx/pic32mx2xxfxxxb", "device-selected"] pic32mx2x4fxxxb = ["pic32mx2xx/pic32mx2x4fxxxb", "device-selected"] +pic32mx37x = ["pic32mx470/pic32mx37xfxxxl", "device-selected"] +pic32mx47x = ["pic32mx470/pic32mx47xfxxxl", "device-selected"] device-selected = [] [dependencies] @@ -28,6 +30,12 @@ enumflags2 = "0.7.7" [dependencies.pic32mx2xx] version = "0.7.0" features = ["rt", "critical-section"] +optional = true + +[dependencies.pic32mx470] +version = "0.1.0" +features = ["rt", "critical-section"] +optional = true [package.metadata.docs.rs] features = ["pic32mx2xxfxxxb", "usb-device"] diff --git a/pic32-hal/check_all b/pic32-hal/check_all new file mode 100755 index 0000000..5e96855 --- /dev/null +++ b/pic32-hal/check_all @@ -0,0 +1,20 @@ +#!/usr/bin/sh +# check and clippy for all reasonable feature combinations + +cargo_check() { + local features=$1 + echo "cargo check --features $features" + cargo check --features $features || exit + cargo clippy --features $features || exit + echo +} + + +cargo_check pic32mx1xxfxxxb +cargo_check pic32mx2xxfxxxb +cargo_check pic32mx2xxfxxxb,usb-device +cargo_check pic32mx2x4fxxxb +cargo_check pic32mx2x4fxxxb,usb-device +cargo_check pic32mx37x +cargo_check pic32mx47x +cargo_check pic32mx47x,usb-device diff --git a/pic32-hal/edc2ports.py b/pic32-hal/edc2ports.py new file mode 100755 index 0000000..a7dcfc4 --- /dev/null +++ b/pic32-hal/edc2ports.py @@ -0,0 +1,109 @@ +#!/usr/bin/python3 +# +# Copyright (c) 2021, 2023 Stephan +# +# SPDX-License-Identifier: MIT OR Apache-2.0 + +""" +edc2pps.py +Create PIC32 port tables from .PIC XML files +""" + +import datetime as dt +import argparse +import xml.etree.ElementTree as ET +import sys +import pycurl +from io import BytesIO +from pathlib import Path + +BASE_URL = 'https://raw.githubusercontent.com/kiffie/pic32-pac/master' +BASE_DIR = f'file:{Path.cwd()}/../..' +MCU_VARIANTS = { + 'pic32mx1xxfxxxb': BASE_URL + '/pic32mx2xx/pic32mx1xxfxxxb/PIC32MX170F256B.PIC', + 'pic32mx2xxfxxxb': BASE_URL + '/pic32mx2xx/pic32mx2xxfxxxb/PIC32MX270F256B.PIC', + 'pic32mx2x4fxxxb': BASE_URL + '/pic32mx2xx/pic32mx2x4fxxxb/PIC32MX274F256B.PIC', + 'pic32mx37x': BASE_DIR + '/pic32-pac/pic32mx470/pic32mx37xfxxxl/PIC32MX370F512L.PIC', + 'pic32mx47x': BASE_DIR + '/pic32-pac/pic32mx470/pic32mx47xfxxxl/PIC32MX470F512L.PIC', +} + + +def generate_tables(edc_root, mcu): + out = '' + # find pin list + ns = {'edc': 'http://crownking/edc'} + + ports = {} + for letter in "ABCDEFGHIJ": + port_reg = edc_root.find(f".//edc:SFRDef[@{{http://crownking/edc}}cname='PORT{letter}']", ns) + if not port_reg: + continue + ansel_reg = edc_root.find(f".//edc:SFRDef[@{{http://crownking/edc}}cname='ANSEL{letter}']", ns) + port_access = port_reg.get('{http://crownking/edc}access') + ansel_access = ansel_reg.get('{http://crownking/edc}access') + port_desc = "" + for (p, a) in zip(port_access, ansel_access): + if p != 'n': + code = "-" + elif a == 'n': + code = "a" + else: + code = "d" + port_desc += code + if len(port_desc) != 32: + msg = f"unexpected length of bitmask of PORT{letter}" + raise Exception(msg) + ports[letter] = port_desc + + out += f"// Port definitions for {mcu}\n" + out += "//\n" + for (letter, desc) in ports.items(): + out += f"// PORT{letter}: {desc}\n" + out += "//\n" + + for (letter, desc) in ports.items(): + llc = letter.lower() + out += f'#[cfg(feature = "{mcu}")]\n' + out += f"port!(PORT{letter}, port{llc}, [\n" + for (i, c) in enumerate(reversed(desc)): + match c: + case 'a': + out += f" R{letter}{i}: (r{llc}{i}, {i}, Input, true),\n" + case 'd': + out += f" R{letter}{i}: (r{llc}{i}, {i}, Input),\n" + out += "]);\n\n" + + return out + + +def parseargs(): + parser = argparse.ArgumentParser() + parser.add_argument("-o", "--output", help="path to output file") + args = parser.parse_args() + return args + + +def main(): + args = parseargs() + + if args.output: + out = open(args.output, 'w') + else: + out = sys.stdout + + timestamp = dt.datetime.now(dt.timezone.utc) + print(f'// generated by edc2ports on {timestamp}\n', file=out) + for (mcu, edc_url) in iter(MCU_VARIANTS.items()): + buf = BytesIO() + curl = pycurl.Curl() + curl.setopt(curl.URL, edc_url) + curl.setopt(curl.WRITEDATA, buf) + curl.perform() + curl.close() + edc_text = buf.getvalue().decode('utf-8') + table = generate_tables(ET.fromstring(edc_text), mcu) + print(table, file=out) + + +if __name__ == "__main__": + main() diff --git a/pic32-hal/edc2pps.py b/pic32-hal/edc2pps.py index 6c09e20..c353e48 100755 --- a/pic32-hal/edc2pps.py +++ b/pic32-hal/edc2pps.py @@ -1,41 +1,48 @@ #!/usr/bin/python3 # -# Copyright (c) 2021 Stephan +# Copyright (c) 2021, 2023 Stephan # # SPDX-License-Identifier: MIT OR Apache-2.0 """ edc2pps.py -Create a PIC32 PPS tables from .PIC XML files +Create PIC32 PPS tables from .PIC XML files """ import datetime as dt import argparse import xml.etree.ElementTree as ET import sys -import requests +import pycurl +from io import BytesIO +from pathlib import Path -BASE_URL = 'https://raw.githubusercontent.com/kiffie/pic32-pac/master/pic32mx2xx' +BASE_URL = 'https://raw.githubusercontent.com/kiffie/pic32-pac/master' +BASE_DIR = f'file:{Path.cwd()}/../..' MCU_VARIANTS = { - 'pic32mx1xxfxxxb': BASE_URL + '/pic32mx1xxfxxxb/PIC32MX170F256B.PIC', - 'pic32mx2xxfxxxb': BASE_URL + '/pic32mx2xxfxxxb/PIC32MX270F256B.PIC', - 'pic32mx2x4fxxxb': BASE_URL + '/pic32mx2x4fxxxb/PIC32MX274F256B.PIC' + 'pic32mx1xxfxxxb': BASE_URL + '/pic32mx2xx/pic32mx1xxfxxxb/PIC32MX170F256B.PIC', + 'pic32mx2xxfxxxb': BASE_URL + '/pic32mx2xx/pic32mx2xxfxxxb/PIC32MX270F256B.PIC', + 'pic32mx2x4fxxxb': BASE_URL + '/pic32mx2xx/pic32mx2x4fxxxb/PIC32MX274F256B.PIC', + 'pic32mx37x': BASE_DIR + '/pic32-pac/pic32mx470/pic32mx37xfxxxl/PIC32MX370F512L.PIC', + 'pic32mx47x': BASE_DIR + '/pic32-pac/pic32mx470/pic32mx47xfxxxl/PIC32MX470F512L.PIC' } def generate_tables(edc_root): out = '' - # find pin list ns = {'edc': 'http://crownking/edc'} - pin_list = edc_root.find('.//edc:PinList', ns) pps_pins = [] - for pin in pin_list.findall('./edc:Pin/edc:VirtualPin[@{http://crownking/edc}ppsgroup]', ns): + pin_list = edc_root.find('.//edc:PinList', ns) + for pin in pin_list.findall('.//edc:Pin/edc:VirtualPin[@{http://crownking/edc}ppsgroup]', ns): name = 'R' + pin.get('{http://crownking/edc}name')[2:] + reg_name = pin.get('{http://crownking/edc}name') + 'R' + if not edc_root.find(f'.//edc:SFRDef[@{{http://crownking/edc}}name="{reg_name}"]', ns): + reg_name = None pps_group = pin.get('{http://crownking/edc}ppsgroup') pps_value = pin.get('{http://crownking/edc}ppsval') if not name in map(lambda x: x[0], pps_pins): - pps_pins.append((name, pps_group, pps_value)) + pps_pins.append((name, pps_group, pps_value, reg_name)) pps_pins.sort(key=lambda x: 0x100 * x[1] + x[2]) inputs = [] @@ -65,23 +72,24 @@ def generate_tables(edc_root): type_name = pin[0].upper() + pin[1:].lower() reg = pin.lower() + 'r' out += f" {type_name}, {reg} {{ // PPS group #{pps_group}\n" - for (pname, pgrp, pval) in pps_pins: + for (pname, pgrp, pval, _) in pps_pins: if pgrp == pps_group: port_letter = pname[1].lower() out += f" gpio::port{port_letter}::{pname}, {pval};\n" out += ' }\n' out += ' }{ // virtual output mapping table\n' - for (pname, pgrp, pval) in pps_pins: + for (pname, pgrp, pval, reg_name) in pps_pins: type_name = pname[0].upper() + pname[1:].lower() port_letter = pname[1].lower() - reg = 'rp' + pname[1:].lower() + 'r' - out += f' gpio::port{port_letter}::{pname}, {reg} {{ // PPS group #{pgrp}\n' - for (name, group, val) in sorted(outputs, key=lambda x: x[2]): - type_name = name[0].upper() + name[1:].lower() - if group == pgrp: - out += f' {type_name}, {val};\n' - out += " }\n" + if reg_name: + reg = reg_name.lower() + out += f' gpio::port{port_letter}::{pname}, {reg} {{ // PPS group #{pgrp}\n' + for (name, group, val) in sorted(outputs, key=lambda x: x[2]): + type_name = name[0].upper() + name[1:].lower() + if group == pgrp: + out += f' {type_name}, {val};\n' + out += " }\n" out += ' }\n}\n' return out @@ -104,7 +112,13 @@ def main(): timestamp = dt.datetime.now(dt.timezone.utc) print(f'//generated by edc2pps on {timestamp}\n', file=out) for (mcu, edc_url) in iter(MCU_VARIANTS.items()): - edc_text = requests.get(edc_url).text + buf = BytesIO() + curl = pycurl.Curl() + curl.setopt(curl.URL, edc_url) + curl.setopt(curl.WRITEDATA, buf) + curl.perform() + curl.close() + edc_text = buf.getvalue().decode('utf-8') table = generate_tables(ET.fromstring(edc_text)) print(f'#[cfg(feature = "{mcu}")]\n{table}', file=out) diff --git a/pic32-hal/src/clock.rs b/pic32-hal/src/clock.rs index 54f59eb..755454f 100644 --- a/pic32-hal/src/clock.rs +++ b/pic32-hal/src/clock.rs @@ -11,7 +11,9 @@ use core::marker::PhantomData; feature = "pic32mx1xxfxxxb", feature = "pic32mx2xxfxxxb", feature = "pic32mx2x4fxxxb", - feature = "pic32mx4xxfxxxh" + feature = "pic32mx4xxfxxxh", + feature = "pic32mx37x", + feature = "pic32mx47x", ))] pub mod refclock; @@ -21,7 +23,9 @@ use crate::pac::CRU; #[cfg(any( feature = "pic32mx1xxfxxxb", feature = "pic32mx2xxfxxxb", - feature = "pic32mx4xxfxxxh" + feature = "pic32mx4xxfxxxh", + feature = "pic32mx37x", + feature = "pic32mx47x", ))] use crate::pac::OSC; @@ -34,7 +38,9 @@ pub struct Osc { #[cfg(any( feature = "pic32mx1xxfxxxb", feature = "pic32mx2xxfxxxb", - feature = "pic32mx4xxfxxxh" + feature = "pic32mx4xxfxxxh", + feature = "pic32mx37x", + feature = "pic32mx47x", ))] pub struct Osc { osc: OSC, @@ -94,7 +100,9 @@ impl Osc { #[cfg(any( feature = "pic32mx1xxfxxxb", feature = "pic32mx2xxfxxxb", - feature = "pic32mx4xxfxxxh" + feature = "pic32mx4xxfxxxh", + feature = "pic32mx37x", + feature = "pic32mx47x", ))] impl Osc { /// Create a new `Osc` from a possibly constant sysclock value. The sysclock diff --git a/pic32-hal/src/clock/refclock.rs b/pic32-hal/src/clock/refclock.rs index a0f01d5..73e033b 100644 --- a/pic32-hal/src/clock/refclock.rs +++ b/pic32-hal/src/clock/refclock.rs @@ -5,7 +5,9 @@ use core::marker::PhantomData; #[cfg(any( feature = "pic32mx1xxfxxxb", feature = "pic32mx2xxfxxxb", - feature = "pic32mx4xxfxxxh" + feature = "pic32mx4xxfxxxh", + feature = "pic32mx37x", + feature = "pic32mx47x", ))] use crate::pac::{osc::RegisterBlock, OSC}; @@ -37,7 +39,9 @@ pub struct Refclock { #[cfg(any( feature = "pic32mx1xxfxxxb", feature = "pic32mx2xxfxxxb", - feature = "pic32mx4xxfxxxh" + feature = "pic32mx4xxfxxxh", + feature = "pic32mx37x", + feature = "pic32mx47x", ))] macro_rules! regs { () => { diff --git a/pic32-hal/src/gpio.rs b/pic32-hal/src/gpio.rs index 919dbcd..4b12be7 100644 --- a/pic32-hal/src/gpio.rs +++ b/pic32-hal/src/gpio.rs @@ -46,8 +46,10 @@ macro_rules! port { use crate::hal::digital::v2::*; use crate::pac::$PORTX; + #[allow(unused_imports)] + use super::Analog; use super::{ - Analog, Floating, GpioExt, Input, OpenDrain, Output, + Floating, GpioExt, Input, OpenDrain, Output, PullDown, PullUp, PushPull, }; @@ -258,81 +260,4 @@ macro_rules! port { } } -// configuration for general purpose (non-USB) devices -#[cfg(any(feature = "pic32mx1xxfxxxb", feature = "pic32mx2xxfxxxb"))] -port!(PORTA, porta, [ - RA0: (ra0, 0, Input, true), - RA1: (ra1, 1, Input, true), - RA2: (ra2, 2, Input), - RA3: (ra3, 3, Input), - RA4: (ra4, 4, Input), - - RA7: (ra7, 7, Input), - RA8: (ra8, 8, Input), - RA9: (ra9, 9, Input), - RA10: (ra10, 10, Input), -]); - -#[cfg(feature = "pic32mx1xxfxxxb")] -port!(PORTB, portb, [ - RB0: (rb0, 0, Input, true), - RB1: (rb1, 1, Input, true), - RB2: (rb2, 2, Input, true), - RB3: (rb3, 3, Input, true), - RB4: (rb4, 4, Input), - RB5: (rb5, 5, Input), - RB6: (rb6, 6, Input), - RB7: (rb7, 7, Input), - RB8: (rb8, 8, Input), - RB9: (rb9, 9, Input), - RB10: (rb10, 10, Input), - RB11: (rb11, 11, Input), - RB12: (rb12, 12, Input, true), - RB13: (rb13, 13, Input, true), - RB14: (rb14, 14, Input, true), - RB15: (rb15, 15, Input, true), -]); - -#[cfg(feature = "pic32mx2xxfxxxb")] -port!(PORTB, portb, [ - RB0: (rb0, 0, Input, true), - RB1: (rb1, 1, Input, true), - RB2: (rb2, 2, Input, true), - RB3: (rb3, 3, Input, true), - RB4: (rb4, 4, Input), - RB5: (rb5, 5, Input), - RB7: (rb7, 7, Input), - RB8: (rb8, 8, Input), - RB9: (rb9, 9, Input), - RB10: (rb10, 10, Input), - RB11: (rb11, 11, Input), - RB13: (rb13, 13, Input, true), - RB14: (rb14, 14, Input, true), - RB15: (rb15, 15, Input, true), -]); - -// PIC32MX2xx 28pin XLP USB devices -#[cfg(feature = "pic32mx2x4fxxxb")] -port!(PORTA, porta, [ - RA0: (ra0, 0, Input, true), - RA1: (ra1, 1, Input, true), - RA2: (ra2, 2, Input), - RA3: (ra3, 3, Input), - RA4: (ra4, 4, Input), -]); - -#[cfg(feature = "pic32mx2x4fxxxb")] -port!(PORTB, portb, [ - RB0: (rb0, 0, Input, true), - RB1: (rb1, 1, Input, true), - RB2: (rb2, 2, Input, true), - RB3: (rb3, 3, Input, true), - RB4: (rb4, 4, Input), - RB5: (rb5, 5, Input), - RB7: (rb7, 7, Input), - RB8: (rb8, 8, Input), - RB9: (rb9, 9, Input), - RB13: (rb13, 13, Input, true), - RB14: (rb14, 14, Input, true), - RB15: (rb15, 15, Input, true), -]); +include!("gpio_tables.rs"); diff --git a/pic32-hal/src/gpio_tables.rs b/pic32-hal/src/gpio_tables.rs new file mode 100644 index 0000000..f5c8fdb --- /dev/null +++ b/pic32-hal/src/gpio_tables.rs @@ -0,0 +1,345 @@ +// generated by edc2ports on 2023-06-17 13:44:48.238228+00:00 + +// Port definitions for pic32mx1xxfxxxb +// +// PORTA: ---------------------------dddaa +// PORTB: ----------------aaaaddddddddaaaa +// +#[cfg(feature = "pic32mx1xxfxxxb")] +port!(PORTA, porta, [ + RA0: (ra0, 0, Input, true), + RA1: (ra1, 1, Input, true), + RA2: (ra2, 2, Input), + RA3: (ra3, 3, Input), + RA4: (ra4, 4, Input), +]); + +#[cfg(feature = "pic32mx1xxfxxxb")] +port!(PORTB, portb, [ + RB0: (rb0, 0, Input, true), + RB1: (rb1, 1, Input, true), + RB2: (rb2, 2, Input, true), + RB3: (rb3, 3, Input, true), + RB4: (rb4, 4, Input), + RB5: (rb5, 5, Input), + RB6: (rb6, 6, Input), + RB7: (rb7, 7, Input), + RB8: (rb8, 8, Input), + RB9: (rb9, 9, Input), + RB10: (rb10, 10, Input), + RB11: (rb11, 11, Input), + RB12: (rb12, 12, Input, true), + RB13: (rb13, 13, Input, true), + RB14: (rb14, 14, Input, true), + RB15: (rb15, 15, Input, true), +]); + + +// Port definitions for pic32mx2xxfxxxb +// +// PORTA: ---------------------------dddaa +// PORTB: ----------------aaa-ddddd-ddaaaa +// +#[cfg(feature = "pic32mx2xxfxxxb")] +port!(PORTA, porta, [ + RA0: (ra0, 0, Input, true), + RA1: (ra1, 1, Input, true), + RA2: (ra2, 2, Input), + RA3: (ra3, 3, Input), + RA4: (ra4, 4, Input), +]); + +#[cfg(feature = "pic32mx2xxfxxxb")] +port!(PORTB, portb, [ + RB0: (rb0, 0, Input, true), + RB1: (rb1, 1, Input, true), + RB2: (rb2, 2, Input, true), + RB3: (rb3, 3, Input, true), + RB4: (rb4, 4, Input), + RB5: (rb5, 5, Input), + RB7: (rb7, 7, Input), + RB8: (rb8, 8, Input), + RB9: (rb9, 9, Input), + RB10: (rb10, 10, Input), + RB11: (rb11, 11, Input), + RB13: (rb13, 13, Input, true), + RB14: (rb14, 14, Input, true), + RB15: (rb15, 15, Input, true), +]); + + +// Port definitions for pic32mx2x4fxxxb +// +// PORTA: ---------------------------dddaa +// PORTB: ----------------aaa---ddd-ddaaaa +// +#[cfg(feature = "pic32mx2x4fxxxb")] +port!(PORTA, porta, [ + RA0: (ra0, 0, Input, true), + RA1: (ra1, 1, Input, true), + RA2: (ra2, 2, Input), + RA3: (ra3, 3, Input), + RA4: (ra4, 4, Input), +]); + +#[cfg(feature = "pic32mx2x4fxxxb")] +port!(PORTB, portb, [ + RB0: (rb0, 0, Input, true), + RB1: (rb1, 1, Input, true), + RB2: (rb2, 2, Input, true), + RB3: (rb3, 3, Input, true), + RB4: (rb4, 4, Input), + RB5: (rb5, 5, Input), + RB7: (rb7, 7, Input), + RB8: (rb8, 8, Input), + RB9: (rb9, 9, Input), + RB13: (rb13, 13, Input, true), + RB14: (rb14, 14, Input, true), + RB15: (rb15, 15, Input, true), +]); + + +// Port definitions for pic32mx37x +// +// PORTA: ----------------dd---aa-dddddddd +// PORTB: ----------------aaaaaaaaaaaaaaaa +// PORTC: ----------------dddd-------dddd- +// PORTD: ----------------ddddddddddddaaad +// PORTE: ----------------------ddaaaadadd +// PORTF: ------------------dd---ddddddddd +// PORTG: ----------------dddd--aaaa--dddd +// +#[cfg(feature = "pic32mx37x")] +port!(PORTA, porta, [ + RA0: (ra0, 0, Input), + RA1: (ra1, 1, Input), + RA2: (ra2, 2, Input), + RA3: (ra3, 3, Input), + RA4: (ra4, 4, Input), + RA5: (ra5, 5, Input), + RA6: (ra6, 6, Input), + RA7: (ra7, 7, Input), + RA9: (ra9, 9, Input, true), + RA10: (ra10, 10, Input, true), + RA14: (ra14, 14, Input), + RA15: (ra15, 15, Input), +]); + +#[cfg(feature = "pic32mx37x")] +port!(PORTB, portb, [ + RB0: (rb0, 0, Input, true), + RB1: (rb1, 1, Input, true), + RB2: (rb2, 2, Input, true), + RB3: (rb3, 3, Input, true), + RB4: (rb4, 4, Input, true), + RB5: (rb5, 5, Input, true), + RB6: (rb6, 6, Input, true), + RB7: (rb7, 7, Input, true), + RB8: (rb8, 8, Input, true), + RB9: (rb9, 9, Input, true), + RB10: (rb10, 10, Input, true), + RB11: (rb11, 11, Input, true), + RB12: (rb12, 12, Input, true), + RB13: (rb13, 13, Input, true), + RB14: (rb14, 14, Input, true), + RB15: (rb15, 15, Input, true), +]); + +#[cfg(feature = "pic32mx37x")] +port!(PORTC, portc, [ + RC1: (rc1, 1, Input), + RC2: (rc2, 2, Input), + RC3: (rc3, 3, Input), + RC4: (rc4, 4, Input), + RC12: (rc12, 12, Input), + RC13: (rc13, 13, Input), + RC14: (rc14, 14, Input), + RC15: (rc15, 15, Input), +]); + +#[cfg(feature = "pic32mx37x")] +port!(PORTD, portd, [ + RD0: (rd0, 0, Input), + RD1: (rd1, 1, Input, true), + RD2: (rd2, 2, Input, true), + RD3: (rd3, 3, Input, true), + RD4: (rd4, 4, Input), + RD5: (rd5, 5, Input), + RD6: (rd6, 6, Input), + RD7: (rd7, 7, Input), + RD8: (rd8, 8, Input), + RD9: (rd9, 9, Input), + RD10: (rd10, 10, Input), + RD11: (rd11, 11, Input), + RD12: (rd12, 12, Input), + RD13: (rd13, 13, Input), + RD14: (rd14, 14, Input), + RD15: (rd15, 15, Input), +]); + +#[cfg(feature = "pic32mx37x")] +port!(PORTE, porte, [ + RE0: (re0, 0, Input), + RE1: (re1, 1, Input), + RE2: (re2, 2, Input, true), + RE3: (re3, 3, Input), + RE4: (re4, 4, Input, true), + RE5: (re5, 5, Input, true), + RE6: (re6, 6, Input, true), + RE7: (re7, 7, Input, true), + RE8: (re8, 8, Input), + RE9: (re9, 9, Input), +]); + +#[cfg(feature = "pic32mx37x")] +port!(PORTF, portf, [ + RF0: (rf0, 0, Input), + RF1: (rf1, 1, Input), + RF2: (rf2, 2, Input), + RF3: (rf3, 3, Input), + RF4: (rf4, 4, Input), + RF5: (rf5, 5, Input), + RF6: (rf6, 6, Input), + RF7: (rf7, 7, Input), + RF8: (rf8, 8, Input), + RF12: (rf12, 12, Input), + RF13: (rf13, 13, Input), +]); + +#[cfg(feature = "pic32mx37x")] +port!(PORTG, portg, [ + RG0: (rg0, 0, Input), + RG1: (rg1, 1, Input), + RG2: (rg2, 2, Input), + RG3: (rg3, 3, Input), + RG6: (rg6, 6, Input, true), + RG7: (rg7, 7, Input, true), + RG8: (rg8, 8, Input, true), + RG9: (rg9, 9, Input, true), + RG12: (rg12, 12, Input), + RG13: (rg13, 13, Input), + RG14: (rg14, 14, Input), + RG15: (rg15, 15, Input), +]); + + +// Port definitions for pic32mx47x +// +// PORTA: ----------------dd---aa-dddddddd +// PORTB: ----------------aaaaaaaaaaaaaaaa +// PORTC: ----------------dddd-------dddd- +// PORTD: ----------------ddddddddddddaaad +// PORTE: ----------------------ddaaaadadd +// PORTF: ------------------dd---d--dddddd +// PORTG: ----------------dddd--aaaa----dd +// +#[cfg(feature = "pic32mx47x")] +port!(PORTA, porta, [ + RA0: (ra0, 0, Input), + RA1: (ra1, 1, Input), + RA2: (ra2, 2, Input), + RA3: (ra3, 3, Input), + RA4: (ra4, 4, Input), + RA5: (ra5, 5, Input), + RA6: (ra6, 6, Input), + RA7: (ra7, 7, Input), + RA9: (ra9, 9, Input, true), + RA10: (ra10, 10, Input, true), + RA14: (ra14, 14, Input), + RA15: (ra15, 15, Input), +]); + +#[cfg(feature = "pic32mx47x")] +port!(PORTB, portb, [ + RB0: (rb0, 0, Input, true), + RB1: (rb1, 1, Input, true), + RB2: (rb2, 2, Input, true), + RB3: (rb3, 3, Input, true), + RB4: (rb4, 4, Input, true), + RB5: (rb5, 5, Input, true), + RB6: (rb6, 6, Input, true), + RB7: (rb7, 7, Input, true), + RB8: (rb8, 8, Input, true), + RB9: (rb9, 9, Input, true), + RB10: (rb10, 10, Input, true), + RB11: (rb11, 11, Input, true), + RB12: (rb12, 12, Input, true), + RB13: (rb13, 13, Input, true), + RB14: (rb14, 14, Input, true), + RB15: (rb15, 15, Input, true), +]); + +#[cfg(feature = "pic32mx47x")] +port!(PORTC, portc, [ + RC1: (rc1, 1, Input), + RC2: (rc2, 2, Input), + RC3: (rc3, 3, Input), + RC4: (rc4, 4, Input), + RC12: (rc12, 12, Input), + RC13: (rc13, 13, Input), + RC14: (rc14, 14, Input), + RC15: (rc15, 15, Input), +]); + +#[cfg(feature = "pic32mx47x")] +port!(PORTD, portd, [ + RD0: (rd0, 0, Input), + RD1: (rd1, 1, Input, true), + RD2: (rd2, 2, Input, true), + RD3: (rd3, 3, Input, true), + RD4: (rd4, 4, Input), + RD5: (rd5, 5, Input), + RD6: (rd6, 6, Input), + RD7: (rd7, 7, Input), + RD8: (rd8, 8, Input), + RD9: (rd9, 9, Input), + RD10: (rd10, 10, Input), + RD11: (rd11, 11, Input), + RD12: (rd12, 12, Input), + RD13: (rd13, 13, Input), + RD14: (rd14, 14, Input), + RD15: (rd15, 15, Input), +]); + +#[cfg(feature = "pic32mx47x")] +port!(PORTE, porte, [ + RE0: (re0, 0, Input), + RE1: (re1, 1, Input), + RE2: (re2, 2, Input, true), + RE3: (re3, 3, Input), + RE4: (re4, 4, Input, true), + RE5: (re5, 5, Input, true), + RE6: (re6, 6, Input, true), + RE7: (re7, 7, Input, true), + RE8: (re8, 8, Input), + RE9: (re9, 9, Input), +]); + +#[cfg(feature = "pic32mx47x")] +port!(PORTF, portf, [ + RF0: (rf0, 0, Input), + RF1: (rf1, 1, Input), + RF2: (rf2, 2, Input), + RF3: (rf3, 3, Input), + RF4: (rf4, 4, Input), + RF5: (rf5, 5, Input), + RF8: (rf8, 8, Input), + RF12: (rf12, 12, Input), + RF13: (rf13, 13, Input), +]); + +#[cfg(feature = "pic32mx47x")] +port!(PORTG, portg, [ + RG0: (rg0, 0, Input), + RG1: (rg1, 1, Input), + RG6: (rg6, 6, Input, true), + RG7: (rg7, 7, Input, true), + RG8: (rg8, 8, Input, true), + RG9: (rg9, 9, Input, true), + RG12: (rg12, 12, Input), + RG13: (rg13, 13, Input), + RG14: (rg14, 14, Input), + RG15: (rg15, 15, Input), +]); + + diff --git a/pic32-hal/src/lib.rs b/pic32-hal/src/lib.rs index 1f3cf68..7c0e862 100644 --- a/pic32-hal/src/lib.rs +++ b/pic32-hal/src/lib.rs @@ -16,19 +16,31 @@ #[cfg(not(feature = "device-selected"))] compile_error!("This crate requires one device feature to be enabled"); -use pic32mx2xx as pac_crate; #[cfg(feature = "pic32mx1xxfxxxb")] pub use pic32mx2xx::pic32mx1xxfxxxb as pac; +#[cfg(feature = "pic32mx1xxfxxxb")] +use pic32mx2xx as pac_crate; #[cfg(feature = "pic32mx2xxfxxxb")] pub use pic32mx2xx::pic32mx2xxfxxxb as pac; +#[cfg(feature = "pic32mx2xxfxxxb")] +use pic32mx2xx as pac_crate; #[cfg(feature = "pic32mx2x4fxxxb")] pub use pic32mx2xx::pic32mx2x4fxxxb as pac; +#[cfg(feature = "pic32mx2x4fxxxb")] +use pic32mx2xx as pac_crate; + +#[cfg(feature = "pic32mx37x")] +pub use pic32mx470::pic32mx37xfxxxl as pac; +#[cfg(feature = "pic32mx37x")] +use pic32mx470 as pac_crate; -#[cfg(feature = "pic32mx4xxfxxxh")] -pub use pic32mx4xxfxxxh as pac; +#[cfg(feature = "pic32mx47x")] +pub use pic32mx470::pic32mx47xfxxxl as pac; +#[cfg(feature = "pic32mx47x")] +use pic32mx470 as pac_crate; use embedded_hal as hal; @@ -47,7 +59,7 @@ pub mod uart; #[cfg(any( feature = "pic32mx2xxfxxxb", feature = "pic32mx2x4fxxxb", - feature = "pic32mx4xxfxxxh" + feature = "pic32mx47x", ))] #[cfg(feature = "usb-device")] pub mod usb; diff --git a/pic32-hal/src/pps_tables.rs b/pic32-hal/src/pps_tables.rs index eafa2b9..60f8bf3 100644 --- a/pic32-hal/src/pps_tables.rs +++ b/pic32-hal/src/pps_tables.rs @@ -1,4 +1,4 @@ -//generated by edc2pps on 2021-12-30 14:28:11.343674+00:00 +//generated by edc2pps on 2023-06-18 09:59:08.655388+00:00 #[cfg(feature = "pic32mx1xxfxxxb")] pps_tables! { @@ -1011,3 +1011,1869 @@ pps_tables! { } } +#[cfg(feature = "pic32mx37x")] +pps_tables! { + { // virtual input declarations + Int3, int3; // PPS group #1 + T2ck, t2ck; // PPS group #1 + Ic3, ic3; // PPS group #1 + U1rx, u1rx; // PPS group #1 + U2rx, u2rx; // PPS group #1 + U5cts, u5cts; // PPS group #1 + Refclki, refclki; // PPS group #1 + Int4, int4; // PPS group #2 + T5ck, t5ck; // PPS group #2 + Ic4, ic4; // PPS group #2 + U3rx, u3rx; // PPS group #2 + U4cts, u4cts; // PPS group #2 + Sdi1, sdi1; // PPS group #2 + Sdi2, sdi2; // PPS group #2 + Int2, int2; // PPS group #3 + T4ck, t4ck; // PPS group #3 + Ic2, ic2; // PPS group #3 + Ic5, ic5; // PPS group #3 + U1cts, u1cts; // PPS group #3 + U2cts, u2cts; // PPS group #3 + Ss1, ss1; // PPS group #3 + Int1, int1; // PPS group #4 + T3ck, t3ck; // PPS group #4 + Ic1, ic1; // PPS group #4 + U3cts, u3cts; // PPS group #4 + U4rx, u4rx; // PPS group #4 + U5rx, u5rx; // PPS group #4 + Ss2, ss2; // PPS group #4 + Ocfa, ocfa; // PPS group #4 + }{ // virtual output declarations + C1out, c1out; + C2out, c2out; + Oc1, oc1; + Oc2, oc2; + Oc3, oc3; + Oc4, oc4; + Oc5, oc5; + Refclko, refclko; + Sdo1, sdo1; + Sdo2, sdo2; + Ss1, ss1; + Ss2, ss2; + U1rts, u1rts; + U1tx, u1tx; + U2rts, u2rts; + U2tx, u2tx; + U3rts, u3rts; + U3tx, u3tx; + U4rts, u4rts; + U4tx, u4tx; + U5rts, u5rts; + U5tx, u5tx; + }{ // virtual input mapping table + Int3, int3r { // PPS group #1 + gpio::portd::RD2, 0; + gpio::portg::RG8, 1; + gpio::portc::RC1, 10; + gpio::portd::RD14, 11; + gpio::portg::RG1, 12; + gpio::porta::RA14, 13; + gpio::portf::RF2, 15; + gpio::portf::RF4, 2; + gpio::portd::RD10, 3; + gpio::portf::RF1, 4; + gpio::portb::RB9, 5; + gpio::portb::RB10, 6; + gpio::portc::RC14, 7; + gpio::portb::RB5, 8; + } + T2ck, t2ckr { // PPS group #1 + gpio::portd::RD2, 0; + gpio::portg::RG8, 1; + gpio::portc::RC1, 10; + gpio::portd::RD14, 11; + gpio::portg::RG1, 12; + gpio::porta::RA14, 13; + gpio::portf::RF2, 15; + gpio::portf::RF4, 2; + gpio::portd::RD10, 3; + gpio::portf::RF1, 4; + gpio::portb::RB9, 5; + gpio::portb::RB10, 6; + gpio::portc::RC14, 7; + gpio::portb::RB5, 8; + } + Ic3, ic3r { // PPS group #1 + gpio::portd::RD2, 0; + gpio::portg::RG8, 1; + gpio::portc::RC1, 10; + gpio::portd::RD14, 11; + gpio::portg::RG1, 12; + gpio::porta::RA14, 13; + gpio::portf::RF2, 15; + gpio::portf::RF4, 2; + gpio::portd::RD10, 3; + gpio::portf::RF1, 4; + gpio::portb::RB9, 5; + gpio::portb::RB10, 6; + gpio::portc::RC14, 7; + gpio::portb::RB5, 8; + } + U1rx, u1rxr { // PPS group #1 + gpio::portd::RD2, 0; + gpio::portg::RG8, 1; + gpio::portc::RC1, 10; + gpio::portd::RD14, 11; + gpio::portg::RG1, 12; + gpio::porta::RA14, 13; + gpio::portf::RF2, 15; + gpio::portf::RF4, 2; + gpio::portd::RD10, 3; + gpio::portf::RF1, 4; + gpio::portb::RB9, 5; + gpio::portb::RB10, 6; + gpio::portc::RC14, 7; + gpio::portb::RB5, 8; + } + U2rx, u2rxr { // PPS group #1 + gpio::portd::RD2, 0; + gpio::portg::RG8, 1; + gpio::portc::RC1, 10; + gpio::portd::RD14, 11; + gpio::portg::RG1, 12; + gpio::porta::RA14, 13; + gpio::portf::RF2, 15; + gpio::portf::RF4, 2; + gpio::portd::RD10, 3; + gpio::portf::RF1, 4; + gpio::portb::RB9, 5; + gpio::portb::RB10, 6; + gpio::portc::RC14, 7; + gpio::portb::RB5, 8; + } + U5cts, u5ctsr { // PPS group #1 + gpio::portd::RD2, 0; + gpio::portg::RG8, 1; + gpio::portc::RC1, 10; + gpio::portd::RD14, 11; + gpio::portg::RG1, 12; + gpio::porta::RA14, 13; + gpio::portf::RF2, 15; + gpio::portf::RF4, 2; + gpio::portd::RD10, 3; + gpio::portf::RF1, 4; + gpio::portb::RB9, 5; + gpio::portb::RB10, 6; + gpio::portc::RC14, 7; + gpio::portb::RB5, 8; + } + Refclki, refclkir { // PPS group #1 + gpio::portd::RD2, 0; + gpio::portg::RG8, 1; + gpio::portc::RC1, 10; + gpio::portd::RD14, 11; + gpio::portg::RG1, 12; + gpio::porta::RA14, 13; + gpio::portf::RF2, 15; + gpio::portf::RF4, 2; + gpio::portd::RD10, 3; + gpio::portf::RF1, 4; + gpio::portb::RB9, 5; + gpio::portb::RB10, 6; + gpio::portc::RC14, 7; + gpio::portb::RB5, 8; + } + Int4, int4r { // PPS group #2 + gpio::portd::RD3, 0; + gpio::portg::RG7, 1; + gpio::portc::RC4, 10; + gpio::portd::RD15, 11; + gpio::portg::RG0, 12; + gpio::porta::RA15, 13; + gpio::portf::RF7, 15; + gpio::portf::RF5, 2; + gpio::portd::RD11, 3; + gpio::portf::RF0, 4; + gpio::portb::RB1, 5; + gpio::porte::RE5, 6; + gpio::portc::RC13, 7; + gpio::portb::RB3, 8; + } + T5ck, t5ckr { // PPS group #2 + gpio::portd::RD3, 0; + gpio::portg::RG7, 1; + gpio::portc::RC4, 10; + gpio::portd::RD15, 11; + gpio::portg::RG0, 12; + gpio::porta::RA15, 13; + gpio::portf::RF7, 15; + gpio::portf::RF5, 2; + gpio::portd::RD11, 3; + gpio::portf::RF0, 4; + gpio::portb::RB1, 5; + gpio::porte::RE5, 6; + gpio::portc::RC13, 7; + gpio::portb::RB3, 8; + } + Ic4, ic4r { // PPS group #2 + gpio::portd::RD3, 0; + gpio::portg::RG7, 1; + gpio::portc::RC4, 10; + gpio::portd::RD15, 11; + gpio::portg::RG0, 12; + gpio::porta::RA15, 13; + gpio::portf::RF7, 15; + gpio::portf::RF5, 2; + gpio::portd::RD11, 3; + gpio::portf::RF0, 4; + gpio::portb::RB1, 5; + gpio::porte::RE5, 6; + gpio::portc::RC13, 7; + gpio::portb::RB3, 8; + } + U3rx, u3rxr { // PPS group #2 + gpio::portd::RD3, 0; + gpio::portg::RG7, 1; + gpio::portc::RC4, 10; + gpio::portd::RD15, 11; + gpio::portg::RG0, 12; + gpio::porta::RA15, 13; + gpio::portf::RF7, 15; + gpio::portf::RF5, 2; + gpio::portd::RD11, 3; + gpio::portf::RF0, 4; + gpio::portb::RB1, 5; + gpio::porte::RE5, 6; + gpio::portc::RC13, 7; + gpio::portb::RB3, 8; + } + U4cts, u4ctsr { // PPS group #2 + gpio::portd::RD3, 0; + gpio::portg::RG7, 1; + gpio::portc::RC4, 10; + gpio::portd::RD15, 11; + gpio::portg::RG0, 12; + gpio::porta::RA15, 13; + gpio::portf::RF7, 15; + gpio::portf::RF5, 2; + gpio::portd::RD11, 3; + gpio::portf::RF0, 4; + gpio::portb::RB1, 5; + gpio::porte::RE5, 6; + gpio::portc::RC13, 7; + gpio::portb::RB3, 8; + } + Sdi1, sdi1r { // PPS group #2 + gpio::portd::RD3, 0; + gpio::portg::RG7, 1; + gpio::portc::RC4, 10; + gpio::portd::RD15, 11; + gpio::portg::RG0, 12; + gpio::porta::RA15, 13; + gpio::portf::RF7, 15; + gpio::portf::RF5, 2; + gpio::portd::RD11, 3; + gpio::portf::RF0, 4; + gpio::portb::RB1, 5; + gpio::porte::RE5, 6; + gpio::portc::RC13, 7; + gpio::portb::RB3, 8; + } + Sdi2, sdi2r { // PPS group #2 + gpio::portd::RD3, 0; + gpio::portg::RG7, 1; + gpio::portc::RC4, 10; + gpio::portd::RD15, 11; + gpio::portg::RG0, 12; + gpio::porta::RA15, 13; + gpio::portf::RF7, 15; + gpio::portf::RF5, 2; + gpio::portd::RD11, 3; + gpio::portf::RF0, 4; + gpio::portb::RB1, 5; + gpio::porte::RE5, 6; + gpio::portc::RC13, 7; + gpio::portb::RB3, 8; + } + Int2, int2r { // PPS group #3 + gpio::portd::RD9, 0; + gpio::portg::RG6, 1; + gpio::portd::RD12, 10; + gpio::portf::RF8, 11; + gpio::portc::RC3, 12; + gpio::porte::RE9, 13; + gpio::portb::RB2, 15; + gpio::portb::RB8, 2; + gpio::portb::RB15, 3; + gpio::portd::RD4, 4; + gpio::portb::RB0, 5; + gpio::porte::RE3, 6; + gpio::portb::RB7, 7; + gpio::portf::RF12, 9; + } + T4ck, t4ckr { // PPS group #3 + gpio::portd::RD9, 0; + gpio::portg::RG6, 1; + gpio::portd::RD12, 10; + gpio::portf::RF8, 11; + gpio::portc::RC3, 12; + gpio::porte::RE9, 13; + gpio::portb::RB2, 15; + gpio::portb::RB8, 2; + gpio::portb::RB15, 3; + gpio::portd::RD4, 4; + gpio::portb::RB0, 5; + gpio::porte::RE3, 6; + gpio::portb::RB7, 7; + gpio::portf::RF12, 9; + } + Ic2, ic2r { // PPS group #3 + gpio::portd::RD9, 0; + gpio::portg::RG6, 1; + gpio::portd::RD12, 10; + gpio::portf::RF8, 11; + gpio::portc::RC3, 12; + gpio::porte::RE9, 13; + gpio::portb::RB2, 15; + gpio::portb::RB8, 2; + gpio::portb::RB15, 3; + gpio::portd::RD4, 4; + gpio::portb::RB0, 5; + gpio::porte::RE3, 6; + gpio::portb::RB7, 7; + gpio::portf::RF12, 9; + } + Ic5, ic5r { // PPS group #3 + gpio::portd::RD9, 0; + gpio::portg::RG6, 1; + gpio::portd::RD12, 10; + gpio::portf::RF8, 11; + gpio::portc::RC3, 12; + gpio::porte::RE9, 13; + gpio::portb::RB2, 15; + gpio::portb::RB8, 2; + gpio::portb::RB15, 3; + gpio::portd::RD4, 4; + gpio::portb::RB0, 5; + gpio::porte::RE3, 6; + gpio::portb::RB7, 7; + gpio::portf::RF12, 9; + } + U1cts, u1ctsr { // PPS group #3 + gpio::portd::RD9, 0; + gpio::portg::RG6, 1; + gpio::portd::RD12, 10; + gpio::portf::RF8, 11; + gpio::portc::RC3, 12; + gpio::porte::RE9, 13; + gpio::portb::RB2, 15; + gpio::portb::RB8, 2; + gpio::portb::RB15, 3; + gpio::portd::RD4, 4; + gpio::portb::RB0, 5; + gpio::porte::RE3, 6; + gpio::portb::RB7, 7; + gpio::portf::RF12, 9; + } + U2cts, u2ctsr { // PPS group #3 + gpio::portd::RD9, 0; + gpio::portg::RG6, 1; + gpio::portd::RD12, 10; + gpio::portf::RF8, 11; + gpio::portc::RC3, 12; + gpio::porte::RE9, 13; + gpio::portb::RB2, 15; + gpio::portb::RB8, 2; + gpio::portb::RB15, 3; + gpio::portd::RD4, 4; + gpio::portb::RB0, 5; + gpio::porte::RE3, 6; + gpio::portb::RB7, 7; + gpio::portf::RF12, 9; + } + Ss1, ss1r { // PPS group #3 + gpio::portd::RD9, 0; + gpio::portg::RG6, 1; + gpio::portd::RD12, 10; + gpio::portf::RF8, 11; + gpio::portc::RC3, 12; + gpio::porte::RE9, 13; + gpio::portb::RB2, 15; + gpio::portb::RB8, 2; + gpio::portb::RB15, 3; + gpio::portd::RD4, 4; + gpio::portb::RB0, 5; + gpio::porte::RE3, 6; + gpio::portb::RB7, 7; + gpio::portf::RF12, 9; + } + Int1, int1r { // PPS group #4 + gpio::portd::RD1, 0; + gpio::portg::RG9, 1; + gpio::portc::RC2, 12; + gpio::porte::RE8, 13; + gpio::portb::RB14, 2; + gpio::portd::RD0, 3; + gpio::portd::RD8, 4; + gpio::portb::RB6, 5; + gpio::portd::RD5, 6; + gpio::portf::RF3, 8; + gpio::portf::RF13, 9; + } + T3ck, t3ckr { // PPS group #4 + gpio::portd::RD1, 0; + gpio::portg::RG9, 1; + gpio::portc::RC2, 12; + gpio::porte::RE8, 13; + gpio::portb::RB14, 2; + gpio::portd::RD0, 3; + gpio::portd::RD8, 4; + gpio::portb::RB6, 5; + gpio::portd::RD5, 6; + gpio::portf::RF3, 8; + gpio::portf::RF13, 9; + } + Ic1, ic1r { // PPS group #4 + gpio::portd::RD1, 0; + gpio::portg::RG9, 1; + gpio::portc::RC2, 12; + gpio::porte::RE8, 13; + gpio::portb::RB14, 2; + gpio::portd::RD0, 3; + gpio::portd::RD8, 4; + gpio::portb::RB6, 5; + gpio::portd::RD5, 6; + gpio::portf::RF3, 8; + gpio::portf::RF13, 9; + } + U3cts, u3ctsr { // PPS group #4 + gpio::portd::RD1, 0; + gpio::portg::RG9, 1; + gpio::portc::RC2, 12; + gpio::porte::RE8, 13; + gpio::portb::RB14, 2; + gpio::portd::RD0, 3; + gpio::portd::RD8, 4; + gpio::portb::RB6, 5; + gpio::portd::RD5, 6; + gpio::portf::RF3, 8; + gpio::portf::RF13, 9; + } + U4rx, u4rxr { // PPS group #4 + gpio::portd::RD1, 0; + gpio::portg::RG9, 1; + gpio::portc::RC2, 12; + gpio::porte::RE8, 13; + gpio::portb::RB14, 2; + gpio::portd::RD0, 3; + gpio::portd::RD8, 4; + gpio::portb::RB6, 5; + gpio::portd::RD5, 6; + gpio::portf::RF3, 8; + gpio::portf::RF13, 9; + } + U5rx, u5rxr { // PPS group #4 + gpio::portd::RD1, 0; + gpio::portg::RG9, 1; + gpio::portc::RC2, 12; + gpio::porte::RE8, 13; + gpio::portb::RB14, 2; + gpio::portd::RD0, 3; + gpio::portd::RD8, 4; + gpio::portb::RB6, 5; + gpio::portd::RD5, 6; + gpio::portf::RF3, 8; + gpio::portf::RF13, 9; + } + Ss2, ss2r { // PPS group #4 + gpio::portd::RD1, 0; + gpio::portg::RG9, 1; + gpio::portc::RC2, 12; + gpio::porte::RE8, 13; + gpio::portb::RB14, 2; + gpio::portd::RD0, 3; + gpio::portd::RD8, 4; + gpio::portb::RB6, 5; + gpio::portd::RD5, 6; + gpio::portf::RF3, 8; + gpio::portf::RF13, 9; + } + Ocfa, ocfar { // PPS group #4 + gpio::portd::RD1, 0; + gpio::portg::RG9, 1; + gpio::portc::RC2, 12; + gpio::porte::RE8, 13; + gpio::portb::RB14, 2; + gpio::portd::RD0, 3; + gpio::portd::RD8, 4; + gpio::portb::RB6, 5; + gpio::portd::RD5, 6; + gpio::portf::RF3, 8; + gpio::portf::RF13, 9; + } + }{ // virtual output mapping table + gpio::portd::RD2, rpd2r { // PPS group #1 + U3tx, 1; + Oc3, 11; + C2out, 13; + U4rts, 2; + Sdo2, 6; + } + gpio::portg::RG8, rpg8r { // PPS group #1 + U3tx, 1; + Oc3, 11; + C2out, 13; + U4rts, 2; + Sdo2, 6; + } + gpio::portc::RC1, rpc1r { // PPS group #1 + U3tx, 1; + Oc3, 11; + C2out, 13; + U4rts, 2; + Sdo2, 6; + } + gpio::portd::RD14, rpd14r { // PPS group #1 + U3tx, 1; + Oc3, 11; + C2out, 13; + U4rts, 2; + Sdo2, 6; + } + gpio::portg::RG1, rpg1r { // PPS group #1 + U3tx, 1; + Oc3, 11; + C2out, 13; + U4rts, 2; + Sdo2, 6; + } + gpio::porta::RA14, rpa14r { // PPS group #1 + U3tx, 1; + Oc3, 11; + C2out, 13; + U4rts, 2; + Sdo2, 6; + } + gpio::portf::RF2, rpf2r { // PPS group #1 + U3tx, 1; + Oc3, 11; + C2out, 13; + U4rts, 2; + Sdo2, 6; + } + gpio::portf::RF4, rpf4r { // PPS group #1 + U3tx, 1; + Oc3, 11; + C2out, 13; + U4rts, 2; + Sdo2, 6; + } + gpio::portd::RD10, rpd10r { // PPS group #1 + U3tx, 1; + Oc3, 11; + C2out, 13; + U4rts, 2; + Sdo2, 6; + } + gpio::portf::RF1, rpf1r { // PPS group #1 + U3tx, 1; + Oc3, 11; + C2out, 13; + U4rts, 2; + Sdo2, 6; + } + gpio::portb::RB9, rpb9r { // PPS group #1 + U3tx, 1; + Oc3, 11; + C2out, 13; + U4rts, 2; + Sdo2, 6; + } + gpio::portb::RB10, rpb10r { // PPS group #1 + U3tx, 1; + Oc3, 11; + C2out, 13; + U4rts, 2; + Sdo2, 6; + } + gpio::portc::RC14, rpc14r { // PPS group #1 + U3tx, 1; + Oc3, 11; + C2out, 13; + U4rts, 2; + Sdo2, 6; + } + gpio::portb::RB5, rpb5r { // PPS group #1 + U3tx, 1; + Oc3, 11; + C2out, 13; + U4rts, 2; + Sdo2, 6; + } + gpio::portd::RD3, rpd3r { // PPS group #2 + U2tx, 1; + Oc4, 11; + U1tx, 3; + U5rts, 4; + Sdo2, 6; + Sdo1, 8; + } + gpio::portg::RG7, rpg7r { // PPS group #2 + U2tx, 1; + Oc4, 11; + U1tx, 3; + U5rts, 4; + Sdo2, 6; + Sdo1, 8; + } + gpio::portc::RC4, rpc4r { // PPS group #2 + U2tx, 1; + Oc4, 11; + U1tx, 3; + U5rts, 4; + Sdo2, 6; + Sdo1, 8; + } + gpio::portd::RD15, rpd15r { // PPS group #2 + U2tx, 1; + Oc4, 11; + U1tx, 3; + U5rts, 4; + Sdo2, 6; + Sdo1, 8; + } + gpio::portg::RG0, rpg0r { // PPS group #2 + U2tx, 1; + Oc4, 11; + U1tx, 3; + U5rts, 4; + Sdo2, 6; + Sdo1, 8; + } + gpio::porta::RA15, rpa15r { // PPS group #2 + U2tx, 1; + Oc4, 11; + U1tx, 3; + U5rts, 4; + Sdo2, 6; + Sdo1, 8; + } + gpio::portf::RF5, rpf5r { // PPS group #2 + U2tx, 1; + Oc4, 11; + U1tx, 3; + U5rts, 4; + Sdo2, 6; + Sdo1, 8; + } + gpio::portd::RD11, rpd11r { // PPS group #2 + U2tx, 1; + Oc4, 11; + U1tx, 3; + U5rts, 4; + Sdo2, 6; + Sdo1, 8; + } + gpio::portf::RF0, rpf0r { // PPS group #2 + U2tx, 1; + Oc4, 11; + U1tx, 3; + U5rts, 4; + Sdo2, 6; + Sdo1, 8; + } + gpio::portb::RB1, rpb1r { // PPS group #2 + U2tx, 1; + Oc4, 11; + U1tx, 3; + U5rts, 4; + Sdo2, 6; + Sdo1, 8; + } + gpio::porte::RE5, rpe5r { // PPS group #2 + U2tx, 1; + Oc4, 11; + U1tx, 3; + U5rts, 4; + Sdo2, 6; + Sdo1, 8; + } + gpio::portc::RC13, rpc13r { // PPS group #2 + U2tx, 1; + Oc4, 11; + U1tx, 3; + U5rts, 4; + Sdo2, 6; + Sdo1, 8; + } + gpio::portb::RB3, rpb3r { // PPS group #2 + U2tx, 1; + Oc4, 11; + U1tx, 3; + U5rts, 4; + Sdo2, 6; + Sdo1, 8; + } + gpio::portd::RD9, rpd9r { // PPS group #3 + U3rts, 1; + Oc5, 11; + C1out, 13; + U4tx, 2; + Refclko, 3; + U5tx, 4; + Ss1, 7; + Sdo1, 8; + } + gpio::portg::RG6, rpg6r { // PPS group #3 + U3rts, 1; + Oc5, 11; + C1out, 13; + U4tx, 2; + Refclko, 3; + U5tx, 4; + Ss1, 7; + Sdo1, 8; + } + gpio::portd::RD12, rpd12r { // PPS group #3 + U3rts, 1; + Oc5, 11; + C1out, 13; + U4tx, 2; + Refclko, 3; + U5tx, 4; + Ss1, 7; + Sdo1, 8; + } + gpio::portf::RF8, rpf8r { // PPS group #3 + U3rts, 1; + Oc5, 11; + C1out, 13; + U4tx, 2; + Refclko, 3; + U5tx, 4; + Ss1, 7; + Sdo1, 8; + } + gpio::portc::RC3, rpc3r { // PPS group #3 + U3rts, 1; + Oc5, 11; + C1out, 13; + U4tx, 2; + Refclko, 3; + U5tx, 4; + Ss1, 7; + Sdo1, 8; + } + gpio::porte::RE9, rpe9r { // PPS group #3 + U3rts, 1; + Oc5, 11; + C1out, 13; + U4tx, 2; + Refclko, 3; + U5tx, 4; + Ss1, 7; + Sdo1, 8; + } + gpio::portb::RB2, rpb2r { // PPS group #3 + U3rts, 1; + Oc5, 11; + C1out, 13; + U4tx, 2; + Refclko, 3; + U5tx, 4; + Ss1, 7; + Sdo1, 8; + } + gpio::portb::RB8, rpb8r { // PPS group #3 + U3rts, 1; + Oc5, 11; + C1out, 13; + U4tx, 2; + Refclko, 3; + U5tx, 4; + Ss1, 7; + Sdo1, 8; + } + gpio::portb::RB15, rpb15r { // PPS group #3 + U3rts, 1; + Oc5, 11; + C1out, 13; + U4tx, 2; + Refclko, 3; + U5tx, 4; + Ss1, 7; + Sdo1, 8; + } + gpio::portd::RD4, rpd4r { // PPS group #3 + U3rts, 1; + Oc5, 11; + C1out, 13; + U4tx, 2; + Refclko, 3; + U5tx, 4; + Ss1, 7; + Sdo1, 8; + } + gpio::portb::RB0, rpb0r { // PPS group #3 + U3rts, 1; + Oc5, 11; + C1out, 13; + U4tx, 2; + Refclko, 3; + U5tx, 4; + Ss1, 7; + Sdo1, 8; + } + gpio::porte::RE3, rpe3r { // PPS group #3 + U3rts, 1; + Oc5, 11; + C1out, 13; + U4tx, 2; + Refclko, 3; + U5tx, 4; + Ss1, 7; + Sdo1, 8; + } + gpio::portb::RB7, rpb7r { // PPS group #3 + U3rts, 1; + Oc5, 11; + C1out, 13; + U4tx, 2; + Refclko, 3; + U5tx, 4; + Ss1, 7; + Sdo1, 8; + } + gpio::portf::RF12, rpf12r { // PPS group #3 + U3rts, 1; + Oc5, 11; + C1out, 13; + U4tx, 2; + Refclko, 3; + U5tx, 4; + Ss1, 7; + Sdo1, 8; + } + gpio::portd::RD1, rpd1r { // PPS group #4 + U2rts, 1; + Oc2, 11; + Oc1, 12; + U1rts, 3; + U5tx, 4; + Ss2, 6; + Sdo1, 8; + } + gpio::portg::RG9, rpg9r { // PPS group #4 + U2rts, 1; + Oc2, 11; + Oc1, 12; + U1rts, 3; + U5tx, 4; + Ss2, 6; + Sdo1, 8; + } + gpio::portc::RC2, rpc2r { // PPS group #4 + U2rts, 1; + Oc2, 11; + Oc1, 12; + U1rts, 3; + U5tx, 4; + Ss2, 6; + Sdo1, 8; + } + gpio::porte::RE8, rpe8r { // PPS group #4 + U2rts, 1; + Oc2, 11; + Oc1, 12; + U1rts, 3; + U5tx, 4; + Ss2, 6; + Sdo1, 8; + } + gpio::portb::RB14, rpb14r { // PPS group #4 + U2rts, 1; + Oc2, 11; + Oc1, 12; + U1rts, 3; + U5tx, 4; + Ss2, 6; + Sdo1, 8; + } + gpio::portd::RD0, rpd0r { // PPS group #4 + U2rts, 1; + Oc2, 11; + Oc1, 12; + U1rts, 3; + U5tx, 4; + Ss2, 6; + Sdo1, 8; + } + gpio::portd::RD8, rpd8r { // PPS group #4 + U2rts, 1; + Oc2, 11; + Oc1, 12; + U1rts, 3; + U5tx, 4; + Ss2, 6; + Sdo1, 8; + } + gpio::portb::RB6, rpb6r { // PPS group #4 + U2rts, 1; + Oc2, 11; + Oc1, 12; + U1rts, 3; + U5tx, 4; + Ss2, 6; + Sdo1, 8; + } + gpio::portd::RD5, rpd5r { // PPS group #4 + U2rts, 1; + Oc2, 11; + Oc1, 12; + U1rts, 3; + U5tx, 4; + Ss2, 6; + Sdo1, 8; + } + gpio::portf::RF3, rpf3r { // PPS group #4 + U2rts, 1; + Oc2, 11; + Oc1, 12; + U1rts, 3; + U5tx, 4; + Ss2, 6; + Sdo1, 8; + } + gpio::portf::RF13, rpf13r { // PPS group #4 + U2rts, 1; + Oc2, 11; + Oc1, 12; + U1rts, 3; + U5tx, 4; + Ss2, 6; + Sdo1, 8; + } + } +} + +#[cfg(feature = "pic32mx47x")] +pps_tables! { + { // virtual input declarations + Int3, int3; // PPS group #1 + T2ck, t2ck; // PPS group #1 + Ic3, ic3; // PPS group #1 + U1rx, u1rx; // PPS group #1 + U2rx, u2rx; // PPS group #1 + U5cts, u5cts; // PPS group #1 + Refclki, refclki; // PPS group #1 + Int4, int4; // PPS group #2 + T5ck, t5ck; // PPS group #2 + Ic4, ic4; // PPS group #2 + U3rx, u3rx; // PPS group #2 + U4cts, u4cts; // PPS group #2 + Sdi1, sdi1; // PPS group #2 + Sdi2, sdi2; // PPS group #2 + Int2, int2; // PPS group #3 + T4ck, t4ck; // PPS group #3 + Ic2, ic2; // PPS group #3 + Ic5, ic5; // PPS group #3 + U1cts, u1cts; // PPS group #3 + U2cts, u2cts; // PPS group #3 + Ss1, ss1; // PPS group #3 + Int1, int1; // PPS group #4 + T3ck, t3ck; // PPS group #4 + Ic1, ic1; // PPS group #4 + U3cts, u3cts; // PPS group #4 + U4rx, u4rx; // PPS group #4 + U5rx, u5rx; // PPS group #4 + Ss2, ss2; // PPS group #4 + Ocfa, ocfa; // PPS group #4 + }{ // virtual output declarations + C1out, c1out; + C2out, c2out; + Oc1, oc1; + Oc2, oc2; + Oc3, oc3; + Oc4, oc4; + Oc5, oc5; + Refclko, refclko; + Sdo1, sdo1; + Sdo2, sdo2; + Ss1, ss1; + Ss2, ss2; + U1rts, u1rts; + U1tx, u1tx; + U2rts, u2rts; + U2tx, u2tx; + U3rts, u3rts; + U3tx, u3tx; + U4rts, u4rts; + U4tx, u4tx; + U5rts, u5rts; + U5tx, u5tx; + }{ // virtual input mapping table + Int3, int3r { // PPS group #1 + gpio::portd::RD2, 0; + gpio::portg::RG8, 1; + gpio::portc::RC1, 10; + gpio::portd::RD14, 11; + gpio::portg::RG1, 12; + gpio::porta::RA14, 13; + gpio::portf::RF2, 15; + gpio::portf::RF4, 2; + gpio::portd::RD10, 3; + gpio::portf::RF1, 4; + gpio::portb::RB9, 5; + gpio::portb::RB10, 6; + gpio::portc::RC14, 7; + gpio::portb::RB5, 8; + } + T2ck, t2ckr { // PPS group #1 + gpio::portd::RD2, 0; + gpio::portg::RG8, 1; + gpio::portc::RC1, 10; + gpio::portd::RD14, 11; + gpio::portg::RG1, 12; + gpio::porta::RA14, 13; + gpio::portf::RF2, 15; + gpio::portf::RF4, 2; + gpio::portd::RD10, 3; + gpio::portf::RF1, 4; + gpio::portb::RB9, 5; + gpio::portb::RB10, 6; + gpio::portc::RC14, 7; + gpio::portb::RB5, 8; + } + Ic3, ic3r { // PPS group #1 + gpio::portd::RD2, 0; + gpio::portg::RG8, 1; + gpio::portc::RC1, 10; + gpio::portd::RD14, 11; + gpio::portg::RG1, 12; + gpio::porta::RA14, 13; + gpio::portf::RF2, 15; + gpio::portf::RF4, 2; + gpio::portd::RD10, 3; + gpio::portf::RF1, 4; + gpio::portb::RB9, 5; + gpio::portb::RB10, 6; + gpio::portc::RC14, 7; + gpio::portb::RB5, 8; + } + U1rx, u1rxr { // PPS group #1 + gpio::portd::RD2, 0; + gpio::portg::RG8, 1; + gpio::portc::RC1, 10; + gpio::portd::RD14, 11; + gpio::portg::RG1, 12; + gpio::porta::RA14, 13; + gpio::portf::RF2, 15; + gpio::portf::RF4, 2; + gpio::portd::RD10, 3; + gpio::portf::RF1, 4; + gpio::portb::RB9, 5; + gpio::portb::RB10, 6; + gpio::portc::RC14, 7; + gpio::portb::RB5, 8; + } + U2rx, u2rxr { // PPS group #1 + gpio::portd::RD2, 0; + gpio::portg::RG8, 1; + gpio::portc::RC1, 10; + gpio::portd::RD14, 11; + gpio::portg::RG1, 12; + gpio::porta::RA14, 13; + gpio::portf::RF2, 15; + gpio::portf::RF4, 2; + gpio::portd::RD10, 3; + gpio::portf::RF1, 4; + gpio::portb::RB9, 5; + gpio::portb::RB10, 6; + gpio::portc::RC14, 7; + gpio::portb::RB5, 8; + } + U5cts, u5ctsr { // PPS group #1 + gpio::portd::RD2, 0; + gpio::portg::RG8, 1; + gpio::portc::RC1, 10; + gpio::portd::RD14, 11; + gpio::portg::RG1, 12; + gpio::porta::RA14, 13; + gpio::portf::RF2, 15; + gpio::portf::RF4, 2; + gpio::portd::RD10, 3; + gpio::portf::RF1, 4; + gpio::portb::RB9, 5; + gpio::portb::RB10, 6; + gpio::portc::RC14, 7; + gpio::portb::RB5, 8; + } + Refclki, refclkir { // PPS group #1 + gpio::portd::RD2, 0; + gpio::portg::RG8, 1; + gpio::portc::RC1, 10; + gpio::portd::RD14, 11; + gpio::portg::RG1, 12; + gpio::porta::RA14, 13; + gpio::portf::RF2, 15; + gpio::portf::RF4, 2; + gpio::portd::RD10, 3; + gpio::portf::RF1, 4; + gpio::portb::RB9, 5; + gpio::portb::RB10, 6; + gpio::portc::RC14, 7; + gpio::portb::RB5, 8; + } + Int4, int4r { // PPS group #2 + gpio::portd::RD3, 0; + gpio::portg::RG7, 1; + gpio::portc::RC4, 10; + gpio::portd::RD15, 11; + gpio::portg::RG0, 12; + gpio::porta::RA15, 13; + gpio::portf::RF5, 2; + gpio::portd::RD11, 3; + gpio::portf::RF0, 4; + gpio::portb::RB1, 5; + gpio::porte::RE5, 6; + gpio::portc::RC13, 7; + gpio::portb::RB3, 8; + } + T5ck, t5ckr { // PPS group #2 + gpio::portd::RD3, 0; + gpio::portg::RG7, 1; + gpio::portc::RC4, 10; + gpio::portd::RD15, 11; + gpio::portg::RG0, 12; + gpio::porta::RA15, 13; + gpio::portf::RF5, 2; + gpio::portd::RD11, 3; + gpio::portf::RF0, 4; + gpio::portb::RB1, 5; + gpio::porte::RE5, 6; + gpio::portc::RC13, 7; + gpio::portb::RB3, 8; + } + Ic4, ic4r { // PPS group #2 + gpio::portd::RD3, 0; + gpio::portg::RG7, 1; + gpio::portc::RC4, 10; + gpio::portd::RD15, 11; + gpio::portg::RG0, 12; + gpio::porta::RA15, 13; + gpio::portf::RF5, 2; + gpio::portd::RD11, 3; + gpio::portf::RF0, 4; + gpio::portb::RB1, 5; + gpio::porte::RE5, 6; + gpio::portc::RC13, 7; + gpio::portb::RB3, 8; + } + U3rx, u3rxr { // PPS group #2 + gpio::portd::RD3, 0; + gpio::portg::RG7, 1; + gpio::portc::RC4, 10; + gpio::portd::RD15, 11; + gpio::portg::RG0, 12; + gpio::porta::RA15, 13; + gpio::portf::RF5, 2; + gpio::portd::RD11, 3; + gpio::portf::RF0, 4; + gpio::portb::RB1, 5; + gpio::porte::RE5, 6; + gpio::portc::RC13, 7; + gpio::portb::RB3, 8; + } + U4cts, u4ctsr { // PPS group #2 + gpio::portd::RD3, 0; + gpio::portg::RG7, 1; + gpio::portc::RC4, 10; + gpio::portd::RD15, 11; + gpio::portg::RG0, 12; + gpio::porta::RA15, 13; + gpio::portf::RF5, 2; + gpio::portd::RD11, 3; + gpio::portf::RF0, 4; + gpio::portb::RB1, 5; + gpio::porte::RE5, 6; + gpio::portc::RC13, 7; + gpio::portb::RB3, 8; + } + Sdi1, sdi1r { // PPS group #2 + gpio::portd::RD3, 0; + gpio::portg::RG7, 1; + gpio::portc::RC4, 10; + gpio::portd::RD15, 11; + gpio::portg::RG0, 12; + gpio::porta::RA15, 13; + gpio::portf::RF5, 2; + gpio::portd::RD11, 3; + gpio::portf::RF0, 4; + gpio::portb::RB1, 5; + gpio::porte::RE5, 6; + gpio::portc::RC13, 7; + gpio::portb::RB3, 8; + } + Sdi2, sdi2r { // PPS group #2 + gpio::portd::RD3, 0; + gpio::portg::RG7, 1; + gpio::portc::RC4, 10; + gpio::portd::RD15, 11; + gpio::portg::RG0, 12; + gpio::porta::RA15, 13; + gpio::portf::RF5, 2; + gpio::portd::RD11, 3; + gpio::portf::RF0, 4; + gpio::portb::RB1, 5; + gpio::porte::RE5, 6; + gpio::portc::RC13, 7; + gpio::portb::RB3, 8; + } + Int2, int2r { // PPS group #3 + gpio::portd::RD9, 0; + gpio::portg::RG6, 1; + gpio::portd::RD12, 10; + gpio::portf::RF8, 11; + gpio::portc::RC3, 12; + gpio::porte::RE9, 13; + gpio::portb::RB2, 15; + gpio::portb::RB8, 2; + gpio::portb::RB15, 3; + gpio::portd::RD4, 4; + gpio::portb::RB0, 5; + gpio::porte::RE3, 6; + gpio::portb::RB7, 7; + gpio::portf::RF12, 9; + } + T4ck, t4ckr { // PPS group #3 + gpio::portd::RD9, 0; + gpio::portg::RG6, 1; + gpio::portd::RD12, 10; + gpio::portf::RF8, 11; + gpio::portc::RC3, 12; + gpio::porte::RE9, 13; + gpio::portb::RB2, 15; + gpio::portb::RB8, 2; + gpio::portb::RB15, 3; + gpio::portd::RD4, 4; + gpio::portb::RB0, 5; + gpio::porte::RE3, 6; + gpio::portb::RB7, 7; + gpio::portf::RF12, 9; + } + Ic2, ic2r { // PPS group #3 + gpio::portd::RD9, 0; + gpio::portg::RG6, 1; + gpio::portd::RD12, 10; + gpio::portf::RF8, 11; + gpio::portc::RC3, 12; + gpio::porte::RE9, 13; + gpio::portb::RB2, 15; + gpio::portb::RB8, 2; + gpio::portb::RB15, 3; + gpio::portd::RD4, 4; + gpio::portb::RB0, 5; + gpio::porte::RE3, 6; + gpio::portb::RB7, 7; + gpio::portf::RF12, 9; + } + Ic5, ic5r { // PPS group #3 + gpio::portd::RD9, 0; + gpio::portg::RG6, 1; + gpio::portd::RD12, 10; + gpio::portf::RF8, 11; + gpio::portc::RC3, 12; + gpio::porte::RE9, 13; + gpio::portb::RB2, 15; + gpio::portb::RB8, 2; + gpio::portb::RB15, 3; + gpio::portd::RD4, 4; + gpio::portb::RB0, 5; + gpio::porte::RE3, 6; + gpio::portb::RB7, 7; + gpio::portf::RF12, 9; + } + U1cts, u1ctsr { // PPS group #3 + gpio::portd::RD9, 0; + gpio::portg::RG6, 1; + gpio::portd::RD12, 10; + gpio::portf::RF8, 11; + gpio::portc::RC3, 12; + gpio::porte::RE9, 13; + gpio::portb::RB2, 15; + gpio::portb::RB8, 2; + gpio::portb::RB15, 3; + gpio::portd::RD4, 4; + gpio::portb::RB0, 5; + gpio::porte::RE3, 6; + gpio::portb::RB7, 7; + gpio::portf::RF12, 9; + } + U2cts, u2ctsr { // PPS group #3 + gpio::portd::RD9, 0; + gpio::portg::RG6, 1; + gpio::portd::RD12, 10; + gpio::portf::RF8, 11; + gpio::portc::RC3, 12; + gpio::porte::RE9, 13; + gpio::portb::RB2, 15; + gpio::portb::RB8, 2; + gpio::portb::RB15, 3; + gpio::portd::RD4, 4; + gpio::portb::RB0, 5; + gpio::porte::RE3, 6; + gpio::portb::RB7, 7; + gpio::portf::RF12, 9; + } + Ss1, ss1r { // PPS group #3 + gpio::portd::RD9, 0; + gpio::portg::RG6, 1; + gpio::portd::RD12, 10; + gpio::portf::RF8, 11; + gpio::portc::RC3, 12; + gpio::porte::RE9, 13; + gpio::portb::RB2, 15; + gpio::portb::RB8, 2; + gpio::portb::RB15, 3; + gpio::portd::RD4, 4; + gpio::portb::RB0, 5; + gpio::porte::RE3, 6; + gpio::portb::RB7, 7; + gpio::portf::RF12, 9; + } + Int1, int1r { // PPS group #4 + gpio::portd::RD1, 0; + gpio::portg::RG9, 1; + gpio::portc::RC2, 12; + gpio::porte::RE8, 13; + gpio::portb::RB14, 2; + gpio::portd::RD0, 3; + gpio::portd::RD8, 4; + gpio::portb::RB6, 5; + gpio::portd::RD5, 6; + gpio::portf::RF3, 8; + gpio::portf::RF13, 9; + } + T3ck, t3ckr { // PPS group #4 + gpio::portd::RD1, 0; + gpio::portg::RG9, 1; + gpio::portc::RC2, 12; + gpio::porte::RE8, 13; + gpio::portb::RB14, 2; + gpio::portd::RD0, 3; + gpio::portd::RD8, 4; + gpio::portb::RB6, 5; + gpio::portd::RD5, 6; + gpio::portf::RF3, 8; + gpio::portf::RF13, 9; + } + Ic1, ic1r { // PPS group #4 + gpio::portd::RD1, 0; + gpio::portg::RG9, 1; + gpio::portc::RC2, 12; + gpio::porte::RE8, 13; + gpio::portb::RB14, 2; + gpio::portd::RD0, 3; + gpio::portd::RD8, 4; + gpio::portb::RB6, 5; + gpio::portd::RD5, 6; + gpio::portf::RF3, 8; + gpio::portf::RF13, 9; + } + U3cts, u3ctsr { // PPS group #4 + gpio::portd::RD1, 0; + gpio::portg::RG9, 1; + gpio::portc::RC2, 12; + gpio::porte::RE8, 13; + gpio::portb::RB14, 2; + gpio::portd::RD0, 3; + gpio::portd::RD8, 4; + gpio::portb::RB6, 5; + gpio::portd::RD5, 6; + gpio::portf::RF3, 8; + gpio::portf::RF13, 9; + } + U4rx, u4rxr { // PPS group #4 + gpio::portd::RD1, 0; + gpio::portg::RG9, 1; + gpio::portc::RC2, 12; + gpio::porte::RE8, 13; + gpio::portb::RB14, 2; + gpio::portd::RD0, 3; + gpio::portd::RD8, 4; + gpio::portb::RB6, 5; + gpio::portd::RD5, 6; + gpio::portf::RF3, 8; + gpio::portf::RF13, 9; + } + U5rx, u5rxr { // PPS group #4 + gpio::portd::RD1, 0; + gpio::portg::RG9, 1; + gpio::portc::RC2, 12; + gpio::porte::RE8, 13; + gpio::portb::RB14, 2; + gpio::portd::RD0, 3; + gpio::portd::RD8, 4; + gpio::portb::RB6, 5; + gpio::portd::RD5, 6; + gpio::portf::RF3, 8; + gpio::portf::RF13, 9; + } + Ss2, ss2r { // PPS group #4 + gpio::portd::RD1, 0; + gpio::portg::RG9, 1; + gpio::portc::RC2, 12; + gpio::porte::RE8, 13; + gpio::portb::RB14, 2; + gpio::portd::RD0, 3; + gpio::portd::RD8, 4; + gpio::portb::RB6, 5; + gpio::portd::RD5, 6; + gpio::portf::RF3, 8; + gpio::portf::RF13, 9; + } + Ocfa, ocfar { // PPS group #4 + gpio::portd::RD1, 0; + gpio::portg::RG9, 1; + gpio::portc::RC2, 12; + gpio::porte::RE8, 13; + gpio::portb::RB14, 2; + gpio::portd::RD0, 3; + gpio::portd::RD8, 4; + gpio::portb::RB6, 5; + gpio::portd::RD5, 6; + gpio::portf::RF3, 8; + gpio::portf::RF13, 9; + } + }{ // virtual output mapping table + gpio::portd::RD2, rpd2r { // PPS group #1 + U3tx, 1; + Oc3, 11; + C2out, 13; + U4rts, 2; + Sdo2, 6; + } + gpio::portg::RG8, rpg8r { // PPS group #1 + U3tx, 1; + Oc3, 11; + C2out, 13; + U4rts, 2; + Sdo2, 6; + } + gpio::portc::RC1, rpc1r { // PPS group #1 + U3tx, 1; + Oc3, 11; + C2out, 13; + U4rts, 2; + Sdo2, 6; + } + gpio::portd::RD14, rpd14r { // PPS group #1 + U3tx, 1; + Oc3, 11; + C2out, 13; + U4rts, 2; + Sdo2, 6; + } + gpio::portg::RG1, rpg1r { // PPS group #1 + U3tx, 1; + Oc3, 11; + C2out, 13; + U4rts, 2; + Sdo2, 6; + } + gpio::porta::RA14, rpa14r { // PPS group #1 + U3tx, 1; + Oc3, 11; + C2out, 13; + U4rts, 2; + Sdo2, 6; + } + gpio::portf::RF2, rpf2r { // PPS group #1 + U3tx, 1; + Oc3, 11; + C2out, 13; + U4rts, 2; + Sdo2, 6; + } + gpio::portf::RF4, rpf4r { // PPS group #1 + U3tx, 1; + Oc3, 11; + C2out, 13; + U4rts, 2; + Sdo2, 6; + } + gpio::portd::RD10, rpd10r { // PPS group #1 + U3tx, 1; + Oc3, 11; + C2out, 13; + U4rts, 2; + Sdo2, 6; + } + gpio::portf::RF1, rpf1r { // PPS group #1 + U3tx, 1; + Oc3, 11; + C2out, 13; + U4rts, 2; + Sdo2, 6; + } + gpio::portb::RB9, rpb9r { // PPS group #1 + U3tx, 1; + Oc3, 11; + C2out, 13; + U4rts, 2; + Sdo2, 6; + } + gpio::portb::RB10, rpb10r { // PPS group #1 + U3tx, 1; + Oc3, 11; + C2out, 13; + U4rts, 2; + Sdo2, 6; + } + gpio::portc::RC14, rpc14r { // PPS group #1 + U3tx, 1; + Oc3, 11; + C2out, 13; + U4rts, 2; + Sdo2, 6; + } + gpio::portb::RB5, rpb5r { // PPS group #1 + U3tx, 1; + Oc3, 11; + C2out, 13; + U4rts, 2; + Sdo2, 6; + } + gpio::portd::RD3, rpd3r { // PPS group #2 + U2tx, 1; + Oc4, 11; + U1tx, 3; + U5rts, 4; + Sdo2, 6; + Sdo1, 8; + } + gpio::portg::RG7, rpg7r { // PPS group #2 + U2tx, 1; + Oc4, 11; + U1tx, 3; + U5rts, 4; + Sdo2, 6; + Sdo1, 8; + } + gpio::portc::RC4, rpc4r { // PPS group #2 + U2tx, 1; + Oc4, 11; + U1tx, 3; + U5rts, 4; + Sdo2, 6; + Sdo1, 8; + } + gpio::portd::RD15, rpd15r { // PPS group #2 + U2tx, 1; + Oc4, 11; + U1tx, 3; + U5rts, 4; + Sdo2, 6; + Sdo1, 8; + } + gpio::portg::RG0, rpg0r { // PPS group #2 + U2tx, 1; + Oc4, 11; + U1tx, 3; + U5rts, 4; + Sdo2, 6; + Sdo1, 8; + } + gpio::porta::RA15, rpa15r { // PPS group #2 + U2tx, 1; + Oc4, 11; + U1tx, 3; + U5rts, 4; + Sdo2, 6; + Sdo1, 8; + } + gpio::portf::RF5, rpf5r { // PPS group #2 + U2tx, 1; + Oc4, 11; + U1tx, 3; + U5rts, 4; + Sdo2, 6; + Sdo1, 8; + } + gpio::portd::RD11, rpd11r { // PPS group #2 + U2tx, 1; + Oc4, 11; + U1tx, 3; + U5rts, 4; + Sdo2, 6; + Sdo1, 8; + } + gpio::portf::RF0, rpf0r { // PPS group #2 + U2tx, 1; + Oc4, 11; + U1tx, 3; + U5rts, 4; + Sdo2, 6; + Sdo1, 8; + } + gpio::portb::RB1, rpb1r { // PPS group #2 + U2tx, 1; + Oc4, 11; + U1tx, 3; + U5rts, 4; + Sdo2, 6; + Sdo1, 8; + } + gpio::porte::RE5, rpe5r { // PPS group #2 + U2tx, 1; + Oc4, 11; + U1tx, 3; + U5rts, 4; + Sdo2, 6; + Sdo1, 8; + } + gpio::portc::RC13, rpc13r { // PPS group #2 + U2tx, 1; + Oc4, 11; + U1tx, 3; + U5rts, 4; + Sdo2, 6; + Sdo1, 8; + } + gpio::portb::RB3, rpb3r { // PPS group #2 + U2tx, 1; + Oc4, 11; + U1tx, 3; + U5rts, 4; + Sdo2, 6; + Sdo1, 8; + } + gpio::portd::RD9, rpd9r { // PPS group #3 + U3rts, 1; + Oc5, 11; + C1out, 13; + U4tx, 2; + Refclko, 3; + U5tx, 4; + Ss1, 7; + Sdo1, 8; + } + gpio::portg::RG6, rpg6r { // PPS group #3 + U3rts, 1; + Oc5, 11; + C1out, 13; + U4tx, 2; + Refclko, 3; + U5tx, 4; + Ss1, 7; + Sdo1, 8; + } + gpio::portd::RD12, rpd12r { // PPS group #3 + U3rts, 1; + Oc5, 11; + C1out, 13; + U4tx, 2; + Refclko, 3; + U5tx, 4; + Ss1, 7; + Sdo1, 8; + } + gpio::portf::RF8, rpf8r { // PPS group #3 + U3rts, 1; + Oc5, 11; + C1out, 13; + U4tx, 2; + Refclko, 3; + U5tx, 4; + Ss1, 7; + Sdo1, 8; + } + gpio::portc::RC3, rpc3r { // PPS group #3 + U3rts, 1; + Oc5, 11; + C1out, 13; + U4tx, 2; + Refclko, 3; + U5tx, 4; + Ss1, 7; + Sdo1, 8; + } + gpio::porte::RE9, rpe9r { // PPS group #3 + U3rts, 1; + Oc5, 11; + C1out, 13; + U4tx, 2; + Refclko, 3; + U5tx, 4; + Ss1, 7; + Sdo1, 8; + } + gpio::portb::RB2, rpb2r { // PPS group #3 + U3rts, 1; + Oc5, 11; + C1out, 13; + U4tx, 2; + Refclko, 3; + U5tx, 4; + Ss1, 7; + Sdo1, 8; + } + gpio::portb::RB8, rpb8r { // PPS group #3 + U3rts, 1; + Oc5, 11; + C1out, 13; + U4tx, 2; + Refclko, 3; + U5tx, 4; + Ss1, 7; + Sdo1, 8; + } + gpio::portb::RB15, rpb15r { // PPS group #3 + U3rts, 1; + Oc5, 11; + C1out, 13; + U4tx, 2; + Refclko, 3; + U5tx, 4; + Ss1, 7; + Sdo1, 8; + } + gpio::portd::RD4, rpd4r { // PPS group #3 + U3rts, 1; + Oc5, 11; + C1out, 13; + U4tx, 2; + Refclko, 3; + U5tx, 4; + Ss1, 7; + Sdo1, 8; + } + gpio::portb::RB0, rpb0r { // PPS group #3 + U3rts, 1; + Oc5, 11; + C1out, 13; + U4tx, 2; + Refclko, 3; + U5tx, 4; + Ss1, 7; + Sdo1, 8; + } + gpio::porte::RE3, rpe3r { // PPS group #3 + U3rts, 1; + Oc5, 11; + C1out, 13; + U4tx, 2; + Refclko, 3; + U5tx, 4; + Ss1, 7; + Sdo1, 8; + } + gpio::portb::RB7, rpb7r { // PPS group #3 + U3rts, 1; + Oc5, 11; + C1out, 13; + U4tx, 2; + Refclko, 3; + U5tx, 4; + Ss1, 7; + Sdo1, 8; + } + gpio::portf::RF12, rpf12r { // PPS group #3 + U3rts, 1; + Oc5, 11; + C1out, 13; + U4tx, 2; + Refclko, 3; + U5tx, 4; + Ss1, 7; + Sdo1, 8; + } + gpio::portd::RD1, rpd1r { // PPS group #4 + U2rts, 1; + Oc2, 11; + Oc1, 12; + U1rts, 3; + U5tx, 4; + Ss2, 6; + Sdo1, 8; + } + gpio::portg::RG9, rpg9r { // PPS group #4 + U2rts, 1; + Oc2, 11; + Oc1, 12; + U1rts, 3; + U5tx, 4; + Ss2, 6; + Sdo1, 8; + } + gpio::portc::RC2, rpc2r { // PPS group #4 + U2rts, 1; + Oc2, 11; + Oc1, 12; + U1rts, 3; + U5tx, 4; + Ss2, 6; + Sdo1, 8; + } + gpio::porte::RE8, rpe8r { // PPS group #4 + U2rts, 1; + Oc2, 11; + Oc1, 12; + U1rts, 3; + U5tx, 4; + Ss2, 6; + Sdo1, 8; + } + gpio::portb::RB14, rpb14r { // PPS group #4 + U2rts, 1; + Oc2, 11; + Oc1, 12; + U1rts, 3; + U5tx, 4; + Ss2, 6; + Sdo1, 8; + } + gpio::portd::RD0, rpd0r { // PPS group #4 + U2rts, 1; + Oc2, 11; + Oc1, 12; + U1rts, 3; + U5tx, 4; + Ss2, 6; + Sdo1, 8; + } + gpio::portd::RD8, rpd8r { // PPS group #4 + U2rts, 1; + Oc2, 11; + Oc1, 12; + U1rts, 3; + U5tx, 4; + Ss2, 6; + Sdo1, 8; + } + gpio::portb::RB6, rpb6r { // PPS group #4 + U2rts, 1; + Oc2, 11; + Oc1, 12; + U1rts, 3; + U5tx, 4; + Ss2, 6; + Sdo1, 8; + } + gpio::portd::RD5, rpd5r { // PPS group #4 + U2rts, 1; + Oc2, 11; + Oc1, 12; + U1rts, 3; + U5tx, 4; + Ss2, 6; + Sdo1, 8; + } + gpio::portf::RF13, rpf13r { // PPS group #4 + U2rts, 1; + Oc2, 11; + Oc1, 12; + U1rts, 3; + U5tx, 4; + Ss2, 6; + Sdo1, 8; + } + } +} +