From 285f4dbce6126c96feb8bc18a29998e962f39a58 Mon Sep 17 00:00:00 2001 From: Omercan Kilic <134288264+kilicomercan@users.noreply.github.com> Date: Wed, 9 Oct 2024 21:01:37 +0300 Subject: [PATCH 01/37] fix(Boards): Add GPIO2_IRQ_Handler for MAX78000 FTHR_RevA (#1221) --- Libraries/Boards/MAX78000/FTHR_RevA/Source/board.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Libraries/Boards/MAX78000/FTHR_RevA/Source/board.c b/Libraries/Boards/MAX78000/FTHR_RevA/Source/board.c index 034b5bf1c7b..39ebd0e3b7d 100644 --- a/Libraries/Boards/MAX78000/FTHR_RevA/Source/board.c +++ b/Libraries/Boards/MAX78000/FTHR_RevA/Source/board.c @@ -80,6 +80,16 @@ __weak void GPIO1_IRQHandler(void) { MXC_GPIO_Handler(MXC_GPIO_GET_IDX(MXC_GPIO1)); } +/******************************************************************************/ +/** + * NOTE: This weak definition is included to support to catch interrupts from + * GPIO2 pins in case user does not define this interrupt handler in their + * application. + **/ +__weak void GPIO2_IRQHandler(void) +{ + MXC_GPIO_Handler(MXC_GPIO_GET_IDX(MXC_GPIO2)); +} /******************************************************************************/ int Board_Init(void) From 8ece572dfd5a9bc064e265a5938012bbb828e23d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Tahsin=20T=C3=BCrker=20Mutlug=C3=BCn?= Date: Wed, 9 Oct 2024 22:09:16 +0300 Subject: [PATCH 02/37] chore(CMSIS): Remove unused includes for MAX32672 (#1220) Signed-off-by: Tahsin Mutlugun --- .../CMSIS/Device/Maxim/MAX32672/Include/max32672.h | 11 ----------- 1 file changed, 11 deletions(-) diff --git a/Libraries/CMSIS/Device/Maxim/MAX32672/Include/max32672.h b/Libraries/CMSIS/Device/Maxim/MAX32672/Include/max32672.h index f4c0d69978f..604e6d5723c 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32672/Include/max32672.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32672/Include/max32672.h @@ -29,13 +29,6 @@ #include -// TODO(ADI): Remove below after grace period. Temporarily added these includes to resolve errors -// for grace period before eventually removing support for deprecated features. 10-24-2022 -//>>> -#include "trimsir_regs.h" -#include "aes_regs.h" -//<<< - #ifndef FALSE #define FALSE (0) #endif @@ -314,10 +307,6 @@ typedef enum { #define MXC_BASE_AES ((uint32_t)0x40207400UL) #define MXC_AES ((mxc_aes_regs_t *)MXC_BASE_AES) -// DEPRECATED(10-24-2022): Scheduled for removal. -typedef __attribute__((deprecated( - "Use MXC_AES (mxc_aes_regs_t), not the deprecated MXC_SYS_AES (mxc_sys_aes_regs_t) instance name and struct. 10-24-2022"))) -mxc_aes_regs_t mxc_sys_aes_regs_t; #define MXC_SYS_AES ((mxc_sys_aes_regs_t *)MXC_BASE_AES) /******************************************************************************/ From b99a9213997c3bfbfacb43554ff4722ff851ef2f Mon Sep 17 00:00:00 2001 From: Sihyung Woo <75494566+sihyung-maxim@users.noreply.github.com> Date: Fri, 11 Oct 2024 11:28:36 -0500 Subject: [PATCH 03/37] fix(Examples): Fix warning in MAX32655/UART_DMA example, and increase Bootloader app size for MAX32665 (#1224) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Sadik Ozer Signed-off-by: dependabot[bot] Signed-off-by: Anıl Kara Signed-off-by: Maureen Helm Signed-off-by: Furkan Akkiz Signed-off-by: Tahsin Mutlugun Signed-off-by: Michael Perkins Signed-off-by: Kevin Townsend Co-authored-by: Lorne Smith <65424047+lorne-maxim@users.noreply.github.com> Co-authored-by: Jake Carter Co-authored-by: Sadik Ozer <46590392+ozersa@users.noreply.github.com> Co-authored-by: Jake Carter Co-authored-by: ahmetyazicii <83782637+ahmetyazicii@users.noreply.github.com> Co-authored-by: Brent K <129296493+BrentK-ADI@users.noreply.github.com> Co-authored-by: dependabot[bot] <49699333+dependabot[bot]@users.noreply.github.com> Co-authored-by: Omercan Kilic <134288264+kilicomercan@users.noreply.github.com> Co-authored-by: EricB-ADI <122300463+EricB-ADI@users.noreply.github.com> Co-authored-by: Jake-Carter Co-authored-by: Anıl Kara Co-authored-by: Brandon Hurst <82959533+Brandon-Hurst@users.noreply.github.com> Co-authored-by: EricB-ADI Co-authored-by: Victor Loginov <65688219+vicloginov@users.noreply.github.com> Co-authored-by: lorne-maxim Co-authored-by: Sadik Ozer Co-authored-by: Maureen Helm Co-authored-by: Furkan AKKIZ <94184469+hfakkiz@users.noreply.github.com> Co-authored-by: isztldav Co-authored-by: JC-282-AD Co-authored-by: Oğuzhan Büyüksolak Co-authored-by: JC-282-AD Co-authored-by: Mehmet Ozgun Kanal <123065567+OzgunKanal@users.noreply.github.com> Co-authored-by: Ozgun Co-authored-by: Noxi123 <61051098+Noxi123@users.noreply.github.com> Co-authored-by: Changmin Jeon Co-authored-by: ersahatmacaa <146827243+ersahatmacaa@users.noreply.github.com> Co-authored-by: Kevin Gillespie Co-authored-by: Kevin Gillespie Co-authored-by: Kalvin McCallum <137926624+kmccalluADI@users.noreply.github.com> Co-authored-by: Omer Demir Co-authored-by: sihyung-maxim Co-authored-by: EricB-ADI Co-authored-by: Tahsin Türker Mutlugün Co-authored-by: Michael Perkins <157516771+perkinsmg@users.noreply.github.com> Co-authored-by: Kevin Townsend Co-authored-by: Bobby Co-authored-by: Bobby Counts Co-authored-by: Mert Ekren Co-authored-by: Anıl Kara Co-authored-by: Ozan Durgut <49796358+ozan956@users.noreply.github.com> Co-authored-by: Cristian Cruz <71054319+crsz20@users.noreply.github.com> --- Examples/MAX32655/UART_DMA/main.c | 2 +- Examples/MAX32665/Bluetooth/Bootloader/README.md | 4 ++-- Examples/MAX32665/Bluetooth/Bootloader/boot_lower.S | 2 +- Examples/MAX32665/Bluetooth/Bootloader/bootloader.ld | 2 +- 4 files changed, 5 insertions(+), 5 deletions(-) diff --git a/Examples/MAX32655/UART_DMA/main.c b/Examples/MAX32655/UART_DMA/main.c index c9e8753cdfe..dbf0f168034 100644 --- a/Examples/MAX32655/UART_DMA/main.c +++ b/Examples/MAX32655/UART_DMA/main.c @@ -71,7 +71,7 @@ void readCallback(mxc_uart_req_t *req, int error) READ_FLAG = error; } -void buttonHandler(void) +void buttonHandler(void *pb) { buttonPressed = 1; } diff --git a/Examples/MAX32665/Bluetooth/Bootloader/README.md b/Examples/MAX32665/Bluetooth/Bootloader/README.md index 2470f1b421e..8e57af49fbd 100644 --- a/Examples/MAX32665/Bluetooth/Bootloader/README.md +++ b/Examples/MAX32665/Bluetooth/Bootloader/README.md @@ -9,12 +9,12 @@ the main flash section is erased and replaced with the update image. If no valid is identified, the Bootloader will boot the exiting image in the main flash space. __0x10000000__: Bootloader -__0x10004000__: Main flash space +__0x10008000__: Main flash space __0x10080000__: Update flash space ## Setup -This Bootloader application needs to be loaded to the first two flash pages. The main application +This Bootloader application needs to be loaded at the beginning of Flash. The main application will run on top of this application. The linker file for the main application must coincide with the memory sections defined in this application. The main application is responsible for updating the update flash space. diff --git a/Examples/MAX32665/Bluetooth/Bootloader/boot_lower.S b/Examples/MAX32665/Bluetooth/Bootloader/boot_lower.S index 6a2646f91c4..1dff366bfd1 100644 --- a/Examples/MAX32665/Bluetooth/Bootloader/boot_lower.S +++ b/Examples/MAX32665/Bluetooth/Bootloader/boot_lower.S @@ -31,7 +31,7 @@ /* Boot from the lower flash array */ Boot_Lower: - ldr r0,=0x10004000 /* Address for main flash image */ + ldr r0,=0x10008000 /* Address for main flash image */ ldr r1,=0xE000ED08 /* Address for SCB_VTOR_REG */ /* First 32-bit word in image is initial stack pointer */ diff --git a/Examples/MAX32665/Bluetooth/Bootloader/bootloader.ld b/Examples/MAX32665/Bluetooth/Bootloader/bootloader.ld index d8f82785125..400c2bc3cbe 100644 --- a/Examples/MAX32665/Bluetooth/Bootloader/bootloader.ld +++ b/Examples/MAX32665/Bluetooth/Bootloader/bootloader.ld @@ -19,7 +19,7 @@ ******************************************************************************/ BOOTLOADER_ORIGIN = 0x10000000; -BOOTLOADER_LEN = 0x4000; +BOOTLOADER_LEN = 0x8000; FLASH_SECTION_LEN = 0x80000 - BOOTLOADER_LEN; FLASH0_ORIGIN = BOOTLOADER_ORIGIN + BOOTLOADER_LEN; From 2e34472705532ace08eff8bfb6c5ab400daa5950 Mon Sep 17 00:00:00 2001 From: Sihyung Woo <75494566+sihyung-maxim@users.noreply.github.com> Date: Fri, 11 Oct 2024 11:44:26 -0500 Subject: [PATCH 04/37] fix(CMSIS,PeriphDrivers): Remove SPI TS3, fix GPIO pad controls, and fix build errors for MAX32657 (#1226) --- .../Device/Maxim/MAX32657/Include/gpio_regs.h | 49 ++++++------------- .../Maxim/MAX32657/Include/max32657.svd | 49 ++----------------- .../Device/Maxim/MAX32657/Include/spi_regs.h | 6 +-- .../Maxim/MAX32657/Include/trimsir_regs.h | 4 +- .../PeriphDrivers/Include/MAX32657/gpio.h | 2 - .../PeriphDrivers/Source/GPIO/gpio_me30.c | 23 ++------- .../Source/GPIO/gpio_reva_me30.svd | 34 +------------ Libraries/PeriphDrivers/Source/RTC/rtc_me30.c | 23 ++++----- .../Source/SPI/spi_reva_me30.svd | 12 +---- .../Source/SYS/SVD/trimsir_me30.svd | 3 +- Libraries/PeriphDrivers/Source/WUT/wut_me30.c | 14 +++--- 11 files changed, 47 insertions(+), 172 deletions(-) diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/gpio_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/gpio_regs.h index 3b9ad89a961..6005fb79828 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/gpio_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/gpio_regs.h @@ -96,8 +96,8 @@ typedef struct { __IO uint32_t wken_clr; /**< \b 0x54: GPIO WKEN_CLR Register */ __R uint32_t rsv_0x58; __IO uint32_t dualedge; /**< \b 0x5C: GPIO DUALEDGE Register */ - __IO uint32_t padctrl0; /**< \b 0x60: GPIO PADCTRL0 Register */ - __IO uint32_t padctrl1; /**< \b 0x64: GPIO PADCTRL1 Register */ + __IO uint32_t padctrl; /**< \b 0x60: GPIO PADCTRL Register */ + __R uint32_t rsv_0x64; __IO uint32_t en1; /**< \b 0x68: GPIO EN1 Register */ __IO uint32_t en1_set; /**< \b 0x6C: GPIO EN1_SET Register */ __IO uint32_t en1_clr; /**< \b 0x70: GPIO EN1_CLR Register */ @@ -143,8 +143,7 @@ typedef struct { #define MXC_R_GPIO_WKEN_SET ((uint32_t)0x00000050UL) /**< Offset from GPIO Base Address: 0x0050 */ #define MXC_R_GPIO_WKEN_CLR ((uint32_t)0x00000054UL) /**< Offset from GPIO Base Address: 0x0054 */ #define MXC_R_GPIO_DUALEDGE ((uint32_t)0x0000005CUL) /**< Offset from GPIO Base Address: 0x005C */ -#define MXC_R_GPIO_PADCTRL0 ((uint32_t)0x00000060UL) /**< Offset from GPIO Base Address: 0x0060 */ -#define MXC_R_GPIO_PADCTRL1 ((uint32_t)0x00000064UL) /**< Offset from GPIO Base Address: 0x0064 */ +#define MXC_R_GPIO_PADCTRL ((uint32_t)0x00000060UL) /**< Offset from GPIO Base Address: 0x0060 */ #define MXC_R_GPIO_EN1 ((uint32_t)0x00000068UL) /**< Offset from GPIO Base Address: 0x0068 */ #define MXC_R_GPIO_EN1_SET ((uint32_t)0x0000006CUL) /**< Offset from GPIO Base Address: 0x006C */ #define MXC_R_GPIO_EN1_CLR ((uint32_t)0x00000070UL) /**< Offset from GPIO Base Address: 0x0070 */ @@ -473,39 +472,21 @@ typedef struct { /** * @ingroup gpio_registers - * @defgroup GPIO_PADCTRL0 GPIO_PADCTRL0 - * @brief GPIO Input Mode Config 0. Each bit in this register enables the weak pull-up for - * the associated GPIO pin in this port. + * @defgroup GPIO_PADCTRL GPIO_PADCTRL + * @brief GPIO Pad Control. Each bit in this register configures the pad for the + * associated GPIO pin in this port. * @{ */ -#define MXC_F_GPIO_PADCTRL0_ALL_POS 0 /**< PADCTRL0_ALL Position */ -#define MXC_F_GPIO_PADCTRL0_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_PADCTRL0_ALL_POS)) /**< PADCTRL0_ALL Mask */ -#define MXC_V_GPIO_PADCTRL0_ALL_IMPEDANCE ((uint32_t)0x0UL) /**< PADCTRL0_ALL_IMPEDANCE Value */ -#define MXC_S_GPIO_PADCTRL0_ALL_IMPEDANCE (MXC_V_GPIO_PADCTRL0_ALL_IMPEDANCE << MXC_F_GPIO_PADCTRL0_ALL_POS) /**< PADCTRL0_ALL_IMPEDANCE Setting */ -#define MXC_V_GPIO_PADCTRL0_ALL_PU ((uint32_t)0x1UL) /**< PADCTRL0_ALL_PU Value */ -#define MXC_S_GPIO_PADCTRL0_ALL_PU (MXC_V_GPIO_PADCTRL0_ALL_PU << MXC_F_GPIO_PADCTRL0_ALL_POS) /**< PADCTRL0_ALL_PU Setting */ -#define MXC_V_GPIO_PADCTRL0_ALL_PD ((uint32_t)0x2UL) /**< PADCTRL0_ALL_PD Value */ -#define MXC_S_GPIO_PADCTRL0_ALL_PD (MXC_V_GPIO_PADCTRL0_ALL_PD << MXC_F_GPIO_PADCTRL0_ALL_POS) /**< PADCTRL0_ALL_PD Setting */ +#define MXC_F_GPIO_PADCTRL_ALL_POS 0 /**< PADCTRL_ALL Position */ +#define MXC_F_GPIO_PADCTRL_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_PADCTRL_ALL_POS)) /**< PADCTRL_ALL Mask */ +#define MXC_V_GPIO_PADCTRL_ALL_IMPEDANCE ((uint32_t)0x0UL) /**< PADCTRL_ALL_IMPEDANCE Value */ +#define MXC_S_GPIO_PADCTRL_ALL_IMPEDANCE (MXC_V_GPIO_PADCTRL_ALL_IMPEDANCE << MXC_F_GPIO_PADCTRL_ALL_POS) /**< PADCTRL_ALL_IMPEDANCE Setting */ +#define MXC_V_GPIO_PADCTRL_ALL_PU ((uint32_t)0x1UL) /**< PADCTRL_ALL_PU Value */ +#define MXC_S_GPIO_PADCTRL_ALL_PU (MXC_V_GPIO_PADCTRL_ALL_PU << MXC_F_GPIO_PADCTRL_ALL_POS) /**< PADCTRL_ALL_PU Setting */ +#define MXC_V_GPIO_PADCTRL_ALL_PD ((uint32_t)0x2UL) /**< PADCTRL_ALL_PD Value */ +#define MXC_S_GPIO_PADCTRL_ALL_PD (MXC_V_GPIO_PADCTRL_ALL_PD << MXC_F_GPIO_PADCTRL_ALL_POS) /**< PADCTRL_ALL_PD Setting */ -/**@} end of group GPIO_PADCTRL0_Register */ - -/** - * @ingroup gpio_registers - * @defgroup GPIO_PADCTRL1 GPIO_PADCTRL1 - * @brief GPIO Input Mode Config 1. Each bit in this register enables the weak pull-up for - * the associated GPIO pin in this port. - * @{ - */ -#define MXC_F_GPIO_PADCTRL1_ALL_POS 0 /**< PADCTRL1_ALL Position */ -#define MXC_F_GPIO_PADCTRL1_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_PADCTRL1_ALL_POS)) /**< PADCTRL1_ALL Mask */ -#define MXC_V_GPIO_PADCTRL1_ALL_IMPEDANCE ((uint32_t)0x0UL) /**< PADCTRL1_ALL_IMPEDANCE Value */ -#define MXC_S_GPIO_PADCTRL1_ALL_IMPEDANCE (MXC_V_GPIO_PADCTRL1_ALL_IMPEDANCE << MXC_F_GPIO_PADCTRL1_ALL_POS) /**< PADCTRL1_ALL_IMPEDANCE Setting */ -#define MXC_V_GPIO_PADCTRL1_ALL_PU ((uint32_t)0x1UL) /**< PADCTRL1_ALL_PU Value */ -#define MXC_S_GPIO_PADCTRL1_ALL_PU (MXC_V_GPIO_PADCTRL1_ALL_PU << MXC_F_GPIO_PADCTRL1_ALL_POS) /**< PADCTRL1_ALL_PU Setting */ -#define MXC_V_GPIO_PADCTRL1_ALL_PD ((uint32_t)0x2UL) /**< PADCTRL1_ALL_PD Value */ -#define MXC_S_GPIO_PADCTRL1_ALL_PD (MXC_V_GPIO_PADCTRL1_ALL_PD << MXC_F_GPIO_PADCTRL1_ALL_POS) /**< PADCTRL1_ALL_PD Setting */ - -/**@} end of group GPIO_PADCTRL1_Register */ +/**@} end of group GPIO_PADCTRL_Register */ /** * @ingroup gpio_registers diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.svd b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.svd index 9b4940507e6..ecfcfda3e4c 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.svd +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.svd @@ -3353,8 +3353,8 @@ - PADCTRL0 - GPIO Input Mode Config 0. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port. + PADCTRL + GPIO Pad Control. Each bit in this register configures the pad for the associated GPIO pin in this port. 0x60 @@ -3382,36 +3382,6 @@ - - PADCTRL1 - GPIO Input Mode Config 1. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port. - 0x64 - - - ALL - The two bits in GPIO_PADCTRL0 and GPIO_PADCTRL1 for each GPIO pin work together to determine the pad mode when the GPIO is set to input mode. - 0 - 32 - - - impedance - High Impedance. - 0 - - - pu - Weak pull-up mode. - 1 - - - pd - weak pull-down mode. - 2 - - - - - EN1 GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port. @@ -8460,11 +8430,6 @@ TS2 is selected. 0x4 - - TS3 - TS3 is selected. - 0x8 - @@ -8682,7 +8647,7 @@ TSPOL Target Select Polarity, each Target Select can have unique polarity. 16 - 4 + 3 TS0_high @@ -8699,11 +8664,6 @@ TS2 active high. 0x4 - - TS3_high - TS3 active high. - 0x8 - @@ -10241,9 +10201,8 @@ RTCX1 - RTC X2 Capacitor Setting. + RTC X1 Capacitor Setting. 0x3C - read-only CAP diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/spi_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/spi_regs.h index c9443d1da82..75860a7efce 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/spi_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/spi_regs.h @@ -176,8 +176,6 @@ typedef struct { #define MXC_S_SPI_CTRL0_TS_ACTIVE_TS1 (MXC_V_SPI_CTRL0_TS_ACTIVE_TS1 << MXC_F_SPI_CTRL0_TS_ACTIVE_POS) /**< CTRL0_TS_ACTIVE_TS1 Setting */ #define MXC_V_SPI_CTRL0_TS_ACTIVE_TS2 ((uint32_t)0x4UL) /**< CTRL0_TS_ACTIVE_TS2 Value */ #define MXC_S_SPI_CTRL0_TS_ACTIVE_TS2 (MXC_V_SPI_CTRL0_TS_ACTIVE_TS2 << MXC_F_SPI_CTRL0_TS_ACTIVE_POS) /**< CTRL0_TS_ACTIVE_TS2 Setting */ -#define MXC_V_SPI_CTRL0_TS_ACTIVE_TS3 ((uint32_t)0x8UL) /**< CTRL0_TS_ACTIVE_TS3 Value */ -#define MXC_S_SPI_CTRL0_TS_ACTIVE_TS3 (MXC_V_SPI_CTRL0_TS_ACTIVE_TS3 << MXC_F_SPI_CTRL0_TS_ACTIVE_POS) /**< CTRL0_TS_ACTIVE_TS3 Setting */ /**@} end of group SPI_CTRL0_Register */ @@ -258,15 +256,13 @@ typedef struct { #define MXC_F_SPI_CTRL2_THREE_WIRE ((uint32_t)(0x1UL << MXC_F_SPI_CTRL2_THREE_WIRE_POS)) /**< CTRL2_THREE_WIRE Mask */ #define MXC_F_SPI_CTRL2_TSPOL_POS 16 /**< CTRL2_TSPOL Position */ -#define MXC_F_SPI_CTRL2_TSPOL ((uint32_t)(0xFUL << MXC_F_SPI_CTRL2_TSPOL_POS)) /**< CTRL2_TSPOL Mask */ +#define MXC_F_SPI_CTRL2_TSPOL ((uint32_t)(0x7UL << MXC_F_SPI_CTRL2_TSPOL_POS)) /**< CTRL2_TSPOL Mask */ #define MXC_V_SPI_CTRL2_TSPOL_TS0_HIGH ((uint32_t)0x1UL) /**< CTRL2_TSPOL_TS0_HIGH Value */ #define MXC_S_SPI_CTRL2_TSPOL_TS0_HIGH (MXC_V_SPI_CTRL2_TSPOL_TS0_HIGH << MXC_F_SPI_CTRL2_TSPOL_POS) /**< CTRL2_TSPOL_TS0_HIGH Setting */ #define MXC_V_SPI_CTRL2_TSPOL_TS1_HIGH ((uint32_t)0x2UL) /**< CTRL2_TSPOL_TS1_HIGH Value */ #define MXC_S_SPI_CTRL2_TSPOL_TS1_HIGH (MXC_V_SPI_CTRL2_TSPOL_TS1_HIGH << MXC_F_SPI_CTRL2_TSPOL_POS) /**< CTRL2_TSPOL_TS1_HIGH Setting */ #define MXC_V_SPI_CTRL2_TSPOL_TS2_HIGH ((uint32_t)0x4UL) /**< CTRL2_TSPOL_TS2_HIGH Value */ #define MXC_S_SPI_CTRL2_TSPOL_TS2_HIGH (MXC_V_SPI_CTRL2_TSPOL_TS2_HIGH << MXC_F_SPI_CTRL2_TSPOL_POS) /**< CTRL2_TSPOL_TS2_HIGH Setting */ -#define MXC_V_SPI_CTRL2_TSPOL_TS3_HIGH ((uint32_t)0x8UL) /**< CTRL2_TSPOL_TS3_HIGH Value */ -#define MXC_S_SPI_CTRL2_TSPOL_TS3_HIGH (MXC_V_SPI_CTRL2_TSPOL_TS3_HIGH << MXC_F_SPI_CTRL2_TSPOL_POS) /**< CTRL2_TSPOL_TS3_HIGH Setting */ /**@} end of group SPI_CTRL2_Register */ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/trimsir_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/trimsir_regs.h index bd2d9012288..63a2682e7a6 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/trimsir_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/trimsir_regs.h @@ -73,7 +73,7 @@ extern "C" { */ typedef struct { __R uint32_t rsv_0x0_0x3b[15]; - __I uint32_t rtcx1; /**< \b 0x3C: TRIMSIR RTCX1 Register */ + __IO uint32_t rtcx1; /**< \b 0x3C: TRIMSIR RTCX1 Register */ __R uint32_t rsv_0x40; __IO uint32_t rtcx2; /**< \b 0x44: TRIMSIR RTCX2 Register */ } mxc_trimsir_regs_t; @@ -92,7 +92,7 @@ typedef struct { /** * @ingroup trimsir_registers * @defgroup TRIMSIR_RTCX1 TRIMSIR_RTCX1 - * @brief RTC X2 Capacitor Setting. + * @brief RTC X1 Capacitor Setting. * @{ */ #define MXC_F_TRIMSIR_RTCX1_CAP_POS 0 /**< RTCX1_CAP Position */ diff --git a/Libraries/PeriphDrivers/Include/MAX32657/gpio.h b/Libraries/PeriphDrivers/Include/MAX32657/gpio.h index db68a95e572..cf1a7ad6c8e 100644 --- a/Libraries/PeriphDrivers/Include/MAX32657/gpio.h +++ b/Libraries/PeriphDrivers/Include/MAX32657/gpio.h @@ -151,8 +151,6 @@ typedef enum { */ typedef enum { MXC_GPIO_PAD_NONE, /**< No pull-up or pull-down */ - MXC_GPIO_PAD_PULL_UP, /**< Set pad to strong pull-up */ - MXC_GPIO_PAD_PULL_DOWN, /**< Set pad to strong pull-down */ MXC_GPIO_PAD_WEAK_PULL_UP, /**< Set pad to weak pull-up */ MXC_GPIO_PAD_WEAK_PULL_DOWN /**< Set pad to weak pull-down */ } mxc_gpio_pad_t; diff --git a/Libraries/PeriphDrivers/Source/GPIO/gpio_me30.c b/Libraries/PeriphDrivers/Source/GPIO/gpio_me30.c index c7e07a07063..335e2a3d956 100644 --- a/Libraries/PeriphDrivers/Source/GPIO/gpio_me30.c +++ b/Libraries/PeriphDrivers/Source/GPIO/gpio_me30.c @@ -96,33 +96,16 @@ int MXC_GPIO_Config(const mxc_gpio_cfg_t *cfg) // Configure the pad switch (cfg->pad) { case MXC_GPIO_PAD_NONE: - gpio->padctrl0 &= ~cfg->mask; - gpio->padctrl1 &= ~cfg->mask; + gpio->padctrl &= ~cfg->mask; break; - // Note: for "ps" field set 1 for weak and 0 for strong. - // As of 8-28-2024 most UG tables have this flipped the wrong way case MXC_GPIO_PAD_WEAK_PULL_UP: - gpio->padctrl0 |= cfg->mask; - gpio->padctrl1 &= ~cfg->mask; + gpio->padctrl |= cfg->mask; gpio->pssel |= cfg->mask; break; - case MXC_GPIO_PAD_PULL_UP: - gpio->padctrl0 |= cfg->mask; - gpio->padctrl1 &= ~cfg->mask; - gpio->pssel &= ~cfg->mask; - break; - case MXC_GPIO_PAD_WEAK_PULL_DOWN: - gpio->padctrl0 &= ~cfg->mask; - gpio->padctrl1 |= cfg->mask; - gpio->pssel |= cfg->mask; - break; - - case MXC_GPIO_PAD_PULL_DOWN: - gpio->padctrl0 &= ~cfg->mask; - gpio->padctrl1 |= cfg->mask; + gpio->padctrl |= cfg->mask; gpio->pssel &= ~cfg->mask; break; diff --git a/Libraries/PeriphDrivers/Source/GPIO/gpio_reva_me30.svd b/Libraries/PeriphDrivers/Source/GPIO/gpio_reva_me30.svd index 2020a611e38..a9a08a0a878 100644 --- a/Libraries/PeriphDrivers/Source/GPIO/gpio_reva_me30.svd +++ b/Libraries/PeriphDrivers/Source/GPIO/gpio_reva_me30.svd @@ -443,8 +443,8 @@ - PADCTRL0 - GPIO Input Mode Config 0. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port. + PADCTRL + GPIO Pad Control. Each bit in this register configures the pad for the associated GPIO pin in this port. 0x60 @@ -472,36 +472,6 @@ - - PADCTRL1 - GPIO Input Mode Config 1. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port. - 0x64 - - - ALL - The two bits in GPIO_PADCTRL0 and GPIO_PADCTRL1 for each GPIO pin work together to determine the pad mode when the GPIO is set to input mode. - 0 - 32 - - - impedance - High Impedance. - 0 - - - pu - Weak pull-up mode. - 1 - - - pd - weak pull-down mode. - 2 - - - - - EN1 GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port. diff --git a/Libraries/PeriphDrivers/Source/RTC/rtc_me30.c b/Libraries/PeriphDrivers/Source/RTC/rtc_me30.c index c8fe6636bf6..313a1012953 100644 --- a/Libraries/PeriphDrivers/Source/RTC/rtc_me30.c +++ b/Libraries/PeriphDrivers/Source/RTC/rtc_me30.c @@ -151,13 +151,10 @@ int MXC_RTC_GetBusyFlag(void) return MXC_RTC_RevA_GetBusyFlag((mxc_rtc_reva_regs_t *)MXC_RTC); } +// TODO(SW): TRIMSIR RTC X1/X2 register descriptions were updated due to design changes. +// CAP vs TRIM value differences unknown, and this function has not been tested. int MXC_RTC_TrimCrystal(void) { -#if TARGET_NUM == 78000 - /* MAX78000 does not have the ERFO clock which the Trim function requires */ - return E_NOT_SUPPORTED; -#endif - unsigned int search_step, elapsed; unsigned int upper, lower, trim, oldtrim, bestTrim, bestElapsed, bestElapsedDiff; unsigned int freq = NOM_32K_FREQ; @@ -209,10 +206,10 @@ int MXC_RTC_TrimCrystal(void) } /* Set the trim values */ - MXC_SETFIELD(MXC_TRIMSIR->rtc, MXC_F_TRIMSIR_RTC_X1TRIM, - (trim << MXC_F_TRIMSIR_RTC_X1TRIM_POS)); - MXC_SETFIELD(MXC_TRIMSIR->rtc, MXC_F_TRIMSIR_RTC_X2TRIM, - (trim << MXC_F_TRIMSIR_RTC_X2TRIM_POS)); + MXC_SETFIELD(MXC_TRIMSIR->rtcx1, MXC_F_TRIMSIR_RTCX1_CAP, + (trim << MXC_F_TRIMSIR_RTCX1_CAP_POS)); + MXC_SETFIELD(MXC_TRIMSIR->rtcx2, MXC_F_TRIMSIR_RTCX2_CAP, + (trim << MXC_F_TRIMSIR_RTCX2_CAP_POS)); /* Sleep to settle new caps */ MXC_Delay(MXC_DELAY_MSEC(10)); @@ -263,10 +260,10 @@ int MXC_RTC_TrimCrystal(void) } /* Apply the closest trim setting */ - MXC_SETFIELD(MXC_TRIMSIR->rtc, MXC_F_TRIMSIR_RTC_X1TRIM, - (bestTrim << MXC_F_TRIMSIR_RTC_X1TRIM_POS)); - MXC_SETFIELD(MXC_TRIMSIR->rtc, MXC_F_TRIMSIR_RTC_X2TRIM, - (bestTrim << MXC_F_TRIMSIR_RTC_X2TRIM_POS)); + MXC_SETFIELD(MXC_TRIMSIR->rtcx1, MXC_F_TRIMSIR_RTCX1_CAP, + (bestTrim << MXC_F_TRIMSIR_RTCX1_CAP_POS)); + MXC_SETFIELD(MXC_TRIMSIR->rtcx2, MXC_F_TRIMSIR_RTCX2_CAP, + (bestTrim << MXC_F_TRIMSIR_RTCX2_CAP_POS)); /* Adjust 32K freq if we can't get close enough to 32768 Hz */ if (bestElapsed >= SEARCH_TARGET) { diff --git a/Libraries/PeriphDrivers/Source/SPI/spi_reva_me30.svd b/Libraries/PeriphDrivers/Source/SPI/spi_reva_me30.svd index 2f6efe4139a..d891741001c 100644 --- a/Libraries/PeriphDrivers/Source/SPI/spi_reva_me30.svd +++ b/Libraries/PeriphDrivers/Source/SPI/spi_reva_me30.svd @@ -177,11 +177,6 @@ TS2 is selected. 0x4 - - TS3 - TS3 is selected. - 0x8 - @@ -399,7 +394,7 @@ TSPOL Target Select Polarity, each Target Select can have unique polarity. 16 - 4 + 3 TS0_high @@ -416,11 +411,6 @@ TS2 active high. 0x4 - - TS3_high - TS3 active high. - 0x8 - diff --git a/Libraries/PeriphDrivers/Source/SYS/SVD/trimsir_me30.svd b/Libraries/PeriphDrivers/Source/SYS/SVD/trimsir_me30.svd index d2c572d5dad..c834decfd1f 100644 --- a/Libraries/PeriphDrivers/Source/SYS/SVD/trimsir_me30.svd +++ b/Libraries/PeriphDrivers/Source/SYS/SVD/trimsir_me30.svd @@ -12,9 +12,8 @@ RTCX1 - RTC X2 Capacitor Setting. + RTC X1 Capacitor Setting. 0x3C - read-only CAP diff --git a/Libraries/PeriphDrivers/Source/WUT/wut_me30.c b/Libraries/PeriphDrivers/Source/WUT/wut_me30.c index 7f6f8689381..2d51c4d2f8f 100644 --- a/Libraries/PeriphDrivers/Source/WUT/wut_me30.c +++ b/Libraries/PeriphDrivers/Source/WUT/wut_me30.c @@ -168,13 +168,15 @@ static void MXC_WUT_GetWUTSync(mxc_wut_regs_t *wut, uint32_t *wutCnt, uint32_t * /* ************************************************************************** */ static void MXC_WUT_SetTrim(uint32_t trimValue) { - MXC_SETFIELD(MXC_TRIMSIR->rtc, MXC_F_TRIMSIR_RTC_X1TRIM, - (trimValue << MXC_F_TRIMSIR_RTC_X1TRIM_POS)); - MXC_SETFIELD(MXC_TRIMSIR->rtc, MXC_F_TRIMSIR_RTC_X2TRIM, - (trimValue << MXC_F_TRIMSIR_RTC_X2TRIM_POS)); + MXC_SETFIELD(MXC_TRIMSIR->rtcx1, MXC_F_TRIMSIR_RTCX1_CAP, + (trimValue << MXC_F_TRIMSIR_RTCX1_CAP_POS)); + MXC_SETFIELD(MXC_TRIMSIR->rtcx2, MXC_F_TRIMSIR_RTCX2_CAP, + (trimValue << MXC_F_TRIMSIR_RTCX2_CAP_POS)); } /* ************************************************************************** */ +// TODO(SW): TRIMSIR RTC X1/X2 register descriptions were updated due to design changes. +// CAP vs TRIM value differences unknown, and this function has not been tested. static int MXC_WUT_StartTrim(mxc_wut_regs_t *wut) { uint32_t wutCnt0, wutCnt1; @@ -194,7 +196,7 @@ static int MXC_WUT_StartTrim(mxc_wut_regs_t *wut) } /* Start with existing trim value */ - trimValue = (MXC_TRIMSIR->rtc & MXC_F_TRIMSIR_RTC_X1TRIM) >> MXC_F_TRIMSIR_RTC_X1TRIM_POS; + trimValue = (MXC_TRIMSIR->rtcx1 & MXC_F_TRIMSIR_RTCX1_CAP) >> MXC_F_TRIMSIR_RTCX1_CAP_POS; MXC_WUT_SetTrim(trimValue); /* Initialize the variables */ @@ -236,7 +238,7 @@ int MXC_WUT_Handler(mxc_wut_regs_t *wut) calcTicks = ((uint64_t)wutTicks * (uint64_t)BB_CLK_RATE_HZ) / (uint64_t)32768; trimComplete = 0; - trimValue = (MXC_TRIMSIR->rtc & MXC_F_TRIMSIR_RTC_X1TRIM) >> MXC_F_TRIMSIR_RTC_X1TRIM_POS; + trimValue = (MXC_TRIMSIR->rtcx1 & MXC_F_TRIMSIR_RTCX1_CAP) >> MXC_F_TRIMSIR_RTCX1_CAP_POS; if (snapTicks > calcTicks) { /* See if we're closer to the calculated value */ From 679fc79d66f0f64a4a1b323c11b98fd9117d22a2 Mon Sep 17 00:00:00 2001 From: Kevin Gillespie Date: Mon, 14 Oct 2024 14:50:58 -0500 Subject: [PATCH 05/37] fix(BLE): Converting bool_t to bool (#1227) --- Examples/MAX32655/Bluetooth/BLE5_ctr/main.c | 2 +- .../Bluetooth/BLE_FreeRTOS/stack_dats.c | 2 +- .../MAX32655/Bluetooth/BLE_HCI_DFU/BLT/main.c | 2 +- Examples/MAX32655/Bluetooth/BLE_datc/main.c | 2 +- Examples/MAX32655/Bluetooth/BLE_dats/main.c | 2 +- Examples/MAX32655/Bluetooth/BLE_fit/main.c | 2 +- .../Bluetooth/BLE_fit_FreeRTOS/bt_stack.c | 2 +- Examples/MAX32655/Bluetooth/BLE_mcs/main.c | 2 +- Examples/MAX32655/Bluetooth/BLE_otac/main.c | 2 +- Examples/MAX32655/Bluetooth/BLE_otas/main.c | 2 +- Examples/MAX32655/Bluetooth/RF_Test/main.c | 2 +- Examples/MAX32665/Bluetooth/BLE5_ctr/main.c | 2 +- .../Bluetooth/BLE_FreeRTOS/stack_dats.c | 2 +- .../MAX32665/Bluetooth/BLE_LR_Central/main.c | 2 +- .../Bluetooth/BLE_LR_Peripheral/main.c | 2 +- Examples/MAX32665/Bluetooth/BLE_datc/main.c | 2 +- Examples/MAX32665/Bluetooth/BLE_dats/main.c | 2 +- Examples/MAX32665/Bluetooth/BLE_fit/main.c | 2 +- Examples/MAX32665/Bluetooth/BLE_mcs/main.c | 2 +- Examples/MAX32665/Bluetooth/BLE_otac/main.c | 2 +- Examples/MAX32665/Bluetooth/BLE_otas/main.c | 2 +- Examples/MAX32665/Bluetooth/RF_Test/main.c | 2 +- Examples/MAX32680/Bluetooth/BLE_dats/main.c | 2 +- Examples/MAX32690/Bluetooth/BLE5_ctr/main.c | 2 +- .../Bluetooth/BLE_FreeRTOS/stack_dats.c | 2 +- Examples/MAX32690/Bluetooth/BLE_datc/main.c | 2 +- Examples/MAX32690/Bluetooth/BLE_dats/main.c | 2 +- Examples/MAX32690/Bluetooth/BLE_fit/main.c | 2 +- Examples/MAX32690/Bluetooth/BLE_mcs/main.c | 2 +- Examples/MAX32690/Bluetooth/BLE_otac/main.c | 2 +- Examples/MAX32690/Bluetooth/BLE_otas/main.c | 2 +- Examples/MAX32690/Bluetooth/RF_Test/main.c | 2 +- .../ble-profiles/sources/af/common/app_db.c | 50 +++++++++---------- .../controller/sources/ble/lhci/lhci_cmd_vs.c | 1 - Libraries/Cordio/platform/include/pal_types.h | 7 +-- Libraries/Cordio/wsf/include/wsf_types.h | 17 +------ 36 files changed, 63 insertions(+), 76 deletions(-) diff --git a/Examples/MAX32655/Bluetooth/BLE5_ctr/main.c b/Examples/MAX32655/Bluetooth/BLE5_ctr/main.c index e2b71be0524..864348ee44a 100644 --- a/Examples/MAX32655/Bluetooth/BLE5_ctr/main.c +++ b/Examples/MAX32655/Bluetooth/BLE5_ctr/main.c @@ -76,7 +76,7 @@ static void mainLoadConfiguration(void) PalBbLoadCfg((PalBbCfg_t *)&mainBbRtCfg); LlGetDefaultRunTimeCfg(&mainLlRtCfg); PalCfgLoadData(PAL_CFG_ID_LL_PARAM, &mainLlRtCfg.maxAdvSets, sizeof(LlRtCfg_t) - 9); - PalCfgLoadData(PAL_CFG_ID_BLE_PHY, &mainLlRtCfg.phy2mSup, 4); + PalCfgLoadData(PAL_CFG_ID_BLE_PHY, (uint8_t *)&mainLlRtCfg.phy2mSup, 4); /* Set 5.0 requirements. */ mainLlRtCfg.btVer = BT_VER; diff --git a/Examples/MAX32655/Bluetooth/BLE_FreeRTOS/stack_dats.c b/Examples/MAX32655/Bluetooth/BLE_FreeRTOS/stack_dats.c index c38bc6e9f33..be5185af202 100644 --- a/Examples/MAX32655/Bluetooth/BLE_FreeRTOS/stack_dats.c +++ b/Examples/MAX32655/Bluetooth/BLE_FreeRTOS/stack_dats.c @@ -308,7 +308,7 @@ void bleStartup(void) #endif PalCfgLoadData(PAL_CFG_ID_LL_PARAM, &mainLlRtCfg.maxAdvSets, sizeof(LlRtCfg_t) - 9); #if (BT_VER >= LL_VER_BT_CORE_SPEC_5_0) - PalCfgLoadData(PAL_CFG_ID_BLE_PHY, &mainLlRtCfg.phy2mSup, 4); + PalCfgLoadData(PAL_CFG_ID_BLE_PHY, (uint8_t *)&mainLlRtCfg.phy2mSup, 4); #endif /* Set the 32k sleep clock accuracy into one of the following bins, default is 20 diff --git a/Examples/MAX32655/Bluetooth/BLE_HCI_DFU/BLT/main.c b/Examples/MAX32655/Bluetooth/BLE_HCI_DFU/BLT/main.c index 97389b08e6d..d44a212cdcc 100644 --- a/Examples/MAX32655/Bluetooth/BLE_HCI_DFU/BLT/main.c +++ b/Examples/MAX32655/Bluetooth/BLE_HCI_DFU/BLT/main.c @@ -83,7 +83,7 @@ static void mainLoadConfiguration(void) PalBbLoadCfg((PalBbCfg_t *)&mainBbRtCfg); LlGetDefaultRunTimeCfg(&mainLlRtCfg); PalCfgLoadData(PAL_CFG_ID_LL_PARAM, &mainLlRtCfg.maxAdvSets, sizeof(LlRtCfg_t) - 9); - PalCfgLoadData(PAL_CFG_ID_BLE_PHY, &mainLlRtCfg.phy2mSup, 4); + PalCfgLoadData(PAL_CFG_ID_BLE_PHY, (uint8_t *)&mainLlRtCfg.phy2mSup, 4); /* Set 5.0 requirements. */ mainLlRtCfg.btVer = BT_VER; diff --git a/Examples/MAX32655/Bluetooth/BLE_datc/main.c b/Examples/MAX32655/Bluetooth/BLE_datc/main.c index 79d4df10763..5ffb01957b7 100644 --- a/Examples/MAX32655/Bluetooth/BLE_datc/main.c +++ b/Examples/MAX32655/Bluetooth/BLE_datc/main.c @@ -189,7 +189,7 @@ int main(void) #endif PalCfgLoadData(PAL_CFG_ID_LL_PARAM, &mainLlRtCfg.maxAdvSets, sizeof(LlRtCfg_t) - 9); #if (BT_VER >= LL_VER_BT_CORE_SPEC_5_0) - PalCfgLoadData(PAL_CFG_ID_BLE_PHY, &mainLlRtCfg.phy2mSup, 4); + PalCfgLoadData(PAL_CFG_ID_BLE_PHY, (uint8_t *)&mainLlRtCfg.phy2mSup, 4); #endif /* Set the 32k sleep clock accuracy into one of the following bins, default is 20 diff --git a/Examples/MAX32655/Bluetooth/BLE_dats/main.c b/Examples/MAX32655/Bluetooth/BLE_dats/main.c index 7e3cf7c7d05..bdcee7ab7cc 100644 --- a/Examples/MAX32655/Bluetooth/BLE_dats/main.c +++ b/Examples/MAX32655/Bluetooth/BLE_dats/main.c @@ -189,7 +189,7 @@ int main(void) #endif PalCfgLoadData(PAL_CFG_ID_LL_PARAM, &mainLlRtCfg.maxAdvSets, sizeof(LlRtCfg_t) - 9); #if (BT_VER >= LL_VER_BT_CORE_SPEC_5_0) - PalCfgLoadData(PAL_CFG_ID_BLE_PHY, &mainLlRtCfg.phy2mSup, 4); + PalCfgLoadData(PAL_CFG_ID_BLE_PHY, (uint8_t *)&mainLlRtCfg.phy2mSup, 4); #endif /* Set the 32k sleep clock accuracy into one of the following bins, default is 20 diff --git a/Examples/MAX32655/Bluetooth/BLE_fit/main.c b/Examples/MAX32655/Bluetooth/BLE_fit/main.c index d583cbf6d79..0199877ad72 100644 --- a/Examples/MAX32655/Bluetooth/BLE_fit/main.c +++ b/Examples/MAX32655/Bluetooth/BLE_fit/main.c @@ -175,7 +175,7 @@ int main(void) #endif PalCfgLoadData(PAL_CFG_ID_LL_PARAM, &mainLlRtCfg.maxAdvSets, sizeof(LlRtCfg_t) - 9); #if (BT_VER >= LL_VER_BT_CORE_SPEC_5_0) - PalCfgLoadData(PAL_CFG_ID_BLE_PHY, &mainLlRtCfg.phy2mSup, 4); + PalCfgLoadData(PAL_CFG_ID_BLE_PHY, (uint8_t *)&mainLlRtCfg.phy2mSup, 4); #endif /* Set the 32k sleep clock accuracy into one of the following bins, default is 20 diff --git a/Examples/MAX32655/Bluetooth/BLE_fit_FreeRTOS/bt_stack.c b/Examples/MAX32655/Bluetooth/BLE_fit_FreeRTOS/bt_stack.c index cd11150b38e..68f0c51d05d 100644 --- a/Examples/MAX32655/Bluetooth/BLE_fit_FreeRTOS/bt_stack.c +++ b/Examples/MAX32655/Bluetooth/BLE_fit_FreeRTOS/bt_stack.c @@ -308,7 +308,7 @@ void btStartup(void) #endif PalCfgLoadData(PAL_CFG_ID_LL_PARAM, &mainLlRtCfg.maxAdvSets, sizeof(LlRtCfg_t) - 9); #if (BT_VER >= LL_VER_BT_CORE_SPEC_5_0) - PalCfgLoadData(PAL_CFG_ID_BLE_PHY, &mainLlRtCfg.phy2mSup, 4); + PalCfgLoadData(PAL_CFG_ID_BLE_PHY, (uint8_t *)&mainLlRtCfg.phy2mSup, 4); #endif /* Set the 32k sleep clock accuracy into one of the following bins, default is 20 diff --git a/Examples/MAX32655/Bluetooth/BLE_mcs/main.c b/Examples/MAX32655/Bluetooth/BLE_mcs/main.c index a53eb4a80ca..507205876e8 100644 --- a/Examples/MAX32655/Bluetooth/BLE_mcs/main.c +++ b/Examples/MAX32655/Bluetooth/BLE_mcs/main.c @@ -163,7 +163,7 @@ int main(void) #endif PalCfgLoadData(PAL_CFG_ID_LL_PARAM, &mainLlRtCfg.maxAdvSets, sizeof(LlRtCfg_t) - 9); #if (BT_VER >= LL_VER_BT_CORE_SPEC_5_0) - PalCfgLoadData(PAL_CFG_ID_BLE_PHY, &mainLlRtCfg.phy2mSup, 4); + PalCfgLoadData(PAL_CFG_ID_BLE_PHY, (uint8_t *)&mainLlRtCfg.phy2mSup, 4); #endif /* Set the 32k sleep clock accuracy into one of the following bins, default is 20 diff --git a/Examples/MAX32655/Bluetooth/BLE_otac/main.c b/Examples/MAX32655/Bluetooth/BLE_otac/main.c index 49d7d9f6202..e0b023266b5 100644 --- a/Examples/MAX32655/Bluetooth/BLE_otac/main.c +++ b/Examples/MAX32655/Bluetooth/BLE_otac/main.c @@ -190,7 +190,7 @@ int main(void) #endif PalCfgLoadData(PAL_CFG_ID_LL_PARAM, &mainLlRtCfg.maxAdvSets, sizeof(LlRtCfg_t) - 9); #if (BT_VER >= LL_VER_BT_CORE_SPEC_5_0) - PalCfgLoadData(PAL_CFG_ID_BLE_PHY, &mainLlRtCfg.phy2mSup, 4); + PalCfgLoadData(PAL_CFG_ID_BLE_PHY, (uint8_t *)&mainLlRtCfg.phy2mSup, 4); #endif /* Set the 32k sleep clock accuracy into one of the following bins, default is 20 diff --git a/Examples/MAX32655/Bluetooth/BLE_otas/main.c b/Examples/MAX32655/Bluetooth/BLE_otas/main.c index c4f2320eaa4..01a0b4b19fe 100644 --- a/Examples/MAX32655/Bluetooth/BLE_otas/main.c +++ b/Examples/MAX32655/Bluetooth/BLE_otas/main.c @@ -202,7 +202,7 @@ int main(void) #endif PalCfgLoadData(PAL_CFG_ID_LL_PARAM, &mainLlRtCfg.maxAdvSets, sizeof(LlRtCfg_t) - 9); #if (BT_VER >= LL_VER_BT_CORE_SPEC_5_0) - PalCfgLoadData(PAL_CFG_ID_BLE_PHY, &mainLlRtCfg.phy2mSup, 4); + PalCfgLoadData(PAL_CFG_ID_BLE_PHY, (uint8_t *)&mainLlRtCfg.phy2mSup, 4); #endif /* Set the 32k sleep clock accuracy into one of the following bins, default is 20 diff --git a/Examples/MAX32655/Bluetooth/RF_Test/main.c b/Examples/MAX32655/Bluetooth/RF_Test/main.c index 459bfac8cef..ad2168753c4 100644 --- a/Examples/MAX32655/Bluetooth/RF_Test/main.c +++ b/Examples/MAX32655/Bluetooth/RF_Test/main.c @@ -462,7 +462,7 @@ static void mainLoadConfiguration(void) PalBbLoadCfg((PalBbCfg_t *)&mainBbRtCfg); LlGetDefaultRunTimeCfg(&mainLlRtCfg); PalCfgLoadData(PAL_CFG_ID_LL_PARAM, &mainLlRtCfg.maxAdvSets, sizeof(LlRtCfg_t) - 9); - PalCfgLoadData(PAL_CFG_ID_BLE_PHY, &mainLlRtCfg.phy2mSup, 4); + PalCfgLoadData(PAL_CFG_ID_BLE_PHY, (uint8_t *)&mainLlRtCfg.phy2mSup, 4); /* Set 5.1 requirements. */ mainLlRtCfg.btVer = LL_VER_BT_CORE_SPEC_5_0; diff --git a/Examples/MAX32665/Bluetooth/BLE5_ctr/main.c b/Examples/MAX32665/Bluetooth/BLE5_ctr/main.c index 62ff05a1c54..0d9f01d126c 100644 --- a/Examples/MAX32665/Bluetooth/BLE5_ctr/main.c +++ b/Examples/MAX32665/Bluetooth/BLE5_ctr/main.c @@ -76,7 +76,7 @@ static void mainLoadConfiguration(void) PalBbLoadCfg((PalBbCfg_t *)&mainBbRtCfg); LlGetDefaultRunTimeCfg(&mainLlRtCfg); PalCfgLoadData(PAL_CFG_ID_LL_PARAM, &mainLlRtCfg.maxAdvSets, sizeof(LlRtCfg_t) - 9); - PalCfgLoadData(PAL_CFG_ID_BLE_PHY, &mainLlRtCfg.phy2mSup, 4); + PalCfgLoadData(PAL_CFG_ID_BLE_PHY, (uint8_t *)&mainLlRtCfg.phy2mSup, 4); /* Set 5.0 requirements. */ mainLlRtCfg.btVer = BT_VER; diff --git a/Examples/MAX32665/Bluetooth/BLE_FreeRTOS/stack_dats.c b/Examples/MAX32665/Bluetooth/BLE_FreeRTOS/stack_dats.c index 4c4a35eb7d8..c262788bb8d 100644 --- a/Examples/MAX32665/Bluetooth/BLE_FreeRTOS/stack_dats.c +++ b/Examples/MAX32665/Bluetooth/BLE_FreeRTOS/stack_dats.c @@ -341,7 +341,7 @@ void bleStartup(void) #endif PalCfgLoadData(PAL_CFG_ID_LL_PARAM, &mainLlRtCfg.maxAdvSets, sizeof(LlRtCfg_t) - 9); #if (BT_VER >= LL_VER_BT_CORE_SPEC_5_0) - PalCfgLoadData(PAL_CFG_ID_BLE_PHY, &mainLlRtCfg.phy2mSup, 4); + PalCfgLoadData(PAL_CFG_ID_BLE_PHY, (uint8_t *)&mainLlRtCfg.phy2mSup, 4); #endif /* Set the 32k sleep clock accuracy into one of the following bins, default is 20 diff --git a/Examples/MAX32665/Bluetooth/BLE_LR_Central/main.c b/Examples/MAX32665/Bluetooth/BLE_LR_Central/main.c index e18016b6532..93dbda8a127 100644 --- a/Examples/MAX32665/Bluetooth/BLE_LR_Central/main.c +++ b/Examples/MAX32665/Bluetooth/BLE_LR_Central/main.c @@ -208,7 +208,7 @@ int main(void) #endif PalCfgLoadData(PAL_CFG_ID_LL_PARAM, &mainLlRtCfg.maxAdvSets, sizeof(LlRtCfg_t) - 9); #if (BT_VER >= LL_VER_BT_CORE_SPEC_5_0) - PalCfgLoadData(PAL_CFG_ID_BLE_PHY, &mainLlRtCfg.phy2mSup, 4); + PalCfgLoadData(PAL_CFG_ID_BLE_PHY, (uint8_t *)&mainLlRtCfg.phy2mSup, 4); #endif /* Set the 32k sleep clock accuracy into one of the following bins, default is 20 diff --git a/Examples/MAX32665/Bluetooth/BLE_LR_Peripheral/main.c b/Examples/MAX32665/Bluetooth/BLE_LR_Peripheral/main.c index d6bceb705f7..4f86e3bc239 100644 --- a/Examples/MAX32665/Bluetooth/BLE_LR_Peripheral/main.c +++ b/Examples/MAX32665/Bluetooth/BLE_LR_Peripheral/main.c @@ -207,7 +207,7 @@ int main(void) #endif PalCfgLoadData(PAL_CFG_ID_LL_PARAM, &mainLlRtCfg.maxAdvSets, sizeof(LlRtCfg_t) - 9); #if (BT_VER >= LL_VER_BT_CORE_SPEC_5_0) - PalCfgLoadData(PAL_CFG_ID_BLE_PHY, &mainLlRtCfg.phy2mSup, 4); + PalCfgLoadData(PAL_CFG_ID_BLE_PHY, (uint8_t *)&mainLlRtCfg.phy2mSup, 4); #endif /* Set the 32k sleep clock accuracy into one of the following bins, default is 20 diff --git a/Examples/MAX32665/Bluetooth/BLE_datc/main.c b/Examples/MAX32665/Bluetooth/BLE_datc/main.c index f0700a02017..26c3b1cb10e 100644 --- a/Examples/MAX32665/Bluetooth/BLE_datc/main.c +++ b/Examples/MAX32665/Bluetooth/BLE_datc/main.c @@ -206,7 +206,7 @@ int main(void) #endif PalCfgLoadData(PAL_CFG_ID_LL_PARAM, &mainLlRtCfg.maxAdvSets, sizeof(LlRtCfg_t) - 9); #if (BT_VER >= LL_VER_BT_CORE_SPEC_5_0) - PalCfgLoadData(PAL_CFG_ID_BLE_PHY, &mainLlRtCfg.phy2mSup, 4); + PalCfgLoadData(PAL_CFG_ID_BLE_PHY, (uint8_t *)&mainLlRtCfg.phy2mSup, 4); #endif /* Set the 32k sleep clock accuracy into one of the following bins, default is 20 diff --git a/Examples/MAX32665/Bluetooth/BLE_dats/main.c b/Examples/MAX32665/Bluetooth/BLE_dats/main.c index bdd2cbd8b0d..f6792f04e03 100644 --- a/Examples/MAX32665/Bluetooth/BLE_dats/main.c +++ b/Examples/MAX32665/Bluetooth/BLE_dats/main.c @@ -207,7 +207,7 @@ int main(void) #endif PalCfgLoadData(PAL_CFG_ID_LL_PARAM, &mainLlRtCfg.maxAdvSets, sizeof(LlRtCfg_t) - 9); #if (BT_VER >= LL_VER_BT_CORE_SPEC_5_0) - PalCfgLoadData(PAL_CFG_ID_BLE_PHY, &mainLlRtCfg.phy2mSup, 4); + PalCfgLoadData(PAL_CFG_ID_BLE_PHY, (uint8_t *)&mainLlRtCfg.phy2mSup, 4); #endif /* Set the 32k sleep clock accuracy into one of the following bins, default is 20 diff --git a/Examples/MAX32665/Bluetooth/BLE_fit/main.c b/Examples/MAX32665/Bluetooth/BLE_fit/main.c index 6650ab98da2..308f7221b19 100644 --- a/Examples/MAX32665/Bluetooth/BLE_fit/main.c +++ b/Examples/MAX32665/Bluetooth/BLE_fit/main.c @@ -206,7 +206,7 @@ int main(void) #endif PalCfgLoadData(PAL_CFG_ID_LL_PARAM, &mainLlRtCfg.maxAdvSets, sizeof(LlRtCfg_t) - 9); #if (BT_VER >= LL_VER_BT_CORE_SPEC_5_0) - PalCfgLoadData(PAL_CFG_ID_BLE_PHY, &mainLlRtCfg.phy2mSup, 4); + PalCfgLoadData(PAL_CFG_ID_BLE_PHY, (uint8_t *)&mainLlRtCfg.phy2mSup, 4); #endif /* Set the 32k sleep clock accuracy into one of the following bins, default is 20 diff --git a/Examples/MAX32665/Bluetooth/BLE_mcs/main.c b/Examples/MAX32665/Bluetooth/BLE_mcs/main.c index f8efc506743..1b2b9d92787 100644 --- a/Examples/MAX32665/Bluetooth/BLE_mcs/main.c +++ b/Examples/MAX32665/Bluetooth/BLE_mcs/main.c @@ -181,7 +181,7 @@ int main(void) #endif PalCfgLoadData(PAL_CFG_ID_LL_PARAM, &mainLlRtCfg.maxAdvSets, sizeof(LlRtCfg_t) - 9); #if (BT_VER >= LL_VER_BT_CORE_SPEC_5_0) - PalCfgLoadData(PAL_CFG_ID_BLE_PHY, &mainLlRtCfg.phy2mSup, 4); + PalCfgLoadData(PAL_CFG_ID_BLE_PHY, (uint8_t *)&mainLlRtCfg.phy2mSup, 4); #endif /* Set the 32k sleep clock accuracy into one of the following bins, default is 20 diff --git a/Examples/MAX32665/Bluetooth/BLE_otac/main.c b/Examples/MAX32665/Bluetooth/BLE_otac/main.c index dfeed8d3355..6ba17c14f45 100644 --- a/Examples/MAX32665/Bluetooth/BLE_otac/main.c +++ b/Examples/MAX32665/Bluetooth/BLE_otac/main.c @@ -207,7 +207,7 @@ int main(void) #endif PalCfgLoadData(PAL_CFG_ID_LL_PARAM, &mainLlRtCfg.maxAdvSets, sizeof(LlRtCfg_t) - 9); #if (BT_VER >= LL_VER_BT_CORE_SPEC_5_0) - PalCfgLoadData(PAL_CFG_ID_BLE_PHY, &mainLlRtCfg.phy2mSup, 4); + PalCfgLoadData(PAL_CFG_ID_BLE_PHY, (uint8_t *)&mainLlRtCfg.phy2mSup, 4); #endif /* Set the 32k sleep clock accuracy into one of the following bins, default is 20 diff --git a/Examples/MAX32665/Bluetooth/BLE_otas/main.c b/Examples/MAX32665/Bluetooth/BLE_otas/main.c index 6bd44b24959..618d2c35a33 100644 --- a/Examples/MAX32665/Bluetooth/BLE_otas/main.c +++ b/Examples/MAX32665/Bluetooth/BLE_otas/main.c @@ -207,7 +207,7 @@ int main(void) #endif PalCfgLoadData(PAL_CFG_ID_LL_PARAM, &mainLlRtCfg.maxAdvSets, sizeof(LlRtCfg_t) - 9); #if (BT_VER >= LL_VER_BT_CORE_SPEC_5_0) - PalCfgLoadData(PAL_CFG_ID_BLE_PHY, &mainLlRtCfg.phy2mSup, 4); + PalCfgLoadData(PAL_CFG_ID_BLE_PHY, (uint8_t *)&mainLlRtCfg.phy2mSup, 4); #endif /* Set the 32k sleep clock accuracy into one of the following bins, default is 20 diff --git a/Examples/MAX32665/Bluetooth/RF_Test/main.c b/Examples/MAX32665/Bluetooth/RF_Test/main.c index 1a01be00a7f..4abcaee86c6 100644 --- a/Examples/MAX32665/Bluetooth/RF_Test/main.c +++ b/Examples/MAX32665/Bluetooth/RF_Test/main.c @@ -465,7 +465,7 @@ static void mainLoadConfiguration(void) PalBbLoadCfg((PalBbCfg_t *)&mainBbRtCfg); LlGetDefaultRunTimeCfg(&mainLlRtCfg); PalCfgLoadData(PAL_CFG_ID_LL_PARAM, &mainLlRtCfg.maxAdvSets, sizeof(LlRtCfg_t) - 9); - PalCfgLoadData(PAL_CFG_ID_BLE_PHY, &mainLlRtCfg.phy2mSup, 4); + PalCfgLoadData(PAL_CFG_ID_BLE_PHY, (uint8_t *)&mainLlRtCfg.phy2mSup, 4); /* Set 5.1 requirements. */ mainLlRtCfg.btVer = LL_VER_BT_CORE_SPEC_5_0; diff --git a/Examples/MAX32680/Bluetooth/BLE_dats/main.c b/Examples/MAX32680/Bluetooth/BLE_dats/main.c index bc2d8735206..226ae80574b 100644 --- a/Examples/MAX32680/Bluetooth/BLE_dats/main.c +++ b/Examples/MAX32680/Bluetooth/BLE_dats/main.c @@ -200,7 +200,7 @@ int main(void) #endif PalCfgLoadData(PAL_CFG_ID_LL_PARAM, &mainLlRtCfg.maxAdvSets, sizeof(LlRtCfg_t) - 9); #if (BT_VER >= LL_VER_BT_CORE_SPEC_5_0) - PalCfgLoadData(PAL_CFG_ID_BLE_PHY, &mainLlRtCfg.phy2mSup, 4); + PalCfgLoadData(PAL_CFG_ID_BLE_PHY, (uint8_t *)&mainLlRtCfg.phy2mSup, 4); #endif /* Set the 32k sleep clock accuracy into one of the following bins, default is 20 diff --git a/Examples/MAX32690/Bluetooth/BLE5_ctr/main.c b/Examples/MAX32690/Bluetooth/BLE5_ctr/main.c index f4b076f5f24..848d21f777c 100644 --- a/Examples/MAX32690/Bluetooth/BLE5_ctr/main.c +++ b/Examples/MAX32690/Bluetooth/BLE5_ctr/main.c @@ -76,7 +76,7 @@ static void mainLoadConfiguration(void) PalBbLoadCfg((PalBbCfg_t *)&mainBbRtCfg); LlGetDefaultRunTimeCfg(&mainLlRtCfg); PalCfgLoadData(PAL_CFG_ID_LL_PARAM, &mainLlRtCfg.maxAdvSets, sizeof(LlRtCfg_t) - 9); - PalCfgLoadData(PAL_CFG_ID_BLE_PHY, &mainLlRtCfg.phy2mSup, 4); + PalCfgLoadData(PAL_CFG_ID_BLE_PHY, (uint8_t *)&mainLlRtCfg.phy2mSup, 4); /* Set 5.0 requirements. */ mainLlRtCfg.btVer = BT_VER; diff --git a/Examples/MAX32690/Bluetooth/BLE_FreeRTOS/stack_dats.c b/Examples/MAX32690/Bluetooth/BLE_FreeRTOS/stack_dats.c index 9ff548426e2..700c2dde6c8 100644 --- a/Examples/MAX32690/Bluetooth/BLE_FreeRTOS/stack_dats.c +++ b/Examples/MAX32690/Bluetooth/BLE_FreeRTOS/stack_dats.c @@ -308,7 +308,7 @@ void bleStartup(void) #endif PalCfgLoadData(PAL_CFG_ID_LL_PARAM, &mainLlRtCfg.maxAdvSets, sizeof(LlRtCfg_t) - 9); #if (BT_VER >= LL_VER_BT_CORE_SPEC_5_0) - PalCfgLoadData(PAL_CFG_ID_BLE_PHY, &mainLlRtCfg.phy2mSup, 4); + PalCfgLoadData(PAL_CFG_ID_BLE_PHY, (uint8_t *)&mainLlRtCfg.phy2mSup, 4); #endif /* Set the 32k sleep clock accuracy into one of the following bins, default is 20 diff --git a/Examples/MAX32690/Bluetooth/BLE_datc/main.c b/Examples/MAX32690/Bluetooth/BLE_datc/main.c index 060c2a2a01e..ed1ca5eb378 100644 --- a/Examples/MAX32690/Bluetooth/BLE_datc/main.c +++ b/Examples/MAX32690/Bluetooth/BLE_datc/main.c @@ -189,7 +189,7 @@ int main(void) #endif PalCfgLoadData(PAL_CFG_ID_LL_PARAM, &mainLlRtCfg.maxAdvSets, sizeof(LlRtCfg_t) - 9); #if (BT_VER >= LL_VER_BT_CORE_SPEC_5_0) - PalCfgLoadData(PAL_CFG_ID_BLE_PHY, &mainLlRtCfg.phy2mSup, 4); + PalCfgLoadData(PAL_CFG_ID_BLE_PHY, (uint8_t *)&mainLlRtCfg.phy2mSup, 4); #endif /* Set the 32k sleep clock accuracy into one of the following bins, default is 20 diff --git a/Examples/MAX32690/Bluetooth/BLE_dats/main.c b/Examples/MAX32690/Bluetooth/BLE_dats/main.c index f9d854e8c15..f7430274b73 100644 --- a/Examples/MAX32690/Bluetooth/BLE_dats/main.c +++ b/Examples/MAX32690/Bluetooth/BLE_dats/main.c @@ -189,7 +189,7 @@ int main(void) #endif PalCfgLoadData(PAL_CFG_ID_LL_PARAM, &mainLlRtCfg.maxAdvSets, sizeof(LlRtCfg_t) - 9); #if (BT_VER >= LL_VER_BT_CORE_SPEC_5_0) - PalCfgLoadData(PAL_CFG_ID_BLE_PHY, &mainLlRtCfg.phy2mSup, 4); + PalCfgLoadData(PAL_CFG_ID_BLE_PHY, (uint8_t *)&mainLlRtCfg.phy2mSup, 4); #endif /* Set the 32k sleep clock accuracy into one of the following bins, default is 20 diff --git a/Examples/MAX32690/Bluetooth/BLE_fit/main.c b/Examples/MAX32690/Bluetooth/BLE_fit/main.c index 80196c3a170..f43129c09bc 100644 --- a/Examples/MAX32690/Bluetooth/BLE_fit/main.c +++ b/Examples/MAX32690/Bluetooth/BLE_fit/main.c @@ -189,7 +189,7 @@ int main(void) #endif PalCfgLoadData(PAL_CFG_ID_LL_PARAM, &mainLlRtCfg.maxAdvSets, sizeof(LlRtCfg_t) - 9); #if (BT_VER >= LL_VER_BT_CORE_SPEC_5_0) - PalCfgLoadData(PAL_CFG_ID_BLE_PHY, &mainLlRtCfg.phy2mSup, 4); + PalCfgLoadData(PAL_CFG_ID_BLE_PHY, (uint8_t *)&mainLlRtCfg.phy2mSup, 4); #endif /* Set the 32k sleep clock accuracy into one of the following bins, default is 20 diff --git a/Examples/MAX32690/Bluetooth/BLE_mcs/main.c b/Examples/MAX32690/Bluetooth/BLE_mcs/main.c index a53eb4a80ca..507205876e8 100644 --- a/Examples/MAX32690/Bluetooth/BLE_mcs/main.c +++ b/Examples/MAX32690/Bluetooth/BLE_mcs/main.c @@ -163,7 +163,7 @@ int main(void) #endif PalCfgLoadData(PAL_CFG_ID_LL_PARAM, &mainLlRtCfg.maxAdvSets, sizeof(LlRtCfg_t) - 9); #if (BT_VER >= LL_VER_BT_CORE_SPEC_5_0) - PalCfgLoadData(PAL_CFG_ID_BLE_PHY, &mainLlRtCfg.phy2mSup, 4); + PalCfgLoadData(PAL_CFG_ID_BLE_PHY, (uint8_t *)&mainLlRtCfg.phy2mSup, 4); #endif /* Set the 32k sleep clock accuracy into one of the following bins, default is 20 diff --git a/Examples/MAX32690/Bluetooth/BLE_otac/main.c b/Examples/MAX32690/Bluetooth/BLE_otac/main.c index 13feaae0cf5..cfc16e2cbfe 100644 --- a/Examples/MAX32690/Bluetooth/BLE_otac/main.c +++ b/Examples/MAX32690/Bluetooth/BLE_otac/main.c @@ -190,7 +190,7 @@ int main(void) #endif PalCfgLoadData(PAL_CFG_ID_LL_PARAM, &mainLlRtCfg.maxAdvSets, sizeof(LlRtCfg_t) - 9); #if (BT_VER >= LL_VER_BT_CORE_SPEC_5_0) - PalCfgLoadData(PAL_CFG_ID_BLE_PHY, &mainLlRtCfg.phy2mSup, 4); + PalCfgLoadData(PAL_CFG_ID_BLE_PHY, (uint8_t *)&mainLlRtCfg.phy2mSup, 4); #endif /* Set the 32k sleep clock accuracy into one of the following bins, default is 20 diff --git a/Examples/MAX32690/Bluetooth/BLE_otas/main.c b/Examples/MAX32690/Bluetooth/BLE_otas/main.c index e329d43fcda..0a9e752ec2a 100644 --- a/Examples/MAX32690/Bluetooth/BLE_otas/main.c +++ b/Examples/MAX32690/Bluetooth/BLE_otas/main.c @@ -190,7 +190,7 @@ int main(void) #endif PalCfgLoadData(PAL_CFG_ID_LL_PARAM, &mainLlRtCfg.maxAdvSets, sizeof(LlRtCfg_t) - 9); #if (BT_VER >= LL_VER_BT_CORE_SPEC_5_0) - PalCfgLoadData(PAL_CFG_ID_BLE_PHY, &mainLlRtCfg.phy2mSup, 4); + PalCfgLoadData(PAL_CFG_ID_BLE_PHY, (uint8_t *)&mainLlRtCfg.phy2mSup, 4); #endif /* Set the 32k sleep clock accuracy into one of the following bins, default is 20 diff --git a/Examples/MAX32690/Bluetooth/RF_Test/main.c b/Examples/MAX32690/Bluetooth/RF_Test/main.c index 1a01be00a7f..4abcaee86c6 100644 --- a/Examples/MAX32690/Bluetooth/RF_Test/main.c +++ b/Examples/MAX32690/Bluetooth/RF_Test/main.c @@ -465,7 +465,7 @@ static void mainLoadConfiguration(void) PalBbLoadCfg((PalBbCfg_t *)&mainBbRtCfg); LlGetDefaultRunTimeCfg(&mainLlRtCfg); PalCfgLoadData(PAL_CFG_ID_LL_PARAM, &mainLlRtCfg.maxAdvSets, sizeof(LlRtCfg_t) - 9); - PalCfgLoadData(PAL_CFG_ID_BLE_PHY, &mainLlRtCfg.phy2mSup, 4); + PalCfgLoadData(PAL_CFG_ID_BLE_PHY, (uint8_t *)&mainLlRtCfg.phy2mSup, 4); /* Set 5.1 requirements. */ mainLlRtCfg.btVer = LL_VER_BT_CORE_SPEC_5_0; diff --git a/Libraries/Cordio/ble-profiles/sources/af/common/app_db.c b/Libraries/Cordio/ble-profiles/sources/af/common/app_db.c index d954e1bcebe..9b8322223a4 100644 --- a/Libraries/Cordio/ble-profiles/sources/af/common/app_db.c +++ b/Libraries/Cordio/ble-profiles/sources/af/common/app_db.c @@ -962,7 +962,7 @@ bool_t AppDbNvmStorePeerRpao(appDbHdl_t hdl) appDbRec_t *pRec = &appDb.rec[recIndex]; uint32_t nvmId = DBNV_ID(APP_DB_NVM_PEER_RAPO_ID, recIndex); - return WsfNvmWriteData(nvmId, &pRec->peerRpao, sizeof(bool_t), NULL); + return WsfNvmWriteData(nvmId, (uint8_t*) &pRec->peerRpao, sizeof(bool_t), NULL); }else { APP_TRACE_INFO0("Invalid record index!"); @@ -1021,7 +1021,7 @@ bool_t AppDbNvmStoreHdlList(appDbHdl_t hdl) nvmId = DBNV_ID(APP_DB_NVM_DISC_STATUS_ID, recIndex); - return WsfNvmWriteData(nvmId, &pRec->discStatus, sizeof(uint8_t), NULL); + return WsfNvmWriteData(nvmId, (uint8_t*) &pRec->discStatus, sizeof(uint8_t), NULL); }else { APP_TRACE_INFO0("Invalid record index!"); @@ -1181,7 +1181,7 @@ bool_t AppDbNvmStoreDbHash(appDbHdl_t hdl) appDbRec_t *pRec = &appDb.rec[recIndex]; uint32_t nvmId = DBNV_ID(APP_DB_NVM_HASH_ID, recIndex); - return WsfNvmWriteData(nvmId, pRec->dbHash, ATT_DATABASE_HASH_LEN, NULL); + return WsfNvmWriteData(nvmId, (uint8_t*) pRec->dbHash, ATT_DATABASE_HASH_LEN, NULL); } else { @@ -1213,7 +1213,7 @@ bool_t AppDbNvmStoreBond(appDbHdl_t hdl) /* Protect against corrupt bond state due to incomplete writes (power failure, crash, etc.). */ /* - First ensure valid FALSE before writing parameters. */ - bool_t writeOk = WsfNvmWriteData(DBNV_ID(APP_DB_NVM_VALID_ID, i), &valid, sizeof(bool_t), NULL); + bool_t writeOk = WsfNvmWriteData(DBNV_ID(APP_DB_NVM_VALID_ID, i), (uint8_t*) &valid, sizeof(bool_t), NULL); if(!writeOk){ return FALSE; @@ -1221,7 +1221,7 @@ bool_t AppDbNvmStoreBond(appDbHdl_t hdl) /* Write record parameters. */ - writeOk = WsfNvmWriteData(DBNV_ID(APP_DB_NVM_KV_MASK_ID, i), &pRec->keyValidMask, sizeof(uint8_t), NULL); + writeOk = WsfNvmWriteData(DBNV_ID(APP_DB_NVM_KV_MASK_ID, i), (uint8_t*) &pRec->keyValidMask, sizeof(uint8_t), NULL); if(!writeOk){ return FALSE; } @@ -1232,7 +1232,7 @@ bool_t AppDbNvmStoreBond(appDbHdl_t hdl) if(!writeOk){ return FALSE; } - writeOk = WsfNvmWriteData(DBNV_ID(APP_DB_NVM_LOCAL_SEC_LVL_ID, i), &pRec->localLtkSecLevel, sizeof(uint8_t), NULL); + writeOk = WsfNvmWriteData(DBNV_ID(APP_DB_NVM_LOCAL_SEC_LVL_ID, i), (uint8_t*) &pRec->localLtkSecLevel, sizeof(uint8_t), NULL); if(!writeOk){ return FALSE; } @@ -1244,7 +1244,7 @@ bool_t AppDbNvmStoreBond(appDbHdl_t hdl) if(!writeOk){ return FALSE; } - writeOk = WsfNvmWriteData(DBNV_ID(APP_DB_NVM_PEER_SEC_LVL_ID, i), &pRec->peerLtkSecLevel, sizeof(uint8_t), NULL); + writeOk = WsfNvmWriteData(DBNV_ID(APP_DB_NVM_PEER_SEC_LVL_ID, i), (uint8_t*) &pRec->peerLtkSecLevel, sizeof(uint8_t), NULL); if(!writeOk){ return FALSE; } @@ -1266,21 +1266,21 @@ bool_t AppDbNvmStoreBond(appDbHdl_t hdl) } } - writeOk = WsfNvmWriteData(DBNV_ID(APP_DB_NVM_PEER_ADDR_ID, i), pRec->peerAddr, sizeof(bdAddr_t), NULL); + writeOk = WsfNvmWriteData(DBNV_ID(APP_DB_NVM_PEER_ADDR_ID, i), (uint8_t*) pRec->peerAddr, sizeof(bdAddr_t), NULL); if(!writeOk){ return FALSE; } - writeOk = WsfNvmWriteData(DBNV_ID(APP_DB_NVM_ADDR_TYPE_ID, i), &pRec->addrType, sizeof(uint8_t), NULL); + writeOk = WsfNvmWriteData(DBNV_ID(APP_DB_NVM_ADDR_TYPE_ID, i), (uint8_t*) &pRec->addrType, sizeof(uint8_t), NULL); if(!writeOk){ return FALSE; } - writeOk = WsfNvmWriteData(DBNV_ID(APP_DB_NVM_CACHE_HASH_ID, i), &pRec->cacheByHash, sizeof(bool_t), NULL); + writeOk = WsfNvmWriteData(DBNV_ID(APP_DB_NVM_CACHE_HASH_ID, i), (uint8_t*) &pRec->cacheByHash, sizeof(bool_t), NULL); if(!writeOk){ return FALSE; } /* Protect against corrupt bond state due to incomplete writes (power failure, crash, etc.). */ /* - Second set valid TRUE after writing parameters. */ - return WsfNvmWriteData(DBNV_ID(APP_DB_NVM_VALID_ID, i), &pRec->valid, sizeof(bool_t), NULL); + return WsfNvmWriteData(DBNV_ID(APP_DB_NVM_VALID_ID, i), (uint8_t*) &pRec->valid, sizeof(bool_t), NULL); } return TRUE; @@ -1306,11 +1306,11 @@ void AppDbNvmReadAll(void) /* Read all records. */ for (i = 0; i < APP_DB_NUM_RECS; i++) { - bool_t valid = FALSE; + uint8_t valid = 0; appDbRec_t *pRec = &appDb.rec[i]; /* Verify record is valid. */ - WsfNvmReadData(DBNV_ID(APP_DB_NVM_VALID_ID, i), &valid, sizeof(bool_t), NULL); + WsfNvmReadData(DBNV_ID(APP_DB_NVM_VALID_ID, i), (uint8_t*) &valid, sizeof(bool_t), NULL); if (valid && valid != 0xFF) { @@ -1318,21 +1318,21 @@ void AppDbNvmReadAll(void) pRec->valid = TRUE; /* Read bonding parameters. */ - WsfNvmReadData(DBNV_ID(APP_DB_NVM_PEER_ADDR_ID, i), pRec->peerAddr, sizeof(bdAddr_t), NULL); - WsfNvmReadData(DBNV_ID(APP_DB_NVM_ADDR_TYPE_ID, i), &pRec->addrType, sizeof(uint8_t), NULL); + WsfNvmReadData(DBNV_ID(APP_DB_NVM_PEER_ADDR_ID, i), (uint8_t*) pRec->peerAddr, sizeof(bdAddr_t), NULL); + WsfNvmReadData(DBNV_ID(APP_DB_NVM_ADDR_TYPE_ID, i), (uint8_t*) &pRec->addrType, sizeof(uint8_t), NULL); - WsfNvmReadData(DBNV_ID(APP_DB_NVM_KV_MASK_ID, i), &pRec->keyValidMask, sizeof(uint8_t), NULL); + WsfNvmReadData(DBNV_ID(APP_DB_NVM_KV_MASK_ID, i), (uint8_t*) &pRec->keyValidMask, sizeof(uint8_t), NULL); if (pRec->keyValidMask & DM_KEY_LOCAL_LTK) { WsfNvmReadData(DBNV_ID(APP_DB_NVM_LOCAL_LTK_ID, i), (uint8_t*) &pRec->localLtk, sizeof(dmSecLtk_t), NULL); - WsfNvmReadData(DBNV_ID(APP_DB_NVM_LOCAL_SEC_LVL_ID, i), &pRec->localLtkSecLevel, sizeof(uint8_t), NULL); + WsfNvmReadData(DBNV_ID(APP_DB_NVM_LOCAL_SEC_LVL_ID, i), (uint8_t*) &pRec->localLtkSecLevel, sizeof(uint8_t), NULL); } if (pRec->keyValidMask & DM_KEY_PEER_LTK) { WsfNvmReadData(DBNV_ID(APP_DB_NVM_PEER_LTK_ID, i), (uint8_t*) &pRec->peerLtk, sizeof(dmSecLtk_t), NULL); - WsfNvmReadData(DBNV_ID(APP_DB_NVM_PEER_SEC_LVL_ID, i), &pRec->peerLtkSecLevel, sizeof(uint8_t), NULL); + WsfNvmReadData(DBNV_ID(APP_DB_NVM_PEER_SEC_LVL_ID, i), (uint8_t*) &pRec->peerLtkSecLevel, sizeof(uint8_t), NULL); } if (pRec->keyValidMask & DM_KEY_IRK) @@ -1346,17 +1346,17 @@ void AppDbNvmReadAll(void) } /* Read additional parameters. */ - WsfNvmReadData(DBNV_ID(APP_DB_NVM_PEER_RAPO_ID, i), &pRec->peerRpao, sizeof(bool_t), NULL); + WsfNvmReadData(DBNV_ID(APP_DB_NVM_PEER_RAPO_ID, i), (uint8_t*) &pRec->peerRpao, sizeof(bool_t), NULL); WsfNvmReadData(DBNV_ID(APP_DB_NVM_CCC_TBL_ID, i), (uint8_t*) pRec->cccTbl, sizeof(uint16_t) * APP_DB_NUM_CCCD, NULL); WsfNvmReadData(DBNV_ID(APP_DB_NVM_HDL_LIST_ID, i), (uint8_t*) &pRec->hdlList, sizeof(uint16_t) * APP_DB_HDL_LIST_LEN, NULL); - WsfNvmReadData(DBNV_ID(APP_DB_NVM_DISC_STATUS_ID, i), &pRec->discStatus, sizeof(uint8_t), NULL); - WsfNvmReadData(DBNV_ID(APP_DB_NVM_PEER_ADDR_RES_ID, i), &pRec->peerAddrRes, sizeof(bool_t), NULL); + WsfNvmReadData(DBNV_ID(APP_DB_NVM_DISC_STATUS_ID, i), (uint8_t*) &pRec->discStatus, sizeof(uint8_t), NULL); + WsfNvmReadData(DBNV_ID(APP_DB_NVM_PEER_ADDR_RES_ID, i), (uint8_t*) &pRec->peerAddrRes, sizeof(bool_t), NULL); - WsfNvmReadData(DBNV_ID(APP_DB_NVM_CAS_ID, i), &pRec->changeAwareState, sizeof(uint8_t), NULL); - WsfNvmReadData(DBNV_ID(APP_DB_NVM_CSF_ID, i), pRec->csf, ATT_CSF_LEN, NULL); - WsfNvmReadData(DBNV_ID(APP_DB_NVM_CACHE_HASH_ID, i), &pRec->cacheByHash, sizeof(bool_t), NULL); - WsfNvmReadData(DBNV_ID(APP_DB_NVM_HASH_ID, i), pRec->dbHash, ATT_DATABASE_HASH_LEN, NULL); + WsfNvmReadData(DBNV_ID(APP_DB_NVM_CAS_ID, i), (uint8_t*) &pRec->changeAwareState, sizeof(uint8_t), NULL); + WsfNvmReadData(DBNV_ID(APP_DB_NVM_CSF_ID, i), (uint8_t*) pRec->csf, ATT_CSF_LEN, NULL); + WsfNvmReadData(DBNV_ID(APP_DB_NVM_CACHE_HASH_ID, i), (uint8_t*) &pRec->cacheByHash, sizeof(bool_t), NULL); + WsfNvmReadData(DBNV_ID(APP_DB_NVM_HASH_ID, i), (uint8_t*) pRec->dbHash, ATT_DATABASE_HASH_LEN, NULL); } } } diff --git a/Libraries/Cordio/controller/sources/ble/lhci/lhci_cmd_vs.c b/Libraries/Cordio/controller/sources/ble/lhci/lhci_cmd_vs.c index 8c4d4027b75..6e036362529 100644 --- a/Libraries/Cordio/controller/sources/ble/lhci/lhci_cmd_vs.c +++ b/Libraries/Cordio/controller/sources/ble/lhci/lhci_cmd_vs.c @@ -94,7 +94,6 @@ bool_t lhciCommonVsStdDecodeCmdPkt(LhciHdr_t *pHdr, uint8_t *pBuf) { uint8_t status = HCI_SUCCESS; uint8_t evtParamLen = 1; /* default is status field only */ - uint32_t regReadAddr = 0; uint32_t channel = 0; (void)channel; diff --git a/Libraries/Cordio/platform/include/pal_types.h b/Libraries/Cordio/platform/include/pal_types.h index 7b876eaeb46..eaef2967a9e 100644 --- a/Libraries/Cordio/platform/include/pal_types.h +++ b/Libraries/Cordio/platform/include/pal_types.h @@ -42,17 +42,18 @@ extern "C" { #include #include +#include #ifndef bool_t - #define bool_t uint8_t +#define bool_t bool #endif #ifndef FALSE - #define FALSE 0 +#define FALSE false #endif #ifndef TRUE - #define TRUE (!FALSE) +#define TRUE true #endif /*! \} */ /* Integer Data Types */ diff --git a/Libraries/Cordio/wsf/include/wsf_types.h b/Libraries/Cordio/wsf/include/wsf_types.h index 73a5ead76c8..abc363fb4c7 100644 --- a/Libraries/Cordio/wsf/include/wsf_types.h +++ b/Libraries/Cordio/wsf/include/wsf_types.h @@ -42,21 +42,8 @@ extern "C" { #include #include - -#ifndef bool_t - #define bool_t uint8_t -#endif - -/* New library uses bool instead of bool_t */ -#define bool _Bool - -#ifndef FALSE - #define FALSE 0 -#endif - -#ifndef TRUE - #define TRUE (!FALSE) -#endif +#include +#include "pal_types.h" /*! \} */ /* Integer Data Types */ From b0219d334e8b8ab3250885a7438975513cafa94d Mon Sep 17 00:00:00 2001 From: Kevin Gillespie Date: Tue, 15 Oct 2024 10:21:52 -0500 Subject: [PATCH 06/37] feat(CMSIS): Adding mallinfo function and reworking Cordio memory management. (#1179) Co-authored-by: crsz20 Co-authored-by: crsz20 --- .github/workflows/clang-format-run-pr.yml | 3 + Examples/MAX32655/Bluetooth/BLE4_ctr/main.c | 72 +- Examples/MAX32655/Bluetooth/BLE5_ctr/main.c | 72 +- .../Bluetooth/BLE_FreeRTOS/stack_dats.c | 55 +- .../MAX32655/Bluetooth/BLE_HCI_DFU/BLT/main.c | 78 +- Examples/MAX32655/Bluetooth/BLE_datc/main.c | 57 +- Examples/MAX32655/Bluetooth/BLE_dats/main.c | 56 +- Examples/MAX32655/Bluetooth/BLE_fit/main.c | 57 +- .../Bluetooth/BLE_fit_FreeRTOS/bt_stack.c | 54 +- Examples/MAX32655/Bluetooth/BLE_mcs/main.c | 57 +- Examples/MAX32655/Bluetooth/BLE_otac/main.c | 57 +- Examples/MAX32655/Bluetooth/BLE_otas/main.c | 57 +- Examples/MAX32655/Bluetooth/BLE_periph/main.c | 57 +- Examples/MAX32655/Bluetooth/RF_Test/main.c | 53 +- Examples/MAX32655/Bluetooth/RF_Test/main.h | 1 + Examples/MAX32665/Bluetooth/BLE4_ctr/main.c | 72 +- Examples/MAX32665/Bluetooth/BLE5_ctr/main.c | 72 +- .../Bluetooth/BLE_FreeRTOS/stack_dats.c | 55 +- Examples/MAX32665/Bluetooth/BLE_datc/main.c | 57 +- Examples/MAX32665/Bluetooth/BLE_dats/main.c | 56 +- Examples/MAX32665/Bluetooth/BLE_fit/main.c | 59 +- Examples/MAX32665/Bluetooth/BLE_mcs/main.c | 57 +- Examples/MAX32665/Bluetooth/BLE_otac/main.c | 57 +- Examples/MAX32665/Bluetooth/BLE_otas/main.c | 68 +- Examples/MAX32665/Bluetooth/BLE_periph/main.c | 57 +- Examples/MAX32665/Bluetooth/RF_Test/main.c | 59 +- Examples/MAX32665/Bluetooth/RF_Test/main.h | 1 + Examples/MAX32690/Bluetooth/BLE4_ctr/main.c | 72 +- Examples/MAX32690/Bluetooth/BLE5_ctr/main.c | 72 +- .../Bluetooth/BLE_FreeRTOS/stack_dats.c | 55 +- Examples/MAX32690/Bluetooth/BLE_datc/main.c | 57 +- Examples/MAX32690/Bluetooth/BLE_dats/main.c | 56 +- Examples/MAX32690/Bluetooth/BLE_fit/main.c | 57 +- Examples/MAX32690/Bluetooth/BLE_mcs/main.c | 57 +- Examples/MAX32690/Bluetooth/BLE_otac/main.c | 57 +- Examples/MAX32690/Bluetooth/BLE_otas/main.c | 68 +- Examples/MAX32690/Bluetooth/BLE_periph/main.c | 57 +- Examples/MAX32690/Bluetooth/RF_Test/main.c | 58 +- Examples/MAX32690/Bluetooth/RF_Test/main.h | 1 + .../DSP/1.16.2/Include/arm_common_tables.h | 332 ++- .../1.16.2/Include/arm_common_tables_f16.h | 61 +- .../DSP/1.16.2/Include/arm_const_structs.h | 80 +- .../1.16.2/Include/arm_const_structs_f16.h | 25 +- .../DSP/1.16.2/Include/arm_helium_utils.h | 356 ++- .../CMSIS/5.9.0/DSP/1.16.2/Include/arm_math.h | 21 +- .../5.9.0/DSP/1.16.2/Include/arm_math_f16.h | 9 +- .../DSP/1.16.2/Include/arm_math_memory.h | 123 +- .../5.9.0/DSP/1.16.2/Include/arm_math_types.h | 640 +++-- .../DSP/1.16.2/Include/arm_math_types_f16.h | 95 +- .../5.9.0/DSP/1.16.2/Include/arm_mve_tables.h | 47 +- .../DSP/1.16.2/Include/arm_mve_tables_f16.h | 25 +- .../5.9.0/DSP/1.16.2/Include/arm_vec_math.h | 147 +- .../DSP/1.16.2/Include/arm_vec_math_f16.h | 124 +- .../1.16.2/Include/dsp/basic_math_functions.h | 525 +--- .../Include/dsp/basic_math_functions_f16.h | 85 +- .../DSP/1.16.2/Include/dsp/bayes_functions.h | 31 +- .../1.16.2/Include/dsp/bayes_functions_f16.h | 30 +- .../Include/dsp/complex_math_functions.h | 200 +- .../Include/dsp/complex_math_functions_f16.h | 57 +- .../1.16.2/Include/dsp/controller_functions.h | 385 ++- .../Include/dsp/controller_functions_f16.h | 8 +- .../5.9.0/DSP/1.16.2/Include/dsp/debug.h | 185 +- .../1.16.2/Include/dsp/distance_functions.h | 73 +- .../Include/dsp/distance_functions_f16.h | 40 +- .../1.16.2/Include/dsp/fast_math_functions.h | 221 +- .../Include/dsp/fast_math_functions_f16.h | 48 +- .../1.16.2/Include/dsp/filtering_functions.h | 2119 ++++++----------- .../Include/dsp/filtering_functions_f16.h | 190 +- .../Include/dsp/interpolation_functions.h | 187 +- .../Include/dsp/interpolation_functions_f16.h | 47 +- .../DSP/1.16.2/Include/dsp/matrix_functions.h | 496 ++-- .../1.16.2/Include/dsp/matrix_functions_f16.h | 150 +- .../DSP/1.16.2/Include/dsp/matrix_utils.h | 1095 ++++----- .../CMSIS/5.9.0/DSP/1.16.2/Include/dsp/none.h | 577 ++--- .../Include/dsp/quaternion_math_functions.h | 58 +- .../1.16.2/Include/dsp/statistics_functions.h | 540 ++--- .../Include/dsp/statistics_functions_f16.h | 129 +- .../1.16.2/Include/dsp/support_functions.h | 341 +-- .../Include/dsp/support_functions_f16.h | 64 +- .../DSP/1.16.2/Include/dsp/svm_defines.h | 12 +- .../DSP/1.16.2/Include/dsp/svm_functions.h | 176 +- .../1.16.2/Include/dsp/svm_functions_f16.h | 169 +- .../1.16.2/Include/dsp/transform_functions.h | 1543 +++++------- .../Include/dsp/transform_functions_f16.h | 388 ++- .../5.9.0/DSP/1.16.2/Include/dsp/utils.h | 145 +- .../DSP/1.16.2/Include/dsp/window_functions.h | 250 +- .../CMSIS/Device/Maxim/MAX32655/Source/heap.c | 77 + .../CMSIS/Device/Maxim/MAX32665/Source/heap.c | 77 + .../CMSIS/Device/Maxim/MAX32690/Source/heap.c | 77 + .../controller/include/ble/ll_init_api.h | 2 + .../Cordio/controller/sources/ble/init/init.c | 31 +- .../controller/sources/ble/ll/ll_init.c | 1 - .../controller/sources/common/bb/bb_main.c | 1 - .../wsf/sources/targets/baremetal/wsf_heap.c | 57 +- 94 files changed, 6621 insertions(+), 8474 deletions(-) mode change 100755 => 100644 Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/arm_common_tables_f16.h mode change 100755 => 100644 Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/arm_const_structs_f16.h mode change 100755 => 100644 Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/arm_helium_utils.h mode change 100755 => 100644 Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/arm_math_f16.h mode change 100755 => 100644 Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/arm_math_memory.h mode change 100755 => 100644 Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/arm_math_types.h mode change 100755 => 100644 Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/arm_math_types_f16.h mode change 100755 => 100644 Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/arm_mve_tables.h mode change 100755 => 100644 Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/arm_mve_tables_f16.h mode change 100755 => 100644 Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/arm_vec_math.h mode change 100755 => 100644 Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/arm_vec_math_f16.h mode change 100755 => 100644 Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/basic_math_functions.h mode change 100755 => 100644 Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/basic_math_functions_f16.h mode change 100755 => 100644 Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/bayes_functions.h mode change 100755 => 100644 Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/bayes_functions_f16.h mode change 100755 => 100644 Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/complex_math_functions.h mode change 100755 => 100644 Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/complex_math_functions_f16.h mode change 100755 => 100644 Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/controller_functions.h mode change 100755 => 100644 Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/controller_functions_f16.h mode change 100755 => 100644 Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/distance_functions.h mode change 100755 => 100644 Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/distance_functions_f16.h mode change 100755 => 100644 Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/fast_math_functions.h mode change 100755 => 100644 Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/fast_math_functions_f16.h mode change 100755 => 100644 Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/filtering_functions.h mode change 100755 => 100644 Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/filtering_functions_f16.h mode change 100755 => 100644 Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/interpolation_functions.h mode change 100755 => 100644 Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/interpolation_functions_f16.h mode change 100755 => 100644 Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/matrix_functions.h mode change 100755 => 100644 Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/matrix_functions_f16.h mode change 100755 => 100644 Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/matrix_utils.h mode change 100755 => 100644 Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/none.h mode change 100755 => 100644 Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/quaternion_math_functions.h mode change 100755 => 100644 Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/statistics_functions.h mode change 100755 => 100644 Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/statistics_functions_f16.h mode change 100755 => 100644 Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/support_functions.h mode change 100755 => 100644 Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/support_functions_f16.h mode change 100755 => 100644 Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/svm_defines.h mode change 100755 => 100644 Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/svm_functions.h mode change 100755 => 100644 Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/svm_functions_f16.h mode change 100755 => 100644 Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/transform_functions.h mode change 100755 => 100644 Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/transform_functions_f16.h mode change 100755 => 100644 Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/utils.h diff --git a/.github/workflows/clang-format-run-pr.yml b/.github/workflows/clang-format-run-pr.yml index 4fd90a8b953..a11fd261615 100644 --- a/.github/workflows/clang-format-run-pr.yml +++ b/.github/workflows/clang-format-run-pr.yml @@ -25,6 +25,9 @@ on: issue_comment: types: [created] +permissions: + actions: write + env: CLANG_VERSION: 14 diff --git a/Examples/MAX32655/Bluetooth/BLE4_ctr/main.c b/Examples/MAX32655/Bluetooth/BLE4_ctr/main.c index d477d982d98..fc810e0a92a 100644 --- a/Examples/MAX32655/Bluetooth/BLE4_ctr/main.c +++ b/Examples/MAX32655/Bluetooth/BLE4_ctr/main.c @@ -95,6 +95,10 @@ static void mainLoadConfiguration(void) /*************************************************************************************************/ static void mainWsfInit(void) { + uint32_t llmemUsed, memUsed; + + mainLoadConfiguration(); + /* +12 for message headroom, +4 for header. */ const uint16_t aclBufSize = 12 + mainLlRtCfg.maxAclLen + 4 + BB_DATA_PDU_TAILROOM; @@ -105,24 +109,61 @@ static void mainWsfInit(void) const uint8_t numPools = sizeof(poolDesc) / sizeof(poolDesc[0]); + /* Calculate how much memory we will need for the LL initialization */ + WsfCsEnter(); + + LlInitRtCfg_t llCfg = { + .pBbRtCfg = &mainBbRtCfg, + .wlSizeCfg = 4, + .rlSizeCfg = 4, + .plSizeCfg = 4, + .pLlRtCfg = &mainLlRtCfg, + /* Not significant yet, only being used for memory size requirement calculation. */ + .pFreeMem = WsfHeapGetFreeStartAddress(), + /* Not significant yet, only being used for memory size requirement calculation. */ + .freeMemAvail = WsfHeapCountAvailable() + }; + + llmemUsed = LlInitSetRtCfg(&llCfg); + + WsfCsExit(); + /* Initial buffer configuration. */ - uint16_t memUsed; WsfCsEnter(); - memUsed = WsfBufInit(numPools, poolDesc); + memUsed = WsfBufCalcSize(numPools, poolDesc); WsfHeapAlloc(memUsed); + WsfBufInit(numPools, poolDesc); WsfCsExit(); WsfOsInit(); WsfTimerInit(); + #if (WSF_TRACE_ENABLED == TRUE) WsfCsEnter(); - memUsed = WsfBufIoUartInit(WsfHeapGetFreeStartAddress(), PLATFORM_UART_TERMINAL_BUFFER_SIZE); - WsfHeapAlloc(memUsed); + WsfHeapAlloc(PLATFORM_UART_TERMINAL_BUFFER_SIZE); + WsfBufIoUartInit(WsfHeapGetFreeStartAddress(), PLATFORM_UART_TERMINAL_BUFFER_SIZE); WsfCsExit(); WsfTraceRegisterHandler(WsfBufIoWrite); WsfTraceEnable(TRUE); #endif + + /* Complete the LL initialization */ + WsfCsEnter(); + + /* Allocate the memory */ + WsfHeapAlloc(llmemUsed); + + /* Set the free memory pointers */ + llCfg.pFreeMem = WsfHeapGetFreeStartAddress(); + llCfg.freeMemAvail = WsfHeapCountAvailable(); + + /* Run the initialization with properly set the free memory pointers */ + if (llmemUsed != LlInitControllerInit(&llCfg)) { + WSF_ASSERT(0); + } + + WsfCsExit(); } /*************************************************************************************************/ @@ -164,31 +205,8 @@ static bool mainCheckServiceTokens(void) /*************************************************************************************************/ int main(void) { - uint32_t memUsed; - - mainLoadConfiguration(); mainWsfInit(); -#if (WSF_TRACE_ENABLED == TRUE) - WsfCsEnter(); - memUsed = WsfBufIoUartInit(WsfHeapGetFreeStartAddress(), PLATFORM_UART_TERMINAL_BUFFER_SIZE); - WsfHeapAlloc(memUsed); - WsfCsExit(); -#endif - - WsfCsEnter(); - LlInitRtCfg_t llCfg = { .pBbRtCfg = &mainBbRtCfg, - .wlSizeCfg = 4, - .rlSizeCfg = 4, - .plSizeCfg = 4, - .pLlRtCfg = &mainLlRtCfg, - .pFreeMem = WsfHeapGetFreeStartAddress(), - .freeMemAvail = WsfHeapCountAvailable() }; - - memUsed = LlInitControllerInit(&llCfg); - WsfHeapAlloc(memUsed); - WsfCsExit(); - bdAddr_t bdAddr; PalCfgLoadData(PAL_CFG_ID_BD_ADDR, bdAddr, sizeof(bdAddr_t)); /* Coverity[uninit_use_in_call] */ diff --git a/Examples/MAX32655/Bluetooth/BLE5_ctr/main.c b/Examples/MAX32655/Bluetooth/BLE5_ctr/main.c index 864348ee44a..81531901b4c 100644 --- a/Examples/MAX32655/Bluetooth/BLE5_ctr/main.c +++ b/Examples/MAX32655/Bluetooth/BLE5_ctr/main.c @@ -111,6 +111,10 @@ static void mainLoadConfiguration(void) /*************************************************************************************************/ static void mainWsfInit(void) { + uint32_t llmemUsed, memUsed; + + mainLoadConfiguration(); + /* +12 for message headroom, + 2 event header, +255 maximum parameter length. */ const uint16_t maxRptBufSize = 12 + 2 + 255; @@ -137,24 +141,61 @@ static void mainWsfInit(void) const uint8_t numPools = sizeof(poolDesc) / sizeof(poolDesc[0]); + /* Calculate how much memory we will need for the LL initialization */ + WsfCsEnter(); + + LlInitRtCfg_t llCfg = { + .pBbRtCfg = &mainBbRtCfg, + .wlSizeCfg = 4, + .rlSizeCfg = 4, + .plSizeCfg = 4, + .pLlRtCfg = &mainLlRtCfg, + /* Not significant yet, only being used for memory size requirement calculation. */ + .pFreeMem = WsfHeapGetFreeStartAddress(), + /* Not significant yet, only being used for memory size requirement calculation. */ + .freeMemAvail = WsfHeapCountAvailable() + }; + + llmemUsed = LlInitSetRtCfg(&llCfg); + + WsfCsExit(); + /* Initial buffer configuration. */ - uint16_t memUsed; WsfCsEnter(); - memUsed = WsfBufInit(numPools, poolDesc); + memUsed = WsfBufCalcSize(numPools, poolDesc); WsfHeapAlloc(memUsed); + WsfBufInit(numPools, poolDesc); WsfCsExit(); WsfOsInit(); WsfTimerInit(); + #if (WSF_TRACE_ENABLED == TRUE) WsfCsEnter(); - memUsed = WsfBufIoUartInit(WsfHeapGetFreeStartAddress(), PLATFORM_UART_TERMINAL_BUFFER_SIZE); - WsfHeapAlloc(memUsed); + WsfHeapAlloc(PLATFORM_UART_TERMINAL_BUFFER_SIZE); + WsfBufIoUartInit(WsfHeapGetFreeStartAddress(), PLATFORM_UART_TERMINAL_BUFFER_SIZE); WsfCsExit(); WsfTraceRegisterHandler(WsfBufIoWrite); WsfTraceEnable(TRUE); #endif + + /* Complete the LL initialization */ + WsfCsEnter(); + + /* Allocate the memory */ + WsfHeapAlloc(llmemUsed); + + /* Set the free memory pointers */ + llCfg.pFreeMem = WsfHeapGetFreeStartAddress(); + llCfg.freeMemAvail = WsfHeapCountAvailable(); + + /* Run the initialization with properly set the free memory pointers */ + if (llmemUsed != LlInitControllerInit(&llCfg)) { + WSF_ASSERT(0); + } + + WsfCsExit(); } /*************************************************************************************************/ @@ -249,31 +290,8 @@ void setInterruptPriority(void) /*************************************************************************************************/ int main(void) { - uint32_t memUsed; - - mainLoadConfiguration(); mainWsfInit(); -#if (WSF_TRACE_ENABLED == TRUE) - WsfCsEnter(); - memUsed = WsfBufIoUartInit(WsfHeapGetFreeStartAddress(), PLATFORM_UART_TERMINAL_BUFFER_SIZE); - WsfHeapAlloc(memUsed); - WsfCsExit(); -#endif - - WsfCsEnter(); - LlInitRtCfg_t llCfg = { .pBbRtCfg = &mainBbRtCfg, - .wlSizeCfg = 4, - .rlSizeCfg = 4, - .plSizeCfg = 4, - .pLlRtCfg = &mainLlRtCfg, - .pFreeMem = WsfHeapGetFreeStartAddress(), - .freeMemAvail = WsfHeapCountAvailable() }; - - memUsed = LlInitControllerInit(&llCfg); - WsfHeapAlloc(memUsed); - WsfCsExit(); - bdAddr_t bdAddr; PalCfgLoadData(PAL_CFG_ID_BD_ADDR, bdAddr, sizeof(bdAddr_t)); /* Coverity[uninit_use_in_call] */ diff --git a/Examples/MAX32655/Bluetooth/BLE_FreeRTOS/stack_dats.c b/Examples/MAX32655/Bluetooth/BLE_FreeRTOS/stack_dats.c index be5185af202..8ed942f5e86 100644 --- a/Examples/MAX32655/Bluetooth/BLE_FreeRTOS/stack_dats.c +++ b/Examples/MAX32655/Bluetooth/BLE_FreeRTOS/stack_dats.c @@ -174,9 +174,11 @@ static void mainWsfInit(void) const uint8_t numPools = sizeof(mainPoolDesc) / sizeof(mainPoolDesc[0]); uint16_t memUsed; + /* Initial buffer configuration. */ WsfCsEnter(); - memUsed = WsfBufInit(numPools, mainPoolDesc); + memUsed = WsfBufCalcSize(numPools, mainPoolDesc); WsfHeapAlloc(memUsed); + WsfBufInit(numPools, mainPoolDesc); WsfCsExit(); WsfOsInit(); @@ -327,27 +329,52 @@ void bleStartup(void) mainLlRtCfg.defTxPwrLvl = DEFAULT_TX_POWER; #endif - uint32_t memUsed; WsfCsEnter(); - memUsed = WsfBufIoUartInit(WsfHeapGetFreeStartAddress(), PLATFORM_UART_TERMINAL_BUFFER_SIZE); - WsfHeapAlloc(memUsed); + WsfHeapAlloc(PLATFORM_UART_TERMINAL_BUFFER_SIZE); + WsfBufIoUartInit(WsfHeapGetFreeStartAddress(), PLATFORM_UART_TERMINAL_BUFFER_SIZE); WsfCsExit(); mainWsfInit(); AppTerminalInit(); #if defined(HCI_TR_EXACTLE) && (HCI_TR_EXACTLE == 1) + uint32_t llmemUsed; + + /* Calculate how much memory we will need for the LL initialization */ WsfCsEnter(); - LlInitRtCfg_t llCfg = { .pBbRtCfg = &mainBbRtCfg, - .wlSizeCfg = 4, - .rlSizeCfg = 4, - .plSizeCfg = 4, - .pLlRtCfg = &mainLlRtCfg, - .pFreeMem = WsfHeapGetFreeStartAddress(), - .freeMemAvail = WsfHeapCountAvailable() }; - - memUsed = LlInit(&llCfg); - WsfHeapAlloc(memUsed); + + WsfTraceEnable(FALSE); + + LlInitRtCfg_t llCfg = { + .pBbRtCfg = &mainBbRtCfg, + .wlSizeCfg = 4, + .rlSizeCfg = 4, + .plSizeCfg = 4, + .pLlRtCfg = &mainLlRtCfg, + /* Not significant yet, only being used for memory size requirement calculation. */ + .pFreeMem = WsfHeapGetFreeStartAddress(), + /* Not significant yet, only being used for memory size requirement calculation. */ + .freeMemAvail = WsfHeapCountAvailable() + }; + + llmemUsed = LlInitSetRtCfg(&llCfg); + + /* Allocate the memory */ + WsfHeapAlloc(llmemUsed); + + /* Set the free memory pointers */ + llCfg.pFreeMem = WsfHeapGetFreeStartAddress(); + llCfg.freeMemAvail = WsfHeapCountAvailable(); + +#if (WSF_TOKEN_ENABLED == TRUE) || (WSF_TRACE_ENABLED == TRUE) + WsfTraceEnable(TRUE); +#endif + + /* Run the initialization with properly set the free memory pointers */ + if (llmemUsed != LlInitControllerInit(&llCfg)) { + WSF_ASSERT(0); + } + WsfCsExit(); bdAddr_t bdAddr; diff --git a/Examples/MAX32655/Bluetooth/BLE_HCI_DFU/BLT/main.c b/Examples/MAX32655/Bluetooth/BLE_HCI_DFU/BLT/main.c index d44a212cdcc..ed7b6082ce9 100644 --- a/Examples/MAX32655/Bluetooth/BLE_HCI_DFU/BLT/main.c +++ b/Examples/MAX32655/Bluetooth/BLE_HCI_DFU/BLT/main.c @@ -118,6 +118,10 @@ static void mainLoadConfiguration(void) /*************************************************************************************************/ static void mainWsfInit(void) { + uint32_t llmemUsed, memUsed; + + mainLoadConfiguration(); + /* +12 for message headroom, + 2 event header, +255 maximum parameter length. */ const uint16_t maxRptBufSize = 12 + 2 + 255; @@ -126,8 +130,8 @@ static void mainWsfInit(void) 12 + HCI_ISO_DL_MAX_LEN + mainLlRtCfg.maxAclLen + 4 + BB_DATA_PDU_TAILROOM; /* Use single pool for data buffers. */ -#if (BT_VER > 9) - WSF_ASSERT(mainLlRtCfg.maxAclLen == mainLlRtCfg.maxIsoSduLen); +#if (BT_VER > 9) && INIT_FEAT_ISO + mainLlRtCfg.maxIsoSduLen = mainLlRtCfg.maxAclLen; #endif /* Ensure pool buffers are ordered correctly. */ @@ -144,24 +148,61 @@ static void mainWsfInit(void) const uint8_t numPools = sizeof(poolDesc) / sizeof(poolDesc[0]); + /* Calculate how much memory we will need for the LL initialization */ + WsfCsEnter(); + + LlInitRtCfg_t llCfg = { + .pBbRtCfg = &mainBbRtCfg, + .wlSizeCfg = 4, + .rlSizeCfg = 4, + .plSizeCfg = 4, + .pLlRtCfg = &mainLlRtCfg, + /* Not significant yet, only being used for memory size requirement calculation. */ + .pFreeMem = WsfHeapGetFreeStartAddress(), + /* Not significant yet, only being used for memory size requirement calculation. */ + .freeMemAvail = WsfHeapCountAvailable() + }; + + llmemUsed = LlInitSetRtCfg(&llCfg); + + WsfCsExit(); + /* Initial buffer configuration. */ - uint16_t memUsed; WsfCsEnter(); - memUsed = WsfBufInit(numPools, poolDesc); + memUsed = WsfBufCalcSize(numPools, poolDesc); WsfHeapAlloc(memUsed); + WsfBufInit(numPools, poolDesc); WsfCsExit(); WsfOsInit(); WsfTimerInit(); + #if (WSF_TRACE_ENABLED == TRUE) WsfCsEnter(); - memUsed = WsfBufIoUartInit(WsfHeapGetFreeStartAddress(), PLATFORM_UART_TERMINAL_BUFFER_SIZE); - WsfHeapAlloc(memUsed); + WsfHeapAlloc(PLATFORM_UART_TERMINAL_BUFFER_SIZE); + WsfBufIoUartInit(WsfHeapGetFreeStartAddress(), PLATFORM_UART_TERMINAL_BUFFER_SIZE); WsfCsExit(); WsfTraceRegisterHandler(WsfBufIoWrite); WsfTraceEnable(TRUE); #endif + + /* Complete the LL initialization */ + WsfCsEnter(); + + /* Allocate the memory */ + WsfHeapAlloc(llmemUsed); + + /* Set the free memory pointers */ + llCfg.pFreeMem = WsfHeapGetFreeStartAddress(); + llCfg.freeMemAvail = WsfHeapCountAvailable(); + + /* Run the initialization with properly set the free memory pointers */ + if (llmemUsed != LlInitControllerInit(&llCfg)) { + WSF_ASSERT(0); + } + + WsfCsExit(); } /*************************************************************************************************/ @@ -171,7 +212,7 @@ static void mainWsfInit(void) * \return TRUE if there is token pending. */ /*************************************************************************************************/ -static bool_t mainCheckServiceTokens(void) +static bool mainCheckServiceTokens(void) { bool_t eventPending = FALSE; @@ -256,31 +297,8 @@ void setInterruptPriority(void) /*************************************************************************************************/ int main(void) { - uint32_t memUsed; - - mainLoadConfiguration(); mainWsfInit(); -#if (WSF_TRACE_ENABLED == TRUE) - WsfCsEnter(); - memUsed = WsfBufIoUartInit(WsfHeapGetFreeStartAddress(), PLATFORM_UART_TERMINAL_BUFFER_SIZE); - WsfHeapAlloc(memUsed); - WsfCsExit(); -#endif - - WsfCsEnter(); - LlInitRtCfg_t llCfg = { .pBbRtCfg = &mainBbRtCfg, - .wlSizeCfg = 4, - .rlSizeCfg = 4, - .plSizeCfg = 4, - .pLlRtCfg = &mainLlRtCfg, - .pFreeMem = WsfHeapGetFreeStartAddress(), - .freeMemAvail = WsfHeapCountAvailable() }; - - memUsed = LlInitControllerInit(&llCfg); - WsfHeapAlloc(memUsed); - WsfCsExit(); - bdAddr_t bdAddr; PalCfgLoadData(PAL_CFG_ID_BD_ADDR, bdAddr, sizeof(bdAddr_t)); /* Coverity[uninit_use_in_call] */ diff --git a/Examples/MAX32655/Bluetooth/BLE_datc/main.c b/Examples/MAX32655/Bluetooth/BLE_datc/main.c index 5ffb01957b7..aa049c63382 100644 --- a/Examples/MAX32655/Bluetooth/BLE_datc/main.c +++ b/Examples/MAX32655/Bluetooth/BLE_datc/main.c @@ -115,9 +115,11 @@ static void mainWsfInit(void) const uint8_t numPools = sizeof(mainPoolDesc) / sizeof(mainPoolDesc[0]); uint16_t memUsed; + /* Initial buffer configuration. */ WsfCsEnter(); - memUsed = WsfBufInit(numPools, mainPoolDesc); + memUsed = WsfBufCalcSize(numPools, mainPoolDesc); WsfHeapAlloc(memUsed); + WsfBufInit(numPools, mainPoolDesc); WsfCsExit(); WsfOsInit(); @@ -213,27 +215,54 @@ int main(void) mainLlRtCfg.defTxPwrLvl = DEFAULT_TX_POWER; #endif - uint32_t memUsed; WsfCsEnter(); - memUsed = WsfBufIoUartInit(WsfHeapGetFreeStartAddress(), PLATFORM_UART_TERMINAL_BUFFER_SIZE); - WsfHeapAlloc(memUsed); + WsfHeapAlloc(PLATFORM_UART_TERMINAL_BUFFER_SIZE); + WsfBufIoUartInit(WsfHeapGetFreeStartAddress(), PLATFORM_UART_TERMINAL_BUFFER_SIZE); WsfCsExit(); mainWsfInit(); AppTerminalInit(); #if defined(HCI_TR_EXACTLE) && (HCI_TR_EXACTLE == 1) + + uint32_t llmemUsed; + + /* Calculate how much memory we will need for the LL initialization */ WsfCsEnter(); - LlInitRtCfg_t llCfg = { .pBbRtCfg = &mainBbRtCfg, - .wlSizeCfg = 4, - .rlSizeCfg = 4, - .plSizeCfg = 4, - .pLlRtCfg = &mainLlRtCfg, - .pFreeMem = WsfHeapGetFreeStartAddress(), - .freeMemAvail = WsfHeapCountAvailable() }; - - memUsed = LlInit(&llCfg); - WsfHeapAlloc(memUsed); + + WsfTraceEnable(FALSE); + + LlInitRtCfg_t llCfg = { + .pBbRtCfg = &mainBbRtCfg, + .wlSizeCfg = 4, + .rlSizeCfg = 4, + .plSizeCfg = 4, + .pLlRtCfg = &mainLlRtCfg, + /* Not significant yet, only being used for memory size requirement calculation. */ + .pFreeMem = WsfHeapGetFreeStartAddress(), + /* Not significant yet, only being used for memory size requirement calculation. */ + .freeMemAvail = WsfHeapCountAvailable() + }; + + llmemUsed = LlInitSetRtCfg(&llCfg); + +#if (WSF_TOKEN_ENABLED == TRUE) || (WSF_TRACE_ENABLED == TRUE) + WsfTraceEnable(TRUE); +#endif + + /* Complete the LL initialization */ + /* Allocate the memory */ + WsfHeapAlloc(llmemUsed); + + /* Set the free memory pointers */ + llCfg.pFreeMem = WsfHeapGetFreeStartAddress(); + llCfg.freeMemAvail = WsfHeapCountAvailable(); + + /* Run the initialization with properly set the free memory pointers */ + if (llmemUsed != LlInit(&llCfg)) { + WSF_ASSERT(0); + } + WsfCsExit(); bdAddr_t bdAddr; diff --git a/Examples/MAX32655/Bluetooth/BLE_dats/main.c b/Examples/MAX32655/Bluetooth/BLE_dats/main.c index bdcee7ab7cc..a24d680d662 100644 --- a/Examples/MAX32655/Bluetooth/BLE_dats/main.c +++ b/Examples/MAX32655/Bluetooth/BLE_dats/main.c @@ -115,9 +115,11 @@ static void mainWsfInit(void) const uint8_t numPools = sizeof(mainPoolDesc) / sizeof(mainPoolDesc[0]); uint16_t memUsed; + /* Initial buffer configuration. */ WsfCsEnter(); - memUsed = WsfBufInit(numPools, mainPoolDesc); + memUsed = WsfBufCalcSize(numPools, mainPoolDesc); WsfHeapAlloc(memUsed); + WsfBufInit(numPools, mainPoolDesc); WsfCsExit(); WsfOsInit(); @@ -208,10 +210,9 @@ int main(void) mainLlRtCfg.defTxPwrLvl = DEFAULT_TX_POWER; #endif - uint32_t memUsed; WsfCsEnter(); - memUsed = WsfBufIoUartInit(WsfHeapGetFreeStartAddress(), PLATFORM_UART_TERMINAL_BUFFER_SIZE); - WsfHeapAlloc(memUsed); + WsfHeapAlloc(PLATFORM_UART_TERMINAL_BUFFER_SIZE); + WsfBufIoUartInit(WsfHeapGetFreeStartAddress(), PLATFORM_UART_TERMINAL_BUFFER_SIZE); WsfCsExit(); mainWsfInit(); @@ -219,17 +220,44 @@ int main(void) #if defined(HCI_TR_EXACTLE) && (HCI_TR_EXACTLE == 1) + uint32_t llmemUsed; + + /* Calculate how much memory we will need for the LL initialization */ WsfCsEnter(); - LlInitRtCfg_t llCfg = { .pBbRtCfg = &mainBbRtCfg, - .wlSizeCfg = 4, - .rlSizeCfg = 4, - .plSizeCfg = 4, - .pLlRtCfg = &mainLlRtCfg, - .pFreeMem = WsfHeapGetFreeStartAddress(), - .freeMemAvail = WsfHeapCountAvailable() }; - - memUsed = LlInit(&llCfg); - WsfHeapAlloc(memUsed); + + WsfTraceEnable(FALSE); + + LlInitRtCfg_t llCfg = { + .pBbRtCfg = &mainBbRtCfg, + .wlSizeCfg = 4, + .rlSizeCfg = 4, + .plSizeCfg = 4, + .pLlRtCfg = &mainLlRtCfg, + /* Not significant yet, only being used for memory size requirement calculation. */ + .pFreeMem = WsfHeapGetFreeStartAddress(), + /* Not significant yet, only being used for memory size requirement calculation. */ + .freeMemAvail = WsfHeapCountAvailable() + }; + + llmemUsed = LlInitSetRtCfg(&llCfg); + +#if (WSF_TOKEN_ENABLED == TRUE) || (WSF_TRACE_ENABLED == TRUE) + WsfTraceEnable(TRUE); +#endif + + /* Complete the LL initialization */ + /* Allocate the memory */ + WsfHeapAlloc(llmemUsed); + + /* Set the free memory pointers */ + llCfg.pFreeMem = WsfHeapGetFreeStartAddress(); + llCfg.freeMemAvail = WsfHeapCountAvailable(); + + /* Run the initialization with properly set the free memory pointers */ + if (llmemUsed != LlInit(&llCfg)) { + WSF_ASSERT(0); + } + WsfCsExit(); bdAddr_t bdAddr; diff --git a/Examples/MAX32655/Bluetooth/BLE_fit/main.c b/Examples/MAX32655/Bluetooth/BLE_fit/main.c index 0199877ad72..9996709c99a 100644 --- a/Examples/MAX32655/Bluetooth/BLE_fit/main.c +++ b/Examples/MAX32655/Bluetooth/BLE_fit/main.c @@ -115,9 +115,11 @@ static void mainWsfInit(void) const uint8_t numPools = sizeof(mainPoolDesc) / sizeof(mainPoolDesc[0]); uint16_t memUsed; + /* Initial buffer configuration. */ WsfCsEnter(); - memUsed = WsfBufInit(numPools, mainPoolDesc); + memUsed = WsfBufCalcSize(numPools, mainPoolDesc); WsfHeapAlloc(memUsed); + WsfBufInit(numPools, mainPoolDesc); WsfCsExit(); WsfOsInit(); @@ -194,27 +196,54 @@ int main(void) mainLlRtCfg.defTxPwrLvl = DEFAULT_TX_POWER; #endif - uint32_t memUsed; WsfCsEnter(); - memUsed = WsfBufIoUartInit(WsfHeapGetFreeStartAddress(), PLATFORM_UART_TERMINAL_BUFFER_SIZE); - WsfHeapAlloc(memUsed); + WsfHeapAlloc(PLATFORM_UART_TERMINAL_BUFFER_SIZE); + WsfBufIoUartInit(WsfHeapGetFreeStartAddress(), PLATFORM_UART_TERMINAL_BUFFER_SIZE); WsfCsExit(); mainWsfInit(); AppTerminalInit(); #if defined(HCI_TR_EXACTLE) && (HCI_TR_EXACTLE == 1) + + uint32_t llmemUsed; + + /* Calculate how much memory we will need for the LL initialization */ WsfCsEnter(); - LlInitRtCfg_t llCfg = { .pBbRtCfg = &mainBbRtCfg, - .wlSizeCfg = 4, - .rlSizeCfg = 4, - .plSizeCfg = 4, - .pLlRtCfg = &mainLlRtCfg, - .pFreeMem = WsfHeapGetFreeStartAddress(), - .freeMemAvail = WsfHeapCountAvailable() }; - - memUsed = LlInit(&llCfg); - WsfHeapAlloc(memUsed); + + WsfTraceEnable(FALSE); + + LlInitRtCfg_t llCfg = { + .pBbRtCfg = &mainBbRtCfg, + .wlSizeCfg = 4, + .rlSizeCfg = 4, + .plSizeCfg = 4, + .pLlRtCfg = &mainLlRtCfg, + /* Not significant yet, only being used for memory size requirement calculation. */ + .pFreeMem = WsfHeapGetFreeStartAddress(), + /* Not significant yet, only being used for memory size requirement calculation. */ + .freeMemAvail = WsfHeapCountAvailable() + }; + + llmemUsed = LlInitSetRtCfg(&llCfg); + +#if (WSF_TOKEN_ENABLED == TRUE) || (WSF_TRACE_ENABLED == TRUE) + WsfTraceEnable(TRUE); +#endif + + /* Complete the LL initialization */ + /* Allocate the memory */ + WsfHeapAlloc(llmemUsed); + + /* Set the free memory pointers */ + llCfg.pFreeMem = WsfHeapGetFreeStartAddress(); + llCfg.freeMemAvail = WsfHeapCountAvailable(); + + /* Run the initialization with properly set the free memory pointers */ + if (llmemUsed != LlInit(&llCfg)) { + WSF_ASSERT(0); + } + WsfCsExit(); bdAddr_t bdAddr; diff --git a/Examples/MAX32655/Bluetooth/BLE_fit_FreeRTOS/bt_stack.c b/Examples/MAX32655/Bluetooth/BLE_fit_FreeRTOS/bt_stack.c index 68f0c51d05d..780c4526aff 100644 --- a/Examples/MAX32655/Bluetooth/BLE_fit_FreeRTOS/bt_stack.c +++ b/Examples/MAX32655/Bluetooth/BLE_fit_FreeRTOS/bt_stack.c @@ -172,9 +172,11 @@ static void mainWsfInit(void) const uint8_t numPools = sizeof(mainPoolDesc) / sizeof(mainPoolDesc[0]); uint16_t memUsed; + /* Initial buffer configuration. */ WsfCsEnter(); - memUsed = WsfBufInit(numPools, mainPoolDesc); + memUsed = WsfBufCalcSize(numPools, mainPoolDesc); WsfHeapAlloc(memUsed); + WsfBufInit(numPools, mainPoolDesc); WsfCsExit(); WsfOsInit(); @@ -327,10 +329,10 @@ void btStartup(void) mainLlRtCfg.defTxPwrLvl = DEFAULT_TX_POWER; #endif - uint32_t memUsed; + uint32_t llmemUsed; WsfCsEnter(); - memUsed = WsfBufIoUartInit(WsfHeapGetFreeStartAddress(), PLATFORM_UART_TERMINAL_BUFFER_SIZE); - WsfHeapAlloc(memUsed); + WsfHeapAlloc(PLATFORM_UART_TERMINAL_BUFFER_SIZE); + WsfBufIoUartInit(WsfHeapGetFreeStartAddress(), PLATFORM_UART_TERMINAL_BUFFER_SIZE); WsfCsExit(); mainWsfInit(); @@ -338,17 +340,41 @@ void btStartup(void) AppTerminalInit(); #if defined(HCI_TR_EXACTLE) && (HCI_TR_EXACTLE == 1) + /* Calculate how much memory we will need for the LL initialization */ WsfCsEnter(); - LlInitRtCfg_t llCfg = { .pBbRtCfg = &mainBbRtCfg, - .wlSizeCfg = 4, - .rlSizeCfg = 4, - .plSizeCfg = 4, - .pLlRtCfg = &mainLlRtCfg, - .pFreeMem = WsfHeapGetFreeStartAddress(), - .freeMemAvail = WsfHeapCountAvailable() }; - - memUsed = LlInit(&llCfg); - WsfHeapAlloc(memUsed); + + WsfTraceEnable(FALSE); + + LlInitRtCfg_t llCfg = { + .pBbRtCfg = &mainBbRtCfg, + .wlSizeCfg = 4, + .rlSizeCfg = 4, + .plSizeCfg = 4, + .pLlRtCfg = &mainLlRtCfg, + /* Not significant yet, only being used for memory size requirement calculation. */ + .pFreeMem = WsfHeapGetFreeStartAddress(), + /* Not significant yet, only being used for memory size requirement calculation. */ + .freeMemAvail = WsfHeapCountAvailable() + }; + + llmemUsed = LlInitSetRtCfg(&llCfg); + + /* Allocate the memory */ + WsfHeapAlloc(llmemUsed); + + /* Set the free memory pointers */ + llCfg.pFreeMem = WsfHeapGetFreeStartAddress(); + llCfg.freeMemAvail = WsfHeapCountAvailable(); + +#if (WSF_TOKEN_ENABLED == TRUE) || (WSF_TRACE_ENABLED == TRUE) + WsfTraceEnable(TRUE); +#endif + + /* Run the initialization with properly set the free memory pointers */ + if (llmemUsed != LlInitControllerInit(&llCfg)) { + WSF_ASSERT(0); + } + WsfCsExit(); bdAddr_t bdAddr; diff --git a/Examples/MAX32655/Bluetooth/BLE_mcs/main.c b/Examples/MAX32655/Bluetooth/BLE_mcs/main.c index 507205876e8..40b8e205399 100644 --- a/Examples/MAX32655/Bluetooth/BLE_mcs/main.c +++ b/Examples/MAX32655/Bluetooth/BLE_mcs/main.c @@ -111,9 +111,11 @@ static void mainWsfInit(void) const uint8_t numPools = sizeof(mainPoolDesc) / sizeof(mainPoolDesc[0]); uint16_t memUsed; + /* Initial buffer configuration. */ WsfCsEnter(); - memUsed = WsfBufInit(numPools, mainPoolDesc); + memUsed = WsfBufCalcSize(numPools, mainPoolDesc); WsfHeapAlloc(memUsed); + WsfBufInit(numPools, mainPoolDesc); WsfCsExit(); WsfOsInit(); @@ -182,27 +184,54 @@ int main(void) mainLlRtCfg.defTxPwrLvl = DEFAULT_TX_POWER; #endif - uint32_t memUsed; WsfCsEnter(); - memUsed = WsfBufIoUartInit(WsfHeapGetFreeStartAddress(), PLATFORM_UART_TERMINAL_BUFFER_SIZE); - WsfHeapAlloc(memUsed); + WsfHeapAlloc(PLATFORM_UART_TERMINAL_BUFFER_SIZE); + WsfBufIoUartInit(WsfHeapGetFreeStartAddress(), PLATFORM_UART_TERMINAL_BUFFER_SIZE); WsfCsExit(); mainWsfInit(); AppTerminalInit(); #if defined(HCI_TR_EXACTLE) && (HCI_TR_EXACTLE == 1) + + uint32_t llmemUsed; + + /* Calculate how much memory we will need for the LL initialization */ WsfCsEnter(); - LlInitRtCfg_t llCfg = { .pBbRtCfg = &mainBbRtCfg, - .wlSizeCfg = 4, - .rlSizeCfg = 4, - .plSizeCfg = 4, - .pLlRtCfg = &mainLlRtCfg, - .pFreeMem = WsfHeapGetFreeStartAddress(), - .freeMemAvail = WsfHeapCountAvailable() }; - - memUsed = LlInit(&llCfg); - WsfHeapAlloc(memUsed); + + WsfTraceEnable(FALSE); + + LlInitRtCfg_t llCfg = { + .pBbRtCfg = &mainBbRtCfg, + .wlSizeCfg = 4, + .rlSizeCfg = 4, + .plSizeCfg = 4, + .pLlRtCfg = &mainLlRtCfg, + /* Not significant yet, only being used for memory size requirement calculation. */ + .pFreeMem = WsfHeapGetFreeStartAddress(), + /* Not significant yet, only being used for memory size requirement calculation. */ + .freeMemAvail = WsfHeapCountAvailable() + }; + + llmemUsed = LlInitSetRtCfg(&llCfg); + +#if (WSF_TOKEN_ENABLED == TRUE) || (WSF_TRACE_ENABLED == TRUE) + WsfTraceEnable(TRUE); +#endif + + /* Complete the LL initialization */ + /* Allocate the memory */ + WsfHeapAlloc(llmemUsed); + + /* Set the free memory pointers */ + llCfg.pFreeMem = WsfHeapGetFreeStartAddress(); + llCfg.freeMemAvail = WsfHeapCountAvailable(); + + /* Run the initialization with properly set the free memory pointers */ + if (llmemUsed != LlInit(&llCfg)) { + WSF_ASSERT(0); + } + WsfCsExit(); bdAddr_t bdAddr; diff --git a/Examples/MAX32655/Bluetooth/BLE_otac/main.c b/Examples/MAX32655/Bluetooth/BLE_otac/main.c index e0b023266b5..9f8799226c6 100644 --- a/Examples/MAX32655/Bluetooth/BLE_otac/main.c +++ b/Examples/MAX32655/Bluetooth/BLE_otac/main.c @@ -116,9 +116,11 @@ static void mainWsfInit(void) const uint8_t numPools = sizeof(mainPoolDesc) / sizeof(mainPoolDesc[0]); uint16_t memUsed; + /* Initial buffer configuration. */ WsfCsEnter(); - memUsed = WsfBufInit(numPools, mainPoolDesc); + memUsed = WsfBufCalcSize(numPools, mainPoolDesc); WsfHeapAlloc(memUsed); + WsfBufInit(numPools, mainPoolDesc); WsfCsExit(); WsfOsInit(); @@ -209,27 +211,54 @@ int main(void) mainLlRtCfg.defTxPwrLvl = DEFAULT_TX_POWER; #endif - uint32_t memUsed; WsfCsEnter(); - memUsed = WsfBufIoUartInit(WsfHeapGetFreeStartAddress(), PLATFORM_UART_TERMINAL_BUFFER_SIZE); - WsfHeapAlloc(memUsed); + WsfHeapAlloc(PLATFORM_UART_TERMINAL_BUFFER_SIZE); + WsfBufIoUartInit(WsfHeapGetFreeStartAddress(), PLATFORM_UART_TERMINAL_BUFFER_SIZE); WsfCsExit(); mainWsfInit(); AppTerminalInit(); #if defined(HCI_TR_EXACTLE) && (HCI_TR_EXACTLE == 1) + + uint32_t llmemUsed; + + /* Calculate how much memory we will need for the LL initialization */ WsfCsEnter(); - LlInitRtCfg_t llCfg = { .pBbRtCfg = &mainBbRtCfg, - .wlSizeCfg = 4, - .rlSizeCfg = 4, - .plSizeCfg = 4, - .pLlRtCfg = &mainLlRtCfg, - .pFreeMem = WsfHeapGetFreeStartAddress(), - .freeMemAvail = WsfHeapCountAvailable() }; - - memUsed = LlInit(&llCfg); - WsfHeapAlloc(memUsed); + + WsfTraceEnable(FALSE); + + LlInitRtCfg_t llCfg = { + .pBbRtCfg = &mainBbRtCfg, + .wlSizeCfg = 4, + .rlSizeCfg = 4, + .plSizeCfg = 4, + .pLlRtCfg = &mainLlRtCfg, + /* Not significant yet, only being used for memory size requirement calculation. */ + .pFreeMem = WsfHeapGetFreeStartAddress(), + /* Not significant yet, only being used for memory size requirement calculation. */ + .freeMemAvail = WsfHeapCountAvailable() + }; + + llmemUsed = LlInitSetRtCfg(&llCfg); + +#if (WSF_TOKEN_ENABLED == TRUE) || (WSF_TRACE_ENABLED == TRUE) + WsfTraceEnable(TRUE); +#endif + + /* Complete the LL initialization */ + /* Allocate the memory */ + WsfHeapAlloc(llmemUsed); + + /* Set the free memory pointers */ + llCfg.pFreeMem = WsfHeapGetFreeStartAddress(); + llCfg.freeMemAvail = WsfHeapCountAvailable(); + + /* Run the initialization with properly set the free memory pointers */ + if (llmemUsed != LlInit(&llCfg)) { + WSF_ASSERT(0); + } + WsfCsExit(); bdAddr_t bdAddr; diff --git a/Examples/MAX32655/Bluetooth/BLE_otas/main.c b/Examples/MAX32655/Bluetooth/BLE_otas/main.c index 01a0b4b19fe..5dbbb6ae70c 100644 --- a/Examples/MAX32655/Bluetooth/BLE_otas/main.c +++ b/Examples/MAX32655/Bluetooth/BLE_otas/main.c @@ -116,19 +116,20 @@ static void mainWsfInit(void) const uint8_t numPools = sizeof(mainPoolDesc) / sizeof(mainPoolDesc[0]); uint16_t memUsed; + /* Initial buffer configuration. */ WsfCsEnter(); - memUsed = WsfBufInit(numPools, mainPoolDesc); + memUsed = WsfBufCalcSize(numPools, mainPoolDesc); WsfHeapAlloc(memUsed); + WsfBufInit(numPools, mainPoolDesc); WsfCsExit(); WsfOsInit(); WsfTimerInit(); - #if (WSF_TOKEN_ENABLED == TRUE) || (WSF_TRACE_ENABLED == TRUE) WsfCsEnter(); + WsfHeapAlloc(PLATFORM_UART_TERMINAL_BUFFER_SIZE); memUsed = WsfBufIoUartInit(WsfHeapGetFreeStartAddress(), PLATFORM_UART_TERMINAL_BUFFER_SIZE); - WsfHeapAlloc(memUsed); WsfCsExit(); WsfTraceRegisterHandler(WsfBufIoWrite); @@ -188,8 +189,6 @@ void setAdvTxPower(void) /*************************************************************************************************/ int main(void) { - uint32_t memUsed; - #if defined(HCI_TR_EXACTLE) && (HCI_TR_EXACTLE == 1) /* Configurations must be persistent. */ static BbRtCfg_t mainBbRtCfg; @@ -224,17 +223,45 @@ int main(void) mainWsfInit(); #if defined(HCI_TR_EXACTLE) && (HCI_TR_EXACTLE == 1) + + uint32_t llmemUsed; + + /* Calculate how much memory we will need for the LL initialization */ WsfCsEnter(); - LlInitRtCfg_t llCfg = { .pBbRtCfg = &mainBbRtCfg, - .wlSizeCfg = 4, - .rlSizeCfg = 4, - .plSizeCfg = 4, - .pLlRtCfg = &mainLlRtCfg, - .pFreeMem = WsfHeapGetFreeStartAddress(), - .freeMemAvail = WsfHeapCountAvailable() }; - - memUsed = LlInit(&llCfg); - WsfHeapAlloc(memUsed); + + WsfTraceEnable(FALSE); + + LlInitRtCfg_t llCfg = { + .pBbRtCfg = &mainBbRtCfg, + .wlSizeCfg = 4, + .rlSizeCfg = 4, + .plSizeCfg = 4, + .pLlRtCfg = &mainLlRtCfg, + /* Not significant yet, only being used for memory size requirement calculation. */ + .pFreeMem = WsfHeapGetFreeStartAddress(), + /* Not significant yet, only being used for memory size requirement calculation. */ + .freeMemAvail = WsfHeapCountAvailable() + }; + + llmemUsed = LlInitSetRtCfg(&llCfg); + +#if (WSF_TOKEN_ENABLED == TRUE) || (WSF_TRACE_ENABLED == TRUE) + WsfTraceEnable(TRUE); +#endif + + /* Complete the LL initialization */ + /* Allocate the memory */ + WsfHeapAlloc(llmemUsed); + + /* Set the free memory pointers */ + llCfg.pFreeMem = WsfHeapGetFreeStartAddress(); + llCfg.freeMemAvail = WsfHeapCountAvailable(); + + /* Run the initialization with properly set the free memory pointers */ + if (llmemUsed != LlInit(&llCfg)) { + WSF_ASSERT(0); + } + WsfCsExit(); bdAddr_t bdAddr; diff --git a/Examples/MAX32655/Bluetooth/BLE_periph/main.c b/Examples/MAX32655/Bluetooth/BLE_periph/main.c index d4b86f7c404..60d68cd354f 100644 --- a/Examples/MAX32655/Bluetooth/BLE_periph/main.c +++ b/Examples/MAX32655/Bluetooth/BLE_periph/main.c @@ -131,8 +131,8 @@ static void mainWsfInit(void) uint32_t memUsed; WsfCsEnter(); - memUsed = WsfBufIoUartInit(WsfHeapGetFreeStartAddress(), PLATFORM_UART_TERMINAL_BUFFER_SIZE); - WsfHeapAlloc(memUsed); + WsfHeapAlloc(PLATFORM_UART_TERMINAL_BUFFER_SIZE); + WsfBufIoUartInit(WsfHeapGetFreeStartAddress(), PLATFORM_UART_TERMINAL_BUFFER_SIZE); WsfCsExit(); #if defined(HCI_TR_EXACTLE) && (HCI_TR_EXACTLE == 1) @@ -151,32 +151,50 @@ static void mainWsfInit(void) const uint8_t numPools = sizeof(mainPoolDesc) / sizeof(mainPoolDesc[0]); + /* Initial buffer configuration. */ WsfCsEnter(); - memUsed = WsfBufInit(numPools, mainPoolDesc); + memUsed = WsfBufCalcSize(numPools, mainPoolDesc); WsfHeapAlloc(memUsed); + WsfBufInit(numPools, mainPoolDesc); WsfCsExit(); WsfOsInit(); WsfTimerInit(); -#if (WSF_TOKEN_ENABLED == TRUE) || (WSF_TRACE_ENABLED == TRUE) - WsfTraceRegisterHandler(WsfBufIoWrite); - WsfTraceEnable(TRUE); -#endif AppTerminalInit(); #if defined(HCI_TR_EXACTLE) && (HCI_TR_EXACTLE == 1) + uint32_t llmemUsed; + + /* Calculate how much memory we will need for the LL initialization */ WsfCsEnter(); - LlInitRtCfg_t llCfg = { .pBbRtCfg = &mainBbRtCfg, - .wlSizeCfg = 4, - .rlSizeCfg = 4, - .plSizeCfg = 4, - .pLlRtCfg = &mainLlRtCfg, - .pFreeMem = WsfHeapGetFreeStartAddress(), - .freeMemAvail = WsfHeapCountAvailable() }; - - memUsed = LlInit(&llCfg); - WsfHeapAlloc(memUsed); + + LlInitRtCfg_t llCfg = { + .pBbRtCfg = &mainBbRtCfg, + .wlSizeCfg = 4, + .rlSizeCfg = 4, + .plSizeCfg = 4, + .pLlRtCfg = &mainLlRtCfg, + /* Not significant yet, only being used for memory size requirement calculation. */ + .pFreeMem = WsfHeapGetFreeStartAddress(), + /* Not significant yet, only being used for memory size requirement calculation. */ + .freeMemAvail = WsfHeapCountAvailable() + }; + + llmemUsed = LlInitSetRtCfg(&llCfg); + + /* Allocate the memory */ + WsfHeapAlloc(llmemUsed); + + /* Set the free memory pointers */ + llCfg.pFreeMem = WsfHeapGetFreeStartAddress(); + llCfg.freeMemAvail = WsfHeapCountAvailable(); + + /* Run the initialization with properly set the free memory pointers */ + if (llmemUsed != LlInitControllerInit(&llCfg)) { + WSF_ASSERT(0); + } + WsfCsExit(); bdAddr_t bdAddr; @@ -184,6 +202,11 @@ static void mainWsfInit(void) LlSetBdAddr((uint8_t *)&bdAddr); #endif +#if (WSF_TOKEN_ENABLED == TRUE) || (WSF_TRACE_ENABLED == TRUE) + WsfTraceRegisterHandler(WsfBufIoWrite); + WsfTraceEnable(TRUE); +#endif + StackInitPeriph(); PeriphStart(); diff --git a/Examples/MAX32655/Bluetooth/RF_Test/main.c b/Examples/MAX32655/Bluetooth/RF_Test/main.c index ad2168753c4..e4387d401e0 100644 --- a/Examples/MAX32655/Bluetooth/RF_Test/main.c +++ b/Examples/MAX32655/Bluetooth/RF_Test/main.c @@ -514,8 +514,13 @@ static void mainWsfInit(void) /* Initial buffer configuration. */ uint16_t memUsed; - memUsed = WsfBufInit(numPools, poolDesc); + /* Initial buffer configuration. */ + WsfCsEnter(); + memUsed = WsfBufCalcSize(numPools, poolDesc); WsfHeapAlloc(memUsed); + WsfBufInit(numPools, poolDesc); + WsfCsExit(); + WsfOsInit(); WsfTimerInit(); #if (WSF_TRACE_ENABLED == TRUE) @@ -857,26 +862,48 @@ void printConfigs(void) /*************************************************************************************************/ int main(void) { - uint32_t memUsed; + uint32_t llmemUsed; mainLoadConfiguration(); mainWsfInit(); #if (WSF_TRACE_ENABLED == TRUE) - memUsed = WsfBufIoUartInit(WsfHeapGetFreeStartAddress(), PLATFORM_UART_TERMINAL_BUFFER_SIZE); - WsfHeapAlloc(memUsed); + WsfCsEnter(); + WsfHeapAlloc(PLATFORM_UART_TERMINAL_BUFFER_SIZE); + WsfBufIoUartInit(WsfHeapGetFreeStartAddress(), PLATFORM_UART_TERMINAL_BUFFER_SIZE); + WsfCsExit(); #endif - LlInitRtCfg_t llCfg = { .pBbRtCfg = &mainBbRtCfg, - .wlSizeCfg = 4, - .rlSizeCfg = 4, - .plSizeCfg = 4, - .pLlRtCfg = &mainLlRtCfg, - .pFreeMem = WsfHeapGetFreeStartAddress(), - .freeMemAvail = WsfHeapCountAvailable() }; + /* Calculate how much memory we will need for the LL initialization */ + WsfCsEnter(); + + LlInitRtCfg_t llCfg = { + .pBbRtCfg = &mainBbRtCfg, + .wlSizeCfg = 4, + .rlSizeCfg = 4, + .plSizeCfg = 4, + .pLlRtCfg = &mainLlRtCfg, + /* Not significant yet, only being used for memory size requirement calculation. */ + .pFreeMem = WsfHeapGetFreeStartAddress(), + /* Not significant yet, only being used for memory size requirement calculation. */ + .freeMemAvail = WsfHeapCountAvailable() + }; - memUsed = LlInitControllerInit(&llCfg); - WsfHeapAlloc(memUsed); + llmemUsed = LlInitSetRtCfg(&llCfg); + + /* Allocate the memory */ + WsfHeapAlloc(llmemUsed); + + /* Set the free memory pointers */ + llCfg.pFreeMem = WsfHeapGetFreeStartAddress(); + llCfg.freeMemAvail = WsfHeapCountAvailable(); + + /* Run the initialization with properly set the free memory pointers */ + if (llmemUsed != LlInitControllerInit(&llCfg)) { + WSF_ASSERT(0); + } + + WsfCsExit(); bdAddr_t bdAddr; PalCfgLoadData(PAL_CFG_ID_BD_ADDR, bdAddr, sizeof(bdAddr_t)); diff --git a/Examples/MAX32655/Bluetooth/RF_Test/main.h b/Examples/MAX32655/Bluetooth/RF_Test/main.h index ba8486b1f02..a082659f7ec 100644 --- a/Examples/MAX32655/Bluetooth/RF_Test/main.h +++ b/Examples/MAX32655/Bluetooth/RF_Test/main.h @@ -41,6 +41,7 @@ #include "wsf_timer.h" #include "wsf_trace.h" #include "wsf_bufio.h" +#include "wsf_cs.h" #include "bb_ble_sniffer_api.h" #include "pal_bb.h" #include "pal_cfg.h" diff --git a/Examples/MAX32665/Bluetooth/BLE4_ctr/main.c b/Examples/MAX32665/Bluetooth/BLE4_ctr/main.c index d477d982d98..fc810e0a92a 100644 --- a/Examples/MAX32665/Bluetooth/BLE4_ctr/main.c +++ b/Examples/MAX32665/Bluetooth/BLE4_ctr/main.c @@ -95,6 +95,10 @@ static void mainLoadConfiguration(void) /*************************************************************************************************/ static void mainWsfInit(void) { + uint32_t llmemUsed, memUsed; + + mainLoadConfiguration(); + /* +12 for message headroom, +4 for header. */ const uint16_t aclBufSize = 12 + mainLlRtCfg.maxAclLen + 4 + BB_DATA_PDU_TAILROOM; @@ -105,24 +109,61 @@ static void mainWsfInit(void) const uint8_t numPools = sizeof(poolDesc) / sizeof(poolDesc[0]); + /* Calculate how much memory we will need for the LL initialization */ + WsfCsEnter(); + + LlInitRtCfg_t llCfg = { + .pBbRtCfg = &mainBbRtCfg, + .wlSizeCfg = 4, + .rlSizeCfg = 4, + .plSizeCfg = 4, + .pLlRtCfg = &mainLlRtCfg, + /* Not significant yet, only being used for memory size requirement calculation. */ + .pFreeMem = WsfHeapGetFreeStartAddress(), + /* Not significant yet, only being used for memory size requirement calculation. */ + .freeMemAvail = WsfHeapCountAvailable() + }; + + llmemUsed = LlInitSetRtCfg(&llCfg); + + WsfCsExit(); + /* Initial buffer configuration. */ - uint16_t memUsed; WsfCsEnter(); - memUsed = WsfBufInit(numPools, poolDesc); + memUsed = WsfBufCalcSize(numPools, poolDesc); WsfHeapAlloc(memUsed); + WsfBufInit(numPools, poolDesc); WsfCsExit(); WsfOsInit(); WsfTimerInit(); + #if (WSF_TRACE_ENABLED == TRUE) WsfCsEnter(); - memUsed = WsfBufIoUartInit(WsfHeapGetFreeStartAddress(), PLATFORM_UART_TERMINAL_BUFFER_SIZE); - WsfHeapAlloc(memUsed); + WsfHeapAlloc(PLATFORM_UART_TERMINAL_BUFFER_SIZE); + WsfBufIoUartInit(WsfHeapGetFreeStartAddress(), PLATFORM_UART_TERMINAL_BUFFER_SIZE); WsfCsExit(); WsfTraceRegisterHandler(WsfBufIoWrite); WsfTraceEnable(TRUE); #endif + + /* Complete the LL initialization */ + WsfCsEnter(); + + /* Allocate the memory */ + WsfHeapAlloc(llmemUsed); + + /* Set the free memory pointers */ + llCfg.pFreeMem = WsfHeapGetFreeStartAddress(); + llCfg.freeMemAvail = WsfHeapCountAvailable(); + + /* Run the initialization with properly set the free memory pointers */ + if (llmemUsed != LlInitControllerInit(&llCfg)) { + WSF_ASSERT(0); + } + + WsfCsExit(); } /*************************************************************************************************/ @@ -164,31 +205,8 @@ static bool mainCheckServiceTokens(void) /*************************************************************************************************/ int main(void) { - uint32_t memUsed; - - mainLoadConfiguration(); mainWsfInit(); -#if (WSF_TRACE_ENABLED == TRUE) - WsfCsEnter(); - memUsed = WsfBufIoUartInit(WsfHeapGetFreeStartAddress(), PLATFORM_UART_TERMINAL_BUFFER_SIZE); - WsfHeapAlloc(memUsed); - WsfCsExit(); -#endif - - WsfCsEnter(); - LlInitRtCfg_t llCfg = { .pBbRtCfg = &mainBbRtCfg, - .wlSizeCfg = 4, - .rlSizeCfg = 4, - .plSizeCfg = 4, - .pLlRtCfg = &mainLlRtCfg, - .pFreeMem = WsfHeapGetFreeStartAddress(), - .freeMemAvail = WsfHeapCountAvailable() }; - - memUsed = LlInitControllerInit(&llCfg); - WsfHeapAlloc(memUsed); - WsfCsExit(); - bdAddr_t bdAddr; PalCfgLoadData(PAL_CFG_ID_BD_ADDR, bdAddr, sizeof(bdAddr_t)); /* Coverity[uninit_use_in_call] */ diff --git a/Examples/MAX32665/Bluetooth/BLE5_ctr/main.c b/Examples/MAX32665/Bluetooth/BLE5_ctr/main.c index 0d9f01d126c..e589abe620b 100644 --- a/Examples/MAX32665/Bluetooth/BLE5_ctr/main.c +++ b/Examples/MAX32665/Bluetooth/BLE5_ctr/main.c @@ -111,6 +111,10 @@ static void mainLoadConfiguration(void) /*************************************************************************************************/ static void mainWsfInit(void) { + uint32_t llmemUsed, memUsed; + + mainLoadConfiguration(); + /* +12 for message headroom, + 2 event header, +255 maximum parameter length. */ const uint16_t maxRptBufSize = 12 + 2 + 255; @@ -137,24 +141,61 @@ static void mainWsfInit(void) const uint8_t numPools = sizeof(poolDesc) / sizeof(poolDesc[0]); + /* Calculate how much memory we will need for the LL initialization */ + WsfCsEnter(); + + LlInitRtCfg_t llCfg = { + .pBbRtCfg = &mainBbRtCfg, + .wlSizeCfg = 4, + .rlSizeCfg = 4, + .plSizeCfg = 4, + .pLlRtCfg = &mainLlRtCfg, + /* Not significant yet, only being used for memory size requirement calculation. */ + .pFreeMem = WsfHeapGetFreeStartAddress(), + /* Not significant yet, only being used for memory size requirement calculation. */ + .freeMemAvail = WsfHeapCountAvailable() + }; + + llmemUsed = LlInitSetRtCfg(&llCfg); + + WsfCsExit(); + /* Initial buffer configuration. */ - uint16_t memUsed; WsfCsEnter(); - memUsed = WsfBufInit(numPools, poolDesc); + memUsed = WsfBufCalcSize(numPools, poolDesc); WsfHeapAlloc(memUsed); + WsfBufInit(numPools, poolDesc); WsfCsExit(); WsfOsInit(); WsfTimerInit(); + #if (WSF_TRACE_ENABLED == TRUE) WsfCsEnter(); - memUsed = WsfBufIoUartInit(WsfHeapGetFreeStartAddress(), PLATFORM_UART_TERMINAL_BUFFER_SIZE); - WsfHeapAlloc(memUsed); + WsfHeapAlloc(PLATFORM_UART_TERMINAL_BUFFER_SIZE); + WsfBufIoUartInit(WsfHeapGetFreeStartAddress(), PLATFORM_UART_TERMINAL_BUFFER_SIZE); WsfCsExit(); WsfTraceRegisterHandler(WsfBufIoWrite); WsfTraceEnable(TRUE); #endif + + /* Complete the LL initialization */ + WsfCsEnter(); + + /* Allocate the memory */ + WsfHeapAlloc(llmemUsed); + + /* Set the free memory pointers */ + llCfg.pFreeMem = WsfHeapGetFreeStartAddress(); + llCfg.freeMemAvail = WsfHeapCountAvailable(); + + /* Run the initialization with properly set the free memory pointers */ + if (llmemUsed != LlInitControllerInit(&llCfg)) { + WSF_ASSERT(0); + } + + WsfCsExit(); } /*************************************************************************************************/ @@ -267,31 +308,8 @@ void setInterruptPriority(void) /*************************************************************************************************/ int main(void) { - uint32_t memUsed; - - mainLoadConfiguration(); mainWsfInit(); -#if (WSF_TRACE_ENABLED == TRUE) - WsfCsEnter(); - memUsed = WsfBufIoUartInit(WsfHeapGetFreeStartAddress(), PLATFORM_UART_TERMINAL_BUFFER_SIZE); - WsfHeapAlloc(memUsed); - WsfCsExit(); -#endif - - WsfCsEnter(); - LlInitRtCfg_t llCfg = { .pBbRtCfg = &mainBbRtCfg, - .wlSizeCfg = 4, - .rlSizeCfg = 4, - .plSizeCfg = 4, - .pLlRtCfg = &mainLlRtCfg, - .pFreeMem = WsfHeapGetFreeStartAddress(), - .freeMemAvail = WsfHeapCountAvailable() }; - - memUsed = LlInitControllerInit(&llCfg); - WsfHeapAlloc(memUsed); - WsfCsExit(); - bdAddr_t bdAddr; PalCfgLoadData(PAL_CFG_ID_BD_ADDR, bdAddr, sizeof(bdAddr_t)); /* Coverity[uninit_use_in_call] */ diff --git a/Examples/MAX32665/Bluetooth/BLE_FreeRTOS/stack_dats.c b/Examples/MAX32665/Bluetooth/BLE_FreeRTOS/stack_dats.c index c262788bb8d..3b057e84f47 100644 --- a/Examples/MAX32665/Bluetooth/BLE_FreeRTOS/stack_dats.c +++ b/Examples/MAX32665/Bluetooth/BLE_FreeRTOS/stack_dats.c @@ -176,9 +176,11 @@ static void mainWsfInit(void) const uint8_t numPools = sizeof(mainPoolDesc) / sizeof(mainPoolDesc[0]); uint16_t memUsed; + /* Initial buffer configuration. */ WsfCsEnter(); - memUsed = WsfBufInit(numPools, mainPoolDesc); + memUsed = WsfBufCalcSize(numPools, mainPoolDesc); WsfHeapAlloc(memUsed); + WsfBufInit(numPools, mainPoolDesc); WsfCsExit(); WsfOsInit(); @@ -360,27 +362,52 @@ void bleStartup(void) mainLlRtCfg.defTxPwrLvl = DEFAULT_TX_POWER; #endif - uint32_t memUsed; WsfCsEnter(); - memUsed = WsfBufIoUartInit(WsfHeapGetFreeStartAddress(), PLATFORM_UART_TERMINAL_BUFFER_SIZE); - WsfHeapAlloc(memUsed); + WsfHeapAlloc(PLATFORM_UART_TERMINAL_BUFFER_SIZE); + WsfBufIoUartInit(WsfHeapGetFreeStartAddress(), PLATFORM_UART_TERMINAL_BUFFER_SIZE); WsfCsExit(); mainWsfInit(); AppTerminalInit(); #if defined(HCI_TR_EXACTLE) && (HCI_TR_EXACTLE == 1) + uint32_t llmemUsed; + + /* Calculate how much memory we will need for the LL initialization */ WsfCsEnter(); - LlInitRtCfg_t llCfg = { .pBbRtCfg = &mainBbRtCfg, - .wlSizeCfg = 4, - .rlSizeCfg = 4, - .plSizeCfg = 4, - .pLlRtCfg = &mainLlRtCfg, - .pFreeMem = WsfHeapGetFreeStartAddress(), - .freeMemAvail = WsfHeapCountAvailable() }; - - memUsed = LlInit(&llCfg); - WsfHeapAlloc(memUsed); + + WsfTraceEnable(FALSE); + + LlInitRtCfg_t llCfg = { + .pBbRtCfg = &mainBbRtCfg, + .wlSizeCfg = 4, + .rlSizeCfg = 4, + .plSizeCfg = 4, + .pLlRtCfg = &mainLlRtCfg, + /* Not significant yet, only being used for memory size requirement calculation. */ + .pFreeMem = WsfHeapGetFreeStartAddress(), + /* Not significant yet, only being used for memory size requirement calculation. */ + .freeMemAvail = WsfHeapCountAvailable() + }; + + llmemUsed = LlInitSetRtCfg(&llCfg); + + /* Allocate the memory */ + WsfHeapAlloc(llmemUsed); + + /* Set the free memory pointers */ + llCfg.pFreeMem = WsfHeapGetFreeStartAddress(); + llCfg.freeMemAvail = WsfHeapCountAvailable(); + +#if (WSF_TOKEN_ENABLED == TRUE) || (WSF_TRACE_ENABLED == TRUE) + WsfTraceEnable(TRUE); +#endif + + /* Run the initialization with properly set the free memory pointers */ + if (llmemUsed != LlInitControllerInit(&llCfg)) { + WSF_ASSERT(0); + } + WsfCsExit(); bdAddr_t bdAddr; diff --git a/Examples/MAX32665/Bluetooth/BLE_datc/main.c b/Examples/MAX32665/Bluetooth/BLE_datc/main.c index 26c3b1cb10e..bf6fba9931e 100644 --- a/Examples/MAX32665/Bluetooth/BLE_datc/main.c +++ b/Examples/MAX32665/Bluetooth/BLE_datc/main.c @@ -117,9 +117,11 @@ static void mainWsfInit(void) const uint8_t numPools = sizeof(mainPoolDesc) / sizeof(mainPoolDesc[0]); uint16_t memUsed; + /* Initial buffer configuration. */ WsfCsEnter(); - memUsed = WsfBufInit(numPools, mainPoolDesc); + memUsed = WsfBufCalcSize(numPools, mainPoolDesc); WsfHeapAlloc(memUsed); + WsfBufInit(numPools, mainPoolDesc); WsfCsExit(); WsfOsInit(); @@ -230,27 +232,54 @@ int main(void) mainLlRtCfg.defTxPwrLvl = DEFAULT_TX_POWER; #endif - uint32_t memUsed; WsfCsEnter(); - memUsed = WsfBufIoUartInit(WsfHeapGetFreeStartAddress(), PLATFORM_UART_TERMINAL_BUFFER_SIZE); - WsfHeapAlloc(memUsed); + WsfHeapAlloc(PLATFORM_UART_TERMINAL_BUFFER_SIZE); + WsfBufIoUartInit(WsfHeapGetFreeStartAddress(), PLATFORM_UART_TERMINAL_BUFFER_SIZE); WsfCsExit(); mainWsfInit(); AppTerminalInit(); #if defined(HCI_TR_EXACTLE) && (HCI_TR_EXACTLE == 1) + + uint32_t llmemUsed; + + /* Calculate how much memory we will need for the LL initialization */ WsfCsEnter(); - LlInitRtCfg_t llCfg = { .pBbRtCfg = &mainBbRtCfg, - .wlSizeCfg = 4, - .rlSizeCfg = 4, - .plSizeCfg = 4, - .pLlRtCfg = &mainLlRtCfg, - .pFreeMem = WsfHeapGetFreeStartAddress(), - .freeMemAvail = WsfHeapCountAvailable() }; - - memUsed = LlInit(&llCfg); - WsfHeapAlloc(memUsed); + + WsfTraceEnable(FALSE); + + LlInitRtCfg_t llCfg = { + .pBbRtCfg = &mainBbRtCfg, + .wlSizeCfg = 4, + .rlSizeCfg = 4, + .plSizeCfg = 4, + .pLlRtCfg = &mainLlRtCfg, + /* Not significant yet, only being used for memory size requirement calculation. */ + .pFreeMem = WsfHeapGetFreeStartAddress(), + /* Not significant yet, only being used for memory size requirement calculation. */ + .freeMemAvail = WsfHeapCountAvailable() + }; + + llmemUsed = LlInitSetRtCfg(&llCfg); + +#if (WSF_TOKEN_ENABLED == TRUE) || (WSF_TRACE_ENABLED == TRUE) + WsfTraceEnable(TRUE); +#endif + + /* Complete the LL initialization */ + /* Allocate the memory */ + WsfHeapAlloc(llmemUsed); + + /* Set the free memory pointers */ + llCfg.pFreeMem = WsfHeapGetFreeStartAddress(); + llCfg.freeMemAvail = WsfHeapCountAvailable(); + + /* Run the initialization with properly set the free memory pointers */ + if (llmemUsed != LlInit(&llCfg)) { + WSF_ASSERT(0); + } + WsfCsExit(); bdAddr_t bdAddr; diff --git a/Examples/MAX32665/Bluetooth/BLE_dats/main.c b/Examples/MAX32665/Bluetooth/BLE_dats/main.c index f6792f04e03..4984dbb9a8e 100644 --- a/Examples/MAX32665/Bluetooth/BLE_dats/main.c +++ b/Examples/MAX32665/Bluetooth/BLE_dats/main.c @@ -117,9 +117,11 @@ static void mainWsfInit(void) const uint8_t numPools = sizeof(mainPoolDesc) / sizeof(mainPoolDesc[0]); uint16_t memUsed; + /* Initial buffer configuration. */ WsfCsEnter(); - memUsed = WsfBufInit(numPools, mainPoolDesc); + memUsed = WsfBufCalcSize(numPools, mainPoolDesc); WsfHeapAlloc(memUsed); + WsfBufInit(numPools, mainPoolDesc); WsfCsExit(); WsfOsInit(); @@ -226,10 +228,9 @@ int main(void) mainLlRtCfg.defTxPwrLvl = DEFAULT_TX_POWER; #endif - uint32_t memUsed; WsfCsEnter(); - memUsed = WsfBufIoUartInit(WsfHeapGetFreeStartAddress(), PLATFORM_UART_TERMINAL_BUFFER_SIZE); - WsfHeapAlloc(memUsed); + WsfHeapAlloc(PLATFORM_UART_TERMINAL_BUFFER_SIZE); + WsfBufIoUartInit(WsfHeapGetFreeStartAddress(), PLATFORM_UART_TERMINAL_BUFFER_SIZE); WsfCsExit(); mainWsfInit(); @@ -237,17 +238,44 @@ int main(void) #if defined(HCI_TR_EXACTLE) && (HCI_TR_EXACTLE == 1) + uint32_t llmemUsed; + + /* Calculate how much memory we will need for the LL initialization */ WsfCsEnter(); - LlInitRtCfg_t llCfg = { .pBbRtCfg = &mainBbRtCfg, - .wlSizeCfg = 4, - .rlSizeCfg = 4, - .plSizeCfg = 4, - .pLlRtCfg = &mainLlRtCfg, - .pFreeMem = WsfHeapGetFreeStartAddress(), - .freeMemAvail = WsfHeapCountAvailable() }; - - memUsed = LlInit(&llCfg); - WsfHeapAlloc(memUsed); + + WsfTraceEnable(FALSE); + + LlInitRtCfg_t llCfg = { + .pBbRtCfg = &mainBbRtCfg, + .wlSizeCfg = 4, + .rlSizeCfg = 4, + .plSizeCfg = 4, + .pLlRtCfg = &mainLlRtCfg, + /* Not significant yet, only being used for memory size requirement calculation. */ + .pFreeMem = WsfHeapGetFreeStartAddress(), + /* Not significant yet, only being used for memory size requirement calculation. */ + .freeMemAvail = WsfHeapCountAvailable() + }; + + llmemUsed = LlInitSetRtCfg(&llCfg); + +#if (WSF_TOKEN_ENABLED == TRUE) || (WSF_TRACE_ENABLED == TRUE) + WsfTraceEnable(TRUE); +#endif + + /* Complete the LL initialization */ + /* Allocate the memory */ + WsfHeapAlloc(llmemUsed); + + /* Set the free memory pointers */ + llCfg.pFreeMem = WsfHeapGetFreeStartAddress(); + llCfg.freeMemAvail = WsfHeapCountAvailable(); + + /* Run the initialization with properly set the free memory pointers */ + if (llmemUsed != LlInit(&llCfg)) { + WSF_ASSERT(0); + } + WsfCsExit(); bdAddr_t bdAddr; diff --git a/Examples/MAX32665/Bluetooth/BLE_fit/main.c b/Examples/MAX32665/Bluetooth/BLE_fit/main.c index 308f7221b19..533f4ecccae 100644 --- a/Examples/MAX32665/Bluetooth/BLE_fit/main.c +++ b/Examples/MAX32665/Bluetooth/BLE_fit/main.c @@ -12,7 +12,7 @@ * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at - * + * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software @@ -117,9 +117,11 @@ static void mainWsfInit(void) const uint8_t numPools = sizeof(mainPoolDesc) / sizeof(mainPoolDesc[0]); uint16_t memUsed; + /* Initial buffer configuration. */ WsfCsEnter(); - memUsed = WsfBufInit(numPools, mainPoolDesc); + memUsed = WsfBufCalcSize(numPools, mainPoolDesc); WsfHeapAlloc(memUsed); + WsfBufInit(numPools, mainPoolDesc); WsfCsExit(); WsfOsInit(); @@ -225,27 +227,54 @@ int main(void) mainLlRtCfg.defTxPwrLvl = DEFAULT_TX_POWER; #endif - uint32_t memUsed; WsfCsEnter(); - memUsed = WsfBufIoUartInit(WsfHeapGetFreeStartAddress(), PLATFORM_UART_TERMINAL_BUFFER_SIZE); - WsfHeapAlloc(memUsed); + WsfHeapAlloc(PLATFORM_UART_TERMINAL_BUFFER_SIZE); + WsfBufIoUartInit(WsfHeapGetFreeStartAddress(), PLATFORM_UART_TERMINAL_BUFFER_SIZE); WsfCsExit(); mainWsfInit(); AppTerminalInit(); #if defined(HCI_TR_EXACTLE) && (HCI_TR_EXACTLE == 1) + + uint32_t llmemUsed; + + /* Calculate how much memory we will need for the LL initialization */ WsfCsEnter(); - LlInitRtCfg_t llCfg = { .pBbRtCfg = &mainBbRtCfg, - .wlSizeCfg = 4, - .rlSizeCfg = 4, - .plSizeCfg = 4, - .pLlRtCfg = &mainLlRtCfg, - .pFreeMem = WsfHeapGetFreeStartAddress(), - .freeMemAvail = WsfHeapCountAvailable() }; - - memUsed = LlInit(&llCfg); - WsfHeapAlloc(memUsed); + + WsfTraceEnable(FALSE); + + LlInitRtCfg_t llCfg = { + .pBbRtCfg = &mainBbRtCfg, + .wlSizeCfg = 4, + .rlSizeCfg = 4, + .plSizeCfg = 4, + .pLlRtCfg = &mainLlRtCfg, + /* Not significant yet, only being used for memory size requirement calculation. */ + .pFreeMem = WsfHeapGetFreeStartAddress(), + /* Not significant yet, only being used for memory size requirement calculation. */ + .freeMemAvail = WsfHeapCountAvailable() + }; + + llmemUsed = LlInitSetRtCfg(&llCfg); + +#if (WSF_TOKEN_ENABLED == TRUE) || (WSF_TRACE_ENABLED == TRUE) + WsfTraceEnable(TRUE); +#endif + + /* Complete the LL initialization */ + /* Allocate the memory */ + WsfHeapAlloc(llmemUsed); + + /* Set the free memory pointers */ + llCfg.pFreeMem = WsfHeapGetFreeStartAddress(); + llCfg.freeMemAvail = WsfHeapCountAvailable(); + + /* Run the initialization with properly set the free memory pointers */ + if (llmemUsed != LlInit(&llCfg)) { + WSF_ASSERT(0); + } + WsfCsExit(); bdAddr_t bdAddr; diff --git a/Examples/MAX32665/Bluetooth/BLE_mcs/main.c b/Examples/MAX32665/Bluetooth/BLE_mcs/main.c index 1b2b9d92787..38769312c56 100644 --- a/Examples/MAX32665/Bluetooth/BLE_mcs/main.c +++ b/Examples/MAX32665/Bluetooth/BLE_mcs/main.c @@ -114,9 +114,11 @@ static void mainWsfInit(void) const uint8_t numPools = sizeof(mainPoolDesc) / sizeof(mainPoolDesc[0]); uint16_t memUsed; + /* Initial buffer configuration. */ WsfCsEnter(); - memUsed = WsfBufInit(numPools, mainPoolDesc); + memUsed = WsfBufCalcSize(numPools, mainPoolDesc); WsfHeapAlloc(memUsed); + WsfBufInit(numPools, mainPoolDesc); WsfCsExit(); WsfOsInit(); @@ -200,27 +202,54 @@ int main(void) mainLlRtCfg.defTxPwrLvl = DEFAULT_TX_POWER; #endif - uint32_t memUsed; WsfCsEnter(); - memUsed = WsfBufIoUartInit(WsfHeapGetFreeStartAddress(), PLATFORM_UART_TERMINAL_BUFFER_SIZE); - WsfHeapAlloc(memUsed); + WsfHeapAlloc(PLATFORM_UART_TERMINAL_BUFFER_SIZE); + WsfBufIoUartInit(WsfHeapGetFreeStartAddress(), PLATFORM_UART_TERMINAL_BUFFER_SIZE); WsfCsExit(); mainWsfInit(); AppTerminalInit(); #if defined(HCI_TR_EXACTLE) && (HCI_TR_EXACTLE == 1) + + uint32_t llmemUsed; + + /* Calculate how much memory we will need for the LL initialization */ WsfCsEnter(); - LlInitRtCfg_t llCfg = { .pBbRtCfg = &mainBbRtCfg, - .wlSizeCfg = 4, - .rlSizeCfg = 4, - .plSizeCfg = 4, - .pLlRtCfg = &mainLlRtCfg, - .pFreeMem = WsfHeapGetFreeStartAddress(), - .freeMemAvail = WsfHeapCountAvailable() }; - - memUsed = LlInit(&llCfg); - WsfHeapAlloc(memUsed); + + WsfTraceEnable(FALSE); + + LlInitRtCfg_t llCfg = { + .pBbRtCfg = &mainBbRtCfg, + .wlSizeCfg = 4, + .rlSizeCfg = 4, + .plSizeCfg = 4, + .pLlRtCfg = &mainLlRtCfg, + /* Not significant yet, only being used for memory size requirement calculation. */ + .pFreeMem = WsfHeapGetFreeStartAddress(), + /* Not significant yet, only being used for memory size requirement calculation. */ + .freeMemAvail = WsfHeapCountAvailable() + }; + + llmemUsed = LlInitSetRtCfg(&llCfg); + +#if (WSF_TOKEN_ENABLED == TRUE) || (WSF_TRACE_ENABLED == TRUE) + WsfTraceEnable(TRUE); +#endif + + /* Complete the LL initialization */ + /* Allocate the memory */ + WsfHeapAlloc(llmemUsed); + + /* Set the free memory pointers */ + llCfg.pFreeMem = WsfHeapGetFreeStartAddress(); + llCfg.freeMemAvail = WsfHeapCountAvailable(); + + /* Run the initialization with properly set the free memory pointers */ + if (llmemUsed != LlInit(&llCfg)) { + WSF_ASSERT(0); + } + WsfCsExit(); bdAddr_t bdAddr; diff --git a/Examples/MAX32665/Bluetooth/BLE_otac/main.c b/Examples/MAX32665/Bluetooth/BLE_otac/main.c index 6ba17c14f45..f61d84ded0a 100644 --- a/Examples/MAX32665/Bluetooth/BLE_otac/main.c +++ b/Examples/MAX32665/Bluetooth/BLE_otac/main.c @@ -118,9 +118,11 @@ static void mainWsfInit(void) const uint8_t numPools = sizeof(mainPoolDesc) / sizeof(mainPoolDesc[0]); uint16_t memUsed; + /* Initial buffer configuration. */ WsfCsEnter(); - memUsed = WsfBufInit(numPools, mainPoolDesc); + memUsed = WsfBufCalcSize(numPools, mainPoolDesc); WsfHeapAlloc(memUsed); + WsfBufInit(numPools, mainPoolDesc); WsfCsExit(); WsfOsInit(); @@ -226,27 +228,54 @@ int main(void) mainLlRtCfg.defTxPwrLvl = DEFAULT_TX_POWER; #endif - uint32_t memUsed; WsfCsEnter(); - memUsed = WsfBufIoUartInit(WsfHeapGetFreeStartAddress(), PLATFORM_UART_TERMINAL_BUFFER_SIZE); - WsfHeapAlloc(memUsed); + WsfHeapAlloc(PLATFORM_UART_TERMINAL_BUFFER_SIZE); + WsfBufIoUartInit(WsfHeapGetFreeStartAddress(), PLATFORM_UART_TERMINAL_BUFFER_SIZE); WsfCsExit(); mainWsfInit(); AppTerminalInit(); #if defined(HCI_TR_EXACTLE) && (HCI_TR_EXACTLE == 1) + + uint32_t llmemUsed; + + /* Calculate how much memory we will need for the LL initialization */ WsfCsEnter(); - LlInitRtCfg_t llCfg = { .pBbRtCfg = &mainBbRtCfg, - .wlSizeCfg = 4, - .rlSizeCfg = 4, - .plSizeCfg = 4, - .pLlRtCfg = &mainLlRtCfg, - .pFreeMem = WsfHeapGetFreeStartAddress(), - .freeMemAvail = WsfHeapCountAvailable() }; - - memUsed = LlInit(&llCfg); - WsfHeapAlloc(memUsed); + + WsfTraceEnable(FALSE); + + LlInitRtCfg_t llCfg = { + .pBbRtCfg = &mainBbRtCfg, + .wlSizeCfg = 4, + .rlSizeCfg = 4, + .plSizeCfg = 4, + .pLlRtCfg = &mainLlRtCfg, + /* Not significant yet, only being used for memory size requirement calculation. */ + .pFreeMem = WsfHeapGetFreeStartAddress(), + /* Not significant yet, only being used for memory size requirement calculation. */ + .freeMemAvail = WsfHeapCountAvailable() + }; + + llmemUsed = LlInitSetRtCfg(&llCfg); + +#if (WSF_TOKEN_ENABLED == TRUE) || (WSF_TRACE_ENABLED == TRUE) + WsfTraceEnable(TRUE); +#endif + + /* Complete the LL initialization */ + /* Allocate the memory */ + WsfHeapAlloc(llmemUsed); + + /* Set the free memory pointers */ + llCfg.pFreeMem = WsfHeapGetFreeStartAddress(); + llCfg.freeMemAvail = WsfHeapCountAvailable(); + + /* Run the initialization with properly set the free memory pointers */ + if (llmemUsed != LlInit(&llCfg)) { + WSF_ASSERT(0); + } + WsfCsExit(); bdAddr_t bdAddr; diff --git a/Examples/MAX32665/Bluetooth/BLE_otas/main.c b/Examples/MAX32665/Bluetooth/BLE_otas/main.c index 618d2c35a33..9056ea9a83e 100644 --- a/Examples/MAX32665/Bluetooth/BLE_otas/main.c +++ b/Examples/MAX32665/Bluetooth/BLE_otas/main.c @@ -118,16 +118,27 @@ static void mainWsfInit(void) const uint8_t numPools = sizeof(mainPoolDesc) / sizeof(mainPoolDesc[0]); uint16_t memUsed; + /* Initial buffer configuration. */ WsfCsEnter(); - memUsed = WsfBufInit(numPools, mainPoolDesc); + memUsed = WsfBufCalcSize(numPools, mainPoolDesc); WsfHeapAlloc(memUsed); + WsfBufInit(numPools, mainPoolDesc); WsfCsExit(); WsfOsInit(); WsfTimerInit(); #if (WSF_TOKEN_ENABLED == TRUE) || (WSF_TRACE_ENABLED == TRUE) + + WsfCsEnter(); + WsfHeapAlloc(PLATFORM_UART_TERMINAL_BUFFER_SIZE); + memUsed = WsfBufIoUartInit(WsfHeapGetFreeStartAddress(), PLATFORM_UART_TERMINAL_BUFFER_SIZE); + WsfCsExit(); + WsfTraceRegisterHandler(WsfBufIoWrite); WsfTraceEnable(TRUE); + + AppTerminalInit(); + #endif } @@ -226,27 +237,48 @@ int main(void) mainLlRtCfg.defTxPwrLvl = DEFAULT_TX_POWER; #endif - uint32_t memUsed; - WsfCsEnter(); - memUsed = WsfBufIoUartInit(WsfHeapGetFreeStartAddress(), PLATFORM_UART_TERMINAL_BUFFER_SIZE); - WsfHeapAlloc(memUsed); - WsfCsExit(); - mainWsfInit(); - AppTerminalInit(); #if defined(HCI_TR_EXACTLE) && (HCI_TR_EXACTLE == 1) + + uint32_t llmemUsed; + + /* Calculate how much memory we will need for the LL initialization */ WsfCsEnter(); - LlInitRtCfg_t llCfg = { .pBbRtCfg = &mainBbRtCfg, - .wlSizeCfg = 4, - .rlSizeCfg = 4, - .plSizeCfg = 4, - .pLlRtCfg = &mainLlRtCfg, - .pFreeMem = WsfHeapGetFreeStartAddress(), - .freeMemAvail = WsfHeapCountAvailable() }; - - memUsed = LlInit(&llCfg); - WsfHeapAlloc(memUsed); + + WsfTraceEnable(FALSE); + + LlInitRtCfg_t llCfg = { + .pBbRtCfg = &mainBbRtCfg, + .wlSizeCfg = 4, + .rlSizeCfg = 4, + .plSizeCfg = 4, + .pLlRtCfg = &mainLlRtCfg, + /* Not significant yet, only being used for memory size requirement calculation. */ + .pFreeMem = WsfHeapGetFreeStartAddress(), + /* Not significant yet, only being used for memory size requirement calculation. */ + .freeMemAvail = WsfHeapCountAvailable() + }; + + llmemUsed = LlInitSetRtCfg(&llCfg); + +#if (WSF_TOKEN_ENABLED == TRUE) || (WSF_TRACE_ENABLED == TRUE) + WsfTraceEnable(TRUE); +#endif + + /* Complete the LL initialization */ + /* Allocate the memory */ + WsfHeapAlloc(llmemUsed); + + /* Set the free memory pointers */ + llCfg.pFreeMem = WsfHeapGetFreeStartAddress(); + llCfg.freeMemAvail = WsfHeapCountAvailable(); + + /* Run the initialization with properly set the free memory pointers */ + if (llmemUsed != LlInit(&llCfg)) { + WSF_ASSERT(0); + } + WsfCsExit(); bdAddr_t bdAddr; diff --git a/Examples/MAX32665/Bluetooth/BLE_periph/main.c b/Examples/MAX32665/Bluetooth/BLE_periph/main.c index d4b86f7c404..60d68cd354f 100644 --- a/Examples/MAX32665/Bluetooth/BLE_periph/main.c +++ b/Examples/MAX32665/Bluetooth/BLE_periph/main.c @@ -131,8 +131,8 @@ static void mainWsfInit(void) uint32_t memUsed; WsfCsEnter(); - memUsed = WsfBufIoUartInit(WsfHeapGetFreeStartAddress(), PLATFORM_UART_TERMINAL_BUFFER_SIZE); - WsfHeapAlloc(memUsed); + WsfHeapAlloc(PLATFORM_UART_TERMINAL_BUFFER_SIZE); + WsfBufIoUartInit(WsfHeapGetFreeStartAddress(), PLATFORM_UART_TERMINAL_BUFFER_SIZE); WsfCsExit(); #if defined(HCI_TR_EXACTLE) && (HCI_TR_EXACTLE == 1) @@ -151,32 +151,50 @@ static void mainWsfInit(void) const uint8_t numPools = sizeof(mainPoolDesc) / sizeof(mainPoolDesc[0]); + /* Initial buffer configuration. */ WsfCsEnter(); - memUsed = WsfBufInit(numPools, mainPoolDesc); + memUsed = WsfBufCalcSize(numPools, mainPoolDesc); WsfHeapAlloc(memUsed); + WsfBufInit(numPools, mainPoolDesc); WsfCsExit(); WsfOsInit(); WsfTimerInit(); -#if (WSF_TOKEN_ENABLED == TRUE) || (WSF_TRACE_ENABLED == TRUE) - WsfTraceRegisterHandler(WsfBufIoWrite); - WsfTraceEnable(TRUE); -#endif AppTerminalInit(); #if defined(HCI_TR_EXACTLE) && (HCI_TR_EXACTLE == 1) + uint32_t llmemUsed; + + /* Calculate how much memory we will need for the LL initialization */ WsfCsEnter(); - LlInitRtCfg_t llCfg = { .pBbRtCfg = &mainBbRtCfg, - .wlSizeCfg = 4, - .rlSizeCfg = 4, - .plSizeCfg = 4, - .pLlRtCfg = &mainLlRtCfg, - .pFreeMem = WsfHeapGetFreeStartAddress(), - .freeMemAvail = WsfHeapCountAvailable() }; - - memUsed = LlInit(&llCfg); - WsfHeapAlloc(memUsed); + + LlInitRtCfg_t llCfg = { + .pBbRtCfg = &mainBbRtCfg, + .wlSizeCfg = 4, + .rlSizeCfg = 4, + .plSizeCfg = 4, + .pLlRtCfg = &mainLlRtCfg, + /* Not significant yet, only being used for memory size requirement calculation. */ + .pFreeMem = WsfHeapGetFreeStartAddress(), + /* Not significant yet, only being used for memory size requirement calculation. */ + .freeMemAvail = WsfHeapCountAvailable() + }; + + llmemUsed = LlInitSetRtCfg(&llCfg); + + /* Allocate the memory */ + WsfHeapAlloc(llmemUsed); + + /* Set the free memory pointers */ + llCfg.pFreeMem = WsfHeapGetFreeStartAddress(); + llCfg.freeMemAvail = WsfHeapCountAvailable(); + + /* Run the initialization with properly set the free memory pointers */ + if (llmemUsed != LlInitControllerInit(&llCfg)) { + WSF_ASSERT(0); + } + WsfCsExit(); bdAddr_t bdAddr; @@ -184,6 +202,11 @@ static void mainWsfInit(void) LlSetBdAddr((uint8_t *)&bdAddr); #endif +#if (WSF_TOKEN_ENABLED == TRUE) || (WSF_TRACE_ENABLED == TRUE) + WsfTraceRegisterHandler(WsfBufIoWrite); + WsfTraceEnable(TRUE); +#endif + StackInitPeriph(); PeriphStart(); diff --git a/Examples/MAX32665/Bluetooth/RF_Test/main.c b/Examples/MAX32665/Bluetooth/RF_Test/main.c index 4abcaee86c6..1659783e480 100644 --- a/Examples/MAX32665/Bluetooth/RF_Test/main.c +++ b/Examples/MAX32665/Bluetooth/RF_Test/main.c @@ -496,10 +496,11 @@ static void mainWsfInit(void) const uint16_t dataBufSize = 12 + HCI_ISO_DL_MAX_LEN + mainLlRtCfg.maxAclLen + 4 + BB_DATA_PDU_TAILROOM; -/* Use single pool for data buffers. */ + /* Use single pool for data buffers. */ #if (BT_VER > 9) WSF_ASSERT(mainLlRtCfg.maxAclLen == mainLlRtCfg.maxIsoSduLen); #endif + /* Ensure pool buffers are ordered correctly. */ WSF_ASSERT(maxRptBufSize < dataBufSize); @@ -516,8 +517,13 @@ static void mainWsfInit(void) /* Initial buffer configuration. */ uint16_t memUsed; - memUsed = WsfBufInit(numPools, poolDesc); + /* Initial buffer configuration. */ + WsfCsEnter(); + memUsed = WsfBufCalcSize(numPools, poolDesc); WsfHeapAlloc(memUsed); + WsfBufInit(numPools, poolDesc); + WsfCsExit(); + WsfOsInit(); WsfTimerInit(); #if (WSF_TRACE_ENABLED == TRUE) @@ -645,11 +651,11 @@ void vCmdLineTask(void *pvParameters) } } while (xMore != pdFALSE); } - /* New prompt */ bufferIndex = 0; memset(inputBuffer, 0x00, 100); prompt(); + } else if (bufferIndex < CMD_LINE_BUF_SIZE) { putchar(tmp); inputBuffer[bufferIndex++] = tmp; @@ -660,6 +666,7 @@ void vCmdLineTask(void *pvParameters) putchar(0x07); fflush(stdout); } + uartReadLen = 1; /* If more characters are ready, process them here */ } while ((MXC_UART_GetRXFIFOAvailable(MXC_UART_GET_UART(CONSOLE_UART)) > 0) && @@ -857,26 +864,48 @@ void printConfigs(void) /*************************************************************************************************/ int main(void) { - uint32_t memUsed; + uint32_t llmemUsed; mainLoadConfiguration(); mainWsfInit(); #if (WSF_TRACE_ENABLED == TRUE) - memUsed = WsfBufIoUartInit(WsfHeapGetFreeStartAddress(), PLATFORM_UART_TERMINAL_BUFFER_SIZE); - WsfHeapAlloc(memUsed); + WsfCsEnter(); + WsfHeapAlloc(PLATFORM_UART_TERMINAL_BUFFER_SIZE); + WsfBufIoUartInit(WsfHeapGetFreeStartAddress(), PLATFORM_UART_TERMINAL_BUFFER_SIZE); + WsfCsExit(); #endif - LlInitRtCfg_t llCfg = { .pBbRtCfg = &mainBbRtCfg, - .wlSizeCfg = 4, - .rlSizeCfg = 4, - .plSizeCfg = 4, - .pLlRtCfg = &mainLlRtCfg, - .pFreeMem = WsfHeapGetFreeStartAddress(), - .freeMemAvail = WsfHeapCountAvailable() }; + /* Calculate how much memory we will need for the LL initialization */ + WsfCsEnter(); + + LlInitRtCfg_t llCfg = { + .pBbRtCfg = &mainBbRtCfg, + .wlSizeCfg = 4, + .rlSizeCfg = 4, + .plSizeCfg = 4, + .pLlRtCfg = &mainLlRtCfg, + /* Not significant yet, only being used for memory size requirement calculation. */ + .pFreeMem = WsfHeapGetFreeStartAddress(), + /* Not significant yet, only being used for memory size requirement calculation. */ + .freeMemAvail = WsfHeapCountAvailable() + }; - memUsed = LlInitControllerInit(&llCfg); - WsfHeapAlloc(memUsed); + llmemUsed = LlInitSetRtCfg(&llCfg); + + /* Allocate the memory */ + WsfHeapAlloc(llmemUsed); + + /* Set the free memory pointers */ + llCfg.pFreeMem = WsfHeapGetFreeStartAddress(); + llCfg.freeMemAvail = WsfHeapCountAvailable(); + + /* Run the initialization with properly set the free memory pointers */ + if (llmemUsed != LlInitControllerInit(&llCfg)) { + WSF_ASSERT(0); + } + + WsfCsExit(); bdAddr_t bdAddr; PalCfgLoadData(PAL_CFG_ID_BD_ADDR, bdAddr, sizeof(bdAddr_t)); diff --git a/Examples/MAX32665/Bluetooth/RF_Test/main.h b/Examples/MAX32665/Bluetooth/RF_Test/main.h index 7b2d776b009..71f4466304b 100644 --- a/Examples/MAX32665/Bluetooth/RF_Test/main.h +++ b/Examples/MAX32665/Bluetooth/RF_Test/main.h @@ -41,6 +41,7 @@ #include "wsf_timer.h" #include "wsf_trace.h" #include "wsf_bufio.h" +#include "wsf_cs.h" #include "bb_ble_sniffer_api.h" #include "pal_bb.h" #include "pal_cfg.h" diff --git a/Examples/MAX32690/Bluetooth/BLE4_ctr/main.c b/Examples/MAX32690/Bluetooth/BLE4_ctr/main.c index d477d982d98..fc810e0a92a 100644 --- a/Examples/MAX32690/Bluetooth/BLE4_ctr/main.c +++ b/Examples/MAX32690/Bluetooth/BLE4_ctr/main.c @@ -95,6 +95,10 @@ static void mainLoadConfiguration(void) /*************************************************************************************************/ static void mainWsfInit(void) { + uint32_t llmemUsed, memUsed; + + mainLoadConfiguration(); + /* +12 for message headroom, +4 for header. */ const uint16_t aclBufSize = 12 + mainLlRtCfg.maxAclLen + 4 + BB_DATA_PDU_TAILROOM; @@ -105,24 +109,61 @@ static void mainWsfInit(void) const uint8_t numPools = sizeof(poolDesc) / sizeof(poolDesc[0]); + /* Calculate how much memory we will need for the LL initialization */ + WsfCsEnter(); + + LlInitRtCfg_t llCfg = { + .pBbRtCfg = &mainBbRtCfg, + .wlSizeCfg = 4, + .rlSizeCfg = 4, + .plSizeCfg = 4, + .pLlRtCfg = &mainLlRtCfg, + /* Not significant yet, only being used for memory size requirement calculation. */ + .pFreeMem = WsfHeapGetFreeStartAddress(), + /* Not significant yet, only being used for memory size requirement calculation. */ + .freeMemAvail = WsfHeapCountAvailable() + }; + + llmemUsed = LlInitSetRtCfg(&llCfg); + + WsfCsExit(); + /* Initial buffer configuration. */ - uint16_t memUsed; WsfCsEnter(); - memUsed = WsfBufInit(numPools, poolDesc); + memUsed = WsfBufCalcSize(numPools, poolDesc); WsfHeapAlloc(memUsed); + WsfBufInit(numPools, poolDesc); WsfCsExit(); WsfOsInit(); WsfTimerInit(); + #if (WSF_TRACE_ENABLED == TRUE) WsfCsEnter(); - memUsed = WsfBufIoUartInit(WsfHeapGetFreeStartAddress(), PLATFORM_UART_TERMINAL_BUFFER_SIZE); - WsfHeapAlloc(memUsed); + WsfHeapAlloc(PLATFORM_UART_TERMINAL_BUFFER_SIZE); + WsfBufIoUartInit(WsfHeapGetFreeStartAddress(), PLATFORM_UART_TERMINAL_BUFFER_SIZE); WsfCsExit(); WsfTraceRegisterHandler(WsfBufIoWrite); WsfTraceEnable(TRUE); #endif + + /* Complete the LL initialization */ + WsfCsEnter(); + + /* Allocate the memory */ + WsfHeapAlloc(llmemUsed); + + /* Set the free memory pointers */ + llCfg.pFreeMem = WsfHeapGetFreeStartAddress(); + llCfg.freeMemAvail = WsfHeapCountAvailable(); + + /* Run the initialization with properly set the free memory pointers */ + if (llmemUsed != LlInitControllerInit(&llCfg)) { + WSF_ASSERT(0); + } + + WsfCsExit(); } /*************************************************************************************************/ @@ -164,31 +205,8 @@ static bool mainCheckServiceTokens(void) /*************************************************************************************************/ int main(void) { - uint32_t memUsed; - - mainLoadConfiguration(); mainWsfInit(); -#if (WSF_TRACE_ENABLED == TRUE) - WsfCsEnter(); - memUsed = WsfBufIoUartInit(WsfHeapGetFreeStartAddress(), PLATFORM_UART_TERMINAL_BUFFER_SIZE); - WsfHeapAlloc(memUsed); - WsfCsExit(); -#endif - - WsfCsEnter(); - LlInitRtCfg_t llCfg = { .pBbRtCfg = &mainBbRtCfg, - .wlSizeCfg = 4, - .rlSizeCfg = 4, - .plSizeCfg = 4, - .pLlRtCfg = &mainLlRtCfg, - .pFreeMem = WsfHeapGetFreeStartAddress(), - .freeMemAvail = WsfHeapCountAvailable() }; - - memUsed = LlInitControllerInit(&llCfg); - WsfHeapAlloc(memUsed); - WsfCsExit(); - bdAddr_t bdAddr; PalCfgLoadData(PAL_CFG_ID_BD_ADDR, bdAddr, sizeof(bdAddr_t)); /* Coverity[uninit_use_in_call] */ diff --git a/Examples/MAX32690/Bluetooth/BLE5_ctr/main.c b/Examples/MAX32690/Bluetooth/BLE5_ctr/main.c index 848d21f777c..f7fcfa370cf 100644 --- a/Examples/MAX32690/Bluetooth/BLE5_ctr/main.c +++ b/Examples/MAX32690/Bluetooth/BLE5_ctr/main.c @@ -111,6 +111,10 @@ static void mainLoadConfiguration(void) /*************************************************************************************************/ static void mainWsfInit(void) { + uint32_t llmemUsed, memUsed; + + mainLoadConfiguration(); + /* +12 for message headroom, + 2 event header, +255 maximum parameter length. */ const uint16_t maxRptBufSize = 12 + 2 + 255; @@ -137,24 +141,61 @@ static void mainWsfInit(void) const uint8_t numPools = sizeof(poolDesc) / sizeof(poolDesc[0]); + /* Calculate how much memory we will need for the LL initialization */ + WsfCsEnter(); + + LlInitRtCfg_t llCfg = { + .pBbRtCfg = &mainBbRtCfg, + .wlSizeCfg = 4, + .rlSizeCfg = 4, + .plSizeCfg = 4, + .pLlRtCfg = &mainLlRtCfg, + /* Not significant yet, only being used for memory size requirement calculation. */ + .pFreeMem = WsfHeapGetFreeStartAddress(), + /* Not significant yet, only being used for memory size requirement calculation. */ + .freeMemAvail = WsfHeapCountAvailable() + }; + + llmemUsed = LlInitSetRtCfg(&llCfg); + + WsfCsExit(); + /* Initial buffer configuration. */ - uint16_t memUsed; WsfCsEnter(); - memUsed = WsfBufInit(numPools, poolDesc); + memUsed = WsfBufCalcSize(numPools, poolDesc); WsfHeapAlloc(memUsed); + WsfBufInit(numPools, poolDesc); WsfCsExit(); WsfOsInit(); WsfTimerInit(); + #if (WSF_TRACE_ENABLED == TRUE) WsfCsEnter(); - memUsed = WsfBufIoUartInit(WsfHeapGetFreeStartAddress(), PLATFORM_UART_TERMINAL_BUFFER_SIZE); - WsfHeapAlloc(memUsed); + WsfHeapAlloc(PLATFORM_UART_TERMINAL_BUFFER_SIZE); + WsfBufIoUartInit(WsfHeapGetFreeStartAddress(), PLATFORM_UART_TERMINAL_BUFFER_SIZE); WsfCsExit(); WsfTraceRegisterHandler(WsfBufIoWrite); WsfTraceEnable(TRUE); #endif + + /* Complete the LL initialization */ + WsfCsEnter(); + + /* Allocate the memory */ + WsfHeapAlloc(llmemUsed); + + /* Set the free memory pointers */ + llCfg.pFreeMem = WsfHeapGetFreeStartAddress(); + llCfg.freeMemAvail = WsfHeapCountAvailable(); + + /* Run the initialization with properly set the free memory pointers */ + if (llmemUsed != LlInitControllerInit(&llCfg)) { + WSF_ASSERT(0); + } + + WsfCsExit(); } /*************************************************************************************************/ @@ -251,31 +292,8 @@ void setInterruptPriority(void) /*************************************************************************************************/ int main(void) { - uint32_t memUsed; - - mainLoadConfiguration(); mainWsfInit(); -#if (WSF_TRACE_ENABLED == TRUE) - WsfCsEnter(); - memUsed = WsfBufIoUartInit(WsfHeapGetFreeStartAddress(), PLATFORM_UART_TERMINAL_BUFFER_SIZE); - WsfHeapAlloc(memUsed); - WsfCsExit(); -#endif - - WsfCsEnter(); - LlInitRtCfg_t llCfg = { .pBbRtCfg = &mainBbRtCfg, - .wlSizeCfg = 4, - .rlSizeCfg = 4, - .plSizeCfg = 4, - .pLlRtCfg = &mainLlRtCfg, - .pFreeMem = WsfHeapGetFreeStartAddress(), - .freeMemAvail = WsfHeapCountAvailable() }; - - memUsed = LlInitControllerInit(&llCfg); - WsfHeapAlloc(memUsed); - WsfCsExit(); - bdAddr_t bdAddr; PalCfgLoadData(PAL_CFG_ID_BD_ADDR, bdAddr, sizeof(bdAddr_t)); /* Coverity[uninit_use_in_call] */ diff --git a/Examples/MAX32690/Bluetooth/BLE_FreeRTOS/stack_dats.c b/Examples/MAX32690/Bluetooth/BLE_FreeRTOS/stack_dats.c index 700c2dde6c8..4d161efd20f 100644 --- a/Examples/MAX32690/Bluetooth/BLE_FreeRTOS/stack_dats.c +++ b/Examples/MAX32690/Bluetooth/BLE_FreeRTOS/stack_dats.c @@ -174,9 +174,11 @@ static void mainWsfInit(void) const uint8_t numPools = sizeof(mainPoolDesc) / sizeof(mainPoolDesc[0]); uint16_t memUsed; + /* Initial buffer configuration. */ WsfCsEnter(); - memUsed = WsfBufInit(numPools, mainPoolDesc); + memUsed = WsfBufCalcSize(numPools, mainPoolDesc); WsfHeapAlloc(memUsed); + WsfBufInit(numPools, mainPoolDesc); WsfCsExit(); WsfOsInit(); @@ -327,27 +329,52 @@ void bleStartup(void) mainLlRtCfg.defTxPwrLvl = DEFAULT_TX_POWER; #endif - uint32_t memUsed; WsfCsEnter(); - memUsed = WsfBufIoUartInit(WsfHeapGetFreeStartAddress(), PLATFORM_UART_TERMINAL_BUFFER_SIZE); - WsfHeapAlloc(memUsed); + WsfHeapAlloc(PLATFORM_UART_TERMINAL_BUFFER_SIZE); + WsfBufIoUartInit(WsfHeapGetFreeStartAddress(), PLATFORM_UART_TERMINAL_BUFFER_SIZE); WsfCsExit(); mainWsfInit(); AppTerminalInit(); #if defined(HCI_TR_EXACTLE) && (HCI_TR_EXACTLE == 1) + uint32_t llmemUsed; + + /* Calculate how much memory we will need for the LL initialization */ WsfCsEnter(); - LlInitRtCfg_t llCfg = { .pBbRtCfg = &mainBbRtCfg, - .wlSizeCfg = 4, - .rlSizeCfg = 4, - .plSizeCfg = 4, - .pLlRtCfg = &mainLlRtCfg, - .pFreeMem = WsfHeapGetFreeStartAddress(), - .freeMemAvail = WsfHeapCountAvailable() }; - - memUsed = LlInit(&llCfg); - WsfHeapAlloc(memUsed); + + WsfTraceEnable(FALSE); + + LlInitRtCfg_t llCfg = { + .pBbRtCfg = &mainBbRtCfg, + .wlSizeCfg = 4, + .rlSizeCfg = 4, + .plSizeCfg = 4, + .pLlRtCfg = &mainLlRtCfg, + /* Not significant yet, only being used for memory size requirement calculation. */ + .pFreeMem = WsfHeapGetFreeStartAddress(), + /* Not significant yet, only being used for memory size requirement calculation. */ + .freeMemAvail = WsfHeapCountAvailable() + }; + + llmemUsed = LlInitSetRtCfg(&llCfg); + + /* Allocate the memory */ + WsfHeapAlloc(llmemUsed); + + /* Set the free memory pointers */ + llCfg.pFreeMem = WsfHeapGetFreeStartAddress(); + llCfg.freeMemAvail = WsfHeapCountAvailable(); + +#if (WSF_TOKEN_ENABLED == TRUE) || (WSF_TRACE_ENABLED == TRUE) + WsfTraceEnable(TRUE); +#endif + + /* Run the initialization with properly set the free memory pointers */ + if (llmemUsed != LlInitControllerInit(&llCfg)) { + WSF_ASSERT(0); + } + WsfCsExit(); bdAddr_t bdAddr; diff --git a/Examples/MAX32690/Bluetooth/BLE_datc/main.c b/Examples/MAX32690/Bluetooth/BLE_datc/main.c index ed1ca5eb378..974026c8523 100644 --- a/Examples/MAX32690/Bluetooth/BLE_datc/main.c +++ b/Examples/MAX32690/Bluetooth/BLE_datc/main.c @@ -116,8 +116,9 @@ static void mainWsfInit(void) uint16_t memUsed; WsfCsEnter(); - memUsed = WsfBufInit(numPools, mainPoolDesc); + memUsed = WsfBufCalcSize(numPools, mainPoolDesc); WsfHeapAlloc(memUsed); + WsfBufInit(numPools, mainPoolDesc); WsfCsExit(); WsfOsInit(); @@ -213,27 +214,55 @@ int main(void) mainLlRtCfg.defTxPwrLvl = DEFAULT_TX_POWER; #endif - uint32_t memUsed; WsfCsEnter(); - memUsed = WsfBufIoUartInit(WsfHeapGetFreeStartAddress(), PLATFORM_UART_TERMINAL_BUFFER_SIZE); - WsfHeapAlloc(memUsed); + WsfHeapAlloc(PLATFORM_UART_TERMINAL_BUFFER_SIZE); + WsfBufIoUartInit(WsfHeapGetFreeStartAddress(), PLATFORM_UART_TERMINAL_BUFFER_SIZE); WsfCsExit(); mainWsfInit(); AppTerminalInit(); #if defined(HCI_TR_EXACTLE) && (HCI_TR_EXACTLE == 1) + + uint32_t llmemUsed; + + /* Calculate how much memory we will need for the LL initialization */ + WsfCsEnter(); - LlInitRtCfg_t llCfg = { .pBbRtCfg = &mainBbRtCfg, - .wlSizeCfg = 4, - .rlSizeCfg = 4, - .plSizeCfg = 4, - .pLlRtCfg = &mainLlRtCfg, - .pFreeMem = WsfHeapGetFreeStartAddress(), - .freeMemAvail = WsfHeapCountAvailable() }; - - memUsed = LlInit(&llCfg); - WsfHeapAlloc(memUsed); + + WsfTraceEnable(FALSE); + + LlInitRtCfg_t llCfg = { + .pBbRtCfg = &mainBbRtCfg, + .wlSizeCfg = 4, + .rlSizeCfg = 4, + .plSizeCfg = 4, + .pLlRtCfg = &mainLlRtCfg, + /* Not significant yet, only being used for memory size requirement calculation. */ + .pFreeMem = WsfHeapGetFreeStartAddress(), + /* Not significant yet, only being used for memory size requirement calculation. */ + .freeMemAvail = WsfHeapCountAvailable() + }; + + llmemUsed = LlInitSetRtCfg(&llCfg); + +#if (WSF_TOKEN_ENABLED == TRUE) || (WSF_TRACE_ENABLED == TRUE) + WsfTraceEnable(TRUE); +#endif + + /* Complete the LL initialization */ + /* Allocate the memory */ + WsfHeapAlloc(llmemUsed); + + /* Set the free memory pointers */ + llCfg.pFreeMem = WsfHeapGetFreeStartAddress(); + llCfg.freeMemAvail = WsfHeapCountAvailable(); + + /* Run the initialization with properly set the free memory pointers */ + if (llmemUsed != LlInit(&llCfg)) { + WSF_ASSERT(0); + } + WsfCsExit(); bdAddr_t bdAddr; diff --git a/Examples/MAX32690/Bluetooth/BLE_dats/main.c b/Examples/MAX32690/Bluetooth/BLE_dats/main.c index f7430274b73..43d033646e3 100644 --- a/Examples/MAX32690/Bluetooth/BLE_dats/main.c +++ b/Examples/MAX32690/Bluetooth/BLE_dats/main.c @@ -115,9 +115,11 @@ static void mainWsfInit(void) const uint8_t numPools = sizeof(mainPoolDesc) / sizeof(mainPoolDesc[0]); uint16_t memUsed; + /* Initial buffer configuration. */ WsfCsEnter(); - memUsed = WsfBufInit(numPools, mainPoolDesc); + memUsed = WsfBufCalcSize(numPools, mainPoolDesc); WsfHeapAlloc(memUsed); + WsfBufInit(numPools, mainPoolDesc); WsfCsExit(); WsfOsInit(); @@ -208,10 +210,9 @@ int main(void) mainLlRtCfg.defTxPwrLvl = DEFAULT_TX_POWER; #endif - uint32_t memUsed; WsfCsEnter(); - memUsed = WsfBufIoUartInit(WsfHeapGetFreeStartAddress(), PLATFORM_UART_TERMINAL_BUFFER_SIZE); - WsfHeapAlloc(memUsed); + WsfHeapAlloc(PLATFORM_UART_TERMINAL_BUFFER_SIZE); + WsfBufIoUartInit(WsfHeapGetFreeStartAddress(), PLATFORM_UART_TERMINAL_BUFFER_SIZE); WsfCsExit(); mainWsfInit(); @@ -219,17 +220,44 @@ int main(void) #if defined(HCI_TR_EXACTLE) && (HCI_TR_EXACTLE == 1) + uint32_t llmemUsed; + + /* Calculate how much memory we will need for the LL initialization */ WsfCsEnter(); - LlInitRtCfg_t llCfg = { .pBbRtCfg = &mainBbRtCfg, - .wlSizeCfg = 4, - .rlSizeCfg = 4, - .plSizeCfg = 4, - .pLlRtCfg = &mainLlRtCfg, - .pFreeMem = WsfHeapGetFreeStartAddress(), - .freeMemAvail = WsfHeapCountAvailable() }; - - memUsed = LlInit(&llCfg); - WsfHeapAlloc(memUsed); + + WsfTraceEnable(FALSE); + + LlInitRtCfg_t llCfg = { + .pBbRtCfg = &mainBbRtCfg, + .wlSizeCfg = 4, + .rlSizeCfg = 4, + .plSizeCfg = 4, + .pLlRtCfg = &mainLlRtCfg, + /* Not significant yet, only being used for memory size requirement calculation. */ + .pFreeMem = WsfHeapGetFreeStartAddress(), + /* Not significant yet, only being used for memory size requirement calculation. */ + .freeMemAvail = WsfHeapCountAvailable() + }; + + llmemUsed = LlInitSetRtCfg(&llCfg); + +#if (WSF_TOKEN_ENABLED == TRUE) || (WSF_TRACE_ENABLED == TRUE) + WsfTraceEnable(TRUE); +#endif + + /* Complete the LL initialization */ + /* Allocate the memory */ + WsfHeapAlloc(llmemUsed); + + /* Set the free memory pointers */ + llCfg.pFreeMem = WsfHeapGetFreeStartAddress(); + llCfg.freeMemAvail = WsfHeapCountAvailable(); + + /* Run the initialization with properly set the free memory pointers */ + if (llmemUsed != LlInit(&llCfg)) { + WSF_ASSERT(0); + } + WsfCsExit(); bdAddr_t bdAddr; diff --git a/Examples/MAX32690/Bluetooth/BLE_fit/main.c b/Examples/MAX32690/Bluetooth/BLE_fit/main.c index f43129c09bc..170005b548d 100644 --- a/Examples/MAX32690/Bluetooth/BLE_fit/main.c +++ b/Examples/MAX32690/Bluetooth/BLE_fit/main.c @@ -115,9 +115,11 @@ static void mainWsfInit(void) const uint8_t numPools = sizeof(mainPoolDesc) / sizeof(mainPoolDesc[0]); uint16_t memUsed; + /* Initial buffer configuration. */ WsfCsEnter(); - memUsed = WsfBufInit(numPools, mainPoolDesc); + memUsed = WsfBufCalcSize(numPools, mainPoolDesc); WsfHeapAlloc(memUsed); + WsfBufInit(numPools, mainPoolDesc); WsfCsExit(); WsfOsInit(); @@ -208,27 +210,54 @@ int main(void) mainLlRtCfg.defTxPwrLvl = DEFAULT_TX_POWER; #endif - uint32_t memUsed; WsfCsEnter(); - memUsed = WsfBufIoUartInit(WsfHeapGetFreeStartAddress(), PLATFORM_UART_TERMINAL_BUFFER_SIZE); - WsfHeapAlloc(memUsed); + WsfHeapAlloc(PLATFORM_UART_TERMINAL_BUFFER_SIZE); + WsfBufIoUartInit(WsfHeapGetFreeStartAddress(), PLATFORM_UART_TERMINAL_BUFFER_SIZE); WsfCsExit(); mainWsfInit(); AppTerminalInit(); #if defined(HCI_TR_EXACTLE) && (HCI_TR_EXACTLE == 1) + + uint32_t llmemUsed; + + /* Calculate how much memory we will need for the LL initialization */ WsfCsEnter(); - LlInitRtCfg_t llCfg = { .pBbRtCfg = &mainBbRtCfg, - .wlSizeCfg = 4, - .rlSizeCfg = 4, - .plSizeCfg = 4, - .pLlRtCfg = &mainLlRtCfg, - .pFreeMem = WsfHeapGetFreeStartAddress(), - .freeMemAvail = WsfHeapCountAvailable() }; - - memUsed = LlInit(&llCfg); - WsfHeapAlloc(memUsed); + + WsfTraceEnable(FALSE); + + LlInitRtCfg_t llCfg = { + .pBbRtCfg = &mainBbRtCfg, + .wlSizeCfg = 4, + .rlSizeCfg = 4, + .plSizeCfg = 4, + .pLlRtCfg = &mainLlRtCfg, + /* Not significant yet, only being used for memory size requirement calculation. */ + .pFreeMem = WsfHeapGetFreeStartAddress(), + /* Not significant yet, only being used for memory size requirement calculation. */ + .freeMemAvail = WsfHeapCountAvailable() + }; + + llmemUsed = LlInitSetRtCfg(&llCfg); + +#if (WSF_TOKEN_ENABLED == TRUE) || (WSF_TRACE_ENABLED == TRUE) + WsfTraceEnable(TRUE); +#endif + + /* Complete the LL initialization */ + /* Allocate the memory */ + WsfHeapAlloc(llmemUsed); + + /* Set the free memory pointers */ + llCfg.pFreeMem = WsfHeapGetFreeStartAddress(); + llCfg.freeMemAvail = WsfHeapCountAvailable(); + + /* Run the initialization with properly set the free memory pointers */ + if (llmemUsed != LlInit(&llCfg)) { + WSF_ASSERT(0); + } + WsfCsExit(); bdAddr_t bdAddr; diff --git a/Examples/MAX32690/Bluetooth/BLE_mcs/main.c b/Examples/MAX32690/Bluetooth/BLE_mcs/main.c index 507205876e8..40b8e205399 100644 --- a/Examples/MAX32690/Bluetooth/BLE_mcs/main.c +++ b/Examples/MAX32690/Bluetooth/BLE_mcs/main.c @@ -111,9 +111,11 @@ static void mainWsfInit(void) const uint8_t numPools = sizeof(mainPoolDesc) / sizeof(mainPoolDesc[0]); uint16_t memUsed; + /* Initial buffer configuration. */ WsfCsEnter(); - memUsed = WsfBufInit(numPools, mainPoolDesc); + memUsed = WsfBufCalcSize(numPools, mainPoolDesc); WsfHeapAlloc(memUsed); + WsfBufInit(numPools, mainPoolDesc); WsfCsExit(); WsfOsInit(); @@ -182,27 +184,54 @@ int main(void) mainLlRtCfg.defTxPwrLvl = DEFAULT_TX_POWER; #endif - uint32_t memUsed; WsfCsEnter(); - memUsed = WsfBufIoUartInit(WsfHeapGetFreeStartAddress(), PLATFORM_UART_TERMINAL_BUFFER_SIZE); - WsfHeapAlloc(memUsed); + WsfHeapAlloc(PLATFORM_UART_TERMINAL_BUFFER_SIZE); + WsfBufIoUartInit(WsfHeapGetFreeStartAddress(), PLATFORM_UART_TERMINAL_BUFFER_SIZE); WsfCsExit(); mainWsfInit(); AppTerminalInit(); #if defined(HCI_TR_EXACTLE) && (HCI_TR_EXACTLE == 1) + + uint32_t llmemUsed; + + /* Calculate how much memory we will need for the LL initialization */ WsfCsEnter(); - LlInitRtCfg_t llCfg = { .pBbRtCfg = &mainBbRtCfg, - .wlSizeCfg = 4, - .rlSizeCfg = 4, - .plSizeCfg = 4, - .pLlRtCfg = &mainLlRtCfg, - .pFreeMem = WsfHeapGetFreeStartAddress(), - .freeMemAvail = WsfHeapCountAvailable() }; - - memUsed = LlInit(&llCfg); - WsfHeapAlloc(memUsed); + + WsfTraceEnable(FALSE); + + LlInitRtCfg_t llCfg = { + .pBbRtCfg = &mainBbRtCfg, + .wlSizeCfg = 4, + .rlSizeCfg = 4, + .plSizeCfg = 4, + .pLlRtCfg = &mainLlRtCfg, + /* Not significant yet, only being used for memory size requirement calculation. */ + .pFreeMem = WsfHeapGetFreeStartAddress(), + /* Not significant yet, only being used for memory size requirement calculation. */ + .freeMemAvail = WsfHeapCountAvailable() + }; + + llmemUsed = LlInitSetRtCfg(&llCfg); + +#if (WSF_TOKEN_ENABLED == TRUE) || (WSF_TRACE_ENABLED == TRUE) + WsfTraceEnable(TRUE); +#endif + + /* Complete the LL initialization */ + /* Allocate the memory */ + WsfHeapAlloc(llmemUsed); + + /* Set the free memory pointers */ + llCfg.pFreeMem = WsfHeapGetFreeStartAddress(); + llCfg.freeMemAvail = WsfHeapCountAvailable(); + + /* Run the initialization with properly set the free memory pointers */ + if (llmemUsed != LlInit(&llCfg)) { + WSF_ASSERT(0); + } + WsfCsExit(); bdAddr_t bdAddr; diff --git a/Examples/MAX32690/Bluetooth/BLE_otac/main.c b/Examples/MAX32690/Bluetooth/BLE_otac/main.c index cfc16e2cbfe..2e4a0fbd036 100644 --- a/Examples/MAX32690/Bluetooth/BLE_otac/main.c +++ b/Examples/MAX32690/Bluetooth/BLE_otac/main.c @@ -116,9 +116,11 @@ static void mainWsfInit(void) const uint8_t numPools = sizeof(mainPoolDesc) / sizeof(mainPoolDesc[0]); uint16_t memUsed; + /* Initial buffer configuration. */ WsfCsEnter(); - memUsed = WsfBufInit(numPools, mainPoolDesc); + memUsed = WsfBufCalcSize(numPools, mainPoolDesc); WsfHeapAlloc(memUsed); + WsfBufInit(numPools, mainPoolDesc); WsfCsExit(); WsfOsInit(); @@ -209,27 +211,54 @@ int main(void) mainLlRtCfg.defTxPwrLvl = DEFAULT_TX_POWER; #endif - uint32_t memUsed; WsfCsEnter(); - memUsed = WsfBufIoUartInit(WsfHeapGetFreeStartAddress(), PLATFORM_UART_TERMINAL_BUFFER_SIZE); - WsfHeapAlloc(memUsed); + WsfHeapAlloc(PLATFORM_UART_TERMINAL_BUFFER_SIZE); + WsfBufIoUartInit(WsfHeapGetFreeStartAddress(), PLATFORM_UART_TERMINAL_BUFFER_SIZE); WsfCsExit(); mainWsfInit(); AppTerminalInit(); #if defined(HCI_TR_EXACTLE) && (HCI_TR_EXACTLE == 1) + + uint32_t llmemUsed; + + /* Calculate how much memory we will need for the LL initialization */ WsfCsEnter(); - LlInitRtCfg_t llCfg = { .pBbRtCfg = &mainBbRtCfg, - .wlSizeCfg = 4, - .rlSizeCfg = 4, - .plSizeCfg = 4, - .pLlRtCfg = &mainLlRtCfg, - .pFreeMem = WsfHeapGetFreeStartAddress(), - .freeMemAvail = WsfHeapCountAvailable() }; - - memUsed = LlInit(&llCfg); - WsfHeapAlloc(memUsed); + + WsfTraceEnable(FALSE); + + LlInitRtCfg_t llCfg = { + .pBbRtCfg = &mainBbRtCfg, + .wlSizeCfg = 4, + .rlSizeCfg = 4, + .plSizeCfg = 4, + .pLlRtCfg = &mainLlRtCfg, + /* Not significant yet, only being used for memory size requirement calculation. */ + .pFreeMem = WsfHeapGetFreeStartAddress(), + /* Not significant yet, only being used for memory size requirement calculation. */ + .freeMemAvail = WsfHeapCountAvailable() + }; + + llmemUsed = LlInitSetRtCfg(&llCfg); + +#if (WSF_TOKEN_ENABLED == TRUE) || (WSF_TRACE_ENABLED == TRUE) + WsfTraceEnable(TRUE); +#endif + + /* Complete the LL initialization */ + /* Allocate the memory */ + WsfHeapAlloc(llmemUsed); + + /* Set the free memory pointers */ + llCfg.pFreeMem = WsfHeapGetFreeStartAddress(); + llCfg.freeMemAvail = WsfHeapCountAvailable(); + + /* Run the initialization with properly set the free memory pointers */ + if (llmemUsed != LlInit(&llCfg)) { + WSF_ASSERT(0); + } + WsfCsExit(); bdAddr_t bdAddr; diff --git a/Examples/MAX32690/Bluetooth/BLE_otas/main.c b/Examples/MAX32690/Bluetooth/BLE_otas/main.c index 0a9e752ec2a..e1a07935747 100644 --- a/Examples/MAX32690/Bluetooth/BLE_otas/main.c +++ b/Examples/MAX32690/Bluetooth/BLE_otas/main.c @@ -116,16 +116,27 @@ static void mainWsfInit(void) const uint8_t numPools = sizeof(mainPoolDesc) / sizeof(mainPoolDesc[0]); uint16_t memUsed; + /* Initial buffer configuration. */ WsfCsEnter(); - memUsed = WsfBufInit(numPools, mainPoolDesc); + memUsed = WsfBufCalcSize(numPools, mainPoolDesc); WsfHeapAlloc(memUsed); + WsfBufInit(numPools, mainPoolDesc); WsfCsExit(); WsfOsInit(); WsfTimerInit(); #if (WSF_TOKEN_ENABLED == TRUE) || (WSF_TRACE_ENABLED == TRUE) + + WsfCsEnter(); + WsfHeapAlloc(PLATFORM_UART_TERMINAL_BUFFER_SIZE); + memUsed = WsfBufIoUartInit(WsfHeapGetFreeStartAddress(), PLATFORM_UART_TERMINAL_BUFFER_SIZE); + WsfCsExit(); + WsfTraceRegisterHandler(WsfBufIoWrite); WsfTraceEnable(TRUE); + + AppTerminalInit(); + #endif } @@ -209,27 +220,48 @@ int main(void) mainLlRtCfg.defTxPwrLvl = DEFAULT_TX_POWER; #endif - uint32_t memUsed; - WsfCsEnter(); - memUsed = WsfBufIoUartInit(WsfHeapGetFreeStartAddress(), PLATFORM_UART_TERMINAL_BUFFER_SIZE); - WsfHeapAlloc(memUsed); - WsfCsExit(); - mainWsfInit(); - AppTerminalInit(); #if defined(HCI_TR_EXACTLE) && (HCI_TR_EXACTLE == 1) + + uint32_t llmemUsed; + + /* Calculate how much memory we will need for the LL initialization */ WsfCsEnter(); - LlInitRtCfg_t llCfg = { .pBbRtCfg = &mainBbRtCfg, - .wlSizeCfg = 4, - .rlSizeCfg = 4, - .plSizeCfg = 4, - .pLlRtCfg = &mainLlRtCfg, - .pFreeMem = WsfHeapGetFreeStartAddress(), - .freeMemAvail = WsfHeapCountAvailable() }; - - memUsed = LlInit(&llCfg); - WsfHeapAlloc(memUsed); + + WsfTraceEnable(FALSE); + + LlInitRtCfg_t llCfg = { + .pBbRtCfg = &mainBbRtCfg, + .wlSizeCfg = 4, + .rlSizeCfg = 4, + .plSizeCfg = 4, + .pLlRtCfg = &mainLlRtCfg, + /* Not significant yet, only being used for memory size requirement calculation. */ + .pFreeMem = WsfHeapGetFreeStartAddress(), + /* Not significant yet, only being used for memory size requirement calculation. */ + .freeMemAvail = WsfHeapCountAvailable() + }; + + llmemUsed = LlInitSetRtCfg(&llCfg); + +#if (WSF_TOKEN_ENABLED == TRUE) || (WSF_TRACE_ENABLED == TRUE) + WsfTraceEnable(TRUE); +#endif + + /* Complete the LL initialization */ + /* Allocate the memory */ + WsfHeapAlloc(llmemUsed); + + /* Set the free memory pointers */ + llCfg.pFreeMem = WsfHeapGetFreeStartAddress(); + llCfg.freeMemAvail = WsfHeapCountAvailable(); + + /* Run the initialization with properly set the free memory pointers */ + if (llmemUsed != LlInit(&llCfg)) { + WSF_ASSERT(0); + } + WsfCsExit(); bdAddr_t bdAddr; diff --git a/Examples/MAX32690/Bluetooth/BLE_periph/main.c b/Examples/MAX32690/Bluetooth/BLE_periph/main.c index d4b86f7c404..60d68cd354f 100644 --- a/Examples/MAX32690/Bluetooth/BLE_periph/main.c +++ b/Examples/MAX32690/Bluetooth/BLE_periph/main.c @@ -131,8 +131,8 @@ static void mainWsfInit(void) uint32_t memUsed; WsfCsEnter(); - memUsed = WsfBufIoUartInit(WsfHeapGetFreeStartAddress(), PLATFORM_UART_TERMINAL_BUFFER_SIZE); - WsfHeapAlloc(memUsed); + WsfHeapAlloc(PLATFORM_UART_TERMINAL_BUFFER_SIZE); + WsfBufIoUartInit(WsfHeapGetFreeStartAddress(), PLATFORM_UART_TERMINAL_BUFFER_SIZE); WsfCsExit(); #if defined(HCI_TR_EXACTLE) && (HCI_TR_EXACTLE == 1) @@ -151,32 +151,50 @@ static void mainWsfInit(void) const uint8_t numPools = sizeof(mainPoolDesc) / sizeof(mainPoolDesc[0]); + /* Initial buffer configuration. */ WsfCsEnter(); - memUsed = WsfBufInit(numPools, mainPoolDesc); + memUsed = WsfBufCalcSize(numPools, mainPoolDesc); WsfHeapAlloc(memUsed); + WsfBufInit(numPools, mainPoolDesc); WsfCsExit(); WsfOsInit(); WsfTimerInit(); -#if (WSF_TOKEN_ENABLED == TRUE) || (WSF_TRACE_ENABLED == TRUE) - WsfTraceRegisterHandler(WsfBufIoWrite); - WsfTraceEnable(TRUE); -#endif AppTerminalInit(); #if defined(HCI_TR_EXACTLE) && (HCI_TR_EXACTLE == 1) + uint32_t llmemUsed; + + /* Calculate how much memory we will need for the LL initialization */ WsfCsEnter(); - LlInitRtCfg_t llCfg = { .pBbRtCfg = &mainBbRtCfg, - .wlSizeCfg = 4, - .rlSizeCfg = 4, - .plSizeCfg = 4, - .pLlRtCfg = &mainLlRtCfg, - .pFreeMem = WsfHeapGetFreeStartAddress(), - .freeMemAvail = WsfHeapCountAvailable() }; - - memUsed = LlInit(&llCfg); - WsfHeapAlloc(memUsed); + + LlInitRtCfg_t llCfg = { + .pBbRtCfg = &mainBbRtCfg, + .wlSizeCfg = 4, + .rlSizeCfg = 4, + .plSizeCfg = 4, + .pLlRtCfg = &mainLlRtCfg, + /* Not significant yet, only being used for memory size requirement calculation. */ + .pFreeMem = WsfHeapGetFreeStartAddress(), + /* Not significant yet, only being used for memory size requirement calculation. */ + .freeMemAvail = WsfHeapCountAvailable() + }; + + llmemUsed = LlInitSetRtCfg(&llCfg); + + /* Allocate the memory */ + WsfHeapAlloc(llmemUsed); + + /* Set the free memory pointers */ + llCfg.pFreeMem = WsfHeapGetFreeStartAddress(); + llCfg.freeMemAvail = WsfHeapCountAvailable(); + + /* Run the initialization with properly set the free memory pointers */ + if (llmemUsed != LlInitControllerInit(&llCfg)) { + WSF_ASSERT(0); + } + WsfCsExit(); bdAddr_t bdAddr; @@ -184,6 +202,11 @@ static void mainWsfInit(void) LlSetBdAddr((uint8_t *)&bdAddr); #endif +#if (WSF_TOKEN_ENABLED == TRUE) || (WSF_TRACE_ENABLED == TRUE) + WsfTraceRegisterHandler(WsfBufIoWrite); + WsfTraceEnable(TRUE); +#endif + StackInitPeriph(); PeriphStart(); diff --git a/Examples/MAX32690/Bluetooth/RF_Test/main.c b/Examples/MAX32690/Bluetooth/RF_Test/main.c index 4abcaee86c6..a6c78d8b502 100644 --- a/Examples/MAX32690/Bluetooth/RF_Test/main.c +++ b/Examples/MAX32690/Bluetooth/RF_Test/main.c @@ -496,10 +496,11 @@ static void mainWsfInit(void) const uint16_t dataBufSize = 12 + HCI_ISO_DL_MAX_LEN + mainLlRtCfg.maxAclLen + 4 + BB_DATA_PDU_TAILROOM; -/* Use single pool for data buffers. */ + /* Use single pool for data buffers. */ #if (BT_VER > 9) WSF_ASSERT(mainLlRtCfg.maxAclLen == mainLlRtCfg.maxIsoSduLen); #endif + /* Ensure pool buffers are ordered correctly. */ WSF_ASSERT(maxRptBufSize < dataBufSize); @@ -516,8 +517,13 @@ static void mainWsfInit(void) /* Initial buffer configuration. */ uint16_t memUsed; - memUsed = WsfBufInit(numPools, poolDesc); + /* Initial buffer configuration. */ + WsfCsEnter(); + memUsed = WsfBufCalcSize(numPools, poolDesc); WsfHeapAlloc(memUsed); + WsfBufInit(numPools, poolDesc); + WsfCsExit(); + WsfOsInit(); WsfTimerInit(); #if (WSF_TRACE_ENABLED == TRUE) @@ -650,6 +656,7 @@ void vCmdLineTask(void *pvParameters) bufferIndex = 0; memset(inputBuffer, 0x00, 100); prompt(); + } else if (bufferIndex < CMD_LINE_BUF_SIZE) { putchar(tmp); inputBuffer[bufferIndex++] = tmp; @@ -660,6 +667,7 @@ void vCmdLineTask(void *pvParameters) putchar(0x07); fflush(stdout); } + uartReadLen = 1; /* If more characters are ready, process them here */ } while ((MXC_UART_GetRXFIFOAvailable(MXC_UART_GET_UART(CONSOLE_UART)) > 0) && @@ -857,26 +865,48 @@ void printConfigs(void) /*************************************************************************************************/ int main(void) { - uint32_t memUsed; + uint32_t llmemUsed; mainLoadConfiguration(); mainWsfInit(); #if (WSF_TRACE_ENABLED == TRUE) - memUsed = WsfBufIoUartInit(WsfHeapGetFreeStartAddress(), PLATFORM_UART_TERMINAL_BUFFER_SIZE); - WsfHeapAlloc(memUsed); + WsfCsEnter(); + WsfHeapAlloc(PLATFORM_UART_TERMINAL_BUFFER_SIZE); + WsfBufIoUartInit(WsfHeapGetFreeStartAddress(), PLATFORM_UART_TERMINAL_BUFFER_SIZE); + WsfCsExit(); #endif - LlInitRtCfg_t llCfg = { .pBbRtCfg = &mainBbRtCfg, - .wlSizeCfg = 4, - .rlSizeCfg = 4, - .plSizeCfg = 4, - .pLlRtCfg = &mainLlRtCfg, - .pFreeMem = WsfHeapGetFreeStartAddress(), - .freeMemAvail = WsfHeapCountAvailable() }; + /* Calculate how much memory we will need for the LL initialization */ + WsfCsEnter(); + + LlInitRtCfg_t llCfg = { + .pBbRtCfg = &mainBbRtCfg, + .wlSizeCfg = 4, + .rlSizeCfg = 4, + .plSizeCfg = 4, + .pLlRtCfg = &mainLlRtCfg, + /* Not significant yet, only being used for memory size requirement calculation. */ + .pFreeMem = WsfHeapGetFreeStartAddress(), + /* Not significant yet, only being used for memory size requirement calculation. */ + .freeMemAvail = WsfHeapCountAvailable() + }; - memUsed = LlInitControllerInit(&llCfg); - WsfHeapAlloc(memUsed); + llmemUsed = LlInitSetRtCfg(&llCfg); + + /* Allocate the memory */ + WsfHeapAlloc(llmemUsed); + + /* Set the free memory pointers */ + llCfg.pFreeMem = WsfHeapGetFreeStartAddress(); + llCfg.freeMemAvail = WsfHeapCountAvailable(); + + /* Run the initialization with properly set the free memory pointers */ + if (llmemUsed != LlInitControllerInit(&llCfg)) { + WSF_ASSERT(0); + } + + WsfCsExit(); bdAddr_t bdAddr; PalCfgLoadData(PAL_CFG_ID_BD_ADDR, bdAddr, sizeof(bdAddr_t)); diff --git a/Examples/MAX32690/Bluetooth/RF_Test/main.h b/Examples/MAX32690/Bluetooth/RF_Test/main.h index 7f526c7b6cb..2ae688709fe 100644 --- a/Examples/MAX32690/Bluetooth/RF_Test/main.h +++ b/Examples/MAX32690/Bluetooth/RF_Test/main.h @@ -41,6 +41,7 @@ #include "wsf_timer.h" #include "wsf_trace.h" #include "wsf_bufio.h" +#include "wsf_cs.h" #include "bb_ble_sniffer_api.h" #include "pal_bb.h" #include "pal_cfg.h" diff --git a/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/arm_common_tables.h b/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/arm_common_tables.h index 6a9270437fb..8dd1833a2a8 100644 --- a/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/arm_common_tables.h +++ b/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/arm_common_tables.h @@ -32,287 +32,281 @@ #include "arm_math_types.h" #include "dsp/fast_math_functions.h" -#ifdef __cplusplus -extern "C" -{ +#ifdef __cplusplus +extern "C" { #endif - /* Double Precision Float CFFT twiddles */ - extern const uint16_t armBitRevTable[1024]; +/* Double Precision Float CFFT twiddles */ +extern const uint16_t armBitRevTable[1024]; - extern const uint64_t twiddleCoefF64_16[32]; +extern const uint64_t twiddleCoefF64_16[32]; - extern const uint64_t twiddleCoefF64_32[64]; +extern const uint64_t twiddleCoefF64_32[64]; - extern const uint64_t twiddleCoefF64_64[128]; +extern const uint64_t twiddleCoefF64_64[128]; - extern const uint64_t twiddleCoefF64_128[256]; +extern const uint64_t twiddleCoefF64_128[256]; - extern const uint64_t twiddleCoefF64_256[512]; +extern const uint64_t twiddleCoefF64_256[512]; - extern const uint64_t twiddleCoefF64_512[1024]; +extern const uint64_t twiddleCoefF64_512[1024]; - extern const uint64_t twiddleCoefF64_1024[2048]; +extern const uint64_t twiddleCoefF64_1024[2048]; - extern const uint64_t twiddleCoefF64_2048[4096]; +extern const uint64_t twiddleCoefF64_2048[4096]; - extern const uint64_t twiddleCoefF64_4096[8192]; +extern const uint64_t twiddleCoefF64_4096[8192]; - extern const float32_t twiddleCoef_16[32]; +extern const float32_t twiddleCoef_16[32]; - extern const float32_t twiddleCoef_32[64]; +extern const float32_t twiddleCoef_32[64]; - extern const float32_t twiddleCoef_64[128]; +extern const float32_t twiddleCoef_64[128]; - extern const float32_t twiddleCoef_128[256]; +extern const float32_t twiddleCoef_128[256]; - extern const float32_t twiddleCoef_256[512]; +extern const float32_t twiddleCoef_256[512]; - extern const float32_t twiddleCoef_512[1024]; +extern const float32_t twiddleCoef_512[1024]; - extern const float32_t twiddleCoef_1024[2048]; +extern const float32_t twiddleCoef_1024[2048]; - extern const float32_t twiddleCoef_2048[4096]; +extern const float32_t twiddleCoef_2048[4096]; - extern const float32_t twiddleCoef_4096[8192]; - #define twiddleCoef twiddleCoef_4096 +extern const float32_t twiddleCoef_4096[8192]; +#define twiddleCoef twiddleCoef_4096 - /* Q31 */ +/* Q31 */ - extern const q31_t twiddleCoef_16_q31[24]; +extern const q31_t twiddleCoef_16_q31[24]; - extern const q31_t twiddleCoef_32_q31[48]; +extern const q31_t twiddleCoef_32_q31[48]; - extern const q31_t twiddleCoef_64_q31[96]; +extern const q31_t twiddleCoef_64_q31[96]; - extern const q31_t twiddleCoef_128_q31[192]; +extern const q31_t twiddleCoef_128_q31[192]; - extern const q31_t twiddleCoef_256_q31[384]; +extern const q31_t twiddleCoef_256_q31[384]; - extern const q31_t twiddleCoef_512_q31[768]; +extern const q31_t twiddleCoef_512_q31[768]; - extern const q31_t twiddleCoef_1024_q31[1536]; +extern const q31_t twiddleCoef_1024_q31[1536]; - extern const q31_t twiddleCoef_2048_q31[3072]; +extern const q31_t twiddleCoef_2048_q31[3072]; - extern const q31_t twiddleCoef_4096_q31[6144]; +extern const q31_t twiddleCoef_4096_q31[6144]; - extern const q15_t twiddleCoef_16_q15[24]; +extern const q15_t twiddleCoef_16_q15[24]; - extern const q15_t twiddleCoef_32_q15[48]; +extern const q15_t twiddleCoef_32_q15[48]; - extern const q15_t twiddleCoef_64_q15[96]; +extern const q15_t twiddleCoef_64_q15[96]; - extern const q15_t twiddleCoef_128_q15[192]; +extern const q15_t twiddleCoef_128_q15[192]; - extern const q15_t twiddleCoef_256_q15[384]; +extern const q15_t twiddleCoef_256_q15[384]; - extern const q15_t twiddleCoef_512_q15[768]; +extern const q15_t twiddleCoef_512_q15[768]; - extern const q15_t twiddleCoef_1024_q15[1536]; +extern const q15_t twiddleCoef_1024_q15[1536]; - extern const q15_t twiddleCoef_2048_q15[3072]; +extern const q15_t twiddleCoef_2048_q15[3072]; - extern const q15_t twiddleCoef_4096_q15[6144]; +extern const q15_t twiddleCoef_4096_q15[6144]; - /* Double Precision Float RFFT twiddles */ - extern const uint64_t twiddleCoefF64_rfft_32[32]; +/* Double Precision Float RFFT twiddles */ +extern const uint64_t twiddleCoefF64_rfft_32[32]; - extern const uint64_t twiddleCoefF64_rfft_64[64]; +extern const uint64_t twiddleCoefF64_rfft_64[64]; - extern const uint64_t twiddleCoefF64_rfft_128[128]; +extern const uint64_t twiddleCoefF64_rfft_128[128]; - extern const uint64_t twiddleCoefF64_rfft_256[256]; +extern const uint64_t twiddleCoefF64_rfft_256[256]; - extern const uint64_t twiddleCoefF64_rfft_512[512]; +extern const uint64_t twiddleCoefF64_rfft_512[512]; - extern const uint64_t twiddleCoefF64_rfft_1024[1024]; +extern const uint64_t twiddleCoefF64_rfft_1024[1024]; - extern const uint64_t twiddleCoefF64_rfft_2048[2048]; +extern const uint64_t twiddleCoefF64_rfft_2048[2048]; - extern const uint64_t twiddleCoefF64_rfft_4096[4096]; +extern const uint64_t twiddleCoefF64_rfft_4096[4096]; - extern const float32_t twiddleCoef_rfft_32[32]; +extern const float32_t twiddleCoef_rfft_32[32]; - extern const float32_t twiddleCoef_rfft_64[64]; +extern const float32_t twiddleCoef_rfft_64[64]; - extern const float32_t twiddleCoef_rfft_128[128]; +extern const float32_t twiddleCoef_rfft_128[128]; - extern const float32_t twiddleCoef_rfft_256[256]; +extern const float32_t twiddleCoef_rfft_256[256]; - extern const float32_t twiddleCoef_rfft_512[512]; +extern const float32_t twiddleCoef_rfft_512[512]; - extern const float32_t twiddleCoef_rfft_1024[1024]; +extern const float32_t twiddleCoef_rfft_1024[1024]; - extern const float32_t twiddleCoef_rfft_2048[2048]; +extern const float32_t twiddleCoef_rfft_2048[2048]; - extern const float32_t twiddleCoef_rfft_4096[4096]; +extern const float32_t twiddleCoef_rfft_4096[4096]; - /* Double precision floating-point bit reversal tables */ +/* Double precision floating-point bit reversal tables */ - #define ARMBITREVINDEXTABLEF64_16_TABLE_LENGTH ((uint16_t)12) - extern const uint16_t armBitRevIndexTableF64_16[ARMBITREVINDEXTABLEF64_16_TABLE_LENGTH]; +#define ARMBITREVINDEXTABLEF64_16_TABLE_LENGTH ((uint16_t)12) +extern const uint16_t armBitRevIndexTableF64_16[ARMBITREVINDEXTABLEF64_16_TABLE_LENGTH]; - #define ARMBITREVINDEXTABLEF64_32_TABLE_LENGTH ((uint16_t)24) - extern const uint16_t armBitRevIndexTableF64_32[ARMBITREVINDEXTABLEF64_32_TABLE_LENGTH]; +#define ARMBITREVINDEXTABLEF64_32_TABLE_LENGTH ((uint16_t)24) +extern const uint16_t armBitRevIndexTableF64_32[ARMBITREVINDEXTABLEF64_32_TABLE_LENGTH]; - #define ARMBITREVINDEXTABLEF64_64_TABLE_LENGTH ((uint16_t)56) - extern const uint16_t armBitRevIndexTableF64_64[ARMBITREVINDEXTABLEF64_64_TABLE_LENGTH]; +#define ARMBITREVINDEXTABLEF64_64_TABLE_LENGTH ((uint16_t)56) +extern const uint16_t armBitRevIndexTableF64_64[ARMBITREVINDEXTABLEF64_64_TABLE_LENGTH]; - #define ARMBITREVINDEXTABLEF64_128_TABLE_LENGTH ((uint16_t)112) - extern const uint16_t armBitRevIndexTableF64_128[ARMBITREVINDEXTABLEF64_128_TABLE_LENGTH]; +#define ARMBITREVINDEXTABLEF64_128_TABLE_LENGTH ((uint16_t)112) +extern const uint16_t armBitRevIndexTableF64_128[ARMBITREVINDEXTABLEF64_128_TABLE_LENGTH]; - #define ARMBITREVINDEXTABLEF64_256_TABLE_LENGTH ((uint16_t)240) - extern const uint16_t armBitRevIndexTableF64_256[ARMBITREVINDEXTABLEF64_256_TABLE_LENGTH]; +#define ARMBITREVINDEXTABLEF64_256_TABLE_LENGTH ((uint16_t)240) +extern const uint16_t armBitRevIndexTableF64_256[ARMBITREVINDEXTABLEF64_256_TABLE_LENGTH]; - #define ARMBITREVINDEXTABLEF64_512_TABLE_LENGTH ((uint16_t)480) - extern const uint16_t armBitRevIndexTableF64_512[ARMBITREVINDEXTABLEF64_512_TABLE_LENGTH]; +#define ARMBITREVINDEXTABLEF64_512_TABLE_LENGTH ((uint16_t)480) +extern const uint16_t armBitRevIndexTableF64_512[ARMBITREVINDEXTABLEF64_512_TABLE_LENGTH]; - #define ARMBITREVINDEXTABLEF64_1024_TABLE_LENGTH ((uint16_t)992) - extern const uint16_t armBitRevIndexTableF64_1024[ARMBITREVINDEXTABLEF64_1024_TABLE_LENGTH]; +#define ARMBITREVINDEXTABLEF64_1024_TABLE_LENGTH ((uint16_t)992) +extern const uint16_t armBitRevIndexTableF64_1024[ARMBITREVINDEXTABLEF64_1024_TABLE_LENGTH]; - #define ARMBITREVINDEXTABLEF64_2048_TABLE_LENGTH ((uint16_t)1984) - extern const uint16_t armBitRevIndexTableF64_2048[ARMBITREVINDEXTABLEF64_2048_TABLE_LENGTH]; +#define ARMBITREVINDEXTABLEF64_2048_TABLE_LENGTH ((uint16_t)1984) +extern const uint16_t armBitRevIndexTableF64_2048[ARMBITREVINDEXTABLEF64_2048_TABLE_LENGTH]; - #define ARMBITREVINDEXTABLEF64_4096_TABLE_LENGTH ((uint16_t)4032) - extern const uint16_t armBitRevIndexTableF64_4096[ARMBITREVINDEXTABLEF64_4096_TABLE_LENGTH]; - /* floating-point bit reversal tables */ +#define ARMBITREVINDEXTABLEF64_4096_TABLE_LENGTH ((uint16_t)4032) +extern const uint16_t armBitRevIndexTableF64_4096[ARMBITREVINDEXTABLEF64_4096_TABLE_LENGTH]; +/* floating-point bit reversal tables */ - #define ARMBITREVINDEXTABLE_16_TABLE_LENGTH ((uint16_t)20) - extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE_16_TABLE_LENGTH]; +#define ARMBITREVINDEXTABLE_16_TABLE_LENGTH ((uint16_t)20) +extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE_16_TABLE_LENGTH]; - #define ARMBITREVINDEXTABLE_32_TABLE_LENGTH ((uint16_t)48) - extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE_32_TABLE_LENGTH]; +#define ARMBITREVINDEXTABLE_32_TABLE_LENGTH ((uint16_t)48) +extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE_32_TABLE_LENGTH]; - #define ARMBITREVINDEXTABLE_64_TABLE_LENGTH ((uint16_t)56) - extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE_64_TABLE_LENGTH]; +#define ARMBITREVINDEXTABLE_64_TABLE_LENGTH ((uint16_t)56) +extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE_64_TABLE_LENGTH]; - #define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208) - extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH]; +#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208) +extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH]; - #define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440) - extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH]; +#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440) +extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH]; - #define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448) - extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH]; +#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448) +extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH]; - #define ARMBITREVINDEXTABLE_1024_TABLE_LENGTH ((uint16_t)1800) - extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE_1024_TABLE_LENGTH]; +#define ARMBITREVINDEXTABLE_1024_TABLE_LENGTH ((uint16_t)1800) +extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE_1024_TABLE_LENGTH]; - #define ARMBITREVINDEXTABLE_2048_TABLE_LENGTH ((uint16_t)3808) - extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE_2048_TABLE_LENGTH]; +#define ARMBITREVINDEXTABLE_2048_TABLE_LENGTH ((uint16_t)3808) +extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE_2048_TABLE_LENGTH]; - #define ARMBITREVINDEXTABLE_4096_TABLE_LENGTH ((uint16_t)4032) - extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE_4096_TABLE_LENGTH]; +#define ARMBITREVINDEXTABLE_4096_TABLE_LENGTH ((uint16_t)4032) +extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE_4096_TABLE_LENGTH]; +/* fixed-point bit reversal tables */ - /* fixed-point bit reversal tables */ +#define ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH ((uint16_t)12) +extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH]; - #define ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH ((uint16_t)12) - extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH]; +#define ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH ((uint16_t)24) +extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH]; - #define ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH ((uint16_t)24) - extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH]; +#define ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH ((uint16_t)56) +extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH]; - #define ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH ((uint16_t)56) - extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH]; +#define ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH ((uint16_t)112) +extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH]; - #define ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH ((uint16_t)112) - extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH]; +#define ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH ((uint16_t)240) +extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH]; - #define ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH ((uint16_t)240) - extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH]; +#define ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH ((uint16_t)480) +extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH]; - #define ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH ((uint16_t)480) - extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH]; +#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992) +extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH]; - #define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992) - extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH]; +#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984) +extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH]; - #define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984) - extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH]; +#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032) +extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH]; - #define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032) - extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH]; +extern const float32_t realCoefA[8192]; +extern const float32_t realCoefB[8192]; - extern const float32_t realCoefA[8192]; - extern const float32_t realCoefB[8192]; +extern const q31_t realCoefAQ31[8192]; +extern const q31_t realCoefBQ31[8192]; - extern const q31_t realCoefAQ31[8192]; - extern const q31_t realCoefBQ31[8192]; +extern const q15_t realCoefAQ15[8192]; +extern const q15_t realCoefBQ15[8192]; - extern const q15_t realCoefAQ15[8192]; - extern const q15_t realCoefBQ15[8192]; +extern const float32_t Weights_128[256]; +extern const float32_t cos_factors_128[128]; - extern const float32_t Weights_128[256]; - extern const float32_t cos_factors_128[128]; +extern const float32_t Weights_512[1024]; +extern const float32_t cos_factors_512[512]; - extern const float32_t Weights_512[1024]; - extern const float32_t cos_factors_512[512]; +extern const float32_t Weights_2048[4096]; +extern const float32_t cos_factors_2048[2048]; - extern const float32_t Weights_2048[4096]; - extern const float32_t cos_factors_2048[2048]; +extern const float32_t Weights_8192[16384]; +extern const float32_t cos_factors_8192[8192]; - extern const float32_t Weights_8192[16384]; - extern const float32_t cos_factors_8192[8192]; +extern const q15_t WeightsQ15_128[256]; +extern const q15_t cos_factorsQ15_128[128]; - extern const q15_t WeightsQ15_128[256]; - extern const q15_t cos_factorsQ15_128[128]; +extern const q15_t WeightsQ15_512[1024]; +extern const q15_t cos_factorsQ15_512[512]; - extern const q15_t WeightsQ15_512[1024]; - extern const q15_t cos_factorsQ15_512[512]; +extern const q15_t WeightsQ15_2048[4096]; +extern const q15_t cos_factorsQ15_2048[2048]; - extern const q15_t WeightsQ15_2048[4096]; - extern const q15_t cos_factorsQ15_2048[2048]; +extern const q15_t WeightsQ15_8192[16384]; +extern const q15_t cos_factorsQ15_8192[8192]; - extern const q15_t WeightsQ15_8192[16384]; - extern const q15_t cos_factorsQ15_8192[8192]; +extern const q31_t WeightsQ31_128[256]; +extern const q31_t cos_factorsQ31_128[128]; - extern const q31_t WeightsQ31_128[256]; - extern const q31_t cos_factorsQ31_128[128]; +extern const q31_t WeightsQ31_512[1024]; +extern const q31_t cos_factorsQ31_512[512]; - extern const q31_t WeightsQ31_512[1024]; - extern const q31_t cos_factorsQ31_512[512]; +extern const q31_t WeightsQ31_2048[4096]; +extern const q31_t cos_factorsQ31_2048[2048]; - extern const q31_t WeightsQ31_2048[4096]; - extern const q31_t cos_factorsQ31_2048[2048]; +extern const q31_t WeightsQ31_8192[16384]; +extern const q31_t cos_factorsQ31_8192[8192]; - extern const q31_t WeightsQ31_8192[16384]; - extern const q31_t cos_factorsQ31_8192[8192]; +extern const q15_t armRecipTableQ15[64]; +extern const q31_t armRecipTableQ31[64]; - extern const q15_t armRecipTableQ15[64]; +/* Tables for Fast Math Sine and Cosine */ +extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1]; - extern const q31_t armRecipTableQ31[64]; +extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1]; - /* Tables for Fast Math Sine and Cosine */ - extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1]; +extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1]; - extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1]; +/* Accurate scalar sqrt */ +extern const q31_t sqrt_initial_lut_q31[32]; - extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1]; - - - /* Accurate scalar sqrt */ - extern const q31_t sqrt_initial_lut_q31[32]; - - extern const q15_t sqrt_initial_lut_q15[16]; +extern const q15_t sqrt_initial_lut_q15[16]; #if (defined(ARM_MATH_MVEI) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE) - extern const q15_t sqrtTable_Q15[256]; - extern const q31_t sqrtTable_Q31[256]; - extern const unsigned char hwLUT[256]; -#endif +extern const q15_t sqrtTable_Q15[256]; +extern const q31_t sqrtTable_Q31[256]; +extern const unsigned char hwLUT[256]; +#endif #if (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE) - extern const float32_t exp_tab[8]; - extern const float32_t __logf_lut_f32[8]; -#endif - +extern const float32_t exp_tab[8]; +extern const float32_t __logf_lut_f32[8]; +#endif -#ifdef __cplusplus +#ifdef __cplusplus } #endif #endif /* ARM_COMMON_TABLES_H */ - diff --git a/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/arm_common_tables_f16.h b/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/arm_common_tables_f16.h old mode 100755 new mode 100644 index c84a766adf6..e94aec547a6 --- a/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/arm_common_tables_f16.h +++ b/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/arm_common_tables_f16.h @@ -31,65 +31,58 @@ #include "arm_math_types_f16.h" -#ifdef __cplusplus -extern "C" -{ +#ifdef __cplusplus +extern "C" { #endif +/* F16 */ +#if !defined(__CC_ARM) && defined(ARM_FLOAT16_SUPPORTED) +extern const float16_t twiddleCoefF16_16[32]; - /* F16 */ - #if !defined(__CC_ARM) && defined(ARM_FLOAT16_SUPPORTED) - extern const float16_t twiddleCoefF16_16[32]; +extern const float16_t twiddleCoefF16_32[64]; - extern const float16_t twiddleCoefF16_32[64]; +extern const float16_t twiddleCoefF16_64[128]; - extern const float16_t twiddleCoefF16_64[128]; +extern const float16_t twiddleCoefF16_128[256]; - extern const float16_t twiddleCoefF16_128[256]; +extern const float16_t twiddleCoefF16_256[512]; - extern const float16_t twiddleCoefF16_256[512]; +extern const float16_t twiddleCoefF16_512[1024]; - extern const float16_t twiddleCoefF16_512[1024]; +extern const float16_t twiddleCoefF16_1024[2048]; - extern const float16_t twiddleCoefF16_1024[2048]; +extern const float16_t twiddleCoefF16_2048[4096]; - extern const float16_t twiddleCoefF16_2048[4096]; +extern const float16_t twiddleCoefF16_4096[8192]; +#define twiddleCoefF16 twiddleCoefF16_4096 - extern const float16_t twiddleCoefF16_4096[8192]; - #define twiddleCoefF16 twiddleCoefF16_4096 - - - extern const float16_t twiddleCoefF16_rfft_32[32]; +extern const float16_t twiddleCoefF16_rfft_32[32]; - extern const float16_t twiddleCoefF16_rfft_64[64]; +extern const float16_t twiddleCoefF16_rfft_64[64]; - extern const float16_t twiddleCoefF16_rfft_128[128]; +extern const float16_t twiddleCoefF16_rfft_128[128]; - extern const float16_t twiddleCoefF16_rfft_256[256]; +extern const float16_t twiddleCoefF16_rfft_256[256]; - extern const float16_t twiddleCoefF16_rfft_512[512]; +extern const float16_t twiddleCoefF16_rfft_512[512]; - extern const float16_t twiddleCoefF16_rfft_1024[1024]; +extern const float16_t twiddleCoefF16_rfft_1024[1024]; - extern const float16_t twiddleCoefF16_rfft_2048[2048]; +extern const float16_t twiddleCoefF16_rfft_2048[2048]; - extern const float16_t twiddleCoefF16_rfft_4096[4096]; +extern const float16_t twiddleCoefF16_rfft_4096[4096]; - #endif /* ARMAC5 */ - +#endif /* ARMAC5 */ #if !defined(__CC_ARM) && defined(ARM_FLOAT16_SUPPORTED) #if (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE) - extern const float16_t exp_tab_f16[8]; - extern const float16_t __logf_lut_f16[8]; +extern const float16_t exp_tab_f16[8]; +extern const float16_t __logf_lut_f16[8]; +#endif #endif -#endif - -#ifdef __cplusplus +#ifdef __cplusplus } #endif #endif /* _ARM_COMMON_TABLES_F16_H */ - - diff --git a/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/arm_const_structs.h b/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/arm_const_structs.h index 32c1a436e67..e561bc28f3b 100644 --- a/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/arm_const_structs.h +++ b/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/arm_const_structs.h @@ -34,53 +34,51 @@ #include "arm_common_tables.h" #include "dsp/transform_functions.h" -#ifdef __cplusplus -extern "C" -{ +#ifdef __cplusplus +extern "C" { #endif - extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len16; - extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len32; - extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len64; - extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len128; - extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len256; - extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len512; - extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len1024; - extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len2048; - extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len4096; +extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len16; +extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len32; +extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len64; +extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len128; +extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len256; +extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len512; +extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len1024; +extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len2048; +extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len4096; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096; +extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16; +extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32; +extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64; +extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128; +extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256; +extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512; +extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024; +extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048; +extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096; +extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16; +extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32; +extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64; +extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128; +extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256; +extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512; +extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024; +extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048; +extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096; +extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16; +extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32; +extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64; +extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128; +extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256; +extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512; +extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024; +extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048; +extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096; -#ifdef __cplusplus +#ifdef __cplusplus } #endif #endif - diff --git a/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/arm_const_structs_f16.h b/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/arm_const_structs_f16.h old mode 100755 new mode 100644 index 3a520b6b94f..aab7cf79fc8 --- a/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/arm_const_structs_f16.h +++ b/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/arm_const_structs_f16.h @@ -35,24 +35,23 @@ #include "arm_common_tables_f16.h" #include "dsp/transform_functions_f16.h" -#ifdef __cplusplus -extern "C" -{ +#ifdef __cplusplus +extern "C" { #endif #if !defined(__CC_ARM) && defined(ARM_FLOAT16_SUPPORTED) - extern const arm_cfft_instance_f16 arm_cfft_sR_f16_len16; - extern const arm_cfft_instance_f16 arm_cfft_sR_f16_len32; - extern const arm_cfft_instance_f16 arm_cfft_sR_f16_len64; - extern const arm_cfft_instance_f16 arm_cfft_sR_f16_len128; - extern const arm_cfft_instance_f16 arm_cfft_sR_f16_len256; - extern const arm_cfft_instance_f16 arm_cfft_sR_f16_len512; - extern const arm_cfft_instance_f16 arm_cfft_sR_f16_len1024; - extern const arm_cfft_instance_f16 arm_cfft_sR_f16_len2048; - extern const arm_cfft_instance_f16 arm_cfft_sR_f16_len4096; +extern const arm_cfft_instance_f16 arm_cfft_sR_f16_len16; +extern const arm_cfft_instance_f16 arm_cfft_sR_f16_len32; +extern const arm_cfft_instance_f16 arm_cfft_sR_f16_len64; +extern const arm_cfft_instance_f16 arm_cfft_sR_f16_len128; +extern const arm_cfft_instance_f16 arm_cfft_sR_f16_len256; +extern const arm_cfft_instance_f16 arm_cfft_sR_f16_len512; +extern const arm_cfft_instance_f16 arm_cfft_sR_f16_len1024; +extern const arm_cfft_instance_f16 arm_cfft_sR_f16_len2048; +extern const arm_cfft_instance_f16 arm_cfft_sR_f16_len4096; #endif -#ifdef __cplusplus +#ifdef __cplusplus } #endif diff --git a/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/arm_helium_utils.h b/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/arm_helium_utils.h old mode 100755 new mode 100644 index 65167678261..10dac14d5b2 --- a/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/arm_helium_utils.h +++ b/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/arm_helium_utils.h @@ -29,20 +29,18 @@ #ifndef ARM_UTILS_HELIUM_H_ #define ARM_UTILS_HELIUM_H_ - -#ifdef __cplusplus -extern "C" -{ +#ifdef __cplusplus +extern "C" { #endif /*************************************** Definitions available for MVEF and MVEI ***************************************/ -#if (defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEF) || defined(ARM_MATH_MVEI)) && !defined(ARM_MATH_AUTOVECTORIZE) - -#define INACTIVELANE 0 /* inactive lane content */ +#if (defined(ARM_MATH_HELIUM) || defined(ARM_MATH_MVEF) || defined(ARM_MATH_MVEI)) && \ + !defined(ARM_MATH_AUTOVECTORIZE) +#define INACTIVELANE 0 /* inactive lane content */ #endif /* defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEF) || defined(ARM_MATH_MVEI) */ @@ -51,70 +49,63 @@ Definitions available for MVEF and MVEI Definitions available for MVEF only ***************************************/ -#if (defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEF)) && !defined(ARM_MATH_AUTOVECTORIZE) +#if (defined(ARM_MATH_HELIUM) || defined(ARM_MATH_MVEF)) && !defined(ARM_MATH_AUTOVECTORIZE) __STATIC_FORCEINLINE float32_t vecAddAcrossF32Mve(float32x4_t in) { float32_t acc; - acc = vgetq_lane(in, 0) + vgetq_lane(in, 1) + - vgetq_lane(in, 2) + vgetq_lane(in, 3); + acc = vgetq_lane(in, 0) + vgetq_lane(in, 1) + vgetq_lane(in, 2) + vgetq_lane(in, 3); return acc; } - - - /* newton initial guess */ -#define INVSQRT_MAGIC_F32 0x5f3759df -#define INV_NEWTON_INIT_F32 0x7EF127EA - - -#define INVSQRT_NEWTON_MVE_F32(invSqrt, xHalf, xStart)\ -{ \ - float32x4_t tmp; \ - \ - /* tmp = xhalf * x * x */ \ - tmp = vmulq(xStart, xStart); \ - tmp = vmulq(tmp, xHalf); \ - /* (1.5f - xhalf * x * x) */ \ - tmp = vsubq(vdupq_n_f32(1.5f), tmp); \ - /* x = x*(1.5f-xhalf*x*x); */ \ - invSqrt = vmulq(tmp, xStart); \ -} +#define INVSQRT_MAGIC_F32 0x5f3759df +#define INV_NEWTON_INIT_F32 0x7EF127EA + +#define INVSQRT_NEWTON_MVE_F32(invSqrt, xHalf, xStart) \ + { \ + float32x4_t tmp; \ + \ + /* tmp = xhalf * x * x */ \ + tmp = vmulq(xStart, xStart); \ + tmp = vmulq(tmp, xHalf); \ + /* (1.5f - xhalf * x * x) */ \ + tmp = vsubq(vdupq_n_f32(1.5f), tmp); \ + /* x = x*(1.5f-xhalf*x*x); */ \ + invSqrt = vmulq(tmp, xStart); \ + } #endif /* defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEF) */ - /*************************************** Definitions available for f16 datatype with HW acceleration only ***************************************/ #if defined(ARM_FLOAT16_SUPPORTED) -#if defined (ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) __STATIC_FORCEINLINE float16_t vecAddAcrossF16Mve(float16x8_t in) { float16x8_t tmpVec; _Float16 acc; - tmpVec = (float16x8_t) vrev32q_s16((int16x8_t) in); + tmpVec = (float16x8_t)vrev32q_s16((int16x8_t)in); in = vaddq_f16(tmpVec, in); - tmpVec = (float16x8_t) vrev64q_s32((int32x4_t) in); + tmpVec = (float16x8_t)vrev64q_s32((int32x4_t)in); in = vaddq_f16(tmpVec, in); acc = (_Float16)vgetq_lane_f16(in, 0) + (_Float16)vgetq_lane_f16(in, 4); return acc; } -__STATIC_FORCEINLINE float16x8_t __mve_cmplx_sum_intra_vec_f16( - float16x8_t vecIn) +__STATIC_FORCEINLINE float16x8_t __mve_cmplx_sum_intra_vec_f16(float16x8_t vecIn) { - float16x8_t vecTmp, vecOut; - uint32_t tmp = 0; + float16x8_t vecTmp, vecOut; + uint32_t tmp = 0; - vecTmp = (float16x8_t) vrev64q_s32((int32x4_t) vecIn); + vecTmp = (float16x8_t)vrev64q_s32((int32x4_t)vecIn); // TO TRACK : using canonical addition leads to unefficient code generation for f16 // vecTmp = vecTmp + vecAccCpx0; /* @@ -127,7 +118,7 @@ __STATIC_FORCEINLINE float16x8_t __mve_cmplx_sum_intra_vec_f16( /* * shift left, random tmp insertion in bottom */ - vecOut = vreinterpretq_f16_s32(vshlcq_s32(vreinterpretq_s32_f16(vecOut) , &tmp, 32)); + vecOut = vreinterpretq_f16_s32(vshlcq_s32(vreinterpretq_s32_f16(vecOut), &tmp, 32)); /* * Compute: * DONTCARE | DONTCARE | re0+re1+re0+re1 |im0+im1+im0+im1 @@ -141,56 +132,51 @@ __STATIC_FORCEINLINE float16x8_t __mve_cmplx_sum_intra_vec_f16( return vecOut; } +#define mve_cmplx_sum_intra_r_i_f16(vec, Re, Im) \ + { \ + float16x8_t vecOut = __mve_cmplx_sum_intra_vec_f16(vec); \ + Re = vgetq_lane(vecOut, 4); \ + Im = vgetq_lane(vecOut, 5); \ + } -#define mve_cmplx_sum_intra_r_i_f16(vec, Re, Im) \ -{ \ - float16x8_t vecOut = __mve_cmplx_sum_intra_vec_f16(vec); \ - Re = vgetq_lane(vecOut, 4); \ - Im = vgetq_lane(vecOut, 5); \ -} - -__STATIC_FORCEINLINE void mve_cmplx_sum_intra_vec_f16( - float16x8_t vecIn, - float16_t *pOut) +__STATIC_FORCEINLINE void mve_cmplx_sum_intra_vec_f16(float16x8_t vecIn, float16_t *pOut) { - float16x8_t vecOut = __mve_cmplx_sum_intra_vec_f16(vecIn); + float16x8_t vecOut = __mve_cmplx_sum_intra_vec_f16(vecIn); /* * Cmplx sum is in 4rd & 5th f16 elt * use 32-bit extraction */ - *(float32_t *) pOut = ((float32x4_t) vecOut)[2]; + *(float32_t *)pOut = ((float32x4_t)vecOut)[2]; } - -#define INVSQRT_MAGIC_F16 0x59ba /* ( 0x1ba = 0x3759df >> 13) */ +#define INVSQRT_MAGIC_F16 0x59ba /* ( 0x1ba = 0x3759df >> 13) */ /* canonical version of INVSQRT_NEWTON_MVE_F16 leads to bad performance */ -#define INVSQRT_NEWTON_MVE_F16(invSqrt, xHalf, xStart) \ -{ \ - float16x8_t tmp; \ - \ - /* tmp = xhalf * x * x */ \ - tmp = vmulq(xStart, xStart); \ - tmp = vmulq(tmp, xHalf); \ - /* (1.5f - xhalf * x * x) */ \ - tmp = vsubq(vdupq_n_f16((float16_t)1.5), tmp); \ - /* x = x*(1.5f-xhalf*x*x); */ \ - invSqrt = vmulq(tmp, xStart); \ -} +#define INVSQRT_NEWTON_MVE_F16(invSqrt, xHalf, xStart) \ + { \ + float16x8_t tmp; \ + \ + /* tmp = xhalf * x * x */ \ + tmp = vmulq(xStart, xStart); \ + tmp = vmulq(tmp, xHalf); \ + /* (1.5f - xhalf * x * x) */ \ + tmp = vsubq(vdupq_n_f16((float16_t)1.5), tmp); \ + /* x = x*(1.5f-xhalf*x*x); */ \ + invSqrt = vmulq(tmp, xStart); \ + } #endif -#endif +#endif /*************************************** Definitions available for MVEI and MVEF only ***************************************/ -#if (defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEF) || defined(ARM_MATH_MVEI)) && !defined(ARM_MATH_AUTOVECTORIZE) +#if (defined(ARM_MATH_HELIUM) || defined(ARM_MATH_MVEF) || defined(ARM_MATH_MVEI)) && \ + !defined(ARM_MATH_AUTOVECTORIZE) /* Following functions are used to transpose matrix in f32 and q31 cases */ -__STATIC_INLINE arm_status arm_mat_trans_32bit_2x2_mve( - uint32_t * pDataSrc, - uint32_t * pDataDest) +__STATIC_INLINE arm_status arm_mat_trans_32bit_2x2_mve(uint32_t *pDataSrc, uint32_t *pDataDest) { static const uint32x4_t vecOffs = { 0, 2, 1, 3 }; /* @@ -205,12 +191,10 @@ __STATIC_INLINE arm_status arm_mat_trans_32bit_2x2_mve( return (ARM_MATH_SUCCESS); } -__STATIC_INLINE arm_status arm_mat_trans_32bit_3x3_mve( - uint32_t * pDataSrc, - uint32_t * pDataDest) +__STATIC_INLINE arm_status arm_mat_trans_32bit_3x3_mve(uint32_t *pDataSrc, uint32_t *pDataDest) { - const uint32x4_t vecOffs1 = { 0, 3, 6, 1}; - const uint32x4_t vecOffs2 = { 4, 7, 2, 5}; + const uint32x4_t vecOffs1 = { 0, 3, 6, 1 }; + const uint32x4_t vecOffs2 = { 4, 7, 2, 5 }; /* * * | 0 1 2 | | 0 3 6 | 4 x 32 flattened version | 0 3 6 1 | @@ -218,8 +202,8 @@ __STATIC_INLINE arm_status arm_mat_trans_32bit_3x3_mve( * | 6 7 8 | | 2 5 8 | (row major) | 8 . . . | * */ - uint32x4_t vecIn1 = vldrwq_u32((uint32_t const *) pDataSrc); - uint32x4_t vecIn2 = vldrwq_u32((uint32_t const *) &pDataSrc[4]); + uint32x4_t vecIn1 = vldrwq_u32((uint32_t const *)pDataSrc); + uint32x4_t vecIn2 = vldrwq_u32((uint32_t const *)&pDataSrc[4]); vstrwq_scatter_shifted_offset_u32(pDataDest, vecOffs1, vecIn1); vstrwq_scatter_shifted_offset_u32(pDataDest, vecOffs2, vecIn2); @@ -229,7 +213,7 @@ __STATIC_INLINE arm_status arm_mat_trans_32bit_3x3_mve( return (ARM_MATH_SUCCESS); } -__STATIC_INLINE arm_status arm_mat_trans_32bit_4x4_mve(uint32_t * pDataSrc, uint32_t * pDataDest) +__STATIC_INLINE arm_status arm_mat_trans_32bit_4x4_mve(uint32_t *pDataSrc, uint32_t *pDataDest) { /* * 4x4 Matrix transposition @@ -243,7 +227,7 @@ __STATIC_INLINE arm_status arm_mat_trans_32bit_4x4_mve(uint32_t * pDataSrc, uint uint32x4x4_t vecIn; - vecIn = vld4q((uint32_t const *) pDataSrc); + vecIn = vld4q((uint32_t const *)pDataSrc); vstrwq(pDataDest, vecIn.val[0]); pDataDest += 4; vstrwq(pDataDest, vecIn.val[1]); @@ -255,16 +239,12 @@ __STATIC_INLINE arm_status arm_mat_trans_32bit_4x4_mve(uint32_t * pDataSrc, uint return (ARM_MATH_SUCCESS); } - -__STATIC_INLINE arm_status arm_mat_trans_32bit_generic_mve( - uint16_t srcRows, - uint16_t srcCols, - uint32_t * pDataSrc, - uint32_t * pDataDest) +__STATIC_INLINE arm_status arm_mat_trans_32bit_generic_mve(uint16_t srcRows, uint16_t srcCols, + uint32_t *pDataSrc, uint32_t *pDataDest) { uint32x4_t vecOffs; - uint32_t i; - uint32_t blkCnt; + uint32_t i; + uint32_t blkCnt; uint32_t const *pDataC; uint32_t *pDataDestR; uint32x4_t vecIn; @@ -273,16 +253,14 @@ __STATIC_INLINE arm_status arm_mat_trans_32bit_generic_mve( vecOffs = vecOffs * srcCols; i = srcCols; - do - { - pDataC = (uint32_t const *) pDataSrc; + do { + pDataC = (uint32_t const *)pDataSrc; pDataDestR = pDataDest; blkCnt = srcRows >> 2; - while (blkCnt > 0U) - { + while (blkCnt > 0U) { vecIn = vldrwq_gather_shifted_offset_u32(pDataC, vecOffs); - vstrwq(pDataDestR, vecIn); + vstrwq(pDataDestR, vecIn); pDataDestR += 4; pDataC = pDataC + srcCols * 4; /* @@ -295,8 +273,7 @@ __STATIC_INLINE arm_status arm_mat_trans_32bit_generic_mve( * tail */ blkCnt = srcRows & 3; - if (blkCnt > 0U) - { + if (blkCnt > 0U) { mve_pred16_t p0 = vctp32q(blkCnt); vecIn = vldrwq_gather_shifted_offset_u32(pDataC, vecOffs); vstrwq_p(pDataDestR, vecIn, p0); @@ -304,34 +281,28 @@ __STATIC_INLINE arm_status arm_mat_trans_32bit_generic_mve( pDataSrc += 1; pDataDest += srcRows; - } - while (--i); + } while (--i); return (ARM_MATH_SUCCESS); } -__STATIC_INLINE arm_status arm_mat_cmplx_trans_32bit( - uint16_t srcRows, - uint16_t srcCols, - uint32_t *pDataSrc, - uint16_t dstRows, - uint16_t dstCols, - uint32_t *pDataDest) +__STATIC_INLINE arm_status arm_mat_cmplx_trans_32bit(uint16_t srcRows, uint16_t srcCols, + uint32_t *pDataSrc, uint16_t dstRows, + uint16_t dstCols, uint32_t *pDataDest) { - uint32_t i; + uint32_t i; uint32_t const *pDataC; - uint32_t *pDataRow; - uint32_t *pDataDestR, *pDataDestRow; - uint32x4_t vecOffsRef, vecOffsCur; - uint32_t blkCnt; - uint32x4_t vecIn; + uint32_t *pDataRow; + uint32_t *pDataDestR, *pDataDestRow; + uint32x4_t vecOffsRef, vecOffsCur; + uint32_t blkCnt; + uint32x4_t vecIn; #ifdef ARM_MATH_MATRIX_CHECK /* * Check for matrix mismatch condition */ - if ((srcRows != dstCols) || (srcCols != dstRows)) - { + if ((srcRows != dstCols) || (srcCols != dstRows)) { /* * Set status as ARM_MATH_SIZE_MISMATCH */ @@ -352,31 +323,28 @@ __STATIC_INLINE arm_status arm_mat_cmplx_trans_32bit( pDataRow = pDataSrc; pDataDestRow = pDataDest; i = srcCols; - do - { - pDataC = (uint32_t const *) pDataRow; + do { + pDataC = (uint32_t const *)pDataRow; pDataDestR = pDataDestRow; vecOffsCur = vecOffsRef; blkCnt = (srcRows * CMPLX_DIM) >> 2; - while (blkCnt > 0U) - { + while (blkCnt > 0U) { vecIn = vldrwq_gather_shifted_offset(pDataC, vecOffsCur); - vstrwq(pDataDestR, vecIn); + vstrwq(pDataDestR, vecIn); pDataDestR += 4; vecOffsCur = vaddq(vecOffsCur, (srcCols << 2)); /* * Decrement the blockSize loop counter */ - blkCnt--; + blkCnt--; } /* * tail * (will be merged thru tail predication) */ blkCnt = (srcRows * CMPLX_DIM) & 3; - if (blkCnt > 0U) - { + if (blkCnt > 0U) { mve_pred16_t p0 = vctp32q(blkCnt); vecIn = vldrwq_gather_shifted_offset(pDataC, vecOffsCur); vstrwq_p(pDataDestR, vecIn, p0); @@ -384,13 +352,12 @@ __STATIC_INLINE arm_status arm_mat_cmplx_trans_32bit( pDataRow += CMPLX_DIM; pDataDestRow += (srcRows * CMPLX_DIM); - } - while (--i); + } while (--i); return (ARM_MATH_SUCCESS); } -__STATIC_INLINE arm_status arm_mat_trans_16bit_2x2(uint16_t * pDataSrc, uint16_t * pDataDest) +__STATIC_INLINE arm_status arm_mat_trans_16bit_2x2(uint16_t *pDataSrc, uint16_t *pDataDest) { pDataDest[0] = pDataSrc[0]; pDataDest[3] = pDataSrc[3]; @@ -400,11 +367,11 @@ __STATIC_INLINE arm_status arm_mat_trans_16bit_2x2(uint16_t * pDataSrc, uint16_t return (ARM_MATH_SUCCESS); } -__STATIC_INLINE arm_status arm_mat_trans_16bit_3x3_mve(uint16_t * pDataSrc, uint16_t * pDataDest) +__STATIC_INLINE arm_status arm_mat_trans_16bit_3x3_mve(uint16_t *pDataSrc, uint16_t *pDataDest) { static const uint16_t stridesTr33[8] = { 0, 3, 6, 1, 4, 7, 2, 5 }; - uint16x8_t vecOffs1; - uint16x8_t vecIn1; + uint16x8_t vecOffs1; + uint16x8_t vecIn1; /* * * | 0 1 2 | | 0 3 6 | 8 x 16 flattened version | 0 3 6 1 4 7 2 5 | @@ -412,8 +379,8 @@ __STATIC_INLINE arm_status arm_mat_trans_16bit_3x3_mve(uint16_t * pDataSrc, uint * | 6 7 8 | | 2 5 8 | (row major) * */ - vecOffs1 = vldrhq_u16((uint16_t const *) stridesTr33); - vecIn1 = vldrhq_u16((uint16_t const *) pDataSrc); + vecOffs1 = vldrhq_u16((uint16_t const *)stridesTr33); + vecIn1 = vldrhq_u16((uint16_t const *)pDataSrc); vstrhq_scatter_shifted_offset_u16(pDataDest, vecOffs1, vecIn1); @@ -422,14 +389,13 @@ __STATIC_INLINE arm_status arm_mat_trans_16bit_3x3_mve(uint16_t * pDataSrc, uint return (ARM_MATH_SUCCESS); } - -__STATIC_INLINE arm_status arm_mat_trans_16bit_4x4_mve(uint16_t * pDataSrc, uint16_t * pDataDest) +__STATIC_INLINE arm_status arm_mat_trans_16bit_4x4_mve(uint16_t *pDataSrc, uint16_t *pDataDest) { static const uint16_t stridesTr44_1[8] = { 0, 4, 8, 12, 1, 5, 9, 13 }; static const uint16_t stridesTr44_2[8] = { 2, 6, 10, 14, 3, 7, 11, 15 }; - uint16x8_t vecOffs1, vecOffs2; - uint16x8_t vecIn1, vecIn2; - uint16_t const * pDataSrcVec = (uint16_t const *) pDataSrc; + uint16x8_t vecOffs1, vecOffs2; + uint16x8_t vecIn1, vecIn2; + uint16_t const *pDataSrcVec = (uint16_t const *)pDataSrc; /* * 4x4 Matrix transposition @@ -440,8 +406,8 @@ __STATIC_INLINE arm_status arm_mat_trans_16bit_4x4_mve(uint16_t * pDataSrc, uint * | 12 13 14 15 | | 3 7 11 15 | */ - vecOffs1 = vldrhq_u16((uint16_t const *) stridesTr44_1); - vecOffs2 = vldrhq_u16((uint16_t const *) stridesTr44_2); + vecOffs1 = vldrhq_u16((uint16_t const *)stridesTr44_1); + vecOffs2 = vldrhq_u16((uint16_t const *)stridesTr44_2); vecIn1 = vldrhq_u16(pDataSrcVec); pDataSrcVec += 8; vecIn2 = vldrhq_u16(pDataSrcVec); @@ -449,39 +415,31 @@ __STATIC_INLINE arm_status arm_mat_trans_16bit_4x4_mve(uint16_t * pDataSrc, uint vstrhq_scatter_shifted_offset_u16(pDataDest, vecOffs1, vecIn1); vstrhq_scatter_shifted_offset_u16(pDataDest, vecOffs2, vecIn2); - return (ARM_MATH_SUCCESS); } - - -__STATIC_INLINE arm_status arm_mat_trans_16bit_generic( - uint16_t srcRows, - uint16_t srcCols, - uint16_t * pDataSrc, - uint16_t * pDataDest) +__STATIC_INLINE arm_status arm_mat_trans_16bit_generic(uint16_t srcRows, uint16_t srcCols, + uint16_t *pDataSrc, uint16_t *pDataDest) { - uint16x8_t vecOffs; - uint32_t i; - uint32_t blkCnt; + uint16x8_t vecOffs; + uint32_t i; + uint32_t blkCnt; uint16_t const *pDataC; - uint16_t *pDataDestR; - uint16x8_t vecIn; + uint16_t *pDataDestR; + uint16x8_t vecIn; vecOffs = vidupq_u16((uint32_t)0, 1); vecOffs = vecOffs * srcCols; i = srcCols; - while(i > 0U) - { - pDataC = (uint16_t const *) pDataSrc; + while (i > 0U) { + pDataC = (uint16_t const *)pDataSrc; pDataDestR = pDataDest; blkCnt = srcRows >> 3; - while (blkCnt > 0U) - { + while (blkCnt > 0U) { vecIn = vldrhq_gather_shifted_offset_u16(pDataC, vecOffs); - vstrhq_u16(pDataDestR, vecIn); + vstrhq_u16(pDataDestR, vecIn); pDataDestR += 8; pDataC = pDataC + srcCols * 8; /* @@ -494,8 +452,7 @@ __STATIC_INLINE arm_status arm_mat_trans_16bit_generic( * tail */ blkCnt = srcRows & 7; - if (blkCnt > 0U) - { + if (blkCnt > 0U) { mve_pred16_t p0 = vctp16q(blkCnt); vecIn = vldrhq_gather_shifted_offset_u16(pDataC, vecOffs); vstrhq_p_u16(pDataDestR, vecIn, p0); @@ -508,30 +465,24 @@ __STATIC_INLINE arm_status arm_mat_trans_16bit_generic( return (ARM_MATH_SUCCESS); } - -__STATIC_INLINE arm_status arm_mat_cmplx_trans_16bit( - uint16_t srcRows, - uint16_t srcCols, - uint16_t *pDataSrc, - uint16_t dstRows, - uint16_t dstCols, - uint16_t *pDataDest) +__STATIC_INLINE arm_status arm_mat_cmplx_trans_16bit(uint16_t srcRows, uint16_t srcCols, + uint16_t *pDataSrc, uint16_t dstRows, + uint16_t dstCols, uint16_t *pDataDest) { static const uint16_t loadCmplxCol[8] = { 0, 0, 1, 1, 2, 2, 3, 3 }; - int i; - uint16x8_t vecOffsRef, vecOffsCur; + int i; + uint16x8_t vecOffsRef, vecOffsCur; uint16_t const *pDataC; - uint16_t *pDataRow; - uint16_t *pDataDestR, *pDataDestRow; - uint32_t blkCnt; - uint16x8_t vecIn; + uint16_t *pDataRow; + uint16_t *pDataDestR, *pDataDestRow; + uint32_t blkCnt; + uint16x8_t vecIn; #ifdef ARM_MATH_MATRIX_CHECK /* * Check for matrix mismatch condition */ - if ((srcRows != dstCols) || (srcCols != dstRows)) - { + if ((srcRows != dstCols) || (srcCols != dstRows)) { /* * Set status as ARM_MATH_SIZE_MISMATCH */ @@ -546,29 +497,26 @@ __STATIC_INLINE arm_status arm_mat_cmplx_trans_16bit( * 2x2, 3x3 and 4x4 specialization to be added */ - /* * build [0, 1, 2xcol, 2xcol+1, 4xcol, 4xcol+1, 6xcol, 6xcol+1] */ - vecOffsRef = vldrhq_u16((uint16_t const *) loadCmplxCol); - vecOffsRef = vmulq(vecOffsRef, (uint16_t) (srcCols * CMPLX_DIM)) - + viwdupq_u16((uint32_t)0, (uint16_t) 2, 1); + vecOffsRef = vldrhq_u16((uint16_t const *)loadCmplxCol); + vecOffsRef = vmulq(vecOffsRef, (uint16_t)(srcCols * CMPLX_DIM)) + + viwdupq_u16((uint32_t)0, (uint16_t)2, 1); pDataRow = pDataSrc; pDataDestRow = pDataDest; i = srcCols; - do - { - pDataC = (uint16_t const *) pDataRow; + do { + pDataC = (uint16_t const *)pDataRow; pDataDestR = pDataDestRow; vecOffsCur = vecOffsRef; blkCnt = (srcRows * CMPLX_DIM) >> 3; - while (blkCnt > 0U) - { + while (blkCnt > 0U) { vecIn = vldrhq_gather_shifted_offset(pDataC, vecOffsCur); - vstrhq(pDataDestR, vecIn); - pDataDestR+= 8; // VEC_LANES_U16 + vstrhq(pDataDestR, vecIn); + pDataDestR += 8; // VEC_LANES_U16 vecOffsCur = vaddq(vecOffsCur, (srcCols << 3)); /* * Decrement the blockSize loop counter @@ -580,8 +528,7 @@ __STATIC_INLINE arm_status arm_mat_cmplx_trans_16bit( * (will be merged thru tail predication) */ blkCnt = (srcRows * CMPLX_DIM) & 0x7; - if (blkCnt > 0U) - { + if (blkCnt > 0U) { mve_pred16_t p0 = vctp16q(blkCnt); vecIn = vldrhq_gather_shifted_offset(pDataC, vecOffsCur); vstrhq_p(pDataDestR, vecIn, p0); @@ -589,8 +536,7 @@ __STATIC_INLINE arm_status arm_mat_cmplx_trans_16bit( pDataRow += CMPLX_DIM; pDataDestRow += (srcRows * CMPLX_DIM); - } - while (--i); + } while (--i); return (ARM_MATH_SUCCESS); } @@ -601,22 +547,20 @@ __STATIC_INLINE arm_status arm_mat_cmplx_trans_16bit( Definitions available for MVEI only ***************************************/ -#if (defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEI)) && !defined(ARM_MATH_AUTOVECTORIZE) +#if (defined(ARM_MATH_HELIUM) || defined(ARM_MATH_MVEI)) && !defined(ARM_MATH_AUTOVECTORIZE) #include "arm_common_tables.h" -#define MVE_ASRL_SAT16(acc, shift) ((sqrshrl_sat48(acc, -(32-shift)) >> 32) & 0xffffffff) -#define MVE_ASRL_SAT32(acc, shift) ((sqrshrl(acc, -(32-shift)) >> 32) & 0xffffffff) - +#define MVE_ASRL_SAT16(acc, shift) ((sqrshrl_sat48(acc, -(32 - shift)) >> 32) & 0xffffffff) +#define MVE_ASRL_SAT32(acc, shift) ((sqrshrl(acc, -(32 - shift)) >> 32) & 0xffffffff) __STATIC_INLINE q31x4_t FAST_VSQRT_Q31(q31x4_t vecIn) { - q63x2_t vecTmpLL; - q31x4_t vecTmp0, vecTmp1; - q31_t scale; - q63_t tmp64; - q31x4_t vecNrm, vecDst, vecIdx, vecSignBits; - + q63x2_t vecTmpLL; + q31x4_t vecTmp0, vecTmp1; + q31_t scale; + q63_t tmp64; + q31x4_t vecNrm, vecDst, vecIdx, vecSignBits; vecSignBits = vclsq(vecIn); vecSignBits = vbicq_n_s32(vecSignBits, 1); @@ -649,11 +593,11 @@ __STATIC_INLINE q31x4_t FAST_VSQRT_Q31(q31x4_t vecIn) */ scale = 26 + (vecSignBits[0] >> 1); tmp64 = asrl(vecTmpLL[0], scale); - vecDst[0] = (q31_t) tmp64; + vecDst[0] = (q31_t)tmp64; scale = 26 + (vecSignBits[2] >> 1); tmp64 = asrl(vecTmpLL[1], scale); - vecDst[2] = (q31_t) tmp64; + vecDst[2] = (q31_t)tmp64; vecTmpLL = vmulltq_int(vecNrm, vecTmp0); @@ -662,11 +606,11 @@ __STATIC_INLINE q31x4_t FAST_VSQRT_Q31(q31x4_t vecIn) */ scale = 26 + (vecSignBits[1] >> 1); tmp64 = asrl(vecTmpLL[0], scale); - vecDst[1] = (q31_t) tmp64; + vecDst[1] = (q31_t)tmp64; scale = 26 + (vecSignBits[3] >> 1); tmp64 = asrl(vecTmpLL[1], scale); - vecDst[3] = (q31_t) tmp64; + vecDst[3] = (q31_t)tmp64; /* * set negative values to 0 */ @@ -677,9 +621,9 @@ __STATIC_INLINE q31x4_t FAST_VSQRT_Q31(q31x4_t vecIn) __STATIC_INLINE q15x8_t FAST_VSQRT_Q15(q15x8_t vecIn) { - q31x4_t vecTmpLev, vecTmpLodd, vecSignL; - q15x8_t vecTmp0, vecTmp1; - q15x8_t vecNrm, vecDst, vecIdx, vecSignBits; + q31x4_t vecTmpLev, vecTmpLodd, vecSignL; + q15x8_t vecTmp0, vecTmp1; + q15x8_t vecNrm, vecDst, vecIdx, vecSignBits; vecDst = vuninitializedq_s16(); @@ -742,7 +686,7 @@ __STATIC_INLINE q15x8_t FAST_VSQRT_Q15(q15x8_t vecIn) #endif /* defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEI) */ -#ifdef __cplusplus +#ifdef __cplusplus } #endif diff --git a/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/arm_math.h b/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/arm_math.h index 0e9ca5997ed..8a7b25cfa30 100644 --- a/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/arm_math.h +++ b/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/arm_math.h @@ -23,18 +23,16 @@ * limitations under the License. */ - #ifndef ARM_MATH_H #define ARM_MATH_H - #include "arm_math_types.h" #include "arm_math_memory.h" #include "dsp/none.h" #include "dsp/utils.h" -#include "dsp/basic_math_functions.h" +#include "dsp/basic_math_functions.h" #include "dsp/interpolation_functions.h" #include "dsp/bayes_functions.h" #include "dsp/matrix_functions.h" @@ -50,28 +48,17 @@ #include "dsp/quaternion_math_functions.h" #include "dsp/window_functions.h" - - -#ifdef __cplusplus -extern "C" -{ +#ifdef __cplusplus +extern "C" { #endif - - - //#define TABLE_SPACING_Q31 0x400000 //#define TABLE_SPACING_Q15 0x80 - - - - -#ifdef __cplusplus +#ifdef __cplusplus } #endif - #endif /* _ARM_MATH_H */ /** diff --git a/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/arm_math_f16.h b/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/arm_math_f16.h old mode 100755 new mode 100644 index 34ca0e542fc..2398a44135a --- a/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/arm_math_f16.h +++ b/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/arm_math_f16.h @@ -28,9 +28,8 @@ #include "arm_math.h" -#ifdef __cplusplus -extern "C" -{ +#ifdef __cplusplus +extern "C" { #endif #include "arm_math_types_f16.h" @@ -50,10 +49,8 @@ extern "C" #include "dsp/transform_functions_f16.h" #include "dsp/filtering_functions_f16.h" -#ifdef __cplusplus +#ifdef __cplusplus } #endif #endif /* _ARM_MATH_F16_H */ - - diff --git a/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/arm_math_memory.h b/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/arm_math_memory.h old mode 100755 new mode 100644 index d4b4c3323ad..55820e37d4c --- a/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/arm_math_memory.h +++ b/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/arm_math_memory.h @@ -29,62 +29,57 @@ #include "arm_math_types.h" - -#ifdef __cplusplus -extern "C" -{ +#ifdef __cplusplus +extern "C" { #endif /** @brief definition to read/write two 16 bit values. @deprecated */ -#if defined ( __CC_ARM ) - #define __SIMD32_TYPE int32_t __packed -#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) - #define __SIMD32_TYPE int32_t -#elif defined ( __GNUC__ ) - #define __SIMD32_TYPE int32_t -#elif defined ( __ICCARM__ ) - #define __SIMD32_TYPE int32_t __packed -#elif defined ( __TI_ARM__ ) - #define __SIMD32_TYPE int32_t -#elif defined ( __CSMC__ ) - #define __SIMD32_TYPE int32_t -#elif defined ( __TASKING__ ) - #define __SIMD32_TYPE __un(aligned) int32_t -#elif defined(_MSC_VER ) - #define __SIMD32_TYPE int32_t +#if defined(__CC_ARM) +#define __SIMD32_TYPE int32_t __packed +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#define __SIMD32_TYPE int32_t +#elif defined(__GNUC__) +#define __SIMD32_TYPE int32_t +#elif defined(__ICCARM__) +#define __SIMD32_TYPE int32_t __packed +#elif defined(__TI_ARM__) +#define __SIMD32_TYPE int32_t +#elif defined(__CSMC__) +#define __SIMD32_TYPE int32_t +#elif defined(__TASKING__) +#define __SIMD32_TYPE __un(aligned) int32_t +#elif defined(_MSC_VER) +#define __SIMD32_TYPE int32_t #else - #error Unknown compiler +#error Unknown compiler #endif -#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr)) -#define __SIMD32_CONST(addr) ( (__SIMD32_TYPE * ) (addr)) -#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE * ) (addr)) -#define __SIMD64(addr) (*( int64_t **) & (addr)) - +#define __SIMD32(addr) (*(__SIMD32_TYPE **)&(addr)) +#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr)) +#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *)(addr)) +#define __SIMD64(addr) (*(int64_t **)&(addr)) /* SIMD replacement */ - /** @brief Read 2 Q15 from Q15 pointer. @param[in] pQ15 points to input value @return Q31 value */ -__STATIC_FORCEINLINE q31_t read_q15x2 ( - q15_t const * pQ15) +__STATIC_FORCEINLINE q31_t read_q15x2(q15_t const *pQ15) { - q31_t val; + q31_t val; #ifdef __ARM_FEATURE_UNALIGNED - memcpy (&val, pQ15, 4); + memcpy(&val, pQ15, 4); #else - val = (pQ15[1] << 16) | (pQ15[0] & 0x0FFFF) ; + val = (pQ15[1] << 16) | (pQ15[0] & 0x0FFFF); #endif - return (val); + return (val); } /** @@ -106,19 +101,17 @@ __STATIC_FORCEINLINE q31_t read_q15x2 ( @param[in] pQ15 points to input value @param[in] value Q31 value */ -__STATIC_FORCEINLINE void write_q15x2_ia ( - q15_t ** pQ15, - q31_t value) +__STATIC_FORCEINLINE void write_q15x2_ia(q15_t **pQ15, q31_t value) { - q31_t val = value; + q31_t val = value; #ifdef __ARM_FEATURE_UNALIGNED - memcpy (*pQ15, &val, 4); + memcpy(*pQ15, &val, 4); #else - (*pQ15)[0] = (q15_t)(val & 0x0FFFF); - (*pQ15)[1] = (q15_t)((val >> 16) & 0x0FFFF); + (*pQ15)[0] = (q15_t)(val & 0x0FFFF); + (*pQ15)[1] = (q15_t)((val >> 16) & 0x0FFFF); #endif - *pQ15 += 2; + *pQ15 += 2; } /** @@ -126,37 +119,34 @@ __STATIC_FORCEINLINE void write_q15x2_ia ( @param[in] pQ15 points to input value @param[in] value Q31 value */ -__STATIC_FORCEINLINE void write_q15x2 ( - q15_t * pQ15, - q31_t value) +__STATIC_FORCEINLINE void write_q15x2(q15_t *pQ15, q31_t value) { - q31_t val = value; + q31_t val = value; #ifdef __ARM_FEATURE_UNALIGNED - memcpy (pQ15, &val, 4); + memcpy(pQ15, &val, 4); #else - pQ15[0] = (q15_t)(val & 0x0FFFF); - pQ15[1] = (q15_t)(val >> 16); + pQ15[0] = (q15_t)(val & 0x0FFFF); + pQ15[1] = (q15_t)(val >> 16); #endif } - /** @brief Read 4 Q7 from Q7 pointer @param[in] pQ7 points to input value @return Q31 value */ -__STATIC_FORCEINLINE q31_t read_q7x4 ( - q7_t const * pQ7) +__STATIC_FORCEINLINE q31_t read_q7x4(q7_t const *pQ7) { - q31_t val; + q31_t val; #ifdef __ARM_FEATURE_UNALIGNED - memcpy (&val, pQ7, 4); + memcpy(&val, pQ7, 4); #else - val =((pQ7[3] & 0x0FF) << 24) | ((pQ7[2] & 0x0FF) << 16) | ((pQ7[1] & 0x0FF) << 8) | (pQ7[0] & 0x0FF); -#endif - return (val); + val = ((pQ7[3] & 0x0FF) << 24) | ((pQ7[2] & 0x0FF) << 16) | ((pQ7[1] & 0x0FF) << 8) | + (pQ7[0] & 0x0FF); +#endif + return (val); } /** @@ -178,25 +168,22 @@ __STATIC_FORCEINLINE q31_t read_q7x4 ( @param[in] pQ7 points to input value @param[in] value Q31 value */ -__STATIC_FORCEINLINE void write_q7x4_ia ( - q7_t ** pQ7, - q31_t value) +__STATIC_FORCEINLINE void write_q7x4_ia(q7_t **pQ7, q31_t value) { - q31_t val = value; + q31_t val = value; #ifdef __ARM_FEATURE_UNALIGNED - memcpy (*pQ7, &val, 4); + memcpy(*pQ7, &val, 4); #else - (*pQ7)[0] = (q7_t)(val & 0x0FF); - (*pQ7)[1] = (q7_t)((val >> 8) & 0x0FF); - (*pQ7)[2] = (q7_t)((val >> 16) & 0x0FF); - (*pQ7)[3] = (q7_t)((val >> 24) & 0x0FF); + (*pQ7)[0] = (q7_t)(val & 0x0FF); + (*pQ7)[1] = (q7_t)((val >> 8) & 0x0FF); + (*pQ7)[2] = (q7_t)((val >> 16) & 0x0FF); + (*pQ7)[3] = (q7_t)((val >> 24) & 0x0FF); #endif - *pQ7 += 4; + *pQ7 += 4; } - -#ifdef __cplusplus +#ifdef __cplusplus } #endif diff --git a/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/arm_math_types.h b/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/arm_math_types.h old mode 100755 new mode 100644 index 74ae8485f77..b0a42274a1d --- a/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/arm_math_types.h +++ b/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/arm_math_types.h @@ -31,261 +31,245 @@ #include "arm_dsp_config.h" #endif -#ifndef ARM_DSP_ATTRIBUTE -#define ARM_DSP_ATTRIBUTE +#ifndef ARM_DSP_ATTRIBUTE +#define ARM_DSP_ATTRIBUTE #endif -#ifndef ARM_DSP_TABLE_ATTRIBUTE -#define ARM_DSP_TABLE_ATTRIBUTE +#ifndef ARM_DSP_TABLE_ATTRIBUTE +#define ARM_DSP_TABLE_ATTRIBUTE #endif -#ifdef __cplusplus -extern "C" -{ +#ifdef __cplusplus +extern "C" { #endif /* Compiler specific diagnostic adjustment */ -#if defined ( __CC_ARM ) +#if defined(__CC_ARM) -#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) -#elif defined ( __APPLE_CC__ ) - #pragma GCC diagnostic ignored "-Wold-style-cast" +#elif defined(__APPLE_CC__) +#pragma GCC diagnostic ignored "-Wold-style-cast" #elif defined(__clang__) - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wsign-conversion" - #pragma GCC diagnostic ignored "-Wconversion" - #pragma GCC diagnostic ignored "-Wunused-parameter" +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" -#elif defined ( __GNUC__ ) - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wsign-conversion" - #pragma GCC diagnostic ignored "-Wconversion" - #pragma GCC diagnostic ignored "-Wunused-parameter" - // Disable some code having issue with GCC - #define ARM_DSP_BUILT_WITH_GCC +#elif defined(__GNUC__) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" +// Disable some code having issue with GCC +#define ARM_DSP_BUILT_WITH_GCC -#elif defined ( __ICCARM__ ) +#elif defined(__ICCARM__) -#elif defined ( __TI_ARM__ ) +#elif defined(__TI_ARM__) -#elif defined ( __CSMC__ ) +#elif defined(__CSMC__) -#elif defined ( __TASKING__ ) +#elif defined(__TASKING__) -#elif defined ( _MSC_VER ) +#elif defined(_MSC_VER) #else - #error Unknown compiler +#error Unknown compiler #endif - /* Included for instrinsics definitions */ -#if defined (_MSC_VER ) +#if defined(_MSC_VER) #include #define __STATIC_FORCEINLINE static __forceinline #define __STATIC_INLINE static __inline #define __ALIGNED(x) __declspec(align(x)) #define __WEAK -#elif defined ( __APPLE_CC__ ) +#elif defined(__APPLE_CC__) #include -#define __ALIGNED(x) __attribute__((aligned(x))) -#define __STATIC_FORCEINLINE static inline __attribute__((always_inline)) +#define __ALIGNED(x) __attribute__((aligned(x))) +#define __STATIC_FORCEINLINE static inline __attribute__((always_inline)) #define __STATIC_INLINE static inline #define __WEAK -#elif defined (__GNUC_PYTHON__) +#elif defined(__GNUC_PYTHON__) #include -#define __ALIGNED(x) __attribute__((aligned(x))) -#define __STATIC_FORCEINLINE static inline __attribute__((always_inline)) +#define __ALIGNED(x) __attribute__((aligned(x))) +#define __STATIC_FORCEINLINE static inline __attribute__((always_inline)) #define __STATIC_INLINE static inline #define __WEAK #else #include "cmsis_compiler.h" #endif - - #include #include #include #include /* evaluate ARM DSP feature */ -#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) - #define ARM_MATH_DSP 1 +#if (defined(__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) +#define ARM_MATH_DSP 1 #endif #if defined(ARM_MATH_NEON) - #if defined(_MSC_VER) && defined(_M_ARM64EC) - #include - #else - #include - #endif - #if defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) && __ARM_FEATURE_FP16_VECTOR_ARITHMETIC - #if !defined(ARM_MATH_NEON_FLOAT16) - #define ARM_MATH_NEON_FLOAT16 - #endif - #endif +#if defined(_MSC_VER) && defined(_M_ARM64EC) +#include +#else +#include +#endif +#if defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) && __ARM_FEATURE_FP16_VECTOR_ARITHMETIC +#if !defined(ARM_MATH_NEON_FLOAT16) +#define ARM_MATH_NEON_FLOAT16 +#endif +#endif #endif #if !defined(ARM_MATH_AUTOVECTORIZE) - #if defined(__ARM_FEATURE_MVE) #if __ARM_FEATURE_MVE - #if !defined(ARM_MATH_MVEI) - #define ARM_MATH_MVEI - #endif +#if !defined(ARM_MATH_MVEI) +#define ARM_MATH_MVEI +#endif #endif #if defined(__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE & 2) - #if !defined(ARM_MATH_MVEF) - #define ARM_MATH_MVEF - #endif - #if !defined(ARM_MATH_MVE_FLOAT16) - #define ARM_MATH_MVE_FLOAT16 - #endif +#if !defined(ARM_MATH_MVEF) +#define ARM_MATH_MVEF +#endif +#if !defined(ARM_MATH_MVE_FLOAT16) +#define ARM_MATH_MVE_FLOAT16 +#endif #endif #endif /* defined (__ARM_FEATURE_MVE) */ #endif /* !defined (ARM_MATH_AUTOVECTORIZE) */ +#if defined(ARM_MATH_HELIUM) +#if !defined(ARM_MATH_MVEF) +#define ARM_MATH_MVEF +#endif -#if defined (ARM_MATH_HELIUM) - #if !defined(ARM_MATH_MVEF) - #define ARM_MATH_MVEF - #endif - - #if !defined(ARM_MATH_MVEI) - #define ARM_MATH_MVEI - #endif - - #if !defined(ARM_MATH_MVE_FLOAT16) - #define ARM_MATH_MVE_FLOAT16 - #endif -#endif - - - -#if defined ( __CC_ARM ) - /* Enter low optimization region - place directly above function definition */ - #if defined( __ARM_ARCH_7EM__ ) - #define LOW_OPTIMIZATION_ENTER \ - _Pragma ("push") \ - _Pragma ("O1") - #else - #define LOW_OPTIMIZATION_ENTER - #endif - - /* Exit low optimization region - place directly after end of function definition */ - #if defined ( __ARM_ARCH_7EM__ ) - #define LOW_OPTIMIZATION_EXIT \ - _Pragma ("pop") - #else - #define LOW_OPTIMIZATION_EXIT - #endif - - /* Enter low optimization region - place directly above function definition */ - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - - /* Exit low optimization region - place directly after end of function definition */ - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined (__ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) - #define LOW_OPTIMIZATION_ENTER - #define LOW_OPTIMIZATION_EXIT - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined ( __APPLE_CC__ ) - #define LOW_OPTIMIZATION_ENTER - #define LOW_OPTIMIZATION_EXIT - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined ( __GNUC__ ) - #define LOW_OPTIMIZATION_ENTER \ - __attribute__(( optimize("-O1") )) - #define LOW_OPTIMIZATION_EXIT - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined ( __ICCARM__ ) - /* Enter low optimization region - place directly above function definition */ - #if defined ( __ARM_ARCH_7EM__ ) - #define LOW_OPTIMIZATION_ENTER \ - _Pragma ("optimize=low") - #else - #define LOW_OPTIMIZATION_ENTER - #endif - - /* Exit low optimization region - place directly after end of function definition */ - #define LOW_OPTIMIZATION_EXIT - - /* Enter low optimization region - place directly above function definition */ - #if defined ( __ARM_ARCH_7EM__ ) - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \ - _Pragma ("optimize=low") - #else - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - #endif - - /* Exit low optimization region - place directly after end of function definition */ - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined ( __TI_ARM__ ) - #define LOW_OPTIMIZATION_ENTER - #define LOW_OPTIMIZATION_EXIT - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined ( __CSMC__ ) - #define LOW_OPTIMIZATION_ENTER - #define LOW_OPTIMIZATION_EXIT - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined ( __TASKING__ ) - #define LOW_OPTIMIZATION_ENTER - #define LOW_OPTIMIZATION_EXIT - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined ( _MSC_VER ) || defined(__GNUC_PYTHON__) - #define LOW_OPTIMIZATION_ENTER - #define LOW_OPTIMIZATION_EXIT - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT +#if !defined(ARM_MATH_MVEI) +#define ARM_MATH_MVEI #endif +#if !defined(ARM_MATH_MVE_FLOAT16) +#define ARM_MATH_MVE_FLOAT16 +#endif +#endif + +#if defined(__CC_ARM) +/* Enter low optimization region - place directly above function definition */ +#if defined(__ARM_ARCH_7EM__) +#define LOW_OPTIMIZATION_ENTER _Pragma("push") _Pragma("O1") +#else +#define LOW_OPTIMIZATION_ENTER +#endif + +/* Exit low optimization region - place directly after end of function definition */ +#if defined(__ARM_ARCH_7EM__) +#define LOW_OPTIMIZATION_EXIT _Pragma("pop") +#else +#define LOW_OPTIMIZATION_EXIT +#endif + +/* Enter low optimization region - place directly above function definition */ +#define IAR_ONLY_LOW_OPTIMIZATION_ENTER + +/* Exit low optimization region - place directly after end of function definition */ +#define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#define LOW_OPTIMIZATION_ENTER +#define LOW_OPTIMIZATION_EXIT +#define IAR_ONLY_LOW_OPTIMIZATION_ENTER +#define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__APPLE_CC__) +#define LOW_OPTIMIZATION_ENTER +#define LOW_OPTIMIZATION_EXIT +#define IAR_ONLY_LOW_OPTIMIZATION_ENTER +#define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__GNUC__) +#define LOW_OPTIMIZATION_ENTER __attribute__((optimize("-O1"))) +#define LOW_OPTIMIZATION_EXIT +#define IAR_ONLY_LOW_OPTIMIZATION_ENTER +#define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__ICCARM__) +/* Enter low optimization region - place directly above function definition */ +#if defined(__ARM_ARCH_7EM__) +#define LOW_OPTIMIZATION_ENTER _Pragma("optimize=low") +#else +#define LOW_OPTIMIZATION_ENTER +#endif +/* Exit low optimization region - place directly after end of function definition */ +#define LOW_OPTIMIZATION_EXIT + +/* Enter low optimization region - place directly above function definition */ +#if defined(__ARM_ARCH_7EM__) +#define IAR_ONLY_LOW_OPTIMIZATION_ENTER _Pragma("optimize=low") +#else +#define IAR_ONLY_LOW_OPTIMIZATION_ENTER +#endif + +/* Exit low optimization region - place directly after end of function definition */ +#define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__TI_ARM__) +#define LOW_OPTIMIZATION_ENTER +#define LOW_OPTIMIZATION_EXIT +#define IAR_ONLY_LOW_OPTIMIZATION_ENTER +#define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__CSMC__) +#define LOW_OPTIMIZATION_ENTER +#define LOW_OPTIMIZATION_EXIT +#define IAR_ONLY_LOW_OPTIMIZATION_ENTER +#define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__TASKING__) +#define LOW_OPTIMIZATION_ENTER +#define LOW_OPTIMIZATION_EXIT +#define IAR_ONLY_LOW_OPTIMIZATION_ENTER +#define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(_MSC_VER) || defined(__GNUC_PYTHON__) +#define LOW_OPTIMIZATION_ENTER +#define LOW_OPTIMIZATION_EXIT +#define IAR_ONLY_LOW_OPTIMIZATION_ENTER +#define IAR_ONLY_LOW_OPTIMIZATION_EXIT +#endif /* Compiler specific diagnostic adjustment */ -#if defined ( __CC_ARM ) +#if defined(__CC_ARM) -#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) -#elif defined ( __APPLE_CC__ ) +#elif defined(__APPLE_CC__) -#elif defined ( __GNUC__ ) +#elif defined(__GNUC__) #pragma GCC diagnostic pop -#elif defined ( __ICCARM__ ) +#elif defined(__ICCARM__) -#elif defined ( __TI_ARM__ ) +#elif defined(__TI_ARM__) -#elif defined ( __CSMC__ ) +#elif defined(__CSMC__) -#elif defined ( __TASKING__ ) +#elif defined(__TASKING__) -#elif defined ( _MSC_VER ) +#elif defined(_MSC_VER) #else - #error Unknown compiler +#error Unknown compiler #endif -#ifdef __cplusplus +#ifdef __cplusplus } #endif @@ -297,9 +281,8 @@ extern "C" #error("-DARM_DSP_CONFIG_TABLES no more supported. Use the new initialization functions to let the linker optimize the code size.") #endif -#ifdef __cplusplus -extern "C" -{ +#ifdef __cplusplus +extern "C" { #endif /** @@ -307,338 +290,327 @@ extern "C" * @{ */ - /** +/** * @brief 8-bit fractional data type in 1.7 format. */ - typedef int8_t q7_t; +typedef int8_t q7_t; - /** +/** * @brief 16-bit fractional data type in 1.15 format. */ - typedef int16_t q15_t; +typedef int16_t q15_t; - /** +/** * @brief 32-bit fractional data type in 1.31 format. */ - typedef int32_t q31_t; +typedef int32_t q31_t; - /** +/** * @brief 64-bit fractional data type in 1.63 format. */ - typedef int64_t q63_t; +typedef int64_t q63_t; - /** +/** * @brief 32-bit floating-point type definition. */ #if !defined(__ICCARM__) || !(__ARM_FEATURE_MVE & 2) - typedef float float32_t; +typedef float float32_t; #endif - /** +/** * @brief 64-bit floating-point type definition. */ - typedef double float64_t; +typedef double float64_t; - /** +/** * @brief vector types */ -#if defined(ARM_MATH_NEON) || (defined (ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE)) +#if defined(ARM_MATH_NEON) || (defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE)) - /** +/** * @brief 64-bit fractional 128-bit vector data type in 1.63 format */ - typedef int64x2_t q63x2_t; +typedef int64x2_t q63x2_t; - /** +/** * @brief 32-bit fractional 128-bit vector data type in 1.31 format. */ - typedef int32x4_t q31x4_t; +typedef int32x4_t q31x4_t; - /** +/** * @brief 16-bit fractional 128-bit vector data type with 16-bit alignment in 1.15 format. */ - typedef __ALIGNED(2) int16x8_t q15x8_t; +typedef __ALIGNED(2) int16x8_t q15x8_t; - /** +/** * @brief 8-bit fractional 128-bit vector data type with 8-bit alignment in 1.7 format. */ - typedef __ALIGNED(1) int8x16_t q7x16_t; +typedef __ALIGNED(1) int8x16_t q7x16_t; - /** +/** * @brief 32-bit fractional 128-bit vector pair data type in 1.31 format. */ - typedef int32x4x2_t q31x4x2_t; +typedef int32x4x2_t q31x4x2_t; - /** +/** * @brief 32-bit fractional 128-bit vector quadruplet data type in 1.31 format. */ - typedef int32x4x4_t q31x4x4_t; +typedef int32x4x4_t q31x4x4_t; - /** +/** * @brief 16-bit fractional 128-bit vector pair data type in 1.15 format. */ - typedef int16x8x2_t q15x8x2_t; +typedef int16x8x2_t q15x8x2_t; - /** +/** * @brief 16-bit fractional 128-bit vector quadruplet data type in 1.15 format. */ - typedef int16x8x4_t q15x8x4_t; +typedef int16x8x4_t q15x8x4_t; - /** +/** * @brief 8-bit fractional 128-bit vector pair data type in 1.7 format. */ - typedef int8x16x2_t q7x16x2_t; +typedef int8x16x2_t q7x16x2_t; - /** +/** * @brief 8-bit fractional 128-bit vector quadruplet data type in 1.7 format. */ - typedef int8x16x4_t q7x16x4_t; +typedef int8x16x4_t q7x16x4_t; - /** +/** * @brief 32-bit fractional data type in 9.23 format. */ - typedef int32_t q23_t; +typedef int32_t q23_t; - /** +/** * @brief 32-bit fractional 128-bit vector data type in 9.23 format. */ - typedef int32x4_t q23x4_t; +typedef int32x4_t q23x4_t; - /** +/** * @brief 64-bit status 128-bit vector data type. */ - typedef int64x2_t status64x2_t; +typedef int64x2_t status64x2_t; - /** +/** * @brief 32-bit status 128-bit vector data type. */ - typedef int32x4_t status32x4_t; +typedef int32x4_t status32x4_t; - /** +/** * @brief 16-bit status 128-bit vector data type. */ - typedef int16x8_t status16x8_t; +typedef int16x8_t status16x8_t; - /** +/** * @brief 8-bit status 128-bit vector data type. */ - typedef int8x16_t status8x16_t; - +typedef int8x16_t status8x16_t; #endif -#if defined(ARM_MATH_NEON) || (defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE)) /* floating point vector*/ +#if defined(ARM_MATH_NEON) || \ + (defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE)) /* floating point vector*/ - /** +/** * @brief 32-bit floating-point 128-bit vector type */ - typedef float32x4_t f32x4_t; +typedef float32x4_t f32x4_t; - /** +/** * @brief 32-bit floating-point 128-bit vector pair data type */ - typedef float32x4x2_t f32x4x2_t; +typedef float32x4x2_t f32x4x2_t; - /** +/** * @brief 32-bit floating-point 128-bit vector quadruplet data type */ - typedef float32x4x4_t f32x4x4_t; +typedef float32x4x4_t f32x4x4_t; - /** +/** * @brief 32-bit ubiquitous 128-bit vector data type */ - typedef union _any32x4_t - { - float32x4_t f; - int32x4_t i; - } any32x4_t; +typedef union _any32x4_t { + float32x4_t f; + int32x4_t i; +} any32x4_t; #endif #if defined(ARM_MATH_NEON) - /** +/** * @brief 32-bit fractional 64-bit vector data type in 1.31 format. */ - typedef int32x2_t q31x2_t; +typedef int32x2_t q31x2_t; - /** +/** * @brief 16-bit fractional 64-bit vector data type in 1.15 format. */ - typedef __ALIGNED(2) int16x4_t q15x4_t; +typedef __ALIGNED(2) int16x4_t q15x4_t; - /** +/** * @brief 8-bit fractional 64-bit vector data type in 1.7 format. */ - typedef __ALIGNED(1) int8x8_t q7x8_t; +typedef __ALIGNED(1) int8x8_t q7x8_t; - /** +/** * @brief 32-bit float 64-bit vector data type. */ - typedef float32x2_t f32x2_t; +typedef float32x2_t f32x2_t; - /** +/** * @brief 32-bit floating-point 128-bit vector triplet data type */ - typedef float32x4x3_t f32x4x3_t; +typedef float32x4x3_t f32x4x3_t; - /** +/** * @brief 32-bit fractional 128-bit vector triplet data type in 1.31 format */ - typedef int32x4x3_t q31x4x3_t; +typedef int32x4x3_t q31x4x3_t; - /** +/** * @brief 16-bit fractional 128-bit vector triplet data type in 1.15 format */ - typedef int16x8x3_t q15x8x3_t; +typedef int16x8x3_t q15x8x3_t; - /** +/** * @brief 8-bit fractional 128-bit vector triplet data type in 1.7 format */ - typedef int8x16x3_t q7x16x3_t; +typedef int8x16x3_t q7x16x3_t; - /** +/** * @brief 32-bit floating-point 64-bit vector pair data type */ - typedef float32x2x2_t f32x2x2_t; +typedef float32x2x2_t f32x2x2_t; - /** +/** * @brief 32-bit floating-point 64-bit vector triplet data type */ - typedef float32x2x3_t f32x2x3_t; +typedef float32x2x3_t f32x2x3_t; - /** +/** * @brief 32-bit floating-point 64-bit vector quadruplet data type */ - typedef float32x2x4_t f32x2x4_t; +typedef float32x2x4_t f32x2x4_t; - /** +/** * @brief 32-bit fractional 64-bit vector pair data type in 1.31 format */ - typedef int32x2x2_t q31x2x2_t; +typedef int32x2x2_t q31x2x2_t; - /** +/** * @brief 32-bit fractional 64-bit vector triplet data type in 1.31 format */ - typedef int32x2x3_t q31x2x3_t; +typedef int32x2x3_t q31x2x3_t; - /** +/** * @brief 32-bit fractional 64-bit vector quadruplet data type in 1.31 format */ - typedef int32x4x3_t q31x2x4_t; +typedef int32x4x3_t q31x2x4_t; - /** +/** * @brief 16-bit fractional 64-bit vector pair data type in 1.15 format */ - typedef int16x4x2_t q15x4x2_t; +typedef int16x4x2_t q15x4x2_t; - /** +/** * @brief 16-bit fractional 64-bit vector triplet data type in 1.15 format */ - typedef int16x4x2_t q15x4x3_t; +typedef int16x4x2_t q15x4x3_t; - /** +/** * @brief 16-bit fractional 64-bit vector quadruplet data type in 1.15 format */ - typedef int16x4x3_t q15x4x4_t; +typedef int16x4x3_t q15x4x4_t; - /** +/** * @brief 8-bit fractional 64-bit vector pair data type in 1.7 format */ - typedef int8x8x2_t q7x8x2_t; +typedef int8x8x2_t q7x8x2_t; - /** +/** * @brief 8-bit fractional 64-bit vector triplet data type in 1.7 format */ - typedef int8x8x3_t q7x8x3_t; +typedef int8x8x3_t q7x8x3_t; - /** +/** * @brief 8-bit fractional 64-bit vector quadruplet data type in 1.7 format */ - typedef int8x8x4_t q7x8x4_t; +typedef int8x8x4_t q7x8x4_t; - /** +/** * @brief 32-bit ubiquitous 64-bit vector data type */ - typedef union _any32x2_t - { - float32x2_t f; - int32x2_t i; - } any32x2_t; +typedef union _any32x2_t { + float32x2_t f; + int32x2_t i; +} any32x2_t; - /** +/** * @brief 32-bit status 64-bit vector data type. */ - typedef int32x4_t status32x2_t; +typedef int32x4_t status32x2_t; - /** +/** * @brief 16-bit status 64-bit vector data type. */ - typedef int16x8_t status16x4_t; +typedef int16x8_t status16x4_t; - /** +/** * @brief 8-bit status 64-bit vector data type. */ - typedef int8x16_t status8x8_t; +typedef int8x16_t status8x8_t; #endif - /** +/** * @brief Error status returned by some functions in the library. */ - typedef enum - { - ARM_MATH_SUCCESS = 0, /**< No error */ - ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ - ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ - ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation */ - ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ - ARM_MATH_SINGULAR = -5, /**< Input matrix is singular and cannot be inverted */ - ARM_MATH_TEST_FAILURE = -6, /**< Test Failed */ - ARM_MATH_DECOMPOSITION_FAILURE = -7 /**< Decomposition Failed */ - } arm_status; +typedef enum { + ARM_MATH_SUCCESS = 0, /**< No error */ + ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ + ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ + ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation */ + ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ + ARM_MATH_SINGULAR = -5, /**< Input matrix is singular and cannot be inverted */ + ARM_MATH_TEST_FAILURE = -6, /**< Test Failed */ + ARM_MATH_DECOMPOSITION_FAILURE = -7 /**< Decomposition Failed */ +} arm_status; /** * @} // endgroup generic */ +#define F64_MAX ((float64_t)DBL_MAX) +#define F32_MAX ((float32_t)FLT_MAX) -#define F64_MAX ((float64_t)DBL_MAX) -#define F32_MAX ((float32_t)FLT_MAX) - - - -#define F64_MIN (-DBL_MAX) -#define F32_MIN (-FLT_MAX) - - - -#define F64_ABSMAX ((float64_t)DBL_MAX) -#define F32_ABSMAX ((float32_t)FLT_MAX) - - +#define F64_MIN (-DBL_MAX) +#define F32_MIN (-FLT_MAX) -#define F64_ABSMIN ((float64_t)0.0) -#define F32_ABSMIN ((float32_t)0.0) +#define F64_ABSMAX ((float64_t)DBL_MAX) +#define F32_ABSMAX ((float32_t)FLT_MAX) +#define F64_ABSMIN ((float64_t)0.0) +#define F32_ABSMIN ((float32_t)0.0) -#define Q31_MAX ((q31_t)(0x7FFFFFFFL)) -#define Q15_MAX ((q15_t)(0x7FFF)) -#define Q7_MAX ((q7_t)(0x7F)) -#define Q31_MIN ((q31_t)(0x80000000L)) -#define Q15_MIN ((q15_t)(0x8000)) -#define Q7_MIN ((q7_t)(0x80)) +#define Q31_MAX ((q31_t)(0x7FFFFFFFL)) +#define Q15_MAX ((q15_t)(0x7FFF)) +#define Q7_MAX ((q7_t)(0x7F)) +#define Q31_MIN ((q31_t)(0x80000000L)) +#define Q15_MIN ((q15_t)(0x8000)) +#define Q7_MIN ((q7_t)(0x80)) -#define Q31_ABSMAX ((q31_t)(0x7FFFFFFFL)) -#define Q15_ABSMAX ((q15_t)(0x7FFF)) -#define Q7_ABSMAX ((q7_t)(0x7F)) -#define Q31_ABSMIN ((q31_t)0) -#define Q15_ABSMIN ((q15_t)0) -#define Q7_ABSMIN ((q7_t)0) +#define Q31_ABSMAX ((q31_t)(0x7FFFFFFFL)) +#define Q15_ABSMAX ((q15_t)(0x7FFF)) +#define Q7_ABSMAX ((q7_t)(0x7F)) +#define Q31_ABSMIN ((q31_t)0) +#define Q15_ABSMIN ((q15_t)0) +#define Q7_ABSMIN ((q7_t)0) - /* Dimension C vector space */ - #define CMPLX_DIM 2 +/* Dimension C vector space */ +#define CMPLX_DIM 2 -#ifdef __cplusplus +#ifdef __cplusplus } #endif diff --git a/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/arm_math_types_f16.h b/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/arm_math_types_f16.h old mode 100755 new mode 100644 index 26b8feeec9c..be4a5a06162 --- a/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/arm_math_types_f16.h +++ b/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/arm_math_types_f16.h @@ -28,12 +28,11 @@ #include "arm_math_types.h" -#ifdef __cplusplus -extern "C" -{ +#ifdef __cplusplus +extern "C" { #endif -#if !defined( __CC_ARM ) +#if !defined(__CC_ARM) /** * @brief 16-bit floating-point type definition. @@ -49,97 +48,93 @@ If it is not available, f16 version of the kernels won't be built. */ -#if defined(__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE & 2) +#if defined(__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE & 2) /* When Vector float16, this flag is always defined and can't be disabled */ - #define ARM_FLOAT16_SUPPORTED +#define ARM_FLOAT16_SUPPORTED #else - #if !defined(DISABLEFLOAT16) - #if defined(__ARM_FP16_FORMAT_IEEE) || defined(__ARM_FP16_FORMAT_ALTERNATIVE) - typedef __fp16 float16_t; - #define ARM_FLOAT16_SUPPORTED - #endif - #endif +#if !defined(DISABLEFLOAT16) +#if defined(__ARM_FP16_FORMAT_IEEE) || defined(__ARM_FP16_FORMAT_ALTERNATIVE) +typedef __fp16 float16_t; +#define ARM_FLOAT16_SUPPORTED +#endif +#endif #endif -#if defined(ARM_MATH_NEON) || (defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE)) /* floating point vector*/ +#if defined(ARM_MATH_NEON) || \ + (defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE)) /* floating point vector*/ #if defined(ARM_MATH_MVE_FLOAT16) || defined(ARM_MATH_NEON_FLOAT16) - /** +/** * @brief 16-bit floating-point 128-bit vector data type */ - typedef __ALIGNED(2) float16x8_t f16x8_t; +typedef __ALIGNED(2) float16x8_t f16x8_t; - /** +/** * @brief 16-bit floating-point 128-bit vector pair data type */ - typedef float16x8x2_t f16x8x2_t; +typedef float16x8x2_t f16x8x2_t; - /** +/** * @brief 16-bit floating-point 128-bit vector quadruplet data type */ - typedef float16x8x4_t f16x8x4_t; +typedef float16x8x4_t f16x8x4_t; - /** +/** * @brief 16-bit ubiquitous 128-bit vector data type */ - typedef union _any16x8_t - { - float16x8_t f; - int16x8_t i; - } any16x8_t; +typedef union _any16x8_t { + float16x8_t f; + int16x8_t i; +} any16x8_t; #endif #endif #if defined(ARM_MATH_NEON) - #if defined(ARM_MATH_NEON_FLOAT16) - /** +/** * @brief 16-bit float 64-bit vector data type. */ - typedef __ALIGNED(2) float16x4_t f16x4_t; +typedef __ALIGNED(2) float16x4_t f16x4_t; - /** +/** * @brief 16-bit floating-point 128-bit vector triplet data type */ - typedef float16x8x3_t f16x8x3_t; +typedef float16x8x3_t f16x8x3_t; - /** +/** * @brief 16-bit floating-point 64-bit vector pair data type */ - typedef float16x4x2_t f16x4x2_t; +typedef float16x4x2_t f16x4x2_t; - /** +/** * @brief 16-bit floating-point 64-bit vector triplet data type */ - typedef float16x4x3_t f16x4x3_t; +typedef float16x4x3_t f16x4x3_t; - /** +/** * @brief 16-bit floating-point 64-bit vector quadruplet data type */ - typedef float16x4x4_t f16x4x4_t; +typedef float16x4x4_t f16x4x4_t; - /** +/** * @brief 16-bit ubiquitous 64-bit vector data type */ - typedef union _any16x4_t - { - float16x4_t f; - int16x4_t i; - } any16x4_t; +typedef union _any16x4_t { + float16x4_t f; + int16x4_t i; +} any16x4_t; #endif #endif - - #if defined(ARM_FLOAT16_SUPPORTED) #if defined(__ICCARM__) -#define F16INFINITY ((float16_t) INFINITY) +#define F16INFINITY ((float16_t)INFINITY) #else @@ -147,16 +142,16 @@ won't be built. #endif -#define F16_MAX ((float16_t)__FLT16_MAX__) -#define F16_MIN (-(_Float16)__FLT16_MAX__) +#define F16_MAX ((float16_t)__FLT16_MAX__) +#define F16_MIN (-(_Float16)__FLT16_MAX__) -#define F16_ABSMAX ((float16_t)__FLT16_MAX__) -#define F16_ABSMIN ((float16_t)0.0f16) +#define F16_ABSMAX ((float16_t)__FLT16_MAX__) +#define F16_ABSMIN ((float16_t)0.0f16) #endif /* ARM_FLOAT16_SUPPORTED*/ #endif /* !defined( __CC_ARM ) */ -#ifdef __cplusplus +#ifdef __cplusplus } #endif diff --git a/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/arm_mve_tables.h b/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/arm_mve_tables.h old mode 100755 new mode 100644 index aa58d7a92c6..6628a7f2fa5 --- a/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/arm_mve_tables.h +++ b/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/arm_mve_tables.h @@ -27,23 +27,17 @@ * limitations under the License. */ - #ifndef ARM_MVE_TABLES_H - #define ARM_MVE_TABLES_H +#ifndef ARM_MVE_TABLES_H +#define ARM_MVE_TABLES_H #include "arm_math_types.h" -#ifdef __cplusplus -extern "C" -{ +#ifdef __cplusplus +extern "C" { #endif - - - #if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) - - extern const uint32_t rearranged_twiddle_tab_stride1_arr_16_f32[2]; extern const uint32_t rearranged_twiddle_tab_stride2_arr_16_f32[2]; extern const uint32_t rearranged_twiddle_tab_stride3_arr_16_f32[2]; @@ -51,7 +45,6 @@ extern const float32_t rearranged_twiddle_stride1_16_f32[8]; extern const float32_t rearranged_twiddle_stride2_16_f32[8]; extern const float32_t rearranged_twiddle_stride3_16_f32[8]; - extern const uint32_t rearranged_twiddle_tab_stride1_arr_64_f32[3]; extern const uint32_t rearranged_twiddle_tab_stride2_arr_64_f32[3]; extern const uint32_t rearranged_twiddle_tab_stride3_arr_64_f32[3]; @@ -59,7 +52,6 @@ extern const float32_t rearranged_twiddle_stride1_64_f32[40]; extern const float32_t rearranged_twiddle_stride2_64_f32[40]; extern const float32_t rearranged_twiddle_stride3_64_f32[40]; - extern const uint32_t rearranged_twiddle_tab_stride1_arr_256_f32[4]; extern const uint32_t rearranged_twiddle_tab_stride2_arr_256_f32[4]; extern const uint32_t rearranged_twiddle_tab_stride3_arr_256_f32[4]; @@ -67,7 +59,6 @@ extern const float32_t rearranged_twiddle_stride1_256_f32[168]; extern const float32_t rearranged_twiddle_stride2_256_f32[168]; extern const float32_t rearranged_twiddle_stride3_256_f32[168]; - extern const uint32_t rearranged_twiddle_tab_stride1_arr_1024_f32[5]; extern const uint32_t rearranged_twiddle_tab_stride2_arr_1024_f32[5]; extern const uint32_t rearranged_twiddle_tab_stride3_arr_1024_f32[5]; @@ -75,7 +66,6 @@ extern const float32_t rearranged_twiddle_stride1_1024_f32[680]; extern const float32_t rearranged_twiddle_stride2_1024_f32[680]; extern const float32_t rearranged_twiddle_stride3_1024_f32[680]; - extern const uint32_t rearranged_twiddle_tab_stride1_arr_4096_f32[6]; extern const uint32_t rearranged_twiddle_tab_stride2_arr_4096_f32[6]; extern const uint32_t rearranged_twiddle_tab_stride3_arr_4096_f32[6]; @@ -83,14 +73,9 @@ extern const float32_t rearranged_twiddle_stride1_4096_f32[2728]; extern const float32_t rearranged_twiddle_stride2_4096_f32[2728]; extern const float32_t rearranged_twiddle_stride3_4096_f32[2728]; - #endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ - - -#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) - - +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) extern const uint32_t rearranged_twiddle_tab_stride1_arr_16_q31[2]; extern const uint32_t rearranged_twiddle_tab_stride2_arr_16_q31[2]; @@ -99,7 +84,6 @@ extern const q31_t rearranged_twiddle_stride1_16_q31[8]; extern const q31_t rearranged_twiddle_stride2_16_q31[8]; extern const q31_t rearranged_twiddle_stride3_16_q31[8]; - extern const uint32_t rearranged_twiddle_tab_stride1_arr_64_q31[3]; extern const uint32_t rearranged_twiddle_tab_stride2_arr_64_q31[3]; extern const uint32_t rearranged_twiddle_tab_stride3_arr_64_q31[3]; @@ -107,7 +91,6 @@ extern const q31_t rearranged_twiddle_stride1_64_q31[40]; extern const q31_t rearranged_twiddle_stride2_64_q31[40]; extern const q31_t rearranged_twiddle_stride3_64_q31[40]; - extern const uint32_t rearranged_twiddle_tab_stride1_arr_256_q31[4]; extern const uint32_t rearranged_twiddle_tab_stride2_arr_256_q31[4]; extern const uint32_t rearranged_twiddle_tab_stride3_arr_256_q31[4]; @@ -115,7 +98,6 @@ extern const q31_t rearranged_twiddle_stride1_256_q31[168]; extern const q31_t rearranged_twiddle_stride2_256_q31[168]; extern const q31_t rearranged_twiddle_stride3_256_q31[168]; - extern const uint32_t rearranged_twiddle_tab_stride1_arr_1024_q31[5]; extern const uint32_t rearranged_twiddle_tab_stride2_arr_1024_q31[5]; extern const uint32_t rearranged_twiddle_tab_stride3_arr_1024_q31[5]; @@ -123,7 +105,6 @@ extern const q31_t rearranged_twiddle_stride1_1024_q31[680]; extern const q31_t rearranged_twiddle_stride2_1024_q31[680]; extern const q31_t rearranged_twiddle_stride3_1024_q31[680]; - extern const uint32_t rearranged_twiddle_tab_stride1_arr_4096_q31[6]; extern const uint32_t rearranged_twiddle_tab_stride2_arr_4096_q31[6]; extern const uint32_t rearranged_twiddle_tab_stride3_arr_4096_q31[6]; @@ -131,15 +112,9 @@ extern const q31_t rearranged_twiddle_stride1_4096_q31[2728]; extern const q31_t rearranged_twiddle_stride2_4096_q31[2728]; extern const q31_t rearranged_twiddle_stride3_4096_q31[2728]; - - #endif /* defined(ARM_MATH_MVEI) */ - - -#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) - - +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) extern const uint32_t rearranged_twiddle_tab_stride1_arr_16_q15[2]; extern const uint32_t rearranged_twiddle_tab_stride2_arr_16_q15[2]; @@ -148,7 +123,6 @@ extern const q15_t rearranged_twiddle_stride1_16_q15[8]; extern const q15_t rearranged_twiddle_stride2_16_q15[8]; extern const q15_t rearranged_twiddle_stride3_16_q15[8]; - extern const uint32_t rearranged_twiddle_tab_stride1_arr_64_q15[3]; extern const uint32_t rearranged_twiddle_tab_stride2_arr_64_q15[3]; extern const uint32_t rearranged_twiddle_tab_stride3_arr_64_q15[3]; @@ -156,7 +130,6 @@ extern const q15_t rearranged_twiddle_stride1_64_q15[40]; extern const q15_t rearranged_twiddle_stride2_64_q15[40]; extern const q15_t rearranged_twiddle_stride3_64_q15[40]; - extern const uint32_t rearranged_twiddle_tab_stride1_arr_256_q15[4]; extern const uint32_t rearranged_twiddle_tab_stride2_arr_256_q15[4]; extern const uint32_t rearranged_twiddle_tab_stride3_arr_256_q15[4]; @@ -164,7 +137,6 @@ extern const q15_t rearranged_twiddle_stride1_256_q15[168]; extern const q15_t rearranged_twiddle_stride2_256_q15[168]; extern const q15_t rearranged_twiddle_stride3_256_q15[168]; - extern const uint32_t rearranged_twiddle_tab_stride1_arr_1024_q15[5]; extern const uint32_t rearranged_twiddle_tab_stride2_arr_1024_q15[5]; extern const uint32_t rearranged_twiddle_tab_stride3_arr_1024_q15[5]; @@ -172,7 +144,6 @@ extern const q15_t rearranged_twiddle_stride1_1024_q15[680]; extern const q15_t rearranged_twiddle_stride2_1024_q15[680]; extern const q15_t rearranged_twiddle_stride3_1024_q15[680]; - extern const uint32_t rearranged_twiddle_tab_stride1_arr_4096_q15[6]; extern const uint32_t rearranged_twiddle_tab_stride2_arr_4096_q15[6]; extern const uint32_t rearranged_twiddle_tab_stride3_arr_4096_q15[6]; @@ -180,14 +151,10 @@ extern const q15_t rearranged_twiddle_stride1_4096_q15[2728]; extern const q15_t rearranged_twiddle_stride2_4096_q15[2728]; extern const q15_t rearranged_twiddle_stride3_4096_q15[2728]; - #endif /* defined(ARM_MATH_MVEI) */ - - -#ifdef __cplusplus +#ifdef __cplusplus } #endif #endif /*_ARM_MVE_TABLES_H*/ - diff --git a/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/arm_mve_tables_f16.h b/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/arm_mve_tables_f16.h old mode 100755 new mode 100644 index ae2824529a3..f72b6969928 --- a/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/arm_mve_tables_f16.h +++ b/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/arm_mve_tables_f16.h @@ -27,23 +27,17 @@ * limitations under the License. */ - #ifndef ARM_MVE_TABLES_F16_H - #define ARM_MVE_TABLES_F16_H +#ifndef ARM_MVE_TABLES_F16_H +#define ARM_MVE_TABLES_F16_H #include "arm_math_types_f16.h" -#ifdef __cplusplus -extern "C" -{ +#ifdef __cplusplus +extern "C" { #endif - - - #if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) - - extern const uint32_t rearranged_twiddle_tab_stride1_arr_16_f16[2]; extern const uint32_t rearranged_twiddle_tab_stride2_arr_16_f16[2]; extern const uint32_t rearranged_twiddle_tab_stride3_arr_16_f16[2]; @@ -51,7 +45,6 @@ extern const float16_t rearranged_twiddle_stride1_16_f16[8]; extern const float16_t rearranged_twiddle_stride2_16_f16[8]; extern const float16_t rearranged_twiddle_stride3_16_f16[8]; - extern const uint32_t rearranged_twiddle_tab_stride1_arr_64_f16[3]; extern const uint32_t rearranged_twiddle_tab_stride2_arr_64_f16[3]; extern const uint32_t rearranged_twiddle_tab_stride3_arr_64_f16[3]; @@ -59,7 +52,6 @@ extern const float16_t rearranged_twiddle_stride1_64_f16[40]; extern const float16_t rearranged_twiddle_stride2_64_f16[40]; extern const float16_t rearranged_twiddle_stride3_64_f16[40]; - extern const uint32_t rearranged_twiddle_tab_stride1_arr_256_f16[4]; extern const uint32_t rearranged_twiddle_tab_stride2_arr_256_f16[4]; extern const uint32_t rearranged_twiddle_tab_stride3_arr_256_f16[4]; @@ -67,7 +59,6 @@ extern const float16_t rearranged_twiddle_stride1_256_f16[168]; extern const float16_t rearranged_twiddle_stride2_256_f16[168]; extern const float16_t rearranged_twiddle_stride3_256_f16[168]; - extern const uint32_t rearranged_twiddle_tab_stride1_arr_1024_f16[5]; extern const uint32_t rearranged_twiddle_tab_stride2_arr_1024_f16[5]; extern const uint32_t rearranged_twiddle_tab_stride3_arr_1024_f16[5]; @@ -75,7 +66,6 @@ extern const float16_t rearranged_twiddle_stride1_1024_f16[680]; extern const float16_t rearranged_twiddle_stride2_1024_f16[680]; extern const float16_t rearranged_twiddle_stride3_1024_f16[680]; - extern const uint32_t rearranged_twiddle_tab_stride1_arr_4096_f16[6]; extern const uint32_t rearranged_twiddle_tab_stride2_arr_4096_f16[6]; extern const uint32_t rearranged_twiddle_tab_stride3_arr_4096_f16[6]; @@ -83,15 +73,10 @@ extern const float16_t rearranged_twiddle_stride1_4096_f16[2728]; extern const float16_t rearranged_twiddle_stride2_4096_f16[2728]; extern const float16_t rearranged_twiddle_stride3_4096_f16[2728]; - - #endif /* defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) */ - - -#ifdef __cplusplus +#ifdef __cplusplus } #endif #endif /*_ARM_MVE_TABLES_F16_H*/ - diff --git a/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/arm_vec_math.h b/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/arm_vec_math.h old mode 100755 new mode 100644 index ec90802e09b..fd3d1ad786b --- a/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/arm_vec_math.h +++ b/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/arm_vec_math.h @@ -30,26 +30,23 @@ #include "arm_common_tables.h" #include "arm_helium_utils.h" -#ifdef __cplusplus -extern "C" -{ +#ifdef __cplusplus +extern "C" { #endif #if (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE) -#define INV_NEWTON_INIT_F32 0x7EF127EA - -static const float32_t __logf_rng_f32=0.693147180f; +#define INV_NEWTON_INIT_F32 0x7EF127EA +static const float32_t __logf_rng_f32 = 0.693147180f; /* fast inverse approximation (3x newton) */ -__STATIC_INLINE f32x4_t vrecip_medprec_f32( - f32x4_t x) +__STATIC_INLINE f32x4_t vrecip_medprec_f32(f32x4_t x) { - q31x4_t m; - f32x4_t b; - any32x4_t xinv; - f32x4_t ax = vabsq(x); + q31x4_t m; + f32x4_t b; + any32x4_t xinv; + f32x4_t ax = vabsq(x); xinv.f = ax; m = 0x3F800000 - (xinv.i & 0x7F800000); @@ -76,13 +73,12 @@ __STATIC_INLINE f32x4_t vrecip_medprec_f32( } /* fast inverse approximation (4x newton) */ -__STATIC_INLINE f32x4_t vrecip_hiprec_f32( - f32x4_t x) +__STATIC_INLINE f32x4_t vrecip_hiprec_f32(f32x4_t x) { - q31x4_t m; - f32x4_t b; - any32x4_t xinv; - f32x4_t ax = vabsq(x); + q31x4_t m; + f32x4_t b; + any32x4_t xinv; + f32x4_t ax = vabsq(x); xinv.f = ax; @@ -112,8 +108,7 @@ __STATIC_INLINE f32x4_t vrecip_hiprec_f32( return xinv.f; } -__STATIC_INLINE f32x4_t vdiv_f32( - f32x4_t num, f32x4_t den) +__STATIC_INLINE f32x4_t vdiv_f32(f32x4_t num, f32x4_t den) { return vmulq(num, vrecip_hiprec_f32(den)); } @@ -125,27 +120,23 @@ __STATIC_INLINE f32x4_t vdiv_f32( @return destination f32 quad vector */ -__STATIC_INLINE f32x4_t vtaylor_polyq_f32( - f32x4_t x, - const float32_t * coeffs) +__STATIC_INLINE f32x4_t vtaylor_polyq_f32(f32x4_t x, const float32_t *coeffs) { - f32x4_t A = vfmasq(vdupq_n_f32(coeffs[4]), x, coeffs[0]); - f32x4_t B = vfmasq(vdupq_n_f32(coeffs[6]), x, coeffs[2]); - f32x4_t C = vfmasq(vdupq_n_f32(coeffs[5]), x, coeffs[1]); - f32x4_t D = vfmasq(vdupq_n_f32(coeffs[7]), x, coeffs[3]); - f32x4_t x2 = vmulq(x, x); - f32x4_t x4 = vmulq(x2, x2); - f32x4_t res = vfmaq(vfmaq_f32(A, B, x2), vfmaq_f32(C, D, x2), x4); + f32x4_t A = vfmasq(vdupq_n_f32(coeffs[4]), x, coeffs[0]); + f32x4_t B = vfmasq(vdupq_n_f32(coeffs[6]), x, coeffs[2]); + f32x4_t C = vfmasq(vdupq_n_f32(coeffs[5]), x, coeffs[1]); + f32x4_t D = vfmasq(vdupq_n_f32(coeffs[7]), x, coeffs[3]); + f32x4_t x2 = vmulq(x, x); + f32x4_t x4 = vmulq(x2, x2); + f32x4_t res = vfmaq(vfmaq_f32(A, B, x2), vfmaq_f32(C, D, x2), x4); return res; } -__STATIC_INLINE f32x4_t vmant_exp_f32( - f32x4_t x, - int32x4_t * e) +__STATIC_INLINE f32x4_t vmant_exp_f32(f32x4_t x, int32x4_t *e) { - any32x4_t r; - int32x4_t n; + any32x4_t r; + int32x4_t n; r.f = x; n = r.i >> 23; @@ -156,13 +147,12 @@ __STATIC_INLINE f32x4_t vmant_exp_f32( return r.f; } - __STATIC_INLINE f32x4_t vlogq_f32(f32x4_t vecIn) { - q31x4_t vecExpUnBiased; - f32x4_t vecTmpFlt0, vecTmpFlt1; - f32x4_t vecAcc0, vecAcc1, vecAcc2, vecAcc3; - f32x4_t vecExpUnBiasedFlt; + q31x4_t vecExpUnBiased; + f32x4_t vecTmpFlt0, vecTmpFlt1; + f32x4_t vecAcc0, vecAcc1, vecAcc2, vecAcc3; + f32x4_t vecExpUnBiasedFlt; /* * extract exponent @@ -217,18 +207,17 @@ __STATIC_INLINE f32x4_t vlogq_f32(f32x4_t vecIn) return vecAcc0; } -__STATIC_INLINE f32x4_t vexpq_f32( - f32x4_t x) +__STATIC_INLINE f32x4_t vexpq_f32(f32x4_t x) { // Perform range reduction [-log(2),log(2)] - int32x4_t m = vcvtq_s32_f32(vmulq_n_f32(x, 1.4426950408f)); - f32x4_t val = vfmsq_f32(x, vcvtq_f32_s32(m), vdupq_n_f32(0.6931471805f)); + int32x4_t m = vcvtq_s32_f32(vmulq_n_f32(x, 1.4426950408f)); + f32x4_t val = vfmsq_f32(x, vcvtq_f32_s32(m), vdupq_n_f32(0.6931471805f)); // Polynomial Approximation - f32x4_t poly = vtaylor_polyq_f32(val, exp_tab); + f32x4_t poly = vtaylor_polyq_f32(val, exp_tab); // Reconstruct - poly = (f32x4_t) (vqaddq_s32((q31x4_t) (poly), vqshlq_n_s32(m, 23))); + poly = (f32x4_t)(vqaddq_s32((q31x4_t)(poly), vqshlq_n_s32(m, 23))); poly = vdupq_m(poly, 0.0f, vcmpltq_n_s32(m, -126)); return poly; @@ -236,7 +225,7 @@ __STATIC_INLINE f32x4_t vexpq_f32( __STATIC_INLINE f32x4_t arm_vec_exponent_f32(f32x4_t x, int32_t nb) { - f32x4_t r = x; + f32x4_t r = x; nb--; while (nb > 0) { r = vmulq(r, x); @@ -247,8 +236,8 @@ __STATIC_INLINE f32x4_t arm_vec_exponent_f32(f32x4_t x, int32_t nb) __STATIC_INLINE f32x4_t vrecip_f32(f32x4_t vecIn) { - f32x4_t vecSx, vecW, vecTmp; - any32x4_t v; + f32x4_t vecSx, vecW, vecTmp; + any32x4_t v; vecSx = vabsq(vecIn); @@ -265,7 +254,7 @@ __STATIC_INLINE f32x4_t vrecip_f32(f32x4_t vecIn) vecTmp = vfmasq(vecW, vecTmp, 56.0f); vecTmp = vfmasq(vecW, vecTmp, -28.0f); vecTmp = vfmasq(vecW, vecTmp, 8.0f); - v.f = vmulq(v.f, vecTmp); + v.f = vmulq(v.f, vecTmp); v.f = vdupq_m(v.f, F32_MAX, vcmpeqq(vecIn, 0.0f)); /* @@ -275,21 +264,17 @@ __STATIC_INLINE f32x4_t vrecip_f32(f32x4_t vecIn) return v.f; } -__STATIC_INLINE f32x4_t vtanhq_f32( - f32x4_t val) +__STATIC_INLINE f32x4_t vtanhq_f32(f32x4_t val) { - f32x4_t x = - vminnmq_f32(vmaxnmq_f32(val, vdupq_n_f32(-10.f)), vdupq_n_f32(10.0f)); - f32x4_t exp2x = vexpq_f32(vmulq_n_f32(x, 2.f)); - f32x4_t num = vsubq_n_f32(exp2x, 1.f); - f32x4_t den = vaddq_n_f32(exp2x, 1.f); - f32x4_t tanh = vmulq_f32(num, vrecip_f32(den)); + f32x4_t x = vminnmq_f32(vmaxnmq_f32(val, vdupq_n_f32(-10.f)), vdupq_n_f32(10.0f)); + f32x4_t exp2x = vexpq_f32(vmulq_n_f32(x, 2.f)); + f32x4_t num = vsubq_n_f32(exp2x, 1.f); + f32x4_t den = vaddq_n_f32(exp2x, 1.f); + f32x4_t tanh = vmulq_f32(num, vrecip_f32(den)); return tanh; } -__STATIC_INLINE f32x4_t vpowq_f32( - f32x4_t val, - f32x4_t n) +__STATIC_INLINE f32x4_t vpowq_f32(f32x4_t val, f32x4_t n) { return vexpq_f32(vmulq_f32(n, vlogq_f32(val))); } @@ -299,7 +284,8 @@ __STATIC_INLINE f32x4_t vpowq_f32( #if (defined(ARM_MATH_MVEI) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE) #endif /* (defined(ARM_MATH_MVEI) || defined(ARM_MATH_HELIUM)) */ -#if (defined(ARM_MATH_NEON) || defined(ARM_MATH_NEON_EXPERIMENTAL)) && !defined(ARM_MATH_AUTOVECTORIZE) +#if (defined(ARM_MATH_NEON) || defined(ARM_MATH_NEON_EXPERIMENTAL)) && \ + !defined(ARM_MATH_AUTOVECTORIZE) #include "NEMath.h" /** @@ -309,20 +295,18 @@ __STATIC_INLINE f32x4_t vpowq_f32( * @return x^nb * */ -__STATIC_INLINE float32x4_t arm_vec_exponent_f32(float32x4_t x, int32_t nb) +__STATIC_INLINE float32x4_t arm_vec_exponent_f32(float32x4_t x, int32_t nb) { float32x4_t r = x; - nb --; - while(nb > 0) - { - r = vmulq_f32(r , x); + nb--; + while (nb > 0) { + r = vmulq_f32(r, x); nb--; } - return(r); + return (r); } - -__STATIC_INLINE float32x4_t __arm_vec_sqrt_f32_neon(float32x4_t x) +__STATIC_INLINE float32x4_t __arm_vec_sqrt_f32_neon(float32x4_t x) { float32x4_t x1 = vmaxq_f32(x, vdupq_n_f32(FLT_MIN)); float32x4_t e = vrsqrteq_f32(x1); @@ -334,37 +318,36 @@ __STATIC_INLINE float32x4_t __arm_vec_sqrt_f32_neon(float32x4_t x) __STATIC_INLINE int16x8_t __arm_vec_sqrt_q15_neon(int16x8_t vec) { float32x4_t tempF; - int32x4_t tempHI,tempLO; + int32x4_t tempHI, tempLO; tempLO = vmovl_s16(vget_low_s16(vec)); - tempF = vcvtq_n_f32_s32(tempLO,15); + tempF = vcvtq_n_f32_s32(tempLO, 15); tempF = __arm_vec_sqrt_f32_neon(tempF); - tempLO = vcvtq_n_s32_f32(tempF,15); + tempLO = vcvtq_n_s32_f32(tempF, 15); tempHI = vmovl_s16(vget_high_s16(vec)); - tempF = vcvtq_n_f32_s32(tempHI,15); + tempF = vcvtq_n_f32_s32(tempHI, 15); tempF = __arm_vec_sqrt_f32_neon(tempF); - tempHI = vcvtq_n_s32_f32(tempF,15); + tempHI = vcvtq_n_s32_f32(tempF, 15); - return(vcombine_s16(vqmovn_s32(tempLO),vqmovn_s32(tempHI))); + return (vcombine_s16(vqmovn_s32(tempLO), vqmovn_s32(tempHI))); } __STATIC_INLINE int32x4_t __arm_vec_sqrt_q31_neon(int32x4_t vec) { - float32x4_t temp; + float32x4_t temp; - temp = vcvtq_n_f32_s32(vec,31); - temp = __arm_vec_sqrt_f32_neon(temp); - return(vcvtq_n_s32_f32(temp,31)); + temp = vcvtq_n_f32_s32(vec, 31); + temp = __arm_vec_sqrt_f32_neon(temp); + return (vcvtq_n_s32_f32(temp, 31)); } #endif /* (defined(ARM_MATH_NEON) || defined(ARM_MATH_NEON_EXPERIMENTAL)) && !defined(ARM_MATH_AUTOVECTORIZE) */ -#ifdef __cplusplus +#ifdef __cplusplus } #endif - #endif /* _ARM_VEC_MATH_H */ /** diff --git a/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/arm_vec_math_f16.h b/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/arm_vec_math_f16.h old mode 100755 new mode 100644 index 70e503d66e2..50bd8941129 --- a/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/arm_vec_math_f16.h +++ b/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/arm_vec_math_f16.h @@ -30,27 +30,23 @@ #include "arm_common_tables_f16.h" #include "arm_helium_utils.h" -#ifdef __cplusplus -extern "C" -{ +#ifdef __cplusplus +extern "C" { #endif #if defined(ARM_FLOAT16_SUPPORTED) - #if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) - -static const float16_t __logf_rng_f16=0.693147180f16; +static const float16_t __logf_rng_f16 = 0.693147180f16; /* fast inverse approximation (3x newton) */ -__STATIC_INLINE f16x8_t vrecip_medprec_f16( - f16x8_t x) +__STATIC_INLINE f16x8_t vrecip_medprec_f16(f16x8_t x) { - q15x8_t m; - f16x8_t b; - any16x8_t xinv; - f16x8_t ax = vabsq(x); + q15x8_t m; + f16x8_t b; + any16x8_t xinv; + f16x8_t ax = vabsq(x); xinv.f = ax; @@ -78,13 +74,12 @@ __STATIC_INLINE f16x8_t vrecip_medprec_f16( } /* fast inverse approximation (4x newton) */ -__STATIC_INLINE f16x8_t vrecip_hiprec_f16( - f16x8_t x) +__STATIC_INLINE f16x8_t vrecip_hiprec_f16(f16x8_t x) { - q15x8_t m; - f16x8_t b; - any16x8_t xinv; - f16x8_t ax = vabsq(x); + q15x8_t m; + f16x8_t b; + any16x8_t xinv; + f16x8_t ax = vabsq(x); xinv.f = ax; @@ -114,13 +109,11 @@ __STATIC_INLINE f16x8_t vrecip_hiprec_f16( return xinv.f; } -__STATIC_INLINE f16x8_t vdiv_f16( - f16x8_t num, f16x8_t den) +__STATIC_INLINE f16x8_t vdiv_f16(f16x8_t num, f16x8_t den) { return vmulq(num, vrecip_hiprec_f16(den)); } - /** @brief Single-precision taylor dev. @param[in] x f16 vector input @@ -128,39 +121,37 @@ __STATIC_INLINE f16x8_t vdiv_f16( @return destination f16 vector */ -__STATIC_INLINE float16x8_t vtaylor_polyq_f16( - float16x8_t x, - const float16_t * coeffs) +__STATIC_INLINE float16x8_t vtaylor_polyq_f16(float16x8_t x, const float16_t *coeffs) { - float16x8_t A = vfmasq(vdupq_n_f16(coeffs[4]), x, coeffs[0]); - float16x8_t B = vfmasq(vdupq_n_f16(coeffs[6]), x, coeffs[2]); - float16x8_t C = vfmasq(vdupq_n_f16(coeffs[5]), x, coeffs[1]); - float16x8_t D = vfmasq(vdupq_n_f16(coeffs[7]), x, coeffs[3]); - float16x8_t x2 = vmulq(x, x); - float16x8_t x4 = vmulq(x2, x2); - float16x8_t res = vfmaq(vfmaq_f16(A, B, x2), vfmaq_f16(C, D, x2), x4); + float16x8_t A = vfmasq(vdupq_n_f16(coeffs[4]), x, coeffs[0]); + float16x8_t B = vfmasq(vdupq_n_f16(coeffs[6]), x, coeffs[2]); + float16x8_t C = vfmasq(vdupq_n_f16(coeffs[5]), x, coeffs[1]); + float16x8_t D = vfmasq(vdupq_n_f16(coeffs[7]), x, coeffs[3]); + float16x8_t x2 = vmulq(x, x); + float16x8_t x4 = vmulq(x2, x2); + float16x8_t res = vfmaq(vfmaq_f16(A, B, x2), vfmaq_f16(C, D, x2), x4); return res; } -#define VMANT_EXP_F16(x) \ - any16x8_t r; \ - int16x8_t n; \ - \ - r.f = x; \ - n = r.i >> 10; \ - n = n - 15; \ - r.i = r.i - (n << 10);\ - \ - vecExpUnBiased = n; \ +#define VMANT_EXP_F16(x) \ + any16x8_t r; \ + int16x8_t n; \ + \ + r.f = x; \ + n = r.i >> 10; \ + n = n - 15; \ + r.i = r.i - (n << 10); \ + \ + vecExpUnBiased = n; \ vecTmpFlt1 = r.f; __STATIC_INLINE float16x8_t vlogq_f16(float16x8_t vecIn) { - q15x8_t vecExpUnBiased; - float16x8_t vecTmpFlt0, vecTmpFlt1; - float16x8_t vecAcc0, vecAcc1, vecAcc2, vecAcc3; - float16x8_t vecExpUnBiasedFlt; + q15x8_t vecExpUnBiased; + float16x8_t vecTmpFlt0, vecTmpFlt1; + float16x8_t vecAcc0, vecAcc1, vecAcc2, vecAcc3; + float16x8_t vecExpUnBiasedFlt; /* * extract exponent @@ -215,18 +206,17 @@ __STATIC_INLINE float16x8_t vlogq_f16(float16x8_t vecIn) return vecAcc0; } -__STATIC_INLINE float16x8_t vexpq_f16( - float16x8_t x) +__STATIC_INLINE float16x8_t vexpq_f16(float16x8_t x) { // Perform range reduction [-log(2),log(2)] - int16x8_t m = vcvtq_s16_f16(vmulq_n_f16(x, 1.4426950408f16)); - float16x8_t val = vfmsq_f16(x, vcvtq_f16_s16(m), vdupq_n_f16(0.6931471805f16)); + int16x8_t m = vcvtq_s16_f16(vmulq_n_f16(x, 1.4426950408f16)); + float16x8_t val = vfmsq_f16(x, vcvtq_f16_s16(m), vdupq_n_f16(0.6931471805f16)); // Polynomial Approximation - float16x8_t poly = vtaylor_polyq_f16(val, exp_tab_f16); + float16x8_t poly = vtaylor_polyq_f16(val, exp_tab_f16); // Reconstruct - poly = (float16x8_t) (vqaddq_s16((int16x8_t) (poly), vqshlq_n_s16(m, 10))); + poly = (float16x8_t)(vqaddq_s16((int16x8_t)(poly), vqshlq_n_s16(m, 10))); poly = vdupq_m_n_f16(poly, 0.0f16, vcmpltq_n_s16(m, -14)); return poly; @@ -234,7 +224,7 @@ __STATIC_INLINE float16x8_t vexpq_f16( __STATIC_INLINE float16x8_t arm_vec_exponent_f16(float16x8_t x, int16_t nb) { - float16x8_t r = x; + float16x8_t r = x; nb--; while (nb > 0) { r = vmulq(r, x); @@ -243,19 +233,17 @@ __STATIC_INLINE float16x8_t arm_vec_exponent_f16(float16x8_t x, int16_t nb) return (r); } -__STATIC_INLINE f16x8_t vpowq_f16( - f16x8_t val, - f16x8_t n) +__STATIC_INLINE f16x8_t vpowq_f16(f16x8_t val, f16x8_t n) { return vexpq_f16(vmulq_f16(n, vlogq_f16(val))); } -#define INV_NEWTON_INIT_F16 0x7773 +#define INV_NEWTON_INIT_F16 0x7773 __STATIC_INLINE f16x8_t vrecip_f16(f16x8_t vecIn) { - f16x8_t vecSx, vecW, vecTmp; - any16x8_t v; + f16x8_t vecSx, vecW, vecTmp; + any16x8_t v; vecSx = vabsq(vecIn); @@ -272,7 +260,7 @@ __STATIC_INLINE f16x8_t vrecip_f16(f16x8_t vecIn) vecTmp = vfmasq_n_f16(vecW, vecTmp, 56.0f16); vecTmp = vfmasq_n_f16(vecW, vecTmp, -28.0f16); vecTmp = vfmasq_n_f16(vecW, vecTmp, 8.0f16); - v.f = vmulq(v.f, vecTmp); + v.f = vmulq(v.f, vecTmp); v.f = vdupq_m_n_f16(v.f, F16INFINITY, vcmpeqq_n_f16(vecIn, 0.0f)); /* @@ -282,23 +270,19 @@ __STATIC_INLINE f16x8_t vrecip_f16(f16x8_t vecIn) return v.f; } -__STATIC_INLINE f16x8_t vtanhq_f16( - f16x8_t val) +__STATIC_INLINE f16x8_t vtanhq_f16(f16x8_t val) { - f16x8_t x = - vminnmq_f16(vmaxnmq_f16(val, vdupq_n_f16(-10.f16)), vdupq_n_f16(10.0f16)); - f16x8_t exp2x = vexpq_f16(vmulq_n_f16(x, 2.f16)); - f16x8_t num = vsubq_n_f16(exp2x, 1.f16); - f16x8_t den = vaddq_n_f16(exp2x, 1.f16); - f16x8_t tanh = vmulq_f16(num, vrecip_f16(den)); + f16x8_t x = vminnmq_f16(vmaxnmq_f16(val, vdupq_n_f16(-10.f16)), vdupq_n_f16(10.0f16)); + f16x8_t exp2x = vexpq_f16(vmulq_n_f16(x, 2.f16)); + f16x8_t num = vsubq_n_f16(exp2x, 1.f16); + f16x8_t den = vaddq_n_f16(exp2x, 1.f16); + f16x8_t tanh = vmulq_f16(num, vrecip_f16(den)); return tanh; } #endif /* defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE)*/ - - -#ifdef __cplusplus +#ifdef __cplusplus } #endif diff --git a/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/basic_math_functions.h b/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/basic_math_functions.h old mode 100755 new mode 100644 index 645afdc3b94..b445a6cce10 --- a/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/basic_math_functions.h +++ b/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/basic_math_functions.h @@ -23,7 +23,6 @@ * limitations under the License. */ - #ifndef BASIC_MATH_FUNCTIONS_H_ #define BASIC_MATH_FUNCTIONS_H_ @@ -33,72 +32,50 @@ #include "dsp/none.h" #include "dsp/utils.h" - -#ifdef __cplusplus -extern "C" -{ +#ifdef __cplusplus +extern "C" { #endif /** * @defgroup groupMath Basic Math Functions */ - /** +/** * @brief Q7 vector multiplication. * @param[in] pSrcA points to the first input vector * @param[in] pSrcB points to the second input vector * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in each vector */ - void arm_mult_q7( - const q7_t * pSrcA, - const q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); +void arm_mult_q7(const q7_t *pSrcA, const q7_t *pSrcB, q7_t *pDst, uint32_t blockSize); - - /** +/** * @brief Q15 vector multiplication. * @param[in] pSrcA points to the first input vector * @param[in] pSrcB points to the second input vector * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in each vector */ - void arm_mult_q15( - const q15_t * pSrcA, - const q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); +void arm_mult_q15(const q15_t *pSrcA, const q15_t *pSrcB, q15_t *pDst, uint32_t blockSize); - - /** +/** * @brief Q31 vector multiplication. * @param[in] pSrcA points to the first input vector * @param[in] pSrcB points to the second input vector * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in each vector */ - void arm_mult_q31( - const q31_t * pSrcA, - const q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - +void arm_mult_q31(const q31_t *pSrcA, const q31_t *pSrcB, q31_t *pDst, uint32_t blockSize); - /** +/** * @brief Floating-point vector multiplication. * @param[in] pSrcA points to the first input vector * @param[in] pSrcB points to the second input vector * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in each vector */ - void arm_mult_f32( - const float32_t * pSrcA, - const float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - +void arm_mult_f32(const float32_t *pSrcA, const float32_t *pSrcB, float32_t *pDst, + uint32_t blockSize); /** * @brief Floating-point vector multiplication. @@ -107,28 +84,18 @@ extern "C" * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in each vector */ -void arm_mult_f64( -const float64_t * pSrcA, -const float64_t * pSrcB, - float64_t * pDst, - uint32_t blockSize); - +void arm_mult_f64(const float64_t *pSrcA, const float64_t *pSrcB, float64_t *pDst, + uint32_t blockSize); - - /** +/** * @brief Floating-point vector addition. * @param[in] pSrcA points to the first input vector * @param[in] pSrcB points to the second input vector * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in each vector */ - void arm_add_f32( - const float32_t * pSrcA, - const float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - +void arm_add_f32(const float32_t *pSrcA, const float32_t *pSrcB, float32_t *pDst, + uint32_t blockSize); /** * @brief Floating-point vector addition. @@ -137,159 +104,102 @@ const float64_t * pSrcB, * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in each vector */ - void arm_add_f64( - const float64_t * pSrcA, - const float64_t * pSrcB, - float64_t * pDst, - uint32_t blockSize); - +void arm_add_f64(const float64_t *pSrcA, const float64_t *pSrcB, float64_t *pDst, + uint32_t blockSize); - - /** +/** * @brief Q7 vector addition. * @param[in] pSrcA points to the first input vector * @param[in] pSrcB points to the second input vector * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in each vector */ - void arm_add_q7( - const q7_t * pSrcA, - const q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); +void arm_add_q7(const q7_t *pSrcA, const q7_t *pSrcB, q7_t *pDst, uint32_t blockSize); - - /** +/** * @brief Q15 vector addition. * @param[in] pSrcA points to the first input vector * @param[in] pSrcB points to the second input vector * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in each vector */ - void arm_add_q15( - const q15_t * pSrcA, - const q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - +void arm_add_q15(const q15_t *pSrcA, const q15_t *pSrcB, q15_t *pDst, uint32_t blockSize); - /** +/** * @brief Q31 vector addition. * @param[in] pSrcA points to the first input vector * @param[in] pSrcB points to the second input vector * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in each vector */ - void arm_add_q31( - const q31_t * pSrcA, - const q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - +void arm_add_q31(const q31_t *pSrcA, const q31_t *pSrcB, q31_t *pDst, uint32_t blockSize); - /** +/** * @brief Floating-point vector subtraction. * @param[in] pSrcA points to the first input vector * @param[in] pSrcB points to the second input vector * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in each vector */ - void arm_sub_f32( - const float32_t * pSrcA, - const float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - +void arm_sub_f32(const float32_t *pSrcA, const float32_t *pSrcB, float32_t *pDst, + uint32_t blockSize); - - /** +/** * @brief Floating-point vector subtraction. * @param[in] pSrcA points to the first input vector * @param[in] pSrcB points to the second input vector * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in each vector */ - void arm_sub_f64( - const float64_t * pSrcA, - const float64_t * pSrcB, - float64_t * pDst, - uint32_t blockSize); - +void arm_sub_f64(const float64_t *pSrcA, const float64_t *pSrcB, float64_t *pDst, + uint32_t blockSize); - - /** +/** * @brief Q7 vector subtraction. * @param[in] pSrcA points to the first input vector * @param[in] pSrcB points to the second input vector * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in each vector */ - void arm_sub_q7( - const q7_t * pSrcA, - const q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); +void arm_sub_q7(const q7_t *pSrcA, const q7_t *pSrcB, q7_t *pDst, uint32_t blockSize); - - /** +/** * @brief Q15 vector subtraction. * @param[in] pSrcA points to the first input vector * @param[in] pSrcB points to the second input vector * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in each vector */ - void arm_sub_q15( - const q15_t * pSrcA, - const q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); +void arm_sub_q15(const q15_t *pSrcA, const q15_t *pSrcB, q15_t *pDst, uint32_t blockSize); - - /** +/** * @brief Q31 vector subtraction. * @param[in] pSrcA points to the first input vector * @param[in] pSrcB points to the second input vector * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in each vector */ - void arm_sub_q31( - const q31_t * pSrcA, - const q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - +void arm_sub_q31(const q31_t *pSrcA, const q31_t *pSrcB, q31_t *pDst, uint32_t blockSize); - /** +/** * @brief Multiplies a floating-point vector by a scalar. * @param[in] pSrc points to the input vector * @param[in] scale scale factor to be applied * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in the vector */ - void arm_scale_f32( - const float32_t * pSrc, - float32_t scale, - float32_t * pDst, - uint32_t blockSize); - +void arm_scale_f32(const float32_t *pSrc, float32_t scale, float32_t *pDst, uint32_t blockSize); - - /** +/** * @brief Multiplies a floating-point vector by a scalar. * @param[in] pSrc points to the input vector * @param[in] scale scale factor to be applied * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in the vector */ - void arm_scale_f64( - const float64_t * pSrc, - float64_t scale, - float64_t * pDst, - uint32_t blockSize); +void arm_scale_f64(const float64_t *pSrc, float64_t scale, float64_t *pDst, uint32_t blockSize); - - - /** +/** * @brief Multiplies a Q7 vector by a scalar. * @param[in] pSrc points to the input vector * @param[in] scaleFract fractional portion of the scale value @@ -297,15 +207,9 @@ const float64_t * pSrcB, * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in the vector */ - void arm_scale_q7( - const q7_t * pSrc, - q7_t scaleFract, - int8_t shift, - q7_t * pDst, - uint32_t blockSize); +void arm_scale_q7(const q7_t *pSrc, q7_t scaleFract, int8_t shift, q7_t *pDst, uint32_t blockSize); - - /** +/** * @brief Multiplies a Q15 vector by a scalar. * @param[in] pSrc points to the input vector * @param[in] scaleFract fractional portion of the scale value @@ -313,15 +217,10 @@ const float64_t * pSrcB, * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in the vector */ - void arm_scale_q15( - const q15_t * pSrc, - q15_t scaleFract, - int8_t shift, - q15_t * pDst, - uint32_t blockSize); +void arm_scale_q15(const q15_t *pSrc, q15_t scaleFract, int8_t shift, q15_t *pDst, + uint32_t blockSize); - - /** +/** * @brief Multiplies a Q31 vector by a scalar. * @param[in] pSrc points to the input vector * @param[in] scaleFract fractional portion of the scale value @@ -329,38 +228,24 @@ const float64_t * pSrcB, * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in the vector */ - void arm_scale_q31( - const q31_t * pSrc, - q31_t scaleFract, - int8_t shift, - q31_t * pDst, - uint32_t blockSize); +void arm_scale_q31(const q31_t *pSrc, q31_t scaleFract, int8_t shift, q31_t *pDst, + uint32_t blockSize); - - /** +/** * @brief Q7 vector absolute value. * @param[in] pSrc points to the input buffer * @param[out] pDst points to the output buffer * @param[in] blockSize number of samples in each vector */ - void arm_abs_q7( - const q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - +void arm_abs_q7(const q7_t *pSrc, q7_t *pDst, uint32_t blockSize); - /** +/** * @brief Floating-point vector absolute value. * @param[in] pSrc points to the input buffer * @param[out] pDst points to the output buffer * @param[in] blockSize number of samples in each vector */ - void arm_abs_f32( - const float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - +void arm_abs_f32(const float32_t *pSrc, float32_t *pDst, uint32_t blockSize); /** * @brief Floating-point vector absolute value. @@ -368,51 +253,33 @@ const float64_t * pSrcB, * @param[out] pDst points to the output buffer * @param[in] blockSize number of samples in each vector */ -void arm_abs_f64( -const float64_t * pSrc, - float64_t * pDst, - uint32_t blockSize); - +void arm_abs_f64(const float64_t *pSrc, float64_t *pDst, uint32_t blockSize); - - /** +/** * @brief Q15 vector absolute value. * @param[in] pSrc points to the input buffer * @param[out] pDst points to the output buffer * @param[in] blockSize number of samples in each vector */ - void arm_abs_q15( - const q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - +void arm_abs_q15(const q15_t *pSrc, q15_t *pDst, uint32_t blockSize); - /** +/** * @brief Q31 vector absolute value. * @param[in] pSrc points to the input buffer * @param[out] pDst points to the output buffer * @param[in] blockSize number of samples in each vector */ - void arm_abs_q31( - const q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - +void arm_abs_q31(const q31_t *pSrc, q31_t *pDst, uint32_t blockSize); - /** +/** * @brief Dot product of floating-point vectors. * @param[in] pSrcA points to the first input vector * @param[in] pSrcB points to the second input vector * @param[in] blockSize number of samples in each vector * @param[out] result output result returned here */ - void arm_dot_prod_f32( - const float32_t * pSrcA, - const float32_t * pSrcB, - uint32_t blockSize, - float32_t * result); - - +void arm_dot_prod_f32(const float32_t *pSrcA, const float32_t *pSrcB, uint32_t blockSize, + float32_t *result); /** * @brief Dot product of floating-point vectors. @@ -421,97 +288,62 @@ const float64_t * pSrc, * @param[in] blockSize number of samples in each vector * @param[out] result output result returned here */ -void arm_dot_prod_f64( -const float64_t * pSrcA, -const float64_t * pSrcB, - uint32_t blockSize, - float64_t * result); - - +void arm_dot_prod_f64(const float64_t *pSrcA, const float64_t *pSrcB, uint32_t blockSize, + float64_t *result); - /** +/** * @brief Dot product of Q7 vectors. * @param[in] pSrcA points to the first input vector * @param[in] pSrcB points to the second input vector * @param[in] blockSize number of samples in each vector * @param[out] result output result returned here */ - void arm_dot_prod_q7( - const q7_t * pSrcA, - const q7_t * pSrcB, - uint32_t blockSize, - q31_t * result); - +void arm_dot_prod_q7(const q7_t *pSrcA, const q7_t *pSrcB, uint32_t blockSize, q31_t *result); - /** +/** * @brief Dot product of Q15 vectors. * @param[in] pSrcA points to the first input vector * @param[in] pSrcB points to the second input vector * @param[in] blockSize number of samples in each vector * @param[out] result output result returned here */ - void arm_dot_prod_q15( - const q15_t * pSrcA, - const q15_t * pSrcB, - uint32_t blockSize, - q63_t * result); - +void arm_dot_prod_q15(const q15_t *pSrcA, const q15_t *pSrcB, uint32_t blockSize, q63_t *result); - /** +/** * @brief Dot product of Q31 vectors. * @param[in] pSrcA points to the first input vector * @param[in] pSrcB points to the second input vector * @param[in] blockSize number of samples in each vector * @param[out] result output result returned here */ - void arm_dot_prod_q31( - const q31_t * pSrcA, - const q31_t * pSrcB, - uint32_t blockSize, - q63_t * result); - +void arm_dot_prod_q31(const q31_t *pSrcA, const q31_t *pSrcB, uint32_t blockSize, q63_t *result); - /** +/** * @brief Shifts the elements of a Q7 vector a specified number of bits. * @param[in] pSrc points to the input vector * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in the vector */ - void arm_shift_q7( - const q7_t * pSrc, - int8_t shiftBits, - q7_t * pDst, - uint32_t blockSize); +void arm_shift_q7(const q7_t *pSrc, int8_t shiftBits, q7_t *pDst, uint32_t blockSize); - - /** +/** * @brief Shifts the elements of a Q15 vector a specified number of bits. * @param[in] pSrc points to the input vector * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in the vector */ - void arm_shift_q15( - const q15_t * pSrc, - int8_t shiftBits, - q15_t * pDst, - uint32_t blockSize); +void arm_shift_q15(const q15_t *pSrc, int8_t shiftBits, q15_t *pDst, uint32_t blockSize); - - /** +/** * @brief Shifts the elements of a Q31 vector a specified number of bits. * @param[in] pSrc points to the input vector * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in the vector */ - void arm_shift_q31( - const q31_t * pSrc, - int8_t shiftBits, - q31_t * pDst, - uint32_t blockSize); - +void arm_shift_q31(const q31_t *pSrc, int8_t shiftBits, q31_t *pDst, uint32_t blockSize); /** * @brief Adds a constant offset to a floating-point vector. @@ -520,83 +352,51 @@ const float64_t * pSrcB, * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in the vector */ -void arm_offset_f64( -const float64_t * pSrc, - float64_t offset, - float64_t * pDst, - uint32_t blockSize); - - +void arm_offset_f64(const float64_t *pSrc, float64_t offset, float64_t *pDst, uint32_t blockSize); - /** +/** * @brief Adds a constant offset to a floating-point vector. * @param[in] pSrc points to the input vector * @param[in] offset is the offset to be added * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in the vector */ - void arm_offset_f32( - const float32_t * pSrc, - float32_t offset, - float32_t * pDst, - uint32_t blockSize); - +void arm_offset_f32(const float32_t *pSrc, float32_t offset, float32_t *pDst, uint32_t blockSize); - - /** +/** * @brief Adds a constant offset to a Q7 vector. * @param[in] pSrc points to the input vector * @param[in] offset is the offset to be added * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in the vector */ - void arm_offset_q7( - const q7_t * pSrc, - q7_t offset, - q7_t * pDst, - uint32_t blockSize); +void arm_offset_q7(const q7_t *pSrc, q7_t offset, q7_t *pDst, uint32_t blockSize); - - /** +/** * @brief Adds a constant offset to a Q15 vector. * @param[in] pSrc points to the input vector * @param[in] offset is the offset to be added * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in the vector */ - void arm_offset_q15( - const q15_t * pSrc, - q15_t offset, - q15_t * pDst, - uint32_t blockSize); - +void arm_offset_q15(const q15_t *pSrc, q15_t offset, q15_t *pDst, uint32_t blockSize); - /** +/** * @brief Adds a constant offset to a Q31 vector. * @param[in] pSrc points to the input vector * @param[in] offset is the offset to be added * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in the vector */ - void arm_offset_q31( - const q31_t * pSrc, - q31_t offset, - q31_t * pDst, - uint32_t blockSize); - +void arm_offset_q31(const q31_t *pSrc, q31_t offset, q31_t *pDst, uint32_t blockSize); - /** +/** * @brief Negates the elements of a floating-point vector. * @param[in] pSrc points to the input vector * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in the vector */ - void arm_negate_f32( - const float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - +void arm_negate_f32(const float32_t *pSrc, float32_t *pDst, uint32_t blockSize); /** * @brief Negates the elements of a floating-point vector. @@ -604,47 +404,31 @@ const float64_t * pSrc, * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in the vector */ -void arm_negate_f64( -const float64_t * pSrc, - float64_t * pDst, - uint32_t blockSize); - - +void arm_negate_f64(const float64_t *pSrc, float64_t *pDst, uint32_t blockSize); - /** +/** * @brief Negates the elements of a Q7 vector. * @param[in] pSrc points to the input vector * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in the vector */ - void arm_negate_q7( - const q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - +void arm_negate_q7(const q7_t *pSrc, q7_t *pDst, uint32_t blockSize); - /** +/** * @brief Negates the elements of a Q15 vector. * @param[in] pSrc points to the input vector * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in the vector */ - void arm_negate_q15( - const q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - +void arm_negate_q15(const q15_t *pSrc, q15_t *pDst, uint32_t blockSize); - /** +/** * @brief Negates the elements of a Q31 vector. * @param[in] pSrc points to the input vector * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in the vector */ - void arm_negate_q31( - const q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); +void arm_negate_q31(const q31_t *pSrc, q31_t *pDst, uint32_t blockSize); /** * @brief Compute the logical bitwise AND of two fixed-point vectors. @@ -653,109 +437,76 @@ const float64_t * pSrc, * @param[out] pDst points to output vector * @param[in] blockSize number of samples in each vector */ - void arm_and_u16( - const uint16_t * pSrcA, - const uint16_t * pSrcB, - uint16_t * pDst, - uint32_t blockSize); +void arm_and_u16(const uint16_t *pSrcA, const uint16_t *pSrcB, uint16_t *pDst, uint32_t blockSize); - /** +/** * @brief Compute the logical bitwise AND of two fixed-point vectors. * @param[in] pSrcA points to input vector A * @param[in] pSrcB points to input vector B * @param[out] pDst points to output vector * @param[in] blockSize number of samples in each vector */ - void arm_and_u32( - const uint32_t * pSrcA, - const uint32_t * pSrcB, - uint32_t * pDst, - uint32_t blockSize); +void arm_and_u32(const uint32_t *pSrcA, const uint32_t *pSrcB, uint32_t *pDst, uint32_t blockSize); - /** +/** * @brief Compute the logical bitwise AND of two fixed-point vectors. * @param[in] pSrcA points to input vector A * @param[in] pSrcB points to input vector B * @param[out] pDst points to output vector * @param[in] blockSize number of samples in each vector */ - void arm_and_u8( - const uint8_t * pSrcA, - const uint8_t * pSrcB, - uint8_t * pDst, - uint32_t blockSize); +void arm_and_u8(const uint8_t *pSrcA, const uint8_t *pSrcB, uint8_t *pDst, uint32_t blockSize); - /** +/** * @brief Compute the logical bitwise OR of two fixed-point vectors. * @param[in] pSrcA points to input vector A * @param[in] pSrcB points to input vector B * @param[out] pDst points to output vector * @param[in] blockSize number of samples in each vector */ - void arm_or_u16( - const uint16_t * pSrcA, - const uint16_t * pSrcB, - uint16_t * pDst, - uint32_t blockSize); +void arm_or_u16(const uint16_t *pSrcA, const uint16_t *pSrcB, uint16_t *pDst, uint32_t blockSize); - /** +/** * @brief Compute the logical bitwise OR of two fixed-point vectors. * @param[in] pSrcA points to input vector A * @param[in] pSrcB points to input vector B * @param[out] pDst points to output vector * @param[in] blockSize number of samples in each vector */ - void arm_or_u32( - const uint32_t * pSrcA, - const uint32_t * pSrcB, - uint32_t * pDst, - uint32_t blockSize); +void arm_or_u32(const uint32_t *pSrcA, const uint32_t *pSrcB, uint32_t *pDst, uint32_t blockSize); - /** +/** * @brief Compute the logical bitwise OR of two fixed-point vectors. * @param[in] pSrcA points to input vector A * @param[in] pSrcB points to input vector B * @param[out] pDst points to output vector * @param[in] blockSize number of samples in each vector */ - void arm_or_u8( - const uint8_t * pSrcA, - const uint8_t * pSrcB, - uint8_t * pDst, - uint32_t blockSize); +void arm_or_u8(const uint8_t *pSrcA, const uint8_t *pSrcB, uint8_t *pDst, uint32_t blockSize); - /** +/** * @brief Compute the logical bitwise NOT of a fixed-point vector. * @param[in] pSrc points to input vector * @param[out] pDst points to output vector * @param[in] blockSize number of samples in each vector */ - void arm_not_u16( - const uint16_t * pSrc, - uint16_t * pDst, - uint32_t blockSize); +void arm_not_u16(const uint16_t *pSrc, uint16_t *pDst, uint32_t blockSize); - /** +/** * @brief Compute the logical bitwise NOT of a fixed-point vector. * @param[in] pSrc points to input vector * @param[out] pDst points to output vector * @param[in] blockSize number of samples in each vector */ - void arm_not_u32( - const uint32_t * pSrc, - uint32_t * pDst, - uint32_t blockSize); +void arm_not_u32(const uint32_t *pSrc, uint32_t *pDst, uint32_t blockSize); - /** +/** * @brief Compute the logical bitwise NOT of a fixed-point vector. * @param[in] pSrc points to input vector * @param[out] pDst points to output vector * @param[in] blockSize number of samples in each vector */ - void arm_not_u8( - const uint8_t * pSrc, - uint8_t * pDst, - uint32_t blockSize); +void arm_not_u8(const uint8_t *pSrc, uint8_t *pDst, uint32_t blockSize); /** * @brief Compute the logical bitwise XOR of two fixed-point vectors. @@ -764,39 +515,27 @@ const float64_t * pSrc, * @param[out] pDst points to output vector * @param[in] blockSize number of samples in each vector */ - void arm_xor_u16( - const uint16_t * pSrcA, - const uint16_t * pSrcB, - uint16_t * pDst, - uint32_t blockSize); +void arm_xor_u16(const uint16_t *pSrcA, const uint16_t *pSrcB, uint16_t *pDst, uint32_t blockSize); - /** +/** * @brief Compute the logical bitwise XOR of two fixed-point vectors. * @param[in] pSrcA points to input vector A * @param[in] pSrcB points to input vector B * @param[out] pDst points to output vector * @param[in] blockSize number of samples in each vector */ - void arm_xor_u32( - const uint32_t * pSrcA, - const uint32_t * pSrcB, - uint32_t * pDst, - uint32_t blockSize); +void arm_xor_u32(const uint32_t *pSrcA, const uint32_t *pSrcB, uint32_t *pDst, uint32_t blockSize); - /** +/** * @brief Compute the logical bitwise XOR of two fixed-point vectors. * @param[in] pSrcA points to input vector A * @param[in] pSrcB points to input vector B * @param[out] pDst points to output vector * @param[in] blockSize number of samples in each vector */ - void arm_xor_u8( - const uint8_t * pSrcA, - const uint8_t * pSrcB, - uint8_t * pDst, - uint32_t blockSize); +void arm_xor_u8(const uint8_t *pSrcA, const uint8_t *pSrcB, uint8_t *pDst, uint32_t blockSize); - /** +/** @brief Elementwise floating-point clipping @param[in] pSrc points to input values @param[out] pDst points to output clipped values @@ -805,13 +544,10 @@ const float64_t * pSrc, @param[in] numSamples number of samples to clip */ -void arm_clip_f32(const float32_t * pSrc, - float32_t * pDst, - float32_t low, - float32_t high, - uint32_t numSamples); +void arm_clip_f32(const float32_t *pSrc, float32_t *pDst, float32_t low, float32_t high, + uint32_t numSamples); - /** +/** @brief Elementwise fixed-point clipping @param[in] pSrc points to input values @param[out] pDst points to output clipped values @@ -820,13 +556,9 @@ void arm_clip_f32(const float32_t * pSrc, @param[in] numSamples number of samples to clip */ -void arm_clip_q31(const q31_t * pSrc, - q31_t * pDst, - q31_t low, - q31_t high, - uint32_t numSamples); +void arm_clip_q31(const q31_t *pSrc, q31_t *pDst, q31_t low, q31_t high, uint32_t numSamples); - /** +/** @brief Elementwise fixed-point clipping @param[in] pSrc points to input values @param[out] pDst points to output clipped values @@ -835,13 +567,9 @@ void arm_clip_q31(const q31_t * pSrc, @param[in] numSamples number of samples to clip */ -void arm_clip_q15(const q15_t * pSrc, - q15_t * pDst, - q15_t low, - q15_t high, - uint32_t numSamples); +void arm_clip_q15(const q15_t *pSrc, q15_t *pDst, q15_t low, q15_t high, uint32_t numSamples); - /** +/** @brief Elementwise fixed-point clipping @param[in] pSrc points to input values @param[out] pDst points to output clipped values @@ -850,14 +578,9 @@ void arm_clip_q15(const q15_t * pSrc, @param[in] numSamples number of samples to clip */ -void arm_clip_q7(const q7_t * pSrc, - q7_t * pDst, - q7_t low, - q7_t high, - uint32_t numSamples); - +void arm_clip_q7(const q7_t *pSrc, q7_t *pDst, q7_t low, q7_t high, uint32_t numSamples); -#ifdef __cplusplus +#ifdef __cplusplus } #endif diff --git a/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/basic_math_functions_f16.h b/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/basic_math_functions_f16.h old mode 100755 new mode 100644 index b3d5ecdc95a..273b48d6820 --- a/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/basic_math_functions_f16.h +++ b/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/basic_math_functions_f16.h @@ -23,7 +23,6 @@ * limitations under the License. */ - #ifndef BASIC_MATH_FUNCTIONS_F16_H_ #define BASIC_MATH_FUNCTIONS_F16_H_ @@ -33,116 +32,87 @@ #include "dsp/none.h" #include "dsp/utils.h" -#ifdef __cplusplus -extern "C" -{ +#ifdef __cplusplus +extern "C" { #endif #if defined(ARM_FLOAT16_SUPPORTED) - - /** +/** * @brief Floating-point vector addition. * @param[in] pSrcA points to the first input vector * @param[in] pSrcB points to the second input vector * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in each vector */ - void arm_add_f16( - const float16_t * pSrcA, - const float16_t * pSrcB, - float16_t * pDst, - uint32_t blockSize); +void arm_add_f16(const float16_t *pSrcA, const float16_t *pSrcB, float16_t *pDst, + uint32_t blockSize); - /** +/** * @brief Floating-point vector subtraction. * @param[in] pSrcA points to the first input vector * @param[in] pSrcB points to the second input vector * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in each vector */ - void arm_sub_f16( - const float16_t * pSrcA, - const float16_t * pSrcB, - float16_t * pDst, - uint32_t blockSize); +void arm_sub_f16(const float16_t *pSrcA, const float16_t *pSrcB, float16_t *pDst, + uint32_t blockSize); - /** +/** * @brief Multiplies a floating-point vector by a scalar. * @param[in] pSrc points to the input vector * @param[in] scale scale factor to be applied * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in the vector */ - void arm_scale_f16( - const float16_t * pSrc, - float16_t scale, - float16_t * pDst, - uint32_t blockSize); +void arm_scale_f16(const float16_t *pSrc, float16_t scale, float16_t *pDst, uint32_t blockSize); - /** +/** * @brief Floating-point vector absolute value. * @param[in] pSrc points to the input buffer * @param[out] pDst points to the output buffer * @param[in] blockSize number of samples in each vector */ - void arm_abs_f16( - const float16_t * pSrc, - float16_t * pDst, - uint32_t blockSize); - +void arm_abs_f16(const float16_t *pSrc, float16_t *pDst, uint32_t blockSize); - /** +/** * @brief Adds a constant offset to a floating-point vector. * @param[in] pSrc points to the input vector * @param[in] offset is the offset to be added * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in the vector */ - void arm_offset_f16( - const float16_t * pSrc, - float16_t offset, - float16_t * pDst, - uint32_t blockSize); +void arm_offset_f16(const float16_t *pSrc, float16_t offset, float16_t *pDst, uint32_t blockSize); - /** +/** * @brief Dot product of floating-point vectors. * @param[in] pSrcA points to the first input vector * @param[in] pSrcB points to the second input vector * @param[in] blockSize number of samples in each vector * @param[out] result output result returned here */ - void arm_dot_prod_f16( - const float16_t * pSrcA, - const float16_t * pSrcB, - uint32_t blockSize, - float16_t * result); +void arm_dot_prod_f16(const float16_t *pSrcA, const float16_t *pSrcB, uint32_t blockSize, + float16_t *result); - /** +/** * @brief Floating-point vector multiplication. * @param[in] pSrcA points to the first input vector * @param[in] pSrcB points to the second input vector * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in each vector */ - void arm_mult_f16( - const float16_t * pSrcA, - const float16_t * pSrcB, - float16_t * pDst, - uint32_t blockSize); +void arm_mult_f16(const float16_t *pSrcA, const float16_t *pSrcB, float16_t *pDst, + uint32_t blockSize); - /** +/** * @brief Negates the elements of a floating-point vector. * @param[in] pSrc points to the input vector * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in the vector */ - void arm_negate_f16( - const float16_t * pSrc, - float16_t * pDst, - uint32_t blockSize); +void arm_negate_f16(const float16_t *pSrc, float16_t *pDst, uint32_t blockSize); - /** +/** @brief Elementwise floating-point clipping @param[in] pSrc points to input values @param[out] pDst points to output clipped values @@ -150,15 +120,12 @@ extern "C" @param[in] high higher bound @param[in] numSamples number of samples to clip */ -void arm_clip_f16(const float16_t * pSrc, - float16_t * pDst, - float16_t low, - float16_t high, - uint32_t numSamples); +void arm_clip_f16(const float16_t *pSrc, float16_t *pDst, float16_t low, float16_t high, + uint32_t numSamples); #endif /* defined(ARM_FLOAT16_SUPPORTED)*/ -#ifdef __cplusplus +#ifdef __cplusplus } #endif diff --git a/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/bayes_functions.h b/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/bayes_functions.h old mode 100755 new mode 100644 index 7b3e0efacbb..b916a3f16db --- a/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/bayes_functions.h +++ b/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/bayes_functions.h @@ -23,7 +23,6 @@ * limitations under the License. */ - #ifndef BAYES_FUNCTIONS_H_ #define BAYES_FUNCTIONS_H_ @@ -46,22 +45,20 @@ * DSP/Testing/PatternGeneration/Bayes.py */ -#ifdef __cplusplus -extern "C" -{ +#ifdef __cplusplus +extern "C" { #endif /** * @brief Instance structure for Naive Gaussian Bayesian estimator. */ -typedef struct -{ - uint32_t vectorDimension; /**< Dimension of vector space */ - uint32_t numberOfClasses; /**< Number of different classes */ - const float32_t *theta; /**< Mean values for the Gaussians */ - const float32_t *sigma; /**< Variances for the Gaussians */ - const float32_t *classPriors; /**< Class prior probabilities */ - float32_t epsilon; /**< Additive value to variances */ +typedef struct { + uint32_t vectorDimension; /**< Dimension of vector space */ + uint32_t numberOfClasses; /**< Number of different classes */ + const float32_t *theta; /**< Mean values for the Gaussians */ + const float32_t *sigma; /**< Variances for the Gaussians */ + const float32_t *classPriors; /**< Class prior probabilities */ + float32_t epsilon; /**< Additive value to variances */ } arm_gaussian_naive_bayes_instance_f32; /** @@ -73,13 +70,11 @@ typedef struct * @param[out] *pBufferB points to a temporary buffer of length numberOfClasses * @return The predicted class */ -uint32_t arm_gaussian_naive_bayes_predict_f32(const arm_gaussian_naive_bayes_instance_f32 *S, - const float32_t * in, - float32_t *pOutputProbabilities, - float32_t *pBufferB); +uint32_t arm_gaussian_naive_bayes_predict_f32(const arm_gaussian_naive_bayes_instance_f32 *S, + const float32_t *in, float32_t *pOutputProbabilities, + float32_t *pBufferB); - -#ifdef __cplusplus +#ifdef __cplusplus } #endif diff --git a/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/bayes_functions_f16.h b/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/bayes_functions_f16.h old mode 100755 new mode 100644 index 100162ed465..bf6fdf93424 --- a/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/bayes_functions_f16.h +++ b/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/bayes_functions_f16.h @@ -23,7 +23,6 @@ * limitations under the License. */ - #ifndef BAYES_FUNCTIONS_F16_H_ #define BAYES_FUNCTIONS_F16_H_ @@ -35,9 +34,8 @@ #include "dsp/statistics_functions_f16.h" -#ifdef __cplusplus -extern "C" -{ +#ifdef __cplusplus +extern "C" { #endif #if defined(ARM_FLOAT16_SUPPORTED) @@ -45,14 +43,13 @@ extern "C" /** * @brief Instance structure for Naive Gaussian Bayesian estimator. */ -typedef struct -{ - uint32_t vectorDimension; /**< Dimension of vector space */ - uint32_t numberOfClasses; /**< Number of different classes */ - const float16_t *theta; /**< Mean values for the Gaussians */ - const float16_t *sigma; /**< Variances for the Gaussians */ - const float16_t *classPriors; /**< Class prior probabilities */ - float16_t epsilon; /**< Additive value to variances */ +typedef struct { + uint32_t vectorDimension; /**< Dimension of vector space */ + uint32_t numberOfClasses; /**< Number of different classes */ + const float16_t *theta; /**< Mean values for the Gaussians */ + const float16_t *sigma; /**< Variances for the Gaussians */ + const float16_t *classPriors; /**< Class prior probabilities */ + float16_t epsilon; /**< Additive value to variances */ } arm_gaussian_naive_bayes_instance_f16; /** @@ -64,13 +61,12 @@ typedef struct * @param[out] *pBufferB points to a temporary buffer of length numberOfClasses * @return The predicted class */ -uint32_t arm_gaussian_naive_bayes_predict_f16(const arm_gaussian_naive_bayes_instance_f16 *S, - const float16_t * in, - float16_t *pOutputProbabilities, - float16_t *pBufferB); +uint32_t arm_gaussian_naive_bayes_predict_f16(const arm_gaussian_naive_bayes_instance_f16 *S, + const float16_t *in, float16_t *pOutputProbabilities, + float16_t *pBufferB); #endif /*defined(ARM_FLOAT16_SUPPORTED)*/ -#ifdef __cplusplus +#ifdef __cplusplus } #endif diff --git a/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/complex_math_functions.h b/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/complex_math_functions.h old mode 100755 new mode 100644 index bdbc2a4ed49..21bf9c605f9 --- a/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/complex_math_functions.h +++ b/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/complex_math_functions.h @@ -23,7 +23,6 @@ * limitations under the License. */ - #ifndef COMPLEX_MATH_FUNCTIONS_H_ #define COMPLEX_MATH_FUNCTIONS_H_ @@ -34,9 +33,8 @@ #include "dsp/utils.h" #include "dsp/fast_math_functions.h" -#ifdef __cplusplus -extern "C" -{ +#ifdef __cplusplus +extern "C" { #endif /** @@ -49,88 +47,61 @@ extern "C" * real values. */ - /** +/** * @brief Floating-point complex conjugate. * @param[in] pSrc points to the input vector * @param[out] pDst points to the output vector * @param[in] numSamples number of complex samples in each vector */ - void arm_cmplx_conj_f32( - const float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); +void arm_cmplx_conj_f32(const float32_t *pSrc, float32_t *pDst, uint32_t numSamples); - /** +/** * @brief Q31 complex conjugate. * @param[in] pSrc points to the input vector * @param[out] pDst points to the output vector * @param[in] numSamples number of complex samples in each vector */ - void arm_cmplx_conj_q31( - const q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - +void arm_cmplx_conj_q31(const q31_t *pSrc, q31_t *pDst, uint32_t numSamples); - /** +/** * @brief Q15 complex conjugate. * @param[in] pSrc points to the input vector * @param[out] pDst points to the output vector * @param[in] numSamples number of complex samples in each vector */ - void arm_cmplx_conj_q15( - const q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - +void arm_cmplx_conj_q15(const q15_t *pSrc, q15_t *pDst, uint32_t numSamples); - /** +/** * @brief Floating-point complex magnitude squared * @param[in] pSrc points to the complex input vector * @param[out] pDst points to the real output vector * @param[in] numSamples number of complex samples in the input vector */ - void arm_cmplx_mag_squared_f32( - const float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - +void arm_cmplx_mag_squared_f32(const float32_t *pSrc, float32_t *pDst, uint32_t numSamples); - /** +/** * @brief Floating-point complex magnitude squared * @param[in] pSrc points to the complex input vector * @param[out] pDst points to the real output vector * @param[in] numSamples number of complex samples in the input vector */ - void arm_cmplx_mag_squared_f64( - const float64_t * pSrc, - float64_t * pDst, - uint32_t numSamples); +void arm_cmplx_mag_squared_f64(const float64_t *pSrc, float64_t *pDst, uint32_t numSamples); - - /** +/** * @brief Q31 complex magnitude squared * @param[in] pSrc points to the complex input vector * @param[out] pDst points to the real output vector * @param[in] numSamples number of complex samples in the input vector */ - void arm_cmplx_mag_squared_q31( - const q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); +void arm_cmplx_mag_squared_q31(const q31_t *pSrc, q31_t *pDst, uint32_t numSamples); - - /** +/** * @brief Q15 complex magnitude squared * @param[in] pSrc points to the complex input vector * @param[out] pDst points to the real output vector * @param[in] numSamples number of complex samples in the input vector */ - void arm_cmplx_mag_squared_q15( - const q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - +void arm_cmplx_mag_squared_q15(const q15_t *pSrc, q15_t *pDst, uint32_t numSamples); /** * @brief Floating-point complex magnitude @@ -138,11 +109,7 @@ extern "C" * @param[out] pDst points to the real output vector * @param[in] numSamples number of complex samples in the input vector */ - void arm_cmplx_mag_f32( - const float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - +void arm_cmplx_mag_f32(const float32_t *pSrc, float32_t *pDst, uint32_t numSamples); /** * @brief Floating-point complex magnitude @@ -150,48 +117,33 @@ extern "C" * @param[out] pDst points to the real output vector * @param[in] numSamples number of complex samples in the input vector */ - void arm_cmplx_mag_f64( - const float64_t * pSrc, - float64_t * pDst, - uint32_t numSamples); - +void arm_cmplx_mag_f64(const float64_t *pSrc, float64_t *pDst, uint32_t numSamples); - /** +/** * @brief Q31 complex magnitude * @param[in] pSrc points to the complex input vector * @param[out] pDst points to the real output vector * @param[in] numSamples number of complex samples in the input vector */ - void arm_cmplx_mag_q31( - const q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - +void arm_cmplx_mag_q31(const q31_t *pSrc, q31_t *pDst, uint32_t numSamples); - /** +/** * @brief Q15 complex magnitude * @param[in] pSrc points to the complex input vector * @param[out] pDst points to the real output vector * @param[in] numSamples number of complex samples in the input vector */ - void arm_cmplx_mag_q15( - const q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); +void arm_cmplx_mag_q15(const q15_t *pSrc, q15_t *pDst, uint32_t numSamples); - /** +/** * @brief Q15 complex magnitude * @param[in] pSrc points to the complex input vector * @param[out] pDst points to the real output vector * @param[in] numSamples number of complex samples in the input vector */ - void arm_cmplx_mag_fast_q15( - const q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - +void arm_cmplx_mag_fast_q15(const q15_t *pSrc, q15_t *pDst, uint32_t numSamples); - /** +/** * @brief Q15 complex dot product * @param[in] pSrcA points to the first input vector * @param[in] pSrcB points to the second input vector @@ -199,15 +151,10 @@ extern "C" * @param[out] realResult real part of the result returned here * @param[out] imagResult imaginary part of the result returned here */ - void arm_cmplx_dot_prod_q15( - const q15_t * pSrcA, - const q15_t * pSrcB, - uint32_t numSamples, - q31_t * realResult, - q31_t * imagResult); - +void arm_cmplx_dot_prod_q15(const q15_t *pSrcA, const q15_t *pSrcB, uint32_t numSamples, + q31_t *realResult, q31_t *imagResult); - /** +/** * @brief Q31 complex dot product * @param[in] pSrcA points to the first input vector * @param[in] pSrcB points to the second input vector @@ -215,15 +162,10 @@ extern "C" * @param[out] realResult real part of the result returned here * @param[out] imagResult imaginary part of the result returned here */ - void arm_cmplx_dot_prod_q31( - const q31_t * pSrcA, - const q31_t * pSrcB, - uint32_t numSamples, - q63_t * realResult, - q63_t * imagResult); +void arm_cmplx_dot_prod_q31(const q31_t *pSrcA, const q31_t *pSrcB, uint32_t numSamples, + q63_t *realResult, q63_t *imagResult); - - /** +/** * @brief Floating-point complex dot product * @param[in] pSrcA points to the first input vector * @param[in] pSrcB points to the second input vector @@ -231,97 +173,68 @@ extern "C" * @param[out] realResult real part of the result returned here * @param[out] imagResult imaginary part of the result returned here */ - void arm_cmplx_dot_prod_f32( - const float32_t * pSrcA, - const float32_t * pSrcB, - uint32_t numSamples, - float32_t * realResult, - float32_t * imagResult); +void arm_cmplx_dot_prod_f32(const float32_t *pSrcA, const float32_t *pSrcB, uint32_t numSamples, + float32_t *realResult, float32_t *imagResult); - - /** +/** * @brief Q15 complex-by-real multiplication * @param[in] pSrcCmplx points to the complex input vector * @param[in] pSrcReal points to the real input vector * @param[out] pCmplxDst points to the complex output vector * @param[in] numSamples number of samples in each vector */ - void arm_cmplx_mult_real_q15( - const q15_t * pSrcCmplx, - const q15_t * pSrcReal, - q15_t * pCmplxDst, - uint32_t numSamples); - +void arm_cmplx_mult_real_q15(const q15_t *pSrcCmplx, const q15_t *pSrcReal, q15_t *pCmplxDst, + uint32_t numSamples); - /** +/** * @brief Q31 complex-by-real multiplication * @param[in] pSrcCmplx points to the complex input vector * @param[in] pSrcReal points to the real input vector * @param[out] pCmplxDst points to the complex output vector * @param[in] numSamples number of samples in each vector */ - void arm_cmplx_mult_real_q31( - const q31_t * pSrcCmplx, - const q31_t * pSrcReal, - q31_t * pCmplxDst, - uint32_t numSamples); - +void arm_cmplx_mult_real_q31(const q31_t *pSrcCmplx, const q31_t *pSrcReal, q31_t *pCmplxDst, + uint32_t numSamples); - /** +/** * @brief Floating-point complex-by-real multiplication * @param[in] pSrcCmplx points to the complex input vector * @param[in] pSrcReal points to the real input vector * @param[out] pCmplxDst points to the complex output vector * @param[in] numSamples number of samples in each vector */ - void arm_cmplx_mult_real_f32( - const float32_t * pSrcCmplx, - const float32_t * pSrcReal, - float32_t * pCmplxDst, - uint32_t numSamples); +void arm_cmplx_mult_real_f32(const float32_t *pSrcCmplx, const float32_t *pSrcReal, + float32_t *pCmplxDst, uint32_t numSamples); - /** +/** * @brief Q15 complex-by-complex multiplication * @param[in] pSrcA points to the first input vector * @param[in] pSrcB points to the second input vector * @param[out] pDst points to the output vector * @param[in] numSamples number of complex samples in each vector */ - void arm_cmplx_mult_cmplx_q15( - const q15_t * pSrcA, - const q15_t * pSrcB, - q15_t * pDst, - uint32_t numSamples); - +void arm_cmplx_mult_cmplx_q15(const q15_t *pSrcA, const q15_t *pSrcB, q15_t *pDst, + uint32_t numSamples); - /** +/** * @brief Q31 complex-by-complex multiplication * @param[in] pSrcA points to the first input vector * @param[in] pSrcB points to the second input vector * @param[out] pDst points to the output vector * @param[in] numSamples number of complex samples in each vector */ - void arm_cmplx_mult_cmplx_q31( - const q31_t * pSrcA, - const q31_t * pSrcB, - q31_t * pDst, - uint32_t numSamples); - +void arm_cmplx_mult_cmplx_q31(const q31_t *pSrcA, const q31_t *pSrcB, q31_t *pDst, + uint32_t numSamples); - /** +/** * @brief Floating-point complex-by-complex multiplication * @param[in] pSrcA points to the first input vector * @param[in] pSrcB points to the second input vector * @param[out] pDst points to the output vector * @param[in] numSamples number of complex samples in each vector */ - void arm_cmplx_mult_cmplx_f32( - const float32_t * pSrcA, - const float32_t * pSrcB, - float32_t * pDst, - uint32_t numSamples); - - +void arm_cmplx_mult_cmplx_f32(const float32_t *pSrcA, const float32_t *pSrcB, float32_t *pDst, + uint32_t numSamples); /** * @brief Floating-point complex-by-complex multiplication @@ -330,15 +243,10 @@ extern "C" * @param[out] pDst points to the output vector * @param[in] numSamples number of complex samples in each vector */ -void arm_cmplx_mult_cmplx_f64( -const float64_t * pSrcA, -const float64_t * pSrcB, - float64_t * pDst, - uint32_t numSamples); - - +void arm_cmplx_mult_cmplx_f64(const float64_t *pSrcA, const float64_t *pSrcB, float64_t *pDst, + uint32_t numSamples); -#ifdef __cplusplus +#ifdef __cplusplus } #endif diff --git a/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/complex_math_functions_f16.h b/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/complex_math_functions_f16.h old mode 100755 new mode 100644 index bd147325f97..d6b3f8ce4ba --- a/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/complex_math_functions_f16.h +++ b/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/complex_math_functions_f16.h @@ -23,7 +23,6 @@ * limitations under the License. */ - #ifndef COMPLEX_MATH_FUNCTIONS_F16_H_ #define COMPLEX_MATH_FUNCTIONS_F16_H_ @@ -34,47 +33,37 @@ #include "dsp/utils.h" #include "dsp/fast_math_functions_f16.h" -#ifdef __cplusplus -extern "C" -{ +#ifdef __cplusplus +extern "C" { #endif #if defined(ARM_FLOAT16_SUPPORTED) - /** +/** * @brief Floating-point complex conjugate. * @param[in] pSrc points to the input vector * @param[out] pDst points to the output vector * @param[in] numSamples number of complex samples in each vector */ - void arm_cmplx_conj_f16( - const float16_t * pSrc, - float16_t * pDst, - uint32_t numSamples); +void arm_cmplx_conj_f16(const float16_t *pSrc, float16_t *pDst, uint32_t numSamples); - /** +/** * @brief Floating-point complex magnitude squared * @param[in] pSrc points to the complex input vector * @param[out] pDst points to the real output vector * @param[in] numSamples number of complex samples in the input vector */ - void arm_cmplx_mag_squared_f16( - const float16_t * pSrc, - float16_t * pDst, - uint32_t numSamples); +void arm_cmplx_mag_squared_f16(const float16_t *pSrc, float16_t *pDst, uint32_t numSamples); - /** +/** * @brief Floating-point complex magnitude * @param[in] pSrc points to the complex input vector * @param[out] pDst points to the real output vector * @param[in] numSamples number of complex samples in the input vector */ - void arm_cmplx_mag_f16( - const float16_t * pSrc, - float16_t * pDst, - uint32_t numSamples); +void arm_cmplx_mag_f16(const float16_t *pSrc, float16_t *pDst, uint32_t numSamples); - /** +/** * @brief Floating-point complex dot product * @param[in] pSrcA points to the first input vector * @param[in] pSrcB points to the second input vector @@ -82,41 +71,31 @@ extern "C" * @param[out] realResult real part of the result returned here * @param[out] imagResult imaginary part of the result returned here */ - void arm_cmplx_dot_prod_f16( - const float16_t * pSrcA, - const float16_t * pSrcB, - uint32_t numSamples, - float16_t * realResult, - float16_t * imagResult); +void arm_cmplx_dot_prod_f16(const float16_t *pSrcA, const float16_t *pSrcB, uint32_t numSamples, + float16_t *realResult, float16_t *imagResult); - /** +/** * @brief Floating-point complex-by-real multiplication * @param[in] pSrcCmplx points to the complex input vector * @param[in] pSrcReal points to the real input vector * @param[out] pCmplxDst points to the complex output vector * @param[in] numSamples number of samples in each vector */ - void arm_cmplx_mult_real_f16( - const float16_t * pSrcCmplx, - const float16_t * pSrcReal, - float16_t * pCmplxDst, - uint32_t numSamples); +void arm_cmplx_mult_real_f16(const float16_t *pSrcCmplx, const float16_t *pSrcReal, + float16_t *pCmplxDst, uint32_t numSamples); - /** +/** * @brief Floating-point complex-by-complex multiplication * @param[in] pSrcA points to the first input vector * @param[in] pSrcB points to the second input vector * @param[out] pDst points to the output vector * @param[in] numSamples number of complex samples in each vector */ - void arm_cmplx_mult_cmplx_f16( - const float16_t * pSrcA, - const float16_t * pSrcB, - float16_t * pDst, - uint32_t numSamples); +void arm_cmplx_mult_cmplx_f16(const float16_t *pSrcA, const float16_t *pSrcB, float16_t *pDst, + uint32_t numSamples); #endif /*defined(ARM_FLOAT16_SUPPORTED)*/ -#ifdef __cplusplus +#ifdef __cplusplus } #endif diff --git a/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/controller_functions.h b/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/controller_functions.h old mode 100755 new mode 100644 index 5d5de98ea58..d0318c8d5b8 --- a/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/controller_functions.h +++ b/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/controller_functions.h @@ -23,7 +23,6 @@ * limitations under the License. */ - #ifndef CONTROLLER_FUNCTIONS_H_ #define CONTROLLER_FUNCTIONS_H_ @@ -33,25 +32,23 @@ #include "dsp/none.h" #include "dsp/utils.h" -#ifdef __cplusplus -extern "C" -{ +#ifdef __cplusplus +extern "C" { #endif - /** +/** * @brief Macros required for SINE and COSINE Controller functions */ -#define CONTROLLER_Q31_SHIFT (32 - 9) - /* 1.31(q31) Fixed value of 2/360 */ - /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ -#define INPUT_SPACING 0xB60B61 - +#define CONTROLLER_Q31_SHIFT (32 - 9) +/* 1.31(q31) Fixed value of 2/360 */ +/* -1 to +1 is divided into 360 values so total spacing is (2/360) */ +#define INPUT_SPACING 0xB60B61 + /** * @defgroup groupController Controller Functions */ - /** @ingroup groupController */ @@ -80,35 +77,27 @@ extern "C" -# Fetch the value corresponding to \c index from cosine table to \c y0 and also value from \c index+1 to \c y1. -# Cosine value is computed as *pcosVal = y0 + (fract * (y1 - y0)). */ - + /** * @brief Floating-point sin_cos function. * @param[in] theta input value in degrees * @param[out] pSinVal points to the processed sine output. * @param[out] pCosVal points to the processed cos output. */ - void arm_sin_cos_f32( - float32_t theta, - float32_t * pSinVal, - float32_t * pCosVal); - +void arm_sin_cos_f32(float32_t theta, float32_t *pSinVal, float32_t *pCosVal); - /** +/** * @brief Q31 sin_cos function. * @param[in] theta scaled input value in degrees * @param[out] pSinVal points to the processed sine output. * @param[out] pCosVal points to the processed cosine output. */ - void arm_sin_cos_q31( - q31_t theta, - q31_t * pSinVal, - q31_t * pCosVal); - +void arm_sin_cos_q31(q31_t theta, q31_t *pSinVal, q31_t *pCosVal); /** @ingroup groupController */ - + /** * @defgroup PID PID Motor Control * @@ -167,132 +156,105 @@ extern "C" * Refer to the function specific documentation below for usage guidelines. */ - - /** +/** * @ingroup PID * @brief Instance structure for the Q15 PID Control. */ - typedef struct - { - q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ -#if !defined (ARM_MATH_DSP) - q15_t A1; /**< The derived gain A1 = -Kp - 2Kd */ - q15_t A2; /**< The derived gain A1 = Kd. */ +typedef struct { + q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ +#if !defined(ARM_MATH_DSP) + q15_t A1; /**< The derived gain A1 = -Kp - 2Kd */ + q15_t A2; /**< The derived gain A1 = Kd. */ #else - q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ + q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ #endif - q15_t state[3]; /**< The state array of length 3. */ - q15_t Kp; /**< The proportional gain. */ - q15_t Ki; /**< The integral gain. */ - q15_t Kd; /**< The derivative gain. */ - } arm_pid_instance_q15; + q15_t state[3]; /**< The state array of length 3. */ + q15_t Kp; /**< The proportional gain. */ + q15_t Ki; /**< The integral gain. */ + q15_t Kd; /**< The derivative gain. */ +} arm_pid_instance_q15; - /** +/** * @ingroup PID * @brief Instance structure for the Q31 PID Control. */ - typedef struct - { - q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ - q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ - q31_t A2; /**< The derived gain, A2 = Kd . */ - q31_t state[3]; /**< The state array of length 3. */ - q31_t Kp; /**< The proportional gain. */ - q31_t Ki; /**< The integral gain. */ - q31_t Kd; /**< The derivative gain. */ - } arm_pid_instance_q31; - - /** +typedef struct { + q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + q31_t A2; /**< The derived gain, A2 = Kd . */ + q31_t state[3]; /**< The state array of length 3. */ + q31_t Kp; /**< The proportional gain. */ + q31_t Ki; /**< The integral gain. */ + q31_t Kd; /**< The derivative gain. */ +} arm_pid_instance_q31; + +/** * @ingroup PID * @brief Instance structure for the floating-point PID Control. */ - typedef struct - { - float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ - float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ - float32_t A2; /**< The derived gain, A2 = Kd . */ - float32_t state[3]; /**< The state array of length 3. */ - float32_t Kp; /**< The proportional gain. */ - float32_t Ki; /**< The integral gain. */ - float32_t Kd; /**< The derivative gain. */ - } arm_pid_instance_f32; +typedef struct { + float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + float32_t A2; /**< The derived gain, A2 = Kd . */ + float32_t state[3]; /**< The state array of length 3. */ + float32_t Kp; /**< The proportional gain. */ + float32_t Ki; /**< The integral gain. */ + float32_t Kd; /**< The derivative gain. */ +} arm_pid_instance_f32; - - - /** +/** * @brief Initialization function for the floating-point PID Control. * @param[in,out] S points to an instance of the PID structure. * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. */ - void arm_pid_init_f32( - arm_pid_instance_f32 * S, - int32_t resetStateFlag); +void arm_pid_init_f32(arm_pid_instance_f32 *S, int32_t resetStateFlag); - - /** +/** * @brief Reset function for the floating-point PID Control. * @param[in,out] S is an instance of the floating-point PID Control structure */ - void arm_pid_reset_f32( - arm_pid_instance_f32 * S); - +void arm_pid_reset_f32(arm_pid_instance_f32 *S); - /** +/** * @brief Initialization function for the Q31 PID Control. * @param[in,out] S points to an instance of the Q15 PID structure. * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. */ - void arm_pid_init_q31( - arm_pid_instance_q31 * S, - int32_t resetStateFlag); - +void arm_pid_init_q31(arm_pid_instance_q31 *S, int32_t resetStateFlag); - /** +/** * @brief Reset function for the Q31 PID Control. * @param[in,out] S points to an instance of the Q31 PID Control structure */ - void arm_pid_reset_q31( - arm_pid_instance_q31 * S); - +void arm_pid_reset_q31(arm_pid_instance_q31 *S); - /** +/** * @brief Initialization function for the Q15 PID Control. * @param[in,out] S points to an instance of the Q15 PID structure. * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. */ - void arm_pid_init_q15( - arm_pid_instance_q15 * S, - int32_t resetStateFlag); +void arm_pid_init_q15(arm_pid_instance_q15 *S, int32_t resetStateFlag); - - /** +/** * @brief Reset function for the Q15 PID Control. * @param[in,out] S points to an instance of the q15 PID Control structure */ - void arm_pid_reset_q15( - arm_pid_instance_q15 * S); - +void arm_pid_reset_q15(arm_pid_instance_q15 *S); - - - - /** +/** * @ingroup PID * @brief Process function for the floating-point PID Control. * @param[in,out] S is an instance of the floating-point PID Control structure * @param[in] in input sample to process * @return processed output sample. */ - __STATIC_FORCEINLINE float32_t arm_pid_f32( - arm_pid_instance_f32 * S, - float32_t in) - { +__STATIC_FORCEINLINE float32_t arm_pid_f32(arm_pid_instance_f32 *S, float32_t in) +{ float32_t out; /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ - out = (S->A0 * in) + - (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); + out = (S->A0 * in) + (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); /* Update state */ S->state[1] = S->state[0]; @@ -301,8 +263,7 @@ extern "C" /* return to application */ return (out); - - } +} /** @ingroup PID @@ -318,24 +279,22 @@ extern "C" In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. */ -__STATIC_FORCEINLINE q31_t arm_pid_q31( - arm_pid_instance_q31 * S, - q31_t in) - { +__STATIC_FORCEINLINE q31_t arm_pid_q31(arm_pid_instance_q31 *S, q31_t in) +{ q63_t acc; q31_t out; /* acc = A0 * x[n] */ - acc = (q63_t) S->A0 * in; + acc = (q63_t)S->A0 * in; /* acc += A1 * x[n-1] */ - acc += (q63_t) S->A1 * S->state[0]; + acc += (q63_t)S->A1 * S->state[0]; /* acc += A2 * x[n-2] */ - acc += (q63_t) S->A2 * S->state[1]; + acc += (q63_t)S->A2 * S->state[1]; /* convert output to 1.31 format to add y[n-1] */ - out = (q31_t) (acc >> 31U); + out = (q31_t)(acc >> 31U); /* out += y[n-1] */ out += S->state[2]; @@ -347,8 +306,7 @@ __STATIC_FORCEINLINE q31_t arm_pid_q31( /* return to application */ return (out); - } - +} /** @ingroup PID @@ -365,35 +323,33 @@ __STATIC_FORCEINLINE q31_t arm_pid_q31( After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. Lastly, the accumulator is saturated to yield a result in 1.15 format. */ -__STATIC_FORCEINLINE q15_t arm_pid_q15( - arm_pid_instance_q15 * S, - q15_t in) - { +__STATIC_FORCEINLINE q15_t arm_pid_q15(arm_pid_instance_q15 *S, q15_t in) +{ q63_t acc; q15_t out; -#if defined (ARM_MATH_DSP) +#if defined(ARM_MATH_DSP) /* Implementation of PID controller */ /* acc = A0 * x[n] */ - acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in); + acc = (q31_t)__SMUAD((uint32_t)S->A0, (uint32_t)in); /* acc += A1 * x[n-1] + A2 * x[n-2] */ - acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)read_q15x2 (S->state), (uint64_t)acc); + acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)read_q15x2(S->state), (uint64_t)acc); #else /* acc = A0 * x[n] */ - acc = ((q31_t) S->A0) * in; + acc = ((q31_t)S->A0) * in; /* acc += A1 * x[n-1] + A2 * x[n-2] */ - acc += (q31_t) S->A1 * S->state[0]; - acc += (q31_t) S->A2 * S->state[1]; + acc += (q31_t)S->A1 * S->state[0]; + acc += (q31_t)S->A2 * S->state[1]; #endif /* acc += y[n-1] */ - acc += (q31_t) S->state[2] << 15; + acc += (q31_t)S->state[2] << 15; /* saturate the output */ - out = (q15_t) (__SSAT((q31_t)(acc >> 15), 16)); + out = (q15_t)(__SSAT((q31_t)(acc >> 15), 16)); /* Update state */ S->state[1] = S->state[0]; @@ -402,15 +358,13 @@ __STATIC_FORCEINLINE q15_t arm_pid_q15( /* return to application */ return (out); - } - - +} - /** +/** * @ingroup groupController */ - /** +/** * @defgroup park Vector Park Transform * * Forward Park transform converts the input two-coordinate vector to flux and torque components. @@ -434,9 +388,7 @@ __STATIC_FORCEINLINE q15_t arm_pid_q15( * Refer to the function specific documentation below for usage guidelines. */ - - - /** +/** * @ingroup park * @brief Floating-point Park transform * @param[in] Ialpha input two-phase vector coordinate alpha @@ -449,21 +401,15 @@ __STATIC_FORCEINLINE q15_t arm_pid_q15( * The function implements the forward Park transform. * */ - __STATIC_FORCEINLINE void arm_park_f32( - float32_t Ialpha, - float32_t Ibeta, - float32_t * pId, - float32_t * pIq, - float32_t sinVal, - float32_t cosVal) - { +__STATIC_FORCEINLINE void arm_park_f32(float32_t Ialpha, float32_t Ibeta, float32_t *pId, + float32_t *pIq, float32_t sinVal, float32_t cosVal) +{ /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ *pId = Ialpha * cosVal + Ibeta * sinVal; /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ *pIq = -Ialpha * sinVal + Ibeta * cosVal; - } - +} /** @ingroup park @@ -480,44 +426,36 @@ __STATIC_FORCEINLINE q15_t arm_pid_q15( The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. There is saturation on the addition and subtraction, hence there is no risk of overflow. */ -__STATIC_FORCEINLINE void arm_park_q31( - q31_t Ialpha, - q31_t Ibeta, - q31_t * pId, - q31_t * pIq, - q31_t sinVal, - q31_t cosVal) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - q31_t product3, product4; /* Temporary variables used to store intermediate results */ +__STATIC_FORCEINLINE void arm_park_q31(q31_t Ialpha, q31_t Ibeta, q31_t *pId, q31_t *pIq, + q31_t sinVal, q31_t cosVal) +{ + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ /* Intermediate product is calculated by (Ialpha * cosVal) */ - product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); + product1 = (q31_t)(((q63_t)(Ialpha) * (cosVal)) >> 31); /* Intermediate product is calculated by (Ibeta * sinVal) */ - product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); - + product2 = (q31_t)(((q63_t)(Ibeta) * (sinVal)) >> 31); /* Intermediate product is calculated by (Ialpha * sinVal) */ - product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); + product3 = (q31_t)(((q63_t)(Ialpha) * (sinVal)) >> 31); /* Intermediate product is calculated by (Ibeta * cosVal) */ - product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); + product4 = (q31_t)(((q63_t)(Ibeta) * (cosVal)) >> 31); /* Calculate pId by adding the two intermediate products 1 and 2 */ *pId = __QADD(product1, product2); /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ *pIq = __QSUB(product4, product3); - } - - +} - /** +/** * @ingroup groupController */ - /** +/** * @defgroup inv_park Vector Inverse Park transform * Inverse Park transform converts the input flux and torque components to two-coordinate vector. * @@ -534,9 +472,7 @@ __STATIC_FORCEINLINE void arm_park_q31( * Refer to the function specific documentation below for usage guidelines. */ - - - /** +/** * @ingroup inv_park * @brief Floating-point Inverse Park transform * @param[in] Id input coordinate of rotor reference frame d @@ -546,21 +482,15 @@ __STATIC_FORCEINLINE void arm_park_q31( * @param[in] sinVal sine value of rotation angle theta * @param[in] cosVal cosine value of rotation angle theta */ - __STATIC_FORCEINLINE void arm_inv_park_f32( - float32_t Id, - float32_t Iq, - float32_t * pIalpha, - float32_t * pIbeta, - float32_t sinVal, - float32_t cosVal) - { +__STATIC_FORCEINLINE void arm_inv_park_f32(float32_t Id, float32_t Iq, float32_t *pIalpha, + float32_t *pIbeta, float32_t sinVal, float32_t cosVal) +{ /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ *pIalpha = Id * cosVal - Iq * sinVal; /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ *pIbeta = Id * sinVal + Iq * cosVal; - } - +} /** @ingroup inv_park @@ -577,43 +507,36 @@ __STATIC_FORCEINLINE void arm_park_q31( The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. There is saturation on the addition, hence there is no risk of overflow. */ -__STATIC_FORCEINLINE void arm_inv_park_q31( - q31_t Id, - q31_t Iq, - q31_t * pIalpha, - q31_t * pIbeta, - q31_t sinVal, - q31_t cosVal) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - q31_t product3, product4; /* Temporary variables used to store intermediate results */ +__STATIC_FORCEINLINE void arm_inv_park_q31(q31_t Id, q31_t Iq, q31_t *pIalpha, q31_t *pIbeta, + q31_t sinVal, q31_t cosVal) +{ + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ /* Intermediate product is calculated by (Id * cosVal) */ - product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); + product1 = (q31_t)(((q63_t)(Id) * (cosVal)) >> 31); /* Intermediate product is calculated by (Iq * sinVal) */ - product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); - + product2 = (q31_t)(((q63_t)(Iq) * (sinVal)) >> 31); /* Intermediate product is calculated by (Id * sinVal) */ - product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); + product3 = (q31_t)(((q63_t)(Id) * (sinVal)) >> 31); /* Intermediate product is calculated by (Iq * cosVal) */ - product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); + product4 = (q31_t)(((q63_t)(Iq) * (cosVal)) >> 31); /* Calculate pIalpha by using the two intermediate products 1 and 2 */ *pIalpha = __QSUB(product1, product2); /* Calculate pIbeta by using the two intermediate products 3 and 4 */ *pIbeta = __QADD(product4, product3); - } - +} /** * @ingroup groupController */ - /** +/** * @defgroup clarke Vector Clarke Transform * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents @@ -635,8 +558,7 @@ __STATIC_FORCEINLINE void arm_inv_park_q31( * Refer to the function specific documentation below for usage guidelines. */ - - /** +/** * * @ingroup clarke * @brief Floating-point Clarke transform @@ -645,19 +567,15 @@ __STATIC_FORCEINLINE void arm_inv_park_q31( * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha * @param[out] pIbeta points to output two-phase orthogonal vector axis beta */ - __STATIC_FORCEINLINE void arm_clarke_f32( - float32_t Ia, - float32_t Ib, - float32_t * pIalpha, - float32_t * pIbeta) - { +__STATIC_FORCEINLINE void arm_clarke_f32(float32_t Ia, float32_t Ib, float32_t *pIalpha, + float32_t *pIbeta) +{ /* Calculate pIalpha using the equation, pIalpha = Ia */ *pIalpha = Ia; /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ *pIbeta = (0.57735026919f * Ia + 1.15470053838f * Ib); - } - +} /** @ingroup clarke @@ -672,34 +590,28 @@ __STATIC_FORCEINLINE void arm_inv_park_q31( The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. There is saturation on the addition, hence there is no risk of overflow. */ -__STATIC_FORCEINLINE void arm_clarke_q31( - q31_t Ia, - q31_t Ib, - q31_t * pIalpha, - q31_t * pIbeta) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ +__STATIC_FORCEINLINE void arm_clarke_q31(q31_t Ia, q31_t Ib, q31_t *pIalpha, q31_t *pIbeta) +{ + q31_t product1, product2; /* Temporary variables used to store intermediate results */ /* Calculating pIalpha from Ia by equation pIalpha = Ia */ *pIalpha = Ia; /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ - product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); + product1 = (q31_t)(((q63_t)Ia * 0x24F34E8B) >> 30); /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ - product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); + product2 = (q31_t)(((q63_t)Ib * 0x49E69D16) >> 30); /* pIbeta is calculated by adding the intermediate products */ *pIbeta = __QADD(product1, product2); - } - - +} - /** +/** * @ingroup groupController */ - /** +/** * @defgroup inv_clarke Vector Inverse Clarke Transform * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. * @@ -715,9 +627,7 @@ __STATIC_FORCEINLINE void arm_clarke_q31( * Refer to the function specific documentation below for usage guidelines. */ - - - /** +/** * @ingroup inv_clarke * @brief Floating-point Inverse Clarke transform * @param[in] Ialpha input two-phase orthogonal vector axis alpha @@ -725,19 +635,15 @@ __STATIC_FORCEINLINE void arm_clarke_q31( * @param[out] pIa points to output three-phase coordinate a * @param[out] pIb points to output three-phase coordinate b */ - __STATIC_FORCEINLINE void arm_inv_clarke_f32( - float32_t Ialpha, - float32_t Ibeta, - float32_t * pIa, - float32_t * pIb) - { +__STATIC_FORCEINLINE void arm_inv_clarke_f32(float32_t Ialpha, float32_t Ibeta, float32_t *pIa, + float32_t *pIb) +{ /* Calculating pIa from Ialpha by equation pIa = Ialpha */ *pIa = Ialpha; /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta; - } - +} /** @ingroup inv_clarke @@ -752,33 +658,24 @@ __STATIC_FORCEINLINE void arm_clarke_q31( The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. There is saturation on the subtraction, hence there is no risk of overflow. */ -__STATIC_FORCEINLINE void arm_inv_clarke_q31( - q31_t Ialpha, - q31_t Ibeta, - q31_t * pIa, - q31_t * pIb) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ +__STATIC_FORCEINLINE void arm_inv_clarke_q31(q31_t Ialpha, q31_t Ibeta, q31_t *pIa, q31_t *pIb) +{ + q31_t product1, product2; /* Temporary variables used to store intermediate results */ /* Calculating pIa from Ialpha by equation pIa = Ialpha */ *pIa = Ialpha; /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ - product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); + product1 = (q31_t)(((q63_t)(Ialpha) * (0x40000000)) >> 31); /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ - product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); + product2 = (q31_t)(((q63_t)(Ibeta) * (0x6ED9EBA1)) >> 31); /* pIb is calculated by subtracting the products */ *pIb = __QSUB(product2, product1); - } - - - - +} - -#ifdef __cplusplus +#ifdef __cplusplus } #endif diff --git a/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/controller_functions_f16.h b/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/controller_functions_f16.h old mode 100755 new mode 100644 index a4622ec3d5d..94b6ddc1754 --- a/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/controller_functions_f16.h +++ b/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/controller_functions_f16.h @@ -23,18 +23,16 @@ * limitations under the License. */ - #ifndef CONTROLLER_FUNCTIONS_F16_H_ #define CONTROLLER_FUNCTIONS_F16_H_ -#ifdef __cplusplus -extern "C" -{ +#ifdef __cplusplus +extern "C" { #endif #if defined(ARM_FLOAT16_SUPPORTED) #endif /*defined(ARM_FLOAT16_SUPPORTED)*/ -#ifdef __cplusplus +#ifdef __cplusplus } #endif diff --git a/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/debug.h b/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/debug.h index b98e038931b..c53c6f28c1d 100644 --- a/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/debug.h +++ b/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/debug.h @@ -23,7 +23,6 @@ * limitations under the License. */ - #ifndef DEBUG_FUNCTIONS_H_ #define DEBUG_FUNCTIONS_H_ @@ -38,108 +37,98 @@ #include -#ifdef __cplusplus -extern "C" -{ +#ifdef __cplusplus +extern "C" { #endif #if defined(ARM_FLOAT16_SUPPORTED) -#define PROW_f16(S,NB) \ -{ \ - printf("{%f",(double)(S)[0]); \ - for(unsigned int i=1;i<(NB) ;i++) \ - { \ - printf(",%f",(double)(S)[i]);\ - } \ - printf("}"); \ -}; - -#define PV_f16(S,V,NB)\ -{ \ - printf("%s=",(S)); \ - PROW_f16((V),(NB)); \ - printf(";\n"); \ -}; - -#define PM_f16(S,M) \ -{ \ - printf("%s={",(S)); \ - for(unsigned int row=0;row<(M)->numRows;row++) \ - { \ - if (row != 0) \ - { \ - printf("\n,"); \ - } \ - PROW_f16((M)->pData + row * (M)->numCols, (M)->numCols);\ - } \ - printf("};\n"); \ -} - -#endif - -#define PROW_f32(S,NB) \ -{ \ - printf("{%f",(double)(S)[0]); \ - for(unsigned int i=1;i<(NB) ;i++) \ - { \ - printf(",%f",(double)(S)[i]);\ - } \ - printf("}"); \ -}; - -#define PV_f32(S,V,NB)\ -{ \ - printf("%s=",(S)); \ - PROW_f32((V),(NB)); \ - printf(";\n"); \ -}; - -#define PM_f32(S,M) \ -{ \ - printf("%s={",(S)); \ - for(unsigned int row=0;row<(M)->numRows;row++) \ - { \ - if (row != 0) \ - { \ - printf("\n,"); \ - } \ - PROW_f32((M)->pData + row * (M)->numCols, (M)->numCols);\ - } \ - printf("};\n"); \ -} +#define PROW_f16(S, NB) \ + { \ + printf("{%f", (double)(S)[0]); \ + for (unsigned int i = 1; i < (NB); i++) { \ + printf(",%f", (double)(S)[i]); \ + } \ + printf("}"); \ + }; + +#define PV_f16(S, V, NB) \ + { \ + printf("%s=", (S)); \ + PROW_f16((V), (NB)); \ + printf(";\n"); \ + }; + +#define PM_f16(S, M) \ + { \ + printf("%s={", (S)); \ + for (unsigned int row = 0; row < (M)->numRows; row++) { \ + if (row != 0) { \ + printf("\n,"); \ + } \ + PROW_f16((M)->pData + row * (M)->numCols, (M)->numCols); \ + } \ + printf("};\n"); \ + } -#define PROW_f64(S,NB) \ -{ \ - printf("{%.20g",(double)(S)[0]); \ - for(unsigned int i=1;i<(NB) ;i++) \ - { \ - printf(",%.20g",(double)(S)[i]);\ - } \ - printf("}"); \ -}; - -#define PV_f64(S,V,NB) \ -{ \ - printf("%s=",(S)); \ - PROW_f64((V),(NB));\ - printf(";\n"); \ -}; - -#define PM_f64(S,M) \ -{ \ - printf("%s={",(S)); \ - for(unsigned int row=0;row<(M)->numRows;row++) \ - { \ - if (row != 0) \ - { \ - printf("\n,"); \ - } \ - PROW_f64((M)->pData + row * (M)->numCols, (M)->numCols);\ - } \ - printf("};\n"); \ -} +#endif -#ifdef __cplusplus +#define PROW_f32(S, NB) \ + { \ + printf("{%f", (double)(S)[0]); \ + for (unsigned int i = 1; i < (NB); i++) { \ + printf(",%f", (double)(S)[i]); \ + } \ + printf("}"); \ + }; + +#define PV_f32(S, V, NB) \ + { \ + printf("%s=", (S)); \ + PROW_f32((V), (NB)); \ + printf(";\n"); \ + }; + +#define PM_f32(S, M) \ + { \ + printf("%s={", (S)); \ + for (unsigned int row = 0; row < (M)->numRows; row++) { \ + if (row != 0) { \ + printf("\n,"); \ + } \ + PROW_f32((M)->pData + row * (M)->numCols, (M)->numCols); \ + } \ + printf("};\n"); \ + } + +#define PROW_f64(S, NB) \ + { \ + printf("{%.20g", (double)(S)[0]); \ + for (unsigned int i = 1; i < (NB); i++) { \ + printf(",%.20g", (double)(S)[i]); \ + } \ + printf("}"); \ + }; + +#define PV_f64(S, V, NB) \ + { \ + printf("%s=", (S)); \ + PROW_f64((V), (NB)); \ + printf(";\n"); \ + }; + +#define PM_f64(S, M) \ + { \ + printf("%s={", (S)); \ + for (unsigned int row = 0; row < (M)->numRows; row++) { \ + if (row != 0) { \ + printf("\n,"); \ + } \ + PROW_f64((M)->pData + row * (M)->numCols, (M)->numCols); \ + } \ + printf("};\n"); \ + } + +#ifdef __cplusplus } #endif diff --git a/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/distance_functions.h b/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/distance_functions.h old mode 100755 new mode 100644 index 995efab8b63..433b0a4a63d --- a/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/distance_functions.h +++ b/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/distance_functions.h @@ -23,7 +23,6 @@ * limitations under the License. */ - #ifndef DISTANCE_FUNCTIONS_H_ #define DISTANCE_FUNCTIONS_H_ @@ -38,12 +37,10 @@ #include "dsp/fast_math_functions.h" #include "dsp/matrix_functions.h" -#ifdef __cplusplus -extern "C" -{ +#ifdef __cplusplus +extern "C" { #endif - /** * @defgroup groupDistance Distance Functions * @@ -53,11 +50,11 @@ extern "C" */ /* 6.14 bug */ -#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) && (__ARMCC_VERSION < 6150001) - +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) && (__ARMCC_VERSION < 6150001) + __attribute__((weak)) float __powisf2(float a, int b); -#endif +#endif /** * @brief Euclidean distance between two vectors @@ -68,7 +65,7 @@ __attribute__((weak)) float __powisf2(float a, int b); * */ -float32_t arm_euclidean_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize); +float32_t arm_euclidean_distance_f32(const float32_t *pA, const float32_t *pB, uint32_t blockSize); /** * @brief Euclidean distance between two vectors @@ -79,7 +76,7 @@ float32_t arm_euclidean_distance_f32(const float32_t *pA,const float32_t *pB, ui * */ -float64_t arm_euclidean_distance_f64(const float64_t *pA,const float64_t *pB, uint32_t blockSize); +float64_t arm_euclidean_distance_f64(const float64_t *pA, const float64_t *pB, uint32_t blockSize); /** * @brief Bray-Curtis distance between two vectors @@ -89,7 +86,7 @@ float64_t arm_euclidean_distance_f64(const float64_t *pA,const float64_t *pB, ui * @return distance * */ -float32_t arm_braycurtis_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize); +float32_t arm_braycurtis_distance_f32(const float32_t *pA, const float32_t *pB, uint32_t blockSize); /** * @brief Canberra distance between two vectors @@ -104,8 +101,7 @@ float32_t arm_braycurtis_distance_f32(const float32_t *pA,const float32_t *pB, u * @return distance * */ -float32_t arm_canberra_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize); - +float32_t arm_canberra_distance_f32(const float32_t *pA, const float32_t *pB, uint32_t blockSize); /** * @brief Chebyshev distance between two vectors @@ -115,8 +111,7 @@ float32_t arm_canberra_distance_f32(const float32_t *pA,const float32_t *pB, uin * @return distance * */ -float32_t arm_chebyshev_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize); - +float32_t arm_chebyshev_distance_f32(const float32_t *pA, const float32_t *pB, uint32_t blockSize); /** * @brief Chebyshev distance between two vectors @@ -126,8 +121,7 @@ float32_t arm_chebyshev_distance_f32(const float32_t *pA,const float32_t *pB, ui * @return distance * */ -float64_t arm_chebyshev_distance_f64(const float64_t *pA,const float64_t *pB, uint32_t blockSize); - +float64_t arm_chebyshev_distance_f64(const float64_t *pA, const float64_t *pB, uint32_t blockSize); /** * @brief Cityblock (Manhattan) distance between two vectors @@ -137,7 +131,7 @@ float64_t arm_chebyshev_distance_f64(const float64_t *pA,const float64_t *pB, ui * @return distance * */ -float32_t arm_cityblock_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize); +float32_t arm_cityblock_distance_f32(const float32_t *pA, const float32_t *pB, uint32_t blockSize); /** * @brief Cityblock (Manhattan) distance between two vectors @@ -147,7 +141,7 @@ float32_t arm_cityblock_distance_f32(const float32_t *pA,const float32_t *pB, ui * @return distance * */ -float64_t arm_cityblock_distance_f64(const float64_t *pA,const float64_t *pB, uint32_t blockSize); +float64_t arm_cityblock_distance_f64(const float64_t *pA, const float64_t *pB, uint32_t blockSize); /** * @brief Correlation distance between two vectors @@ -160,7 +154,7 @@ float64_t arm_cityblock_distance_f64(const float64_t *pA,const float64_t *pB, ui * @return distance * */ -float32_t arm_correlation_distance_f32(float32_t *pA,float32_t *pB, uint32_t blockSize); +float32_t arm_correlation_distance_f32(float32_t *pA, float32_t *pB, uint32_t blockSize); /** * @brief Cosine distance between two vectors @@ -172,7 +166,7 @@ float32_t arm_correlation_distance_f32(float32_t *pA,float32_t *pB, uint32_t blo * */ -float32_t arm_cosine_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize); +float32_t arm_cosine_distance_f32(const float32_t *pA, const float32_t *pB, uint32_t blockSize); /** * @brief Cosine distance between two vectors @@ -184,7 +178,7 @@ float32_t arm_cosine_distance_f32(const float32_t *pA,const float32_t *pB, uint3 * */ -float64_t arm_cosine_distance_f64(const float64_t *pA,const float64_t *pB, uint32_t blockSize); +float64_t arm_cosine_distance_f64(const float64_t *pA, const float64_t *pB, uint32_t blockSize); /** * @brief Jensen-Shannon distance between two vectors @@ -206,7 +200,8 @@ float64_t arm_cosine_distance_f64(const float64_t *pA,const float64_t *pB, uint3 * */ -float32_t arm_jensenshannon_distance_f32(const float32_t *pA,const float32_t *pB,uint32_t blockSize); +float32_t arm_jensenshannon_distance_f32(const float32_t *pA, const float32_t *pB, + uint32_t blockSize); /** * @brief Minkowski distance between two vectors @@ -219,9 +214,8 @@ float32_t arm_jensenshannon_distance_f32(const float32_t *pA,const float32_t *pB * */ - - -float32_t arm_minkowski_distance_f32(const float32_t *pA,const float32_t *pB, int32_t order, uint32_t blockSize); +float32_t arm_minkowski_distance_f32(const float32_t *pA, const float32_t *pB, int32_t order, + uint32_t blockSize); /** * @brief Dice distance between two vectors @@ -234,7 +228,6 @@ float32_t arm_minkowski_distance_f32(const float32_t *pA,const float32_t *pB, in * */ - float32_t arm_dice_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); /** @@ -283,7 +276,8 @@ float32_t arm_kulsinski_distance(const uint32_t *pA, const uint32_t *pB, uint32_ * */ -float32_t arm_rogerstanimoto_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); +float32_t arm_rogerstanimoto_distance(const uint32_t *pA, const uint32_t *pB, + uint32_t numberOfBools); /** * @brief Russell-Rao distance between two vectors @@ -307,7 +301,8 @@ float32_t arm_russellrao_distance(const uint32_t *pA, const uint32_t *pB, uint32 * */ -float32_t arm_sokalmichener_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); +float32_t arm_sokalmichener_distance(const uint32_t *pA, const uint32_t *pB, + uint32_t numberOfBools); /** * @brief Sokal-Sneath distance between two vectors @@ -333,12 +328,11 @@ float32_t arm_sokalsneath_distance(const uint32_t *pA, const uint32_t *pB, uint3 float32_t arm_yule_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); -typedef enum - { +typedef enum { ARM_DTW_SAKOE_CHIBA_WINDOW = 1, /*ARM_DTW_ITAKURA_WINDOW = 2,*/ ARM_DTW_SLANTED_BAND_WINDOW = 3 - } arm_dtw_window; +} arm_dtw_window; /** * @brief Window for dynamic time warping computation @@ -348,8 +342,7 @@ typedef enum * @return Error if window type not recognized * */ -arm_status arm_dtw_init_window_q7(const arm_dtw_window windowType, - const int32_t windowSize, +arm_status arm_dtw_init_window_q7(const arm_dtw_window windowType, const int32_t windowSize, arm_matrix_instance_q7 *pWindow); /** @@ -363,10 +356,8 @@ arm_status arm_dtw_init_window_q7(const arm_dtw_window windowType, */ arm_status arm_dtw_distance_f32(const arm_matrix_instance_f32 *pDistance, - const arm_matrix_instance_q7 *pWindow, - arm_matrix_instance_f32 *pDTW, - float32_t *distance); - + const arm_matrix_instance_q7 *pWindow, + arm_matrix_instance_f32 *pDTW, float32_t *distance); /** * @brief Mapping between query and template @@ -376,10 +367,8 @@ arm_status arm_dtw_distance_f32(const arm_matrix_instance_f32 *pDistance, * */ -void arm_dtw_path_f32(const arm_matrix_instance_f32 *pDTW, - int16_t *pPath, - uint32_t *pathLength); -#ifdef __cplusplus +void arm_dtw_path_f32(const arm_matrix_instance_f32 *pDTW, int16_t *pPath, uint32_t *pathLength); +#ifdef __cplusplus } #endif diff --git a/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/distance_functions_f16.h b/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/distance_functions_f16.h old mode 100755 new mode 100644 index 224d8149974..3a1933bffe5 --- a/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/distance_functions_f16.h +++ b/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/distance_functions_f16.h @@ -23,7 +23,6 @@ * limitations under the License. */ - #ifndef DISTANCE_FUNCTIONS_F16_H_ #define DISTANCE_FUNCTIONS_F16_H_ @@ -34,19 +33,18 @@ #include "dsp/utils.h" /* 6.14 bug */ -#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) && (__ARMCC_VERSION < 6150001) +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) && (__ARMCC_VERSION < 6150001) /* Defined in minkowski_f32 */ __attribute__((weak)) float __powisf2(float a, int b); -#endif +#endif #include "dsp/statistics_functions_f16.h" #include "dsp/basic_math_functions_f16.h" #include "dsp/fast_math_functions_f16.h" -#ifdef __cplusplus -extern "C" -{ +#ifdef __cplusplus +extern "C" { #endif #if defined(ARM_FLOAT16_SUPPORTED) @@ -58,8 +56,7 @@ extern "C" * @param[in] blockSize vector length * @return distance */ -float16_t arm_euclidean_distance_f16(const float16_t *pA,const float16_t *pB, uint32_t blockSize); - +float16_t arm_euclidean_distance_f16(const float16_t *pA, const float16_t *pB, uint32_t blockSize); /** * @brief Bray-Curtis distance between two vectors @@ -68,7 +65,7 @@ float16_t arm_euclidean_distance_f16(const float16_t *pA,const float16_t *pB, ui * @param[in] blockSize vector length * @return distance */ -float16_t arm_braycurtis_distance_f16(const float16_t *pA,const float16_t *pB, uint32_t blockSize); +float16_t arm_braycurtis_distance_f16(const float16_t *pA, const float16_t *pB, uint32_t blockSize); /** * @brief Canberra distance between two vectors @@ -82,8 +79,7 @@ float16_t arm_braycurtis_distance_f16(const float16_t *pA,const float16_t *pB, u * @param[in] blockSize vector length * @return distance */ -float16_t arm_canberra_distance_f16(const float16_t *pA,const float16_t *pB, uint32_t blockSize); - +float16_t arm_canberra_distance_f16(const float16_t *pA, const float16_t *pB, uint32_t blockSize); /** * @brief Chebyshev distance between two vectors @@ -92,8 +88,7 @@ float16_t arm_canberra_distance_f16(const float16_t *pA,const float16_t *pB, uin * @param[in] blockSize vector length * @return distance */ -float16_t arm_chebyshev_distance_f16(const float16_t *pA,const float16_t *pB, uint32_t blockSize); - +float16_t arm_chebyshev_distance_f16(const float16_t *pA, const float16_t *pB, uint32_t blockSize); /** * @brief Cityblock (Manhattan) distance between two vectors @@ -102,8 +97,7 @@ float16_t arm_chebyshev_distance_f16(const float16_t *pA,const float16_t *pB, ui * @param[in] blockSize vector length * @return distance */ -float16_t arm_cityblock_distance_f16(const float16_t *pA,const float16_t *pB, uint32_t blockSize); - +float16_t arm_cityblock_distance_f16(const float16_t *pA, const float16_t *pB, uint32_t blockSize); /** * @brief Correlation distance between two vectors @@ -115,8 +109,7 @@ float16_t arm_cityblock_distance_f16(const float16_t *pA,const float16_t *pB, ui * @param[in] blockSize vector length * @return distance */ -float16_t arm_correlation_distance_f16(float16_t *pA,float16_t *pB, uint32_t blockSize); - +float16_t arm_correlation_distance_f16(float16_t *pA, float16_t *pB, uint32_t blockSize); /** * @brief Cosine distance between two vectors @@ -126,8 +119,7 @@ float16_t arm_correlation_distance_f16(float16_t *pA,float16_t *pB, uint32_t blo * @param[in] blockSize vector length * @return distance */ -float16_t arm_cosine_distance_f16(const float16_t *pA,const float16_t *pB, uint32_t blockSize); - +float16_t arm_cosine_distance_f16(const float16_t *pA, const float16_t *pB, uint32_t blockSize); /** * @brief Jensen-Shannon distance between two vectors @@ -147,8 +139,8 @@ float16_t arm_cosine_distance_f16(const float16_t *pA,const float16_t *pB, uint3 * @param[in] blockSize vector length * @return distance */ -float16_t arm_jensenshannon_distance_f16(const float16_t *pA,const float16_t *pB,uint32_t blockSize); - +float16_t arm_jensenshannon_distance_f16(const float16_t *pA, const float16_t *pB, + uint32_t blockSize); /** * @brief Minkowski distance between two vectors @@ -159,11 +151,11 @@ float16_t arm_jensenshannon_distance_f16(const float16_t *pA,const float16_t *pB * @param[in] blockSize vector length * @return distance */ -float16_t arm_minkowski_distance_f16(const float16_t *pA,const float16_t *pB, int32_t order, uint32_t blockSize); - +float16_t arm_minkowski_distance_f16(const float16_t *pA, const float16_t *pB, int32_t order, + uint32_t blockSize); #endif /*defined(ARM_FLOAT16_SUPPORTED)*/ -#ifdef __cplusplus +#ifdef __cplusplus } #endif diff --git a/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/fast_math_functions.h b/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/fast_math_functions.h old mode 100755 new mode 100644 index 8e600ccff30..a4f348f9ab8 --- a/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/fast_math_functions.h +++ b/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/fast_math_functions.h @@ -23,7 +23,6 @@ * limitations under the License. */ - #ifndef FAST_MATH_FUNCTIONS_H_ #define FAST_MATH_FUNCTIONS_H_ @@ -37,29 +36,26 @@ #include -#ifdef __cplusplus -extern "C" -{ +#ifdef __cplusplus +extern "C" { #endif - /** +/** * @brief Macros required for SINE and COSINE Fast math approximations */ -#define FAST_MATH_TABLE_SIZE 512 -#define FAST_MATH_Q31_SHIFT (32 - 10) -#define FAST_MATH_Q15_SHIFT (16 - 10) - +#define FAST_MATH_TABLE_SIZE 512 +#define FAST_MATH_Q31_SHIFT (32 - 10) +#define FAST_MATH_Q15_SHIFT (16 - 10) + #ifndef PI - #define PI 3.14159265358979f +#define PI 3.14159265358979f #endif -#ifndef PI_F64 - #define PI_F64 3.14159265358979323846 +#ifndef PI_F64 +#define PI_F64 3.14159265358979323846 #endif - - /** * @defgroup groupFastMath Fast Math Functions * This set of functions provides a fast approximation to sine, cosine, and square root. @@ -69,59 +65,47 @@ extern "C" * */ - - /** +/** * @brief Fast approximation to the trigonometric sine function for floating-point data. * @param[in] x input value in radians. * @return sin(x). */ - float32_t arm_sin_f32( - float32_t x); +float32_t arm_sin_f32(float32_t x); - - /** +/** * @brief Fast approximation to the trigonometric sine function for Q31 data. * @param[in] x Scaled input value in radians. * @return sin(x). */ - q31_t arm_sin_q31( - q31_t x); +q31_t arm_sin_q31(q31_t x); - /** +/** * @brief Fast approximation to the trigonometric sine function for Q15 data. * @param[in] x Scaled input value in radians. * @return sin(x). */ - q15_t arm_sin_q15( - q15_t x); - +q15_t arm_sin_q15(q15_t x); - /** +/** * @brief Fast approximation to the trigonometric cosine function for floating-point data. * @param[in] x input value in radians. * @return cos(x). */ - float32_t arm_cos_f32( - float32_t x); - +float32_t arm_cos_f32(float32_t x); - /** +/** * @brief Fast approximation to the trigonometric cosine function for Q31 data. * @param[in] x Scaled input value in radians. * @return cos(x). */ - q31_t arm_cos_q31( - q31_t x); +q31_t arm_cos_q31(q31_t x); - - /** +/** * @brief Fast approximation to the trigonometric cosine function for Q15 data. * @param[in] x Scaled input value in radians. * @return cos(x). */ - q15_t arm_cos_q15( - q15_t x); - +q15_t arm_cos_q15(q15_t x); /** @brief Floating-point vector of log values. @@ -129,12 +113,7 @@ extern "C" @param[out] pDst points to the output vector @param[in] blockSize number of samples in each vector */ - void arm_vlog_f32( - const float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - +void arm_vlog_f32(const float32_t *pSrc, float32_t *pDst, uint32_t blockSize); /** @brief Floating-point vector of log values. @@ -142,34 +121,23 @@ extern "C" @param[out] pDst points to the output vector @param[in] blockSize number of samples in each vector */ - void arm_vlog_f64( - const float64_t * pSrc, - float64_t * pDst, - uint32_t blockSize); - - +void arm_vlog_f64(const float64_t *pSrc, float64_t *pDst, uint32_t blockSize); - /** +/** * @brief q31 vector of log values. * @param[in] pSrc points to the input vector in q31 * @param[out] pDst points to the output vector in q5.26 * @param[in] blockSize number of samples in each vector */ - void arm_vlog_q31(const q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); +void arm_vlog_q31(const q31_t *pSrc, q31_t *pDst, uint32_t blockSize); - /** +/** * @brief q15 vector of log values. * @param[in] pSrc points to the input vector in q15 * @param[out] pDst points to the output vector in q4.11 * @param[in] blockSize number of samples in each vector */ - void arm_vlog_q15(const q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - +void arm_vlog_q15(const q15_t *pSrc, q15_t *pDst, uint32_t blockSize); /** @brief Floating-point vector of exp values. @@ -177,12 +145,7 @@ extern "C" @param[out] pDst points to the output vector @param[in] blockSize number of samples in each vector */ - void arm_vexp_f32( - const float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - +void arm_vexp_f32(const float32_t *pSrc, float32_t *pDst, uint32_t blockSize); /** @brief Floating-point vector of exp values. @@ -190,14 +153,9 @@ extern "C" @param[out] pDst points to the output vector @param[in] blockSize number of samples in each vector */ - void arm_vexp_f64( - const float64_t * pSrc, - float64_t * pDst, - uint32_t blockSize); - +void arm_vexp_f64(const float64_t *pSrc, float64_t *pDst, uint32_t blockSize); - - /** +/** * @defgroup SQRT Square Root * * Computes the square root of a number. @@ -217,8 +175,7 @@ extern "C" * */ - - /** +/** * @addtogroup SQRT * @{ */ @@ -231,49 +188,43 @@ extern "C" - \ref ARM_MATH_SUCCESS : input value is positive - \ref ARM_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0 */ -__STATIC_FORCEINLINE arm_status arm_sqrt_f32( - const float32_t in, - float32_t * pOut) - { - if (in >= 0.0f) - { -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - *pOut = __sqrtf(in); - #else - *pOut = sqrtf(in); - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in)); - #else - *pOut = sqrtf(in); - #endif - -#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) - *pOut = _sqrtf(in); +__STATIC_FORCEINLINE arm_status arm_sqrt_f32(const float32_t in, float32_t *pOut) +{ + if (in >= 0.0f) { +#if defined(__CC_ARM) +#if defined __TARGET_FPU_VFP + *pOut = __sqrtf(in); +#else + *pOut = sqrtf(in); +#endif + +#elif defined(__ICCARM__) +#if defined __ARMVFP__ + __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in)); +#else + *pOut = sqrtf(in); +#endif + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + *pOut = _sqrtf(in); #elif defined(__GNUC_PYTHON__) - *pOut = sqrtf(in); -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in)); - #else - *pOut = sqrtf(in); - #endif + *pOut = sqrtf(in); +#elif defined(__GNUC__) +#if defined(__VFP_FP__) && !defined(__SOFTFP__) + __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in)); #else - *pOut = sqrtf(in); + *pOut = sqrtf(in); +#endif +#else + *pOut = sqrtf(in); #endif - return (ARM_MATH_SUCCESS); - } - else - { - *pOut = 0.0f; - return (ARM_MATH_ARGUMENT_ERROR); + return (ARM_MATH_SUCCESS); + } else { + *pOut = 0.0f; + return (ARM_MATH_ARGUMENT_ERROR); } - } - +} /** @brief Q31 square root function. @@ -283,10 +234,7 @@ __STATIC_FORCEINLINE arm_status arm_sqrt_f32( - \ref ARM_MATH_SUCCESS : input value is positive - \ref ARM_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0 */ -arm_status arm_sqrt_q31( - q31_t in, - q31_t * pOut); - +arm_status arm_sqrt_q31(q31_t in, q31_t *pOut); /** @brief Q15 square root function. @@ -296,17 +244,13 @@ arm_status arm_sqrt_q31( - \ref ARM_MATH_SUCCESS : input value is positive - \ref ARM_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0 */ -arm_status arm_sqrt_q15( - q15_t in, - q15_t * pOut); - +arm_status arm_sqrt_q15(q15_t in, q15_t *pOut); - - /** +/** * @} end of SQRT group */ - /** +/** @brief Fixed point division @param[in] numerator Numerator @param[in] denominator Denominator @@ -318,12 +262,9 @@ arm_status arm_sqrt_q15( to the saturated negative or positive value. */ -arm_status arm_divide_q15(q15_t numerator, - q15_t denominator, - q15_t *quotient, - int16_t *shift); +arm_status arm_divide_q15(q15_t numerator, q15_t denominator, q15_t *quotient, int16_t *shift); - /** +/** @brief Fixed point division @param[in] numerator Numerator @param[in] denominator Denominator @@ -335,42 +276,36 @@ arm_status arm_divide_q15(q15_t numerator, to the saturated negative or positive value. */ -arm_status arm_divide_q31(q31_t numerator, - q31_t denominator, - q31_t *quotient, - int16_t *shift); - +arm_status arm_divide_q31(q31_t numerator, q31_t denominator, q31_t *quotient, int16_t *shift); - - /** +/** @brief Arc tangent in radian of y/x using sign of x and y to determine right quadrant. @param[in] y y coordinate @param[in] x x coordinate @param[out] result Result @return error status. */ - arm_status arm_atan2_f32(float32_t y,float32_t x,float32_t *result); +arm_status arm_atan2_f32(float32_t y, float32_t x, float32_t *result); - - /** +/** @brief Arc tangent in radian of y/x using sign of x and y to determine right quadrant. @param[in] y y coordinate @param[in] x x coordinate @param[out] result Result in Q2.29 @return error status. */ - arm_status arm_atan2_q31(q31_t y,q31_t x,q31_t *result); +arm_status arm_atan2_q31(q31_t y, q31_t x, q31_t *result); - /** +/** @brief Arc tangent in radian of y/x using sign of x and y to determine right quadrant. @param[in] y y coordinate @param[in] x x coordinate @param[out] result Result in Q2.13 @return error status. */ - arm_status arm_atan2_q15(q15_t y,q15_t x,q15_t *result); +arm_status arm_atan2_q15(q15_t y, q15_t x, q15_t *result); -#ifdef __cplusplus +#ifdef __cplusplus } #endif diff --git a/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/fast_math_functions_f16.h b/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/fast_math_functions_f16.h old mode 100755 new mode 100644 index 1fa45a86e1b..731ab2a8533 --- a/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/fast_math_functions_f16.h +++ b/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/fast_math_functions_f16.h @@ -23,7 +23,6 @@ * limitations under the License. */ - #ifndef FAST_MATH_FUNCTIONS_F16_H_ #define FAST_MATH_FUNCTIONS_F16_H_ @@ -36,14 +35,13 @@ /* For sqrt_f32 */ #include "dsp/fast_math_functions.h" -#ifdef __cplusplus -extern "C" -{ +#ifdef __cplusplus +extern "C" { #endif #if defined(ARM_FLOAT16_SUPPORTED) - /** +/** * @addtogroup SQRT * @{ */ @@ -56,32 +54,26 @@ extern "C" - \ref ARM_MATH_SUCCESS : input value is positive - \ref ARM_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0 */ -__STATIC_FORCEINLINE arm_status arm_sqrt_f16( - float16_t in, - float16_t * pOut) - { +__STATIC_FORCEINLINE arm_status arm_sqrt_f16(float16_t in, float16_t *pOut) +{ float32_t r; arm_status status; - status=arm_sqrt_f32((float32_t)in,&r); - *pOut=(float16_t)r; - return(status); - } - + status = arm_sqrt_f32((float32_t)in, &r); + *pOut = (float16_t)r; + return (status); +} /** @} end of SQRT group */ - + /** @brief Floating-point vector of log values. @param[in] pSrc points to the input vector @param[out] pDst points to the output vector @param[in] blockSize number of samples in each vector */ - void arm_vlog_f16( - const float16_t * pSrc, - float16_t * pDst, - uint32_t blockSize); +void arm_vlog_f16(const float16_t *pSrc, float16_t *pDst, uint32_t blockSize); /** @brief Floating-point vector of exp values. @@ -89,33 +81,27 @@ __STATIC_FORCEINLINE arm_status arm_sqrt_f16( @param[out] pDst points to the output vector @param[in] blockSize number of samples in each vector */ - void arm_vexp_f16( - const float16_t * pSrc, - float16_t * pDst, - uint32_t blockSize); +void arm_vexp_f16(const float16_t *pSrc, float16_t *pDst, uint32_t blockSize); - /** +/** @brief Floating-point vector of inverse values. @param[in] pSrc points to the input vector @param[out] pDst points to the output vector @param[in] blockSize number of samples in each vector */ - void arm_vinverse_f16( - const float16_t * pSrc, - float16_t * pDst, - uint32_t blockSize); +void arm_vinverse_f16(const float16_t *pSrc, float16_t *pDst, uint32_t blockSize); - /** +/** @brief Arc tangent in radian of y/x using sign of x and y to determine right quadrant. @param[in] y y coordinate @param[in] x x coordinate @param[out] result Result @return error status. */ - arm_status arm_atan2_f16(float16_t y,float16_t x,float16_t *result); +arm_status arm_atan2_f16(float16_t y, float16_t x, float16_t *result); #endif /*defined(ARM_FLOAT16_SUPPORTED)*/ -#ifdef __cplusplus +#ifdef __cplusplus } #endif diff --git a/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/filtering_functions.h b/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/filtering_functions.h old mode 100755 new mode 100644 index fa149595bbe..71ba95a5828 --- a/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/filtering_functions.h +++ b/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/filtering_functions.h @@ -23,7 +23,6 @@ * limitations under the License. */ - #ifndef FILTERING_FUNCTIONS_H_ #define FILTERING_FUNCTIONS_H_ @@ -36,84 +35,76 @@ #include "dsp/support_functions.h" #include "dsp/fast_math_functions.h" -#ifdef __cplusplus -extern "C" -{ +#ifdef __cplusplus +extern "C" { #endif - - -#define DELTA_Q31 ((q31_t)(0x100)) -#define DELTA_Q15 ((q15_t)0x5) +#define DELTA_Q31 ((q31_t)(0x100)) +#define DELTA_Q15 ((q15_t)0x5) /** * @defgroup groupFilters Filtering Functions */ - - /** + +/** * @brief Instance structure for the Q7 FIR filter. */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - const q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - } arm_fir_instance_q7; +typedef struct { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + const q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ +} arm_fir_instance_q7; - /** +/** * @brief Instance structure for the Q15 FIR filter. */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - } arm_fir_instance_q15; +typedef struct { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q15_t * + pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ +} arm_fir_instance_q15; - /** +/** * @brief Instance structure for the Q31 FIR filter. */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - } arm_fir_instance_q31; +typedef struct { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q31_t * + pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ +} arm_fir_instance_q31; - /** +/** * @brief Instance structure for the floating-point FIR filter. */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - } arm_fir_instance_f32; +typedef struct { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + float32_t * + pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ +} arm_fir_instance_f32; - /** +/** * @brief Instance structure for the floating-point FIR filter. */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - float64_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - const float64_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - } arm_fir_instance_f64; +typedef struct { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + float64_t * + pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + const float64_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ +} arm_fir_instance_f64; - /** +/** * @brief Processing function for the Q7 FIR filter. * @param[in] S points to an instance of the Q7 FIR filter structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data. * @param[in] blockSize number of samples to process. */ - void arm_fir_q7( - const arm_fir_instance_q7 * S, - const q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); +void arm_fir_q7(const arm_fir_instance_q7 *S, const q7_t *pSrc, q7_t *pDst, uint32_t blockSize); - /** +/** * @brief Initialization function for the Q7 FIR filter. * @param[in,out] S points to an instance of the Q7 FIR structure. * @param[in] numTaps Number of filter coefficients in the filter. @@ -124,40 +115,29 @@ extern "C" * For the MVE version, the coefficient length must be a multiple of 16. * You can pad with zeros if you have less coefficients. */ - void arm_fir_init_q7( - arm_fir_instance_q7 * S, - uint16_t numTaps, - const q7_t * pCoeffs, - q7_t * pState, - uint32_t blockSize); +void arm_fir_init_q7(arm_fir_instance_q7 *S, uint16_t numTaps, const q7_t *pCoeffs, q7_t *pState, + uint32_t blockSize); - /** +/** * @brief Processing function for the Q15 FIR filter. * @param[in] S points to an instance of the Q15 FIR structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data. * @param[in] blockSize number of samples to process. */ - void arm_fir_q15( - const arm_fir_instance_q15 * S, - const q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); +void arm_fir_q15(const arm_fir_instance_q15 *S, const q15_t *pSrc, q15_t *pDst, uint32_t blockSize); - /** +/** * @brief Processing function for the fast Q15 FIR filter (fast version). * @param[in] S points to an instance of the Q15 FIR filter structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data. * @param[in] blockSize number of samples to process. */ - void arm_fir_fast_q15( - const arm_fir_instance_q15 * S, - const q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); +void arm_fir_fast_q15(const arm_fir_instance_q15 *S, const q15_t *pSrc, q15_t *pDst, + uint32_t blockSize); - /** +/** * @brief Initialization function for the Q15 FIR filter. * @param[in,out] S points to an instance of the Q15 FIR filter structure. * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. @@ -172,40 +152,29 @@ extern "C" * You can pad with zeros if you have less coefficients. * */ - arm_status arm_fir_init_q15( - arm_fir_instance_q15 * S, - uint16_t numTaps, - const q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); +arm_status arm_fir_init_q15(arm_fir_instance_q15 *S, uint16_t numTaps, const q15_t *pCoeffs, + q15_t *pState, uint32_t blockSize); - /** +/** * @brief Processing function for the Q31 FIR filter. * @param[in] S points to an instance of the Q31 FIR filter structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data. * @param[in] blockSize number of samples to process. */ - void arm_fir_q31( - const arm_fir_instance_q31 * S, - const q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); +void arm_fir_q31(const arm_fir_instance_q31 *S, const q31_t *pSrc, q31_t *pDst, uint32_t blockSize); - /** +/** * @brief Processing function for the fast Q31 FIR filter (fast version). * @param[in] S points to an instance of the Q31 FIR filter structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data. * @param[in] blockSize number of samples to process. */ - void arm_fir_fast_q31( - const arm_fir_instance_q31 * S, - const q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); +void arm_fir_fast_q31(const arm_fir_instance_q31 *S, const q31_t *pSrc, q31_t *pDst, + uint32_t blockSize); - /** +/** * @brief Initialization function for the Q31 FIR filter. * @param[in,out] S points to an instance of the Q31 FIR structure. * @param[in] numTaps Number of filter coefficients in the filter. @@ -216,40 +185,30 @@ extern "C" * For the MVE version, the coefficient length must be a multiple of 4. * You can pad with zeros if you have less coefficients. */ - void arm_fir_init_q31( - arm_fir_instance_q31 * S, - uint16_t numTaps, - const q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); +void arm_fir_init_q31(arm_fir_instance_q31 *S, uint16_t numTaps, const q31_t *pCoeffs, + q31_t *pState, uint32_t blockSize); - /** +/** * @brief Processing function for the floating-point FIR filter. * @param[in] S points to an instance of the floating-point FIR structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data. * @param[in] blockSize number of samples to process. */ - void arm_fir_f32( - const arm_fir_instance_f32 * S, - const float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); +void arm_fir_f32(const arm_fir_instance_f32 *S, const float32_t *pSrc, float32_t *pDst, + uint32_t blockSize); - /** +/** * @brief Processing function for the floating-point FIR filter. * @param[in] S points to an instance of the floating-point FIR structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data. * @param[in] blockSize number of samples to process. */ - void arm_fir_f64( - const arm_fir_instance_f64 * S, - const float64_t * pSrc, - float64_t * pDst, - uint32_t blockSize); +void arm_fir_f64(const arm_fir_instance_f64 *S, const float64_t *pSrc, float64_t *pDst, + uint32_t blockSize); - /** +/** * @brief Initialization function for the floating-point FIR filter. * @param[in,out] S points to an instance of the floating-point FIR filter structure. * @param[in] numTaps Number of filter coefficients in the filter. @@ -257,14 +216,10 @@ extern "C" * @param[in] pState points to the state buffer. * @param[in] blockSize number of samples that are processed at a time. */ - void arm_fir_init_f32( - arm_fir_instance_f32 * S, - uint16_t numTaps, - const float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); +void arm_fir_init_f32(arm_fir_instance_f32 *S, uint16_t numTaps, const float32_t *pCoeffs, + float32_t *pState, uint32_t blockSize); - /** +/** * @brief Initialization function for the floating-point FIR filter. * @param[in,out] S points to an instance of the floating-point FIR filter structure. * @param[in] numTaps Number of filter coefficients in the filter. @@ -272,69 +227,68 @@ extern "C" * @param[in] pState points to the state buffer. * @param[in] blockSize number of samples that are processed at a time. */ - void arm_fir_init_f64( - arm_fir_instance_f64 * S, - uint16_t numTaps, - const float64_t * pCoeffs, - float64_t * pState, - uint32_t blockSize); +void arm_fir_init_f64(arm_fir_instance_f64 *S, uint16_t numTaps, const float64_t *pCoeffs, + float64_t *pState, uint32_t blockSize); - /** +/** * @brief Instance structure for the Q15 Biquad cascade filter. */ - typedef struct - { - int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - const q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ - } arm_biquad_casd_df1_inst_q15; +typedef struct { + int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q15_t * + pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + const q15_t + *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ +} arm_biquad_casd_df1_inst_q15; - /** +/** * @brief Instance structure for the Q31 Biquad cascade filter. */ - typedef struct - { - uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - const q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ - } arm_biquad_casd_df1_inst_q31; +typedef struct { + uint32_t + numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q31_t * + pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + const q31_t + *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ +} arm_biquad_casd_df1_inst_q31; - /** +/** * @brief Instance structure for the floating-point Biquad cascade filter. */ - typedef struct - { - uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - const float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - } arm_biquad_casd_df1_inst_f32; +typedef struct { + uint32_t + numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t * + pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + const float32_t + *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ +} arm_biquad_casd_df1_inst_f32; #if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) - /** +/** * @brief Instance structure for the modified Biquad coefs required by vectorized code. */ - typedef struct - { - float32_t coeffs[8][4]; /**< Points to the array of modified coefficients. The array is of length 32. There is one per stage */ - } arm_biquad_mod_coef_f32; -#endif +typedef struct { + float32_t coeffs + [8] + [4]; /**< Points to the array of modified coefficients. The array is of length 32. There is one per stage */ +} arm_biquad_mod_coef_f32; +#endif - /** +/** * @brief Processing function for the Q15 Biquad cascade filter. * @param[in] S points to an instance of the Q15 Biquad cascade structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data. * @param[in] blockSize number of samples to process. */ - void arm_biquad_cascade_df1_q15( - const arm_biquad_casd_df1_inst_q15 * S, - const q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); +void arm_biquad_cascade_df1_q15(const arm_biquad_casd_df1_inst_q15 *S, const q15_t *pSrc, + q15_t *pDst, uint32_t blockSize); - /** +/** * @brief Initialization function for the Q15 Biquad cascade filter. * @param[in,out] S points to an instance of the Q15 Biquad cascade structure. * @param[in] numStages number of 2nd order stages in the filter. @@ -342,53 +296,40 @@ extern "C" * @param[in] pState points to the state buffer. * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format */ - void arm_biquad_cascade_df1_init_q15( - arm_biquad_casd_df1_inst_q15 * S, - uint8_t numStages, - const q15_t * pCoeffs, - q15_t * pState, - int8_t postShift); +void arm_biquad_cascade_df1_init_q15(arm_biquad_casd_df1_inst_q15 *S, uint8_t numStages, + const q15_t *pCoeffs, q15_t *pState, int8_t postShift); - /** +/** * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. * @param[in] S points to an instance of the Q15 Biquad cascade structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data. * @param[in] blockSize number of samples to process. */ - void arm_biquad_cascade_df1_fast_q15( - const arm_biquad_casd_df1_inst_q15 * S, - const q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); +void arm_biquad_cascade_df1_fast_q15(const arm_biquad_casd_df1_inst_q15 *S, const q15_t *pSrc, + q15_t *pDst, uint32_t blockSize); - /** +/** * @brief Processing function for the Q31 Biquad cascade filter * @param[in] S points to an instance of the Q31 Biquad cascade structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data. * @param[in] blockSize number of samples to process. */ - void arm_biquad_cascade_df1_q31( - const arm_biquad_casd_df1_inst_q31 * S, - const q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); +void arm_biquad_cascade_df1_q31(const arm_biquad_casd_df1_inst_q31 *S, const q31_t *pSrc, + q31_t *pDst, uint32_t blockSize); - /** +/** * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. * @param[in] S points to an instance of the Q31 Biquad cascade structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data. * @param[in] blockSize number of samples to process. */ - void arm_biquad_cascade_df1_fast_q31( - const arm_biquad_casd_df1_inst_q31 * S, - const q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); +void arm_biquad_cascade_df1_fast_q31(const arm_biquad_casd_df1_inst_q31 *S, const q31_t *pSrc, + q31_t *pDst, uint32_t blockSize); - /** +/** * @brief Initialization function for the Q31 Biquad cascade filter. * @param[in,out] S points to an instance of the Q31 Biquad cascade structure. * @param[in] numStages number of 2nd order stages in the filter. @@ -396,27 +337,20 @@ extern "C" * @param[in] pState points to the state buffer. * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format */ - void arm_biquad_cascade_df1_init_q31( - arm_biquad_casd_df1_inst_q31 * S, - uint8_t numStages, - const q31_t * pCoeffs, - q31_t * pState, - int8_t postShift); +void arm_biquad_cascade_df1_init_q31(arm_biquad_casd_df1_inst_q31 *S, uint8_t numStages, + const q31_t *pCoeffs, q31_t *pState, int8_t postShift); - /** +/** * @brief Processing function for the floating-point Biquad cascade filter. * @param[in] S points to an instance of the floating-point Biquad cascade structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data. * @param[in] blockSize number of samples to process. */ - void arm_biquad_cascade_df1_f32( - const arm_biquad_casd_df1_inst_f32 * S, - const float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); +void arm_biquad_cascade_df1_f32(const arm_biquad_casd_df1_inst_f32 *S, const float32_t *pSrc, + float32_t *pDst, uint32_t blockSize); - /** +/** * @brief Initialization function for the floating-point Biquad cascade filter. * @param[in,out] S points to an instance of the floating-point Biquad cascade structure. * @param[in] numStages number of 2nd order stages in the filter. @@ -425,20 +359,13 @@ extern "C" * @param[in] pState points to the state buffer. */ #if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) - void arm_biquad_cascade_df1_mve_init_f32( - arm_biquad_casd_df1_inst_f32 * S, - uint8_t numStages, - const float32_t * pCoeffs, - arm_biquad_mod_coef_f32 * pCoeffsMod, - float32_t * pState); +void arm_biquad_cascade_df1_mve_init_f32(arm_biquad_casd_df1_inst_f32 *S, uint8_t numStages, + const float32_t *pCoeffs, + arm_biquad_mod_coef_f32 *pCoeffsMod, float32_t *pState); #endif - - void arm_biquad_cascade_df1_init_f32( - arm_biquad_casd_df1_inst_f32 * S, - uint8_t numStages, - const float32_t * pCoeffs, - float32_t * pState); +void arm_biquad_cascade_df1_init_f32(arm_biquad_casd_df1_inst_f32 *S, uint8_t numStages, + const float32_t *pCoeffs, float32_t *pState); /** * @brief Convolution of floating-point sequences. @@ -448,15 +375,10 @@ extern "C" * @param[in] srcBLen length of the second input sequence. * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. */ - void arm_conv_f32( - const float32_t * pSrcA, - uint32_t srcALen, - const float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst); - +void arm_conv_f32(const float32_t *pSrcA, uint32_t srcALen, const float32_t *pSrcB, + uint32_t srcBLen, float32_t *pDst); - /** +/** * @brief Convolution of Q15 sequences. * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. @@ -466,15 +388,8 @@ extern "C" * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). */ - void arm_conv_opt_q15( - const q15_t * pSrcA, - uint32_t srcALen, - const q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - +void arm_conv_opt_q15(const q15_t *pSrcA, uint32_t srcALen, const q15_t *pSrcB, uint32_t srcBLen, + q15_t *pDst, q15_t *pScratch1, q15_t *pScratch2); /** * @brief Convolution of Q15 sequences. @@ -484,15 +399,10 @@ extern "C" * @param[in] srcBLen length of the second input sequence. * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. */ - void arm_conv_q15( - const q15_t * pSrcA, - uint32_t srcALen, - const q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - +void arm_conv_q15(const q15_t *pSrcA, uint32_t srcALen, const q15_t *pSrcB, uint32_t srcBLen, + q15_t *pDst); - /** +/** * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. @@ -500,15 +410,10 @@ extern "C" * @param[in] srcBLen length of the second input sequence. * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. */ - void arm_conv_fast_q15( - const q15_t * pSrcA, - uint32_t srcALen, - const q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - +void arm_conv_fast_q15(const q15_t *pSrcA, uint32_t srcALen, const q15_t *pSrcB, uint32_t srcBLen, + q15_t *pDst); - /** +/** * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. @@ -518,17 +423,10 @@ extern "C" * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). */ - void arm_conv_fast_opt_q15( - const q15_t * pSrcA, - uint32_t srcALen, - const q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - +void arm_conv_fast_opt_q15(const q15_t *pSrcA, uint32_t srcALen, const q15_t *pSrcB, + uint32_t srcBLen, q15_t *pDst, q15_t *pScratch1, q15_t *pScratch2); - /** +/** * @brief Convolution of Q31 sequences. * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. @@ -536,15 +434,10 @@ extern "C" * @param[in] srcBLen length of the second input sequence. * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. */ - void arm_conv_q31( - const q31_t * pSrcA, - uint32_t srcALen, - const q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - +void arm_conv_q31(const q31_t *pSrcA, uint32_t srcALen, const q31_t *pSrcB, uint32_t srcBLen, + q31_t *pDst); - /** +/** * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. @@ -552,15 +445,10 @@ extern "C" * @param[in] srcBLen length of the second input sequence. * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. */ - void arm_conv_fast_q31( - const q31_t * pSrcA, - uint32_t srcALen, - const q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - +void arm_conv_fast_q31(const q31_t *pSrcA, uint32_t srcALen, const q31_t *pSrcB, uint32_t srcBLen, + q31_t *pDst); - /** +/** * @brief Convolution of Q7 sequences. * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. @@ -570,17 +458,10 @@ extern "C" * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). */ - void arm_conv_opt_q7( - const q7_t * pSrcA, - uint32_t srcALen, - const q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - +void arm_conv_opt_q7(const q7_t *pSrcA, uint32_t srcALen, const q7_t *pSrcB, uint32_t srcBLen, + q7_t *pDst, q15_t *pScratch1, q15_t *pScratch2); - /** +/** * @brief Convolution of Q7 sequences. * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. @@ -588,15 +469,10 @@ extern "C" * @param[in] srcBLen length of the second input sequence. * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. */ - void arm_conv_q7( - const q7_t * pSrcA, - uint32_t srcALen, - const q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst); - +void arm_conv_q7(const q7_t *pSrcA, uint32_t srcALen, const q7_t *pSrcB, uint32_t srcBLen, + q7_t *pDst); - /** +/** * @brief Partial convolution of floating-point sequences. * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. @@ -607,17 +483,11 @@ extern "C" * @param[in] numPoints is the number of output points to be computed. * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. */ - arm_status arm_conv_partial_f32( - const float32_t * pSrcA, - uint32_t srcALen, - const float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - +arm_status arm_conv_partial_f32(const float32_t *pSrcA, uint32_t srcALen, const float32_t *pSrcB, + uint32_t srcBLen, float32_t *pDst, uint32_t firstIndex, + uint32_t numPoints); - /** +/** * @brief Partial convolution of Q15 sequences. * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. @@ -630,19 +500,11 @@ extern "C" * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. */ - arm_status arm_conv_partial_opt_q15( - const q15_t * pSrcA, - uint32_t srcALen, - const q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t * pScratch1, - q15_t * pScratch2); - +arm_status arm_conv_partial_opt_q15(const q15_t *pSrcA, uint32_t srcALen, const q15_t *pSrcB, + uint32_t srcBLen, q15_t *pDst, uint32_t firstIndex, + uint32_t numPoints, q15_t *pScratch1, q15_t *pScratch2); - /** +/** * @brief Partial convolution of Q15 sequences. * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. @@ -653,17 +515,11 @@ extern "C" * @param[in] numPoints is the number of output points to be computed. * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. */ - arm_status arm_conv_partial_q15( - const q15_t * pSrcA, - uint32_t srcALen, - const q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - +arm_status arm_conv_partial_q15(const q15_t *pSrcA, uint32_t srcALen, const q15_t *pSrcB, + uint32_t srcBLen, q15_t *pDst, uint32_t firstIndex, + uint32_t numPoints); - /** +/** * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. @@ -674,17 +530,11 @@ extern "C" * @param[in] numPoints is the number of output points to be computed. * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. */ - arm_status arm_conv_partial_fast_q15( - const q15_t * pSrcA, - uint32_t srcALen, - const q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - +arm_status arm_conv_partial_fast_q15(const q15_t *pSrcA, uint32_t srcALen, const q15_t *pSrcB, + uint32_t srcBLen, q15_t *pDst, uint32_t firstIndex, + uint32_t numPoints); - /** +/** * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. @@ -697,19 +547,11 @@ extern "C" * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. */ - arm_status arm_conv_partial_fast_opt_q15( - const q15_t * pSrcA, - uint32_t srcALen, - const q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t * pScratch1, - q15_t * pScratch2); - +arm_status arm_conv_partial_fast_opt_q15(const q15_t *pSrcA, uint32_t srcALen, const q15_t *pSrcB, + uint32_t srcBLen, q15_t *pDst, uint32_t firstIndex, + uint32_t numPoints, q15_t *pScratch1, q15_t *pScratch2); - /** +/** * @brief Partial convolution of Q31 sequences. * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. @@ -720,17 +562,11 @@ extern "C" * @param[in] numPoints is the number of output points to be computed. * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. */ - arm_status arm_conv_partial_q31( - const q31_t * pSrcA, - uint32_t srcALen, - const q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - +arm_status arm_conv_partial_q31(const q31_t *pSrcA, uint32_t srcALen, const q31_t *pSrcB, + uint32_t srcBLen, q31_t *pDst, uint32_t firstIndex, + uint32_t numPoints); - /** +/** * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. @@ -741,17 +577,11 @@ extern "C" * @param[in] numPoints is the number of output points to be computed. * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. */ - arm_status arm_conv_partial_fast_q31( - const q31_t * pSrcA, - uint32_t srcALen, - const q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - +arm_status arm_conv_partial_fast_q31(const q31_t *pSrcA, uint32_t srcALen, const q31_t *pSrcB, + uint32_t srcBLen, q31_t *pDst, uint32_t firstIndex, + uint32_t numPoints); - /** +/** * @brief Partial convolution of Q7 sequences * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. @@ -764,17 +594,9 @@ extern "C" * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. */ - arm_status arm_conv_partial_opt_q7( - const q7_t * pSrcA, - uint32_t srcALen, - const q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t * pScratch1, - q15_t * pScratch2); - +arm_status arm_conv_partial_opt_q7(const q7_t *pSrcA, uint32_t srcALen, const q7_t *pSrcB, + uint32_t srcBLen, q7_t *pDst, uint32_t firstIndex, + uint32_t numPoints, q15_t *pScratch1, q15_t *pScratch2); /** * @brief Partial convolution of Q7 sequences. @@ -787,75 +609,65 @@ extern "C" * @param[in] numPoints is the number of output points to be computed. * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. */ - arm_status arm_conv_partial_q7( - const q7_t * pSrcA, - uint32_t srcALen, - const q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); +arm_status arm_conv_partial_q7(const q7_t *pSrcA, uint32_t srcALen, const q7_t *pSrcB, + uint32_t srcBLen, q7_t *pDst, uint32_t firstIndex, + uint32_t numPoints); - - /** +/** * @brief Instance structure for the Q15 FIR decimator. */ - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - } arm_fir_decimate_instance_q15; +typedef struct { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q15_t * + pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ +} arm_fir_decimate_instance_q15; - /** +/** * @brief Instance structure for the Q31 FIR decimator. */ - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - } arm_fir_decimate_instance_q31; +typedef struct { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q31_t * + pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ +} arm_fir_decimate_instance_q31; /** @brief Instance structure for single precision floating-point FIR decimator. */ -typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - } arm_fir_decimate_instance_f32; - - /** +typedef struct { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + float32_t * + pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ +} arm_fir_decimate_instance_f32; + +/** @brief Instance structure for double precision floating-point FIR decimator. */ - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - const float64_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - float64_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - } arm_fir_decimate_instance_f64; - - /** +typedef struct { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + const float64_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + float64_t * + pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ +} arm_fir_decimate_instance_f64; + +/** @brief Processing function for floating-point FIR decimator. @param[in] S points to an instance of the floating-point FIR decimator structure @param[in] pSrc points to the block of input data @param[out] pDst points to the block of output data @param[in] blockSize number of samples to process */ - void arm_fir_decimate_f64( - const arm_fir_decimate_instance_f64 * S, - const float64_t * pSrc, - float64_t * pDst, - uint32_t blockSize); +void arm_fir_decimate_f64(const arm_fir_decimate_instance_f64 *S, const float64_t *pSrc, + float64_t *pDst, uint32_t blockSize); - - /** +/** @brief Initialization function for the floating-point FIR decimator. @param[in,out] S points to an instance of the floating-point FIR decimator structure @param[in] numTaps number of coefficients in the filter @@ -867,28 +679,19 @@ typedef struct - \ref ARM_MATH_SUCCESS : Operation successful - \ref ARM_MATH_LENGTH_ERROR : blockSize is not a multiple of M */ - arm_status arm_fir_decimate_init_f64( - arm_fir_decimate_instance_f64 * S, - uint16_t numTaps, - uint8_t M, - const float64_t * pCoeffs, - float64_t * pState, - uint32_t blockSize); +arm_status arm_fir_decimate_init_f64(arm_fir_decimate_instance_f64 *S, uint16_t numTaps, uint8_t M, + const float64_t *pCoeffs, float64_t *pState, + uint32_t blockSize); - - /** +/** @brief Processing function for floating-point FIR decimator. @param[in] S points to an instance of the floating-point FIR decimator structure @param[in] pSrc points to the block of input data @param[out] pDst points to the block of output data @param[in] blockSize number of samples to process */ -void arm_fir_decimate_f32( - const arm_fir_decimate_instance_f32 * S, - const float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - +void arm_fir_decimate_f32(const arm_fir_decimate_instance_f32 *S, const float32_t *pSrc, + float32_t *pDst, uint32_t blockSize); /** @brief Initialization function for the floating-point FIR decimator. @@ -902,44 +705,31 @@ void arm_fir_decimate_f32( - \ref ARM_MATH_SUCCESS : Operation successful - \ref ARM_MATH_LENGTH_ERROR : blockSize is not a multiple of M */ -arm_status arm_fir_decimate_init_f32( - arm_fir_decimate_instance_f32 * S, - uint16_t numTaps, - uint8_t M, - const float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - +arm_status arm_fir_decimate_init_f32(arm_fir_decimate_instance_f32 *S, uint16_t numTaps, uint8_t M, + const float32_t *pCoeffs, float32_t *pState, + uint32_t blockSize); - /** +/** * @brief Processing function for the Q15 FIR decimator. * @param[in] S points to an instance of the Q15 FIR decimator structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data * @param[in] blockSize number of input samples to process per call. */ - void arm_fir_decimate_q15( - const arm_fir_decimate_instance_q15 * S, - const q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - +void arm_fir_decimate_q15(const arm_fir_decimate_instance_q15 *S, const q15_t *pSrc, q15_t *pDst, + uint32_t blockSize); - /** +/** * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. * @param[in] S points to an instance of the Q15 FIR decimator structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data * @param[in] blockSize number of input samples to process per call. */ - void arm_fir_decimate_fast_q15( - const arm_fir_decimate_instance_q15 * S, - const q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - +void arm_fir_decimate_fast_q15(const arm_fir_decimate_instance_q15 *S, const q15_t *pSrc, + q15_t *pDst, uint32_t blockSize); - /** +/** * @brief Initialization function for the Q15 FIR decimator. * @param[in,out] S points to an instance of the Q15 FIR decimator structure. * @param[in] numTaps number of coefficients in the filter. @@ -950,43 +740,30 @@ arm_status arm_fir_decimate_init_f32( * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if * blockSize is not a multiple of M. */ - arm_status arm_fir_decimate_init_q15( - arm_fir_decimate_instance_q15 * S, - uint16_t numTaps, - uint8_t M, - const q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - +arm_status arm_fir_decimate_init_q15(arm_fir_decimate_instance_q15 *S, uint16_t numTaps, uint8_t M, + const q15_t *pCoeffs, q15_t *pState, uint32_t blockSize); - /** +/** * @brief Processing function for the Q31 FIR decimator. * @param[in] S points to an instance of the Q31 FIR decimator structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data * @param[in] blockSize number of input samples to process per call. */ - void arm_fir_decimate_q31( - const arm_fir_decimate_instance_q31 * S, - const q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); +void arm_fir_decimate_q31(const arm_fir_decimate_instance_q31 *S, const q31_t *pSrc, q31_t *pDst, + uint32_t blockSize); - /** +/** * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. * @param[in] S points to an instance of the Q31 FIR decimator structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data * @param[in] blockSize number of input samples to process per call. */ - void arm_fir_decimate_fast_q31( - const arm_fir_decimate_instance_q31 * S, - const q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); +void arm_fir_decimate_fast_q31(const arm_fir_decimate_instance_q31 *S, const q31_t *pSrc, + q31_t *pDst, uint32_t blockSize); - - /** +/** * @brief Initialization function for the Q31 FIR decimator. * @param[in,out] S points to an instance of the Q31 FIR decimator structure. * @param[in] numTaps number of coefficients in the filter. @@ -997,64 +774,56 @@ arm_status arm_fir_decimate_init_f32( * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if * blockSize is not a multiple of M. */ - arm_status arm_fir_decimate_init_q31( - arm_fir_decimate_instance_q31 * S, - uint16_t numTaps, - uint8_t M, - const q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); +arm_status arm_fir_decimate_init_q31(arm_fir_decimate_instance_q31 *S, uint16_t numTaps, uint8_t M, + const q31_t *pCoeffs, q31_t *pState, uint32_t blockSize); - - /** +/** * @brief Instance structure for the Q15 FIR interpolator. */ - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ - } arm_fir_interpolate_instance_q15; +typedef struct { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + const q15_t + *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q15_t * + pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ +} arm_fir_interpolate_instance_q15; - /** +/** * @brief Instance structure for the Q31 FIR interpolator. */ - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ - } arm_fir_interpolate_instance_q31; +typedef struct { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + const q31_t + *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q31_t * + pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ +} arm_fir_interpolate_instance_q31; - /** +/** * @brief Instance structure for the floating-point FIR interpolator. */ - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ - } arm_fir_interpolate_instance_f32; +typedef struct { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + const float32_t + *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + float32_t * + pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ +} arm_fir_interpolate_instance_f32; - - /** +/** * @brief Processing function for the Q15 FIR interpolator. * @param[in] S points to an instance of the Q15 FIR interpolator structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data. * @param[in] blockSize number of input samples to process per call. */ - void arm_fir_interpolate_q15( - const arm_fir_interpolate_instance_q15 * S, - const q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); +void arm_fir_interpolate_q15(const arm_fir_interpolate_instance_q15 *S, const q15_t *pSrc, + q15_t *pDst, uint32_t blockSize); - - /** +/** * @brief Initialization function for the Q15 FIR interpolator. * @param[in,out] S points to an instance of the Q15 FIR interpolator structure. * @param[in] L upsample factor. @@ -1065,30 +834,21 @@ arm_status arm_fir_decimate_init_f32( * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if * the filter length numTaps is not a multiple of the interpolation factor L. */ - arm_status arm_fir_interpolate_init_q15( - arm_fir_interpolate_instance_q15 * S, - uint8_t L, - uint16_t numTaps, - const q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); +arm_status arm_fir_interpolate_init_q15(arm_fir_interpolate_instance_q15 *S, uint8_t L, + uint16_t numTaps, const q15_t *pCoeffs, q15_t *pState, + uint32_t blockSize); - - /** +/** * @brief Processing function for the Q31 FIR interpolator. * @param[in] S points to an instance of the Q15 FIR interpolator structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data. * @param[in] blockSize number of input samples to process per call. */ - void arm_fir_interpolate_q31( - const arm_fir_interpolate_instance_q31 * S, - const q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); +void arm_fir_interpolate_q31(const arm_fir_interpolate_instance_q31 *S, const q31_t *pSrc, + q31_t *pDst, uint32_t blockSize); - - /** +/** * @brief Initialization function for the Q31 FIR interpolator. * @param[in,out] S points to an instance of the Q31 FIR interpolator structure. * @param[in] L upsample factor. @@ -1099,30 +859,21 @@ arm_status arm_fir_decimate_init_f32( * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if * the filter length numTaps is not a multiple of the interpolation factor L. */ - arm_status arm_fir_interpolate_init_q31( - arm_fir_interpolate_instance_q31 * S, - uint8_t L, - uint16_t numTaps, - const q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); +arm_status arm_fir_interpolate_init_q31(arm_fir_interpolate_instance_q31 *S, uint8_t L, + uint16_t numTaps, const q31_t *pCoeffs, q31_t *pState, + uint32_t blockSize); - - /** +/** * @brief Processing function for the floating-point FIR interpolator. * @param[in] S points to an instance of the floating-point FIR interpolator structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data. * @param[in] blockSize number of input samples to process per call. */ - void arm_fir_interpolate_f32( - const arm_fir_interpolate_instance_f32 * S, - const float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); +void arm_fir_interpolate_f32(const arm_fir_interpolate_instance_f32 *S, const float32_t *pSrc, + float32_t *pDst, uint32_t blockSize); - - /** +/** * @brief Initialization function for the floating-point FIR interpolator. * @param[in,out] S points to an instance of the floating-point FIR interpolator structure. * @param[in] L upsample factor. @@ -1133,268 +884,216 @@ arm_status arm_fir_decimate_init_f32( * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if * the filter length numTaps is not a multiple of the interpolation factor L. */ - arm_status arm_fir_interpolate_init_f32( - arm_fir_interpolate_instance_f32 * S, - uint8_t L, - uint16_t numTaps, - const float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); +arm_status arm_fir_interpolate_init_f32(arm_fir_interpolate_instance_f32 *S, uint8_t L, + uint16_t numTaps, const float32_t *pCoeffs, + float32_t *pState, uint32_t blockSize); - - /** +/** * @brief Instance structure for the high precision Q31 Biquad cascade filter. */ - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ - const q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ - } arm_biquad_cas_df1_32x64_ins_q31; +typedef struct { + uint8_t + numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q63_t * + pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + const q31_t + *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ +} arm_biquad_cas_df1_32x64_ins_q31; - - /** +/** * @param[in] S points to an instance of the high precision Q31 Biquad cascade filter structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data * @param[in] blockSize number of samples to process. */ - void arm_biquad_cas_df1_32x64_q31( - const arm_biquad_cas_df1_32x64_ins_q31 * S, - const q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); +void arm_biquad_cas_df1_32x64_q31(const arm_biquad_cas_df1_32x64_ins_q31 *S, const q31_t *pSrc, + q31_t *pDst, uint32_t blockSize); - - /** +/** * @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure. * @param[in] numStages number of 2nd order stages in the filter. * @param[in] pCoeffs points to the filter coefficients. * @param[in] pState points to the state buffer. * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format */ - void arm_biquad_cas_df1_32x64_init_q31( - arm_biquad_cas_df1_32x64_ins_q31 * S, - uint8_t numStages, - const q31_t * pCoeffs, - q63_t * pState, - uint8_t postShift); +void arm_biquad_cas_df1_32x64_init_q31(arm_biquad_cas_df1_32x64_ins_q31 *S, uint8_t numStages, + const q31_t *pCoeffs, q63_t *pState, uint8_t postShift); - - /** +/** * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. */ - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ - const float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - } arm_biquad_cascade_df2T_instance_f32; +typedef struct { + uint8_t + numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t * + pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + const float32_t + *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ +} arm_biquad_cascade_df2T_instance_f32; - /** +/** * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. */ - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ - const float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - } arm_biquad_cascade_stereo_df2T_instance_f32; +typedef struct { + uint8_t + numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t * + pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + const float32_t + *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ +} arm_biquad_cascade_stereo_df2T_instance_f32; - /** +/** * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. */ - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ - const float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - } arm_biquad_cascade_df2T_instance_f64; +typedef struct { + uint8_t + numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float64_t * + pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + const float64_t + *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ +} arm_biquad_cascade_df2T_instance_f64; - - /** +/** * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. * @param[in] S points to an instance of the filter data structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data * @param[in] blockSize number of samples to process. */ - void arm_biquad_cascade_df2T_f32( - const arm_biquad_cascade_df2T_instance_f32 * S, - const float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); +void arm_biquad_cascade_df2T_f32(const arm_biquad_cascade_df2T_instance_f32 *S, + const float32_t *pSrc, float32_t *pDst, uint32_t blockSize); - - /** +/** * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels * @param[in] S points to an instance of the filter data structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data * @param[in] blockSize number of samples to process. */ - void arm_biquad_cascade_stereo_df2T_f32( - const arm_biquad_cascade_stereo_df2T_instance_f32 * S, - const float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); +void arm_biquad_cascade_stereo_df2T_f32(const arm_biquad_cascade_stereo_df2T_instance_f32 *S, + const float32_t *pSrc, float32_t *pDst, uint32_t blockSize); - - /** +/** * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. * @param[in] S points to an instance of the filter data structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data * @param[in] blockSize number of samples to process. */ - void arm_biquad_cascade_df2T_f64( - const arm_biquad_cascade_df2T_instance_f64 * S, - const float64_t * pSrc, - float64_t * pDst, - uint32_t blockSize); +void arm_biquad_cascade_df2T_f64(const arm_biquad_cascade_df2T_instance_f64 *S, + const float64_t *pSrc, float64_t *pDst, uint32_t blockSize); - -#if defined(ARM_MATH_NEON) +#if defined(ARM_MATH_NEON) /** @brief Compute new coefficient arrays for use in vectorized filter (Neon only). @param[in] numStages number of 2nd order stages in the filter. @param[in] pCoeffs points to the original filter coefficients. @param[in] pComputedCoeffs points to the new computed coefficients for the vectorized version. */ -void arm_biquad_cascade_df2T_compute_coefs_f32( - uint8_t numStages, - const float32_t * pCoeffs, - float32_t * pComputedCoeffs); +void arm_biquad_cascade_df2T_compute_coefs_f32(uint8_t numStages, const float32_t *pCoeffs, + float32_t *pComputedCoeffs); #endif - /** +/** * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. * @param[in,out] S points to an instance of the filter data structure. * @param[in] numStages number of 2nd order stages in the filter. * @param[in] pCoeffs points to the filter coefficients. * @param[in] pState points to the state buffer. */ - void arm_biquad_cascade_df2T_init_f32( - arm_biquad_cascade_df2T_instance_f32 * S, - uint8_t numStages, - const float32_t * pCoeffs, - float32_t * pState); +void arm_biquad_cascade_df2T_init_f32(arm_biquad_cascade_df2T_instance_f32 *S, uint8_t numStages, + const float32_t *pCoeffs, float32_t *pState); - - /** +/** * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. * @param[in,out] S points to an instance of the filter data structure. * @param[in] numStages number of 2nd order stages in the filter. * @param[in] pCoeffs points to the filter coefficients. * @param[in] pState points to the state buffer. */ - void arm_biquad_cascade_stereo_df2T_init_f32( - arm_biquad_cascade_stereo_df2T_instance_f32 * S, - uint8_t numStages, - const float32_t * pCoeffs, - float32_t * pState); +void arm_biquad_cascade_stereo_df2T_init_f32(arm_biquad_cascade_stereo_df2T_instance_f32 *S, + uint8_t numStages, const float32_t *pCoeffs, + float32_t *pState); - - /** +/** * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. * @param[in,out] S points to an instance of the filter data structure. * @param[in] numStages number of 2nd order stages in the filter. * @param[in] pCoeffs points to the filter coefficients. * @param[in] pState points to the state buffer. */ - void arm_biquad_cascade_df2T_init_f64( - arm_biquad_cascade_df2T_instance_f64 * S, - uint8_t numStages, - const float64_t * pCoeffs, - float64_t * pState); +void arm_biquad_cascade_df2T_init_f64(arm_biquad_cascade_df2T_instance_f64 *S, uint8_t numStages, + const float64_t *pCoeffs, float64_t *pState); - - /** +/** * @brief Instance structure for the Q15 FIR lattice filter. */ - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ - const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_q15; +typedef struct { + uint16_t numStages; /**< number of filter stages. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ + const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ +} arm_fir_lattice_instance_q15; - /** +/** * @brief Instance structure for the Q31 FIR lattice filter. */ - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ - const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_q31; +typedef struct { + uint16_t numStages; /**< number of filter stages. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ + const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ +} arm_fir_lattice_instance_q31; - /** +/** * @brief Instance structure for the floating-point FIR lattice filter. */ - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ - const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_f32; +typedef struct { + uint16_t numStages; /**< number of filter stages. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ + const float32_t + *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ +} arm_fir_lattice_instance_f32; - - /** +/** * @brief Initialization function for the Q15 FIR lattice filter. * @param[in] S points to an instance of the Q15 FIR lattice structure. * @param[in] numStages number of filter stages. * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. * @param[in] pState points to the state buffer. The array is of length numStages. */ - void arm_fir_lattice_init_q15( - arm_fir_lattice_instance_q15 * S, - uint16_t numStages, - const q15_t * pCoeffs, - q15_t * pState); - +void arm_fir_lattice_init_q15(arm_fir_lattice_instance_q15 *S, uint16_t numStages, + const q15_t *pCoeffs, q15_t *pState); - /** +/** * @brief Processing function for the Q15 FIR lattice filter. * @param[in] S points to an instance of the Q15 FIR lattice structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data. * @param[in] blockSize number of samples to process. */ - void arm_fir_lattice_q15( - const arm_fir_lattice_instance_q15 * S, - const q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - +void arm_fir_lattice_q15(const arm_fir_lattice_instance_q15 *S, const q15_t *pSrc, q15_t *pDst, + uint32_t blockSize); - /** +/** * @brief Initialization function for the Q31 FIR lattice filter. * @param[in] S points to an instance of the Q31 FIR lattice structure. * @param[in] numStages number of filter stages. * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. * @param[in] pState points to the state buffer. The array is of length numStages. */ - void arm_fir_lattice_init_q31( - arm_fir_lattice_instance_q31 * S, - uint16_t numStages, - const q31_t * pCoeffs, - q31_t * pState); - +void arm_fir_lattice_init_q31(arm_fir_lattice_instance_q31 *S, uint16_t numStages, + const q31_t *pCoeffs, q31_t *pState); - /** +/** * @brief Processing function for the Q31 FIR lattice filter. * @param[in] S points to an instance of the Q31 FIR lattice structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data * @param[in] blockSize number of samples to process. */ - void arm_fir_lattice_q31( - const arm_fir_lattice_instance_q31 * S, - const q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - +void arm_fir_lattice_q31(const arm_fir_lattice_instance_q31 *S, const q31_t *pSrc, q31_t *pDst, + uint32_t blockSize); /** * @brief Initialization function for the floating-point FIR lattice filter. @@ -1403,76 +1102,69 @@ void arm_biquad_cascade_df2T_compute_coefs_f32( * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. * @param[in] pState points to the state buffer. The array is of length numStages. */ - void arm_fir_lattice_init_f32( - arm_fir_lattice_instance_f32 * S, - uint16_t numStages, - const float32_t * pCoeffs, - float32_t * pState); +void arm_fir_lattice_init_f32(arm_fir_lattice_instance_f32 *S, uint16_t numStages, + const float32_t *pCoeffs, float32_t *pState); - - /** +/** * @brief Processing function for the floating-point FIR lattice filter. * @param[in] S points to an instance of the floating-point FIR lattice structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data * @param[in] blockSize number of samples to process. */ - void arm_fir_lattice_f32( - const arm_fir_lattice_instance_f32 * S, - const float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); +void arm_fir_lattice_f32(const arm_fir_lattice_instance_f32 *S, const float32_t *pSrc, + float32_t *pDst, uint32_t blockSize); - - /** +/** * @brief Instance structure for the Q15 IIR lattice filter. */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } arm_iir_lattice_instance_q15; +typedef struct { + uint16_t numStages; /**< number of stages in the filter. */ + q15_t * + pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q15_t * + pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q15_t * + pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ +} arm_iir_lattice_instance_q15; - /** +/** * @brief Instance structure for the Q31 IIR lattice filter. */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } arm_iir_lattice_instance_q31; +typedef struct { + uint16_t numStages; /**< number of stages in the filter. */ + q31_t * + pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q31_t * + pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q31_t * + pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ +} arm_iir_lattice_instance_q31; - /** +/** * @brief Instance structure for the floating-point IIR lattice filter. */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } arm_iir_lattice_instance_f32; +typedef struct { + uint16_t numStages; /**< number of stages in the filter. */ + float32_t * + pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + float32_t * + pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + float32_t * + pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ +} arm_iir_lattice_instance_f32; - - /** +/** * @brief Processing function for the floating-point IIR lattice filter. * @param[in] S points to an instance of the floating-point IIR lattice structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data. * @param[in] blockSize number of samples to process. */ - void arm_iir_lattice_f32( - const arm_iir_lattice_instance_f32 * S, - const float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); +void arm_iir_lattice_f32(const arm_iir_lattice_instance_f32 *S, const float32_t *pSrc, + float32_t *pDst, uint32_t blockSize); - - /** +/** * @brief Initialization function for the floating-point IIR lattice filter. * @param[in] S points to an instance of the floating-point IIR lattice structure. * @param[in] numStages number of stages in the filter. @@ -1481,30 +1173,21 @@ void arm_biquad_cascade_df2T_compute_coefs_f32( * @param[in] pState points to the state buffer. The array is of length numStages+blockSize-1. * @param[in] blockSize number of samples to process. */ - void arm_iir_lattice_init_f32( - arm_iir_lattice_instance_f32 * S, - uint16_t numStages, - float32_t * pkCoeffs, - float32_t * pvCoeffs, - float32_t * pState, - uint32_t blockSize); +void arm_iir_lattice_init_f32(arm_iir_lattice_instance_f32 *S, uint16_t numStages, + float32_t *pkCoeffs, float32_t *pvCoeffs, float32_t *pState, + uint32_t blockSize); - - /** +/** * @brief Processing function for the Q31 IIR lattice filter. * @param[in] S points to an instance of the Q31 IIR lattice structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data. * @param[in] blockSize number of samples to process. */ - void arm_iir_lattice_q31( - const arm_iir_lattice_instance_q31 * S, - const q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); +void arm_iir_lattice_q31(const arm_iir_lattice_instance_q31 *S, const q31_t *pSrc, q31_t *pDst, + uint32_t blockSize); - - /** +/** * @brief Initialization function for the Q31 IIR lattice filter. * @param[in] S points to an instance of the Q31 IIR lattice structure. * @param[in] numStages number of stages in the filter. @@ -1513,28 +1196,18 @@ void arm_biquad_cascade_df2T_compute_coefs_f32( * @param[in] pState points to the state buffer. The array is of length numStages+blockSize. * @param[in] blockSize number of samples to process. */ - void arm_iir_lattice_init_q31( - arm_iir_lattice_instance_q31 * S, - uint16_t numStages, - q31_t * pkCoeffs, - q31_t * pvCoeffs, - q31_t * pState, - uint32_t blockSize); +void arm_iir_lattice_init_q31(arm_iir_lattice_instance_q31 *S, uint16_t numStages, q31_t *pkCoeffs, + q31_t *pvCoeffs, q31_t *pState, uint32_t blockSize); - - /** +/** * @brief Processing function for the Q15 IIR lattice filter. * @param[in] S points to an instance of the Q15 IIR lattice structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data. * @param[in] blockSize number of samples to process. */ - void arm_iir_lattice_q15( - const arm_iir_lattice_instance_q15 * S, - const q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - +void arm_iir_lattice_q15(const arm_iir_lattice_instance_q15 *S, const q15_t *pSrc, q15_t *pDst, + uint32_t blockSize); /** * @brief Initialization function for the Q15 IIR lattice filter. @@ -1545,28 +1218,21 @@ void arm_biquad_cascade_df2T_compute_coefs_f32( * @param[in] pState points to state buffer. The array is of length numStages+blockSize. * @param[in] blockSize number of samples to process per call. */ - void arm_iir_lattice_init_q15( - arm_iir_lattice_instance_q15 * S, - uint16_t numStages, - q15_t * pkCoeffs, - q15_t * pvCoeffs, - q15_t * pState, - uint32_t blockSize); - +void arm_iir_lattice_init_q15(arm_iir_lattice_instance_q15 *S, uint16_t numStages, q15_t *pkCoeffs, + q15_t *pvCoeffs, q15_t *pState, uint32_t blockSize); - /** +/** * @brief Instance structure for the floating-point LMS filter. */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - float32_t mu; /**< step size that controls filter coefficient updates. */ - } arm_lms_instance_f32; - +typedef struct { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t * + pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that controls filter coefficient updates. */ +} arm_lms_instance_f32; - /** +/** * @brief Processing function for floating-point LMS filter. * @param[in] S points to an instance of the floating-point LMS filter structure. * @param[in] pSrc points to the block of input data. @@ -1575,16 +1241,10 @@ void arm_biquad_cascade_df2T_compute_coefs_f32( * @param[out] pErr points to the block of error data. * @param[in] blockSize number of samples to process. */ - void arm_lms_f32( - const arm_lms_instance_f32 * S, - const float32_t * pSrc, - float32_t * pRef, - float32_t * pOut, - float32_t * pErr, - uint32_t blockSize); - +void arm_lms_f32(const arm_lms_instance_f32 *S, const float32_t *pSrc, float32_t *pRef, + float32_t *pOut, float32_t *pErr, uint32_t blockSize); - /** +/** * @brief Initialization function for floating-point LMS filter. * @param[in] S points to an instance of the floating-point LMS filter structure. * @param[in] numTaps number of filter coefficients. @@ -1593,29 +1253,22 @@ void arm_biquad_cascade_df2T_compute_coefs_f32( * @param[in] mu step size that controls filter coefficient updates. * @param[in] blockSize number of samples to process. */ - void arm_lms_init_f32( - arm_lms_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - float32_t mu, - uint32_t blockSize); - +void arm_lms_init_f32(arm_lms_instance_f32 *S, uint16_t numTaps, float32_t *pCoeffs, + float32_t *pState, float32_t mu, uint32_t blockSize); - /** +/** * @brief Instance structure for the Q15 LMS filter. */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q15_t mu; /**< step size that controls filter coefficient updates. */ - uint32_t postShift; /**< bit shift applied to coefficients. */ - } arm_lms_instance_q15; - +typedef struct { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t * + pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ +} arm_lms_instance_q15; - /** +/** * @brief Initialization function for the Q15 LMS filter. * @param[in] S points to an instance of the Q15 LMS filter structure. * @param[in] numTaps number of filter coefficients. @@ -1625,17 +1278,10 @@ void arm_biquad_cascade_df2T_compute_coefs_f32( * @param[in] blockSize number of samples to process. * @param[in] postShift bit shift applied to coefficients. */ - void arm_lms_init_q15( - arm_lms_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - q15_t mu, - uint32_t blockSize, - uint32_t postShift); +void arm_lms_init_q15(arm_lms_instance_q15 *S, uint16_t numTaps, q15_t *pCoeffs, q15_t *pState, + q15_t mu, uint32_t blockSize, uint32_t postShift); - - /** +/** * @brief Processing function for Q15 LMS filter. * @param[in] S points to an instance of the Q15 LMS filter structure. * @param[in] pSrc points to the block of input data. @@ -1644,29 +1290,22 @@ void arm_biquad_cascade_df2T_compute_coefs_f32( * @param[out] pErr points to the block of error data. * @param[in] blockSize number of samples to process. */ - void arm_lms_q15( - const arm_lms_instance_q15 * S, - const q15_t * pSrc, - q15_t * pRef, - q15_t * pOut, - q15_t * pErr, - uint32_t blockSize); +void arm_lms_q15(const arm_lms_instance_q15 *S, const q15_t *pSrc, q15_t *pRef, q15_t *pOut, + q15_t *pErr, uint32_t blockSize); - - /** +/** * @brief Instance structure for the Q31 LMS filter. */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q31_t mu; /**< step size that controls filter coefficient updates. */ - uint32_t postShift; /**< bit shift applied to coefficients. */ - } arm_lms_instance_q31; +typedef struct { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t * + pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ +} arm_lms_instance_q31; - - /** +/** * @brief Processing function for Q31 LMS filter. * @param[in] S points to an instance of the Q15 LMS filter structure. * @param[in] pSrc points to the block of input data. @@ -1675,16 +1314,10 @@ void arm_biquad_cascade_df2T_compute_coefs_f32( * @param[out] pErr points to the block of error data. * @param[in] blockSize number of samples to process. */ - void arm_lms_q31( - const arm_lms_instance_q31 * S, - const q31_t * pSrc, - q31_t * pRef, - q31_t * pOut, - q31_t * pErr, - uint32_t blockSize); +void arm_lms_q31(const arm_lms_instance_q31 *S, const q31_t *pSrc, q31_t *pRef, q31_t *pOut, + q31_t *pErr, uint32_t blockSize); - - /** +/** * @brief Initialization function for Q31 LMS filter. * @param[in] S points to an instance of the Q31 LMS filter structure. * @param[in] numTaps number of filter coefficients. @@ -1694,31 +1327,23 @@ void arm_biquad_cascade_df2T_compute_coefs_f32( * @param[in] blockSize number of samples to process. * @param[in] postShift bit shift applied to coefficients. */ - void arm_lms_init_q31( - arm_lms_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - q31_t mu, - uint32_t blockSize, - uint32_t postShift); +void arm_lms_init_q31(arm_lms_instance_q31 *S, uint16_t numTaps, q31_t *pCoeffs, q31_t *pState, + q31_t mu, uint32_t blockSize, uint32_t postShift); - - /** +/** * @brief Instance structure for the floating-point normalized LMS filter. */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - float32_t mu; /**< step size that control filter coefficient updates. */ - float32_t energy; /**< saves previous frame energy. */ - float32_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_f32; +typedef struct { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t * + pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that control filter coefficient updates. */ + float32_t energy; /**< saves previous frame energy. */ + float32_t x0; /**< saves previous input sample. */ +} arm_lms_norm_instance_f32; - - /** +/** * @brief Processing function for floating-point normalized LMS filter. * @param[in] S points to an instance of the floating-point normalized LMS filter structure. * @param[in] pSrc points to the block of input data. @@ -1727,16 +1352,10 @@ void arm_biquad_cascade_df2T_compute_coefs_f32( * @param[out] pErr points to the block of error data. * @param[in] blockSize number of samples to process. */ - void arm_lms_norm_f32( - arm_lms_norm_instance_f32 * S, - const float32_t * pSrc, - float32_t * pRef, - float32_t * pOut, - float32_t * pErr, - uint32_t blockSize); +void arm_lms_norm_f32(arm_lms_norm_instance_f32 *S, const float32_t *pSrc, float32_t *pRef, + float32_t *pOut, float32_t *pErr, uint32_t blockSize); - - /** +/** * @brief Initialization function for floating-point normalized LMS filter. * @param[in] S points to an instance of the floating-point LMS filter structure. * @param[in] numTaps number of filter coefficients. @@ -1745,32 +1364,25 @@ void arm_biquad_cascade_df2T_compute_coefs_f32( * @param[in] mu step size that controls filter coefficient updates. * @param[in] blockSize number of samples to process. */ - void arm_lms_norm_init_f32( - arm_lms_norm_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - float32_t mu, - uint32_t blockSize); +void arm_lms_norm_init_f32(arm_lms_norm_instance_f32 *S, uint16_t numTaps, float32_t *pCoeffs, + float32_t *pState, float32_t mu, uint32_t blockSize); - - /** +/** * @brief Instance structure for the Q31 normalized LMS filter. */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q31_t mu; /**< step size that controls filter coefficient updates. */ - uint8_t postShift; /**< bit shift applied to coefficients. */ - const q31_t *recipTable; /**< points to the reciprocal initial value table. */ - q31_t energy; /**< saves previous frame energy. */ - q31_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_q31; +typedef struct { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t * + pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + const q31_t *recipTable; /**< points to the reciprocal initial value table. */ + q31_t energy; /**< saves previous frame energy. */ + q31_t x0; /**< saves previous input sample. */ +} arm_lms_norm_instance_q31; - - /** +/** * @brief Processing function for Q31 normalized LMS filter. * @param[in] S points to an instance of the Q31 normalized LMS filter structure. * @param[in] pSrc points to the block of input data. @@ -1779,16 +1391,10 @@ void arm_biquad_cascade_df2T_compute_coefs_f32( * @param[out] pErr points to the block of error data. * @param[in] blockSize number of samples to process. */ - void arm_lms_norm_q31( - arm_lms_norm_instance_q31 * S, - const q31_t * pSrc, - q31_t * pRef, - q31_t * pOut, - q31_t * pErr, - uint32_t blockSize); +void arm_lms_norm_q31(arm_lms_norm_instance_q31 *S, const q31_t *pSrc, q31_t *pRef, q31_t *pOut, + q31_t *pErr, uint32_t blockSize); - - /** +/** * @brief Initialization function for Q31 normalized LMS filter. * @param[in] S points to an instance of the Q31 normalized LMS filter structure. * @param[in] numTaps number of filter coefficients. @@ -1798,33 +1404,25 @@ void arm_biquad_cascade_df2T_compute_coefs_f32( * @param[in] blockSize number of samples to process. * @param[in] postShift bit shift applied to coefficients. */ - void arm_lms_norm_init_q31( - arm_lms_norm_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - q31_t mu, - uint32_t blockSize, - uint8_t postShift); +void arm_lms_norm_init_q31(arm_lms_norm_instance_q31 *S, uint16_t numTaps, q31_t *pCoeffs, + q31_t *pState, q31_t mu, uint32_t blockSize, uint8_t postShift); - - /** +/** * @brief Instance structure for the Q15 normalized LMS filter. */ - typedef struct - { - uint16_t numTaps; /**< Number of coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q15_t mu; /**< step size that controls filter coefficient updates. */ - uint8_t postShift; /**< bit shift applied to coefficients. */ - const q15_t *recipTable; /**< Points to the reciprocal initial value table. */ - q15_t energy; /**< saves previous frame energy. */ - q15_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_q15; +typedef struct { + uint16_t numTaps; /**< Number of coefficients in the filter. */ + q15_t * + pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + const q15_t *recipTable; /**< Points to the reciprocal initial value table. */ + q15_t energy; /**< saves previous frame energy. */ + q15_t x0; /**< saves previous input sample. */ +} arm_lms_norm_instance_q15; - - /** +/** * @brief Processing function for Q15 normalized LMS filter. * @param[in] S points to an instance of the Q15 normalized LMS filter structure. * @param[in] pSrc points to the block of input data. @@ -1833,16 +1431,10 @@ void arm_biquad_cascade_df2T_compute_coefs_f32( * @param[out] pErr points to the block of error data. * @param[in] blockSize number of samples to process. */ - void arm_lms_norm_q15( - arm_lms_norm_instance_q15 * S, - const q15_t * pSrc, - q15_t * pRef, - q15_t * pOut, - q15_t * pErr, - uint32_t blockSize); +void arm_lms_norm_q15(arm_lms_norm_instance_q15 *S, const q15_t *pSrc, q15_t *pRef, q15_t *pOut, + q15_t *pErr, uint32_t blockSize); - - /** +/** * @brief Initialization function for Q15 normalized LMS filter. * @param[in] S points to an instance of the Q15 normalized LMS filter structure. * @param[in] numTaps number of filter coefficients. @@ -1852,17 +1444,10 @@ void arm_biquad_cascade_df2T_compute_coefs_f32( * @param[in] blockSize number of samples to process. * @param[in] postShift bit shift applied to coefficients. */ - void arm_lms_norm_init_q15( - arm_lms_norm_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - q15_t mu, - uint32_t blockSize, - uint8_t postShift); +void arm_lms_norm_init_q15(arm_lms_norm_instance_q15 *S, uint16_t numTaps, q15_t *pCoeffs, + q15_t *pState, q15_t mu, uint32_t blockSize, uint8_t postShift); - - /** +/** * @brief Correlation of floating-point sequences. * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. @@ -1870,15 +1455,10 @@ void arm_biquad_cascade_df2T_compute_coefs_f32( * @param[in] srcBLen length of the second input sequence. * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. */ - void arm_correlate_f32( - const float32_t * pSrcA, - uint32_t srcALen, - const float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst); +void arm_correlate_f32(const float32_t *pSrcA, uint32_t srcALen, const float32_t *pSrcB, + uint32_t srcBLen, float32_t *pDst); - - /** +/** * @brief Correlation of floating-point sequences. * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. @@ -1886,13 +1466,8 @@ void arm_biquad_cascade_df2T_compute_coefs_f32( * @param[in] srcBLen length of the second input sequence. * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. */ - void arm_correlate_f64( - const float64_t * pSrcA, - uint32_t srcALen, - const float64_t * pSrcB, - uint32_t srcBLen, - float64_t * pDst); - +void arm_correlate_f64(const float64_t *pSrcA, uint32_t srcALen, const float64_t *pSrcB, + uint32_t srcBLen, float64_t *pDst); /** @brief Correlation of Q15 sequences @@ -1903,14 +1478,8 @@ void arm_biquad_cascade_df2T_compute_coefs_f32( @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. */ -void arm_correlate_opt_q15( - const q15_t * pSrcA, - uint32_t srcALen, - const q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch); - +void arm_correlate_opt_q15(const q15_t *pSrcA, uint32_t srcALen, const q15_t *pSrcB, + uint32_t srcBLen, q15_t *pDst, q15_t *pScratch); /** @brief Correlation of Q15 sequences. @@ -1920,13 +1489,8 @@ void arm_correlate_opt_q15( @param[in] srcBLen length of the second input sequence @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. */ - void arm_correlate_q15( - const q15_t * pSrcA, - uint32_t srcALen, - const q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - +void arm_correlate_q15(const q15_t *pSrcA, uint32_t srcALen, const q15_t *pSrcB, uint32_t srcBLen, + q15_t *pDst); /** @brief Correlation of Q15 sequences (fast version). @@ -1936,13 +1500,8 @@ void arm_correlate_opt_q15( @param[in] srcBLen length of the second input sequence @param[out] pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1. */ -void arm_correlate_fast_q15( - const q15_t * pSrcA, - uint32_t srcALen, - const q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - +void arm_correlate_fast_q15(const q15_t *pSrcA, uint32_t srcALen, const q15_t *pSrcB, + uint32_t srcBLen, q15_t *pDst); /** @brief Correlation of Q15 sequences (fast version). @@ -1953,16 +1512,10 @@ void arm_correlate_fast_q15( @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. */ -void arm_correlate_fast_opt_q15( - const q15_t * pSrcA, - uint32_t srcALen, - const q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch); - +void arm_correlate_fast_opt_q15(const q15_t *pSrcA, uint32_t srcALen, const q15_t *pSrcB, + uint32_t srcBLen, q15_t *pDst, q15_t *pScratch); - /** +/** * @brief Correlation of Q31 sequences. * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. @@ -1970,13 +1523,8 @@ void arm_correlate_fast_opt_q15( * @param[in] srcBLen length of the second input sequence. * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. */ - void arm_correlate_q31( - const q31_t * pSrcA, - uint32_t srcALen, - const q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - +void arm_correlate_q31(const q31_t *pSrcA, uint32_t srcALen, const q31_t *pSrcB, uint32_t srcBLen, + q31_t *pDst); /** @brief Correlation of Q31 sequences (fast version). @@ -1986,15 +1534,10 @@ void arm_correlate_fast_opt_q15( @param[in] srcBLen length of the second input sequence @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. */ -void arm_correlate_fast_q31( - const q31_t * pSrcA, - uint32_t srcALen, - const q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); +void arm_correlate_fast_q31(const q31_t *pSrcA, uint32_t srcALen, const q31_t *pSrcB, + uint32_t srcBLen, q31_t *pDst); - - /** +/** * @brief Correlation of Q7 sequences. * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. @@ -2004,17 +1547,10 @@ void arm_correlate_fast_q31( * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). */ - void arm_correlate_opt_q7( - const q7_t * pSrcA, - uint32_t srcALen, - const q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); +void arm_correlate_opt_q7(const q7_t *pSrcA, uint32_t srcALen, const q7_t *pSrcB, uint32_t srcBLen, + q7_t *pDst, q15_t *pScratch1, q15_t *pScratch2); - - /** +/** * @brief Correlation of Q7 sequences. * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. @@ -2022,68 +1558,61 @@ void arm_correlate_fast_q31( * @param[in] srcBLen length of the second input sequence. * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. */ - void arm_correlate_q7( - const q7_t * pSrcA, - uint32_t srcALen, - const q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst); +void arm_correlate_q7(const q7_t *pSrcA, uint32_t srcALen, const q7_t *pSrcB, uint32_t srcBLen, + q7_t *pDst); - - /** +/** * @brief Instance structure for the floating-point sparse FIR filter. */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_f32; - - /** +typedef struct { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + float32_t * + pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ +} arm_fir_sparse_instance_f32; + +/** * @brief Instance structure for the Q31 sparse FIR filter. */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q31; - - /** +typedef struct { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q31_t * + pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ +} arm_fir_sparse_instance_q31; + +/** * @brief Instance structure for the Q15 sparse FIR filter. */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q15; - - /** +typedef struct { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q15_t * + pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ +} arm_fir_sparse_instance_q15; + +/** * @brief Instance structure for the Q7 sparse FIR filter. */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - const q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q7; +typedef struct { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + const q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ +} arm_fir_sparse_instance_q7; - - /** +/** * @brief Processing function for the floating-point sparse FIR filter. * @param[in] S points to an instance of the floating-point sparse FIR structure. * @param[in] pSrc points to the block of input data. @@ -2091,15 +1620,10 @@ void arm_correlate_fast_q31( * @param[in] pScratchIn points to a temporary buffer of size blockSize. * @param[in] blockSize number of input samples to process per call. */ - void arm_fir_sparse_f32( - arm_fir_sparse_instance_f32 * S, - const float32_t * pSrc, - float32_t * pDst, - float32_t * pScratchIn, - uint32_t blockSize); +void arm_fir_sparse_f32(arm_fir_sparse_instance_f32 *S, const float32_t *pSrc, float32_t *pDst, + float32_t *pScratchIn, uint32_t blockSize); - - /** +/** * @brief Initialization function for the floating-point sparse FIR filter. * @param[in,out] S points to an instance of the floating-point sparse FIR structure. * @param[in] numTaps number of nonzero coefficients in the filter. @@ -2109,17 +1633,11 @@ void arm_correlate_fast_q31( * @param[in] maxDelay maximum offset time supported. * @param[in] blockSize number of samples that will be processed per block. */ - void arm_fir_sparse_init_f32( - arm_fir_sparse_instance_f32 * S, - uint16_t numTaps, - const float32_t * pCoeffs, - float32_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); +void arm_fir_sparse_init_f32(arm_fir_sparse_instance_f32 *S, uint16_t numTaps, + const float32_t *pCoeffs, float32_t *pState, int32_t *pTapDelay, + uint16_t maxDelay, uint32_t blockSize); - - /** +/** * @brief Processing function for the Q31 sparse FIR filter. * @param[in] S points to an instance of the Q31 sparse FIR structure. * @param[in] pSrc points to the block of input data. @@ -2127,15 +1645,10 @@ void arm_correlate_fast_q31( * @param[in] pScratchIn points to a temporary buffer of size blockSize. * @param[in] blockSize number of input samples to process per call. */ - void arm_fir_sparse_q31( - arm_fir_sparse_instance_q31 * S, - const q31_t * pSrc, - q31_t * pDst, - q31_t * pScratchIn, - uint32_t blockSize); +void arm_fir_sparse_q31(arm_fir_sparse_instance_q31 *S, const q31_t *pSrc, q31_t *pDst, + q31_t *pScratchIn, uint32_t blockSize); - - /** +/** * @brief Initialization function for the Q31 sparse FIR filter. * @param[in,out] S points to an instance of the Q31 sparse FIR structure. * @param[in] numTaps number of nonzero coefficients in the filter. @@ -2145,17 +1658,11 @@ void arm_correlate_fast_q31( * @param[in] maxDelay maximum offset time supported. * @param[in] blockSize number of samples that will be processed per block. */ - void arm_fir_sparse_init_q31( - arm_fir_sparse_instance_q31 * S, - uint16_t numTaps, - const q31_t * pCoeffs, - q31_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); +void arm_fir_sparse_init_q31(arm_fir_sparse_instance_q31 *S, uint16_t numTaps, const q31_t *pCoeffs, + q31_t *pState, int32_t *pTapDelay, uint16_t maxDelay, + uint32_t blockSize); - - /** +/** * @brief Processing function for the Q15 sparse FIR filter. * @param[in] S points to an instance of the Q15 sparse FIR structure. * @param[in] pSrc points to the block of input data. @@ -2164,16 +1671,10 @@ void arm_correlate_fast_q31( * @param[in] pScratchOut points to a temporary buffer of size blockSize. * @param[in] blockSize number of input samples to process per call. */ - void arm_fir_sparse_q15( - arm_fir_sparse_instance_q15 * S, - const q15_t * pSrc, - q15_t * pDst, - q15_t * pScratchIn, - q31_t * pScratchOut, - uint32_t blockSize); +void arm_fir_sparse_q15(arm_fir_sparse_instance_q15 *S, const q15_t *pSrc, q15_t *pDst, + q15_t *pScratchIn, q31_t *pScratchOut, uint32_t blockSize); - - /** +/** * @brief Initialization function for the Q15 sparse FIR filter. * @param[in,out] S points to an instance of the Q15 sparse FIR structure. * @param[in] numTaps number of nonzero coefficients in the filter. @@ -2183,17 +1684,11 @@ void arm_correlate_fast_q31( * @param[in] maxDelay maximum offset time supported. * @param[in] blockSize number of samples that will be processed per block. */ - void arm_fir_sparse_init_q15( - arm_fir_sparse_instance_q15 * S, - uint16_t numTaps, - const q15_t * pCoeffs, - q15_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); +void arm_fir_sparse_init_q15(arm_fir_sparse_instance_q15 *S, uint16_t numTaps, const q15_t *pCoeffs, + q15_t *pState, int32_t *pTapDelay, uint16_t maxDelay, + uint32_t blockSize); - - /** +/** * @brief Processing function for the Q7 sparse FIR filter. * @param[in] S points to an instance of the Q7 sparse FIR structure. * @param[in] pSrc points to the block of input data. @@ -2202,16 +1697,10 @@ void arm_correlate_fast_q31( * @param[in] pScratchOut points to a temporary buffer of size blockSize. * @param[in] blockSize number of input samples to process per call. */ - void arm_fir_sparse_q7( - arm_fir_sparse_instance_q7 * S, - const q7_t * pSrc, - q7_t * pDst, - q7_t * pScratchIn, - q31_t * pScratchOut, - uint32_t blockSize); +void arm_fir_sparse_q7(arm_fir_sparse_instance_q7 *S, const q7_t *pSrc, q7_t *pDst, + q7_t *pScratchIn, q31_t *pScratchOut, uint32_t blockSize); - - /** +/** * @brief Initialization function for the Q7 sparse FIR filter. * @param[in,out] S points to an instance of the Q7 sparse FIR structure. * @param[in] numTaps number of nonzero coefficients in the filter. @@ -2221,32 +1710,18 @@ void arm_correlate_fast_q31( * @param[in] maxDelay maximum offset time supported. * @param[in] blockSize number of samples that will be processed per block. */ - void arm_fir_sparse_init_q7( - arm_fir_sparse_instance_q7 * S, - uint16_t numTaps, - const q7_t * pCoeffs, - q7_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - +void arm_fir_sparse_init_q7(arm_fir_sparse_instance_q7 *S, uint16_t numTaps, const q7_t *pCoeffs, + q7_t *pState, int32_t *pTapDelay, uint16_t maxDelay, + uint32_t blockSize); - - - - /** +/** * @brief floating-point Circular write function. */ - __STATIC_FORCEINLINE void arm_circularWrite_f32( - int32_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const int32_t * src, - int32_t srcInc, - uint32_t blockSize) - { +__STATIC_FORCEINLINE void arm_circularWrite_f32(int32_t *circBuffer, int32_t L, + uint16_t *writeOffset, int32_t bufferInc, + const int32_t *src, int32_t srcInc, + uint32_t blockSize) +{ uint32_t i = 0U; int32_t wOffset; @@ -2257,46 +1732,37 @@ void arm_correlate_fast_q31( /* Loop over the blockSize */ i = blockSize; - while (i > 0U) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; + while (i > 0U) { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; - /* Update the input pointer */ - src += srcInc; + /* Update the input pointer */ + src += srcInc; - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if (wOffset >= L) - wOffset -= L; + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; - /* Decrement the loop counter */ - i--; + /* Decrement the loop counter */ + i--; } /* Update the index pointer */ *writeOffset = (uint16_t)wOffset; - } - - +} - /** +/** * @brief floating-point Circular Read function. */ - __STATIC_FORCEINLINE void arm_circularRead_f32( - int32_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - int32_t * dst, - int32_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { +__STATIC_FORCEINLINE void arm_circularRead_f32(int32_t *circBuffer, int32_t L, int32_t *readOffset, + int32_t bufferInc, int32_t *dst, int32_t *dst_base, + int32_t dst_length, int32_t dstInc, + uint32_t blockSize) +{ uint32_t i = 0U; int32_t rOffset; - int32_t* dst_end; + int32_t *dst_end; /* Copy the value of Index pointer that points * to the current location from where the input samples to be read */ @@ -2306,48 +1772,39 @@ void arm_correlate_fast_q31( /* Loop over the blockSize */ i = blockSize; - while (i > 0U) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; + while (i > 0U) { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; - /* Update the input pointer */ - dst += dstInc; + /* Update the input pointer */ + dst += dstInc; - if (dst == dst_end) - { - dst = dst_base; - } + if (dst == dst_end) { + dst = dst_base; + } - /* Circularly update rOffset. Watch out for positive and negative value */ - rOffset += bufferInc; + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; - if (rOffset >= L) - { - rOffset -= L; - } + if (rOffset >= L) { + rOffset -= L; + } - /* Decrement the loop counter */ - i--; + /* Decrement the loop counter */ + i--; } /* Update the index pointer */ *readOffset = rOffset; - } - +} - /** +/** * @brief Q15 Circular write function. */ - __STATIC_FORCEINLINE void arm_circularWrite_q15( - q15_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const q15_t * src, - int32_t srcInc, - uint32_t blockSize) - { +__STATIC_FORCEINLINE void arm_circularWrite_q15(q15_t *circBuffer, int32_t L, uint16_t *writeOffset, + int32_t bufferInc, const q15_t *src, int32_t srcInc, + uint32_t blockSize) +{ uint32_t i = 0U; int32_t wOffset; @@ -2358,45 +1815,37 @@ void arm_correlate_fast_q31( /* Loop over the blockSize */ i = blockSize; - while (i > 0U) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; + while (i > 0U) { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; - /* Update the input pointer */ - src += srcInc; + /* Update the input pointer */ + src += srcInc; - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if (wOffset >= L) - wOffset -= L; + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; - /* Decrement the loop counter */ - i--; + /* Decrement the loop counter */ + i--; } /* Update the index pointer */ *writeOffset = (uint16_t)wOffset; - } - +} - /** +/** * @brief Q15 Circular Read function. */ - __STATIC_FORCEINLINE void arm_circularRead_q15( - q15_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - q15_t * dst, - q15_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { +__STATIC_FORCEINLINE void arm_circularRead_q15(q15_t *circBuffer, int32_t L, int32_t *readOffset, + int32_t bufferInc, q15_t *dst, q15_t *dst_base, + int32_t dst_length, int32_t dstInc, + uint32_t blockSize) +{ uint32_t i = 0; int32_t rOffset; - q15_t* dst_end; + q15_t *dst_end; /* Copy the value of Index pointer that points * to the current location from where the input samples to be read */ @@ -2407,48 +1856,39 @@ void arm_correlate_fast_q31( /* Loop over the blockSize */ i = blockSize; - while (i > 0U) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; + while (i > 0U) { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; - /* Update the input pointer */ - dst += dstInc; + /* Update the input pointer */ + dst += dstInc; - if (dst == dst_end) - { - dst = dst_base; - } + if (dst == dst_end) { + dst = dst_base; + } - /* Circularly update wOffset. Watch out for positive and negative value */ - rOffset += bufferInc; + /* Circularly update wOffset. Watch out for positive and negative value */ + rOffset += bufferInc; - if (rOffset >= L) - { - rOffset -= L; - } + if (rOffset >= L) { + rOffset -= L; + } - /* Decrement the loop counter */ - i--; + /* Decrement the loop counter */ + i--; } /* Update the index pointer */ *readOffset = rOffset; - } - +} - /** +/** * @brief Q7 Circular write function. */ - __STATIC_FORCEINLINE void arm_circularWrite_q7( - q7_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const q7_t * src, - int32_t srcInc, - uint32_t blockSize) - { +__STATIC_FORCEINLINE void arm_circularWrite_q7(q7_t *circBuffer, int32_t L, uint16_t *writeOffset, + int32_t bufferInc, const q7_t *src, int32_t srcInc, + uint32_t blockSize) +{ uint32_t i = 0U; int32_t wOffset; @@ -2459,45 +1899,37 @@ void arm_correlate_fast_q31( /* Loop over the blockSize */ i = blockSize; - while (i > 0U) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; + while (i > 0U) { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; - /* Update the input pointer */ - src += srcInc; + /* Update the input pointer */ + src += srcInc; - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if (wOffset >= L) - wOffset -= L; + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; - /* Decrement the loop counter */ - i--; + /* Decrement the loop counter */ + i--; } /* Update the index pointer */ *writeOffset = (uint16_t)wOffset; - } - +} - /** +/** * @brief Q7 Circular Read function. */ - __STATIC_FORCEINLINE void arm_circularRead_q7( - q7_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - q7_t * dst, - q7_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { +__STATIC_FORCEINLINE void arm_circularRead_q7(q7_t *circBuffer, int32_t L, int32_t *readOffset, + int32_t bufferInc, q7_t *dst, q7_t *dst_base, + int32_t dst_length, int32_t dstInc, + uint32_t blockSize) +{ uint32_t i = 0; int32_t rOffset; - q7_t* dst_end; + q7_t *dst_end; /* Copy the value of Index pointer that points * to the current location from where the input samples to be read */ @@ -2508,35 +1940,31 @@ void arm_correlate_fast_q31( /* Loop over the blockSize */ i = blockSize; - while (i > 0U) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; + while (i > 0U) { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; - /* Update the input pointer */ - dst += dstInc; + /* Update the input pointer */ + dst += dstInc; - if (dst == dst_end) - { - dst = dst_base; - } + if (dst == dst_end) { + dst = dst_base; + } - /* Circularly update rOffset. Watch out for positive and negative value */ - rOffset += bufferInc; + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; - if (rOffset >= L) - { - rOffset -= L; - } + if (rOffset >= L) { + rOffset -= L; + } - /* Decrement the loop counter */ - i--; + /* Decrement the loop counter */ + i--; } /* Update the index pointer */ *readOffset = rOffset; - } - +} /** @brief Levinson Durbin @@ -2545,11 +1973,7 @@ void arm_correlate_fast_q31( @param[out] err prediction error (variance) @param[in] nbCoefs number of autoregressive coefficients */ -void arm_levinson_durbin_f32(const float32_t *phi, - float32_t *a, - float32_t *err, - int nbCoefs); - +void arm_levinson_durbin_f32(const float32_t *phi, float32_t *a, float32_t *err, int nbCoefs); /** @brief Levinson Durbin @@ -2558,12 +1982,9 @@ void arm_levinson_durbin_f32(const float32_t *phi, @param[out] err prediction error (variance) @param[in] nbCoefs number of autoregressive coefficients */ -void arm_levinson_durbin_q31(const q31_t *phi, - q31_t *a, - q31_t *err, - int nbCoefs); +void arm_levinson_durbin_q31(const q31_t *phi, q31_t *a, q31_t *err, int nbCoefs); -#ifdef __cplusplus +#ifdef __cplusplus } #endif diff --git a/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/filtering_functions_f16.h b/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/filtering_functions_f16.h old mode 100755 new mode 100644 index 655cd7e0f56..47fd207086b --- a/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/filtering_functions_f16.h +++ b/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/filtering_functions_f16.h @@ -23,7 +23,6 @@ * limitations under the License. */ - #ifndef FILTERING_FUNCTIONS_F16_H_ #define FILTERING_FUNCTIONS_F16_H_ @@ -33,25 +32,23 @@ #include "dsp/none.h" #include "dsp/utils.h" - -#ifdef __cplusplus -extern "C" -{ +#ifdef __cplusplus +extern "C" { #endif #if defined(ARM_FLOAT16_SUPPORTED) - /** +/** * @brief Instance structure for the floating-point FIR filter. */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - float16_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - const float16_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - } arm_fir_instance_f16; - - /** +typedef struct { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + float16_t * + pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + const float16_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ +} arm_fir_instance_f16; + +/** * @brief Initialization function for the floating-point FIR filter. * @param[in,out] S points to an instance of the floating-point FIR filter structure. * @param[in] numTaps Number of filter coefficients in the filter. @@ -59,148 +56,127 @@ extern "C" * @param[in] pState points to the state buffer. * @param[in] blockSize number of samples that are processed at a time. */ - void arm_fir_init_f16( - arm_fir_instance_f16 * S, - uint16_t numTaps, - const float16_t * pCoeffs, - float16_t * pState, - uint32_t blockSize); - - /** +void arm_fir_init_f16(arm_fir_instance_f16 *S, uint16_t numTaps, const float16_t *pCoeffs, + float16_t *pState, uint32_t blockSize); + +/** * @brief Processing function for the floating-point FIR filter. * @param[in] S points to an instance of the floating-point FIR structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data. * @param[in] blockSize number of samples to process. */ - void arm_fir_f16( - const arm_fir_instance_f16 * S, - const float16_t * pSrc, - float16_t * pDst, - uint32_t blockSize); +void arm_fir_f16(const arm_fir_instance_f16 *S, const float16_t *pSrc, float16_t *pDst, + uint32_t blockSize); - - /** +/** * @brief Instance structure for the floating-point Biquad cascade filter. */ - typedef struct - { - uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float16_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - const float16_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - } arm_biquad_casd_df1_inst_f16; +typedef struct { + uint32_t + numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float16_t * + pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + const float16_t + *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ +} arm_biquad_casd_df1_inst_f16; #if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) - /** +/** * @brief Instance structure for the modified Biquad coefs required by vectorized code. */ - typedef struct - { - float16_t coeffs[12][8]; /**< Points to the array of modified coefficients. The array is of length 32. There is one per stage */ - } arm_biquad_mod_coef_f16; -#endif +typedef struct { + float16_t coeffs + [12] + [8]; /**< Points to the array of modified coefficients. The array is of length 32. There is one per stage */ +} arm_biquad_mod_coef_f16; +#endif - /** +/** * @brief Processing function for the floating-point Biquad cascade filter. * @param[in] S points to an instance of the floating-point Biquad cascade structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data. * @param[in] blockSize number of samples to process. */ - void arm_biquad_cascade_df1_f16( - const arm_biquad_casd_df1_inst_f16 * S, - const float16_t * pSrc, - float16_t * pDst, - uint32_t blockSize); +void arm_biquad_cascade_df1_f16(const arm_biquad_casd_df1_inst_f16 *S, const float16_t *pSrc, + float16_t *pDst, uint32_t blockSize); #if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) - void arm_biquad_cascade_df1_mve_init_f16( - arm_biquad_casd_df1_inst_f16 * S, - uint8_t numStages, - const float16_t * pCoeffs, - arm_biquad_mod_coef_f16 * pCoeffsMod, - float16_t * pState); +void arm_biquad_cascade_df1_mve_init_f16(arm_biquad_casd_df1_inst_f16 *S, uint8_t numStages, + const float16_t *pCoeffs, + arm_biquad_mod_coef_f16 *pCoeffsMod, float16_t *pState); #endif - void arm_biquad_cascade_df1_init_f16( - arm_biquad_casd_df1_inst_f16 * S, - uint8_t numStages, - const float16_t * pCoeffs, - float16_t * pState); +void arm_biquad_cascade_df1_init_f16(arm_biquad_casd_df1_inst_f16 *S, uint8_t numStages, + const float16_t *pCoeffs, float16_t *pState); - /** +/** * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. */ - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float16_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ - const float16_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - } arm_biquad_cascade_df2T_instance_f16; - - /** +typedef struct { + uint8_t + numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float16_t * + pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + const float16_t + *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ +} arm_biquad_cascade_df2T_instance_f16; + +/** * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. */ - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float16_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ - const float16_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - } arm_biquad_cascade_stereo_df2T_instance_f16; - - /** +typedef struct { + uint8_t + numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float16_t * + pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + const float16_t + *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ +} arm_biquad_cascade_stereo_df2T_instance_f16; + +/** * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. * @param[in] S points to an instance of the filter data structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data * @param[in] blockSize number of samples to process. */ - void arm_biquad_cascade_df2T_f16( - const arm_biquad_cascade_df2T_instance_f16 * S, - const float16_t * pSrc, - float16_t * pDst, - uint32_t blockSize); +void arm_biquad_cascade_df2T_f16(const arm_biquad_cascade_df2T_instance_f16 *S, + const float16_t *pSrc, float16_t *pDst, uint32_t blockSize); - /** +/** * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels * @param[in] S points to an instance of the filter data structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data * @param[in] blockSize number of samples to process. */ - void arm_biquad_cascade_stereo_df2T_f16( - const arm_biquad_cascade_stereo_df2T_instance_f16 * S, - const float16_t * pSrc, - float16_t * pDst, - uint32_t blockSize); +void arm_biquad_cascade_stereo_df2T_f16(const arm_biquad_cascade_stereo_df2T_instance_f16 *S, + const float16_t *pSrc, float16_t *pDst, uint32_t blockSize); - /** +/** * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. * @param[in,out] S points to an instance of the filter data structure. * @param[in] numStages number of 2nd order stages in the filter. * @param[in] pCoeffs points to the filter coefficients. * @param[in] pState points to the state buffer. */ - void arm_biquad_cascade_df2T_init_f16( - arm_biquad_cascade_df2T_instance_f16 * S, - uint8_t numStages, - const float16_t * pCoeffs, - float16_t * pState); +void arm_biquad_cascade_df2T_init_f16(arm_biquad_cascade_df2T_instance_f16 *S, uint8_t numStages, + const float16_t *pCoeffs, float16_t *pState); - /** +/** * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. * @param[in,out] S points to an instance of the filter data structure. * @param[in] numStages number of 2nd order stages in the filter. * @param[in] pCoeffs points to the filter coefficients. * @param[in] pState points to the state buffer. */ - void arm_biquad_cascade_stereo_df2T_init_f16( - arm_biquad_cascade_stereo_df2T_instance_f16 * S, - uint8_t numStages, - const float16_t * pCoeffs, - float16_t * pState); +void arm_biquad_cascade_stereo_df2T_init_f16(arm_biquad_cascade_stereo_df2T_instance_f16 *S, + uint8_t numStages, const float16_t *pCoeffs, + float16_t *pState); - /** +/** * @brief Correlation of floating-point sequences. * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. @@ -208,13 +184,8 @@ extern "C" * @param[in] srcBLen length of the second input sequence. * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. */ - void arm_correlate_f16( - const float16_t * pSrcA, - uint32_t srcALen, - const float16_t * pSrcB, - uint32_t srcBLen, - float16_t * pDst); - +void arm_correlate_f16(const float16_t *pSrcA, uint32_t srcALen, const float16_t *pSrcB, + uint32_t srcBLen, float16_t *pDst); /** @brief Levinson Durbin @@ -223,13 +194,10 @@ extern "C" @param[out] err prediction error (variance) @param[in] nbCoefs number of autoregressive coefficients */ -void arm_levinson_durbin_f16(const float16_t *phi, - float16_t *a, - float16_t *err, - int nbCoefs); +void arm_levinson_durbin_f16(const float16_t *phi, float16_t *a, float16_t *err, int nbCoefs); #endif /*defined(ARM_FLOAT16_SUPPORTED)*/ -#ifdef __cplusplus +#ifdef __cplusplus } #endif diff --git a/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/interpolation_functions.h b/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/interpolation_functions.h old mode 100755 new mode 100644 index 574b73738f5..24110f4d038 --- a/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/interpolation_functions.h +++ b/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/interpolation_functions.h @@ -23,7 +23,6 @@ * limitations under the License. */ - #ifndef INTERPOLATION_FUNCTIONS_H_ #define INTERPOLATION_FUNCTIONS_H_ @@ -33,12 +32,10 @@ #include "dsp/none.h" #include "dsp/utils.h" -#ifdef __cplusplus -extern "C" -{ +#ifdef __cplusplus +extern "C" { #endif - /** * @defgroup groupInterpolation Interpolation Functions * These functions perform 1- and 2-dimensional interpolation of data. @@ -46,95 +43,82 @@ extern "C" * bilinear interpolation is used for 2-dimensional data. */ - - /** +/** * @brief Instance structure for the floating-point Linear Interpolate function. */ - typedef struct - { - uint32_t nValues; /**< nValues */ - float32_t x1; /**< x1 */ - float32_t xSpacing; /**< xSpacing */ - const float32_t *pYData; /**< pointer to the table of Y values */ - } arm_linear_interp_instance_f32; +typedef struct { + uint32_t nValues; /**< nValues */ + float32_t x1; /**< x1 */ + float32_t xSpacing; /**< xSpacing */ + const float32_t *pYData; /**< pointer to the table of Y values */ +} arm_linear_interp_instance_f32; - /** +/** * @brief Instance structure for the floating-point bilinear interpolation function. */ - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - const float32_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_f32; +typedef struct { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + const float32_t *pData; /**< points to the data table. */ +} arm_bilinear_interp_instance_f32; - /** +/** * @brief Instance structure for the Q31 bilinear interpolation function. */ - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - const q31_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q31; +typedef struct { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + const q31_t *pData; /**< points to the data table. */ +} arm_bilinear_interp_instance_q31; - /** +/** * @brief Instance structure for the Q15 bilinear interpolation function. */ - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - const q15_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q15; +typedef struct { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + const q15_t *pData; /**< points to the data table. */ +} arm_bilinear_interp_instance_q15; - /** +/** * @brief Instance structure for the Q15 bilinear interpolation function. */ - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - const q7_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q7; - +typedef struct { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + const q7_t *pData; /**< points to the data table. */ +} arm_bilinear_interp_instance_q7; - /** +/** * @brief Struct for specifying cubic spline type */ - typedef enum - { - ARM_SPLINE_NATURAL = 0, /**< Natural spline */ - ARM_SPLINE_PARABOLIC_RUNOUT = 1 /**< Parabolic runout spline */ - } arm_spline_type; +typedef enum { + ARM_SPLINE_NATURAL = 0, /**< Natural spline */ + ARM_SPLINE_PARABOLIC_RUNOUT = 1 /**< Parabolic runout spline */ +} arm_spline_type; - /** +/** * @brief Instance structure for the floating-point cubic spline interpolation. */ - typedef struct - { - arm_spline_type type; /**< Type (boundary conditions) */ - const float32_t * x; /**< x values */ - const float32_t * y; /**< y values */ - uint32_t n_x; /**< Number of known data points */ - float32_t * coeffs; /**< Coefficients buffer (b,c, and d) */ - } arm_spline_instance_f32; - +typedef struct { + arm_spline_type type; /**< Type (boundary conditions) */ + const float32_t *x; /**< x values */ + const float32_t *y; /**< y values */ + uint32_t n_x; /**< Number of known data points */ + float32_t *coeffs; /**< Coefficients buffer (b,c, and d) */ +} arm_spline_instance_f32; - /** +/** * @brief Processing function for the floating-point cubic spline interpolation. * @param[in] S points to an instance of the floating-point spline structure. * @param[in] xq points to the x values ot the interpolated data points. * @param[out] pDst points to the block of output data. * @param[in] blockSize number of samples of output data. */ - void arm_spline_f32( - arm_spline_instance_f32 * S, - const float32_t * xq, - float32_t * pDst, - uint32_t blockSize); +void arm_spline_f32(arm_spline_instance_f32 *S, const float32_t *xq, float32_t *pDst, + uint32_t blockSize); - /** +/** * @brief Initialization function for the floating-point cubic spline interpolation. * @param[in,out] S points to an instance of the floating-point spline structure. * @param[in] type type of cubic spline interpolation (boundary conditions) @@ -144,28 +128,19 @@ extern "C" * @param[in] coeffs coefficients array for b, c, and d * @param[in] tempBuffer buffer array for internal computations */ - void arm_spline_init_f32( - arm_spline_instance_f32 * S, - arm_spline_type type, - const float32_t * x, - const float32_t * y, - uint32_t n, - float32_t * coeffs, - float32_t * tempBuffer); - +void arm_spline_init_f32(arm_spline_instance_f32 *S, arm_spline_type type, const float32_t *x, + const float32_t *y, uint32_t n, float32_t *coeffs, float32_t *tempBuffer); - /** +/** * @brief Process function for the floating-point Linear Interpolation Function. * @param[in,out] S is an instance of the floating-point Linear Interpolation structure * @param[in] x input sample to process * @return y processed output sample. * */ - float32_t arm_linear_interp_f32( - const arm_linear_interp_instance_f32 * S, - float32_t x); +float32_t arm_linear_interp_f32(const arm_linear_interp_instance_f32 *S, float32_t x); - /** +/** * * @brief Process function for the Q31 Linear Interpolation Function. * @param[in] pYData pointer to Q31 Linear Interpolation table @@ -178,12 +153,9 @@ extern "C" * This function can support maximum of table size 2^12. * */ - q31_t arm_linear_interp_q31( - const q31_t * pYData, - q31_t x, - uint32_t nValues); +q31_t arm_linear_interp_q31(const q31_t *pYData, q31_t x, uint32_t nValues); - /** +/** * * @brief Process function for the Q15 Linear Interpolation Function. * @param[in] pYData pointer to Q15 Linear Interpolation table @@ -196,12 +168,9 @@ extern "C" * This function can support maximum of table size 2^12. * */ - q15_t arm_linear_interp_q15( - const q15_t * pYData, - q31_t x, - uint32_t nValues); +q15_t arm_linear_interp_q15(const q15_t *pYData, q31_t x, uint32_t nValues); - /** +/** * * @brief Process function for the Q7 Linear Interpolation Function. * @param[in] pYData pointer to Q7 Linear Interpolation table @@ -213,62 +182,46 @@ extern "C" * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. * This function can support maximum of table size 2^12. */ -q7_t arm_linear_interp_q7( - const q7_t * pYData, - q31_t x, - uint32_t nValues); +q7_t arm_linear_interp_q7(const q7_t *pYData, q31_t x, uint32_t nValues); - /** +/** * @brief Floating-point bilinear interpolation. * @param[in,out] S points to an instance of the interpolation structure. * @param[in] X interpolation coordinate. * @param[in] Y interpolation coordinate. * @return out interpolated value. */ - float32_t arm_bilinear_interp_f32( - const arm_bilinear_interp_instance_f32 * S, - float32_t X, - float32_t Y); +float32_t arm_bilinear_interp_f32(const arm_bilinear_interp_instance_f32 *S, float32_t X, + float32_t Y); - /** +/** * @brief Q31 bilinear interpolation. * @param[in,out] S points to an instance of the interpolation structure. * @param[in] X interpolation coordinate in 12.20 format. * @param[in] Y interpolation coordinate in 12.20 format. * @return out interpolated value. */ - q31_t arm_bilinear_interp_q31( - arm_bilinear_interp_instance_q31 * S, - q31_t X, - q31_t Y); - +q31_t arm_bilinear_interp_q31(arm_bilinear_interp_instance_q31 *S, q31_t X, q31_t Y); - /** +/** * @brief Q15 bilinear interpolation. * @param[in,out] S points to an instance of the interpolation structure. * @param[in] X interpolation coordinate in 12.20 format. * @param[in] Y interpolation coordinate in 12.20 format. * @return out interpolated value. */ - q15_t arm_bilinear_interp_q15( - arm_bilinear_interp_instance_q15 * S, - q31_t X, - q31_t Y); +q15_t arm_bilinear_interp_q15(arm_bilinear_interp_instance_q15 *S, q31_t X, q31_t Y); - /** +/** * @brief Q7 bilinear interpolation. * @param[in,out] S points to an instance of the interpolation structure. * @param[in] X interpolation coordinate in 12.20 format. * @param[in] Y interpolation coordinate in 12.20 format. * @return out interpolated value. */ - q7_t arm_bilinear_interp_q7( - arm_bilinear_interp_instance_q7 * S, - q31_t X, - q31_t Y); - +q7_t arm_bilinear_interp_q7(arm_bilinear_interp_instance_q7 *S, q31_t X, q31_t Y); -#ifdef __cplusplus +#ifdef __cplusplus } #endif diff --git a/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/interpolation_functions_f16.h b/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/interpolation_functions_f16.h old mode 100755 new mode 100644 index e1f27c3cdaf..8451ab7300a --- a/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/interpolation_functions_f16.h +++ b/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/interpolation_functions_f16.h @@ -23,7 +23,6 @@ * limitations under the License. */ - #ifndef INTERPOLATION_FUNCTIONS_F16_H_ #define INTERPOLATION_FUNCTIONS_F16_H_ @@ -33,9 +32,8 @@ #include "dsp/none.h" #include "dsp/utils.h" -#ifdef __cplusplus -extern "C" -{ +#ifdef __cplusplus +extern "C" { #endif #if defined(ARM_FLOAT16_SUPPORTED) @@ -43,40 +41,36 @@ extern "C" /** * @brief Instance structure for the half floating-point Linear Interpolate function. */ -typedef struct -{ - uint32_t nValues; /**< nValues */ - float16_t x1; /**< x1 */ - float16_t xSpacing; /**< xSpacing */ - const float16_t *pYData; /**< pointer to the table of Y values */ +typedef struct { + uint32_t nValues; /**< nValues */ + float16_t x1; /**< x1 */ + float16_t xSpacing; /**< xSpacing */ + const float16_t *pYData; /**< pointer to the table of Y values */ } arm_linear_interp_instance_f16; /** * @brief Instance structure for the floating-point bilinear interpolation function. */ -typedef struct -{ - uint16_t numRows;/**< number of rows in the data table. */ - uint16_t numCols;/**< number of columns in the data table. */ +typedef struct { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ const float16_t *pData; /**< points to the data table. */ } arm_bilinear_interp_instance_f16; - /** +/** * @addtogroup LinearInterpolate * @{ */ - /** +/** * @brief Process function for the floating-point Linear Interpolation Function. * @param[in,out] S is an instance of the floating-point Linear Interpolation structure * @param[in] x input sample to process * @return y processed output sample. */ - float16_t arm_linear_interp_f16( - const arm_linear_interp_instance_f16 * S, - float16_t x); +float16_t arm_linear_interp_f16(const arm_linear_interp_instance_f16 *S, float16_t x); - /** +/** * @} end of LinearInterpolate group */ @@ -85,24 +79,21 @@ typedef struct * @{ */ - /** +/** * @brief Floating-point bilinear interpolation. * @param[in,out] S points to an instance of the interpolation structure. * @param[in] X interpolation coordinate. * @param[in] Y interpolation coordinate. * @return out interpolated value. */ - float16_t arm_bilinear_interp_f16( - const arm_bilinear_interp_instance_f16 * S, - float16_t X, - float16_t Y); - +float16_t arm_bilinear_interp_f16(const arm_bilinear_interp_instance_f16 *S, float16_t X, + float16_t Y); - /** +/** * @} end of BilinearInterpolate group */ #endif /*defined(ARM_FLOAT16_SUPPORTED)*/ -#ifdef __cplusplus +#ifdef __cplusplus } #endif diff --git a/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/matrix_functions.h b/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/matrix_functions.h old mode 100755 new mode 100644 index 175ca2fac22..7b8b99e24af --- a/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/matrix_functions.h +++ b/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/matrix_functions.h @@ -23,7 +23,6 @@ * limitations under the License. */ - #ifndef MATRIX_FUNCTIONS_H_ #define MATRIX_FUNCTIONS_H_ @@ -33,9 +32,8 @@ #include "dsp/none.h" #include "dsp/utils.h" -#ifdef __cplusplus -extern "C" -{ +#ifdef __cplusplus +extern "C" { #endif /** @@ -109,60 +107,55 @@ extern "C" * return ARM_MATH_SUCCESS. */ - #define DEFAULT_HOUSEHOLDER_THRESHOLD_F64 (1.0e-16) - #define DEFAULT_HOUSEHOLDER_THRESHOLD_F32 (1.0e-12f) +#define DEFAULT_HOUSEHOLDER_THRESHOLD_F64 (1.0e-16) +#define DEFAULT_HOUSEHOLDER_THRESHOLD_F32 (1.0e-12f) - /** +/** * @brief Instance structure for the floating-point matrix structure. */ - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - float32_t *pData; /**< points to the data of the matrix. */ - } arm_matrix_instance_f32; - - /** +typedef struct { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float32_t *pData; /**< points to the data of the matrix. */ +} arm_matrix_instance_f32; + +/** * @brief Instance structure for the floating-point matrix structure. */ - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - float64_t *pData; /**< points to the data of the matrix. */ - } arm_matrix_instance_f64; +typedef struct { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float64_t *pData; /**< points to the data of the matrix. */ +} arm_matrix_instance_f64; - /** +/** * @brief Instance structure for the Q7 matrix structure. */ - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - q7_t *pData; /**< points to the data of the matrix. */ - } arm_matrix_instance_q7; +typedef struct { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q7_t *pData; /**< points to the data of the matrix. */ +} arm_matrix_instance_q7; - /** +/** * @brief Instance structure for the Q15 matrix structure. */ - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - q15_t *pData; /**< points to the data of the matrix. */ - } arm_matrix_instance_q15; +typedef struct { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q15_t *pData; /**< points to the data of the matrix. */ +} arm_matrix_instance_q15; - /** +/** * @brief Instance structure for the Q31 matrix structure. */ - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - q31_t *pData; /**< points to the data of the matrix. */ - } arm_matrix_instance_q31; +typedef struct { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q31_t *pData; /**< points to the data of the matrix. */ +} arm_matrix_instance_q31; - /** +/** * @brief Floating-point matrix addition. * @param[in] pSrcA points to the first input matrix structure * @param[in] pSrcB points to the second input matrix structure @@ -170,12 +163,10 @@ extern "C" * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ -arm_status arm_mat_add_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); +arm_status arm_mat_add_f32(const arm_matrix_instance_f32 *pSrcA, + const arm_matrix_instance_f32 *pSrcB, arm_matrix_instance_f32 *pDst); - /** +/** * @brief Q15 matrix addition. * @param[in] pSrcA points to the first input matrix structure * @param[in] pSrcB points to the second input matrix structure @@ -183,12 +174,10 @@ arm_status arm_mat_add_f32( * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ -arm_status arm_mat_add_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst); +arm_status arm_mat_add_q15(const arm_matrix_instance_q15 *pSrcA, + const arm_matrix_instance_q15 *pSrcB, arm_matrix_instance_q15 *pDst); - /** +/** * @brief Q31 matrix addition. * @param[in] pSrcA points to the first input matrix structure * @param[in] pSrcB points to the second input matrix structure @@ -196,12 +185,10 @@ arm_status arm_mat_add_q15( * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ -arm_status arm_mat_add_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); +arm_status arm_mat_add_q31(const arm_matrix_instance_q31 *pSrcA, + const arm_matrix_instance_q31 *pSrcB, arm_matrix_instance_q31 *pDst); - /** +/** * @brief Floating-point, complex, matrix multiplication. * @param[in] pSrcA points to the first input matrix structure * @param[in] pSrcB points to the second input matrix structure @@ -209,12 +196,11 @@ arm_status arm_mat_add_q31( * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ -arm_status arm_mat_cmplx_mult_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); +arm_status arm_mat_cmplx_mult_f32(const arm_matrix_instance_f32 *pSrcA, + const arm_matrix_instance_f32 *pSrcB, + arm_matrix_instance_f32 *pDst); - /** +/** * @brief Q15, complex, matrix multiplication. * @param[in] pSrcA points to the first input matrix structure * @param[in] pSrcB points to the second input matrix structure @@ -222,13 +208,11 @@ arm_status arm_mat_cmplx_mult_f32( * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ -arm_status arm_mat_cmplx_mult_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst, - q15_t * pScratch); +arm_status arm_mat_cmplx_mult_q15(const arm_matrix_instance_q15 *pSrcA, + const arm_matrix_instance_q15 *pSrcB, + arm_matrix_instance_q15 *pDst, q15_t *pScratch); - /** +/** * @brief Q31, complex, matrix multiplication. * @param[in] pSrcA points to the first input matrix structure * @param[in] pSrcB points to the second input matrix structure @@ -236,21 +220,18 @@ arm_status arm_mat_cmplx_mult_q15( * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ -arm_status arm_mat_cmplx_mult_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); +arm_status arm_mat_cmplx_mult_q31(const arm_matrix_instance_q31 *pSrcA, + const arm_matrix_instance_q31 *pSrcB, + arm_matrix_instance_q31 *pDst); - /** +/** * @brief Floating-point matrix transpose. * @param[in] pSrc points to the input matrix * @param[out] pDst points to the output matrix * @return The function returns either ARM_MATH_SIZE_MISMATCH * or ARM_MATH_SUCCESS based on the outcome of size checking. */ -arm_status arm_mat_trans_f32( - const arm_matrix_instance_f32 * pSrc, - arm_matrix_instance_f32 * pDst); +arm_status arm_mat_trans_f32(const arm_matrix_instance_f32 *pSrc, arm_matrix_instance_f32 *pDst); /** * @brief Floating-point matrix transpose. @@ -259,78 +240,66 @@ arm_status arm_mat_trans_f32( * @return The function returns either ARM_MATH_SIZE_MISMATCH * or ARM_MATH_SUCCESS based on the outcome of size checking. */ -arm_status arm_mat_trans_f64( - const arm_matrix_instance_f64 * pSrc, - arm_matrix_instance_f64 * pDst); +arm_status arm_mat_trans_f64(const arm_matrix_instance_f64 *pSrc, arm_matrix_instance_f64 *pDst); - /** +/** * @brief Floating-point complex matrix transpose. * @param[in] pSrc points to the input matrix * @param[out] pDst points to the output matrix * @return The function returns either ARM_MATH_SIZE_MISMATCH * or ARM_MATH_SUCCESS based on the outcome of size checking. */ -arm_status arm_mat_cmplx_trans_f32( - const arm_matrix_instance_f32 * pSrc, - arm_matrix_instance_f32 * pDst); - +arm_status arm_mat_cmplx_trans_f32(const arm_matrix_instance_f32 *pSrc, + arm_matrix_instance_f32 *pDst); - /** +/** * @brief Q15 matrix transpose. * @param[in] pSrc points to the input matrix * @param[out] pDst points to the output matrix * @return The function returns either ARM_MATH_SIZE_MISMATCH * or ARM_MATH_SUCCESS based on the outcome of size checking. */ -arm_status arm_mat_trans_q15( - const arm_matrix_instance_q15 * pSrc, - arm_matrix_instance_q15 * pDst); +arm_status arm_mat_trans_q15(const arm_matrix_instance_q15 *pSrc, arm_matrix_instance_q15 *pDst); - /** +/** * @brief Q15 complex matrix transpose. * @param[in] pSrc points to the input matrix * @param[out] pDst points to the output matrix * @return The function returns either ARM_MATH_SIZE_MISMATCH * or ARM_MATH_SUCCESS based on the outcome of size checking. */ -arm_status arm_mat_cmplx_trans_q15( - const arm_matrix_instance_q15 * pSrc, - arm_matrix_instance_q15 * pDst); +arm_status arm_mat_cmplx_trans_q15(const arm_matrix_instance_q15 *pSrc, + arm_matrix_instance_q15 *pDst); - /** +/** * @brief Q7 matrix transpose. * @param[in] pSrc points to the input matrix * @param[out] pDst points to the output matrix * @return The function returns either ARM_MATH_SIZE_MISMATCH * or ARM_MATH_SUCCESS based on the outcome of size checking. */ -arm_status arm_mat_trans_q7( - const arm_matrix_instance_q7 * pSrc, - arm_matrix_instance_q7 * pDst); +arm_status arm_mat_trans_q7(const arm_matrix_instance_q7 *pSrc, arm_matrix_instance_q7 *pDst); - /** +/** * @brief Q31 matrix transpose. * @param[in] pSrc points to the input matrix * @param[out] pDst points to the output matrix * @return The function returns either ARM_MATH_SIZE_MISMATCH * or ARM_MATH_SUCCESS based on the outcome of size checking. */ -arm_status arm_mat_trans_q31( - const arm_matrix_instance_q31 * pSrc, - arm_matrix_instance_q31 * pDst); +arm_status arm_mat_trans_q31(const arm_matrix_instance_q31 *pSrc, arm_matrix_instance_q31 *pDst); - /** +/** * @brief Q31 complex matrix transpose. * @param[in] pSrc points to the input matrix * @param[out] pDst points to the output matrix * @return The function returns either ARM_MATH_SIZE_MISMATCH * or ARM_MATH_SUCCESS based on the outcome of size checking. */ -arm_status arm_mat_cmplx_trans_q31( - const arm_matrix_instance_q31 * pSrc, - arm_matrix_instance_q31 * pDst); +arm_status arm_mat_cmplx_trans_q31(const arm_matrix_instance_q31 *pSrc, + arm_matrix_instance_q31 *pDst); - /** +/** * @brief Floating-point matrix multiplication * @param[in] pSrcA points to the first input matrix structure * @param[in] pSrcB points to the second input matrix structure @@ -338,12 +307,10 @@ arm_status arm_mat_cmplx_trans_q31( * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ -arm_status arm_mat_mult_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); +arm_status arm_mat_mult_f32(const arm_matrix_instance_f32 *pSrcA, + const arm_matrix_instance_f32 *pSrcB, arm_matrix_instance_f32 *pDst); - /** +/** * @brief Floating-point matrix multiplication * @param[in] pSrcA points to the first input matrix structure * @param[in] pSrcB points to the second input matrix structure @@ -351,23 +318,19 @@ arm_status arm_mat_mult_f32( * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ -arm_status arm_mat_mult_f64( - const arm_matrix_instance_f64 * pSrcA, - const arm_matrix_instance_f64 * pSrcB, - arm_matrix_instance_f64 * pDst); +arm_status arm_mat_mult_f64(const arm_matrix_instance_f64 *pSrcA, + const arm_matrix_instance_f64 *pSrcB, arm_matrix_instance_f64 *pDst); - /** +/** * @brief Floating-point matrix and vector multiplication * @param[in] pSrcMat points to the input matrix structure * @param[in] pVec points to vector * @param[out] pDst points to output vector */ -void arm_mat_vec_mult_f32( - const arm_matrix_instance_f32 *pSrcMat, - const float32_t *pVec, - float32_t *pDst); +void arm_mat_vec_mult_f32(const arm_matrix_instance_f32 *pSrcMat, const float32_t *pVec, + float32_t *pDst); - /** +/** * @brief Q7 matrix multiplication * @param[in] pSrcA points to the first input matrix structure * @param[in] pSrcB points to the second input matrix structure @@ -376,24 +339,18 @@ void arm_mat_vec_mult_f32( * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ -arm_status arm_mat_mult_q7( - const arm_matrix_instance_q7 * pSrcA, - const arm_matrix_instance_q7 * pSrcB, - arm_matrix_instance_q7 * pDst, - q7_t * pState); +arm_status arm_mat_mult_q7(const arm_matrix_instance_q7 *pSrcA, const arm_matrix_instance_q7 *pSrcB, + arm_matrix_instance_q7 *pDst, q7_t *pState); - /** +/** * @brief Q7 matrix and vector multiplication * @param[in] pSrcMat points to the input matrix structure * @param[in] pVec points to vector * @param[out] pDst points to output vector */ -void arm_mat_vec_mult_q7( - const arm_matrix_instance_q7 *pSrcMat, - const q7_t *pVec, - q7_t *pDst); +void arm_mat_vec_mult_q7(const arm_matrix_instance_q7 *pSrcMat, const q7_t *pVec, q7_t *pDst); - /** +/** * @brief Q15 matrix multiplication * @param[in] pSrcA points to the first input matrix structure * @param[in] pSrcB points to the second input matrix structure @@ -402,24 +359,19 @@ void arm_mat_vec_mult_q7( * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ -arm_status arm_mat_mult_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst, - q15_t * pState); +arm_status arm_mat_mult_q15(const arm_matrix_instance_q15 *pSrcA, + const arm_matrix_instance_q15 *pSrcB, arm_matrix_instance_q15 *pDst, + q15_t *pState); - /** +/** * @brief Q15 matrix and vector multiplication * @param[in] pSrcMat points to the input matrix structure * @param[in] pVec points to vector * @param[out] pDst points to output vector */ -void arm_mat_vec_mult_q15( - const arm_matrix_instance_q15 *pSrcMat, - const q15_t *pVec, - q15_t *pDst); +void arm_mat_vec_mult_q15(const arm_matrix_instance_q15 *pSrcMat, const q15_t *pVec, q15_t *pDst); - /** +/** * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 * @param[in] pSrcA points to the first input matrix structure * @param[in] pSrcB points to the second input matrix structure @@ -428,13 +380,11 @@ void arm_mat_vec_mult_q15( * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ -arm_status arm_mat_mult_fast_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst, - q15_t * pState); +arm_status arm_mat_mult_fast_q15(const arm_matrix_instance_q15 *pSrcA, + const arm_matrix_instance_q15 *pSrcB, + arm_matrix_instance_q15 *pDst, q15_t *pState); - /** +/** * @brief Q31 matrix multiplication * @param[in] pSrcA points to the first input matrix structure * @param[in] pSrcB points to the second input matrix structure @@ -442,12 +392,10 @@ arm_status arm_mat_mult_fast_q15( * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ -arm_status arm_mat_mult_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); +arm_status arm_mat_mult_q31(const arm_matrix_instance_q31 *pSrcA, + const arm_matrix_instance_q31 *pSrcB, arm_matrix_instance_q31 *pDst); - /** +/** * @brief Q31 matrix multiplication * @param[in] pSrcA points to the first input matrix structure * @param[in] pSrcB points to the second input matrix structure @@ -456,24 +404,19 @@ arm_status arm_mat_mult_q31( * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ -arm_status arm_mat_mult_opt_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst, - q31_t *pState); +arm_status arm_mat_mult_opt_q31(const arm_matrix_instance_q31 *pSrcA, + const arm_matrix_instance_q31 *pSrcB, arm_matrix_instance_q31 *pDst, + q31_t *pState); - /** +/** * @brief Q31 matrix and vector multiplication * @param[in] pSrcMat points to the input matrix structure * @param[in] pVec points to vector * @param[out] pDst points to output vector */ -void arm_mat_vec_mult_q31( - const arm_matrix_instance_q31 *pSrcMat, - const q31_t *pVec, - q31_t *pDst); +void arm_mat_vec_mult_q31(const arm_matrix_instance_q31 *pSrcMat, const q31_t *pVec, q31_t *pDst); - /** +/** * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 * @param[in] pSrcA points to the first input matrix structure * @param[in] pSrcB points to the second input matrix structure @@ -481,12 +424,11 @@ void arm_mat_vec_mult_q31( * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ -arm_status arm_mat_mult_fast_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); +arm_status arm_mat_mult_fast_q31(const arm_matrix_instance_q31 *pSrcA, + const arm_matrix_instance_q31 *pSrcB, + arm_matrix_instance_q31 *pDst); - /** +/** * @brief Floating-point matrix subtraction * @param[in] pSrcA points to the first input matrix structure * @param[in] pSrcB points to the second input matrix structure @@ -494,12 +436,10 @@ arm_status arm_mat_mult_fast_q31( * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ -arm_status arm_mat_sub_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); +arm_status arm_mat_sub_f32(const arm_matrix_instance_f32 *pSrcA, + const arm_matrix_instance_f32 *pSrcB, arm_matrix_instance_f32 *pDst); - /** +/** * @brief Floating-point matrix subtraction * @param[in] pSrcA points to the first input matrix structure * @param[in] pSrcB points to the second input matrix structure @@ -507,12 +447,10 @@ arm_status arm_mat_sub_f32( * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ -arm_status arm_mat_sub_f64( - const arm_matrix_instance_f64 * pSrcA, - const arm_matrix_instance_f64 * pSrcB, - arm_matrix_instance_f64 * pDst); +arm_status arm_mat_sub_f64(const arm_matrix_instance_f64 *pSrcA, + const arm_matrix_instance_f64 *pSrcB, arm_matrix_instance_f64 *pDst); - /** +/** * @brief Q15 matrix subtraction * @param[in] pSrcA points to the first input matrix structure * @param[in] pSrcB points to the second input matrix structure @@ -520,12 +458,10 @@ arm_status arm_mat_sub_f64( * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ -arm_status arm_mat_sub_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst); +arm_status arm_mat_sub_q15(const arm_matrix_instance_q15 *pSrcA, + const arm_matrix_instance_q15 *pSrcB, arm_matrix_instance_q15 *pDst); - /** +/** * @brief Q31 matrix subtraction * @param[in] pSrcA points to the first input matrix structure * @param[in] pSrcB points to the second input matrix structure @@ -533,12 +469,10 @@ arm_status arm_mat_sub_q15( * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ -arm_status arm_mat_sub_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); +arm_status arm_mat_sub_q31(const arm_matrix_instance_q31 *pSrcA, + const arm_matrix_instance_q31 *pSrcB, arm_matrix_instance_q31 *pDst); - /** +/** * @brief Floating-point matrix scaling. * @param[in] pSrc points to the input matrix * @param[in] scale scale factor @@ -546,12 +480,10 @@ arm_status arm_mat_sub_q31( * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ -arm_status arm_mat_scale_f32( - const arm_matrix_instance_f32 * pSrc, - float32_t scale, - arm_matrix_instance_f32 * pDst); +arm_status arm_mat_scale_f32(const arm_matrix_instance_f32 *pSrc, float32_t scale, + arm_matrix_instance_f32 *pDst); - /** +/** * @brief Q15 matrix scaling. * @param[in] pSrc points to input matrix * @param[in] scaleFract fractional portion of the scale factor @@ -560,13 +492,10 @@ arm_status arm_mat_scale_f32( * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ -arm_status arm_mat_scale_q15( - const arm_matrix_instance_q15 * pSrc, - q15_t scaleFract, - int32_t shift, - arm_matrix_instance_q15 * pDst); +arm_status arm_mat_scale_q15(const arm_matrix_instance_q15 *pSrc, q15_t scaleFract, int32_t shift, + arm_matrix_instance_q15 *pDst); - /** +/** * @brief Q31 matrix scaling. * @param[in] pSrc points to input matrix * @param[in] scaleFract fractional portion of the scale factor @@ -575,50 +504,36 @@ arm_status arm_mat_scale_q15( * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ -arm_status arm_mat_scale_q31( - const arm_matrix_instance_q31 * pSrc, - q31_t scaleFract, - int32_t shift, - arm_matrix_instance_q31 * pDst); +arm_status arm_mat_scale_q31(const arm_matrix_instance_q31 *pSrc, q31_t scaleFract, int32_t shift, + arm_matrix_instance_q31 *pDst); - /** +/** * @brief Q31 matrix initialization. * @param[in,out] S points to an instance of the floating-point matrix structure. * @param[in] nRows number of rows in the matrix. * @param[in] nColumns number of columns in the matrix. * @param[in] pData points to the matrix data array. */ -void arm_mat_init_q31( - arm_matrix_instance_q31 * S, - uint16_t nRows, - uint16_t nColumns, - q31_t * pData); +void arm_mat_init_q31(arm_matrix_instance_q31 *S, uint16_t nRows, uint16_t nColumns, q31_t *pData); - /** +/** * @brief Q15 matrix initialization. * @param[in,out] S points to an instance of the floating-point matrix structure. * @param[in] nRows number of rows in the matrix. * @param[in] nColumns number of columns in the matrix. * @param[in] pData points to the matrix data array. */ -void arm_mat_init_q15( - arm_matrix_instance_q15 * S, - uint16_t nRows, - uint16_t nColumns, - q15_t * pData); +void arm_mat_init_q15(arm_matrix_instance_q15 *S, uint16_t nRows, uint16_t nColumns, q15_t *pData); - /** +/** * @brief Floating-point matrix initialization. * @param[in,out] S points to an instance of the floating-point matrix structure. * @param[in] nRows number of rows in the matrix. * @param[in] nColumns number of columns in the matrix. * @param[in] pData points to the matrix data array. */ -void arm_mat_init_f32( - arm_matrix_instance_f32 * S, - uint16_t nRows, - uint16_t nColumns, - float32_t * pData); +void arm_mat_init_f32(arm_matrix_instance_f32 *S, uint16_t nRows, uint16_t nColumns, + float32_t *pData); /** * @brief Floating-point matrix initialization. @@ -627,39 +542,28 @@ void arm_mat_init_f32( * @param[in] nColumns number of columns in the matrix. * @param[in] pData points to the matrix data array. */ -void arm_mat_init_f64( - arm_matrix_instance_f64 * S, - uint16_t nRows, - uint16_t nColumns, - float64_t * pData); - - +void arm_mat_init_f64(arm_matrix_instance_f64 *S, uint16_t nRows, uint16_t nColumns, + float64_t *pData); - - /** +/** * @brief Floating-point matrix inverse. * @param[in] src points to the instance of the input floating-point matrix structure. * @param[out] dst points to the instance of the output floating-point matrix structure. * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. */ - arm_status arm_mat_inverse_f32( - const arm_matrix_instance_f32 * src, - arm_matrix_instance_f32 * dst); +arm_status arm_mat_inverse_f32(const arm_matrix_instance_f32 *src, arm_matrix_instance_f32 *dst); - - /** +/** * @brief Floating-point matrix inverse. * @param[in] src points to the instance of the input floating-point matrix structure. * @param[out] dst points to the instance of the output floating-point matrix structure. * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. */ - arm_status arm_mat_inverse_f64( - const arm_matrix_instance_f64 * src, - arm_matrix_instance_f64 * dst); +arm_status arm_mat_inverse_f64(const arm_matrix_instance_f64 *src, arm_matrix_instance_f64 *dst); - /** +/** * @brief Floating-point Cholesky decomposition of Symmetric Positive Definite Matrix. * @param[in] src points to the instance of the input floating-point matrix structure. * @param[out] dst points to the instance of the output floating-point matrix structure. @@ -668,11 +572,9 @@ void arm_mat_init_f64( * If the matrix is ill conditioned or only semi-definite, then it is better using the LDL^t decomposition. * The decomposition is returning a lower triangular matrix. */ - arm_status arm_mat_cholesky_f64( - const arm_matrix_instance_f64 * src, - arm_matrix_instance_f64 * dst); +arm_status arm_mat_cholesky_f64(const arm_matrix_instance_f64 *src, arm_matrix_instance_f64 *dst); - /** +/** * @brief Floating-point Cholesky decomposition of Symmetric Positive Definite Matrix. * @param[in] src points to the instance of the input floating-point matrix structure. * @param[out] dst points to the instance of the output floating-point matrix structure. @@ -681,61 +583,53 @@ void arm_mat_init_f64( * If the matrix is ill conditioned or only semi-definite, then it is better using the LDL^t decomposition. * The decomposition is returning a lower triangular matrix. */ - arm_status arm_mat_cholesky_f32( - const arm_matrix_instance_f32 * src, - arm_matrix_instance_f32 * dst); +arm_status arm_mat_cholesky_f32(const arm_matrix_instance_f32 *src, arm_matrix_instance_f32 *dst); - /** +/** * @brief Solve UT . X = A where UT is an upper triangular matrix * @param[in] ut The upper triangular matrix * @param[in] a The matrix a * @param[out] dst The solution X of UT . X = A * @return The function returns ARM_MATH_SINGULAR, if the system can't be solved. */ - arm_status arm_mat_solve_upper_triangular_f32( - const arm_matrix_instance_f32 * ut, - const arm_matrix_instance_f32 * a, - arm_matrix_instance_f32 * dst); +arm_status arm_mat_solve_upper_triangular_f32(const arm_matrix_instance_f32 *ut, + const arm_matrix_instance_f32 *a, + arm_matrix_instance_f32 *dst); - /** +/** * @brief Solve LT . X = A where LT is a lower triangular matrix * @param[in] lt The lower triangular matrix * @param[in] a The matrix a * @param[out] dst The solution X of LT . X = A * @return The function returns ARM_MATH_SINGULAR, if the system can't be solved. */ - arm_status arm_mat_solve_lower_triangular_f32( - const arm_matrix_instance_f32 * lt, - const arm_matrix_instance_f32 * a, - arm_matrix_instance_f32 * dst); - +arm_status arm_mat_solve_lower_triangular_f32(const arm_matrix_instance_f32 *lt, + const arm_matrix_instance_f32 *a, + arm_matrix_instance_f32 *dst); - /** +/** * @brief Solve UT . X = A where UT is an upper triangular matrix * @param[in] ut The upper triangular matrix * @param[in] a The matrix a * @param[out] dst The solution X of UT . X = A * @return The function returns ARM_MATH_SINGULAR, if the system can't be solved. */ - arm_status arm_mat_solve_upper_triangular_f64( - const arm_matrix_instance_f64 * ut, - const arm_matrix_instance_f64 * a, - arm_matrix_instance_f64 * dst); +arm_status arm_mat_solve_upper_triangular_f64(const arm_matrix_instance_f64 *ut, + const arm_matrix_instance_f64 *a, + arm_matrix_instance_f64 *dst); - /** +/** * @brief Solve LT . X = A where LT is a lower triangular matrix * @param[in] lt The lower triangular matrix * @param[in] a The matrix a * @param[out] dst The solution X of LT . X = A * @return The function returns ARM_MATH_SINGULAR, if the system can't be solved. */ - arm_status arm_mat_solve_lower_triangular_f64( - const arm_matrix_instance_f64 * lt, - const arm_matrix_instance_f64 * a, - arm_matrix_instance_f64 * dst); +arm_status arm_mat_solve_lower_triangular_f64(const arm_matrix_instance_f64 *lt, + const arm_matrix_instance_f64 *a, + arm_matrix_instance_f64 *dst); - - /** +/** * @brief Floating-point LDL decomposition of Symmetric Positive Semi-Definite Matrix. * @param[in] src points to the instance of the input floating-point matrix structure. * @param[out] l points to the instance of the output floating-point triangular matrix structure. @@ -745,13 +639,10 @@ void arm_mat_init_f64( * If the input matrix does not have a decomposition, then the algorithm terminates and returns error status ARM_MATH_DECOMPOSITION_FAILURE. * The decomposition is returning a lower triangular matrix. */ - arm_status arm_mat_ldlt_f32( - const arm_matrix_instance_f32 * src, - arm_matrix_instance_f32 * l, - arm_matrix_instance_f32 * d, - uint16_t * pp); +arm_status arm_mat_ldlt_f32(const arm_matrix_instance_f32 *src, arm_matrix_instance_f32 *l, + arm_matrix_instance_f32 *d, uint16_t *pp); - /** +/** * @brief Floating-point LDL decomposition of Symmetric Positive Semi-Definite Matrix. * @param[in] src points to the instance of the input floating-point matrix structure. * @param[out] l points to the instance of the output floating-point triangular matrix structure. @@ -761,11 +652,8 @@ void arm_mat_init_f64( * If the input matrix does not have a decomposition, then the algorithm terminates and returns error status ARM_MATH_DECOMPOSITION_FAILURE. * The decomposition is returning a lower triangular matrix. */ - arm_status arm_mat_ldlt_f64( - const arm_matrix_instance_f64 * src, - arm_matrix_instance_f64 * l, - arm_matrix_instance_f64 * d, - uint16_t * pp); +arm_status arm_mat_ldlt_f64(const arm_matrix_instance_f64 *src, arm_matrix_instance_f64 *l, + arm_matrix_instance_f64 *d, uint16_t *pp); /** @brief QR decomposition of a m x n floating point matrix with m >= n. @@ -782,15 +670,9 @@ void arm_mat_init_f64( - \ref ARM_MATH_SINGULAR : Input matrix is found to be singular (non-invertible) */ -arm_status arm_mat_qr_f32( - const arm_matrix_instance_f32 * pSrc, - const float32_t threshold, - arm_matrix_instance_f32 * pOutR, - arm_matrix_instance_f32 * pOutQ, - float32_t * pOutTau, - float32_t *pTmpA, - float32_t *pTmpB - ); +arm_status arm_mat_qr_f32(const arm_matrix_instance_f32 *pSrc, const float32_t threshold, + arm_matrix_instance_f32 *pOutR, arm_matrix_instance_f32 *pOutQ, + float32_t *pOutTau, float32_t *pTmpA, float32_t *pTmpB); /** @brief QR decomposition of a m x n floating point matrix with m >= n. @@ -807,15 +689,9 @@ arm_status arm_mat_qr_f32( - \ref ARM_MATH_SINGULAR : Input matrix is found to be singular (non-invertible) */ -arm_status arm_mat_qr_f64( - const arm_matrix_instance_f64 * pSrc, - const float64_t threshold, - arm_matrix_instance_f64 * pOutR, - arm_matrix_instance_f64 * pOutQ, - float64_t * pOutTau, - float64_t *pTmpA, - float64_t *pTmpB - ); +arm_status arm_mat_qr_f64(const arm_matrix_instance_f64 *pSrc, const float64_t threshold, + arm_matrix_instance_f64 *pOutR, arm_matrix_instance_f64 *pOutQ, + float64_t *pOutTau, float64_t *pTmpA, float64_t *pTmpB); /** @brief Householder transform of a floating point vector. @@ -826,12 +702,8 @@ arm_status arm_mat_qr_f64( @return beta return the scaling factor beta */ -float32_t arm_householder_f32( - const float32_t * pSrc, - const float32_t threshold, - uint32_t blockSize, - float32_t * pOut - ); +float32_t arm_householder_f32(const float32_t *pSrc, const float32_t threshold, uint32_t blockSize, + float32_t *pOut); /** @brief Householder transform of a double floating point vector. @@ -842,14 +714,10 @@ float32_t arm_householder_f32( @return beta return the scaling factor beta */ -float64_t arm_householder_f64( - const float64_t * pSrc, - const float64_t threshold, - uint32_t blockSize, - float64_t * pOut - ); +float64_t arm_householder_f64(const float64_t *pSrc, const float64_t threshold, uint32_t blockSize, + float64_t *pOut); -#ifdef __cplusplus +#ifdef __cplusplus } #endif diff --git a/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/matrix_functions_f16.h b/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/matrix_functions_f16.h old mode 100755 new mode 100644 index 39eb9a80175..7e11a7014d8 --- a/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/matrix_functions_f16.h +++ b/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/matrix_functions_f16.h @@ -23,37 +23,33 @@ * limitations under the License. */ - #ifndef MATRIX_FUNCTIONS_F16_H_ #define MATRIX_FUNCTIONS_F16_H_ -#ifdef __cplusplus -extern "C" -{ +#ifdef __cplusplus +extern "C" { #endif - #include "arm_math_types_f16.h" #include "arm_math_memory.h" #include "dsp/none.h" #include "dsp/utils.h" - + #if defined(ARM_FLOAT16_SUPPORTED) - #define DEFAULT_HOUSEHOLDER_THRESHOLD_F16 (1.0e-3f) +#define DEFAULT_HOUSEHOLDER_THRESHOLD_F16 (1.0e-3f) - /** +/** * @brief Instance structure for the floating-point matrix structure. */ - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - float16_t *pData; /**< points to the data of the matrix. */ - } arm_matrix_instance_f16; +typedef struct { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float16_t *pData; /**< points to the data of the matrix. */ +} arm_matrix_instance_f16; - /** +/** * @brief Floating-point matrix addition. * @param[in] pSrcA points to the first input matrix structure * @param[in] pSrcB points to the second input matrix structure @@ -61,12 +57,10 @@ extern "C" * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ -arm_status arm_mat_add_f16( - const arm_matrix_instance_f16 * pSrcA, - const arm_matrix_instance_f16 * pSrcB, - arm_matrix_instance_f16 * pDst); +arm_status arm_mat_add_f16(const arm_matrix_instance_f16 *pSrcA, + const arm_matrix_instance_f16 *pSrcB, arm_matrix_instance_f16 *pDst); - /** +/** * @brief Floating-point, complex, matrix multiplication. * @param[in] pSrcA points to the first input matrix structure * @param[in] pSrcB points to the second input matrix structure @@ -74,34 +68,30 @@ arm_status arm_mat_add_f16( * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ -arm_status arm_mat_cmplx_mult_f16( - const arm_matrix_instance_f16 * pSrcA, - const arm_matrix_instance_f16 * pSrcB, - arm_matrix_instance_f16 * pDst); +arm_status arm_mat_cmplx_mult_f16(const arm_matrix_instance_f16 *pSrcA, + const arm_matrix_instance_f16 *pSrcB, + arm_matrix_instance_f16 *pDst); - /** +/** * @brief Floating-point matrix transpose. * @param[in] pSrc points to the input matrix * @param[out] pDst points to the output matrix * @return The function returns either ARM_MATH_SIZE_MISMATCH * or ARM_MATH_SUCCESS based on the outcome of size checking. */ -arm_status arm_mat_trans_f16( - const arm_matrix_instance_f16 * pSrc, - arm_matrix_instance_f16 * pDst); +arm_status arm_mat_trans_f16(const arm_matrix_instance_f16 *pSrc, arm_matrix_instance_f16 *pDst); - /** +/** * @brief Floating-point complex matrix transpose. * @param[in] pSrc points to the input matrix * @param[out] pDst points to the output matrix * @return The function returns either ARM_MATH_SIZE_MISMATCH * or ARM_MATH_SUCCESS based on the outcome of size checking. */ -arm_status arm_mat_cmplx_trans_f16( - const arm_matrix_instance_f16 * pSrc, - arm_matrix_instance_f16 * pDst); +arm_status arm_mat_cmplx_trans_f16(const arm_matrix_instance_f16 *pSrc, + arm_matrix_instance_f16 *pDst); - /** +/** * @brief Floating-point matrix multiplication * @param[in] pSrcA points to the first input matrix structure * @param[in] pSrcB points to the second input matrix structure @@ -109,22 +99,18 @@ arm_status arm_mat_cmplx_trans_f16( * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ -arm_status arm_mat_mult_f16( - const arm_matrix_instance_f16 * pSrcA, - const arm_matrix_instance_f16 * pSrcB, - arm_matrix_instance_f16 * pDst); - /** +arm_status arm_mat_mult_f16(const arm_matrix_instance_f16 *pSrcA, + const arm_matrix_instance_f16 *pSrcB, arm_matrix_instance_f16 *pDst); +/** * @brief Floating-point matrix and vector multiplication * @param[in] pSrcMat points to the input matrix structure * @param[in] pVec points to vector * @param[out] pDst points to output vector */ -void arm_mat_vec_mult_f16( - const arm_matrix_instance_f16 *pSrcMat, - const float16_t *pVec, - float16_t *pDst); +void arm_mat_vec_mult_f16(const arm_matrix_instance_f16 *pSrcMat, const float16_t *pVec, + float16_t *pDst); - /** +/** * @brief Floating-point matrix subtraction * @param[in] pSrcA points to the first input matrix structure * @param[in] pSrcB points to the second input matrix structure @@ -132,12 +118,10 @@ void arm_mat_vec_mult_f16( * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ -arm_status arm_mat_sub_f16( - const arm_matrix_instance_f16 * pSrcA, - const arm_matrix_instance_f16 * pSrcB, - arm_matrix_instance_f16 * pDst); +arm_status arm_mat_sub_f16(const arm_matrix_instance_f16 *pSrcA, + const arm_matrix_instance_f16 *pSrcB, arm_matrix_instance_f16 *pDst); - /** +/** * @brief Floating-point matrix scaling. * @param[in] pSrc points to the input matrix * @param[in] scale scale factor @@ -145,38 +129,29 @@ arm_status arm_mat_sub_f16( * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ -arm_status arm_mat_scale_f16( - const arm_matrix_instance_f16 * pSrc, - float16_t scale, - arm_matrix_instance_f16 * pDst); +arm_status arm_mat_scale_f16(const arm_matrix_instance_f16 *pSrc, float16_t scale, + arm_matrix_instance_f16 *pDst); - /** +/** * @brief Floating-point matrix initialization. * @param[in,out] S points to an instance of the floating-point matrix structure. * @param[in] nRows number of rows in the matrix. * @param[in] nColumns number of columns in the matrix. * @param[in] pData points to the matrix data array. */ -void arm_mat_init_f16( - arm_matrix_instance_f16 * S, - uint16_t nRows, - uint16_t nColumns, - float16_t * pData); - +void arm_mat_init_f16(arm_matrix_instance_f16 *S, uint16_t nRows, uint16_t nColumns, + float16_t *pData); - /** +/** * @brief Floating-point matrix inverse. * @param[in] src points to the instance of the input floating-point matrix structure. * @param[out] dst points to the instance of the output floating-point matrix structure. * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. */ - arm_status arm_mat_inverse_f16( - const arm_matrix_instance_f16 * src, - arm_matrix_instance_f16 * dst); - +arm_status arm_mat_inverse_f16(const arm_matrix_instance_f16 *src, arm_matrix_instance_f16 *dst); - /** +/** * @brief Floating-point Cholesky decomposition of Symmetric Positive Definite Matrix. * @param[in] src points to the instance of the input floating-point matrix structure. * @param[out] dst points to the instance of the output floating-point matrix structure. @@ -185,34 +160,29 @@ void arm_mat_init_f16( * If the matrix is ill conditioned or only semi-definite, then it is better using the LDL^t decomposition. * The decomposition is returning a lower triangular matrix. */ - arm_status arm_mat_cholesky_f16( - const arm_matrix_instance_f16 * src, - arm_matrix_instance_f16 * dst); +arm_status arm_mat_cholesky_f16(const arm_matrix_instance_f16 *src, arm_matrix_instance_f16 *dst); - /** +/** * @brief Solve UT . X = A where UT is an upper triangular matrix * @param[in] ut The upper triangular matrix * @param[in] a The matrix a * @param[out] dst The solution X of UT . X = A * @return The function returns ARM_MATH_SINGULAR, if the system can't be solved. */ - arm_status arm_mat_solve_upper_triangular_f16( - const arm_matrix_instance_f16 * ut, - const arm_matrix_instance_f16 * a, - arm_matrix_instance_f16 * dst); +arm_status arm_mat_solve_upper_triangular_f16(const arm_matrix_instance_f16 *ut, + const arm_matrix_instance_f16 *a, + arm_matrix_instance_f16 *dst); - /** +/** * @brief Solve LT . X = A where LT is a lower triangular matrix * @param[in] lt The lower triangular matrix * @param[in] a The matrix a * @param[out] dst The solution X of LT . X = A * @return The function returns ARM_MATH_SINGULAR, if the system can't be solved. */ - arm_status arm_mat_solve_lower_triangular_f16( - const arm_matrix_instance_f16 * lt, - const arm_matrix_instance_f16 * a, - arm_matrix_instance_f16 * dst); - +arm_status arm_mat_solve_lower_triangular_f16(const arm_matrix_instance_f16 *lt, + const arm_matrix_instance_f16 *a, + arm_matrix_instance_f16 *dst); /** @brief QR decomposition of a m x n floating point matrix with m >= n. @@ -228,15 +198,9 @@ void arm_mat_init_f16( - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed - \ref ARM_MATH_SINGULAR : Input matrix is found to be singular (non-invertible) */ -arm_status arm_mat_qr_f16( - const arm_matrix_instance_f16 * pSrc, - const float16_t threshold, - arm_matrix_instance_f16 * pOutR, - arm_matrix_instance_f16 * pOutQ, - float16_t * pOutTau, - float16_t *pTmpA, - float16_t *pTmpB - ); +arm_status arm_mat_qr_f16(const arm_matrix_instance_f16 *pSrc, const float16_t threshold, + arm_matrix_instance_f16 *pOutR, arm_matrix_instance_f16 *pOutQ, + float16_t *pOutTau, float16_t *pTmpA, float16_t *pTmpB); /** @brief Householder transform of a half floating point vector. @@ -246,15 +210,11 @@ arm_status arm_mat_qr_f16( @param[outQ] pOut points to the output vector. @return beta return the scaling factor beta */ -float16_t arm_householder_f16( - const float16_t * pSrc, - const float16_t threshold, - uint32_t blockSize, - float16_t * pOut - ); +float16_t arm_householder_f16(const float16_t *pSrc, const float16_t threshold, uint32_t blockSize, + float16_t *pOut); #endif /*defined(ARM_FLOAT16_SUPPORTED)*/ -#ifdef __cplusplus +#ifdef __cplusplus } #endif diff --git a/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/matrix_utils.h b/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/matrix_utils.h old mode 100755 new mode 100644 index 79e7f8cf103..c493802222b --- a/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/matrix_utils.h +++ b/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/matrix_utils.h @@ -23,7 +23,6 @@ * limitations under the License. */ - #ifndef MATRIX_UTILS_H_ #define MATRIX_UTILS_H_ @@ -33,607 +32,557 @@ #include "dsp/none.h" #include "dsp/utils.h" -#ifdef __cplusplus -extern "C" -{ +#ifdef __cplusplus +extern "C" { #endif -#define ELEM(A,ROW,COL) &((A)->pData[(A)->numCols* (ROW) + (COL)]) - -#define SCALE_COL_T(T,CAST,A,ROW,v,i) \ -{ \ - int32_t _w; \ - T *data = (A)->pData; \ - const int32_t _numCols = (A)->numCols; \ - const int32_t nb = (A)->numRows - ROW;\ - \ - data += i + _numCols * (ROW); \ - \ - for(_w=0;_w < nb; _w++) \ - { \ - *data *= CAST v; \ - data += _numCols; \ - } \ -} - -#define COPY_COL_T(T,A,ROW,COL,DST) \ -{ \ - uint32_t _row; \ - T *_pb=DST; \ - T *_pa = (A)->pData + ROW * (A)->numCols + COL;\ - for(_row = ROW; _row < (A)->numRows; _row ++) \ - { \ - *_pb++ = *_pa; \ - _pa += (A)->numCols; \ - } \ -} +#define ELEM(A, ROW, COL) &((A)->pData[(A)->numCols * (ROW) + (COL)]) + +#define SCALE_COL_T(T, CAST, A, ROW, v, i) \ + { \ + int32_t _w; \ + T *data = (A)->pData; \ + const int32_t _numCols = (A)->numCols; \ + const int32_t nb = (A)->numRows - ROW; \ + \ + data += i + _numCols * (ROW); \ + \ + for (_w = 0; _w < nb; _w++) { \ + *data *= CAST v; \ + data += _numCols; \ + } \ + } + +#define COPY_COL_T(T, A, ROW, COL, DST) \ + { \ + uint32_t _row; \ + T *_pb = DST; \ + T *_pa = (A)->pData + ROW * (A)->numCols + COL; \ + for (_row = ROW; _row < (A)->numRows; _row++) { \ + *_pb++ = *_pa; \ + _pa += (A)->numCols; \ + } \ + } #if defined(ARM_FLOAT16_SUPPORTED) #if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) -#define SWAP_ROWS_F16(A,COL,i,j) \ - { \ - int cnt = ((A)->numCols)-(COL); \ - int32_t _w; \ - float16_t *data = (A)->pData; \ - const int32_t _numCols = (A)->numCols; \ - \ - for(_w=(COL);_w < _numCols; _w+=8) \ - { \ - f16x8_t tmpa,tmpb; \ - mve_pred16_t p0 = vctp16q(cnt); \ - \ - tmpa=vldrhq_z_f16(&data[i*_numCols + _w],p0);\ - tmpb=vldrhq_z_f16(&data[j*_numCols + _w],p0);\ - \ - vstrhq_p(&data[i*_numCols + _w], tmpb, p0); \ - vstrhq_p(&data[j*_numCols + _w], tmpa, p0); \ - \ - cnt -= 8; \ - } \ - } - -#define SCALE_ROW_F16(A,COL,v,i) \ -{ \ - int cnt = ((A)->numCols)-(COL); \ - int32_t _w; \ - float16_t *data = (A)->pData; \ - const int32_t _numCols = (A)->numCols; \ - \ - for(_w=(COL);_w < _numCols; _w+=8) \ - { \ - f16x8_t tmpa; \ - mve_pred16_t p0 = vctp16q(cnt); \ - tmpa = vldrhq_z_f16(&data[i*_numCols + _w],p0);\ - tmpa = vmulq_n_f16(tmpa,(_Float16)v); \ - vstrhq_p(&data[i*_numCols + _w], tmpa, p0); \ - cnt -= 8; \ - } \ - \ -} - -#define MAC_ROW_F16(COL,A,i,v,B,j) \ -{ \ - int cnt = ((A)->numCols)-(COL); \ - int32_t _w; \ - float16_t *dataA = (A)->pData; \ - float16_t *dataB = (B)->pData; \ - const int32_t _numCols = (A)->numCols; \ - \ - for(_w=(COL);_w < _numCols; _w+=8) \ - { \ - f16x8_t tmpa,tmpb; \ - mve_pred16_t p0 = vctp16q(cnt); \ - tmpa = vldrhq_z_f16(&dataA[i*_numCols + _w],p0);\ - tmpb = vldrhq_z_f16(&dataB[j*_numCols + _w],p0);\ - tmpa = vfmaq_n_f16(tmpa,tmpb,v); \ - vstrhq_p(&dataA[i*_numCols + _w], tmpa, p0); \ - cnt -= 8; \ - } \ - \ -} - -#define MAS_ROW_F16(COL,A,i,v,B,j) \ -{ \ - int cnt = ((A)->numCols)-(COL); \ - int32_t _w; \ - float16_t *dataA = (A)->pData; \ - float16_t *dataB = (B)->pData; \ - const int32_t _numCols = (A)->numCols; \ - f16x8_t vec=vdupq_n_f16(v); \ - \ - for(_w=(COL);_w < _numCols; _w+=8) \ - { \ - f16x8_t tmpa,tmpb; \ - mve_pred16_t p0 = vctp16q(cnt); \ - tmpa = vldrhq_z_f16(&dataA[i*_numCols + _w],p0);\ - tmpb = vldrhq_z_f16(&dataB[j*_numCols + _w],p0);\ - tmpa = vfmsq_f16(tmpa,tmpb,vec); \ - vstrhq_p(&dataA[i*_numCols + _w], tmpa, p0); \ - cnt -= 8; \ - } \ - \ -} +#define SWAP_ROWS_F16(A, COL, i, j) \ + { \ + int cnt = ((A)->numCols) - (COL); \ + int32_t _w; \ + float16_t *data = (A)->pData; \ + const int32_t _numCols = (A)->numCols; \ + \ + for (_w = (COL); _w < _numCols; _w += 8) { \ + f16x8_t tmpa, tmpb; \ + mve_pred16_t p0 = vctp16q(cnt); \ + \ + tmpa = vldrhq_z_f16(&data[i * _numCols + _w], p0); \ + tmpb = vldrhq_z_f16(&data[j * _numCols + _w], p0); \ + \ + vstrhq_p(&data[i * _numCols + _w], tmpb, p0); \ + vstrhq_p(&data[j * _numCols + _w], tmpa, p0); \ + \ + cnt -= 8; \ + } \ + } + +#define SCALE_ROW_F16(A, COL, v, i) \ + { \ + int cnt = ((A)->numCols) - (COL); \ + int32_t _w; \ + float16_t *data = (A)->pData; \ + const int32_t _numCols = (A)->numCols; \ + \ + for (_w = (COL); _w < _numCols; _w += 8) { \ + f16x8_t tmpa; \ + mve_pred16_t p0 = vctp16q(cnt); \ + tmpa = vldrhq_z_f16(&data[i * _numCols + _w], p0); \ + tmpa = vmulq_n_f16(tmpa, (_Float16)v); \ + vstrhq_p(&data[i * _numCols + _w], tmpa, p0); \ + cnt -= 8; \ + } \ + } + +#define MAC_ROW_F16(COL, A, i, v, B, j) \ + { \ + int cnt = ((A)->numCols) - (COL); \ + int32_t _w; \ + float16_t *dataA = (A)->pData; \ + float16_t *dataB = (B)->pData; \ + const int32_t _numCols = (A)->numCols; \ + \ + for (_w = (COL); _w < _numCols; _w += 8) { \ + f16x8_t tmpa, tmpb; \ + mve_pred16_t p0 = vctp16q(cnt); \ + tmpa = vldrhq_z_f16(&dataA[i * _numCols + _w], p0); \ + tmpb = vldrhq_z_f16(&dataB[j * _numCols + _w], p0); \ + tmpa = vfmaq_n_f16(tmpa, tmpb, v); \ + vstrhq_p(&dataA[i * _numCols + _w], tmpa, p0); \ + cnt -= 8; \ + } \ + } + +#define MAS_ROW_F16(COL, A, i, v, B, j) \ + { \ + int cnt = ((A)->numCols) - (COL); \ + int32_t _w; \ + float16_t *dataA = (A)->pData; \ + float16_t *dataB = (B)->pData; \ + const int32_t _numCols = (A)->numCols; \ + f16x8_t vec = vdupq_n_f16(v); \ + \ + for (_w = (COL); _w < _numCols; _w += 8) { \ + f16x8_t tmpa, tmpb; \ + mve_pred16_t p0 = vctp16q(cnt); \ + tmpa = vldrhq_z_f16(&dataA[i * _numCols + _w], p0); \ + tmpb = vldrhq_z_f16(&dataB[j * _numCols + _w], p0); \ + tmpa = vfmsq_f16(tmpa, tmpb, vec); \ + vstrhq_p(&dataA[i * _numCols + _w], tmpa, p0); \ + cnt -= 8; \ + } \ + } #else - -#define SWAP_ROWS_F16(A,COL,i,j) \ -{ \ - int32_t _w; \ - float16_t *dataI = (A)->pData; \ - float16_t *dataJ = (A)->pData; \ - const int32_t _numCols = (A)->numCols;\ - const int32_t nb = _numCols-(COL); \ - \ - dataI += i*_numCols + (COL); \ - dataJ += j*_numCols + (COL); \ - \ - for(_w=0;_w < nb; _w++) \ - { \ - float16_t tmp; \ - tmp = *dataI; \ - *dataI++ = *dataJ; \ - *dataJ++ = tmp; \ - } \ -} - -#define SCALE_ROW_F16(A,COL,v,i) \ -{ \ - int32_t _w; \ - float16_t *data = (A)->pData; \ - const int32_t _numCols = (A)->numCols;\ - const int32_t nb = _numCols-(COL); \ - \ - data += i*_numCols + (COL); \ - \ - for(_w=0;_w < nb; _w++) \ - { \ - *data++ *= (_Float16)v; \ - } \ -} - - -#define MAC_ROW_F16(COL,A,i,v,B,j) \ -{ \ - int32_t _w; \ - float16_t *dataA = (A)->pData; \ - float16_t *dataB = (B)->pData; \ - const int32_t _numCols = (A)->numCols; \ - const int32_t nb = _numCols-(COL); \ - \ - dataA += i*_numCols + (COL); \ - dataB += j*_numCols + (COL); \ - \ - for(_w=0;_w < nb; _w++) \ - { \ - *dataA++ += (_Float16)v * (_Float16)*dataB++;\ - } \ -} - -#define MAS_ROW_F16(COL,A,i,v,B,j) \ -{ \ - int32_t _w; \ - float16_t *dataA = (A)->pData; \ - float16_t *dataB = (B)->pData; \ - const int32_t _numCols = (A)->numCols; \ - const int32_t nb = _numCols-(COL); \ - \ - dataA += i*_numCols + (COL); \ - dataB += j*_numCols + (COL); \ - \ - for(_w=0;_w < nb; _w++) \ - { \ - *dataA++ -= (_Float16)v * (_Float16)*dataB++;\ - } \ -} +#define SWAP_ROWS_F16(A, COL, i, j) \ + { \ + int32_t _w; \ + float16_t *dataI = (A)->pData; \ + float16_t *dataJ = (A)->pData; \ + const int32_t _numCols = (A)->numCols; \ + const int32_t nb = _numCols - (COL); \ + \ + dataI += i * _numCols + (COL); \ + dataJ += j * _numCols + (COL); \ + \ + for (_w = 0; _w < nb; _w++) { \ + float16_t tmp; \ + tmp = *dataI; \ + *dataI++ = *dataJ; \ + *dataJ++ = tmp; \ + } \ + } + +#define SCALE_ROW_F16(A, COL, v, i) \ + { \ + int32_t _w; \ + float16_t *data = (A)->pData; \ + const int32_t _numCols = (A)->numCols; \ + const int32_t nb = _numCols - (COL); \ + \ + data += i * _numCols + (COL); \ + \ + for (_w = 0; _w < nb; _w++) { \ + *data++ *= (_Float16)v; \ + } \ + } + +#define MAC_ROW_F16(COL, A, i, v, B, j) \ + { \ + int32_t _w; \ + float16_t *dataA = (A)->pData; \ + float16_t *dataB = (B)->pData; \ + const int32_t _numCols = (A)->numCols; \ + const int32_t nb = _numCols - (COL); \ + \ + dataA += i * _numCols + (COL); \ + dataB += j * _numCols + (COL); \ + \ + for (_w = 0; _w < nb; _w++) { \ + *dataA++ += (_Float16)v * (_Float16)*dataB++; \ + } \ + } + +#define MAS_ROW_F16(COL, A, i, v, B, j) \ + { \ + int32_t _w; \ + float16_t *dataA = (A)->pData; \ + float16_t *dataB = (B)->pData; \ + const int32_t _numCols = (A)->numCols; \ + const int32_t nb = _numCols - (COL); \ + \ + dataA += i * _numCols + (COL); \ + dataB += j * _numCols + (COL); \ + \ + for (_w = 0; _w < nb; _w++) { \ + *dataA++ -= (_Float16)v * (_Float16)*dataB++; \ + } \ + } #endif /*defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE)*/ /* Functions with only a scalar version */ -#define COPY_COL_F16(A,ROW,COL,DST) \ - COPY_COL_T(float16_t,A,ROW,COL,DST) +#define COPY_COL_F16(A, ROW, COL, DST) COPY_COL_T(float16_t, A, ROW, COL, DST) + +#define SCALE_COL_F16(A, ROW, v, i) SCALE_COL_T(float16_t, (_Float16), A, ROW, v, i) -#define SCALE_COL_F16(A,ROW,v,i) \ - SCALE_COL_T(float16_t,(_Float16),A,ROW,v,i) - #endif /* defined(ARM_FLOAT16_SUPPORTED)*/ #if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) -#define SWAP_ROWS_F32(A,COL,i,j) \ - { \ - int cnt = ((A)->numCols)-(COL); \ - float32_t *data = (A)->pData; \ - const int32_t _numCols = (A)->numCols; \ - int32_t _w; \ - \ - for(_w=(COL);_w < _numCols; _w+=4) \ - { \ - f32x4_t tmpa,tmpb; \ - mve_pred16_t p0 = vctp32q(cnt); \ - \ - tmpa=vldrwq_z_f32(&data[i*_numCols + _w],p0);\ - tmpb=vldrwq_z_f32(&data[j*_numCols + _w],p0);\ - \ - vstrwq_p(&data[i*_numCols + _w], tmpb, p0); \ - vstrwq_p(&data[j*_numCols + _w], tmpa, p0); \ - \ - cnt -= 4; \ - } \ - } - -#define MAC_ROW_F32(COL,A,i,v,B,j) \ -{ \ - int cnt = ((A)->numCols)-(COL); \ - float32_t *dataA = (A)->pData; \ - float32_t *dataB = (B)->pData; \ - const int32_t _numCols = (A)->numCols; \ - int32_t _w; \ - \ - for(_w=(COL);_w < _numCols; _w+=4) \ - { \ - f32x4_t tmpa,tmpb; \ - mve_pred16_t p0 = vctp32q(cnt); \ - tmpa = vldrwq_z_f32(&dataA[i*_numCols + _w],p0);\ - tmpb = vldrwq_z_f32(&dataB[j*_numCols + _w],p0);\ - tmpa = vfmaq_n_f32(tmpa,tmpb,v); \ - vstrwq_p(&dataA[i*_numCols + _w], tmpa, p0); \ - cnt -= 4; \ - } \ - \ -} - -#define MAS_ROW_F32(COL,A,i,v,B,j) \ -{ \ - int cnt = ((A)->numCols)-(COL); \ - float32_t *dataA = (A)->pData; \ - float32_t *dataB = (B)->pData; \ - const int32_t _numCols = (A)->numCols; \ - int32_t _w; \ - f32x4_t vec=vdupq_n_f32(v); \ - \ - for(_w=(COL);_w < _numCols; _w+=4) \ - { \ - f32x4_t tmpa,tmpb; \ - mve_pred16_t p0 = vctp32q(cnt); \ - tmpa = vldrwq_z_f32(&dataA[i*_numCols + _w],p0);\ - tmpb = vldrwq_z_f32(&dataB[j*_numCols + _w],p0);\ - tmpa = vfmsq_f32(tmpa,tmpb,vec); \ - vstrwq_p(&dataA[i*_numCols + _w], tmpa, p0); \ - cnt -= 4; \ - } \ - \ -} - -#define SCALE_ROW_F32(A,COL,v,i) \ -{ \ - int cnt = ((A)->numCols)-(COL); \ - float32_t *data = (A)->pData; \ - const int32_t _numCols = (A)->numCols; \ - int32_t _w; \ - \ - for(_w=(COL);_w < _numCols; _w+=4) \ - { \ - f32x4_t tmpa; \ - mve_pred16_t p0 = vctp32q(cnt); \ - tmpa = vldrwq_z_f32(&data[i*_numCols + _w],p0);\ - tmpa = vmulq_n_f32(tmpa,v); \ - vstrwq_p(&data[i*_numCols + _w], tmpa, p0); \ - cnt -= 4; \ - } \ - \ -} +#define SWAP_ROWS_F32(A, COL, i, j) \ + { \ + int cnt = ((A)->numCols) - (COL); \ + float32_t *data = (A)->pData; \ + const int32_t _numCols = (A)->numCols; \ + int32_t _w; \ + \ + for (_w = (COL); _w < _numCols; _w += 4) { \ + f32x4_t tmpa, tmpb; \ + mve_pred16_t p0 = vctp32q(cnt); \ + \ + tmpa = vldrwq_z_f32(&data[i * _numCols + _w], p0); \ + tmpb = vldrwq_z_f32(&data[j * _numCols + _w], p0); \ + \ + vstrwq_p(&data[i * _numCols + _w], tmpb, p0); \ + vstrwq_p(&data[j * _numCols + _w], tmpa, p0); \ + \ + cnt -= 4; \ + } \ + } + +#define MAC_ROW_F32(COL, A, i, v, B, j) \ + { \ + int cnt = ((A)->numCols) - (COL); \ + float32_t *dataA = (A)->pData; \ + float32_t *dataB = (B)->pData; \ + const int32_t _numCols = (A)->numCols; \ + int32_t _w; \ + \ + for (_w = (COL); _w < _numCols; _w += 4) { \ + f32x4_t tmpa, tmpb; \ + mve_pred16_t p0 = vctp32q(cnt); \ + tmpa = vldrwq_z_f32(&dataA[i * _numCols + _w], p0); \ + tmpb = vldrwq_z_f32(&dataB[j * _numCols + _w], p0); \ + tmpa = vfmaq_n_f32(tmpa, tmpb, v); \ + vstrwq_p(&dataA[i * _numCols + _w], tmpa, p0); \ + cnt -= 4; \ + } \ + } + +#define MAS_ROW_F32(COL, A, i, v, B, j) \ + { \ + int cnt = ((A)->numCols) - (COL); \ + float32_t *dataA = (A)->pData; \ + float32_t *dataB = (B)->pData; \ + const int32_t _numCols = (A)->numCols; \ + int32_t _w; \ + f32x4_t vec = vdupq_n_f32(v); \ + \ + for (_w = (COL); _w < _numCols; _w += 4) { \ + f32x4_t tmpa, tmpb; \ + mve_pred16_t p0 = vctp32q(cnt); \ + tmpa = vldrwq_z_f32(&dataA[i * _numCols + _w], p0); \ + tmpb = vldrwq_z_f32(&dataB[j * _numCols + _w], p0); \ + tmpa = vfmsq_f32(tmpa, tmpb, vec); \ + vstrwq_p(&dataA[i * _numCols + _w], tmpa, p0); \ + cnt -= 4; \ + } \ + } + +#define SCALE_ROW_F32(A, COL, v, i) \ + { \ + int cnt = ((A)->numCols) - (COL); \ + float32_t *data = (A)->pData; \ + const int32_t _numCols = (A)->numCols; \ + int32_t _w; \ + \ + for (_w = (COL); _w < _numCols; _w += 4) { \ + f32x4_t tmpa; \ + mve_pred16_t p0 = vctp32q(cnt); \ + tmpa = vldrwq_z_f32(&data[i * _numCols + _w], p0); \ + tmpa = vmulq_n_f32(tmpa, v); \ + vstrwq_p(&data[i * _numCols + _w], tmpa, p0); \ + cnt -= 4; \ + } \ + } #elif defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) -#define SWAP_ROWS_F32(A,COL,i,j) \ -{ \ - int32_t _w; \ - float32_t *dataI = (A)->pData; \ - float32_t *dataJ = (A)->pData; \ - const int32_t _numCols = (A)->numCols;\ - const int32_t nb = _numCols - COL; \ - \ - dataI += i*_numCols + (COL); \ - dataJ += j*_numCols + (COL); \ - \ - float32_t tmp; \ - \ - for(_w=0;_w < nb; _w++) \ - { \ - tmp = *dataI; \ - *dataI++ = *dataJ; \ - *dataJ++ = tmp; \ - } \ -} - -#define MAC_ROW_F32(COL,A,i,v,B,j) \ -{ \ - float32_t *dataA = (A)->pData; \ - float32_t *dataB = (B)->pData; \ - const int32_t _numCols = (A)->numCols;\ - const int32_t nb = _numCols - (COL); \ - int32_t nbElems; \ - f32x4_t vec = vdupq_n_f32(v); \ - \ - nbElems = nb >> 2; \ - \ - dataA += i*_numCols + (COL); \ - dataB += j*_numCols + (COL); \ - \ - while(nbElems>0) \ - { \ - f32x4_t tmpa,tmpb; \ - tmpa = vld1q_f32(dataA,p0); \ - tmpb = vld1q_f32(dataB,p0); \ - tmpa = vmlaq_f32(tmpa,tmpb,vec);\ - vst1q_f32(dataA, tmpa, p0); \ - nbElems--; \ - dataA += 4; \ - dataB += 4; \ - } \ - \ - nbElems = nb & 3; \ - while(nbElems > 0) \ - { \ - *dataA++ += v* *dataB++; \ - nbElems--; \ - } \ -} - -#define MAS_ROW_F32(COL,A,i,v,B,j) \ -{ \ - float32_t *dataA = (A)->pData; \ - float32_t *dataB = (B)->pData; \ - const int32_t _numCols = (A)->numCols;\ - const int32_t nb = _numCols - (COL); \ - int32_t nbElems; \ - f32x4_t vec = vdupq_n_f32(v); \ - \ - nbElems = nb >> 2; \ - \ - dataA += i*_numCols + (COL); \ - dataB += j*_numCols + (COL); \ - \ - while(nbElems>0) \ - { \ - f32x4_t tmpa,tmpb; \ - tmpa = vld1q_f32(dataA); \ - tmpb = vld1q_f32(dataB); \ - tmpa = vmlsq_f32(tmpa,tmpb,vec);\ - vst1q_f32(dataA, tmpa); \ - nbElems--; \ - dataA += 4; \ - dataB += 4; \ - } \ - \ - nbElems = nb & 3; \ - while(nbElems > 0) \ - { \ - *dataA++ -= v* *dataB++; \ - nbElems--; \ - } \ -} - -#define SCALE_ROW_F32(A,COL,v,i) \ -{ \ - float32_t *data = (A)->pData; \ - const int32_t _numCols = (A)->numCols; \ - const int32_t nb = _numCols - (COL); \ - int32_t nbElems; \ - f32x4_t vec = vdupq_n_f32(v); \ - \ - nbElems = nb >> 2; \ - \ - data += i*_numCols + (COL); \ - while(nbElems>0) \ - { \ - f32x4_t tmpa; \ - tmpa = vld1q_f32(data); \ - tmpa = vmulq_f32(tmpa,vec); \ - vst1q_f32(data, tmpa); \ - data += 4; \ - nbElems --; \ - } \ - \ - nbElems = nb & 3; \ - while(nbElems > 0) \ - { \ - *data++ *= v; \ - nbElems--; \ - } \ - \ -} +#define SWAP_ROWS_F32(A, COL, i, j) \ + { \ + int32_t _w; \ + float32_t *dataI = (A)->pData; \ + float32_t *dataJ = (A)->pData; \ + const int32_t _numCols = (A)->numCols; \ + const int32_t nb = _numCols - COL; \ + \ + dataI += i * _numCols + (COL); \ + dataJ += j * _numCols + (COL); \ + \ + float32_t tmp; \ + \ + for (_w = 0; _w < nb; _w++) { \ + tmp = *dataI; \ + *dataI++ = *dataJ; \ + *dataJ++ = tmp; \ + } \ + } + +#define MAC_ROW_F32(COL, A, i, v, B, j) \ + { \ + float32_t *dataA = (A)->pData; \ + float32_t *dataB = (B)->pData; \ + const int32_t _numCols = (A)->numCols; \ + const int32_t nb = _numCols - (COL); \ + int32_t nbElems; \ + f32x4_t vec = vdupq_n_f32(v); \ + \ + nbElems = nb >> 2; \ + \ + dataA += i * _numCols + (COL); \ + dataB += j * _numCols + (COL); \ + \ + while (nbElems > 0) { \ + f32x4_t tmpa, tmpb; \ + tmpa = vld1q_f32(dataA, p0); \ + tmpb = vld1q_f32(dataB, p0); \ + tmpa = vmlaq_f32(tmpa, tmpb, vec); \ + vst1q_f32(dataA, tmpa, p0); \ + nbElems--; \ + dataA += 4; \ + dataB += 4; \ + } \ + \ + nbElems = nb & 3; \ + while (nbElems > 0) { \ + *dataA++ += v * *dataB++; \ + nbElems--; \ + } \ + } + +#define MAS_ROW_F32(COL, A, i, v, B, j) \ + { \ + float32_t *dataA = (A)->pData; \ + float32_t *dataB = (B)->pData; \ + const int32_t _numCols = (A)->numCols; \ + const int32_t nb = _numCols - (COL); \ + int32_t nbElems; \ + f32x4_t vec = vdupq_n_f32(v); \ + \ + nbElems = nb >> 2; \ + \ + dataA += i * _numCols + (COL); \ + dataB += j * _numCols + (COL); \ + \ + while (nbElems > 0) { \ + f32x4_t tmpa, tmpb; \ + tmpa = vld1q_f32(dataA); \ + tmpb = vld1q_f32(dataB); \ + tmpa = vmlsq_f32(tmpa, tmpb, vec); \ + vst1q_f32(dataA, tmpa); \ + nbElems--; \ + dataA += 4; \ + dataB += 4; \ + } \ + \ + nbElems = nb & 3; \ + while (nbElems > 0) { \ + *dataA++ -= v * *dataB++; \ + nbElems--; \ + } \ + } + +#define SCALE_ROW_F32(A, COL, v, i) \ + { \ + float32_t *data = (A)->pData; \ + const int32_t _numCols = (A)->numCols; \ + const int32_t nb = _numCols - (COL); \ + int32_t nbElems; \ + f32x4_t vec = vdupq_n_f32(v); \ + \ + nbElems = nb >> 2; \ + \ + data += i * _numCols + (COL); \ + while (nbElems > 0) { \ + f32x4_t tmpa; \ + tmpa = vld1q_f32(data); \ + tmpa = vmulq_f32(tmpa, vec); \ + vst1q_f32(data, tmpa); \ + data += 4; \ + nbElems--; \ + } \ + \ + nbElems = nb & 3; \ + while (nbElems > 0) { \ + *data++ *= v; \ + nbElems--; \ + } \ + } #else -#define SWAP_ROWS_F32(A,COL,i,j) \ -{ \ - int32_t _w; \ - float32_t tmp; \ - float32_t *dataI = (A)->pData; \ - float32_t *dataJ = (A)->pData; \ - const int32_t _numCols = (A)->numCols;\ - const int32_t nb = _numCols - COL; \ - \ - dataI += i*_numCols + (COL); \ - dataJ += j*_numCols + (COL); \ - \ - \ - for(_w=0;_w < nb; _w++) \ - { \ - tmp = *dataI; \ - *dataI++ = *dataJ; \ - *dataJ++ = tmp; \ - } \ -} - -#define SCALE_ROW_F32(A,COL,v,i) \ -{ \ - int32_t _w; \ - float32_t *data = (A)->pData; \ - const int32_t _numCols = (A)->numCols;\ - const int32_t nb = _numCols - COL; \ - \ - data += i*_numCols + (COL); \ - \ - for(_w=0;_w < nb; _w++) \ - { \ - *data++ *= v; \ - } \ -} - - -#define MAC_ROW_F32(COL,A,i,v,B,j) \ -{ \ - int32_t _w; \ - float32_t *dataA = (A)->pData; \ - float32_t *dataB = (B)->pData; \ - const int32_t _numCols = (A)->numCols;\ - const int32_t nb = _numCols-(COL); \ - \ - dataA = dataA + i*_numCols + (COL); \ - dataB = dataB + j*_numCols + (COL); \ - \ - for(_w=0;_w < nb; _w++) \ - { \ - *dataA++ += v* *dataB++; \ - } \ -} - -#define MAS_ROW_F32(COL,A,i,v,B,j) \ -{ \ - int32_t _w; \ - float32_t *dataA = (A)->pData; \ - float32_t *dataB = (B)->pData; \ - const int32_t _numCols = (A)->numCols;\ - const int32_t nb = _numCols-(COL); \ - \ - dataA = dataA + i*_numCols + (COL); \ - dataB = dataB + j*_numCols + (COL); \ - \ - for(_w=0;_w < nb; _w++) \ - { \ - *dataA++ -= v* *dataB++; \ - } \ -} +#define SWAP_ROWS_F32(A, COL, i, j) \ + { \ + int32_t _w; \ + float32_t tmp; \ + float32_t *dataI = (A)->pData; \ + float32_t *dataJ = (A)->pData; \ + const int32_t _numCols = (A)->numCols; \ + const int32_t nb = _numCols - COL; \ + \ + dataI += i * _numCols + (COL); \ + dataJ += j * _numCols + (COL); \ + \ + for (_w = 0; _w < nb; _w++) { \ + tmp = *dataI; \ + *dataI++ = *dataJ; \ + *dataJ++ = tmp; \ + } \ + } + +#define SCALE_ROW_F32(A, COL, v, i) \ + { \ + int32_t _w; \ + float32_t *data = (A)->pData; \ + const int32_t _numCols = (A)->numCols; \ + const int32_t nb = _numCols - COL; \ + \ + data += i * _numCols + (COL); \ + \ + for (_w = 0; _w < nb; _w++) { \ + *data++ *= v; \ + } \ + } + +#define MAC_ROW_F32(COL, A, i, v, B, j) \ + { \ + int32_t _w; \ + float32_t *dataA = (A)->pData; \ + float32_t *dataB = (B)->pData; \ + const int32_t _numCols = (A)->numCols; \ + const int32_t nb = _numCols - (COL); \ + \ + dataA = dataA + i * _numCols + (COL); \ + dataB = dataB + j * _numCols + (COL); \ + \ + for (_w = 0; _w < nb; _w++) { \ + *dataA++ += v * *dataB++; \ + } \ + } + +#define MAS_ROW_F32(COL, A, i, v, B, j) \ + { \ + int32_t _w; \ + float32_t *dataA = (A)->pData; \ + float32_t *dataB = (B)->pData; \ + const int32_t _numCols = (A)->numCols; \ + const int32_t nb = _numCols - (COL); \ + \ + dataA = dataA + i * _numCols + (COL); \ + dataB = dataB + j * _numCols + (COL); \ + \ + for (_w = 0; _w < nb; _w++) { \ + *dataA++ -= v * *dataB++; \ + } \ + } #endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ - /* Functions _with only a scalar version */ -#define COPY_COL_F32(A,ROW,COL,DST) \ - COPY_COL_T(float32_t,A,ROW,COL,DST) - -#define COPY_COL_F64(A,ROW,COL,DST) \ - COPY_COL_T(float64_t,A,ROW,COL,DST) - -#define SWAP_COLS_F32(A,COL,i,j) \ -{ \ - int32_t _w; \ - float32_t *data = (A)->pData; \ - const int32_t _numCols = (A)->numCols; \ - for(_w=(COL);_w < _numCols; _w++) \ - { \ - float32_t tmp; \ - tmp = data[_w*_numCols + i]; \ - data[_w*_numCols + i] = data[_w*_numCols + j];\ - data[_w*_numCols + j] = tmp; \ - } \ -} - -#define SCALE_COL_F32(A,ROW,v,i) \ - SCALE_COL_T(float32_t,,A,ROW,v,i) - -#define SWAP_ROWS_F64(A,COL,i,j) \ -{ \ - int32_t _w; \ - float64_t *dataI = (A)->pData; \ - float64_t *dataJ = (A)->pData; \ - const int32_t _numCols = (A)->numCols;\ - const int32_t nb = _numCols-(COL); \ - \ - dataI += i*_numCols + (COL); \ - dataJ += j*_numCols + (COL); \ - \ - for(_w=0;_w < nb; _w++) \ - { \ - float64_t tmp; \ - tmp = *dataI; \ - *dataI++ = *dataJ; \ - *dataJ++ = tmp; \ - } \ -} - -#define SWAP_COLS_F64(A,COL,i,j) \ -{ \ - int32_t _w; \ - float64_t *data = (A)->pData; \ - const int32_t _numCols = (A)->numCols; \ - for(_w=(COL);_w < _numCols; _w++) \ - { \ - float64_t tmp; \ - tmp = data[_w*_numCols + i]; \ - data[_w*_numCols + i] = data[_w*_numCols + j];\ - data[_w*_numCols + j] = tmp; \ - } \ -} - -#define SCALE_ROW_F64(A,COL,v,i) \ -{ \ - int32_t _w; \ - float64_t *data = (A)->pData; \ - const int32_t _numCols = (A)->numCols;\ - const int32_t nb = _numCols-(COL); \ - \ - data += i*_numCols + (COL); \ - \ - for(_w=0;_w < nb; _w++) \ - { \ - *data++ *= v; \ - } \ -} - -#define SCALE_COL_F64(A,ROW,v,i) \ - SCALE_COL_T(float64_t,,A,ROW,v,i) - -#define MAC_ROW_F64(COL,A,i,v,B,j) \ -{ \ - int32_t _w; \ - float64_t *dataA = (A)->pData; \ - float64_t *dataB = (B)->pData; \ - const int32_t _numCols = (A)->numCols;\ - const int32_t nb = _numCols-(COL); \ - \ - dataA += i*_numCols + (COL); \ - dataB += j*_numCols + (COL); \ - \ - for(_w=0;_w < nb; _w++) \ - { \ - *dataA++ += v* *dataB++; \ - } \ -} - -#define MAS_ROW_F64(COL,A,i,v,B,j) \ -{ \ - int32_t _w; \ - float64_t *dataA = (A)->pData; \ - float64_t *dataB = (B)->pData; \ - const int32_t _numCols = (A)->numCols;\ - const int32_t nb = _numCols-(COL); \ - \ - dataA += i*_numCols + (COL); \ - dataB += j*_numCols + (COL); \ - \ - for(_w=0;_w < nb; _w++) \ - { \ - *dataA++ -= v* *dataB++; \ - } \ -} - -#ifdef __cplusplus +#define COPY_COL_F32(A, ROW, COL, DST) COPY_COL_T(float32_t, A, ROW, COL, DST) + +#define COPY_COL_F64(A, ROW, COL, DST) COPY_COL_T(float64_t, A, ROW, COL, DST) + +#define SWAP_COLS_F32(A, COL, i, j) \ + { \ + int32_t _w; \ + float32_t *data = (A)->pData; \ + const int32_t _numCols = (A)->numCols; \ + for (_w = (COL); _w < _numCols; _w++) { \ + float32_t tmp; \ + tmp = data[_w * _numCols + i]; \ + data[_w * _numCols + i] = data[_w * _numCols + j]; \ + data[_w * _numCols + j] = tmp; \ + } \ + } + +#define SCALE_COL_F32(A, ROW, v, i) SCALE_COL_T(float32_t, , A, ROW, v, i) + +#define SWAP_ROWS_F64(A, COL, i, j) \ + { \ + int32_t _w; \ + float64_t *dataI = (A)->pData; \ + float64_t *dataJ = (A)->pData; \ + const int32_t _numCols = (A)->numCols; \ + const int32_t nb = _numCols - (COL); \ + \ + dataI += i * _numCols + (COL); \ + dataJ += j * _numCols + (COL); \ + \ + for (_w = 0; _w < nb; _w++) { \ + float64_t tmp; \ + tmp = *dataI; \ + *dataI++ = *dataJ; \ + *dataJ++ = tmp; \ + } \ + } + +#define SWAP_COLS_F64(A, COL, i, j) \ + { \ + int32_t _w; \ + float64_t *data = (A)->pData; \ + const int32_t _numCols = (A)->numCols; \ + for (_w = (COL); _w < _numCols; _w++) { \ + float64_t tmp; \ + tmp = data[_w * _numCols + i]; \ + data[_w * _numCols + i] = data[_w * _numCols + j]; \ + data[_w * _numCols + j] = tmp; \ + } \ + } + +#define SCALE_ROW_F64(A, COL, v, i) \ + { \ + int32_t _w; \ + float64_t *data = (A)->pData; \ + const int32_t _numCols = (A)->numCols; \ + const int32_t nb = _numCols - (COL); \ + \ + data += i * _numCols + (COL); \ + \ + for (_w = 0; _w < nb; _w++) { \ + *data++ *= v; \ + } \ + } + +#define SCALE_COL_F64(A, ROW, v, i) SCALE_COL_T(float64_t, , A, ROW, v, i) + +#define MAC_ROW_F64(COL, A, i, v, B, j) \ + { \ + int32_t _w; \ + float64_t *dataA = (A)->pData; \ + float64_t *dataB = (B)->pData; \ + const int32_t _numCols = (A)->numCols; \ + const int32_t nb = _numCols - (COL); \ + \ + dataA += i * _numCols + (COL); \ + dataB += j * _numCols + (COL); \ + \ + for (_w = 0; _w < nb; _w++) { \ + *dataA++ += v * *dataB++; \ + } \ + } + +#define MAS_ROW_F64(COL, A, i, v, B, j) \ + { \ + int32_t _w; \ + float64_t *dataA = (A)->pData; \ + float64_t *dataB = (B)->pData; \ + const int32_t _numCols = (A)->numCols; \ + const int32_t nb = _numCols - (COL); \ + \ + dataA += i * _numCols + (COL); \ + dataB += j * _numCols + (COL); \ + \ + for (_w = 0; _w < nb; _w++) { \ + *dataA++ -= v * *dataB++; \ + } \ + } + +#ifdef __cplusplus } #endif diff --git a/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/none.h b/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/none.h old mode 100755 new mode 100644 index 7551ee95ed8..910ed2b6f28 --- a/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/none.h +++ b/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/none.h @@ -33,19 +33,16 @@ But those are not always available or use a restricted set of intrinsics. */ - + #ifndef NONE_H_ #define NONE_H_ #include "arm_math_types.h" -#ifdef __cplusplus -extern "C" -{ +#ifdef __cplusplus +extern "C" { #endif - - /* Normally those kind of definitions are in a compiler file @@ -59,58 +56,51 @@ MSVC is not going to be used to cross-compile to ARM. So, having a MSVC compiler file in Core or Core_A would not make sense. */ -#if defined ( _MSC_VER ) || defined(__GNUC_PYTHON__) || defined(__APPLE_CC__) - __STATIC_FORCEINLINE uint8_t __CLZ(uint32_t data) - { - if (data == 0U) { return 32U; } +#if defined(_MSC_VER) || defined(__GNUC_PYTHON__) || defined(__APPLE_CC__) +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t data) +{ + if (data == 0U) { + return 32U; + } - uint32_t count = 0U; - uint32_t mask = 0x80000000U; + uint32_t count = 0U; + uint32_t mask = 0x80000000U; - while ((data & mask) == 0U) - { + while ((data & mask) == 0U) { count += 1U; mask = mask >> 1U; - } - return count; } + return count; +} - __STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) - { - if ((sat >= 1U) && (sat <= 32U)) - { - const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); - const int32_t min = -1 - max ; - if (val > max) - { - return max; - } - else if (val < min) - { - return min; - } +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max; + if (val > max) { + return max; + } else if (val < min) { + return min; + } } return val; - } - - __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) - { - if (sat <= 31U) - { - const uint32_t max = ((1U << sat) - 1U); - if (val > (int32_t)max) - { - return max; - } - else if (val < 0) - { - return 0U; - } +} + +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) { + return max; + } else if (val < 0) { + return 0U; + } } return (uint32_t)val; - } +} - /** +/** \brief Rotate Right in unsigned value (32 bit) \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. \param [in] op1 Value to rotate @@ -119,457 +109,362 @@ compiler file in Core or Core_A would not make sense. */ __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) { - op2 %= 32U; - if (op2 == 0U) - { - return op1; - } - return (op1 >> op2) | (op1 << (32U - op2)); + op2 %= 32U; + if (op2 == 0U) { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); } - #endif /** * @brief Clips Q63 to Q31 values. */ - __STATIC_FORCEINLINE q31_t clip_q63_to_q31( - q63_t x) - { - return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? - ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; - } - - /** +__STATIC_FORCEINLINE q31_t clip_q63_to_q31(q63_t x) +{ + return ((q31_t)(x >> 32) != ((q31_t)x >> 31)) ? ((0x7FFFFFFF ^ ((q31_t)(x >> 63)))) : (q31_t)x; +} + +/** * @brief Clips Q63 to Q15 values. */ - __STATIC_FORCEINLINE q15_t clip_q63_to_q15( - q63_t x) - { - return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? - ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); - } - - /** +__STATIC_FORCEINLINE q15_t clip_q63_to_q15(q63_t x) +{ + return ((q31_t)(x >> 32) != ((q31_t)x >> 31)) ? ((0x7FFF ^ ((q15_t)(x >> 63)))) : + (q15_t)(x >> 15); +} + +/** * @brief Clips Q31 to Q7 values. */ - __STATIC_FORCEINLINE q7_t clip_q31_to_q7( - q31_t x) - { - return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? - ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; - } - - /** +__STATIC_FORCEINLINE q7_t clip_q31_to_q7(q31_t x) +{ + return ((q31_t)(x >> 24) != ((q31_t)x >> 23)) ? ((0x7F ^ ((q7_t)(x >> 31)))) : (q7_t)x; +} + +/** * @brief Clips Q31 to Q15 values. */ - __STATIC_FORCEINLINE q15_t clip_q31_to_q15( - q31_t x) - { - return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? - ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; - } - - /** +__STATIC_FORCEINLINE q15_t clip_q31_to_q15(q31_t x) +{ + return ((q31_t)(x >> 16) != ((q31_t)x >> 15)) ? ((0x7FFF ^ ((q15_t)(x >> 31)))) : (q15_t)x; +} + +/** * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. */ - __STATIC_FORCEINLINE q63_t mult32x64( - q63_t x, - q31_t y) - { - return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + - (((q63_t) (x >> 32) * y) ) ); - } +__STATIC_FORCEINLINE q63_t mult32x64(q63_t x, q31_t y) +{ + return ((((q63_t)(x & 0x00000000FFFFFFFF) * y) >> 32) + (((q63_t)(x >> 32) * y))); +} /* SMMLAR */ #define multAcc_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32) + a = (q31_t)(((((q63_t)a) << 32) + ((q63_t)x * y) + 0x80000000LL) >> 32) /* SMMLSR */ #define multSub_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32) + a = (q31_t)(((((q63_t)a) << 32) - ((q63_t)x * y) + 0x80000000LL) >> 32) /* SMMULR */ -#define mult_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32) +#define mult_32x32_keep32_R(a, x, y) a = (q31_t)(((q63_t)x * y + 0x80000000LL) >> 32) /* SMMLA */ -#define multAcc_32x32_keep32(a, x, y) \ - a += (q31_t) (((q63_t) x * y) >> 32) +#define multAcc_32x32_keep32(a, x, y) a += (q31_t)(((q63_t)x * y) >> 32) /* SMMLS */ -#define multSub_32x32_keep32(a, x, y) \ - a -= (q31_t) (((q63_t) x * y) >> 32) +#define multSub_32x32_keep32(a, x, y) a -= (q31_t)(((q63_t)x * y) >> 32) /* SMMUL */ -#define mult_32x32_keep32(a, x, y) \ - a = (q31_t) (((q63_t) x * y ) >> 32) +#define mult_32x32_keep32(a, x, y) a = (q31_t)(((q63_t)x * y) >> 32) #ifndef ARM_MATH_DSP - /** +/** * @brief definition to pack two 16 bit values. */ - #define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ - (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) - #define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ - (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) +#define __PKHBT(ARG1, ARG2, ARG3) \ + ((((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ + (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000)) +#define __PKHTB(ARG1, ARG2, ARG3) \ + ((((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ + (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF)) #endif - /** +/** * @brief definition to pack four 8 bit values. */ #ifndef ARM_MATH_BIG_ENDIAN - #define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ - (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ - (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ - (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) +#define __PACKq7(v0, v1, v2, v3) \ + ((((int32_t)(v0) << 0) & (int32_t)0x000000FF) | (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v3) << 24) & (int32_t)0xFF000000)) #else - #define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ - (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ - (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ - (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) +#define __PACKq7(v0, v1, v2, v3) \ + ((((int32_t)(v3) << 0) & (int32_t)0x000000FF) | (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v0) << 24) & (int32_t)0xFF000000)) #endif - - - /* * @brief C custom defined intrinsic functions */ -#if !defined (ARM_MATH_DSP) +#if !defined(ARM_MATH_DSP) - - /* +/* * @brief C custom defined QADD8 */ - __STATIC_FORCEINLINE uint32_t __QADD8( - uint32_t x, - uint32_t y) - { +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t x, uint32_t y) +{ q31_t r, s, t, u; r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; - t = __SSAT(((((q31_t)x << 8) >> 24) + (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; - u = __SSAT(((((q31_t)x ) >> 24) + (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; - - return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); - } + t = __SSAT(((((q31_t)x << 8) >> 24) + (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((q31_t)x) >> 24) + (((q31_t)y) >> 24)), 8) & (int32_t)0x000000FF; + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r))); +} - /* +/* * @brief C custom defined QSUB8 */ - __STATIC_FORCEINLINE uint32_t __QSUB8( - uint32_t x, - uint32_t y) - { +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t x, uint32_t y) +{ q31_t r, s, t, u; r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; - t = __SSAT(((((q31_t)x << 8) >> 24) - (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; - u = __SSAT(((((q31_t)x ) >> 24) - (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; - - return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); - } + t = __SSAT(((((q31_t)x << 8) >> 24) - (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((q31_t)x) >> 24) - (((q31_t)y) >> 24)), 8) & (int32_t)0x000000FF; + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r))); +} - /* +/* * @brief C custom defined QADD16 */ - __STATIC_FORCEINLINE uint32_t __QADD16( - uint32_t x, - uint32_t y) - { -/* q31_t r, s; without initialisation 'arm_offset_q15 test' fails but 'intrinsic' tests pass! for armCC */ +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t x, uint32_t y) +{ + /* q31_t r, s; without initialisation 'arm_offset_q15 test' fails but 'intrinsic' tests pass! for armCC */ q31_t r = 0, s = 0; r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; - s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } + s = __SSAT(((((q31_t)x) >> 16) + (((q31_t)y) >> 16)), 16) & (int32_t)0x0000FFFF; + return ((uint32_t)((s << 16) | (r))); +} - /* +/* * @brief C custom defined SHADD16 */ - __STATIC_FORCEINLINE uint32_t __SHADD16( - uint32_t x, - uint32_t y) - { +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t x, uint32_t y) +{ q31_t r, s; r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; - s = (((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } + s = (((((q31_t)x) >> 16) + (((q31_t)y) >> 16)) >> 1) & (int32_t)0x0000FFFF; + return ((uint32_t)((s << 16) | (r))); +} - /* +/* * @brief C custom defined QSUB16 */ - __STATIC_FORCEINLINE uint32_t __QSUB16( - uint32_t x, - uint32_t y) - { +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t x, uint32_t y) +{ q31_t r, s; r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; - s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } + s = __SSAT(((((q31_t)x) >> 16) - (((q31_t)y) >> 16)), 16) & (int32_t)0x0000FFFF; + return ((uint32_t)((s << 16) | (r))); +} - /* +/* * @brief C custom defined SHSUB16 */ - __STATIC_FORCEINLINE uint32_t __SHSUB16( - uint32_t x, - uint32_t y) - { +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t x, uint32_t y) +{ q31_t r, s; r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; - s = (((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } + s = (((((q31_t)x) >> 16) - (((q31_t)y) >> 16)) >> 1) & (int32_t)0x0000FFFF; + return ((uint32_t)((s << 16) | (r))); +} - /* +/* * @brief C custom defined QASX */ - __STATIC_FORCEINLINE uint32_t __QASX( - uint32_t x, - uint32_t y) - { +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t x, uint32_t y) +{ q31_t r, s; - r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; - s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } + r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + return ((uint32_t)((s << 16) | (r))); +} - /* +/* * @brief C custom defined SHASX */ - __STATIC_FORCEINLINE uint32_t __SHASX( - uint32_t x, - uint32_t y) - { +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t x, uint32_t y) +{ q31_t r, s; - r = (((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; - s = (((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } + r = (((((q31_t)x << 16) >> 16) - (((q31_t)y) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + return ((uint32_t)((s << 16) | (r))); +} - /* +/* * @brief C custom defined QSAX */ - __STATIC_FORCEINLINE uint32_t __QSAX( - uint32_t x, - uint32_t y) - { +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t x, uint32_t y) +{ q31_t r, s; - r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; - s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } + r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + return ((uint32_t)((s << 16) | (r))); +} - /* +/* * @brief C custom defined SHSAX */ - __STATIC_FORCEINLINE uint32_t __SHSAX( - uint32_t x, - uint32_t y) - { +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t x, uint32_t y) +{ q31_t r, s; - r = (((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; - s = (((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } + r = (((((q31_t)x << 16) >> 16) + (((q31_t)y) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + return ((uint32_t)((s << 16) | (r))); +} - /* +/* * @brief C custom defined SMUSDX */ - __STATIC_FORCEINLINE uint32_t __SMUSDX( - uint32_t x, - uint32_t y) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - - ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); - } - - /* +__STATIC_FORCEINLINE uint32_t __SMUSDX(uint32_t x, uint32_t y) +{ + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y) >> 16)) - + ((((q31_t)x) >> 16) * (((q31_t)y << 16) >> 16)))); +} + +/* * @brief C custom defined SMUADX */ - __STATIC_FORCEINLINE uint32_t __SMUADX( - uint32_t x, - uint32_t y) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); - } - +__STATIC_FORCEINLINE uint32_t __SMUADX(uint32_t x, uint32_t y) +{ + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y) >> 16)) + + ((((q31_t)x) >> 16) * (((q31_t)y << 16) >> 16)))); +} - /* +/* * @brief C custom defined QADD */ - __STATIC_FORCEINLINE int32_t __QADD( - int32_t x, - int32_t y) - { +__STATIC_FORCEINLINE int32_t __QADD(int32_t x, int32_t y) +{ return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y))); - } - +} - /* +/* * @brief C custom defined QSUB */ - __STATIC_FORCEINLINE int32_t __QSUB( - int32_t x, - int32_t y) - { +__STATIC_FORCEINLINE int32_t __QSUB(int32_t x, int32_t y) +{ return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y))); - } - +} - /* +/* * @brief C custom defined SMLAD */ - __STATIC_FORCEINLINE uint32_t __SMLAD( - uint32_t x, - uint32_t y, - uint32_t sum) - { +__STATIC_FORCEINLINE uint32_t __SMLAD(uint32_t x, uint32_t y, uint32_t sum) +{ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + - ( ((q31_t)sum ) ) )); - } - + ((((q31_t)x) >> 16) * (((q31_t)y) >> 16)) + (((q31_t)sum)))); +} - /* +/* * @brief C custom defined SMLADX */ - __STATIC_FORCEINLINE uint32_t __SMLADX( - uint32_t x, - uint32_t y, - uint32_t sum) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + - ( ((q31_t)sum ) ) )); - } - - - /* +__STATIC_FORCEINLINE uint32_t __SMLADX(uint32_t x, uint32_t y, uint32_t sum) +{ + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y) >> 16)) + + ((((q31_t)x) >> 16) * (((q31_t)y << 16) >> 16)) + (((q31_t)sum)))); +} + +/* * @brief C custom defined SMLSDX */ - __STATIC_FORCEINLINE uint32_t __SMLSDX( - uint32_t x, - uint32_t y, - uint32_t sum) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - - ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + - ( ((q31_t)sum ) ) )); - } - - - /* +__STATIC_FORCEINLINE uint32_t __SMLSDX(uint32_t x, uint32_t y, uint32_t sum) +{ + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y) >> 16)) - + ((((q31_t)x) >> 16) * (((q31_t)y << 16) >> 16)) + (((q31_t)sum)))); +} + +/* * @brief C custom defined SMLALD */ - __STATIC_FORCEINLINE uint64_t __SMLALD( - uint32_t x, - uint32_t y, - uint64_t sum) - { -/* return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */ +__STATIC_FORCEINLINE uint64_t __SMLALD(uint32_t x, uint32_t y, uint64_t sum) +{ + /* return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */ return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + - ( ((q63_t)sum ) ) )); - } - + ((((q31_t)x) >> 16) * (((q31_t)y) >> 16)) + (((q63_t)sum)))); +} - /* +/* * @brief C custom defined SMLALDX */ - __STATIC_FORCEINLINE uint64_t __SMLALDX( - uint32_t x, - uint32_t y, - uint64_t sum) - { -/* return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */ - return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + - ( ((q63_t)sum ) ) )); - } - - - /* +__STATIC_FORCEINLINE uint64_t __SMLALDX(uint32_t x, uint32_t y, uint64_t sum) +{ + /* return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */ + return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y) >> 16)) + + ((((q31_t)x) >> 16) * (((q31_t)y << 16) >> 16)) + (((q63_t)sum)))); +} + +/* * @brief C custom defined SMUAD */ - __STATIC_FORCEINLINE uint32_t __SMUAD( - uint32_t x, - uint32_t y) - { +__STATIC_FORCEINLINE uint32_t __SMUAD(uint32_t x, uint32_t y) +{ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); - } - + ((((q31_t)x) >> 16) * (((q31_t)y) >> 16)))); +} - /* +/* * @brief C custom defined SMUSD */ - __STATIC_FORCEINLINE uint32_t __SMUSD( - uint32_t x, - uint32_t y) - { +__STATIC_FORCEINLINE uint32_t __SMUSD(uint32_t x, uint32_t y) +{ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) - - ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); - } - + ((((q31_t)x) >> 16) * (((q31_t)y) >> 16)))); +} - /* +/* * @brief C custom defined SXTB16 */ - __STATIC_FORCEINLINE uint32_t __SXTB16( - uint32_t x) - { +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t x) +{ return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) | - ((((q31_t)x << 8) >> 8) & (q31_t)0xFFFF0000) )); - } + ((((q31_t)x << 8) >> 8) & (q31_t)0xFFFF0000))); +} - /* +/* * @brief C custom defined SMMLA */ - __STATIC_FORCEINLINE int32_t __SMMLA( - int32_t x, - int32_t y, - int32_t sum) - { - return (sum + (int32_t) (((int64_t) x * y) >> 32)); - } +__STATIC_FORCEINLINE int32_t __SMMLA(int32_t x, int32_t y, int32_t sum) +{ + return (sum + (int32_t)(((int64_t)x * y) >> 32)); +} #endif /* !defined (ARM_MATH_DSP) */ - -#ifdef __cplusplus +#ifdef __cplusplus } #endif diff --git a/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/quaternion_math_functions.h b/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/quaternion_math_functions.h old mode 100755 new mode 100644 index 6c823a368b6..c8799ad18de --- a/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/quaternion_math_functions.h +++ b/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/quaternion_math_functions.h @@ -24,7 +24,6 @@ * limitations under the License. */ - #ifndef QUATERNION_MATH_FUNCTIONS_H_ #define QUATERNION_MATH_FUNCTIONS_H_ @@ -34,10 +33,8 @@ #include "dsp/none.h" #include "dsp/utils.h" - -#ifdef __cplusplus -extern "C" -{ +#ifdef __cplusplus +extern "C" { #endif /** @@ -46,17 +43,14 @@ extern "C" * rotation and quaternion representation. */ - /** @brief Floating-point quaternion Norm. @param[in] pInputQuaternions points to the input vector of quaternions @param[out] pNorms points to the output vector of norms @param[in] nbQuaternions number of quaternions in each vector */ -void arm_quaternion_norm_f32(const float32_t *pInputQuaternions, - float32_t *pNorms, - uint32_t nbQuaternions); - +void arm_quaternion_norm_f32(const float32_t *pInputQuaternions, float32_t *pNorms, + uint32_t nbQuaternions); /** @brief Floating-point quaternion inverse. @@ -64,10 +58,8 @@ void arm_quaternion_norm_f32(const float32_t *pInputQuaternions, @param[out] pInverseQuaternions points to the output vector of inverse quaternions @param[in] nbQuaternions number of quaternions in each vector */ -void arm_quaternion_inverse_f32(const float32_t *pInputQuaternions, - float32_t *pInverseQuaternions, - uint32_t nbQuaternions); - +void arm_quaternion_inverse_f32(const float32_t *pInputQuaternions, float32_t *pInverseQuaternions, + uint32_t nbQuaternions); /** @brief Floating-point quaternion conjugates. @@ -75,10 +67,8 @@ void arm_quaternion_inverse_f32(const float32_t *pInputQuaternions, @param[out] pConjugateQuaternions points to the output vector of conjugate quaternions @param[in] nbQuaternions number of quaternions in each vector */ -void arm_quaternion_conjugate_f32(const float32_t *inputQuaternions, - float32_t *pConjugateQuaternions, - uint32_t nbQuaternions); - +void arm_quaternion_conjugate_f32(const float32_t *inputQuaternions, + float32_t *pConjugateQuaternions, uint32_t nbQuaternions); /** @brief Floating-point normalization of quaternions. @@ -86,10 +76,8 @@ void arm_quaternion_conjugate_f32(const float32_t *inputQuaternions, @param[out] pNormalizedQuaternions points to the output vector of normalized quaternions @param[in] nbQuaternions number of quaternions in each vector */ -void arm_quaternion_normalize_f32(const float32_t *inputQuaternions, - float32_t *pNormalizedQuaternions, - uint32_t nbQuaternions); - +void arm_quaternion_normalize_f32(const float32_t *inputQuaternions, + float32_t *pNormalizedQuaternions, uint32_t nbQuaternions); /** @brief Floating-point product of two quaternions. @@ -97,10 +85,7 @@ void arm_quaternion_normalize_f32(const float32_t *inputQuaternions, @param[in] qb Second quaternion @param[out] r Product of two quaternions */ -void arm_quaternion_product_single_f32(const float32_t *qa, - const float32_t *qb, - float32_t *r); - +void arm_quaternion_product_single_f32(const float32_t *qa, const float32_t *qb, float32_t *r); /** @brief Floating-point elementwise product two quaternions. @@ -109,11 +94,8 @@ void arm_quaternion_product_single_f32(const float32_t *qa, @param[out] r Elementwise product of quaternions @param[in] nbQuaternions Number of quaternions in the array */ -void arm_quaternion_product_f32(const float32_t *qa, - const float32_t *qb, - float32_t *r, - uint32_t nbQuaternions); - +void arm_quaternion_product_f32(const float32_t *qa, const float32_t *qb, float32_t *r, + uint32_t nbQuaternions); /** * @brief Conversion of quaternion to equivalent rotation matrix. @@ -130,10 +112,8 @@ void arm_quaternion_product_f32(const float32_t *qa, * * Rotation matrix is saved in row order : R00 R01 R02 R10 R11 R12 R20 R21 R22 */ -void arm_quaternion2rotation_f32(const float32_t *pInputQuaternions, - float32_t *pOutputRotations, - uint32_t nbQuaternions); - +void arm_quaternion2rotation_f32(const float32_t *pInputQuaternions, float32_t *pOutputRotations, + uint32_t nbQuaternions); /** * @brief Conversion of a rotation matrix to equivalent quaternion. @@ -141,12 +121,10 @@ void arm_quaternion2rotation_f32(const float32_t *pInputQuaternions, * @param[out] pOutputQuaternions points to an array of quaternions * @param[in] nbQuaternions in the array */ -void arm_rotation2quaternion_f32(const float32_t *pInputRotations, - float32_t *pOutputQuaternions, - uint32_t nbQuaternions); - +void arm_rotation2quaternion_f32(const float32_t *pInputRotations, float32_t *pOutputQuaternions, + uint32_t nbQuaternions); -#ifdef __cplusplus +#ifdef __cplusplus } #endif diff --git a/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/statistics_functions.h b/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/statistics_functions.h old mode 100755 new mode 100644 index 301aadd023c..66a4bb50a9b --- a/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/statistics_functions.h +++ b/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/statistics_functions.h @@ -23,7 +23,6 @@ * limitations under the License. */ - #ifndef STATISTICS_FUNCTIONS_H_ #define STATISTICS_FUNCTIONS_H_ @@ -36,12 +35,10 @@ #include "dsp/basic_math_functions.h" #include "dsp/fast_math_functions.h" -#ifdef __cplusplus -extern "C" -{ +#ifdef __cplusplus +extern "C" { #endif - /** * @defgroup groupStats Statistics Functions */ @@ -70,7 +67,6 @@ extern "C" * */ - float32_t arm_logsumexp_f32(const float32_t *in, uint32_t blockSize); /** @@ -86,11 +82,8 @@ float32_t arm_logsumexp_f32(const float32_t *in, uint32_t blockSize); * */ - -float32_t arm_logsumexp_dot_prod_f32(const float32_t * pSrcA, - const float32_t * pSrcB, - uint32_t blockSize, - float32_t *pTmpBuffer); +float32_t arm_logsumexp_dot_prod_f32(const float32_t *pSrcA, const float32_t *pSrcB, + uint32_t blockSize, float32_t *pTmpBuffer); /** * @brief Entropy @@ -101,9 +94,7 @@ float32_t arm_logsumexp_dot_prod_f32(const float32_t * pSrcA, * */ - -float32_t arm_entropy_f32(const float32_t * pSrcA,uint32_t blockSize); - +float32_t arm_entropy_f32(const float32_t *pSrcA, uint32_t blockSize); /** * @brief Entropy @@ -114,9 +105,7 @@ float32_t arm_entropy_f32(const float32_t * pSrcA,uint32_t blockSize); * */ - -float64_t arm_entropy_f64(const float64_t * pSrcA, uint32_t blockSize); - +float64_t arm_entropy_f64(const float64_t *pSrcA, uint32_t blockSize); /** * @brief Kullback-Leibler @@ -127,10 +116,8 @@ float64_t arm_entropy_f64(const float64_t * pSrcA, uint32_t blockSize); * @return Kullback-Leibler Divergence D(A || B) * */ -float32_t arm_kullback_leibler_f32(const float32_t * pSrcA - ,const float32_t * pSrcB - ,uint32_t blockSize); - +float32_t arm_kullback_leibler_f32(const float32_t *pSrcA, const float32_t *pSrcB, + uint32_t blockSize); /** * @brief Kullback-Leibler @@ -141,314 +128,211 @@ float32_t arm_kullback_leibler_f32(const float32_t * pSrcA * @return Kullback-Leibler Divergence D(A || B) * */ -float64_t arm_kullback_leibler_f64(const float64_t * pSrcA, - const float64_t * pSrcB, - uint32_t blockSize); - +float64_t arm_kullback_leibler_f64(const float64_t *pSrcA, const float64_t *pSrcB, + uint32_t blockSize); - /** +/** * @brief Sum of the squares of the elements of a Q31 vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output value. */ - void arm_power_q31( - const q31_t * pSrc, - uint32_t blockSize, - q63_t * pResult); - +void arm_power_q31(const q31_t *pSrc, uint32_t blockSize, q63_t *pResult); - /** +/** * @brief Sum of the squares of the elements of a floating-point vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output value. */ - void arm_power_f32( - const float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - +void arm_power_f32(const float32_t *pSrc, uint32_t blockSize, float32_t *pResult); - /** +/** * @brief Sum of the squares of the elements of a floating-point vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output value. */ - void arm_power_f64( - const float64_t * pSrc, - uint32_t blockSize, - float64_t * pResult); +void arm_power_f64(const float64_t *pSrc, uint32_t blockSize, float64_t *pResult); - - /** +/** * @brief Sum of the squares of the elements of a Q15 vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output value. */ - void arm_power_q15( - const q15_t * pSrc, - uint32_t blockSize, - q63_t * pResult); - +void arm_power_q15(const q15_t *pSrc, uint32_t blockSize, q63_t *pResult); - /** +/** * @brief Sum of the squares of the elements of a Q7 vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output value. */ - void arm_power_q7( - const q7_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - +void arm_power_q7(const q7_t *pSrc, uint32_t blockSize, q31_t *pResult); - /** +/** * @brief Mean value of a Q7 vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output value. */ - void arm_mean_q7( - const q7_t * pSrc, - uint32_t blockSize, - q7_t * pResult); +void arm_mean_q7(const q7_t *pSrc, uint32_t blockSize, q7_t *pResult); - - /** +/** * @brief Mean value of a Q15 vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output value. */ - void arm_mean_q15( - const q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); +void arm_mean_q15(const q15_t *pSrc, uint32_t blockSize, q15_t *pResult); - - /** +/** * @brief Mean value of a Q31 vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output value. */ - void arm_mean_q31( - const q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - +void arm_mean_q31(const q31_t *pSrc, uint32_t blockSize, q31_t *pResult); - /** +/** * @brief Mean value of a floating-point vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output value. */ - void arm_mean_f32( - const float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - +void arm_mean_f32(const float32_t *pSrc, uint32_t blockSize, float32_t *pResult); - /** +/** * @brief Mean value of a floating-point vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output value. */ - void arm_mean_f64( - const float64_t * pSrc, - uint32_t blockSize, - float64_t * pResult); +void arm_mean_f64(const float64_t *pSrc, uint32_t blockSize, float64_t *pResult); - - /** +/** * @brief Variance of the elements of a floating-point vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output value. */ - void arm_var_f32( - const float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - +void arm_var_f32(const float32_t *pSrc, uint32_t blockSize, float32_t *pResult); - /** +/** * @brief Variance of the elements of a floating-point vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output value. */ - void arm_var_f64( - const float64_t * pSrc, - uint32_t blockSize, - float64_t * pResult); - +void arm_var_f64(const float64_t *pSrc, uint32_t blockSize, float64_t *pResult); - /** +/** * @brief Variance of the elements of a Q31 vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output value. */ - void arm_var_q31( - const q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - +void arm_var_q31(const q31_t *pSrc, uint32_t blockSize, q31_t *pResult); - /** +/** * @brief Variance of the elements of a Q15 vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output value. */ - void arm_var_q15( - const q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); +void arm_var_q15(const q15_t *pSrc, uint32_t blockSize, q15_t *pResult); - - /** +/** * @brief Root Mean Square of the elements of a floating-point vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output value. */ - void arm_rms_f32( - const float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - +void arm_rms_f32(const float32_t *pSrc, uint32_t blockSize, float32_t *pResult); - /** +/** * @brief Root Mean Square of the elements of a Q31 vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output value. */ - void arm_rms_q31( - const q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - +void arm_rms_q31(const q31_t *pSrc, uint32_t blockSize, q31_t *pResult); - /** +/** * @brief Root Mean Square of the elements of a Q15 vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output value. */ - void arm_rms_q15( - const q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); +void arm_rms_q15(const q15_t *pSrc, uint32_t blockSize, q15_t *pResult); - - /** +/** * @brief Standard deviation of the elements of a floating-point vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output value. */ - void arm_std_f32( - const float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); +void arm_std_f32(const float32_t *pSrc, uint32_t blockSize, float32_t *pResult); - - /** +/** * @brief Standard deviation of the elements of a floating-point vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output value. */ - void arm_std_f64( - const float64_t * pSrc, - uint32_t blockSize, - float64_t * pResult); - +void arm_std_f64(const float64_t *pSrc, uint32_t blockSize, float64_t *pResult); - /** +/** * @brief Standard deviation of the elements of a Q31 vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output value. */ - void arm_std_q31( - const q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - +void arm_std_q31(const q31_t *pSrc, uint32_t blockSize, q31_t *pResult); - /** +/** * @brief Standard deviation of the elements of a Q15 vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output value. */ - void arm_std_q15( - const q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); +void arm_std_q15(const q15_t *pSrc, uint32_t blockSize, q15_t *pResult); - - - /** +/** * @brief Minimum value of a Q7 vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output pointer * @param[in] pIndex is the array index of the minimum value in the input buffer. */ - void arm_min_q7( - const q7_t * pSrc, - uint32_t blockSize, - q7_t * pResult, - uint32_t * pIndex); +void arm_min_q7(const q7_t *pSrc, uint32_t blockSize, q7_t *pResult, uint32_t *pIndex); - /** +/** * @brief Minimum value of absolute values of a Q7 vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output pointer * @param[in] pIndex is the array index of the minimum value in the input buffer. */ - void arm_absmin_q7( - const q7_t * pSrc, - uint32_t blockSize, - q7_t * pResult, - uint32_t * pIndex); +void arm_absmin_q7(const q7_t *pSrc, uint32_t blockSize, q7_t *pResult, uint32_t *pIndex); - /** +/** * @brief Minimum value of absolute values of a Q7 vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output pointer */ - void arm_absmin_no_idx_q7( - const q7_t * pSrc, - uint32_t blockSize, - q7_t * pResult); - +void arm_absmin_no_idx_q7(const q7_t *pSrc, uint32_t blockSize, q7_t *pResult); - /** +/** * @brief Minimum value of a Q15 vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output pointer * @param[in] pIndex is the array index of the minimum value in the input buffer. */ - void arm_min_q15( - const q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult, - uint32_t * pIndex); +void arm_min_q15(const q15_t *pSrc, uint32_t blockSize, q15_t *pResult, uint32_t *pIndex); /** * @brief Minimum value of absolute values of a Q15 vector. @@ -457,137 +341,95 @@ float64_t arm_kullback_leibler_f64(const float64_t * pSrcA, * @param[out] pResult is output pointer * @param[in] pIndex is the array index of the minimum value in the input buffer. */ - void arm_absmin_q15( - const q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult, - uint32_t * pIndex); +void arm_absmin_q15(const q15_t *pSrc, uint32_t blockSize, q15_t *pResult, uint32_t *pIndex); - /** +/** * @brief Minimum value of absolute values of a Q15 vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output pointer */ - void arm_absmin_no_idx_q15( - const q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - +void arm_absmin_no_idx_q15(const q15_t *pSrc, uint32_t blockSize, q15_t *pResult); - /** +/** * @brief Minimum value of a Q31 vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output pointer * @param[out] pIndex is the array index of the minimum value in the input buffer. */ - void arm_min_q31( - const q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult, - uint32_t * pIndex); +void arm_min_q31(const q31_t *pSrc, uint32_t blockSize, q31_t *pResult, uint32_t *pIndex); - /** +/** * @brief Minimum value of absolute values of a Q31 vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output pointer * @param[out] pIndex is the array index of the minimum value in the input buffer. */ - void arm_absmin_q31( - const q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult, - uint32_t * pIndex); +void arm_absmin_q31(const q31_t *pSrc, uint32_t blockSize, q31_t *pResult, uint32_t *pIndex); - /** +/** * @brief Minimum value of absolute values of a Q31 vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output pointer */ - void arm_absmin_no_idx_q31( - const q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); +void arm_absmin_no_idx_q31(const q31_t *pSrc, uint32_t blockSize, q31_t *pResult); - - /** +/** * @brief Minimum value of a floating-point vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output pointer * @param[out] pIndex is the array index of the minimum value in the input buffer. */ - void arm_min_f32( - const float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult, - uint32_t * pIndex); +void arm_min_f32(const float32_t *pSrc, uint32_t blockSize, float32_t *pResult, uint32_t *pIndex); - /** +/** * @brief Minimum value of absolute values of a floating-point vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output pointer * @param[out] pIndex is the array index of the minimum value in the input buffer. */ - void arm_absmin_f32( - const float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult, - uint32_t * pIndex); +void arm_absmin_f32(const float32_t *pSrc, uint32_t blockSize, float32_t *pResult, + uint32_t *pIndex); - /** +/** * @brief Minimum value of absolute values of a floating-point vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output pointer */ - void arm_absmin_no_idx_f32( - const float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - +void arm_absmin_no_idx_f32(const float32_t *pSrc, uint32_t blockSize, float32_t *pResult); - /** +/** * @brief Minimum value of a floating-point vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output pointer * @param[out] pIndex is the array index of the minimum value in the input buffer. */ - void arm_min_f64( - const float64_t * pSrc, - uint32_t blockSize, - float64_t * pResult, - uint32_t * pIndex); +void arm_min_f64(const float64_t *pSrc, uint32_t blockSize, float64_t *pResult, uint32_t *pIndex); - /** +/** * @brief Minimum value of absolute values of a floating-point vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output pointer * @param[out] pIndex is the array index of the minimum value in the input buffer. */ - void arm_absmin_f64( - const float64_t * pSrc, - uint32_t blockSize, - float64_t * pResult, - uint32_t * pIndex); +void arm_absmin_f64(const float64_t *pSrc, uint32_t blockSize, float64_t *pResult, + uint32_t *pIndex); - /** +/** * @brief Minimum value of absolute values of a floating-point vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output pointer */ - void arm_absmin_no_idx_f64( - const float64_t * pSrc, - uint32_t blockSize, - float64_t * pResult); - +void arm_absmin_no_idx_f64(const float64_t *pSrc, uint32_t blockSize, float64_t *pResult); /** * @brief Maximum value of a Q7 vector. @@ -596,11 +438,7 @@ float64_t arm_kullback_leibler_f64(const float64_t * pSrcA, * @param[out] pResult maximum value returned here * @param[out] pIndex index of maximum value returned here */ - void arm_max_q7( - const q7_t * pSrc, - uint32_t blockSize, - q7_t * pResult, - uint32_t * pIndex); +void arm_max_q7(const q7_t *pSrc, uint32_t blockSize, q7_t *pResult, uint32_t *pIndex); /** * @brief Maximum value of absolute values of a Q7 vector. @@ -609,11 +447,7 @@ float64_t arm_kullback_leibler_f64(const float64_t * pSrcA, * @param[out] pResult maximum value returned here * @param[out] pIndex index of maximum value returned here */ - void arm_absmax_q7( - const q7_t * pSrc, - uint32_t blockSize, - q7_t * pResult, - uint32_t * pIndex); +void arm_absmax_q7(const q7_t *pSrc, uint32_t blockSize, q7_t *pResult, uint32_t *pIndex); /** * @brief Maximum value of absolute values of a Q7 vector. @@ -621,11 +455,7 @@ float64_t arm_kullback_leibler_f64(const float64_t * pSrcA, * @param[in] blockSize length of the input vector * @param[out] pResult maximum value returned here */ - void arm_absmax_no_idx_q7( - const q7_t * pSrc, - uint32_t blockSize, - q7_t * pResult); - +void arm_absmax_no_idx_q7(const q7_t *pSrc, uint32_t blockSize, q7_t *pResult); /** * @brief Maximum value of a Q15 vector. @@ -634,11 +464,7 @@ float64_t arm_kullback_leibler_f64(const float64_t * pSrcA, * @param[out] pResult maximum value returned here * @param[out] pIndex index of maximum value returned here */ - void arm_max_q15( - const q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult, - uint32_t * pIndex); +void arm_max_q15(const q15_t *pSrc, uint32_t blockSize, q15_t *pResult, uint32_t *pIndex); /** * @brief Maximum value of absolute values of a Q15 vector. @@ -647,22 +473,15 @@ float64_t arm_kullback_leibler_f64(const float64_t * pSrcA, * @param[out] pResult maximum value returned here * @param[out] pIndex index of maximum value returned here */ - void arm_absmax_q15( - const q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult, - uint32_t * pIndex); +void arm_absmax_q15(const q15_t *pSrc, uint32_t blockSize, q15_t *pResult, uint32_t *pIndex); - /** +/** * @brief Maximum value of absolute values of a Q15 vector. * @param[in] pSrc points to the input buffer * @param[in] blockSize length of the input vector * @param[out] pResult maximum value returned here */ - void arm_absmax_no_idx_q15( - const q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); +void arm_absmax_no_idx_q15(const q15_t *pSrc, uint32_t blockSize, q15_t *pResult); /** * @brief Maximum value of a Q31 vector. @@ -671,11 +490,7 @@ float64_t arm_kullback_leibler_f64(const float64_t * pSrcA, * @param[out] pResult maximum value returned here * @param[out] pIndex index of maximum value returned here */ - void arm_max_q31( - const q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult, - uint32_t * pIndex); +void arm_max_q31(const q31_t *pSrc, uint32_t blockSize, q31_t *pResult, uint32_t *pIndex); /** * @brief Maximum value of absolute values of a Q31 vector. @@ -684,22 +499,15 @@ float64_t arm_kullback_leibler_f64(const float64_t * pSrcA, * @param[out] pResult maximum value returned here * @param[out] pIndex index of maximum value returned here */ - void arm_absmax_q31( - const q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult, - uint32_t * pIndex); +void arm_absmax_q31(const q31_t *pSrc, uint32_t blockSize, q31_t *pResult, uint32_t *pIndex); - /** +/** * @brief Maximum value of absolute values of a Q31 vector. * @param[in] pSrc points to the input buffer * @param[in] blockSize length of the input vector * @param[out] pResult maximum value returned here */ - void arm_absmax_no_idx_q31( - const q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); +void arm_absmax_no_idx_q31(const q31_t *pSrc, uint32_t blockSize, q31_t *pResult); /** * @brief Maximum value of a floating-point vector. @@ -708,11 +516,7 @@ float64_t arm_kullback_leibler_f64(const float64_t * pSrcA, * @param[out] pResult maximum value returned here * @param[out] pIndex index of maximum value returned here */ - void arm_max_f32( - const float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult, - uint32_t * pIndex); +void arm_max_f32(const float32_t *pSrc, uint32_t blockSize, float32_t *pResult, uint32_t *pIndex); /** * @brief Maximum value of absolute values of a floating-point vector. @@ -721,22 +525,16 @@ float64_t arm_kullback_leibler_f64(const float64_t * pSrcA, * @param[out] pResult maximum value returned here * @param[out] pIndex index of maximum value returned here */ - void arm_absmax_f32( - const float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult, - uint32_t * pIndex); +void arm_absmax_f32(const float32_t *pSrc, uint32_t blockSize, float32_t *pResult, + uint32_t *pIndex); - /** +/** * @brief Maximum value of absolute values of a floating-point vector. * @param[in] pSrc points to the input buffer * @param[in] blockSize length of the input vector * @param[out] pResult maximum value returned here */ - void arm_absmax_no_idx_f32( - const float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); +void arm_absmax_no_idx_f32(const float32_t *pSrc, uint32_t blockSize, float32_t *pResult); /** * @brief Maximum value of a floating-point vector. @@ -745,11 +543,7 @@ float64_t arm_kullback_leibler_f64(const float64_t * pSrcA, * @param[out] pResult maximum value returned here * @param[out] pIndex index of maximum value returned here */ - void arm_max_f64( - const float64_t * pSrc, - uint32_t blockSize, - float64_t * pResult, - uint32_t * pIndex); +void arm_max_f64(const float64_t *pSrc, uint32_t blockSize, float64_t *pResult, uint32_t *pIndex); /** * @brief Maximum value of absolute values of a floating-point vector. @@ -758,11 +552,8 @@ float64_t arm_kullback_leibler_f64(const float64_t * pSrcA, * @param[out] pResult maximum value returned here * @param[out] pIndex index of maximum value returned here */ - void arm_absmax_f64( - const float64_t * pSrc, - uint32_t blockSize, - float64_t * pResult, - uint32_t * pIndex); +void arm_absmax_f64(const float64_t *pSrc, uint32_t blockSize, float64_t *pResult, + uint32_t *pIndex); /** * @brief Maximum value of absolute values of a floating-point vector. @@ -770,87 +561,63 @@ float64_t arm_kullback_leibler_f64(const float64_t * pSrcA, * @param[in] blockSize length of the input vector * @param[out] pResult maximum value returned here */ - void arm_absmax_no_idx_f64( - const float64_t * pSrc, - uint32_t blockSize, - float64_t * pResult); +void arm_absmax_no_idx_f64(const float64_t *pSrc, uint32_t blockSize, float64_t *pResult); - /** +/** @brief Maximum value of a floating-point vector. @param[in] pSrc points to the input vector @param[in] blockSize number of samples in input vector @param[out] pResult maximum value returned here */ - void arm_max_no_idx_f32( - const float32_t *pSrc, - uint32_t blockSize, - float32_t *pResult); +void arm_max_no_idx_f32(const float32_t *pSrc, uint32_t blockSize, float32_t *pResult); - /** +/** @brief Minimum value of a floating-point vector. @param[in] pSrc points to the input vector @param[in] blockSize number of samples in input vector @param[out] pResult minimum value returned here */ - void arm_min_no_idx_f32( - const float32_t *pSrc, - uint32_t blockSize, - float32_t *pResult); +void arm_min_no_idx_f32(const float32_t *pSrc, uint32_t blockSize, float32_t *pResult); - /** +/** @brief Maximum value of a floating-point vector. @param[in] pSrc points to the input vector @param[in] blockSize number of samples in input vector @param[out] pResult maximum value returned here */ - void arm_max_no_idx_f64( - const float64_t *pSrc, - uint32_t blockSize, - float64_t *pResult); +void arm_max_no_idx_f64(const float64_t *pSrc, uint32_t blockSize, float64_t *pResult); - /** +/** @brief Maximum value of a q31 vector. @param[in] pSrc points to the input vector @param[in] blockSize number of samples in input vector @param[out] pResult maximum value returned here */ - void arm_max_no_idx_q31( - const q31_t *pSrc, - uint32_t blockSize, - q31_t *pResult); +void arm_max_no_idx_q31(const q31_t *pSrc, uint32_t blockSize, q31_t *pResult); - /** +/** @brief Maximum value of a q15 vector. @param[in] pSrc points to the input vector @param[in] blockSize number of samples in input vector @param[out] pResult maximum value returned here */ - void arm_max_no_idx_q15( - const q15_t *pSrc, - uint32_t blockSize, - q15_t *pResult); +void arm_max_no_idx_q15(const q15_t *pSrc, uint32_t blockSize, q15_t *pResult); - /** +/** @brief Maximum value of a q7 vector. @param[in] pSrc points to the input vector @param[in] blockSize number of samples in input vector @param[out] pResult maximum value returned here */ - void arm_max_no_idx_q7( - const q7_t *pSrc, - uint32_t blockSize, - q7_t *pResult); +void arm_max_no_idx_q7(const q7_t *pSrc, uint32_t blockSize, q7_t *pResult); - /** +/** @brief Minimum value of a floating-point vector. @param[in] pSrc points to the input vector @param[in] blockSize number of samples in input vector @param[out] pResult minimum value returned here */ - void arm_min_no_idx_f64( - const float64_t *pSrc, - uint32_t blockSize, - float64_t *pResult); +void arm_min_no_idx_f64(const float64_t *pSrc, uint32_t blockSize, float64_t *pResult); /** @brief Minimum value of a q31 vector. @@ -858,32 +625,23 @@ float64_t arm_kullback_leibler_f64(const float64_t * pSrcA, @param[in] blockSize number of samples in input vector @param[out] pResult minimum value returned here */ - void arm_min_no_idx_q31( - const q31_t *pSrc, - uint32_t blockSize, - q31_t *pResult); +void arm_min_no_idx_q31(const q31_t *pSrc, uint32_t blockSize, q31_t *pResult); - /** +/** @brief Minimum value of a q15 vector. @param[in] pSrc points to the input vector @param[in] blockSize number of samples in input vector @param[out] pResult minimum value returned here */ - void arm_min_no_idx_q15( - const q15_t *pSrc, - uint32_t blockSize, - q15_t *pResult); +void arm_min_no_idx_q15(const q15_t *pSrc, uint32_t blockSize, q15_t *pResult); - /** +/** @brief Minimum value of a q7 vector. @param[in] pSrc points to the input vector @param[in] blockSize number of samples in input vector @param[out] pResult minimum value returned here */ -void arm_min_no_idx_q7( - const q7_t *pSrc, - uint32_t blockSize, - q7_t *pResult); +void arm_min_no_idx_q7(const q7_t *pSrc, uint32_t blockSize, q7_t *pResult); /** @brief Mean square error between two Q7 vectors. @@ -892,12 +650,8 @@ void arm_min_no_idx_q7( @param[in] blockSize number of samples in input vector @param[out] pResult mean square error */ - -void arm_mse_q7( - const q7_t * pSrcA, - const q7_t * pSrcB, - uint32_t blockSize, - q7_t * pResult); + +void arm_mse_q7(const q7_t *pSrcA, const q7_t *pSrcB, uint32_t blockSize, q7_t *pResult); /** @brief Mean square error between two Q15 vectors. @@ -906,12 +660,8 @@ void arm_mse_q7( @param[in] blockSize number of samples in input vector @param[out] pResult mean square error */ - -void arm_mse_q15( - const q15_t * pSrcA, - const q15_t * pSrcB, - uint32_t blockSize, - q15_t * pResult); + +void arm_mse_q15(const q15_t *pSrcA, const q15_t *pSrcB, uint32_t blockSize, q15_t *pResult); /** @brief Mean square error between two Q31 vectors. @@ -920,12 +670,8 @@ void arm_mse_q15( @param[in] blockSize number of samples in input vector @param[out] pResult mean square error */ - -void arm_mse_q31( - const q31_t * pSrcA, - const q31_t * pSrcB, - uint32_t blockSize, - q31_t * pResult); + +void arm_mse_q31(const q31_t *pSrcA, const q31_t *pSrcB, uint32_t blockSize, q31_t *pResult); /** @brief Mean square error between two single precision float vectors. @@ -934,12 +680,9 @@ void arm_mse_q31( @param[in] blockSize number of samples in input vector @param[out] pResult mean square error */ - -void arm_mse_f32( - const float32_t * pSrcA, - const float32_t * pSrcB, - uint32_t blockSize, - float32_t * pResult); + +void arm_mse_f32(const float32_t *pSrcA, const float32_t *pSrcB, uint32_t blockSize, + float32_t *pResult); /** @brief Mean square error between two double precision float vectors. @@ -948,13 +691,9 @@ void arm_mse_f32( @param[in] blockSize number of samples in input vector @param[out] pResult mean square error */ - -void arm_mse_f64( - const float64_t * pSrcA, - const float64_t * pSrcB, - uint32_t blockSize, - float64_t * pResult); +void arm_mse_f64(const float64_t *pSrcA, const float64_t *pSrcB, uint32_t blockSize, + float64_t *pResult); /** * @brief Accumulation value of a floating-point vector. @@ -963,10 +702,7 @@ void arm_mse_f64( * @param[out] pResult is output value. */ -void arm_accumulate_f32( -const float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); +void arm_accumulate_f32(const float32_t *pSrc, uint32_t blockSize, float32_t *pResult); /** * @brief Accumulation value of a floating-point vector. @@ -975,13 +711,9 @@ const float32_t * pSrc, * @param[out] pResult is output value. */ -void arm_accumulate_f64( -const float64_t * pSrc, - uint32_t blockSize, - float64_t * pResult); - +void arm_accumulate_f64(const float64_t *pSrc, uint32_t blockSize, float64_t *pResult); -#ifdef __cplusplus +#ifdef __cplusplus } #endif diff --git a/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/statistics_functions_f16.h b/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/statistics_functions_f16.h old mode 100755 new mode 100644 index 746e8df39b8..0eba2792f5e --- a/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/statistics_functions_f16.h +++ b/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/statistics_functions_f16.h @@ -23,7 +23,6 @@ * limitations under the License. */ - #ifndef STATISTICS_FUNCTIONS_F16_H_ #define STATISTICS_FUNCTIONS_F16_H_ @@ -36,93 +35,70 @@ #include "dsp/basic_math_functions_f16.h" #include "dsp/fast_math_functions_f16.h" -#ifdef __cplusplus -extern "C" -{ +#ifdef __cplusplus +extern "C" { #endif #if defined(ARM_FLOAT16_SUPPORTED) - /** +/** * @brief Sum of the squares of the elements of a floating-point vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output value. */ - void arm_power_f16( - const float16_t * pSrc, - uint32_t blockSize, - float16_t * pResult); +void arm_power_f16(const float16_t *pSrc, uint32_t blockSize, float16_t *pResult); - /** +/** * @brief Mean value of a floating-point vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output value. */ - void arm_mean_f16( - const float16_t * pSrc, - uint32_t blockSize, - float16_t * pResult); +void arm_mean_f16(const float16_t *pSrc, uint32_t blockSize, float16_t *pResult); - /** +/** * @brief Variance of the elements of a floating-point vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output value. */ - void arm_var_f16( - const float16_t * pSrc, - uint32_t blockSize, - float16_t * pResult); +void arm_var_f16(const float16_t *pSrc, uint32_t blockSize, float16_t *pResult); - /** +/** * @brief Root Mean Square of the elements of a floating-point vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output value. */ - void arm_rms_f16( - const float16_t * pSrc, - uint32_t blockSize, - float16_t * pResult); +void arm_rms_f16(const float16_t *pSrc, uint32_t blockSize, float16_t *pResult); - /** +/** * @brief Standard deviation of the elements of a floating-point vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output value. */ - void arm_std_f16( - const float16_t * pSrc, - uint32_t blockSize, - float16_t * pResult); +void arm_std_f16(const float16_t *pSrc, uint32_t blockSize, float16_t *pResult); - /** +/** * @brief Minimum value of a floating-point vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output pointer * @param[out] pIndex is the array index of the minimum value in the input buffer. */ - void arm_min_f16( - const float16_t * pSrc, - uint32_t blockSize, - float16_t * pResult, - uint32_t * pIndex); +void arm_min_f16(const float16_t *pSrc, uint32_t blockSize, float16_t *pResult, uint32_t *pIndex); - /** +/** * @brief Minimum value of absolute values of a floating-point vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output pointer * @param[out] pIndex is the array index of the minimum value in the input buffer. */ - void arm_absmin_f16( - const float16_t * pSrc, - uint32_t blockSize, - float16_t * pResult, - uint32_t * pIndex); +void arm_absmin_f16(const float16_t *pSrc, uint32_t blockSize, float16_t *pResult, + uint32_t *pIndex); /** * @brief Maximum value of a floating-point vector. @@ -131,11 +107,7 @@ extern "C" * @param[out] pResult maximum value returned here * @param[out] pIndex index of maximum value returned here */ - void arm_max_f16( - const float16_t * pSrc, - uint32_t blockSize, - float16_t * pResult, - uint32_t * pIndex); +void arm_max_f16(const float16_t *pSrc, uint32_t blockSize, float16_t *pResult, uint32_t *pIndex); /** * @brief Maximum value of absolute values of a floating-point vector. @@ -144,22 +116,16 @@ extern "C" * @param[out] pResult maximum value returned here * @param[out] pIndex index of maximum value returned here */ - void arm_absmax_f16( - const float16_t * pSrc, - uint32_t blockSize, - float16_t * pResult, - uint32_t * pIndex); +void arm_absmax_f16(const float16_t *pSrc, uint32_t blockSize, float16_t *pResult, + uint32_t *pIndex); - /** +/** * @brief Minimum value of absolute values of a floating-point vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output pointer */ - void arm_absmin_no_idx_f16( - const float16_t * pSrc, - uint32_t blockSize, - float16_t * pResult); +void arm_absmin_no_idx_f16(const float16_t *pSrc, uint32_t blockSize, float16_t *pResult); /** * @brief Maximum value of a floating-point vector. @@ -167,11 +133,7 @@ extern "C" * @param[in] blockSize length of the input vector * @param[out] pResult maximum value returned here */ - void arm_absmax_no_idx_f16( - const float16_t * pSrc, - uint32_t blockSize, - float16_t * pResult); - +void arm_absmax_no_idx_f16(const float16_t *pSrc, uint32_t blockSize, float16_t *pResult); /** * @brief Entropy @@ -180,12 +142,10 @@ extern "C" * @param[in] blockSize Number of samples in the input array. * @return Entropy -Sum(p ln p) */ -float16_t arm_entropy_f16(const float16_t * pSrcA,uint32_t blockSize); - +float16_t arm_entropy_f16(const float16_t *pSrcA, uint32_t blockSize); float16_t arm_logsumexp_f16(const float16_t *in, uint32_t blockSize); - /** * @brief Dot product with log arithmetic * @@ -197,11 +157,8 @@ float16_t arm_logsumexp_f16(const float16_t *in, uint32_t blockSize); * @param[in] pTmpBuffer temporary buffer of length blockSize * @return The log of the dot product . */ -float16_t arm_logsumexp_dot_prod_f16(const float16_t * pSrcA, - const float16_t * pSrcB, - uint32_t blockSize, - float16_t *pTmpBuffer); - +float16_t arm_logsumexp_dot_prod_f16(const float16_t *pSrcA, const float16_t *pSrcB, + uint32_t blockSize, float16_t *pTmpBuffer); /** * @brief Kullback-Leibler @@ -211,10 +168,8 @@ float16_t arm_logsumexp_dot_prod_f16(const float16_t * pSrcA, * @param[in] blockSize Number of samples in the input array. * @return Kullback-Leibler Divergence D(A || B) */ -float16_t arm_kullback_leibler_f16(const float16_t * pSrcA - ,const float16_t * pSrcB - ,uint32_t blockSize); - +float16_t arm_kullback_leibler_f16(const float16_t *pSrcA, const float16_t *pSrcB, + uint32_t blockSize); /** @brief Maximum value of a floating-point vector. @@ -222,11 +177,7 @@ float16_t arm_kullback_leibler_f16(const float16_t * pSrcA @param[in] blockSize number of samples in input vector @param[out] pResult maximum value returned here */ - void arm_max_no_idx_f16( - const float16_t *pSrc, - uint32_t blockSize, - float16_t *pResult); - +void arm_max_no_idx_f16(const float16_t *pSrc, uint32_t blockSize, float16_t *pResult); /** @brief Minimum value of a floating-point vector. @@ -234,11 +185,7 @@ float16_t arm_kullback_leibler_f16(const float16_t * pSrcA @param[in] blockSize number of samples in input vector @param[out] pResult minimum value returned here */ - void arm_min_no_idx_f16( - const float16_t *pSrc, - uint32_t blockSize, - float16_t *pResult); - +void arm_min_no_idx_f16(const float16_t *pSrc, uint32_t blockSize, float16_t *pResult); /** @brief Mean square error between two half precision float vectors. @@ -247,12 +194,8 @@ float16_t arm_kullback_leibler_f16(const float16_t * pSrcA @param[in] blockSize number of samples in input vector @param[out] pResult mean square error */ -void arm_mse_f16( - const float16_t * pSrcA, - const float16_t * pSrcB, - uint32_t blockSize, - float16_t * pResult); - +void arm_mse_f16(const float16_t *pSrcA, const float16_t *pSrcB, uint32_t blockSize, + float16_t *pResult); /** * @brief Sum value of a floating-point vector. @@ -260,14 +203,10 @@ void arm_mse_f16( * @param[in] blockSize is the number of samples to process * @param[out] pResult is output value. */ - void arm_accumulate_f16( - const float16_t * pSrc, - uint32_t blockSize, - float16_t * pResult); - +void arm_accumulate_f16(const float16_t *pSrc, uint32_t blockSize, float16_t *pResult); #endif /*defined(ARM_FLOAT16_SUPPORTED)*/ -#ifdef __cplusplus +#ifdef __cplusplus } #endif diff --git a/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/support_functions.h b/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/support_functions.h old mode 100755 new mode 100644 index 928cf403f15..10bdca63b29 --- a/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/support_functions.h +++ b/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/support_functions.h @@ -23,7 +23,6 @@ * limitations under the License. */ - #ifndef SUPPORT_FUNCTIONS_H_ #define SUPPORT_FUNCTIONS_H_ @@ -33,26 +32,21 @@ #include "dsp/none.h" #include "dsp/utils.h" -#ifdef __cplusplus -extern "C" -{ +#ifdef __cplusplus +extern "C" { #endif /** * @defgroup groupSupport Support Functions */ - /** * @brief Converts the elements of the 64 bit floating-point vector to floating-point vector. * @param[in] pSrc points to the floating-point 64 input vector * @param[out] pDst points to the floating-point output vector * @param[in] blockSize length of the input vector */ - void arm_f64_to_float( - const float64_t * pSrc, - float32_t * pDst, - uint32_t blockSize); +void arm_f64_to_float(const float64_t *pSrc, float32_t *pDst, uint32_t blockSize); /** * @brief Converts the elements of the 64 bit floating-point vector to Q31 vector. @@ -60,10 +54,7 @@ extern "C" * @param[out] pDst points to the Q31 output vector * @param[in] blockSize length of the input vector */ - void arm_f64_to_q31( - const float64_t * pSrc, - q31_t * pDst, - uint32_t blockSize); +void arm_f64_to_q31(const float64_t *pSrc, q31_t *pDst, uint32_t blockSize); /** * @brief Converts the elements of the 64 bit floating-point vector to Q15 vector. @@ -71,10 +62,7 @@ extern "C" * @param[out] pDst points to the Q15 output vector * @param[in] blockSize length of the input vector */ - void arm_f64_to_q15( - const float64_t * pSrc, - q15_t * pDst, - uint32_t blockSize); +void arm_f64_to_q15(const float64_t *pSrc, q15_t *pDst, uint32_t blockSize); /** * @brief Converts the elements of the 64 bit floating-point vector to Q7 vector. @@ -82,12 +70,7 @@ extern "C" * @param[out] pDst points to the Q7 output vector * @param[in] blockSize length of the input vector */ - void arm_f64_to_q7( - const float64_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - +void arm_f64_to_q7(const float64_t *pSrc, q7_t *pDst, uint32_t blockSize); /** * @brief Converts the elements of the floating-point vector to 64 bit floating-point vector. @@ -95,10 +78,7 @@ extern "C" * @param[out] pDst points to the 64 bit floating-point output vector * @param[in] blockSize length of the input vector */ - void arm_float_to_f64( - const float32_t * pSrc, - float64_t * pDst, - uint32_t blockSize); +void arm_float_to_f64(const float32_t *pSrc, float64_t *pDst, uint32_t blockSize); /** * @brief Converts the elements of the floating-point vector to Q31 vector. @@ -106,34 +86,23 @@ extern "C" * @param[out] pDst points to the Q31 output vector * @param[in] blockSize length of the input vector */ - void arm_float_to_q31( - const float32_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - +void arm_float_to_q31(const float32_t *pSrc, q31_t *pDst, uint32_t blockSize); - /** +/** * @brief Converts the elements of the floating-point vector to Q15 vector. * @param[in] pSrc points to the floating-point input vector * @param[out] pDst points to the Q15 output vector * @param[in] blockSize length of the input vector */ - void arm_float_to_q15( - const float32_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - +void arm_float_to_q15(const float32_t *pSrc, q15_t *pDst, uint32_t blockSize); - /** +/** * @brief Converts the elements of the floating-point vector to Q7 vector. * @param[in] pSrc points to the floating-point input vector * @param[out] pDst points to the Q7 output vector * @param[in] blockSize length of the input vector */ - void arm_float_to_q7( - const float32_t * pSrc, - q7_t * pDst, - uint32_t blockSize); +void arm_float_to_q7(const float32_t *pSrc, q7_t *pDst, uint32_t blockSize); /** * @brief Converts the elements of the Q31 vector to 64 bit floating-point vector. @@ -141,45 +110,31 @@ extern "C" * @param[out] pDst is output pointer * @param[in] blockSize is the number of samples to process */ -void arm_q31_to_f64( -const q31_t * pSrc, - float64_t * pDst, - uint32_t blockSize); +void arm_q31_to_f64(const q31_t *pSrc, float64_t *pDst, uint32_t blockSize); - /** +/** * @brief Converts the elements of the Q31 vector to floating-point vector. * @param[in] pSrc is input pointer * @param[out] pDst is output pointer * @param[in] blockSize is the number of samples to process */ - void arm_q31_to_float( - const q31_t * pSrc, - float32_t * pDst, - uint32_t blockSize); +void arm_q31_to_float(const q31_t *pSrc, float32_t *pDst, uint32_t blockSize); - - /** +/** * @brief Converts the elements of the Q31 vector to Q15 vector. * @param[in] pSrc is input pointer * @param[out] pDst is output pointer * @param[in] blockSize is the number of samples to process */ - void arm_q31_to_q15( - const q31_t * pSrc, - q15_t * pDst, - uint32_t blockSize); +void arm_q31_to_q15(const q31_t *pSrc, q15_t *pDst, uint32_t blockSize); - - /** +/** * @brief Converts the elements of the Q31 vector to Q7 vector. * @param[in] pSrc is input pointer * @param[out] pDst is output pointer * @param[in] blockSize is the number of samples to process */ - void arm_q31_to_q7( - const q31_t * pSrc, - q7_t * pDst, - uint32_t blockSize); +void arm_q31_to_q7(const q31_t *pSrc, q7_t *pDst, uint32_t blockSize); /** * @brief Converts the elements of the Q15 vector to 64 bit floating-point vector. @@ -187,45 +142,31 @@ const q31_t * pSrc, * @param[out] pDst is output pointer * @param[in] blockSize is the number of samples to process */ -void arm_q15_to_f64( -const q15_t * pSrc, - float64_t * pDst, - uint32_t blockSize); +void arm_q15_to_f64(const q15_t *pSrc, float64_t *pDst, uint32_t blockSize); - /** +/** * @brief Converts the elements of the Q15 vector to floating-point vector. * @param[in] pSrc is input pointer * @param[out] pDst is output pointer * @param[in] blockSize is the number of samples to process */ - void arm_q15_to_float( - const q15_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - +void arm_q15_to_float(const q15_t *pSrc, float32_t *pDst, uint32_t blockSize); - /** +/** * @brief Converts the elements of the Q15 vector to Q31 vector. * @param[in] pSrc is input pointer * @param[out] pDst is output pointer * @param[in] blockSize is the number of samples to process */ - void arm_q15_to_q31( - const q15_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - +void arm_q15_to_q31(const q15_t *pSrc, q31_t *pDst, uint32_t blockSize); - /** +/** * @brief Converts the elements of the Q15 vector to Q7 vector. * @param[in] pSrc is input pointer * @param[out] pDst is output pointer * @param[in] blockSize is the number of samples to process */ - void arm_q15_to_q7( - const q15_t * pSrc, - q7_t * pDst, - uint32_t blockSize); +void arm_q15_to_q7(const q15_t *pSrc, q7_t *pDst, uint32_t blockSize); /** * @brief Converts the elements of the Q7 vector to 64 bit floating-point vector. @@ -233,270 +174,187 @@ const q15_t * pSrc, * @param[out] pDst is output pointer * @param[in] blockSize is the number of samples to process */ -void arm_q7_to_f64( -const q7_t * pSrc, - float64_t * pDst, - uint32_t blockSize); +void arm_q7_to_f64(const q7_t *pSrc, float64_t *pDst, uint32_t blockSize); - /** +/** * @brief Converts the elements of the Q7 vector to floating-point vector. * @param[in] pSrc is input pointer * @param[out] pDst is output pointer * @param[in] blockSize is the number of samples to process */ - void arm_q7_to_float( - const q7_t * pSrc, - float32_t * pDst, - uint32_t blockSize); +void arm_q7_to_float(const q7_t *pSrc, float32_t *pDst, uint32_t blockSize); - - /** +/** * @brief Converts the elements of the Q7 vector to Q31 vector. * @param[in] pSrc input pointer * @param[out] pDst output pointer * @param[in] blockSize number of samples to process */ - void arm_q7_to_q31( - const q7_t * pSrc, - q31_t * pDst, - uint32_t blockSize); +void arm_q7_to_q31(const q7_t *pSrc, q31_t *pDst, uint32_t blockSize); - - /** +/** * @brief Converts the elements of the Q7 vector to Q15 vector. * @param[in] pSrc input pointer * @param[out] pDst output pointer * @param[in] blockSize number of samples to process */ - void arm_q7_to_q15( - const q7_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - +void arm_q7_to_q15(const q7_t *pSrc, q15_t *pDst, uint32_t blockSize); - - - /** +/** * @brief Struct for specifying sorting algorithm */ - typedef enum - { - ARM_SORT_BITONIC = 0, - /**< Bitonic sort */ - ARM_SORT_BUBBLE = 1, - /**< Bubble sort */ - ARM_SORT_HEAP = 2, - /**< Heap sort */ +typedef enum { + ARM_SORT_BITONIC = 0, + /**< Bitonic sort */ + ARM_SORT_BUBBLE = 1, + /**< Bubble sort */ + ARM_SORT_HEAP = 2, + /**< Heap sort */ ARM_SORT_INSERTION = 3, - /**< Insertion sort */ - ARM_SORT_QUICK = 4, - /**< Quick sort */ + /**< Insertion sort */ + ARM_SORT_QUICK = 4, + /**< Quick sort */ ARM_SORT_SELECTION = 5 - /**< Selection sort */ - } arm_sort_alg; + /**< Selection sort */ +} arm_sort_alg; - /** +/** * @brief Struct for specifying sorting algorithm */ - typedef enum - { +typedef enum { ARM_SORT_DESCENDING = 0, - /**< Descending order (9 to 0) */ + /**< Descending order (9 to 0) */ ARM_SORT_ASCENDING = 1 - /**< Ascending order (0 to 9) */ - } arm_sort_dir; + /**< Ascending order (0 to 9) */ +} arm_sort_dir; - /** +/** * @brief Instance structure for the sorting algorithms. */ - typedef struct - { - arm_sort_alg alg; /**< Sorting algorithm selected */ - arm_sort_dir dir; /**< Sorting order (direction) */ - } arm_sort_instance_f32; +typedef struct { + arm_sort_alg alg; /**< Sorting algorithm selected */ + arm_sort_dir dir; /**< Sorting order (direction) */ +} arm_sort_instance_f32; - /** +/** * @param[in] S points to an instance of the sorting structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data. * @param[in] blockSize number of samples to process. */ - void arm_sort_f32( - const arm_sort_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); +void arm_sort_f32(const arm_sort_instance_f32 *S, float32_t *pSrc, float32_t *pDst, + uint32_t blockSize); - /** +/** * @param[in,out] S points to an instance of the sorting structure. * @param[in] alg Selected algorithm. * @param[in] dir Sorting order. */ - void arm_sort_init_f32( - arm_sort_instance_f32 * S, - arm_sort_alg alg, - arm_sort_dir dir); +void arm_sort_init_f32(arm_sort_instance_f32 *S, arm_sort_alg alg, arm_sort_dir dir); - /** +/** * @brief Instance structure for the sorting algorithms. */ - typedef struct - { - arm_sort_dir dir; /**< Sorting order (direction) */ - float32_t * buffer; /**< Working buffer */ - } arm_merge_sort_instance_f32; +typedef struct { + arm_sort_dir dir; /**< Sorting order (direction) */ + float32_t *buffer; /**< Working buffer */ +} arm_merge_sort_instance_f32; - /** +/** * @param[in] S points to an instance of the sorting structure. * @param[in,out] pSrc points to the block of input data. * @param[out] pDst points to the block of output data * @param[in] blockSize number of samples to process. */ - void arm_merge_sort_f32( - const arm_merge_sort_instance_f32 * S, - float32_t *pSrc, - float32_t *pDst, - uint32_t blockSize); +void arm_merge_sort_f32(const arm_merge_sort_instance_f32 *S, float32_t *pSrc, float32_t *pDst, + uint32_t blockSize); - /** +/** * @param[in,out] S points to an instance of the sorting structure. * @param[in] dir Sorting order. * @param[in] buffer Working buffer. */ - void arm_merge_sort_init_f32( - arm_merge_sort_instance_f32 * S, - arm_sort_dir dir, - float32_t * buffer); +void arm_merge_sort_init_f32(arm_merge_sort_instance_f32 *S, arm_sort_dir dir, float32_t *buffer); - - - /** +/** * @brief Copies the elements of a floating-point vector. * @param[in] pSrc input pointer * @param[out] pDst output pointer * @param[in] blockSize number of samples to process */ - void arm_copy_f32( - const float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); +void arm_copy_f32(const float32_t *pSrc, float32_t *pDst, uint32_t blockSize); - - - /** +/** * @brief Copies the elements of a floating-point vector. * @param[in] pSrc input pointer * @param[out] pDst output pointer * @param[in] blockSize number of samples to process */ - void arm_copy_f64( - const float64_t * pSrc, - float64_t * pDst, - uint32_t blockSize); +void arm_copy_f64(const float64_t *pSrc, float64_t *pDst, uint32_t blockSize); - - - /** +/** * @brief Copies the elements of a Q7 vector. * @param[in] pSrc input pointer * @param[out] pDst output pointer * @param[in] blockSize number of samples to process */ - void arm_copy_q7( - const q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - +void arm_copy_q7(const q7_t *pSrc, q7_t *pDst, uint32_t blockSize); - /** +/** * @brief Copies the elements of a Q15 vector. * @param[in] pSrc input pointer * @param[out] pDst output pointer * @param[in] blockSize number of samples to process */ - void arm_copy_q15( - const q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - +void arm_copy_q15(const q15_t *pSrc, q15_t *pDst, uint32_t blockSize); - /** +/** * @brief Copies the elements of a Q31 vector. * @param[in] pSrc input pointer * @param[out] pDst output pointer * @param[in] blockSize number of samples to process */ - void arm_copy_q31( - const q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - +void arm_copy_q31(const q31_t *pSrc, q31_t *pDst, uint32_t blockSize); - /** +/** * @brief Fills a constant value into a floating-point vector. * @param[in] value input value to be filled * @param[out] pDst output pointer * @param[in] blockSize number of samples to process */ - void arm_fill_f32( - float32_t value, - float32_t * pDst, - uint32_t blockSize); - +void arm_fill_f32(float32_t value, float32_t *pDst, uint32_t blockSize); - /** +/** * @brief Fills a constant value into a floating-point vector. * @param[in] value input value to be filled * @param[out] pDst output pointer * @param[in] blockSize number of samples to process */ - void arm_fill_f64( - float64_t value, - float64_t * pDst, - uint32_t blockSize); +void arm_fill_f64(float64_t value, float64_t *pDst, uint32_t blockSize); - - /** +/** * @brief Fills a constant value into a Q7 vector. * @param[in] value input value to be filled * @param[out] pDst output pointer * @param[in] blockSize number of samples to process */ - void arm_fill_q7( - q7_t value, - q7_t * pDst, - uint32_t blockSize); +void arm_fill_q7(q7_t value, q7_t *pDst, uint32_t blockSize); - - /** +/** * @brief Fills a constant value into a Q15 vector. * @param[in] value input value to be filled * @param[out] pDst output pointer * @param[in] blockSize number of samples to process */ - void arm_fill_q15( - q15_t value, - q15_t * pDst, - uint32_t blockSize); +void arm_fill_q15(q15_t value, q15_t *pDst, uint32_t blockSize); - - /** +/** * @brief Fills a constant value into a Q31 vector. * @param[in] value input value to be filled * @param[out] pDst output pointer * @param[in] blockSize number of samples to process */ - void arm_fill_q31( - q31_t value, - q31_t * pDst, - uint32_t blockSize); - - - - - - +void arm_fill_q31(q31_t value, q31_t *pDst, uint32_t blockSize); /** * @brief Weighted average @@ -508,10 +366,8 @@ const q7_t * pSrc, * @return Weighted average * */ -float32_t arm_weighted_average_f32(const float32_t *in - , const float32_t *weigths - , uint32_t blockSize); - +float32_t arm_weighted_average_f32(const float32_t *in, const float32_t *weigths, + uint32_t blockSize); /** * @brief Barycenter @@ -524,15 +380,10 @@ float32_t arm_weighted_average_f32(const float32_t *in * @param[in] vecDim Dimension of space (vector dimension) * */ -void arm_barycenter_f32(const float32_t *in - , const float32_t *weights - , float32_t *out - , uint32_t nbVectors - , uint32_t vecDim); - - +void arm_barycenter_f32(const float32_t *in, const float32_t *weights, float32_t *out, + uint32_t nbVectors, uint32_t vecDim); -#ifdef __cplusplus +#ifdef __cplusplus } #endif diff --git a/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/support_functions_f16.h b/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/support_functions_f16.h old mode 100755 new mode 100644 index ab0c1ad7a90..4d36aae2357 --- a/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/support_functions_f16.h +++ b/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/support_functions_f16.h @@ -23,7 +23,6 @@ * limitations under the License. */ - #ifndef SUPPORT_FUNCTIONS_F16_H_ #define SUPPORT_FUNCTIONS_F16_H_ @@ -33,30 +32,27 @@ #include "dsp/none.h" #include "dsp/utils.h" -#ifdef __cplusplus -extern "C" -{ +#ifdef __cplusplus +extern "C" { #endif #if defined(ARM_FLOAT16_SUPPORTED) - /** +/** * @brief Copies the elements of a floating-point vector. * @param[in] pSrc input pointer * @param[out] pDst output pointer * @param[in] blockSize number of samples to process */ -void arm_copy_f16(const float16_t * pSrc, float16_t * pDst, uint32_t blockSize); +void arm_copy_f16(const float16_t *pSrc, float16_t *pDst, uint32_t blockSize); - - /** +/** * @brief Fills a constant value into a floating-point vector. * @param[in] value input value to be filled * @param[out] pDst output pointer * @param[in] blockSize number of samples to process */ -void arm_fill_f16(float16_t value, float16_t * pDst, uint32_t blockSize); - +void arm_fill_f16(float16_t value, float16_t *pDst, uint32_t blockSize); /** * @brief Converts the elements of the floating-point vector to Q31 vector. @@ -64,8 +60,7 @@ void arm_fill_f16(float16_t value, float16_t * pDst, uint32_t blockSize); * @param[out] pDst points to the q15 output vector * @param[in] blockSize length of the input vector */ -void arm_f16_to_q15(const float16_t * pSrc, q15_t * pDst, uint32_t blockSize); - +void arm_f16_to_q15(const float16_t *pSrc, q15_t *pDst, uint32_t blockSize); /** * @brief Converts the elements of the floating-point vector to Q31 vector. @@ -73,8 +68,7 @@ void arm_f16_to_q15(const float16_t * pSrc, q15_t * pDst, uint32_t blockSize); * @param[out] pDst points to the f16 output vector * @param[in] blockSize length of the input vector */ -void arm_q15_to_f16(const q15_t * pSrc, float16_t * pDst, uint32_t blockSize); - +void arm_q15_to_f16(const q15_t *pSrc, float16_t *pDst, uint32_t blockSize); /** * @brief Converts the elements of the 64 bit floating-point vector to 16 bit floating-point vector. @@ -82,8 +76,7 @@ void arm_q15_to_f16(const q15_t * pSrc, float16_t * pDst, uint32_t blockSize); * @param[out] pDst points to the f16 output vector * @param[in] blockSize length of the input vector */ -void arm_f64_to_f16(const float64_t * pSrc, float16_t * pDst, uint32_t blockSize); - +void arm_f64_to_f16(const float64_t *pSrc, float16_t *pDst, uint32_t blockSize); /** * @brief Converts the elements of the 16 bit floating-point vector to 64 bit floating-point vector. @@ -91,8 +84,7 @@ void arm_f64_to_f16(const float64_t * pSrc, float16_t * pDst, uint32_t blockSize * @param[out] pDst points to the f64 output vector * @param[in] blockSize length of the input vector */ -void arm_f16_to_f64(const float16_t * pSrc, float64_t * pDst, uint32_t blockSize); - +void arm_f16_to_f64(const float16_t *pSrc, float64_t *pDst, uint32_t blockSize); /** * @brief Converts the elements of the floating-point vector to Q31 vector. @@ -100,8 +92,7 @@ void arm_f16_to_f64(const float16_t * pSrc, float64_t * pDst, uint32_t blockSize * @param[out] pDst points to the f16 output vector * @param[in] blockSize length of the input vector */ -void arm_float_to_f16(const float32_t * pSrc, float16_t * pDst, uint32_t blockSize); - +void arm_float_to_f16(const float32_t *pSrc, float16_t *pDst, uint32_t blockSize); /** * @brief Converts the elements of the floating-point vector to Q31 vector. @@ -109,8 +100,7 @@ void arm_float_to_f16(const float32_t * pSrc, float16_t * pDst, uint32_t blockSi * @param[out] pDst points to the f32 output vector * @param[in] blockSize length of the input vector */ -void arm_f16_to_float(const float16_t * pSrc, float32_t * pDst, uint32_t blockSize); - +void arm_f16_to_float(const float16_t *pSrc, float32_t *pDst, uint32_t blockSize); /** * @brief Weighted average @@ -119,10 +109,8 @@ void arm_f16_to_float(const float16_t * pSrc, float32_t * pDst, uint32_t blockSi * @param[in] blockSize Number of samples in the input array. * @return Weighted average */ -float16_t arm_weighted_average_f16(const float16_t *in - , const float16_t *weigths - , uint32_t blockSize); - +float16_t arm_weighted_average_f16(const float16_t *in, const float16_t *weigths, + uint32_t blockSize); /** * @brief Barycenter @@ -132,12 +120,8 @@ float16_t arm_weighted_average_f16(const float16_t *in * @param[in] nbVectors Number of vectors * @param[in] vecDim Dimension of space (vector dimension) */ -void arm_barycenter_f16(const float16_t *in - , const float16_t *weights - , float16_t *out - , uint32_t nbVectors - , uint32_t vecDim); - +void arm_barycenter_f16(const float16_t *in, const float16_t *weights, float16_t *out, + uint32_t nbVectors, uint32_t vecDim); /** @ingroup groupSupport @@ -166,9 +150,9 @@ void arm_barycenter_f16(const float16_t *in */ __STATIC_INLINE int16_t arm_typecast_s16_f16(float16_t x) { - int16_t res; - res=*(int16_t*)memcpy((char*)&res,(char*)&x,sizeof(float16_t)); - return(res); + int16_t res; + res = *(int16_t *)memcpy((char *)&res, (char *)&x, sizeof(float16_t)); + return (res); } /** @@ -185,19 +169,17 @@ __STATIC_INLINE int16_t arm_typecast_s16_f16(float16_t x) */ __STATIC_INLINE float16_t arm_typecast_f16_s16(int16_t x) { - float16_t res; - res=*(float16_t*)memcpy((char*)&res,(char*)&x,sizeof(int16_t)); - return(res); + float16_t res; + res = *(float16_t *)memcpy((char *)&res, (char *)&x, sizeof(int16_t)); + return (res); } - /** @} end of typecast group */ - #endif /*defined(ARM_FLOAT16_SUPPORTED)*/ -#ifdef __cplusplus +#ifdef __cplusplus } #endif diff --git a/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/svm_defines.h b/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/svm_defines.h old mode 100755 new mode 100644 index 185a8a902c9..995d6bf9761 --- a/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/svm_defines.h +++ b/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/svm_defines.h @@ -24,23 +24,21 @@ * limitations under the License. */ - #ifndef SVM_DEFINES_H_ #define SVM_DEFINES_H_ /** * @brief Struct for specifying SVM Kernel */ -typedef enum -{ +typedef enum { ARM_ML_KERNEL_LINEAR = 0, - /**< Linear kernel */ + /**< Linear kernel */ ARM_ML_KERNEL_POLYNOMIAL = 1, - /**< Polynomial kernel */ + /**< Polynomial kernel */ ARM_ML_KERNEL_RBF = 2, - /**< Radial Basis Function kernel */ + /**< Radial Basis Function kernel */ ARM_ML_KERNEL_SIGMOID = 3 - /**< Sigmoid kernel */ + /**< Sigmoid kernel */ } arm_ml_kernel_type; #endif diff --git a/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/svm_functions.h b/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/svm_functions.h old mode 100755 new mode 100644 index cb00cd4f1b3..a218cafa388 --- a/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/svm_functions.h +++ b/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/svm_functions.h @@ -23,7 +23,6 @@ * limitations under the License. */ - #ifndef SVM_FUNCTIONS_H_ #define SVM_FUNCTIONS_H_ @@ -34,9 +33,8 @@ #include "dsp/utils.h" #include "dsp/svm_defines.h" -#ifdef __cplusplus -extern "C" -{ +#ifdef __cplusplus +extern "C" { #endif #define STEP(x) (x) <= 0 ? 0 : 1 @@ -64,78 +62,68 @@ extern "C" __STATIC_INLINE float32_t arm_exponent_f32(float32_t x, int32_t nb) { float32_t r = x; - nb --; - while(nb > 0) - { + nb--; + while (nb > 0) { r = r * x; nb--; } - return(r); + return (r); } - /** * @brief Instance structure for linear SVM prediction function. */ -typedef struct -{ - uint32_t nbOfSupportVectors; /**< Number of support vectors */ - uint32_t vectorDimension; /**< Dimension of vector space */ - float32_t intercept; /**< Intercept */ - const float32_t *dualCoefficients; /**< Dual coefficients */ - const float32_t *supportVectors; /**< Support vectors */ - const int32_t *classes; /**< The two SVM classes */ +typedef struct { + uint32_t nbOfSupportVectors; /**< Number of support vectors */ + uint32_t vectorDimension; /**< Dimension of vector space */ + float32_t intercept; /**< Intercept */ + const float32_t *dualCoefficients; /**< Dual coefficients */ + const float32_t *supportVectors; /**< Support vectors */ + const int32_t *classes; /**< The two SVM classes */ } arm_svm_linear_instance_f32; - /** * @brief Instance structure for polynomial SVM prediction function. */ -typedef struct -{ - uint32_t nbOfSupportVectors; /**< Number of support vectors */ - uint32_t vectorDimension; /**< Dimension of vector space */ - float32_t intercept; /**< Intercept */ - const float32_t *dualCoefficients; /**< Dual coefficients */ - const float32_t *supportVectors; /**< Support vectors */ - const int32_t *classes; /**< The two SVM classes */ - int32_t degree; /**< Polynomial degree */ - float32_t coef0; /**< Polynomial constant */ - float32_t gamma; /**< Gamma factor */ +typedef struct { + uint32_t nbOfSupportVectors; /**< Number of support vectors */ + uint32_t vectorDimension; /**< Dimension of vector space */ + float32_t intercept; /**< Intercept */ + const float32_t *dualCoefficients; /**< Dual coefficients */ + const float32_t *supportVectors; /**< Support vectors */ + const int32_t *classes; /**< The two SVM classes */ + int32_t degree; /**< Polynomial degree */ + float32_t coef0; /**< Polynomial constant */ + float32_t gamma; /**< Gamma factor */ } arm_svm_polynomial_instance_f32; - /** * @brief Instance structure for rbf SVM prediction function. */ -typedef struct -{ - uint32_t nbOfSupportVectors; /**< Number of support vectors */ - uint32_t vectorDimension; /**< Dimension of vector space */ - float32_t intercept; /**< Intercept */ - const float32_t *dualCoefficients; /**< Dual coefficients */ - const float32_t *supportVectors; /**< Support vectors */ - const int32_t *classes; /**< The two SVM classes */ - float32_t gamma; /**< Gamma factor */ +typedef struct { + uint32_t nbOfSupportVectors; /**< Number of support vectors */ + uint32_t vectorDimension; /**< Dimension of vector space */ + float32_t intercept; /**< Intercept */ + const float32_t *dualCoefficients; /**< Dual coefficients */ + const float32_t *supportVectors; /**< Support vectors */ + const int32_t *classes; /**< The two SVM classes */ + float32_t gamma; /**< Gamma factor */ } arm_svm_rbf_instance_f32; - /** * @brief Instance structure for sigmoid SVM prediction function. */ -typedef struct -{ - uint32_t nbOfSupportVectors; /**< Number of support vectors */ - uint32_t vectorDimension; /**< Dimension of vector space */ - float32_t intercept; /**< Intercept */ - const float32_t *dualCoefficients; /**< Dual coefficients */ - const float32_t *supportVectors; /**< Support vectors */ - const int32_t *classes; /**< The two SVM classes */ - float32_t coef0; /**< Independent constant */ - float32_t gamma; /**< Gamma factor */ +typedef struct { + uint32_t nbOfSupportVectors; /**< Number of support vectors */ + uint32_t vectorDimension; /**< Dimension of vector space */ + float32_t intercept; /**< Intercept */ + const float32_t *dualCoefficients; /**< Dual coefficients */ + const float32_t *supportVectors; /**< Support vectors */ + const int32_t *classes; /**< The two SVM classes */ + float32_t coef0; /**< Independent constant */ + float32_t gamma; /**< Gamma factor */ } arm_svm_sigmoid_instance_f32; - /** * @brief SVM linear instance init function * @param[in] S Parameters for SVM functions @@ -146,14 +134,10 @@ typedef struct * @param[in] supportVectors Array of support vectors * @param[in] classes Array of 2 classes ID */ -void arm_svm_linear_init_f32(arm_svm_linear_instance_f32 *S, - uint32_t nbOfSupportVectors, - uint32_t vectorDimension, - float32_t intercept, - const float32_t *dualCoefficients, - const float32_t *supportVectors, - const int32_t *classes); - +void arm_svm_linear_init_f32(arm_svm_linear_instance_f32 *S, uint32_t nbOfSupportVectors, + uint32_t vectorDimension, float32_t intercept, + const float32_t *dualCoefficients, const float32_t *supportVectors, + const int32_t *classes); /** * @brief SVM linear prediction @@ -161,10 +145,8 @@ void arm_svm_linear_init_f32(arm_svm_linear_instance_f32 *S, * @param[in] in Pointer to input vector * @param[out] pResult Decision value */ -void arm_svm_linear_predict_f32(const arm_svm_linear_instance_f32 *S, - const float32_t * in, - int32_t * pResult); - +void arm_svm_linear_predict_f32(const arm_svm_linear_instance_f32 *S, const float32_t *in, + int32_t *pResult); /** * @brief SVM polynomial instance init function @@ -179,18 +161,11 @@ void arm_svm_linear_predict_f32(const arm_svm_linear_instance_f32 *S, * @param[in] coef0 coeff0 (scikit-learn terminology) * @param[in] gamma gamma (scikit-learn terminology) */ -void arm_svm_polynomial_init_f32(arm_svm_polynomial_instance_f32 *S, - uint32_t nbOfSupportVectors, - uint32_t vectorDimension, - float32_t intercept, - const float32_t *dualCoefficients, - const float32_t *supportVectors, - const int32_t *classes, - int32_t degree, - float32_t coef0, - float32_t gamma - ); - +void arm_svm_polynomial_init_f32(arm_svm_polynomial_instance_f32 *S, uint32_t nbOfSupportVectors, + uint32_t vectorDimension, float32_t intercept, + const float32_t *dualCoefficients, const float32_t *supportVectors, + const int32_t *classes, int32_t degree, float32_t coef0, + float32_t gamma); /** * @brief SVM polynomial prediction @@ -198,10 +173,8 @@ void arm_svm_polynomial_init_f32(arm_svm_polynomial_instance_f32 *S, * @param[in] in Pointer to input vector * @param[out] pResult Decision value */ -void arm_svm_polynomial_predict_f32(const arm_svm_polynomial_instance_f32 *S, - const float32_t * in, - int32_t * pResult); - +void arm_svm_polynomial_predict_f32(const arm_svm_polynomial_instance_f32 *S, const float32_t *in, + int32_t *pResult); /** * @brief SVM radial basis function instance init function @@ -214,16 +187,10 @@ void arm_svm_polynomial_predict_f32(const arm_svm_polynomial_instance_f32 *S, * @param[in] classes Array of 2 classes ID * @param[in] gamma gamma (scikit-learn terminology) */ -void arm_svm_rbf_init_f32(arm_svm_rbf_instance_f32 *S, - uint32_t nbOfSupportVectors, - uint32_t vectorDimension, - float32_t intercept, - const float32_t *dualCoefficients, - const float32_t *supportVectors, - const int32_t *classes, - float32_t gamma - ); - +void arm_svm_rbf_init_f32(arm_svm_rbf_instance_f32 *S, uint32_t nbOfSupportVectors, + uint32_t vectorDimension, float32_t intercept, + const float32_t *dualCoefficients, const float32_t *supportVectors, + const int32_t *classes, float32_t gamma); /** * @brief SVM rbf prediction @@ -231,10 +198,8 @@ void arm_svm_rbf_init_f32(arm_svm_rbf_instance_f32 *S, * @param[in] in Pointer to input vector * @param[out] pResult decision value */ -void arm_svm_rbf_predict_f32(const arm_svm_rbf_instance_f32 *S, - const float32_t * in, - int32_t * pResult); - +void arm_svm_rbf_predict_f32(const arm_svm_rbf_instance_f32 *S, const float32_t *in, + int32_t *pResult); /** * @brief SVM sigmoid instance init function @@ -248,17 +213,10 @@ void arm_svm_rbf_predict_f32(const arm_svm_rbf_instance_f32 *S, * @param[in] coef0 coeff0 (scikit-learn terminology) * @param[in] gamma gamma (scikit-learn terminology) */ -void arm_svm_sigmoid_init_f32(arm_svm_sigmoid_instance_f32 *S, - uint32_t nbOfSupportVectors, - uint32_t vectorDimension, - float32_t intercept, - const float32_t *dualCoefficients, - const float32_t *supportVectors, - const int32_t *classes, - float32_t coef0, - float32_t gamma - ); - +void arm_svm_sigmoid_init_f32(arm_svm_sigmoid_instance_f32 *S, uint32_t nbOfSupportVectors, + uint32_t vectorDimension, float32_t intercept, + const float32_t *dualCoefficients, const float32_t *supportVectors, + const int32_t *classes, float32_t coef0, float32_t gamma); /** * @brief SVM sigmoid prediction @@ -266,14 +224,10 @@ void arm_svm_sigmoid_init_f32(arm_svm_sigmoid_instance_f32 *S, * @param[in] in Pointer to input vector * @param[out] pResult Decision value */ -void arm_svm_sigmoid_predict_f32(const arm_svm_sigmoid_instance_f32 *S, - const float32_t * in, - int32_t * pResult); - - - +void arm_svm_sigmoid_predict_f32(const arm_svm_sigmoid_instance_f32 *S, const float32_t *in, + int32_t *pResult); -#ifdef __cplusplus +#ifdef __cplusplus } #endif diff --git a/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/svm_functions_f16.h b/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/svm_functions_f16.h old mode 100755 new mode 100644 index 5f757a0a10d..eb03f4a8515 --- a/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/svm_functions_f16.h +++ b/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/svm_functions_f16.h @@ -23,7 +23,6 @@ * limitations under the License. */ - #ifndef SVM_FUNCTIONS_F16_H_ #define SVM_FUNCTIONS_F16_H_ @@ -34,10 +33,8 @@ #include "dsp/utils.h" #include "dsp/svm_defines.h" - -#ifdef __cplusplus -extern "C" -{ +#ifdef __cplusplus +extern "C" { #endif #if defined(ARM_FLOAT16_SUPPORTED) @@ -58,70 +55,60 @@ extern "C" * */ - - /** * @brief Instance structure for linear SVM prediction function. */ -typedef struct -{ - uint32_t nbOfSupportVectors; /**< Number of support vectors */ - uint32_t vectorDimension; /**< Dimension of vector space */ - float16_t intercept; /**< Intercept */ - const float16_t *dualCoefficients; /**< Dual coefficients */ - const float16_t *supportVectors; /**< Support vectors */ - const int32_t *classes; /**< The two SVM classes */ +typedef struct { + uint32_t nbOfSupportVectors; /**< Number of support vectors */ + uint32_t vectorDimension; /**< Dimension of vector space */ + float16_t intercept; /**< Intercept */ + const float16_t *dualCoefficients; /**< Dual coefficients */ + const float16_t *supportVectors; /**< Support vectors */ + const int32_t *classes; /**< The two SVM classes */ } arm_svm_linear_instance_f16; - /** * @brief Instance structure for polynomial SVM prediction function. */ -typedef struct -{ - uint32_t nbOfSupportVectors; /**< Number of support vectors */ - uint32_t vectorDimension; /**< Dimension of vector space */ - float16_t intercept; /**< Intercept */ - const float16_t *dualCoefficients; /**< Dual coefficients */ - const float16_t *supportVectors; /**< Support vectors */ - const int32_t *classes; /**< The two SVM classes */ - int32_t degree; /**< Polynomial degree */ - float16_t coef0; /**< Polynomial constant */ - float16_t gamma; /**< Gamma factor */ +typedef struct { + uint32_t nbOfSupportVectors; /**< Number of support vectors */ + uint32_t vectorDimension; /**< Dimension of vector space */ + float16_t intercept; /**< Intercept */ + const float16_t *dualCoefficients; /**< Dual coefficients */ + const float16_t *supportVectors; /**< Support vectors */ + const int32_t *classes; /**< The two SVM classes */ + int32_t degree; /**< Polynomial degree */ + float16_t coef0; /**< Polynomial constant */ + float16_t gamma; /**< Gamma factor */ } arm_svm_polynomial_instance_f16; - /** * @brief Instance structure for rbf SVM prediction function. */ -typedef struct -{ - uint32_t nbOfSupportVectors; /**< Number of support vectors */ - uint32_t vectorDimension; /**< Dimension of vector space */ - float16_t intercept; /**< Intercept */ - const float16_t *dualCoefficients; /**< Dual coefficients */ - const float16_t *supportVectors; /**< Support vectors */ - const int32_t *classes; /**< The two SVM classes */ - float16_t gamma; /**< Gamma factor */ +typedef struct { + uint32_t nbOfSupportVectors; /**< Number of support vectors */ + uint32_t vectorDimension; /**< Dimension of vector space */ + float16_t intercept; /**< Intercept */ + const float16_t *dualCoefficients; /**< Dual coefficients */ + const float16_t *supportVectors; /**< Support vectors */ + const int32_t *classes; /**< The two SVM classes */ + float16_t gamma; /**< Gamma factor */ } arm_svm_rbf_instance_f16; - /** * @brief Instance structure for sigmoid SVM prediction function. */ -typedef struct -{ - uint32_t nbOfSupportVectors; /**< Number of support vectors */ - uint32_t vectorDimension; /**< Dimension of vector space */ - float16_t intercept; /**< Intercept */ - const float16_t *dualCoefficients; /**< Dual coefficients */ - const float16_t *supportVectors; /**< Support vectors */ - const int32_t *classes; /**< The two SVM classes */ - float16_t coef0; /**< Independent constant */ - float16_t gamma; /**< Gamma factor */ +typedef struct { + uint32_t nbOfSupportVectors; /**< Number of support vectors */ + uint32_t vectorDimension; /**< Dimension of vector space */ + float16_t intercept; /**< Intercept */ + const float16_t *dualCoefficients; /**< Dual coefficients */ + const float16_t *supportVectors; /**< Support vectors */ + const int32_t *classes; /**< The two SVM classes */ + float16_t coef0; /**< Independent constant */ + float16_t gamma; /**< Gamma factor */ } arm_svm_sigmoid_instance_f16; - /** * @brief SVM linear instance init function * @param[in] S Parameters for SVM functions @@ -132,13 +119,10 @@ typedef struct * @param[in] supportVectors Array of support vectors * @param[in] classes Array of 2 classes ID */ -void arm_svm_linear_init_f16(arm_svm_linear_instance_f16 *S, - uint32_t nbOfSupportVectors, - uint32_t vectorDimension, - float16_t intercept, - const float16_t *dualCoefficients, - const float16_t *supportVectors, - const int32_t *classes); +void arm_svm_linear_init_f16(arm_svm_linear_instance_f16 *S, uint32_t nbOfSupportVectors, + uint32_t vectorDimension, float16_t intercept, + const float16_t *dualCoefficients, const float16_t *supportVectors, + const int32_t *classes); /** * @brief SVM linear prediction @@ -146,10 +130,8 @@ void arm_svm_linear_init_f16(arm_svm_linear_instance_f16 *S, * @param[in] in Pointer to input vector * @param[out] pResult Decision value */ -void arm_svm_linear_predict_f16(const arm_svm_linear_instance_f16 *S, - const float16_t * in, - int32_t * pResult); - +void arm_svm_linear_predict_f16(const arm_svm_linear_instance_f16 *S, const float16_t *in, + int32_t *pResult); /** * @brief SVM polynomial instance init function @@ -164,18 +146,11 @@ void arm_svm_linear_predict_f16(const arm_svm_linear_instance_f16 *S, * @param[in] coef0 coeff0 (scikit-learn terminology) * @param[in] gamma gamma (scikit-learn terminology) */ -void arm_svm_polynomial_init_f16(arm_svm_polynomial_instance_f16 *S, - uint32_t nbOfSupportVectors, - uint32_t vectorDimension, - float16_t intercept, - const float16_t *dualCoefficients, - const float16_t *supportVectors, - const int32_t *classes, - int32_t degree, - float16_t coef0, - float16_t gamma - ); - +void arm_svm_polynomial_init_f16(arm_svm_polynomial_instance_f16 *S, uint32_t nbOfSupportVectors, + uint32_t vectorDimension, float16_t intercept, + const float16_t *dualCoefficients, const float16_t *supportVectors, + const int32_t *classes, int32_t degree, float16_t coef0, + float16_t gamma); /** * @brief SVM polynomial prediction @@ -183,10 +158,8 @@ void arm_svm_polynomial_init_f16(arm_svm_polynomial_instance_f16 *S, * @param[in] in Pointer to input vector * @param[out] pResult Decision value */ -void arm_svm_polynomial_predict_f16(const arm_svm_polynomial_instance_f16 *S, - const float16_t * in, - int32_t * pResult); - +void arm_svm_polynomial_predict_f16(const arm_svm_polynomial_instance_f16 *S, const float16_t *in, + int32_t *pResult); /** * @brief SVM radial basis function instance init function @@ -199,16 +172,10 @@ void arm_svm_polynomial_predict_f16(const arm_svm_polynomial_instance_f16 *S, * @param[in] classes Array of 2 classes ID * @param[in] gamma gamma (scikit-learn terminology) */ -void arm_svm_rbf_init_f16(arm_svm_rbf_instance_f16 *S, - uint32_t nbOfSupportVectors, - uint32_t vectorDimension, - float16_t intercept, - const float16_t *dualCoefficients, - const float16_t *supportVectors, - const int32_t *classes, - float16_t gamma - ); - +void arm_svm_rbf_init_f16(arm_svm_rbf_instance_f16 *S, uint32_t nbOfSupportVectors, + uint32_t vectorDimension, float16_t intercept, + const float16_t *dualCoefficients, const float16_t *supportVectors, + const int32_t *classes, float16_t gamma); /** * @brief SVM rbf prediction @@ -216,10 +183,8 @@ void arm_svm_rbf_init_f16(arm_svm_rbf_instance_f16 *S, * @param[in] in Pointer to input vector * @param[out] pResult decision value */ -void arm_svm_rbf_predict_f16(const arm_svm_rbf_instance_f16 *S, - const float16_t * in, - int32_t * pResult); - +void arm_svm_rbf_predict_f16(const arm_svm_rbf_instance_f16 *S, const float16_t *in, + int32_t *pResult); /** * @brief SVM sigmoid instance init function @@ -233,17 +198,10 @@ void arm_svm_rbf_predict_f16(const arm_svm_rbf_instance_f16 *S, * @param[in] coef0 coeff0 (scikit-learn terminology) * @param[in] gamma gamma (scikit-learn terminology) */ -void arm_svm_sigmoid_init_f16(arm_svm_sigmoid_instance_f16 *S, - uint32_t nbOfSupportVectors, - uint32_t vectorDimension, - float16_t intercept, - const float16_t *dualCoefficients, - const float16_t *supportVectors, - const int32_t *classes, - float16_t coef0, - float16_t gamma - ); - +void arm_svm_sigmoid_init_f16(arm_svm_sigmoid_instance_f16 *S, uint32_t nbOfSupportVectors, + uint32_t vectorDimension, float16_t intercept, + const float16_t *dualCoefficients, const float16_t *supportVectors, + const int32_t *classes, float16_t coef0, float16_t gamma); /** * @brief SVM sigmoid prediction @@ -251,14 +209,11 @@ void arm_svm_sigmoid_init_f16(arm_svm_sigmoid_instance_f16 *S, * @param[in] in Pointer to input vector * @param[out] pResult Decision value */ -void arm_svm_sigmoid_predict_f16(const arm_svm_sigmoid_instance_f16 *S, - const float16_t * in, - int32_t * pResult); - - +void arm_svm_sigmoid_predict_f16(const arm_svm_sigmoid_instance_f16 *S, const float16_t *in, + int32_t *pResult); #endif /*defined(ARM_FLOAT16_SUPPORTED)*/ -#ifdef __cplusplus +#ifdef __cplusplus } #endif diff --git a/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/transform_functions.h b/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/transform_functions.h old mode 100755 new mode 100644 index b2c13d9dfcf..d325e321c45 --- a/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/transform_functions.h +++ b/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/transform_functions.h @@ -23,7 +23,6 @@ * limitations under the License. */ - #ifndef TRANSFORM_FUNCTIONS_H_ #define TRANSFORM_FUNCTIONS_H_ @@ -36,579 +35,479 @@ #include "dsp/basic_math_functions.h" #include "dsp/complex_math_functions.h" -#ifdef __cplusplus -extern "C" -{ +#ifdef __cplusplus +extern "C" { #endif - /** * @defgroup groupTransforms Transform Functions */ - - /** +/** * @brief Instance structure for the Q15 CFFT/CIFFT function. */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - const q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ - const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix2_instance_q15; +typedef struct { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t + ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t + bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + const q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t + twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t + bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ +} arm_cfft_radix2_instance_q15; /* Deprecated */ - arm_status arm_cfft_radix2_init_q15( - arm_cfft_radix2_instance_q15 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); +arm_status arm_cfft_radix2_init_q15(arm_cfft_radix2_instance_q15 *S, uint16_t fftLen, + uint8_t ifftFlag, uint8_t bitReverseFlag); /* Deprecated */ - void arm_cfft_radix2_q15( - const arm_cfft_radix2_instance_q15 * S, - q15_t * pSrc); +void arm_cfft_radix2_q15(const arm_cfft_radix2_instance_q15 *S, q15_t *pSrc); - - /** +/** * @brief Instance structure for the Q15 CFFT/CIFFT function. */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - const q15_t *pTwiddle; /**< points to the twiddle factor table. */ - const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix4_instance_q15; +typedef struct { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t + ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t + bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + const q15_t *pTwiddle; /**< points to the twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t + twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t + bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ +} arm_cfft_radix4_instance_q15; /* Deprecated */ - arm_status arm_cfft_radix4_init_q15( - arm_cfft_radix4_instance_q15 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); +arm_status arm_cfft_radix4_init_q15(arm_cfft_radix4_instance_q15 *S, uint16_t fftLen, + uint8_t ifftFlag, uint8_t bitReverseFlag); /* Deprecated */ - void arm_cfft_radix4_q15( - const arm_cfft_radix4_instance_q15 * S, - q15_t * pSrc); +void arm_cfft_radix4_q15(const arm_cfft_radix4_instance_q15 *S, q15_t *pSrc); - /** +/** * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ - const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix2_instance_q31; +typedef struct { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t + ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t + bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t + twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t + bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ +} arm_cfft_radix2_instance_q31; /* Deprecated */ - arm_status arm_cfft_radix2_init_q31( - arm_cfft_radix2_instance_q31 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); +arm_status arm_cfft_radix2_init_q31(arm_cfft_radix2_instance_q31 *S, uint16_t fftLen, + uint8_t ifftFlag, uint8_t bitReverseFlag); /* Deprecated */ - void arm_cfft_radix2_q31( - const arm_cfft_radix2_instance_q31 * S, - q31_t * pSrc); +void arm_cfft_radix2_q31(const arm_cfft_radix2_instance_q31 *S, q31_t *pSrc); - /** +/** * @brief Instance structure for the Q31 CFFT/CIFFT function. */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - const q31_t *pTwiddle; /**< points to the twiddle factor table. */ - const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix4_instance_q31; +typedef struct { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t + ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t + bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + const q31_t *pTwiddle; /**< points to the twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t + twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t + bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ +} arm_cfft_radix4_instance_q31; /* Deprecated */ - void arm_cfft_radix4_q31( - const arm_cfft_radix4_instance_q31 * S, - q31_t * pSrc); +void arm_cfft_radix4_q31(const arm_cfft_radix4_instance_q31 *S, q31_t *pSrc); /* Deprecated */ - arm_status arm_cfft_radix4_init_q31( - arm_cfft_radix4_instance_q31 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); +arm_status arm_cfft_radix4_init_q31(arm_cfft_radix4_instance_q31 *S, uint16_t fftLen, + uint8_t ifftFlag, uint8_t bitReverseFlag); - /** +/** * @brief Instance structure for the floating-point CFFT/CIFFT function. */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ - const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - float32_t onebyfftLen; /**< value of 1/fftLen. */ - } arm_cfft_radix2_instance_f32; - +typedef struct { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t + ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t + bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t + twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t + bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ +} arm_cfft_radix2_instance_f32; /* Deprecated */ - arm_status arm_cfft_radix2_init_f32( - arm_cfft_radix2_instance_f32 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); +arm_status arm_cfft_radix2_init_f32(arm_cfft_radix2_instance_f32 *S, uint16_t fftLen, + uint8_t ifftFlag, uint8_t bitReverseFlag); /* Deprecated */ - void arm_cfft_radix2_f32( - const arm_cfft_radix2_instance_f32 * S, - float32_t * pSrc); +void arm_cfft_radix2_f32(const arm_cfft_radix2_instance_f32 *S, float32_t *pSrc); - /** +/** * @brief Instance structure for the floating-point CFFT/CIFFT function. */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ - const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - float32_t onebyfftLen; /**< value of 1/fftLen. */ - } arm_cfft_radix4_instance_f32; - - +typedef struct { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t + ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t + bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t + twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t + bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ +} arm_cfft_radix4_instance_f32; /* Deprecated */ - arm_status arm_cfft_radix4_init_f32( - arm_cfft_radix4_instance_f32 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); +arm_status arm_cfft_radix4_init_f32(arm_cfft_radix4_instance_f32 *S, uint16_t fftLen, + uint8_t ifftFlag, uint8_t bitReverseFlag); /* Deprecated */ - void arm_cfft_radix4_f32( - const arm_cfft_radix4_instance_f32 * S, - float32_t * pSrc); +void arm_cfft_radix4_f32(const arm_cfft_radix4_instance_f32 *S, float32_t *pSrc); - /** +/** * @brief Instance structure for the fixed-point CFFT/CIFFT function. */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - const q15_t *pTwiddle; /**< points to the Twiddle factor table. */ - const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t bitRevLength; /**< bit reversal table length. */ +typedef struct { + uint16_t fftLen; /**< length of the FFT. */ + const q15_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ #if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) - const uint32_t *rearranged_twiddle_tab_stride1_arr; /**< Per stage reordered twiddle pointer (offset 1) */ \ - const uint32_t *rearranged_twiddle_tab_stride2_arr; /**< Per stage reordered twiddle pointer (offset 2) */ \ - const uint32_t *rearranged_twiddle_tab_stride3_arr; /**< Per stage reordered twiddle pointer (offset 3) */ \ - const q15_t *rearranged_twiddle_stride1; /**< reordered twiddle offset 1 storage */ \ - const q15_t *rearranged_twiddle_stride2; /**< reordered twiddle offset 2 storage */ \ - const q15_t *rearranged_twiddle_stride3; + const uint32_t + *rearranged_twiddle_tab_stride1_arr; /**< Per stage reordered twiddle pointer (offset 1) */ + const uint32_t + *rearranged_twiddle_tab_stride2_arr; /**< Per stage reordered twiddle pointer (offset 2) */ + const uint32_t + *rearranged_twiddle_tab_stride3_arr; /**< Per stage reordered twiddle pointer (offset 3) */ + const q15_t *rearranged_twiddle_stride1; /**< reordered twiddle offset 1 storage */ + const q15_t *rearranged_twiddle_stride2; /**< reordered twiddle offset 2 storage */ + const q15_t *rearranged_twiddle_stride3; #endif - } arm_cfft_instance_q15; - -arm_status arm_cfft_init_4096_q15(arm_cfft_instance_q15 * S); -arm_status arm_cfft_init_2048_q15(arm_cfft_instance_q15 * S); -arm_status arm_cfft_init_1024_q15(arm_cfft_instance_q15 * S); -arm_status arm_cfft_init_512_q15(arm_cfft_instance_q15 * S); -arm_status arm_cfft_init_256_q15(arm_cfft_instance_q15 * S); -arm_status arm_cfft_init_128_q15(arm_cfft_instance_q15 * S); -arm_status arm_cfft_init_64_q15(arm_cfft_instance_q15 * S); -arm_status arm_cfft_init_32_q15(arm_cfft_instance_q15 * S); -arm_status arm_cfft_init_16_q15(arm_cfft_instance_q15 * S); - -arm_status arm_cfft_init_q15( - arm_cfft_instance_q15 * S, - uint16_t fftLen); - -void arm_cfft_q15( - const arm_cfft_instance_q15 * S, - q15_t * p1, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** +} arm_cfft_instance_q15; + +arm_status arm_cfft_init_4096_q15(arm_cfft_instance_q15 *S); +arm_status arm_cfft_init_2048_q15(arm_cfft_instance_q15 *S); +arm_status arm_cfft_init_1024_q15(arm_cfft_instance_q15 *S); +arm_status arm_cfft_init_512_q15(arm_cfft_instance_q15 *S); +arm_status arm_cfft_init_256_q15(arm_cfft_instance_q15 *S); +arm_status arm_cfft_init_128_q15(arm_cfft_instance_q15 *S); +arm_status arm_cfft_init_64_q15(arm_cfft_instance_q15 *S); +arm_status arm_cfft_init_32_q15(arm_cfft_instance_q15 *S); +arm_status arm_cfft_init_16_q15(arm_cfft_instance_q15 *S); + +arm_status arm_cfft_init_q15(arm_cfft_instance_q15 *S, uint16_t fftLen); + +void arm_cfft_q15(const arm_cfft_instance_q15 *S, q15_t *p1, uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/** * @brief Instance structure for the fixed-point CFFT/CIFFT function. */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ - const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t bitRevLength; /**< bit reversal table length. */ +typedef struct { + uint16_t fftLen; /**< length of the FFT. */ + const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ #if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) - const uint32_t *rearranged_twiddle_tab_stride1_arr; /**< Per stage reordered twiddle pointer (offset 1) */ \ - const uint32_t *rearranged_twiddle_tab_stride2_arr; /**< Per stage reordered twiddle pointer (offset 2) */ \ - const uint32_t *rearranged_twiddle_tab_stride3_arr; /**< Per stage reordered twiddle pointer (offset 3) */ \ - const q31_t *rearranged_twiddle_stride1; /**< reordered twiddle offset 1 storage */ \ - const q31_t *rearranged_twiddle_stride2; /**< reordered twiddle offset 2 storage */ \ - const q31_t *rearranged_twiddle_stride3; + const uint32_t + *rearranged_twiddle_tab_stride1_arr; /**< Per stage reordered twiddle pointer (offset 1) */ + const uint32_t + *rearranged_twiddle_tab_stride2_arr; /**< Per stage reordered twiddle pointer (offset 2) */ + const uint32_t + *rearranged_twiddle_tab_stride3_arr; /**< Per stage reordered twiddle pointer (offset 3) */ + const q31_t *rearranged_twiddle_stride1; /**< reordered twiddle offset 1 storage */ + const q31_t *rearranged_twiddle_stride2; /**< reordered twiddle offset 2 storage */ + const q31_t *rearranged_twiddle_stride3; #endif - } arm_cfft_instance_q31; - -arm_status arm_cfft_init_4096_q31(arm_cfft_instance_q31 * S); -arm_status arm_cfft_init_2048_q31(arm_cfft_instance_q31 * S); -arm_status arm_cfft_init_1024_q31(arm_cfft_instance_q31 * S); -arm_status arm_cfft_init_512_q31(arm_cfft_instance_q31 * S); -arm_status arm_cfft_init_256_q31(arm_cfft_instance_q31 * S); -arm_status arm_cfft_init_128_q31(arm_cfft_instance_q31 * S); -arm_status arm_cfft_init_64_q31(arm_cfft_instance_q31 * S); -arm_status arm_cfft_init_32_q31(arm_cfft_instance_q31 * S); -arm_status arm_cfft_init_16_q31(arm_cfft_instance_q31 * S); - -arm_status arm_cfft_init_q31( - arm_cfft_instance_q31 * S, - uint16_t fftLen); - -void arm_cfft_q31( - const arm_cfft_instance_q31 * S, - q31_t * p1, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** +} arm_cfft_instance_q31; + +arm_status arm_cfft_init_4096_q31(arm_cfft_instance_q31 *S); +arm_status arm_cfft_init_2048_q31(arm_cfft_instance_q31 *S); +arm_status arm_cfft_init_1024_q31(arm_cfft_instance_q31 *S); +arm_status arm_cfft_init_512_q31(arm_cfft_instance_q31 *S); +arm_status arm_cfft_init_256_q31(arm_cfft_instance_q31 *S); +arm_status arm_cfft_init_128_q31(arm_cfft_instance_q31 *S); +arm_status arm_cfft_init_64_q31(arm_cfft_instance_q31 *S); +arm_status arm_cfft_init_32_q31(arm_cfft_instance_q31 *S); +arm_status arm_cfft_init_16_q31(arm_cfft_instance_q31 *S); + +arm_status arm_cfft_init_q31(arm_cfft_instance_q31 *S, uint16_t fftLen); + +void arm_cfft_q31(const arm_cfft_instance_q31 *S, q31_t *p1, uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/** * @brief Instance structure for the floating-point CFFT/CIFFT function. */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ - const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t bitRevLength; /**< bit reversal table length. */ +typedef struct { + uint16_t fftLen; /**< length of the FFT. */ + const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ #if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) - const uint32_t *rearranged_twiddle_tab_stride1_arr; /**< Per stage reordered twiddle pointer (offset 1) */ \ - const uint32_t *rearranged_twiddle_tab_stride2_arr; /**< Per stage reordered twiddle pointer (offset 2) */ \ - const uint32_t *rearranged_twiddle_tab_stride3_arr; /**< Per stage reordered twiddle pointer (offset 3) */ \ - const float32_t *rearranged_twiddle_stride1; /**< reordered twiddle offset 1 storage */ \ - const float32_t *rearranged_twiddle_stride2; /**< reordered twiddle offset 2 storage */ \ - const float32_t *rearranged_twiddle_stride3; + const uint32_t + *rearranged_twiddle_tab_stride1_arr; /**< Per stage reordered twiddle pointer (offset 1) */ + const uint32_t + *rearranged_twiddle_tab_stride2_arr; /**< Per stage reordered twiddle pointer (offset 2) */ + const uint32_t + *rearranged_twiddle_tab_stride3_arr; /**< Per stage reordered twiddle pointer (offset 3) */ + const float32_t *rearranged_twiddle_stride1; /**< reordered twiddle offset 1 storage */ + const float32_t *rearranged_twiddle_stride2; /**< reordered twiddle offset 2 storage */ + const float32_t *rearranged_twiddle_stride3; #endif - } arm_cfft_instance_f32; - - -arm_status arm_cfft_init_4096_f32(arm_cfft_instance_f32 * S); -arm_status arm_cfft_init_2048_f32(arm_cfft_instance_f32 * S); -arm_status arm_cfft_init_1024_f32(arm_cfft_instance_f32 * S); -arm_status arm_cfft_init_512_f32(arm_cfft_instance_f32 * S); -arm_status arm_cfft_init_256_f32(arm_cfft_instance_f32 * S); -arm_status arm_cfft_init_128_f32(arm_cfft_instance_f32 * S); -arm_status arm_cfft_init_64_f32(arm_cfft_instance_f32 * S); -arm_status arm_cfft_init_32_f32(arm_cfft_instance_f32 * S); -arm_status arm_cfft_init_16_f32(arm_cfft_instance_f32 * S); +} arm_cfft_instance_f32; - arm_status arm_cfft_init_f32( - arm_cfft_instance_f32 * S, - uint16_t fftLen); +arm_status arm_cfft_init_4096_f32(arm_cfft_instance_f32 *S); +arm_status arm_cfft_init_2048_f32(arm_cfft_instance_f32 *S); +arm_status arm_cfft_init_1024_f32(arm_cfft_instance_f32 *S); +arm_status arm_cfft_init_512_f32(arm_cfft_instance_f32 *S); +arm_status arm_cfft_init_256_f32(arm_cfft_instance_f32 *S); +arm_status arm_cfft_init_128_f32(arm_cfft_instance_f32 *S); +arm_status arm_cfft_init_64_f32(arm_cfft_instance_f32 *S); +arm_status arm_cfft_init_32_f32(arm_cfft_instance_f32 *S); +arm_status arm_cfft_init_16_f32(arm_cfft_instance_f32 *S); - void arm_cfft_f32( - const arm_cfft_instance_f32 * S, - float32_t * p1, - uint8_t ifftFlag, - uint8_t bitReverseFlag); +arm_status arm_cfft_init_f32(arm_cfft_instance_f32 *S, uint16_t fftLen); +void arm_cfft_f32(const arm_cfft_instance_f32 *S, float32_t *p1, uint8_t ifftFlag, + uint8_t bitReverseFlag); - /** +/** * @brief Instance structure for the Double Precision Floating-point CFFT/CIFFT function. */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - const float64_t *pTwiddle; /**< points to the Twiddle factor table. */ - const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t bitRevLength; /**< bit reversal table length. */ - } arm_cfft_instance_f64; - -arm_status arm_cfft_init_4096_f64(arm_cfft_instance_f64 * S); -arm_status arm_cfft_init_2048_f64(arm_cfft_instance_f64 * S); -arm_status arm_cfft_init_1024_f64(arm_cfft_instance_f64 * S); -arm_status arm_cfft_init_512_f64(arm_cfft_instance_f64 * S); -arm_status arm_cfft_init_256_f64(arm_cfft_instance_f64 * S); -arm_status arm_cfft_init_128_f64(arm_cfft_instance_f64 * S); -arm_status arm_cfft_init_64_f64(arm_cfft_instance_f64 * S); -arm_status arm_cfft_init_32_f64(arm_cfft_instance_f64 * S); -arm_status arm_cfft_init_16_f64(arm_cfft_instance_f64 * S); - - arm_status arm_cfft_init_f64( - arm_cfft_instance_f64 * S, - uint16_t fftLen); - - void arm_cfft_f64( - const arm_cfft_instance_f64 * S, - float64_t * p1, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** +typedef struct { + uint16_t fftLen; /**< length of the FFT. */ + const float64_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ +} arm_cfft_instance_f64; + +arm_status arm_cfft_init_4096_f64(arm_cfft_instance_f64 *S); +arm_status arm_cfft_init_2048_f64(arm_cfft_instance_f64 *S); +arm_status arm_cfft_init_1024_f64(arm_cfft_instance_f64 *S); +arm_status arm_cfft_init_512_f64(arm_cfft_instance_f64 *S); +arm_status arm_cfft_init_256_f64(arm_cfft_instance_f64 *S); +arm_status arm_cfft_init_128_f64(arm_cfft_instance_f64 *S); +arm_status arm_cfft_init_64_f64(arm_cfft_instance_f64 *S); +arm_status arm_cfft_init_32_f64(arm_cfft_instance_f64 *S); +arm_status arm_cfft_init_16_f64(arm_cfft_instance_f64 *S); + +arm_status arm_cfft_init_f64(arm_cfft_instance_f64 *S, uint16_t fftLen); + +void arm_cfft_f64(const arm_cfft_instance_f64 *S, float64_t *p1, uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/** * @brief Instance structure for the Q15 RFFT/RIFFT function. */ - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - const q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - const q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ +typedef struct { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t + ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t + bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t + twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + const q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + const q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ #if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) arm_cfft_instance_q15 cfftInst; #else - const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */ #endif - } arm_rfft_instance_q15; - -arm_status arm_rfft_init_32_q15( - arm_rfft_instance_q15 * S, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - -arm_status arm_rfft_init_64_q15( - arm_rfft_instance_q15 * S, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - -arm_status arm_rfft_init_128_q15( - arm_rfft_instance_q15 * S, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - -arm_status arm_rfft_init_256_q15( - arm_rfft_instance_q15 * S, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - -arm_status arm_rfft_init_512_q15( - arm_rfft_instance_q15 * S, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - -arm_status arm_rfft_init_1024_q15( - arm_rfft_instance_q15 * S, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - -arm_status arm_rfft_init_2048_q15( - arm_rfft_instance_q15 * S, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - -arm_status arm_rfft_init_4096_q15( - arm_rfft_instance_q15 * S, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - -arm_status arm_rfft_init_8192_q15( - arm_rfft_instance_q15 * S, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - arm_status arm_rfft_init_q15( - arm_rfft_instance_q15 * S, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - void arm_rfft_q15( - const arm_rfft_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst); - - /** +} arm_rfft_instance_q15; + +arm_status arm_rfft_init_32_q15(arm_rfft_instance_q15 *S, uint32_t ifftFlagR, + uint32_t bitReverseFlag); + +arm_status arm_rfft_init_64_q15(arm_rfft_instance_q15 *S, uint32_t ifftFlagR, + uint32_t bitReverseFlag); + +arm_status arm_rfft_init_128_q15(arm_rfft_instance_q15 *S, uint32_t ifftFlagR, + uint32_t bitReverseFlag); + +arm_status arm_rfft_init_256_q15(arm_rfft_instance_q15 *S, uint32_t ifftFlagR, + uint32_t bitReverseFlag); + +arm_status arm_rfft_init_512_q15(arm_rfft_instance_q15 *S, uint32_t ifftFlagR, + uint32_t bitReverseFlag); + +arm_status arm_rfft_init_1024_q15(arm_rfft_instance_q15 *S, uint32_t ifftFlagR, + uint32_t bitReverseFlag); + +arm_status arm_rfft_init_2048_q15(arm_rfft_instance_q15 *S, uint32_t ifftFlagR, + uint32_t bitReverseFlag); + +arm_status arm_rfft_init_4096_q15(arm_rfft_instance_q15 *S, uint32_t ifftFlagR, + uint32_t bitReverseFlag); + +arm_status arm_rfft_init_8192_q15(arm_rfft_instance_q15 *S, uint32_t ifftFlagR, + uint32_t bitReverseFlag); + +arm_status arm_rfft_init_q15(arm_rfft_instance_q15 *S, uint32_t fftLenReal, uint32_t ifftFlagR, + uint32_t bitReverseFlag); + +void arm_rfft_q15(const arm_rfft_instance_q15 *S, q15_t *pSrc, q15_t *pDst); + +/** * @brief Instance structure for the Q31 RFFT/RIFFT function. */ - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - const q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - const q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ +typedef struct { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t + ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t + bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t + twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + const q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + const q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ #if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) arm_cfft_instance_q31 cfftInst; #else - const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */ #endif - } arm_rfft_instance_q31; - - arm_status arm_rfft_init_32_q31( - arm_rfft_instance_q31 * S, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - arm_status arm_rfft_init_64_q31( - arm_rfft_instance_q31 * S, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - arm_status arm_rfft_init_128_q31( - arm_rfft_instance_q31 * S, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - arm_status arm_rfft_init_256_q31( - arm_rfft_instance_q31 * S, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - arm_status arm_rfft_init_512_q31( - arm_rfft_instance_q31 * S, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - arm_status arm_rfft_init_1024_q31( - arm_rfft_instance_q31 * S, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - arm_status arm_rfft_init_2048_q31( - arm_rfft_instance_q31 * S, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - arm_status arm_rfft_init_4096_q31( - arm_rfft_instance_q31 * S, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - arm_status arm_rfft_init_8192_q31( - arm_rfft_instance_q31 * S, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - arm_status arm_rfft_init_q31( - arm_rfft_instance_q31 * S, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - void arm_rfft_q31( - const arm_rfft_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst); - - /** +} arm_rfft_instance_q31; + +arm_status arm_rfft_init_32_q31(arm_rfft_instance_q31 *S, uint32_t ifftFlagR, + uint32_t bitReverseFlag); + +arm_status arm_rfft_init_64_q31(arm_rfft_instance_q31 *S, uint32_t ifftFlagR, + uint32_t bitReverseFlag); + +arm_status arm_rfft_init_128_q31(arm_rfft_instance_q31 *S, uint32_t ifftFlagR, + uint32_t bitReverseFlag); + +arm_status arm_rfft_init_256_q31(arm_rfft_instance_q31 *S, uint32_t ifftFlagR, + uint32_t bitReverseFlag); + +arm_status arm_rfft_init_512_q31(arm_rfft_instance_q31 *S, uint32_t ifftFlagR, + uint32_t bitReverseFlag); + +arm_status arm_rfft_init_1024_q31(arm_rfft_instance_q31 *S, uint32_t ifftFlagR, + uint32_t bitReverseFlag); + +arm_status arm_rfft_init_2048_q31(arm_rfft_instance_q31 *S, uint32_t ifftFlagR, + uint32_t bitReverseFlag); + +arm_status arm_rfft_init_4096_q31(arm_rfft_instance_q31 *S, uint32_t ifftFlagR, + uint32_t bitReverseFlag); + +arm_status arm_rfft_init_8192_q31(arm_rfft_instance_q31 *S, uint32_t ifftFlagR, + uint32_t bitReverseFlag); + +arm_status arm_rfft_init_q31(arm_rfft_instance_q31 *S, uint32_t fftLenReal, uint32_t ifftFlagR, + uint32_t bitReverseFlag); + +void arm_rfft_q31(const arm_rfft_instance_q31 *S, q31_t *pSrc, q31_t *pDst); + +/** * @brief Instance structure for the floating-point RFFT/RIFFT function. */ - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint16_t fftLenBy2; /**< length of the complex FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - const float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - const float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ - } arm_rfft_instance_f32; - - arm_status arm_rfft_init_f32( - arm_rfft_instance_f32 * S, - arm_cfft_radix4_instance_f32 * S_CFFT, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - void arm_rfft_f32( - const arm_rfft_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst); - - /** +typedef struct { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint16_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t + ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t + bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t + twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + const float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + const float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ +} arm_rfft_instance_f32; + +arm_status arm_rfft_init_f32(arm_rfft_instance_f32 *S, arm_cfft_radix4_instance_f32 *S_CFFT, + uint32_t fftLenReal, uint32_t ifftFlagR, uint32_t bitReverseFlag); + +void arm_rfft_f32(const arm_rfft_instance_f32 *S, float32_t *pSrc, float32_t *pDst); + +/** * @brief Instance structure for the Double Precision Floating-point RFFT/RIFFT function. */ -typedef struct - { - arm_cfft_instance_f64 Sint; /**< Internal CFFT structure. */ - uint16_t fftLenRFFT; /**< length of the real sequence */ - const float64_t * pTwiddleRFFT; /**< Twiddle factors real stage */ - } arm_rfft_fast_instance_f64 ; - -arm_status arm_rfft_fast_init_32_f64( arm_rfft_fast_instance_f64 * S ); -arm_status arm_rfft_fast_init_64_f64( arm_rfft_fast_instance_f64 * S ); -arm_status arm_rfft_fast_init_128_f64( arm_rfft_fast_instance_f64 * S ); -arm_status arm_rfft_fast_init_256_f64( arm_rfft_fast_instance_f64 * S ); -arm_status arm_rfft_fast_init_512_f64( arm_rfft_fast_instance_f64 * S ); -arm_status arm_rfft_fast_init_1024_f64( arm_rfft_fast_instance_f64 * S ); -arm_status arm_rfft_fast_init_2048_f64( arm_rfft_fast_instance_f64 * S ); -arm_status arm_rfft_fast_init_4096_f64( arm_rfft_fast_instance_f64 * S ); - -arm_status arm_rfft_fast_init_f64 ( - arm_rfft_fast_instance_f64 * S, - uint16_t fftLen); - - -void arm_rfft_fast_f64( - arm_rfft_fast_instance_f64 * S, - float64_t * p, float64_t * pOut, - uint8_t ifftFlag); - - - /** +typedef struct { + arm_cfft_instance_f64 Sint; /**< Internal CFFT structure. */ + uint16_t fftLenRFFT; /**< length of the real sequence */ + const float64_t *pTwiddleRFFT; /**< Twiddle factors real stage */ +} arm_rfft_fast_instance_f64; + +arm_status arm_rfft_fast_init_32_f64(arm_rfft_fast_instance_f64 *S); +arm_status arm_rfft_fast_init_64_f64(arm_rfft_fast_instance_f64 *S); +arm_status arm_rfft_fast_init_128_f64(arm_rfft_fast_instance_f64 *S); +arm_status arm_rfft_fast_init_256_f64(arm_rfft_fast_instance_f64 *S); +arm_status arm_rfft_fast_init_512_f64(arm_rfft_fast_instance_f64 *S); +arm_status arm_rfft_fast_init_1024_f64(arm_rfft_fast_instance_f64 *S); +arm_status arm_rfft_fast_init_2048_f64(arm_rfft_fast_instance_f64 *S); +arm_status arm_rfft_fast_init_4096_f64(arm_rfft_fast_instance_f64 *S); + +arm_status arm_rfft_fast_init_f64(arm_rfft_fast_instance_f64 *S, uint16_t fftLen); + +void arm_rfft_fast_f64(arm_rfft_fast_instance_f64 *S, float64_t *p, float64_t *pOut, + uint8_t ifftFlag); + +/** * @brief Instance structure for the floating-point RFFT/RIFFT function. */ -typedef struct - { - arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ - uint16_t fftLenRFFT; /**< length of the real sequence */ - const float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */ - } arm_rfft_fast_instance_f32 ; - -arm_status arm_rfft_fast_init_32_f32( arm_rfft_fast_instance_f32 * S ); -arm_status arm_rfft_fast_init_64_f32( arm_rfft_fast_instance_f32 * S ); -arm_status arm_rfft_fast_init_128_f32( arm_rfft_fast_instance_f32 * S ); -arm_status arm_rfft_fast_init_256_f32( arm_rfft_fast_instance_f32 * S ); -arm_status arm_rfft_fast_init_512_f32( arm_rfft_fast_instance_f32 * S ); -arm_status arm_rfft_fast_init_1024_f32( arm_rfft_fast_instance_f32 * S ); -arm_status arm_rfft_fast_init_2048_f32( arm_rfft_fast_instance_f32 * S ); -arm_status arm_rfft_fast_init_4096_f32( arm_rfft_fast_instance_f32 * S ); - -arm_status arm_rfft_fast_init_f32 ( - arm_rfft_fast_instance_f32 * S, - uint16_t fftLen); - - - void arm_rfft_fast_f32( - const arm_rfft_fast_instance_f32 * S, - float32_t * p, float32_t * pOut, - uint8_t ifftFlag); - - /** +typedef struct { + arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ + uint16_t fftLenRFFT; /**< length of the real sequence */ + const float32_t *pTwiddleRFFT; /**< Twiddle factors real stage */ +} arm_rfft_fast_instance_f32; + +arm_status arm_rfft_fast_init_32_f32(arm_rfft_fast_instance_f32 *S); +arm_status arm_rfft_fast_init_64_f32(arm_rfft_fast_instance_f32 *S); +arm_status arm_rfft_fast_init_128_f32(arm_rfft_fast_instance_f32 *S); +arm_status arm_rfft_fast_init_256_f32(arm_rfft_fast_instance_f32 *S); +arm_status arm_rfft_fast_init_512_f32(arm_rfft_fast_instance_f32 *S); +arm_status arm_rfft_fast_init_1024_f32(arm_rfft_fast_instance_f32 *S); +arm_status arm_rfft_fast_init_2048_f32(arm_rfft_fast_instance_f32 *S); +arm_status arm_rfft_fast_init_4096_f32(arm_rfft_fast_instance_f32 *S); + +arm_status arm_rfft_fast_init_f32(arm_rfft_fast_instance_f32 *S, uint16_t fftLen); + +void arm_rfft_fast_f32(const arm_rfft_fast_instance_f32 *S, float32_t *p, float32_t *pOut, + uint8_t ifftFlag); + +/** * @brief Instance structure for the floating-point DCT4/IDCT4 function. */ - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - float32_t normalize; /**< normalizing factor. */ - const float32_t *pTwiddle; /**< points to the twiddle factor table. */ - const float32_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_f32; - - - /** +typedef struct { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + float32_t normalize; /**< normalizing factor. */ + const float32_t *pTwiddle; /**< points to the twiddle factor table. */ + const float32_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ +} arm_dct4_instance_f32; + +/** * @brief Initialization function for the floating-point DCT4/IDCT4. * @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure. * @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure. @@ -618,43 +517,32 @@ arm_status arm_rfft_fast_init_f32 ( * @param[in] normalize normalizing factor. * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. */ - arm_status arm_dct4_init_f32( - arm_dct4_instance_f32 * S, - arm_rfft_instance_f32 * S_RFFT, - arm_cfft_radix4_instance_f32 * S_CFFT, - uint16_t N, - uint16_t Nby2, - float32_t normalize); +arm_status arm_dct4_init_f32(arm_dct4_instance_f32 *S, arm_rfft_instance_f32 *S_RFFT, + arm_cfft_radix4_instance_f32 *S_CFFT, uint16_t N, uint16_t Nby2, + float32_t normalize); - - /** +/** * @brief Processing function for the floating-point DCT4/IDCT4. * @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure. * @param[in] pState points to state buffer. * @param[in,out] pInlineBuffer points to the in-place input and output buffer. */ - void arm_dct4_f32( - const arm_dct4_instance_f32 * S, - float32_t * pState, - float32_t * pInlineBuffer); +void arm_dct4_f32(const arm_dct4_instance_f32 *S, float32_t *pState, float32_t *pInlineBuffer); - - /** +/** * @brief Instance structure for the Q31 DCT4/IDCT4 function. */ - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - q31_t normalize; /**< normalizing factor. */ - const q31_t *pTwiddle; /**< points to the twiddle factor table. */ - const q31_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_q31; - - - /** +typedef struct { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q31_t normalize; /**< normalizing factor. */ + const q31_t *pTwiddle; /**< points to the twiddle factor table. */ + const q31_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ +} arm_dct4_instance_q31; + +/** * @brief Initialization function for the Q31 DCT4/IDCT4. * @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure. * @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure @@ -664,43 +552,32 @@ arm_status arm_rfft_fast_init_f32 ( * @param[in] normalize normalizing factor. * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. */ - arm_status arm_dct4_init_q31( - arm_dct4_instance_q31 * S, - arm_rfft_instance_q31 * S_RFFT, - arm_cfft_radix4_instance_q31 * S_CFFT, - uint16_t N, - uint16_t Nby2, - q31_t normalize); - +arm_status arm_dct4_init_q31(arm_dct4_instance_q31 *S, arm_rfft_instance_q31 *S_RFFT, + arm_cfft_radix4_instance_q31 *S_CFFT, uint16_t N, uint16_t Nby2, + q31_t normalize); - /** +/** * @brief Processing function for the Q31 DCT4/IDCT4. * @param[in] S points to an instance of the Q31 DCT4 structure. * @param[in] pState points to state buffer. * @param[in,out] pInlineBuffer points to the in-place input and output buffer. */ - void arm_dct4_q31( - const arm_dct4_instance_q31 * S, - q31_t * pState, - q31_t * pInlineBuffer); +void arm_dct4_q31(const arm_dct4_instance_q31 *S, q31_t *pState, q31_t *pInlineBuffer); - - /** +/** * @brief Instance structure for the Q15 DCT4/IDCT4 function. */ - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - q15_t normalize; /**< normalizing factor. */ - const q15_t *pTwiddle; /**< points to the twiddle factor table. */ - const q15_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_q15; - - - /** +typedef struct { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q15_t normalize; /**< normalizing factor. */ + const q15_t *pTwiddle; /**< points to the twiddle factor table. */ + const q15_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ +} arm_dct4_instance_q15; + +/** * @brief Initialization function for the Q15 DCT4/IDCT4. * @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure. * @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure. @@ -710,148 +587,83 @@ arm_status arm_rfft_fast_init_f32 ( * @param[in] normalize normalizing factor. * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. */ - arm_status arm_dct4_init_q15( - arm_dct4_instance_q15 * S, - arm_rfft_instance_q15 * S_RFFT, - arm_cfft_radix4_instance_q15 * S_CFFT, - uint16_t N, - uint16_t Nby2, - q15_t normalize); - +arm_status arm_dct4_init_q15(arm_dct4_instance_q15 *S, arm_rfft_instance_q15 *S_RFFT, + arm_cfft_radix4_instance_q15 *S_CFFT, uint16_t N, uint16_t Nby2, + q15_t normalize); - /** +/** * @brief Processing function for the Q15 DCT4/IDCT4. * @param[in] S points to an instance of the Q15 DCT4 structure. * @param[in] pState points to state buffer. * @param[in,out] pInlineBuffer points to the in-place input and output buffer. */ - void arm_dct4_q15( - const arm_dct4_instance_q15 * S, - q15_t * pState, - q15_t * pInlineBuffer); +void arm_dct4_q15(const arm_dct4_instance_q15 *S, q15_t *pState, q15_t *pInlineBuffer); - /** +/** * @brief Instance structure for the Floating-point MFCC function. */ -typedef struct - { - const float32_t *dctCoefs; /**< Internal DCT coefficients */ - const float32_t *filterCoefs; /**< Internal Mel filter coefficients */ - const float32_t *windowCoefs; /**< Windowing coefficients */ - const uint32_t *filterPos; /**< Internal Mel filter positions in spectrum */ - const uint32_t *filterLengths; /**< Internal Mel filter lengths */ - uint32_t fftLen; /**< FFT length */ - uint32_t nbMelFilters; /**< Number of Mel filters */ - uint32_t nbDctOutputs; /**< Number of DCT outputs */ +typedef struct { + const float32_t *dctCoefs; /**< Internal DCT coefficients */ + const float32_t *filterCoefs; /**< Internal Mel filter coefficients */ + const float32_t *windowCoefs; /**< Windowing coefficients */ + const uint32_t *filterPos; /**< Internal Mel filter positions in spectrum */ + const uint32_t *filterLengths; /**< Internal Mel filter lengths */ + uint32_t fftLen; /**< FFT length */ + uint32_t nbMelFilters; /**< Number of Mel filters */ + uint32_t nbDctOutputs; /**< Number of DCT outputs */ #if defined(ARM_MFCC_CFFT_BASED) - /* Implementation of the MFCC is using a CFFT */ - arm_cfft_instance_f32 cfft; /**< Internal CFFT instance */ + /* Implementation of the MFCC is using a CFFT */ + arm_cfft_instance_f32 cfft; /**< Internal CFFT instance */ #else - /* Implementation of the MFCC is using a RFFT (default) */ - arm_rfft_fast_instance_f32 rfft; + /* Implementation of the MFCC is using a RFFT (default) */ + arm_rfft_fast_instance_f32 rfft; #endif - } arm_mfcc_instance_f32 ; - -arm_status arm_mfcc_init_32_f32( - arm_mfcc_instance_f32 * S, - uint32_t nbMelFilters, - uint32_t nbDctOutputs, - const float32_t *dctCoefs, - const uint32_t *filterPos, - const uint32_t *filterLengths, - const float32_t *filterCoefs, - const float32_t *windowCoefs - ); - -arm_status arm_mfcc_init_64_f32( - arm_mfcc_instance_f32 * S, - uint32_t nbMelFilters, - uint32_t nbDctOutputs, - const float32_t *dctCoefs, - const uint32_t *filterPos, - const uint32_t *filterLengths, - const float32_t *filterCoefs, - const float32_t *windowCoefs - ); - -arm_status arm_mfcc_init_128_f32( - arm_mfcc_instance_f32 * S, - uint32_t nbMelFilters, - uint32_t nbDctOutputs, - const float32_t *dctCoefs, - const uint32_t *filterPos, - const uint32_t *filterLengths, - const float32_t *filterCoefs, - const float32_t *windowCoefs - ); - -arm_status arm_mfcc_init_256_f32( - arm_mfcc_instance_f32 * S, - uint32_t nbMelFilters, - uint32_t nbDctOutputs, - const float32_t *dctCoefs, - const uint32_t *filterPos, - const uint32_t *filterLengths, - const float32_t *filterCoefs, - const float32_t *windowCoefs - ); - -arm_status arm_mfcc_init_512_f32( - arm_mfcc_instance_f32 * S, - uint32_t nbMelFilters, - uint32_t nbDctOutputs, - const float32_t *dctCoefs, - const uint32_t *filterPos, - const uint32_t *filterLengths, - const float32_t *filterCoefs, - const float32_t *windowCoefs - ); - -arm_status arm_mfcc_init_1024_f32( - arm_mfcc_instance_f32 * S, - uint32_t nbMelFilters, - uint32_t nbDctOutputs, - const float32_t *dctCoefs, - const uint32_t *filterPos, - const uint32_t *filterLengths, - const float32_t *filterCoefs, - const float32_t *windowCoefs - ); - -arm_status arm_mfcc_init_2048_f32( - arm_mfcc_instance_f32 * S, - uint32_t nbMelFilters, - uint32_t nbDctOutputs, - const float32_t *dctCoefs, - const uint32_t *filterPos, - const uint32_t *filterLengths, - const float32_t *filterCoefs, - const float32_t *windowCoefs - ); - -arm_status arm_mfcc_init_4096_f32( - arm_mfcc_instance_f32 * S, - uint32_t nbMelFilters, - uint32_t nbDctOutputs, - const float32_t *dctCoefs, - const uint32_t *filterPos, - const uint32_t *filterLengths, - const float32_t *filterCoefs, - const float32_t *windowCoefs - ); - -arm_status arm_mfcc_init_f32( - arm_mfcc_instance_f32 * S, - uint32_t fftLen, - uint32_t nbMelFilters, - uint32_t nbDctOutputs, - const float32_t *dctCoefs, - const uint32_t *filterPos, - const uint32_t *filterLengths, - const float32_t *filterCoefs, - const float32_t *windowCoefs - ); - +} arm_mfcc_instance_f32; + +arm_status arm_mfcc_init_32_f32(arm_mfcc_instance_f32 *S, uint32_t nbMelFilters, + uint32_t nbDctOutputs, const float32_t *dctCoefs, + const uint32_t *filterPos, const uint32_t *filterLengths, + const float32_t *filterCoefs, const float32_t *windowCoefs); + +arm_status arm_mfcc_init_64_f32(arm_mfcc_instance_f32 *S, uint32_t nbMelFilters, + uint32_t nbDctOutputs, const float32_t *dctCoefs, + const uint32_t *filterPos, const uint32_t *filterLengths, + const float32_t *filterCoefs, const float32_t *windowCoefs); + +arm_status arm_mfcc_init_128_f32(arm_mfcc_instance_f32 *S, uint32_t nbMelFilters, + uint32_t nbDctOutputs, const float32_t *dctCoefs, + const uint32_t *filterPos, const uint32_t *filterLengths, + const float32_t *filterCoefs, const float32_t *windowCoefs); + +arm_status arm_mfcc_init_256_f32(arm_mfcc_instance_f32 *S, uint32_t nbMelFilters, + uint32_t nbDctOutputs, const float32_t *dctCoefs, + const uint32_t *filterPos, const uint32_t *filterLengths, + const float32_t *filterCoefs, const float32_t *windowCoefs); + +arm_status arm_mfcc_init_512_f32(arm_mfcc_instance_f32 *S, uint32_t nbMelFilters, + uint32_t nbDctOutputs, const float32_t *dctCoefs, + const uint32_t *filterPos, const uint32_t *filterLengths, + const float32_t *filterCoefs, const float32_t *windowCoefs); + +arm_status arm_mfcc_init_1024_f32(arm_mfcc_instance_f32 *S, uint32_t nbMelFilters, + uint32_t nbDctOutputs, const float32_t *dctCoefs, + const uint32_t *filterPos, const uint32_t *filterLengths, + const float32_t *filterCoefs, const float32_t *windowCoefs); + +arm_status arm_mfcc_init_2048_f32(arm_mfcc_instance_f32 *S, uint32_t nbMelFilters, + uint32_t nbDctOutputs, const float32_t *dctCoefs, + const uint32_t *filterPos, const uint32_t *filterLengths, + const float32_t *filterCoefs, const float32_t *windowCoefs); + +arm_status arm_mfcc_init_4096_f32(arm_mfcc_instance_f32 *S, uint32_t nbMelFilters, + uint32_t nbDctOutputs, const float32_t *dctCoefs, + const uint32_t *filterPos, const uint32_t *filterLengths, + const float32_t *filterCoefs, const float32_t *windowCoefs); + +arm_status arm_mfcc_init_f32(arm_mfcc_instance_f32 *S, uint32_t fftLen, uint32_t nbMelFilters, + uint32_t nbDctOutputs, const float32_t *dctCoefs, + const uint32_t *filterPos, const uint32_t *filterLengths, + const float32_t *filterCoefs, const float32_t *windowCoefs); /** @brief MFCC F32 @@ -860,135 +672,74 @@ arm_status arm_mfcc_init_f32( @param[out] pDst points to the output MFCC values @param[inout] pTmp points to a temporary buffer of complex */ - void arm_mfcc_f32( - const arm_mfcc_instance_f32 * S, - float32_t *pSrc, - float32_t *pDst, - float32_t *pTmp - ); - - /** +void arm_mfcc_f32(const arm_mfcc_instance_f32 *S, float32_t *pSrc, float32_t *pDst, + float32_t *pTmp); + +/** * @brief Instance structure for the Q31 MFCC function. */ -typedef struct - { - const q31_t *dctCoefs; /**< Internal DCT coefficients */ - const q31_t *filterCoefs; /**< Internal Mel filter coefficients */ - const q31_t *windowCoefs; /**< Windowing coefficients */ - const uint32_t *filterPos; /**< Internal Mel filter positions in spectrum */ - const uint32_t *filterLengths; /**< Internal Mel filter lengths */ - uint32_t fftLen; /**< FFT length */ - uint32_t nbMelFilters; /**< Number of Mel filters */ - uint32_t nbDctOutputs; /**< Number of DCT outputs */ +typedef struct { + const q31_t *dctCoefs; /**< Internal DCT coefficients */ + const q31_t *filterCoefs; /**< Internal Mel filter coefficients */ + const q31_t *windowCoefs; /**< Windowing coefficients */ + const uint32_t *filterPos; /**< Internal Mel filter positions in spectrum */ + const uint32_t *filterLengths; /**< Internal Mel filter lengths */ + uint32_t fftLen; /**< FFT length */ + uint32_t nbMelFilters; /**< Number of Mel filters */ + uint32_t nbDctOutputs; /**< Number of DCT outputs */ #if defined(ARM_MFCC_CFFT_BASED) - /* Implementation of the MFCC is using a CFFT */ - arm_cfft_instance_q31 cfft; /**< Internal CFFT instance */ + /* Implementation of the MFCC is using a CFFT */ + arm_cfft_instance_q31 cfft; /**< Internal CFFT instance */ #else - /* Implementation of the MFCC is using a RFFT (default) */ - arm_rfft_instance_q31 rfft; + /* Implementation of the MFCC is using a RFFT (default) */ + arm_rfft_instance_q31 rfft; #endif - } arm_mfcc_instance_q31 ; - -arm_status arm_mfcc_init_32_q31( - arm_mfcc_instance_q31 * S, - uint32_t nbMelFilters, - uint32_t nbDctOutputs, - const q31_t *dctCoefs, - const uint32_t *filterPos, - const uint32_t *filterLengths, - const q31_t *filterCoefs, - const q31_t *windowCoefs - ); - -arm_status arm_mfcc_init_64_q31( - arm_mfcc_instance_q31 * S, - uint32_t nbMelFilters, - uint32_t nbDctOutputs, - const q31_t *dctCoefs, - const uint32_t *filterPos, - const uint32_t *filterLengths, - const q31_t *filterCoefs, - const q31_t *windowCoefs - ); - -arm_status arm_mfcc_init_128_q31( - arm_mfcc_instance_q31 * S, - uint32_t nbMelFilters, - uint32_t nbDctOutputs, - const q31_t *dctCoefs, - const uint32_t *filterPos, - const uint32_t *filterLengths, - const q31_t *filterCoefs, - const q31_t *windowCoefs - ); - -arm_status arm_mfcc_init_256_q31( - arm_mfcc_instance_q31 * S, - uint32_t nbMelFilters, - uint32_t nbDctOutputs, - const q31_t *dctCoefs, - const uint32_t *filterPos, - const uint32_t *filterLengths, - const q31_t *filterCoefs, - const q31_t *windowCoefs - ); - -arm_status arm_mfcc_init_512_q31( - arm_mfcc_instance_q31 * S, - uint32_t nbMelFilters, - uint32_t nbDctOutputs, - const q31_t *dctCoefs, - const uint32_t *filterPos, - const uint32_t *filterLengths, - const q31_t *filterCoefs, - const q31_t *windowCoefs - ); - -arm_status arm_mfcc_init_1024_q31( - arm_mfcc_instance_q31 * S, - uint32_t nbMelFilters, - uint32_t nbDctOutputs, - const q31_t *dctCoefs, - const uint32_t *filterPos, - const uint32_t *filterLengths, - const q31_t *filterCoefs, - const q31_t *windowCoefs - ); - -arm_status arm_mfcc_init_2048_q31( - arm_mfcc_instance_q31 * S, - uint32_t nbMelFilters, - uint32_t nbDctOutputs, - const q31_t *dctCoefs, - const uint32_t *filterPos, - const uint32_t *filterLengths, - const q31_t *filterCoefs, - const q31_t *windowCoefs - ); - -arm_status arm_mfcc_init_4096_q31( - arm_mfcc_instance_q31 * S, - uint32_t nbMelFilters, - uint32_t nbDctOutputs, - const q31_t *dctCoefs, - const uint32_t *filterPos, - const uint32_t *filterLengths, - const q31_t *filterCoefs, - const q31_t *windowCoefs - ); - -arm_status arm_mfcc_init_q31( - arm_mfcc_instance_q31 * S, - uint32_t fftLen, - uint32_t nbMelFilters, - uint32_t nbDctOutputs, - const q31_t *dctCoefs, - const uint32_t *filterPos, - const uint32_t *filterLengths, - const q31_t *filterCoefs, - const q31_t *windowCoefs - ); - +} arm_mfcc_instance_q31; + +arm_status arm_mfcc_init_32_q31(arm_mfcc_instance_q31 *S, uint32_t nbMelFilters, + uint32_t nbDctOutputs, const q31_t *dctCoefs, + const uint32_t *filterPos, const uint32_t *filterLengths, + const q31_t *filterCoefs, const q31_t *windowCoefs); + +arm_status arm_mfcc_init_64_q31(arm_mfcc_instance_q31 *S, uint32_t nbMelFilters, + uint32_t nbDctOutputs, const q31_t *dctCoefs, + const uint32_t *filterPos, const uint32_t *filterLengths, + const q31_t *filterCoefs, const q31_t *windowCoefs); + +arm_status arm_mfcc_init_128_q31(arm_mfcc_instance_q31 *S, uint32_t nbMelFilters, + uint32_t nbDctOutputs, const q31_t *dctCoefs, + const uint32_t *filterPos, const uint32_t *filterLengths, + const q31_t *filterCoefs, const q31_t *windowCoefs); + +arm_status arm_mfcc_init_256_q31(arm_mfcc_instance_q31 *S, uint32_t nbMelFilters, + uint32_t nbDctOutputs, const q31_t *dctCoefs, + const uint32_t *filterPos, const uint32_t *filterLengths, + const q31_t *filterCoefs, const q31_t *windowCoefs); + +arm_status arm_mfcc_init_512_q31(arm_mfcc_instance_q31 *S, uint32_t nbMelFilters, + uint32_t nbDctOutputs, const q31_t *dctCoefs, + const uint32_t *filterPos, const uint32_t *filterLengths, + const q31_t *filterCoefs, const q31_t *windowCoefs); + +arm_status arm_mfcc_init_1024_q31(arm_mfcc_instance_q31 *S, uint32_t nbMelFilters, + uint32_t nbDctOutputs, const q31_t *dctCoefs, + const uint32_t *filterPos, const uint32_t *filterLengths, + const q31_t *filterCoefs, const q31_t *windowCoefs); + +arm_status arm_mfcc_init_2048_q31(arm_mfcc_instance_q31 *S, uint32_t nbMelFilters, + uint32_t nbDctOutputs, const q31_t *dctCoefs, + const uint32_t *filterPos, const uint32_t *filterLengths, + const q31_t *filterCoefs, const q31_t *windowCoefs); + +arm_status arm_mfcc_init_4096_q31(arm_mfcc_instance_q31 *S, uint32_t nbMelFilters, + uint32_t nbDctOutputs, const q31_t *dctCoefs, + const uint32_t *filterPos, const uint32_t *filterLengths, + const q31_t *filterCoefs, const q31_t *windowCoefs); + +arm_status arm_mfcc_init_q31(arm_mfcc_instance_q31 *S, uint32_t fftLen, uint32_t nbMelFilters, + uint32_t nbDctOutputs, const q31_t *dctCoefs, + const uint32_t *filterPos, const uint32_t *filterLengths, + const q31_t *filterCoefs, const q31_t *windowCoefs); /** @brief MFCC Q31 @@ -998,135 +749,73 @@ arm_status arm_mfcc_init_q31( @param[inout] pTmp points to a temporary buffer of complex @return error status */ - arm_status arm_mfcc_q31( - const arm_mfcc_instance_q31 * S, - q31_t *pSrc, - q31_t *pDst, - q31_t *pTmp - ); - - /** +arm_status arm_mfcc_q31(const arm_mfcc_instance_q31 *S, q31_t *pSrc, q31_t *pDst, q31_t *pTmp); + +/** * @brief Instance structure for the Q15 MFCC function. */ -typedef struct - { - const q15_t *dctCoefs; /**< Internal DCT coefficients */ - const q15_t *filterCoefs; /**< Internal Mel filter coefficients */ - const q15_t *windowCoefs; /**< Windowing coefficients */ - const uint32_t *filterPos; /**< Internal Mel filter positions in spectrum */ - const uint32_t *filterLengths; /**< Internal Mel filter lengths */ - uint32_t fftLen; /**< FFT length */ - uint32_t nbMelFilters; /**< Number of Mel filters */ - uint32_t nbDctOutputs; /**< Number of DCT outputs */ +typedef struct { + const q15_t *dctCoefs; /**< Internal DCT coefficients */ + const q15_t *filterCoefs; /**< Internal Mel filter coefficients */ + const q15_t *windowCoefs; /**< Windowing coefficients */ + const uint32_t *filterPos; /**< Internal Mel filter positions in spectrum */ + const uint32_t *filterLengths; /**< Internal Mel filter lengths */ + uint32_t fftLen; /**< FFT length */ + uint32_t nbMelFilters; /**< Number of Mel filters */ + uint32_t nbDctOutputs; /**< Number of DCT outputs */ #if defined(ARM_MFCC_CFFT_BASED) - /* Implementation of the MFCC is using a CFFT */ - arm_cfft_instance_q15 cfft; /**< Internal CFFT instance */ + /* Implementation of the MFCC is using a CFFT */ + arm_cfft_instance_q15 cfft; /**< Internal CFFT instance */ #else - /* Implementation of the MFCC is using a RFFT (default) */ - arm_rfft_instance_q15 rfft; + /* Implementation of the MFCC is using a RFFT (default) */ + arm_rfft_instance_q15 rfft; #endif - } arm_mfcc_instance_q15 ; - -arm_status arm_mfcc_init_32_q15( - arm_mfcc_instance_q15 * S, - uint32_t nbMelFilters, - uint32_t nbDctOutputs, - const q15_t *dctCoefs, - const uint32_t *filterPos, - const uint32_t *filterLengths, - const q15_t *filterCoefs, - const q15_t *windowCoefs - ); - -arm_status arm_mfcc_init_64_q15( - arm_mfcc_instance_q15 * S, - uint32_t nbMelFilters, - uint32_t nbDctOutputs, - const q15_t *dctCoefs, - const uint32_t *filterPos, - const uint32_t *filterLengths, - const q15_t *filterCoefs, - const q15_t *windowCoefs - ); - -arm_status arm_mfcc_init_128_q15( - arm_mfcc_instance_q15 * S, - uint32_t nbMelFilters, - uint32_t nbDctOutputs, - const q15_t *dctCoefs, - const uint32_t *filterPos, - const uint32_t *filterLengths, - const q15_t *filterCoefs, - const q15_t *windowCoefs - ); - -arm_status arm_mfcc_init_256_q15( - arm_mfcc_instance_q15 * S, - uint32_t nbMelFilters, - uint32_t nbDctOutputs, - const q15_t *dctCoefs, - const uint32_t *filterPos, - const uint32_t *filterLengths, - const q15_t *filterCoefs, - const q15_t *windowCoefs - ); - -arm_status arm_mfcc_init_512_q15( - arm_mfcc_instance_q15 * S, - uint32_t nbMelFilters, - uint32_t nbDctOutputs, - const q15_t *dctCoefs, - const uint32_t *filterPos, - const uint32_t *filterLengths, - const q15_t *filterCoefs, - const q15_t *windowCoefs - ); - -arm_status arm_mfcc_init_1024_q15( - arm_mfcc_instance_q15 * S, - uint32_t nbMelFilters, - uint32_t nbDctOutputs, - const q15_t *dctCoefs, - const uint32_t *filterPos, - const uint32_t *filterLengths, - const q15_t *filterCoefs, - const q15_t *windowCoefs - ); - -arm_status arm_mfcc_init_2048_q15( - arm_mfcc_instance_q15 * S, - uint32_t nbMelFilters, - uint32_t nbDctOutputs, - const q15_t *dctCoefs, - const uint32_t *filterPos, - const uint32_t *filterLengths, - const q15_t *filterCoefs, - const q15_t *windowCoefs - ); - -arm_status arm_mfcc_init_4096_q15( - arm_mfcc_instance_q15 * S, - uint32_t nbMelFilters, - uint32_t nbDctOutputs, - const q15_t *dctCoefs, - const uint32_t *filterPos, - const uint32_t *filterLengths, - const q15_t *filterCoefs, - const q15_t *windowCoefs - ); - -arm_status arm_mfcc_init_q15( - arm_mfcc_instance_q15 * S, - uint32_t fftLen, - uint32_t nbMelFilters, - uint32_t nbDctOutputs, - const q15_t *dctCoefs, - const uint32_t *filterPos, - const uint32_t *filterLengths, - const q15_t *filterCoefs, - const q15_t *windowCoefs - ); - +} arm_mfcc_instance_q15; + +arm_status arm_mfcc_init_32_q15(arm_mfcc_instance_q15 *S, uint32_t nbMelFilters, + uint32_t nbDctOutputs, const q15_t *dctCoefs, + const uint32_t *filterPos, const uint32_t *filterLengths, + const q15_t *filterCoefs, const q15_t *windowCoefs); + +arm_status arm_mfcc_init_64_q15(arm_mfcc_instance_q15 *S, uint32_t nbMelFilters, + uint32_t nbDctOutputs, const q15_t *dctCoefs, + const uint32_t *filterPos, const uint32_t *filterLengths, + const q15_t *filterCoefs, const q15_t *windowCoefs); + +arm_status arm_mfcc_init_128_q15(arm_mfcc_instance_q15 *S, uint32_t nbMelFilters, + uint32_t nbDctOutputs, const q15_t *dctCoefs, + const uint32_t *filterPos, const uint32_t *filterLengths, + const q15_t *filterCoefs, const q15_t *windowCoefs); + +arm_status arm_mfcc_init_256_q15(arm_mfcc_instance_q15 *S, uint32_t nbMelFilters, + uint32_t nbDctOutputs, const q15_t *dctCoefs, + const uint32_t *filterPos, const uint32_t *filterLengths, + const q15_t *filterCoefs, const q15_t *windowCoefs); + +arm_status arm_mfcc_init_512_q15(arm_mfcc_instance_q15 *S, uint32_t nbMelFilters, + uint32_t nbDctOutputs, const q15_t *dctCoefs, + const uint32_t *filterPos, const uint32_t *filterLengths, + const q15_t *filterCoefs, const q15_t *windowCoefs); + +arm_status arm_mfcc_init_1024_q15(arm_mfcc_instance_q15 *S, uint32_t nbMelFilters, + uint32_t nbDctOutputs, const q15_t *dctCoefs, + const uint32_t *filterPos, const uint32_t *filterLengths, + const q15_t *filterCoefs, const q15_t *windowCoefs); + +arm_status arm_mfcc_init_2048_q15(arm_mfcc_instance_q15 *S, uint32_t nbMelFilters, + uint32_t nbDctOutputs, const q15_t *dctCoefs, + const uint32_t *filterPos, const uint32_t *filterLengths, + const q15_t *filterCoefs, const q15_t *windowCoefs); + +arm_status arm_mfcc_init_4096_q15(arm_mfcc_instance_q15 *S, uint32_t nbMelFilters, + uint32_t nbDctOutputs, const q15_t *dctCoefs, + const uint32_t *filterPos, const uint32_t *filterLengths, + const q15_t *filterCoefs, const q15_t *windowCoefs); + +arm_status arm_mfcc_init_q15(arm_mfcc_instance_q15 *S, uint32_t fftLen, uint32_t nbMelFilters, + uint32_t nbDctOutputs, const q15_t *dctCoefs, + const uint32_t *filterPos, const uint32_t *filterLengths, + const q15_t *filterCoefs, const q15_t *windowCoefs); /** @brief MFCC Q15 @@ -1136,15 +825,9 @@ arm_status arm_mfcc_init_q15( @param[inout] pTmp points to a temporary buffer of complex @return error status */ - arm_status arm_mfcc_q15( - const arm_mfcc_instance_q15 * S, - q15_t *pSrc, - q15_t *pDst, - q31_t *pTmp - ); - +arm_status arm_mfcc_q15(const arm_mfcc_instance_q15 *S, q15_t *pSrc, q15_t *pDst, q31_t *pTmp); -#ifdef __cplusplus +#ifdef __cplusplus } #endif diff --git a/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/transform_functions_f16.h b/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/transform_functions_f16.h old mode 100755 new mode 100644 index b0ca0c0d2de..aaf4c8dff32 --- a/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/transform_functions_f16.h +++ b/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/transform_functions_f16.h @@ -23,7 +23,6 @@ * limitations under the License. */ - #ifndef TRANSFORM_FUNCTIONS_F16_H_ #define TRANSFORM_FUNCTIONS_F16_H_ @@ -33,264 +32,186 @@ #include "dsp/none.h" #include "dsp/utils.h" -#ifdef __cplusplus -extern "C" -{ +#ifdef __cplusplus +extern "C" { #endif - - #if defined(ARM_FLOAT16_SUPPORTED) - - /** +/** * @brief Instance structure for the floating-point CFFT/CIFFT function. */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - const float16_t *pTwiddle; /**< points to the Twiddle factor table. */ - const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - float16_t onebyfftLen; /**< value of 1/fftLen. */ - } arm_cfft_radix2_instance_f16; - - /** +typedef struct { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t + ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t + bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + const float16_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t + twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t + bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float16_t onebyfftLen; /**< value of 1/fftLen. */ +} arm_cfft_radix2_instance_f16; + +/** * @brief Instance structure for the floating-point CFFT/CIFFT function. */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - const float16_t *pTwiddle; /**< points to the Twiddle factor table. */ - const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - float16_t onebyfftLen; /**< value of 1/fftLen. */ - } arm_cfft_radix4_instance_f16; - - /** +typedef struct { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t + ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t + bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + const float16_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t + twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t + bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float16_t onebyfftLen; /**< value of 1/fftLen. */ +} arm_cfft_radix4_instance_f16; + +/** * @brief Instance structure for the floating-point CFFT/CIFFT function. */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - const float16_t *pTwiddle; /**< points to the Twiddle factor table. */ - const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t bitRevLength; /**< bit reversal table length. */ +typedef struct { + uint16_t fftLen; /**< length of the FFT. */ + const float16_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ #if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) - const uint32_t *rearranged_twiddle_tab_stride1_arr; /**< Per stage reordered twiddle pointer (offset 1) */ \ - const uint32_t *rearranged_twiddle_tab_stride2_arr; /**< Per stage reordered twiddle pointer (offset 2) */ \ - const uint32_t *rearranged_twiddle_tab_stride3_arr; /**< Per stage reordered twiddle pointer (offset 3) */ \ - const float16_t *rearranged_twiddle_stride1; /**< reordered twiddle offset 1 storage */ \ - const float16_t *rearranged_twiddle_stride2; /**< reordered twiddle offset 2 storage */ \ - const float16_t *rearranged_twiddle_stride3; + const uint32_t + *rearranged_twiddle_tab_stride1_arr; /**< Per stage reordered twiddle pointer (offset 1) */ + const uint32_t + *rearranged_twiddle_tab_stride2_arr; /**< Per stage reordered twiddle pointer (offset 2) */ + const uint32_t + *rearranged_twiddle_tab_stride3_arr; /**< Per stage reordered twiddle pointer (offset 3) */ + const float16_t *rearranged_twiddle_stride1; /**< reordered twiddle offset 1 storage */ + const float16_t *rearranged_twiddle_stride2; /**< reordered twiddle offset 2 storage */ + const float16_t *rearranged_twiddle_stride3; #endif - } arm_cfft_instance_f16; +} arm_cfft_instance_f16; +arm_status arm_cfft_init_4096_f16(arm_cfft_instance_f16 *S); +arm_status arm_cfft_init_2048_f16(arm_cfft_instance_f16 *S); +arm_status arm_cfft_init_1024_f16(arm_cfft_instance_f16 *S); +arm_status arm_cfft_init_512_f16(arm_cfft_instance_f16 *S); +arm_status arm_cfft_init_256_f16(arm_cfft_instance_f16 *S); +arm_status arm_cfft_init_128_f16(arm_cfft_instance_f16 *S); +arm_status arm_cfft_init_64_f16(arm_cfft_instance_f16 *S); +arm_status arm_cfft_init_32_f16(arm_cfft_instance_f16 *S); +arm_status arm_cfft_init_16_f16(arm_cfft_instance_f16 *S); -arm_status arm_cfft_init_4096_f16(arm_cfft_instance_f16 * S); -arm_status arm_cfft_init_2048_f16(arm_cfft_instance_f16 * S); -arm_status arm_cfft_init_1024_f16(arm_cfft_instance_f16 * S); -arm_status arm_cfft_init_512_f16(arm_cfft_instance_f16 * S); -arm_status arm_cfft_init_256_f16(arm_cfft_instance_f16 * S); -arm_status arm_cfft_init_128_f16(arm_cfft_instance_f16 * S); -arm_status arm_cfft_init_64_f16(arm_cfft_instance_f16 * S); -arm_status arm_cfft_init_32_f16(arm_cfft_instance_f16 * S); -arm_status arm_cfft_init_16_f16(arm_cfft_instance_f16 * S); +arm_status arm_cfft_init_f16(arm_cfft_instance_f16 *S, uint16_t fftLen); +void arm_cfft_f16(const arm_cfft_instance_f16 *S, float16_t *p1, uint8_t ifftFlag, + uint8_t bitReverseFlag); - arm_status arm_cfft_init_f16( - arm_cfft_instance_f16 * S, - uint16_t fftLen); - - void arm_cfft_f16( - const arm_cfft_instance_f16 * S, - float16_t * p1, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** +/** * @brief Instance structure for the floating-point RFFT/RIFFT function. */ -typedef struct - { - arm_cfft_instance_f16 Sint; /**< Internal CFFT structure. */ - uint16_t fftLenRFFT; /**< length of the real sequence */ - const float16_t * pTwiddleRFFT; /**< Twiddle factors real stage */ - } arm_rfft_fast_instance_f16 ; - -arm_status arm_rfft_fast_init_32_f16( arm_rfft_fast_instance_f16 * S ); -arm_status arm_rfft_fast_init_64_f16( arm_rfft_fast_instance_f16 * S ); -arm_status arm_rfft_fast_init_128_f16( arm_rfft_fast_instance_f16 * S ); -arm_status arm_rfft_fast_init_256_f16( arm_rfft_fast_instance_f16 * S ); -arm_status arm_rfft_fast_init_512_f16( arm_rfft_fast_instance_f16 * S ); -arm_status arm_rfft_fast_init_1024_f16( arm_rfft_fast_instance_f16 * S ); -arm_status arm_rfft_fast_init_2048_f16( arm_rfft_fast_instance_f16 * S ); -arm_status arm_rfft_fast_init_4096_f16( arm_rfft_fast_instance_f16 * S ); - -arm_status arm_rfft_fast_init_f16 ( - arm_rfft_fast_instance_f16 * S, - uint16_t fftLen); - - - void arm_rfft_fast_f16( - const arm_rfft_fast_instance_f16 * S, - float16_t * p, float16_t * pOut, - uint8_t ifftFlag); +typedef struct { + arm_cfft_instance_f16 Sint; /**< Internal CFFT structure. */ + uint16_t fftLenRFFT; /**< length of the real sequence */ + const float16_t *pTwiddleRFFT; /**< Twiddle factors real stage */ +} arm_rfft_fast_instance_f16; + +arm_status arm_rfft_fast_init_32_f16(arm_rfft_fast_instance_f16 *S); +arm_status arm_rfft_fast_init_64_f16(arm_rfft_fast_instance_f16 *S); +arm_status arm_rfft_fast_init_128_f16(arm_rfft_fast_instance_f16 *S); +arm_status arm_rfft_fast_init_256_f16(arm_rfft_fast_instance_f16 *S); +arm_status arm_rfft_fast_init_512_f16(arm_rfft_fast_instance_f16 *S); +arm_status arm_rfft_fast_init_1024_f16(arm_rfft_fast_instance_f16 *S); +arm_status arm_rfft_fast_init_2048_f16(arm_rfft_fast_instance_f16 *S); +arm_status arm_rfft_fast_init_4096_f16(arm_rfft_fast_instance_f16 *S); + +arm_status arm_rfft_fast_init_f16(arm_rfft_fast_instance_f16 *S, uint16_t fftLen); + +void arm_rfft_fast_f16(const arm_rfft_fast_instance_f16 *S, float16_t *p, float16_t *pOut, + uint8_t ifftFlag); /* Deprecated */ - arm_status arm_cfft_radix4_init_f16( - arm_cfft_radix4_instance_f16 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); +arm_status arm_cfft_radix4_init_f16(arm_cfft_radix4_instance_f16 *S, uint16_t fftLen, + uint8_t ifftFlag, uint8_t bitReverseFlag); /* Deprecated */ - void arm_cfft_radix4_f16( - const arm_cfft_radix4_instance_f16 * S, - float16_t * pSrc); - +void arm_cfft_radix4_f16(const arm_cfft_radix4_instance_f16 *S, float16_t *pSrc); /* Deprecated */ - arm_status arm_cfft_radix2_init_f16( - arm_cfft_radix2_instance_f16 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); +arm_status arm_cfft_radix2_init_f16(arm_cfft_radix2_instance_f16 *S, uint16_t fftLen, + uint8_t ifftFlag, uint8_t bitReverseFlag); /* Deprecated */ - void arm_cfft_radix2_f16( - const arm_cfft_radix2_instance_f16 * S, - float16_t * pSrc); +void arm_cfft_radix2_f16(const arm_cfft_radix2_instance_f16 *S, float16_t *pSrc); - /** +/** * @brief Instance structure for the Floating-point MFCC function. */ -typedef struct - { - const float16_t *dctCoefs; /**< Internal DCT coefficients */ - const float16_t *filterCoefs; /**< Internal Mel filter coefficients */ - const float16_t *windowCoefs; /**< Windowing coefficients */ - const uint32_t *filterPos; /**< Internal Mel filter positions in spectrum */ - const uint32_t *filterLengths; /**< Internal Mel filter lengths */ - uint32_t fftLen; /**< FFT length */ - uint32_t nbMelFilters; /**< Number of Mel filters */ - uint32_t nbDctOutputs; /**< Number of DCT outputs */ +typedef struct { + const float16_t *dctCoefs; /**< Internal DCT coefficients */ + const float16_t *filterCoefs; /**< Internal Mel filter coefficients */ + const float16_t *windowCoefs; /**< Windowing coefficients */ + const uint32_t *filterPos; /**< Internal Mel filter positions in spectrum */ + const uint32_t *filterLengths; /**< Internal Mel filter lengths */ + uint32_t fftLen; /**< FFT length */ + uint32_t nbMelFilters; /**< Number of Mel filters */ + uint32_t nbDctOutputs; /**< Number of DCT outputs */ #if defined(ARM_MFCC_CFFT_BASED) - /* Implementation of the MFCC is using a CFFT */ - arm_cfft_instance_f16 cfft; /**< Internal CFFT instance */ + /* Implementation of the MFCC is using a CFFT */ + arm_cfft_instance_f16 cfft; /**< Internal CFFT instance */ #else - /* Implementation of the MFCC is using a RFFT (default) */ - arm_rfft_fast_instance_f16 rfft; + /* Implementation of the MFCC is using a RFFT (default) */ + arm_rfft_fast_instance_f16 rfft; #endif - } arm_mfcc_instance_f16 ; - -arm_status arm_mfcc_init_32_f16( - arm_mfcc_instance_f16 * S, - uint32_t nbMelFilters, - uint32_t nbDctOutputs, - const float16_t *dctCoefs, - const uint32_t *filterPos, - const uint32_t *filterLengths, - const float16_t *filterCoefs, - const float16_t *windowCoefs - ); - -arm_status arm_mfcc_init_64_f16( - arm_mfcc_instance_f16 * S, - uint32_t nbMelFilters, - uint32_t nbDctOutputs, - const float16_t *dctCoefs, - const uint32_t *filterPos, - const uint32_t *filterLengths, - const float16_t *filterCoefs, - const float16_t *windowCoefs - ); - -arm_status arm_mfcc_init_128_f16( - arm_mfcc_instance_f16 * S, - uint32_t nbMelFilters, - uint32_t nbDctOutputs, - const float16_t *dctCoefs, - const uint32_t *filterPos, - const uint32_t *filterLengths, - const float16_t *filterCoefs, - const float16_t *windowCoefs - ); - -arm_status arm_mfcc_init_256_f16( - arm_mfcc_instance_f16 * S, - uint32_t nbMelFilters, - uint32_t nbDctOutputs, - const float16_t *dctCoefs, - const uint32_t *filterPos, - const uint32_t *filterLengths, - const float16_t *filterCoefs, - const float16_t *windowCoefs - ); - -arm_status arm_mfcc_init_512_f16( - arm_mfcc_instance_f16 * S, - uint32_t nbMelFilters, - uint32_t nbDctOutputs, - const float16_t *dctCoefs, - const uint32_t *filterPos, - const uint32_t *filterLengths, - const float16_t *filterCoefs, - const float16_t *windowCoefs - ); - -arm_status arm_mfcc_init_1024_f16( - arm_mfcc_instance_f16 * S, - uint32_t nbMelFilters, - uint32_t nbDctOutputs, - const float16_t *dctCoefs, - const uint32_t *filterPos, - const uint32_t *filterLengths, - const float16_t *filterCoefs, - const float16_t *windowCoefs - ); - -arm_status arm_mfcc_init_2048_f16( - arm_mfcc_instance_f16 * S, - uint32_t nbMelFilters, - uint32_t nbDctOutputs, - const float16_t *dctCoefs, - const uint32_t *filterPos, - const uint32_t *filterLengths, - const float16_t *filterCoefs, - const float16_t *windowCoefs - ); - -arm_status arm_mfcc_init_4096_f16( - arm_mfcc_instance_f16 * S, - uint32_t nbMelFilters, - uint32_t nbDctOutputs, - const float16_t *dctCoefs, - const uint32_t *filterPos, - const uint32_t *filterLengths, - const float16_t *filterCoefs, - const float16_t *windowCoefs - ); - -arm_status arm_mfcc_init_f16( - arm_mfcc_instance_f16 * S, - uint32_t fftLen, - uint32_t nbMelFilters, - uint32_t nbDctOutputs, - const float16_t *dctCoefs, - const uint32_t *filterPos, - const uint32_t *filterLengths, - const float16_t *filterCoefs, - const float16_t *windowCoefs - ); - - +} arm_mfcc_instance_f16; + +arm_status arm_mfcc_init_32_f16(arm_mfcc_instance_f16 *S, uint32_t nbMelFilters, + uint32_t nbDctOutputs, const float16_t *dctCoefs, + const uint32_t *filterPos, const uint32_t *filterLengths, + const float16_t *filterCoefs, const float16_t *windowCoefs); + +arm_status arm_mfcc_init_64_f16(arm_mfcc_instance_f16 *S, uint32_t nbMelFilters, + uint32_t nbDctOutputs, const float16_t *dctCoefs, + const uint32_t *filterPos, const uint32_t *filterLengths, + const float16_t *filterCoefs, const float16_t *windowCoefs); + +arm_status arm_mfcc_init_128_f16(arm_mfcc_instance_f16 *S, uint32_t nbMelFilters, + uint32_t nbDctOutputs, const float16_t *dctCoefs, + const uint32_t *filterPos, const uint32_t *filterLengths, + const float16_t *filterCoefs, const float16_t *windowCoefs); + +arm_status arm_mfcc_init_256_f16(arm_mfcc_instance_f16 *S, uint32_t nbMelFilters, + uint32_t nbDctOutputs, const float16_t *dctCoefs, + const uint32_t *filterPos, const uint32_t *filterLengths, + const float16_t *filterCoefs, const float16_t *windowCoefs); + +arm_status arm_mfcc_init_512_f16(arm_mfcc_instance_f16 *S, uint32_t nbMelFilters, + uint32_t nbDctOutputs, const float16_t *dctCoefs, + const uint32_t *filterPos, const uint32_t *filterLengths, + const float16_t *filterCoefs, const float16_t *windowCoefs); + +arm_status arm_mfcc_init_1024_f16(arm_mfcc_instance_f16 *S, uint32_t nbMelFilters, + uint32_t nbDctOutputs, const float16_t *dctCoefs, + const uint32_t *filterPos, const uint32_t *filterLengths, + const float16_t *filterCoefs, const float16_t *windowCoefs); + +arm_status arm_mfcc_init_2048_f16(arm_mfcc_instance_f16 *S, uint32_t nbMelFilters, + uint32_t nbDctOutputs, const float16_t *dctCoefs, + const uint32_t *filterPos, const uint32_t *filterLengths, + const float16_t *filterCoefs, const float16_t *windowCoefs); + +arm_status arm_mfcc_init_4096_f16(arm_mfcc_instance_f16 *S, uint32_t nbMelFilters, + uint32_t nbDctOutputs, const float16_t *dctCoefs, + const uint32_t *filterPos, const uint32_t *filterLengths, + const float16_t *filterCoefs, const float16_t *windowCoefs); + +arm_status arm_mfcc_init_f16(arm_mfcc_instance_f16 *S, uint32_t fftLen, uint32_t nbMelFilters, + uint32_t nbDctOutputs, const float16_t *dctCoefs, + const uint32_t *filterPos, const uint32_t *filterLengths, + const float16_t *filterCoefs, const float16_t *windowCoefs); /** @brief MFCC F16 @@ -299,17 +220,12 @@ arm_status arm_mfcc_init_f16( @param[out] pDst points to the output MFCC values @param[inout] pTmp points to a temporary buffer of complex */ - void arm_mfcc_f16( - const arm_mfcc_instance_f16 * S, - float16_t *pSrc, - float16_t *pDst, - float16_t *pTmp - ); - - +void arm_mfcc_f16(const arm_mfcc_instance_f16 *S, float16_t *pSrc, float16_t *pDst, + float16_t *pTmp); + #endif /* defined(ARM_FLOAT16_SUPPORTED)*/ -#ifdef __cplusplus +#ifdef __cplusplus } #endif diff --git a/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/utils.h b/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/utils.h old mode 100755 new mode 100644 index e0c5c90c17c..5f9413921ee --- a/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/utils.h +++ b/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/utils.h @@ -29,55 +29,47 @@ #include "arm_math_types.h" #include -#ifdef __cplusplus -extern "C" -{ +#ifdef __cplusplus +extern "C" { #endif - /** +/** * @brief Macros required for reciprocal calculation in Normalized LMS */ -#define INDEX_MASK 0x0000003F +#define INDEX_MASK 0x0000003F #ifndef MIN - #define MIN(x,y) ((x) < (y) ? (x) : (y)) -#endif +#define MIN(x, y) ((x) < (y) ? (x) : (y)) +#endif #ifndef MAX - #define MAX(x,y) ((x) > (y) ? (x) : (y)) -#endif +#define MAX(x, y) ((x) > (y) ? (x) : (y)) +#endif #ifndef ARM_SQ #define ARM_SQ(x) ((x) * (x)) #endif #ifndef ARM_ROUND_UP - #define ARM_ROUND_UP(N, S) ((((N) + (S) - 1) / (S)) * (S)) +#define ARM_ROUND_UP(N, S) ((((N) + (S)-1) / (S)) * (S)) #endif - - /** +/** * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type. It should not be used with negative values. */ - __STATIC_FORCEINLINE uint32_t arm_recip_q31( - q31_t in, - q31_t * dst, - const q31_t * pRecipTable) - { +__STATIC_FORCEINLINE uint32_t arm_recip_q31(q31_t in, q31_t *dst, const q31_t *pRecipTable) +{ q31_t out; uint32_t tempVal; uint32_t index, i; uint32_t signBits; - if (in > 0) - { - signBits = ((uint32_t) (__CLZ( (uint32_t)in) - 1)); - } - else - { - signBits = ((uint32_t) (__CLZ((uint32_t)(-in)) - 1)); + if (in > 0) { + signBits = ((uint32_t)(__CLZ((uint32_t)in) - 1)); + } else { + signBits = ((uint32_t)(__CLZ((uint32_t)(-in)) - 1)); } /* Convert input sample to 1.31 format */ @@ -92,13 +84,12 @@ extern "C" /* calculation of reciprocal value */ /* running approximation for two iterations */ - for (i = 0U; i < 2U; i++) - { - tempVal = (uint32_t) (((q63_t) in * out) >> 31); - tempVal = 0x7FFFFFFFu - tempVal; - /* 1.31 with exp 1 */ - /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */ - out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30); + for (i = 0U; i < 2U; i++) { + tempVal = (uint32_t)(((q63_t)in * out) >> 31); + tempVal = 0x7FFFFFFFu - tempVal; + /* 1.31 with exp 1 */ + /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */ + out = clip_q63_to_q31(((q63_t)out * tempVal) >> 30); } /* write output */ @@ -106,37 +97,30 @@ extern "C" /* return num of signbits of out = 1/in value */ return (signBits + 1U); - } - +} - /** +/** * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type. It should not be used with negative values. */ - __STATIC_FORCEINLINE uint32_t arm_recip_q15( - q15_t in, - q15_t * dst, - const q15_t * pRecipTable) - { +__STATIC_FORCEINLINE uint32_t arm_recip_q15(q15_t in, q15_t *dst, const q15_t *pRecipTable) +{ q15_t out = 0; int32_t tempVal = 0; uint32_t index = 0, i = 0; uint32_t signBits = 0; - if (in > 0) - { - signBits = ((uint32_t)(__CLZ( (uint32_t)in) - 17)); - } - else - { - signBits = ((uint32_t)(__CLZ((uint32_t)(-in)) - 17)); + if (in > 0) { + signBits = ((uint32_t)(__CLZ((uint32_t)in) - 17)); + } else { + signBits = ((uint32_t)(__CLZ((uint32_t)(-in)) - 17)); } /* Convert input sample to 1.15 format */ in = (q15_t)(in << signBits); /* calculation of index for initial approximated Val */ - index = (uint32_t)(in >> 8); + index = (uint32_t)(in >> 8); index = (index & INDEX_MASK); /* 1.15 with exp 1 */ @@ -144,13 +128,12 @@ extern "C" /* calculation of reciprocal value */ /* running approximation for two iterations */ - for (i = 0U; i < 2U; i++) - { - tempVal = (((q31_t) in * out) >> 15); - tempVal = 0x7FFF - tempVal; - /* 1.15 with exp 1 */ - out = (q15_t) (((q31_t) out * tempVal) >> 14); - /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */ + for (i = 0U; i < 2U; i++) { + tempVal = (((q31_t)in * out) >> 15); + tempVal = 0x7FFF - tempVal; + /* 1.15 with exp 1 */ + out = (q15_t)(((q31_t)out * tempVal) >> 14); + /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */ } /* write output */ @@ -158,8 +141,7 @@ extern "C" /* return num of signbits of out = 1/in value */ return (signBits + 1); - } - +} /** * @brief 64-bit to 32-bit unsigned normalization @@ -167,37 +149,32 @@ extern "C" * @param[out] normalized is the 32-bit normalized value * @param[out] norm is norm scale */ -__STATIC_INLINE void arm_norm_64_to_32u(uint64_t in, int32_t * normalized, int32_t *norm) +__STATIC_INLINE void arm_norm_64_to_32u(uint64_t in, int32_t *normalized, int32_t *norm) { - int32_t n1; - int32_t hi = (int32_t) (in >> 32); - int32_t lo = (int32_t) ((in << 32) >> 32); + int32_t n1; + int32_t hi = (int32_t)(in >> 32); + int32_t lo = (int32_t)((in << 32) >> 32); n1 = __CLZ((uint32_t)hi) - 32; - if (!n1) - { + if (!n1) { /* * input fits in 32-bit */ n1 = __CLZ((uint32_t)lo); - if (!n1) - { + if (!n1) { /* * MSB set, need to scale down by 1 */ *norm = -1; - *normalized = (((uint32_t) lo) >> 1); - } else - { - if (n1 == 32) - { + *normalized = (((uint32_t)lo) >> 1); + } else { + if (n1 == 32) { /* * input is zero */ *norm = 0; *normalized = 0; - } else - { + } else { /* * 32-bit normalization */ @@ -205,8 +182,7 @@ __STATIC_INLINE void arm_norm_64_to_32u(uint64_t in, int32_t * normalized, int3 *normalized = lo << *norm; } } - } else - { + } else { /* * input fits in 64-bit */ @@ -221,41 +197,38 @@ __STATIC_INLINE void arm_norm_64_to_32u(uint64_t in, int32_t * normalized, int3 __STATIC_INLINE int32_t arm_div_int64_to_int32(int64_t num, int32_t den) { - int32_t result; - uint64_t absNum; - int32_t normalized; - int32_t norm; + int32_t result; + uint64_t absNum; + int32_t normalized; + int32_t norm; /* * if sum fits in 32bits * avoid costly 64-bit division */ - if (num == (int64_t)LONG_MIN) - { + if (num == (int64_t)LONG_MIN) { absNum = LONG_MAX; - } - else - { - absNum = (uint64_t) (num > 0 ? num : -num); + } else { + absNum = (uint64_t)(num > 0 ? num : -num); } arm_norm_64_to_32u(absNum, &normalized, &norm); if (norm > 0) /* * 32-bit division */ - result = (int32_t) num / den; + result = (int32_t)num / den; else /* * 64-bit division */ - result = (int32_t) (num / den); + result = (int32_t)(num / den); return result; } #undef INDEX_MASK -#ifdef __cplusplus +#ifdef __cplusplus } #endif diff --git a/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/window_functions.h b/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/window_functions.h index 27f05a73964..a93eff1f43d 100644 --- a/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/window_functions.h +++ b/Libraries/CMSIS/5.9.0/DSP/1.16.2/Include/dsp/window_functions.h @@ -23,7 +23,6 @@ * limitations under the License. */ - #ifndef WINDOW_FUNCTIONS_H_ #define WINDOW_FUNCTIONS_H_ @@ -33,17 +32,15 @@ #include "dsp/none.h" #include "dsp/utils.h" - -#ifdef __cplusplus -extern "C" -{ +#ifdef __cplusplus +extern "C" { #endif /** * @defgroup groupWindow Window Functions */ - /** +/** * @brief Welch window (double). * @param[out] pDst points to the output generated window * @param[in] blockSize number of samples in the window @@ -58,11 +55,9 @@ extern "C" * | Recommended overlap | 29.3 % | * */ - void arm_welch_f64( - float64_t * pDst, - uint32_t blockSize); +void arm_welch_f64(float64_t *pDst, uint32_t blockSize); - /** +/** * @brief Welch window (float). * @param[out] pDst points to the output generated window * @param[in] blockSize number of samples in the window @@ -78,10 +73,8 @@ extern "C" * * */ - void arm_welch_f32( - float32_t * pDst, - uint32_t blockSize); - /** +void arm_welch_f32(float32_t *pDst, uint32_t blockSize); +/** * @brief Bartlett window (double). * @param[out] pDst points to the output generated window * @param[in] blockSize number of samples in the window @@ -96,11 +89,9 @@ extern "C" * | Recommended overlap | 50.0 % | * */ - void arm_bartlett_f64( - float64_t * pDst, - uint32_t blockSize); +void arm_bartlett_f64(float64_t *pDst, uint32_t blockSize); - /** +/** * @brief Bartlett window (float). * @param[out] pDst points to the output generated window * @param[in] blockSize number of samples in the window @@ -116,10 +107,8 @@ extern "C" * * */ - void arm_bartlett_f32( - float32_t * pDst, - uint32_t blockSize); - /** +void arm_bartlett_f32(float32_t *pDst, uint32_t blockSize); +/** * @brief Hamming window (double). * @param[out] pDst points to the output generated window * @param[in] blockSize number of samples in the window @@ -134,11 +123,9 @@ extern "C" * | Recommended overlap | 50 % | * */ - void arm_hamming_f64( - float64_t * pDst, - uint32_t blockSize); +void arm_hamming_f64(float64_t *pDst, uint32_t blockSize); - /** +/** * @brief Hamming window (float). * @param[out] pDst points to the output generated window * @param[in] blockSize number of samples in the window @@ -154,10 +141,8 @@ extern "C" * * */ - void arm_hamming_f32( - float32_t * pDst, - uint32_t blockSize); - /** +void arm_hamming_f32(float32_t *pDst, uint32_t blockSize); +/** * @brief Hanning window (double). * @param[out] pDst points to the output generated window * @param[in] blockSize number of samples in the window @@ -172,11 +157,9 @@ extern "C" * | Recommended overlap | 50 % | * */ - void arm_hanning_f64( - float64_t * pDst, - uint32_t blockSize); +void arm_hanning_f64(float64_t *pDst, uint32_t blockSize); - /** +/** * @brief Hanning window (float). * @param[out] pDst points to the output generated window * @param[in] blockSize number of samples in the window @@ -192,10 +175,8 @@ extern "C" * * */ - void arm_hanning_f32( - float32_t * pDst, - uint32_t blockSize); - /** +void arm_hanning_f32(float32_t *pDst, uint32_t blockSize); +/** * @brief Nuttall3 window (double). * @param[out] pDst points to the output generated window * @param[in] blockSize number of samples in the window @@ -210,11 +191,9 @@ extern "C" * | Recommended overlap | 64.7 % | * */ - void arm_nuttall3_f64( - float64_t * pDst, - uint32_t blockSize); +void arm_nuttall3_f64(float64_t *pDst, uint32_t blockSize); - /** +/** * @brief Nuttall3 window (float). * @param[out] pDst points to the output generated window * @param[in] blockSize number of samples in the window @@ -230,10 +209,8 @@ extern "C" * * */ - void arm_nuttall3_f32( - float32_t * pDst, - uint32_t blockSize); - /** +void arm_nuttall3_f32(float32_t *pDst, uint32_t blockSize); +/** * @brief Nuttall4 window (double). * @param[out] pDst points to the output generated window * @param[in] blockSize number of samples in the window @@ -248,11 +225,9 @@ extern "C" * | Recommended overlap | 70.5 % | * */ - void arm_nuttall4_f64( - float64_t * pDst, - uint32_t blockSize); +void arm_nuttall4_f64(float64_t *pDst, uint32_t blockSize); - /** +/** * @brief Nuttall4 window (float). * @param[out] pDst points to the output generated window * @param[in] blockSize number of samples in the window @@ -268,10 +243,8 @@ extern "C" * * */ - void arm_nuttall4_f32( - float32_t * pDst, - uint32_t blockSize); - /** +void arm_nuttall4_f32(float32_t *pDst, uint32_t blockSize); +/** * @brief Nuttall3a window (double). * @param[out] pDst points to the output generated window * @param[in] blockSize number of samples in the window @@ -286,11 +259,9 @@ extern "C" * | Recommended overlap | 61.2 % | * */ - void arm_nuttall3a_f64( - float64_t * pDst, - uint32_t blockSize); +void arm_nuttall3a_f64(float64_t *pDst, uint32_t blockSize); - /** +/** * @brief Nuttall3a window (float). * @param[out] pDst points to the output generated window * @param[in] blockSize number of samples in the window @@ -306,10 +277,8 @@ extern "C" * * */ - void arm_nuttall3a_f32( - float32_t * pDst, - uint32_t blockSize); - /** +void arm_nuttall3a_f32(float32_t *pDst, uint32_t blockSize); +/** * @brief Nuttall3b window (double). * @param[out] pDst points to the output generated window * @param[in] blockSize number of samples in the window @@ -324,11 +293,9 @@ extern "C" * | Recommended overlap | 59.8 % | * */ - void arm_nuttall3b_f64( - float64_t * pDst, - uint32_t blockSize); +void arm_nuttall3b_f64(float64_t *pDst, uint32_t blockSize); - /** +/** * @brief Nuttall3b window (float). * @param[out] pDst points to the output generated window * @param[in] blockSize number of samples in the window @@ -344,10 +311,8 @@ extern "C" * * */ - void arm_nuttall3b_f32( - float32_t * pDst, - uint32_t blockSize); - /** +void arm_nuttall3b_f32(float32_t *pDst, uint32_t blockSize); +/** * @brief Nuttall4a window (double). * @param[out] pDst points to the output generated window * @param[in] blockSize number of samples in the window @@ -362,11 +327,9 @@ extern "C" * | Recommended overlap | 68.0 % | * */ - void arm_nuttall4a_f64( - float64_t * pDst, - uint32_t blockSize); +void arm_nuttall4a_f64(float64_t *pDst, uint32_t blockSize); - /** +/** * @brief Nuttall4a window (float). * @param[out] pDst points to the output generated window * @param[in] blockSize number of samples in the window @@ -382,10 +345,8 @@ extern "C" * * */ - void arm_nuttall4a_f32( - float32_t * pDst, - uint32_t blockSize); - /** +void arm_nuttall4a_f32(float32_t *pDst, uint32_t blockSize); +/** * @brief 92 db blackman harris window (double). * @param[out] pDst points to the output generated window * @param[in] blockSize number of samples in the window @@ -400,11 +361,9 @@ extern "C" * | Recommended overlap | 66.1 % | * */ - void arm_blackman_harris_92db_f64( - float64_t * pDst, - uint32_t blockSize); +void arm_blackman_harris_92db_f64(float64_t *pDst, uint32_t blockSize); - /** +/** * @brief 92 db blackman harris window (float). * @param[out] pDst points to the output generated window * @param[in] blockSize number of samples in the window @@ -420,10 +379,8 @@ extern "C" * * */ - void arm_blackman_harris_92db_f32( - float32_t * pDst, - uint32_t blockSize); - /** +void arm_blackman_harris_92db_f32(float32_t *pDst, uint32_t blockSize); +/** * @brief Nuttall4b window (double). * @param[out] pDst points to the output generated window * @param[in] blockSize number of samples in the window @@ -438,11 +395,9 @@ extern "C" * | Recommended overlap | 66.3 % | * */ - void arm_nuttall4b_f64( - float64_t * pDst, - uint32_t blockSize); +void arm_nuttall4b_f64(float64_t *pDst, uint32_t blockSize); - /** +/** * @brief Nuttall4b window (float). * @param[out] pDst points to the output generated window * @param[in] blockSize number of samples in the window @@ -458,10 +413,8 @@ extern "C" * * */ - void arm_nuttall4b_f32( - float32_t * pDst, - uint32_t blockSize); - /** +void arm_nuttall4b_f32(float32_t *pDst, uint32_t blockSize); +/** * @brief Nuttall4c window (double). * @param[out] pDst points to the output generated window * @param[in] blockSize number of samples in the window @@ -476,11 +429,9 @@ extern "C" * | Recommended overlap | 65.6 % | * */ - void arm_nuttall4c_f64( - float64_t * pDst, - uint32_t blockSize); +void arm_nuttall4c_f64(float64_t *pDst, uint32_t blockSize); - /** +/** * @brief Nuttall4c window (float). * @param[out] pDst points to the output generated window * @param[in] blockSize number of samples in the window @@ -496,10 +447,8 @@ extern "C" * * */ - void arm_nuttall4c_f32( - float32_t * pDst, - uint32_t blockSize); - /** +void arm_nuttall4c_f32(float32_t *pDst, uint32_t blockSize); +/** * @brief Hft90d window (double). * @param[out] pDst points to the output generated window * @param[in] blockSize number of samples in the window @@ -514,11 +463,9 @@ extern "C" * | Recommended overlap | 76.0 % | * */ - void arm_hft90d_f64( - float64_t * pDst, - uint32_t blockSize); +void arm_hft90d_f64(float64_t *pDst, uint32_t blockSize); - /** +/** * @brief Hft90d window (float). * @param[out] pDst points to the output generated window * @param[in] blockSize number of samples in the window @@ -534,10 +481,8 @@ extern "C" * * */ - void arm_hft90d_f32( - float32_t * pDst, - uint32_t blockSize); - /** +void arm_hft90d_f32(float32_t *pDst, uint32_t blockSize); +/** * @brief Hft95 window (double). * @param[out] pDst points to the output generated window * @param[in] blockSize number of samples in the window @@ -552,11 +497,9 @@ extern "C" * | Recommended overlap | 75.6 % | * */ - void arm_hft95_f64( - float64_t * pDst, - uint32_t blockSize); +void arm_hft95_f64(float64_t *pDst, uint32_t blockSize); - /** +/** * @brief Hft95 window (float). * @param[out] pDst points to the output generated window * @param[in] blockSize number of samples in the window @@ -572,10 +515,8 @@ extern "C" * * */ - void arm_hft95_f32( - float32_t * pDst, - uint32_t blockSize); - /** +void arm_hft95_f32(float32_t *pDst, uint32_t blockSize); +/** * @brief Hft116d window (double). * @param[out] pDst points to the output generated window * @param[in] blockSize number of samples in the window @@ -590,11 +531,9 @@ extern "C" * | Recommended overlap | 78.2 % | * */ - void arm_hft116d_f64( - float64_t * pDst, - uint32_t blockSize); +void arm_hft116d_f64(float64_t *pDst, uint32_t blockSize); - /** +/** * @brief Hft116d window (float). * @param[out] pDst points to the output generated window * @param[in] blockSize number of samples in the window @@ -610,10 +549,8 @@ extern "C" * * */ - void arm_hft116d_f32( - float32_t * pDst, - uint32_t blockSize); - /** +void arm_hft116d_f32(float32_t *pDst, uint32_t blockSize); +/** * @brief Hft144d window (double). * @param[out] pDst points to the output generated window * @param[in] blockSize number of samples in the window @@ -628,11 +565,9 @@ extern "C" * | Recommended overlap | 79.9 % | * */ - void arm_hft144d_f64( - float64_t * pDst, - uint32_t blockSize); +void arm_hft144d_f64(float64_t *pDst, uint32_t blockSize); - /** +/** * @brief Hft144d window (float). * @param[out] pDst points to the output generated window * @param[in] blockSize number of samples in the window @@ -648,10 +583,8 @@ extern "C" * * */ - void arm_hft144d_f32( - float32_t * pDst, - uint32_t blockSize); - /** +void arm_hft144d_f32(float32_t *pDst, uint32_t blockSize); +/** * @brief Hft169d window (double). * @param[out] pDst points to the output generated window * @param[in] blockSize number of samples in the window @@ -666,11 +599,9 @@ extern "C" * | Recommended overlap | 81.2 % | * */ - void arm_hft169d_f64( - float64_t * pDst, - uint32_t blockSize); +void arm_hft169d_f64(float64_t *pDst, uint32_t blockSize); - /** +/** * @brief Hft169d window (float). * @param[out] pDst points to the output generated window * @param[in] blockSize number of samples in the window @@ -686,10 +617,8 @@ extern "C" * * */ - void arm_hft169d_f32( - float32_t * pDst, - uint32_t blockSize); - /** +void arm_hft169d_f32(float32_t *pDst, uint32_t blockSize); +/** * @brief Hft196d window (double). * @param[out] pDst points to the output generated window * @param[in] blockSize number of samples in the window @@ -704,11 +633,9 @@ extern "C" * | Recommended overlap | 82.3 % | * */ - void arm_hft196d_f64( - float64_t * pDst, - uint32_t blockSize); +void arm_hft196d_f64(float64_t *pDst, uint32_t blockSize); - /** +/** * @brief Hft196d window (float). * @param[out] pDst points to the output generated window * @param[in] blockSize number of samples in the window @@ -724,10 +651,8 @@ extern "C" * * */ - void arm_hft196d_f32( - float32_t * pDst, - uint32_t blockSize); - /** +void arm_hft196d_f32(float32_t *pDst, uint32_t blockSize); +/** * @brief Hft223d window (double). * @param[out] pDst points to the output generated window * @param[in] blockSize number of samples in the window @@ -742,11 +667,9 @@ extern "C" * | Recommended overlap | 83.3 % | * */ - void arm_hft223d_f64( - float64_t * pDst, - uint32_t blockSize); +void arm_hft223d_f64(float64_t *pDst, uint32_t blockSize); - /** +/** * @brief Hft223d window (float). * @param[out] pDst points to the output generated window * @param[in] blockSize number of samples in the window @@ -762,10 +685,8 @@ extern "C" * * */ - void arm_hft223d_f32( - float32_t * pDst, - uint32_t blockSize); - /** +void arm_hft223d_f32(float32_t *pDst, uint32_t blockSize); +/** * @brief Hft248d window (double). * @param[out] pDst points to the output generated window * @param[in] blockSize number of samples in the window @@ -780,11 +701,9 @@ extern "C" * | Recommended overlap | 84.1 % | * */ - void arm_hft248d_f64( - float64_t * pDst, - uint32_t blockSize); +void arm_hft248d_f64(float64_t *pDst, uint32_t blockSize); - /** +/** * @brief Hft248d window (float). * @param[out] pDst points to the output generated window * @param[in] blockSize number of samples in the window @@ -800,12 +719,9 @@ extern "C" * * */ - void arm_hft248d_f32( - float32_t * pDst, - uint32_t blockSize); - +void arm_hft248d_f32(float32_t *pDst, uint32_t blockSize); -#ifdef __cplusplus +#ifdef __cplusplus } #endif diff --git a/Libraries/CMSIS/Device/Maxim/MAX32655/Source/heap.c b/Libraries/CMSIS/Device/Maxim/MAX32655/Source/heap.c index 80559e95034..4409f35aff9 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32655/Source/heap.c +++ b/Libraries/CMSIS/Device/Maxim/MAX32655/Source/heap.c @@ -21,6 +21,7 @@ #include #include #include +#include /* sbrk @@ -48,3 +49,79 @@ caddr_t _sbrk(int incr) return (caddr_t)prev_heap_end; } + +// struct mallinfo { +// size_t arena; /* total space allocated from system */ +// size_t ordblks; /* number of non-inuse chunks */ +// size_t smblks; /* unused -- always zero */ +// size_t hblks; /* number of mmapped regions */ +// size_t hblkhd; /* total space in mmapped regions */ +// size_t usmblks; /* unused -- always zero */ +// size_t fsmblks; /* unused -- always zero */ +// size_t uordblks; /* total allocated space */ +// size_t fordblks; /* total non-inuse space */ +// size_t keepcost; /* top-most, releasable (via malloc_trim) space */ +// }; + +/* +The structure fields contain the following information: + + arena The total amount of memory allocated by means other than + mmap(2) (i.e., memory allocated on the heap). This figure + includes both in-use blocks and blocks on the free list. + + ordblks + The number of ordinary (i.e., non-fastbin) free blocks. + + smblks The number of fastbin free blocks (see mallopt(3)). + + hblks The number of blocks currently allocated using mmap(2). + (See the discussion of M_MMAP_THRESHOLD in mallopt(3).) + + hblkhd The number of bytes in blocks currently allocated using + mmap(2). + + usmblks + This field is unused, and is always 0. Historically, it + was the "highwater mark" for allocated space—that is, the + maximum amount of space that was ever allocated (in + bytes); this field was maintained only in nonthreading + environments. + + fsmblks + The total number of bytes in fastbin free blocks. + + uordblks + The total number of bytes used by in-use allocations. + + fordblks + The total number of bytes in free blocks. + + keepcost + The total amount of releasable free space at the top of + the heap. This is the maximum number of bytes that could + ideally (i.e., ignoring page alignment restrictions, and + so on) be released by malloc_trim(3). +*/ + +struct mallinfo mallinfo(void) +{ + struct mallinfo temp_mallinfo; + + if (heap_end == 0) { + heap_end = (caddr_t)&__HeapBase; + } + + temp_mallinfo.arena = ((size_t)&__HeapLimit - (size_t)&__HeapBase); + temp_mallinfo.ordblks = 0; /* Unused */ + temp_mallinfo.smblks = 0; /* Unused */ + temp_mallinfo.hblks = 0; /* Unused */ + temp_mallinfo.hblkhd = 0; /* Unused */ + temp_mallinfo.usmblks = 0; /* Unused */ + temp_mallinfo.fsmblks = 0; /* Unused */ + temp_mallinfo.uordblks = (size_t)heap_end - (size_t)&__HeapBase; + temp_mallinfo.fordblks = (size_t)&__HeapLimit - (size_t)heap_end; + temp_mallinfo.keepcost = 0 /* Unused */; + + return temp_mallinfo; +} diff --git a/Libraries/CMSIS/Device/Maxim/MAX32665/Source/heap.c b/Libraries/CMSIS/Device/Maxim/MAX32665/Source/heap.c index 80559e95034..4409f35aff9 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32665/Source/heap.c +++ b/Libraries/CMSIS/Device/Maxim/MAX32665/Source/heap.c @@ -21,6 +21,7 @@ #include #include #include +#include /* sbrk @@ -48,3 +49,79 @@ caddr_t _sbrk(int incr) return (caddr_t)prev_heap_end; } + +// struct mallinfo { +// size_t arena; /* total space allocated from system */ +// size_t ordblks; /* number of non-inuse chunks */ +// size_t smblks; /* unused -- always zero */ +// size_t hblks; /* number of mmapped regions */ +// size_t hblkhd; /* total space in mmapped regions */ +// size_t usmblks; /* unused -- always zero */ +// size_t fsmblks; /* unused -- always zero */ +// size_t uordblks; /* total allocated space */ +// size_t fordblks; /* total non-inuse space */ +// size_t keepcost; /* top-most, releasable (via malloc_trim) space */ +// }; + +/* +The structure fields contain the following information: + + arena The total amount of memory allocated by means other than + mmap(2) (i.e., memory allocated on the heap). This figure + includes both in-use blocks and blocks on the free list. + + ordblks + The number of ordinary (i.e., non-fastbin) free blocks. + + smblks The number of fastbin free blocks (see mallopt(3)). + + hblks The number of blocks currently allocated using mmap(2). + (See the discussion of M_MMAP_THRESHOLD in mallopt(3).) + + hblkhd The number of bytes in blocks currently allocated using + mmap(2). + + usmblks + This field is unused, and is always 0. Historically, it + was the "highwater mark" for allocated space—that is, the + maximum amount of space that was ever allocated (in + bytes); this field was maintained only in nonthreading + environments. + + fsmblks + The total number of bytes in fastbin free blocks. + + uordblks + The total number of bytes used by in-use allocations. + + fordblks + The total number of bytes in free blocks. + + keepcost + The total amount of releasable free space at the top of + the heap. This is the maximum number of bytes that could + ideally (i.e., ignoring page alignment restrictions, and + so on) be released by malloc_trim(3). +*/ + +struct mallinfo mallinfo(void) +{ + struct mallinfo temp_mallinfo; + + if (heap_end == 0) { + heap_end = (caddr_t)&__HeapBase; + } + + temp_mallinfo.arena = ((size_t)&__HeapLimit - (size_t)&__HeapBase); + temp_mallinfo.ordblks = 0; /* Unused */ + temp_mallinfo.smblks = 0; /* Unused */ + temp_mallinfo.hblks = 0; /* Unused */ + temp_mallinfo.hblkhd = 0; /* Unused */ + temp_mallinfo.usmblks = 0; /* Unused */ + temp_mallinfo.fsmblks = 0; /* Unused */ + temp_mallinfo.uordblks = (size_t)heap_end - (size_t)&__HeapBase; + temp_mallinfo.fordblks = (size_t)&__HeapLimit - (size_t)heap_end; + temp_mallinfo.keepcost = 0 /* Unused */; + + return temp_mallinfo; +} diff --git a/Libraries/CMSIS/Device/Maxim/MAX32690/Source/heap.c b/Libraries/CMSIS/Device/Maxim/MAX32690/Source/heap.c index 80559e95034..4409f35aff9 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32690/Source/heap.c +++ b/Libraries/CMSIS/Device/Maxim/MAX32690/Source/heap.c @@ -21,6 +21,7 @@ #include #include #include +#include /* sbrk @@ -48,3 +49,79 @@ caddr_t _sbrk(int incr) return (caddr_t)prev_heap_end; } + +// struct mallinfo { +// size_t arena; /* total space allocated from system */ +// size_t ordblks; /* number of non-inuse chunks */ +// size_t smblks; /* unused -- always zero */ +// size_t hblks; /* number of mmapped regions */ +// size_t hblkhd; /* total space in mmapped regions */ +// size_t usmblks; /* unused -- always zero */ +// size_t fsmblks; /* unused -- always zero */ +// size_t uordblks; /* total allocated space */ +// size_t fordblks; /* total non-inuse space */ +// size_t keepcost; /* top-most, releasable (via malloc_trim) space */ +// }; + +/* +The structure fields contain the following information: + + arena The total amount of memory allocated by means other than + mmap(2) (i.e., memory allocated on the heap). This figure + includes both in-use blocks and blocks on the free list. + + ordblks + The number of ordinary (i.e., non-fastbin) free blocks. + + smblks The number of fastbin free blocks (see mallopt(3)). + + hblks The number of blocks currently allocated using mmap(2). + (See the discussion of M_MMAP_THRESHOLD in mallopt(3).) + + hblkhd The number of bytes in blocks currently allocated using + mmap(2). + + usmblks + This field is unused, and is always 0. Historically, it + was the "highwater mark" for allocated space—that is, the + maximum amount of space that was ever allocated (in + bytes); this field was maintained only in nonthreading + environments. + + fsmblks + The total number of bytes in fastbin free blocks. + + uordblks + The total number of bytes used by in-use allocations. + + fordblks + The total number of bytes in free blocks. + + keepcost + The total amount of releasable free space at the top of + the heap. This is the maximum number of bytes that could + ideally (i.e., ignoring page alignment restrictions, and + so on) be released by malloc_trim(3). +*/ + +struct mallinfo mallinfo(void) +{ + struct mallinfo temp_mallinfo; + + if (heap_end == 0) { + heap_end = (caddr_t)&__HeapBase; + } + + temp_mallinfo.arena = ((size_t)&__HeapLimit - (size_t)&__HeapBase); + temp_mallinfo.ordblks = 0; /* Unused */ + temp_mallinfo.smblks = 0; /* Unused */ + temp_mallinfo.hblks = 0; /* Unused */ + temp_mallinfo.hblkhd = 0; /* Unused */ + temp_mallinfo.usmblks = 0; /* Unused */ + temp_mallinfo.fsmblks = 0; /* Unused */ + temp_mallinfo.uordblks = (size_t)heap_end - (size_t)&__HeapBase; + temp_mallinfo.fordblks = (size_t)&__HeapLimit - (size_t)heap_end; + temp_mallinfo.keepcost = 0 /* Unused */; + + return temp_mallinfo; +} diff --git a/Libraries/Cordio/controller/include/ble/ll_init_api.h b/Libraries/Cordio/controller/include/ble/ll_init_api.h index 0bf0a9c793a..ad06f3622d8 100644 --- a/Libraries/Cordio/controller/include/ble/ll_init_api.h +++ b/Libraries/Cordio/controller/include/ble/ll_init_api.h @@ -93,6 +93,7 @@ uint32_t LlInitControllerInit(LlInitRtCfg_t *pCfg); uint32_t LlInitSetBbRtCfg(const BbRtCfg_t *pBbRtCfg, const uint8_t wlSizeCfg, const uint8_t rlSizeCfg, const uint8_t plSizeCfg, uint8_t *pFreeMem, uint32_t freeMemAvail); uint32_t LlInitSetLlRtCfg(const LlRtCfg_t *pLlRtCfg, uint8_t *pFreeMem, uint32_t freeMemAvail); +uint32_t LlInitSetRtCfg(LlInitRtCfg_t *pLlInitRtCfg); void LlInitBbInit(void); void LlInitSchInit(void); void LlInitLlInit(void); @@ -101,6 +102,7 @@ void LlInitLhciInit(void); void LlMathSetSeed(const uint32_t *pSeed); void LlInitLhciHandler(void); + /*! \} */ /* LL_INIT_API */ #ifdef __cplusplus diff --git a/Libraries/Cordio/controller/sources/ble/init/init.c b/Libraries/Cordio/controller/sources/ble/init/init.c index 3d0a8a078a5..92c5e6db7c2 100644 --- a/Libraries/Cordio/controller/sources/ble/init/init.c +++ b/Libraries/Cordio/controller/sources/ble/init/init.c @@ -310,28 +310,39 @@ uint32_t LlInitSetLlRtCfg(const LlRtCfg_t *pLlRtCfg, uint8_t *pFreeMem, uint32_t /*************************************************************************************************/ /*! - * \brief Initialize configuration. + * \brief Set LL and BB runtime configurations. * * \param pCfg Runtime configuration. * * \return Memory used. */ /*************************************************************************************************/ -uint32_t LlInit(LlInitRtCfg_t *pCfg) +uint32_t LlInitSetRtCfg(LlInitRtCfg_t *pCfg) { - uint32_t memUsed; - uint32_t totalMemUsed = 0; - - memUsed = LlInitSetBbRtCfg(pCfg->pBbRtCfg, pCfg->wlSizeCfg, pCfg->rlSizeCfg, pCfg->plSizeCfg, - pCfg->pFreeMem, pCfg->freeMemAvail); + uint32_t memUsed = LlInitSetBbRtCfg(pCfg->pBbRtCfg, pCfg->wlSizeCfg, pCfg->rlSizeCfg, pCfg->plSizeCfg, + pCfg->pFreeMem, pCfg->freeMemAvail); pCfg->pFreeMem += memUsed; pCfg->freeMemAvail -= memUsed; - totalMemUsed += memUsed; - memUsed = LlInitSetLlRtCfg(pCfg->pLlRtCfg, pCfg->pFreeMem, pCfg->freeMemAvail); + memUsed += LlInitSetLlRtCfg(pCfg->pLlRtCfg, pCfg->pFreeMem, pCfg->freeMemAvail); pCfg->pFreeMem += memUsed; pCfg->freeMemAvail -= memUsed; - totalMemUsed += memUsed; + + return memUsed; +} + +/*************************************************************************************************/ +/*! + * \brief Initialize configuration. + * + * \param pCfg Runtime configuration. + * + * \return Memory used. + */ +/*************************************************************************************************/ +uint32_t LlInit(LlInitRtCfg_t *pCfg) +{ + uint32_t totalMemUsed = LlInitSetRtCfg(pCfg); LlInitBbInit(); LlInitSchInit(); diff --git a/Libraries/Cordio/controller/sources/ble/ll/ll_init.c b/Libraries/Cordio/controller/sources/ble/ll/ll_init.c index ffa938219ed..de89e2b33f3 100644 --- a/Libraries/Cordio/controller/sources/ble/ll/ll_init.c +++ b/Libraries/Cordio/controller/sources/ble/ll/ll_init.c @@ -113,7 +113,6 @@ void LlGetDefaultRunTimeCfg(LlRtCfg_t *pCfg) /*************************************************************************************************/ void LlInitRunTimeCfg(const LlRtCfg_t *pCfg) { - WSF_ASSERT(pLctrRtCfg == NULL); WSF_ASSERT(pCfg); WSF_ASSERT(pCfg->btVer >= LL_VER_BT_CORE_SPEC_4_0); diff --git a/Libraries/Cordio/controller/sources/common/bb/bb_main.c b/Libraries/Cordio/controller/sources/common/bb/bb_main.c index aadddbc8331..6607fa158ab 100644 --- a/Libraries/Cordio/controller/sources/common/bb/bb_main.c +++ b/Libraries/Cordio/controller/sources/common/bb/bb_main.c @@ -51,7 +51,6 @@ const BbRtCfg_t *pBbRtCfg = NULL; /*!< Runtime configuration. */ /*************************************************************************************************/ void BbInitRunTimeCfg(const BbRtCfg_t *pCfg) { - WSF_ASSERT(pBbRtCfg == NULL); WSF_ASSERT(pCfg); WSF_ASSERT(pCfg->clkPpm >= 20); diff --git a/Libraries/Cordio/wsf/sources/targets/baremetal/wsf_heap.c b/Libraries/Cordio/wsf/sources/targets/baremetal/wsf_heap.c index 3c84251274a..992a98fabe9 100644 --- a/Libraries/Cordio/wsf/sources/targets/baremetal/wsf_heap.c +++ b/Libraries/Cordio/wsf/sources/targets/baremetal/wsf_heap.c @@ -24,6 +24,7 @@ #if defined ( __GNUC__ ) #include +#include #endif /* __GNUC__ */ #include "wsf_types.h" @@ -38,37 +39,16 @@ Macros **************************************************************************************************/ -#ifndef WSF_HEAP_SIZE -#if(PAL_CFG_LL_MAX == 1) -/* Larger link layer configurations will require more heap space. */ -#define WSF_HEAP_SIZE 0x18000 -#else -/* This is the minimum heap size. */ -#define WSF_HEAP_SIZE 0x8000 -#endif -#endif - /************************************************************************************************** Global Variables **************************************************************************************************/ -static void* freeStartAddr = 0; -static uint32_t freeLen = 0; - -/*************************************************************************************************/ -/*! - * \brief Initialize the heap memory. - */ -/*************************************************************************************************/ -static void wsfHeapInit(void) -{ - freeStartAddr = sbrk(WSF_HEAP_SIZE); - freeLen = WSF_HEAP_SIZE; -} +static void* freeStartAddr = NULL; +static uint32_t heapUsed = 0; /*************************************************************************************************/ /*! - * \brief Reserve heap memory. + * \brief Allocate heap memory. * * \param size Number of bytes of heap memory used. */ @@ -78,16 +58,8 @@ void WsfHeapAlloc(uint32_t size) /* Round up to nearest multiple of 4 for word alignment */ size = (size + 3) & ~3; - if(freeStartAddr == 0) { - wsfHeapInit(); - } - - if(freeLen < size) { - WSF_ASSERT(FALSE); - } - - freeStartAddr += size; - freeLen -= size; + freeStartAddr = sbrk(size); + heapUsed += size; } /*************************************************************************************************/ @@ -99,8 +71,9 @@ void WsfHeapAlloc(uint32_t size) /*************************************************************************************************/ void *WsfHeapGetFreeStartAddress(void) { - if(freeStartAddr == 0) { - wsfHeapInit(); + if(freeStartAddr == (caddr_t)-1) { + WSF_ASSERT(0); + return NULL; } return freeStartAddr; @@ -115,11 +88,9 @@ void *WsfHeapGetFreeStartAddress(void) /*************************************************************************************************/ uint32_t WsfHeapCountAvailable(void) { - if(freeStartAddr == 0) { - wsfHeapInit(); - } + struct mallinfo temp_mallinfo = mallinfo(); - return freeLen; + return temp_mallinfo.fordblks; } /*************************************************************************************************/ @@ -131,9 +102,5 @@ uint32_t WsfHeapCountAvailable(void) /*************************************************************************************************/ uint32_t WsfHeapCountUsed(void) { - if(freeStartAddr == 0) { - wsfHeapInit(); - } - - return (WSF_HEAP_SIZE - freeLen); + return heapUsed; } From 3bdf51490a750ab762b1fbe2430338f49751b686 Mon Sep 17 00:00:00 2001 From: Mert Ekren Date: Thu, 17 Oct 2024 21:52:18 +0300 Subject: [PATCH 07/37] fix(PeriphDrivers): Add GPIO Drive Strength Configuration for ME14 (#1223) Signed-off-by: Mert Ekren --- Libraries/PeriphDrivers/Source/GPIO/gpio_me14.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/Libraries/PeriphDrivers/Source/GPIO/gpio_me14.c b/Libraries/PeriphDrivers/Source/GPIO/gpio_me14.c index 8caa986ae4d..38e489f1c1f 100644 --- a/Libraries/PeriphDrivers/Source/GPIO/gpio_me14.c +++ b/Libraries/PeriphDrivers/Source/GPIO/gpio_me14.c @@ -133,7 +133,12 @@ int MXC_GPIO_Config(const mxc_gpio_cfg_t *cfg) return E_BAD_PARAM; } - return E_NO_ERROR; + // Configure the drive strength + if (cfg->func == MXC_GPIO_FUNC_IN) { + return E_NO_ERROR; + } else { + return MXC_GPIO_SetDriveStrength(gpio, cfg->drvstr, cfg->mask); + } } /* ************************************************************************** */ From 8c24d39679abe46db46b3cc4b607439e04bc004d Mon Sep 17 00:00:00 2001 From: Furkan AKKIZ <94184469+hfakkiz@users.noreply.github.com> Date: Mon, 21 Oct 2024 18:29:00 +0300 Subject: [PATCH 08/37] fix(PeriphDrivers): Fix build warnings for MAX78002 ADC (#1235) Signed-off-by: Furkan Akkiz --- Libraries/PeriphDrivers/Source/ADC/adc_ai87.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/Libraries/PeriphDrivers/Source/ADC/adc_ai87.c b/Libraries/PeriphDrivers/Source/ADC/adc_ai87.c index 6fa2ec4cf60..7a38c23184d 100644 --- a/Libraries/PeriphDrivers/Source/ADC/adc_ai87.c +++ b/Libraries/PeriphDrivers/Source/ADC/adc_ai87.c @@ -37,9 +37,9 @@ */ #define MXC_F_MCR_ADCCFG2_CH 0x3 -#define TEMP_FACTOR 530.582f / 4096.0 -#define TEMP_FACTOR1V25 1.25 * TEMP_FACTOR -#define TEMP_FACTOR2V048 2.048 * TEMP_FACTOR +#define TEMP_FACTOR 530.582f / 4096.0f +#define TEMP_FACTOR1V25 1.25f * TEMP_FACTOR +#define TEMP_FACTOR2V048 2.048f * TEMP_FACTOR static void initGPIOForChannel(mxc_adc_chsel_t channel) { @@ -397,7 +397,7 @@ int MXC_ConvertTemperature_ToF(uint16_t tempSensor_Readout, mxc_adc_refsel_t ref float *temp) { if (MXC_ConvertTemperature_ToK(tempSensor_Readout, ref, ext_ref, temp) == E_NO_ERROR) { - *temp = ((*temp * 1.8) - 459.67f); + *temp = (*temp * 1.8f) - 459.67f; return E_NO_ERROR; } else { return E_BAD_PARAM; From 06330acc5f3c87c5f1c5992e25767bdeffcf9356 Mon Sep 17 00:00:00 2001 From: EricB-ADI <122300463+EricB-ADI@users.noreply.github.com> Date: Mon, 21 Oct 2024 13:26:42 -0500 Subject: [PATCH 09/37] fix(BLE): Update PAL UART to derive clock via IBRO (#1236) --- .../platform/targets/maxim/max32655/sources/pal_uart.c | 10 ++-------- .../platform/targets/maxim/max32690/sources/pal_uart.c | 9 +-------- 2 files changed, 3 insertions(+), 16 deletions(-) diff --git a/Libraries/Cordio/platform/targets/maxim/max32655/sources/pal_uart.c b/Libraries/Cordio/platform/targets/maxim/max32655/sources/pal_uart.c index 16dd4dd44a4..231b2545c1e 100644 --- a/Libraries/Cordio/platform/targets/maxim/max32655/sources/pal_uart.c +++ b/Libraries/Cordio/platform/targets/maxim/max32655/sources/pal_uart.c @@ -295,14 +295,8 @@ void PalUartInit(PalUartId_t id, const PalUartConfig_t *pCfg) palUartCb[uartNum].rdCback = pCfg->rdCback; palUartCb[uartNum].wrCback = pCfg->wrCback; - /* Initialize the UART */ - if(uartNum == 3) { - /* Use the IBRO clock for UART3 */ - result = MXC_UART_Init(MXC_UART_GET_UART(uartNum), pCfg->baud, MXC_UART_IBRO_CLK); - } else { - /* Use the APB clock for rest of the UARTs */ - result = MXC_UART_Init(MXC_UART_GET_UART(uartNum), pCfg->baud, MXC_UART_APB_CLK); - } + result = MXC_UART_Init(MXC_UART_GET_UART(uartNum), pCfg->baud, MXC_UART_IBRO_CLK); + (void)result; PAL_SYS_ASSERT(result == 0); diff --git a/Libraries/Cordio/platform/targets/maxim/max32690/sources/pal_uart.c b/Libraries/Cordio/platform/targets/maxim/max32690/sources/pal_uart.c index b5b49f3cccc..51f5af827af 100644 --- a/Libraries/Cordio/platform/targets/maxim/max32690/sources/pal_uart.c +++ b/Libraries/Cordio/platform/targets/maxim/max32690/sources/pal_uart.c @@ -301,14 +301,7 @@ void PalUartInit(PalUartId_t id, const PalUartConfig_t *pCfg) palUartCb[uartNum].rdCback = pCfg->rdCback; palUartCb[uartNum].wrCback = pCfg->wrCback; - /* Initialize the UART */ - if(uartNum == 3) { - /* Use the IBRO clock for UART3 */ - result = MXC_UART_Init(MXC_UART_GET_UART(uartNum), pCfg->baud, MXC_UART_IBRO_CLK); - } else { - /* Use the APB clock for rest of the UARTs */ - result = MXC_UART_Init(MXC_UART_GET_UART(uartNum), pCfg->baud, MXC_UART_APB_CLK); - } + result = MXC_UART_Init(MXC_UART_GET_UART(uartNum), pCfg->baud, MXC_UART_IBRO_CLK); (void)result; PAL_SYS_ASSERT(result == 0); From 6dd49f8b40a0d67994184b7e8f2420b50e4e21ff Mon Sep 17 00:00:00 2001 From: Sihyung Woo <75494566+sihyung-maxim@users.noreply.github.com> Date: Tue, 22 Oct 2024 14:49:12 -0500 Subject: [PATCH 10/37] fix(workflow): Update clang-format-run-pr.yml to Node20.js and update permissions (#1233) --- .github/workflows/clang-format-run-pr.yml | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/.github/workflows/clang-format-run-pr.yml b/.github/workflows/clang-format-run-pr.yml index a11fd261615..f3815c3f745 100644 --- a/.github/workflows/clang-format-run-pr.yml +++ b/.github/workflows/clang-format-run-pr.yml @@ -27,14 +27,20 @@ on: permissions: actions: write + contents: write env: CLANG_VERSION: 14 jobs: - run-on-pr: - # Run on branchs, not forked PR branches + run-on-pr: + permissions: + contents: write + pull-requests: write + actions: write + + # Run on branches, not forked PR branches if: | contains(github.event.comment.body, '/clang-format-run') @@ -47,7 +53,7 @@ jobs: run: | sudo apt-get install clang-format-${CLANG_VERSION} - - uses: actions/github-script@v6 + - uses: actions/github-script@v7 id: get-pr with: script: | From f557dbf1716422a7f4b376e1c3a911076cc9820b Mon Sep 17 00:00:00 2001 From: Cristian Cruz <71054319+crsz20@users.noreply.github.com> Date: Tue, 22 Oct 2024 16:34:17 -0500 Subject: [PATCH 11/37] fix(BLE): Resolve double increment of memory management in LlInitSetRtCfg (#1237) --- .github/workflows/BLE_Examples_Test.yml | 26 +++++++------------ .../Cordio/controller/sources/ble/init/init.c | 12 ++++++--- 2 files changed, 19 insertions(+), 19 deletions(-) diff --git a/.github/workflows/BLE_Examples_Test.yml b/.github/workflows/BLE_Examples_Test.yml index fb7db194fbb..8e59e0816fd 100644 --- a/.github/workflows/BLE_Examples_Test.yml +++ b/.github/workflows/BLE_Examples_Test.yml @@ -595,8 +595,6 @@ jobs: boards: | max32655_board1 max32655_board2 - max32665_board1 - max32690_board_w1 lock: true timeout: 3600 # Attempt to lock for an hour @@ -615,23 +613,21 @@ jobs: # sed -i "s/'S'/'!'/g" Examples/MAX32690/Bluetooth/BLE_otac/datc_main.c - name: Erase Boards DATS - if: ${{env.MAX32655_DATS_CONNECTED_TEST == 'true' || env.MAX32665_DATS_CONNECTED_TEST == 'true' || env.MAX32690_DATS_CONNECTED_TEST == 'true'}} + if: ${{env.MAX32655_DATS_CONNECTED_TEST == 'true' || env.MAX32655_RUN_ALL_TEST == 'true'}} uses: Analog-Devices-MSDK/btm-ci-scripts/actions/ocderase@v1.1 with: board: | max32655_board1 max32655_board2 - max32665_board1 - max32690_board_w1 has_two_flash_banks: | true true - true - true + # true + # true - name: Flash DATS 655 - if: ${{env.MAX32655_DATS_CONNECTED_TEST == 'true'}} + if: ${{env.MAX32655_DATS_CONNECTED_TEST == 'true' || env.MAX32655_RUN_ALL_TEST == 'true'}} uses: Analog-Devices-MSDK/btm-ci-scripts/actions/ocdflash@v1.1 with: board: | @@ -652,7 +648,7 @@ jobs: distclean: true - name: DATS 655 - if: ${{env.MAX32655_DATS_CONNECTED_TEST == 'true'}} + if: ${{env.MAX32655_DATS_CONNECTED_TEST == 'true' || env.MAX32655_RUN_ALL_TEST == 'true'}} run: | DATS_TEST_DIR=$TEST_DIR/dats DATS_BOARD_655=max32655_board1 @@ -662,17 +658,15 @@ jobs: - name: Erase Boards OTAS - if: ${{env.MAX32655_DATS_CONNECTED_TEST == 'true' || env.MAX32665_DATS_CONNECTED_TEST == 'true' || env.MAX32690_DATS_CONNECTED_TEST == 'true'}} + if: ${{env.MAX32655_DATS_CONNECTED_TEST == 'true' || env.MAX32655_RUN_ALL_TEST == 'true'}} uses: Analog-Devices-MSDK/btm-ci-scripts/actions/ocderase@v1.1 with: board: | max32655_board1 max32655_board2 - max32665_board1 - max32690_board_w1 - name: Flash OTAS - if: ${{env.MAX32655_DATS_CONNECTED_TEST == 'true' || env.MAX32665_DATS_CONNECTED_TEST == 'true' || env.MAX32690_DATS_CONNECTED_TEST == 'true'}} + if: ${{env.MAX32655_DATS_CONNECTED_TEST == 'true' || env.MAX32655_RUN_ALL_TEST == 'true'}} uses: Analog-Devices-MSDK/btm-ci-scripts/actions/ocdflash@v1.1 with: board: | @@ -695,13 +689,13 @@ jobs: distclean: true - name: OTAS - if: ${{env.MAX32655_DATS_CONNECTED_TEST == 'true' || env.MAX32665_DATS_CONNECTED_TEST == 'true' || env.MAX32690_DATS_CONNECTED_TEST == 'true'}} + if: ${{env.MAX32655_DATS_CONNECTED_TEST == 'true' || env.MAX32655_RUN_ALL_TEST == 'true'}} run: | OTAS_TEST_DIR=$TEST_DIR/otas OTAS_BOARD_655=max32655_board1 OTAC_BOARD_655=max32655_board2 - OTAC_BOARD_665=max32665_board1 - OTAC_BOARD_690=max32690_board_w1 + # OTAC_BOARD_665=max32665_board1 + # OTAC_BOARD_690=max32690_board_w1 if [[ $MAX32655_OTAS_CONNECTED_TEST == 'true' ]]; then diff --git a/Libraries/Cordio/controller/sources/ble/init/init.c b/Libraries/Cordio/controller/sources/ble/init/init.c index 92c5e6db7c2..60e85ffa86f 100644 --- a/Libraries/Cordio/controller/sources/ble/init/init.c +++ b/Libraries/Cordio/controller/sources/ble/init/init.c @@ -319,16 +319,22 @@ uint32_t LlInitSetLlRtCfg(const LlRtCfg_t *pLlRtCfg, uint8_t *pFreeMem, uint32_t /*************************************************************************************************/ uint32_t LlInitSetRtCfg(LlInitRtCfg_t *pCfg) { - uint32_t memUsed = LlInitSetBbRtCfg(pCfg->pBbRtCfg, pCfg->wlSizeCfg, pCfg->rlSizeCfg, pCfg->plSizeCfg, + uint32_t totalMemUsed = 0; + uint32_t memUsed; + + memUsed = LlInitSetBbRtCfg(pCfg->pBbRtCfg, pCfg->wlSizeCfg, pCfg->rlSizeCfg, pCfg->plSizeCfg, pCfg->pFreeMem, pCfg->freeMemAvail); + pCfg->pFreeMem += memUsed; pCfg->freeMemAvail -= memUsed; + totalMemUsed += memUsed; - memUsed += LlInitSetLlRtCfg(pCfg->pLlRtCfg, pCfg->pFreeMem, pCfg->freeMemAvail); + memUsed = LlInitSetLlRtCfg(pCfg->pLlRtCfg, pCfg->pFreeMem, pCfg->freeMemAvail); pCfg->pFreeMem += memUsed; pCfg->freeMemAvail -= memUsed; + totalMemUsed += memUsed; - return memUsed; + return totalMemUsed; } /*************************************************************************************************/ From db69388844d29e727cd245b90b54279341f77401 Mon Sep 17 00:00:00 2001 From: Brandon Hurst <82959533+Brandon-Hurst@users.noreply.github.com> Date: Thu, 24 Oct 2024 11:53:34 -0700 Subject: [PATCH 12/37] fix(PeriphDrivers): Fix nvic-table.c warnings and remove unused DMA RevB drivers (#1229) --- Libraries/PeriphDrivers/Source/DMA/dma_revb.c | 507 ------------------ Libraries/PeriphDrivers/Source/DMA/dma_revb.h | 55 -- .../PeriphDrivers/Source/SYS/nvic_table.c | 12 +- 3 files changed, 6 insertions(+), 568 deletions(-) delete mode 100644 Libraries/PeriphDrivers/Source/DMA/dma_revb.c delete mode 100644 Libraries/PeriphDrivers/Source/DMA/dma_revb.h diff --git a/Libraries/PeriphDrivers/Source/DMA/dma_revb.c b/Libraries/PeriphDrivers/Source/DMA/dma_revb.c deleted file mode 100644 index e91c33288e5..00000000000 --- a/Libraries/PeriphDrivers/Source/DMA/dma_revb.c +++ /dev/null @@ -1,507 +0,0 @@ -/****************************************************************************** - * - * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by - * Analog Devices, Inc.), - * Copyright (C) 2023-2024 Analog Devices, Inc. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ******************************************************************************/ - -/****** Includes *******/ -#include -#include -#include "mxc_device.h" -#include "mxc_assert.h" -#include "mxc_lock.h" -#include "mxc_sys.h" -#include "dma.h" -#include "dma_revb.h" - -/***** Definitions *****/ -#define CHECK_HANDLE(x) ((x >= 0) && (x < MXC_DMA_CHANNELS) && (dma_resource[x].valid)) - -typedef struct { - void *userCallback; // user given callback - void *dest; // memcpy destination -} mxc_dma_highlevel_t; - -typedef struct { - unsigned int valid; // Flag to invalidate this resource - unsigned int instance; // Hardware instance of this DMA controller - unsigned int id; // Channel ID, which matches the index into the underlying hardware - mxc_dma_ch_regs_t *regs; // Pointer to the registers for this channel - void (*cb)(int, int); // Pointer to a callback function type -} mxc_dma_channel_t; - -/******* Globals *******/ -static unsigned int dma_initialized = 0; -static mxc_dma_channel_t dma_resource[MXC_DMA_CHANNELS]; -static mxc_dma_highlevel_t memcpy_resource[MXC_DMA_CHANNELS]; -static uint32_t dma_lock; - -/****** Functions ******/ -static void memcpy_callback(int ch, int error); -static void transfer_callback(int ch, int error); - -int MXC_DMA_RevB_Init(void) -{ - int i; - - if (dma_initialized) { - return E_BAD_STATE; - } - - //TODO(ADI): Necessary? - ///* Initialize any system-level DMA settings */ - //SYS_DMA_Init(); - - /* Initialize mutex */ - MXC_FreeLock(&dma_lock); - - if (MXC_GetLock(&dma_lock, 1) != E_NO_ERROR) { - return E_BUSY; - } - - /* Ensure all channels are disabled at start, clear flags, init handles */ - MXC_DMA->inten = 0; - - for (i = 0; i < MXC_DMA_CHANNELS; i++) { - dma_resource[i].valid = 0; - dma_resource[i].instance = 0; - dma_resource[i].id = i; - dma_resource[i].regs = (mxc_dma_ch_regs_t *)&MXC_DMA->ch[i]; - dma_resource[i].regs->ctrl = 0; - dma_resource[i].regs->status = dma_resource[i].regs->status; - - dma_resource[i].cb = NULL; - } - - dma_initialized++; - MXC_FreeLock(&dma_lock); - - return E_NO_ERROR; -} - -int MXC_DMA_RevB_AcquireChannel(void) -{ - int i, channel; - - /* Check for initialization */ - if (!dma_initialized) { - return E_BAD_STATE; - } - - /* If DMA is locked return busy */ - if (MXC_GetLock(&dma_lock, 1) != E_NO_ERROR) { - return E_BUSY; - } - - /* Default is no channel available */ - channel = E_NONE_AVAIL; - - if (dma_initialized) { - for (i = 0; i < MXC_DMA_CHANNELS; i++) { - if (!dma_resource[i].valid) { - /* Found one */ - channel = i; - dma_resource[i].valid = 1; - dma_resource[i].regs->ctrl = 0; - dma_resource[i].regs->cntrld = - 0; /* Used by DMA_Start() to conditionally set RLDEN */ - break; - } - } - } - - MXC_FreeLock(&dma_lock); - - return channel; -} - -int MXC_DMA_RevB_ReleaseChannel(int ch) -{ - if (CHECK_HANDLE(ch)) { - if (MXC_GetLock(&dma_lock, 1) != E_NO_ERROR) { - return E_BUSY; - } - - dma_resource[ch].valid = 0; - dma_resource[ch].regs->ctrl = 0; - dma_resource[ch].regs->status = dma_resource[ch].regs->status; - MXC_FreeLock(&dma_lock); - } else { - return E_BAD_PARAM; - } - - return E_NO_ERROR; -} - -int MXC_DMA_RevB_ConfigChannel(mxc_dma_config_t config, mxc_dma_srcdst_t srcdst) -{ - if (CHECK_HANDLE(config.ch)) { - /* Designed to be safe, not speedy. Should not be called often */ - dma_resource[config.ch].regs->ctrl = - ((config.srcinc_en ? MXC_F_DMA_CTRL_SRCINC : 0) | - (config.dstinc_en ? MXC_F_DMA_CTRL_DSTINC : 0) | config.reqsel | - (config.srcwd << MXC_F_DMA_CTRL_SRCWD_POS) | - (config.dstwd << MXC_F_DMA_CTRL_DSTWD_POS)); - } else { - return E_BAD_PARAM; - } - - return MXC_DMA_RevB_SetSrcDst(srcdst); -} - -//TODO(ADI): Necessary? -int MXC_DMA_RevB_AdvConfigChannel(mxc_dma_adv_config_t advConfig) -{ - if (CHECK_HANDLE(advConfig.ch) && (advConfig.burst_size > 0)) { - dma_resource[advConfig.ch].regs->ctrl &= ~(0x1F00FC0C); // Clear all fields we set here - /* Designed to be safe, not speedy. Should not be called often */ - dma_resource[advConfig.ch].regs->ctrl |= - ((advConfig.reqwait_en ? MXC_F_DMA_CTRL_TO_WAIT : 0) | advConfig.prio | - advConfig.tosel | advConfig.pssel | - (((advConfig.burst_size - 1) << MXC_F_DMA_CTRL_BURST_SIZE_POS) & - MXC_F_DMA_CTRL_BURST_SIZE)); - } else { - return E_BAD_PARAM; - } - - return E_NO_ERROR; -} - -int MXC_DMA_RevB_SetSrcDst(mxc_dma_srcdst_t srcdst) -{ - if (CHECK_HANDLE(srcdst.ch)) { - dma_resource[srcdst.ch].regs->src = (unsigned int)srcdst.source; - dma_resource[srcdst.ch].regs->dst = (unsigned int)srcdst.dest; - dma_resource[srcdst.ch].regs->cnt = srcdst.len; - } else { - return E_BAD_PARAM; - } - - return E_NO_ERROR; -} - -//TODO(ADI): Necessary? -int MXC_DMA_RevB_GetSrcDst(mxc_dma_srcdst_t *srcdst) -{ - if (CHECK_HANDLE(srcdst.ch)) { - srcdst->source = (void *)dma_resource[srcdst->ch].regs->src; - srcdst->dest = (void *)dma_resource[srcdst->ch].regs->dst; - srcdst->len = (dma_resource[srcdst->ch].regs->cnt) & ~MXC_F_DMA_CNTRLD_EN; - } else { - return E_BAD_PARAM; - } - - return E_NO_ERROR; -} - -int MXC_DMA_RevB_SetSrcReload(mxc_dma_srcdst_t srcdst) -{ - if (CHECK_HANDLE(srcdst.ch)) { - dma_resource[srcdst.ch].regs->srcrld = (unsigned int)srcdst.source; - dma_resource[srcdst.ch].regs->dstrld = (unsigned int)srcdst.dest; - - if (dma_resource[srcdst.ch].regs->ctrl & MXC_F_DMA_CTRL_EN) { - /* If channel is already running, set RLDEN to enable next reload */ - dma_resource[srcdst.ch].regs->cntrld = MXC_F_DMA_CNTRLD_EN | srcdst.len; - } else { - /* Otherwise, this is the initial setup, so DMA_Start() will handle setting that bit */ - dma_resource[srcdst.ch].regs->cntrld = srcdst.len; - } - } else { - return E_BAD_PARAM; - } - - return E_NO_ERROR; -} - -//TODO(ADI): Necessary? -int MXC_DMA_RevB_GetSrcReload(mxc_dma_srcdst_t *srcdst) -{ - if (CHECK_HANDLE(srcdst.ch)) { - srcdst->source = (void *)dma_resource[srcdst->ch].regs->srcrld; - srcdst->dest = (void *)dma_resource[srcdst->ch].regs->dstrld; - srcdst->len = (dma_resource[srcdst->ch].regs->cntrld) & ~MXC_F_DMA_CNTRLD_EN; - } else { - return E_BAD_PARAM; - } - - return E_NO_ERROR; -} - -int MXC_DMA_RevB_SetCallback(int ch, void (*callback)(int, int)) -{ - if (CHECK_HANDLE(ch)) { - /* Callback for interrupt handler, no checking is done, as NULL is valid for (none) */ - dma_resource[ch].cb = callback; - } else { - return E_BAD_PARAM; - } - - return E_NO_ERROR; -} - -//TODO(ADI): Necessary? -int MXC_DMA_RevB_SetChannelInterruptEn(int ch, int chdis, int ctz) -{ - return E_NOT_SUPPORTED; -} - -//TODO(ADI): Necessary? -int MXC_DMA_RevB_GetChannelInterruptEn(int ch) -{ - return E_NOT_SUPPORTED; -} - -//TODO(ADI): Necessary? -int MXC_DMA_RevB_ChannelEnableInt(int ch, int flags) -{ - if (CHECK_HANDLE(ch)) { - dma_resource[ch].regs->ctrl |= (flags & (MXC_F_DMA_CTRL_DIS_IE | MXC_F_DMA_CTRL_CTZ_IE)); - } else { - return E_BAD_PARAM; - } - - return E_NO_ERROR; -} - -//TODO(ADI): Necessary? -int MXC_DMA_RevB_ChannelDisableInt(int ch, int flags) -{ - if (CHECK_HANDLE(ch)) { - dma_resource[ch].regs->ctrl &= ~(flags & (MXC_F_DMA_CTRL_DIS_IE | MXC_F_DMA_CTRL_CTZ_IE)); - } else { - return E_BAD_PARAM; - } - - return E_NO_ERROR; -} - -int MXC_DMA_RevB_EnableInt(int ch) -{ - if (CHECK_HANDLE(ch)) { - MXC_DMA->inten |= (1 << ch); - } else { - return E_BAD_PARAM; - } - - return E_NO_ERROR; -} - -int MXC_DMA_RevB_DisableInt(int ch) -{ - if (CHECK_HANDLE(ch)) { - MXC_DMA->inten &= ~(1 << ch); - } else { - return E_BAD_PARAM; - } - - return E_NO_ERROR; -} - -//TODO(ADI): Necessary? -int MXC_DMA_RevB_ChannelGetFlags(int ch) -{ - if (CHECK_HANDLE(ch)) { - return dma_resource[ch].regs->status; - } else { - return E_BAD_PARAM; - } - - return E_NO_ERROR; -} - -//TODO(ADI): Necessary? -int MXC_DMA_RevB_ChannelClearFlags(int ch, int flags) -{ - if (CHECK_HANDLE(ch)) { - dma_resource[ch].regs->status |= (flags & 0x5F); // Mask for Interrupt flags - } else { - return E_BAD_PARAM; - } - - return E_NO_ERROR; -} - -int MXC_DMA_RevB_Start(int ch) -{ - if (CHECK_HANDLE(ch)) { - MXC_DMA_ChannelClearFlags(ch, MXC_DMA_RevB_ChannelGetFlags(ch)); - - if (dma_resource[ch].regs->cntrld) { - dma_resource[ch].regs->ctrl |= (MXC_F_DMA_CTRL_EN | MXC_F_DMA_CTRL_RLDEN); - } else { - dma_resource[ch].regs->ctrl |= MXC_F_DMA_CTRL_EN; - } - } else { - return E_BAD_PARAM; - } - - return E_NO_ERROR; -} - -int MXC_DMA_RevB_Stop(int ch) -{ - if (CHECK_HANDLE(ch)) { - dma_resource[ch].regs->ctrl &= ~MXC_F_DMA_CTRL_EN; - } else { - return E_BAD_PARAM; - } - - return E_NO_ERROR; -} - -mxc_dma_ch_regs_t *MXC_DMA_RevB_GetCHRegs(int ch) -{ - if (CHECK_HANDLE(ch)) { - return dma_resource[ch].regs; - } else { - return NULL; - } -} - -void MXC_DMA_RevB_Handler() -{ - /* Do callback, if enabled */ - for (int i = 0; i < MXC_DMA_CHANNELS; i++) { - if (CHECK_HANDLE(i)) { - if (MXC_DMA->intfl & (0x1 << i)) { - if (dma_resource[i].cb != NULL) { - dma_resource[i].cb(i, E_NO_ERROR); - } - - MXC_DMA_ChannelClearFlags(i, MXC_DMA_RevB_ChannelGetFlags(i)); - break; - } - } - } -} - -void memcpy_callback(int ch, int error) -{ - mxc_dma_complete_cb_t callback; - callback = (mxc_dma_complete_cb_t)memcpy_resource[ch].userCallback; - - if (error != E_NO_ERROR) { - callback(NULL); - } - - callback(memcpy_resource[ch].dest); - - callback = NULL; - MXC_DMA_ReleaseChannel(ch); -} - -//TODO(ADI): Necessary? -int MXC_DMA_RevB_MemCpy(void *dest, void *src, int len, mxc_dma_complete_cb_t callback) -{ - int retval; - mxc_dma_config_t config; - mxc_dma_srcdst_t transfer; - int channel = MXC_DMA_AcquireChannel(); - - if (memcpy_resource[channel].userCallback != NULL) { - // We acquired a channel we haven't cleared yet - MXC_DMA_ReleaseChannel(channel); - return E_UNKNOWN; - } - - transfer.ch = channel; - transfer.source = src; - transfer.dest = dest; - transfer.len = len; - - config.ch = channel; - config.reqsel = MXC_DMA_REQUEST_MEMTOMEM; - config.srcwd = MXC_DMA_WIDTH_WORD; - config.dstwd = MXC_DMA_WIDTH_WORD; - config.srcinc_en = 1; - config.dstinc_en = 1; - - retval = MXC_DMA_ConfigChannel(config, transfer); - - if (retval != E_NO_ERROR) { - return retval; - } - - retval = MXC_DMA_EnableInt(channel); - - if (retval != E_NO_ERROR) { - return retval; - } - - retval = MXC_DMA_ChannelEnableInt(channel, MXC_F_DMA_CTRL_CTZ_IE); - - if (retval != E_NO_ERROR) { - return retval; - } - - MXC_DMA_SetCallback(channel, memcpy_callback); - - memcpy_resource[channel].userCallback = (void *)callback; - memcpy_resource[channel].dest = dest; - - return MXC_DMA_Start(channel); -} - -//TODO(ADI): Necessary? -void transfer_callback(int ch, int error) -{ - // Unimplemented - // Check for reason - // Call user callback for next transfer - // determine whether to load into the transfer slot or reload slot - // continue on or stop - while (1) {} -} - -//TODO(ADI): Necessary? -int MXC_DMA_RevB_DoTransfer(mxc_dma_config_t config, mxc_dma_srcdst_t firstSrcDst, - mxc_dma_trans_chain_t callback) -{ - int retval; - int channel = MXC_DMA_AcquireChannel(); - - if (memcpy_resource[channel].userCallback != NULL) { - // We acquired a channel we haven't cleared yet - MXC_DMA_ReleaseChannel(channel); - return E_UNKNOWN; - } - - retval = MXC_DMA_ConfigChannel(config, firstSrcDst); - - if (retval != E_NO_ERROR) { - return retval; - } - - retval = MXC_DMA_EnableInt(channel); - - if (retval != E_NO_ERROR) { - return retval; - } - - retval = MXC_DMA_ChannelEnableInt(channel, MXC_F_DMA_CTRL_CTZ_IE); - - if (retval != E_NO_ERROR) { - return retval; - } - - MXC_DMA_SetCallback(channel, transfer_callback); - - memcpy_resource[channel].userCallback = (void *)callback; - - return MXC_DMA_Start(channel); -} diff --git a/Libraries/PeriphDrivers/Source/DMA/dma_revb.h b/Libraries/PeriphDrivers/Source/DMA/dma_revb.h deleted file mode 100644 index dd81bc123ce..00000000000 --- a/Libraries/PeriphDrivers/Source/DMA/dma_revb.h +++ /dev/null @@ -1,55 +0,0 @@ -/****************************************************************************** - * - * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by - * Analog Devices, Inc.), - * Copyright (C) 2023-2024 Analog Devices, Inc. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ******************************************************************************/ - -#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_DMA_DMA_REVB_H_ -#define LIBRARIES_PERIPHDRIVERS_SOURCE_DMA_DMA_REVB_H_ - -/****** Includes *******/ - -/***** Definitions *****/ - -/******* Globals *******/ - -/****** Functions ******/ -int MXC_DMA_RevB_Init(void); -int MXC_DMA_RevB_AcquireChannel(void); -int MXC_DMA_RevB_ReleaseChannel(int ch); -int MXC_DMA_RevB_ConfigChannel(mxc_dma_config_t config, mxc_dma_srcdst_t srcdst); -int MXC_DMA_RevB_AdvConfigChannel(mxc_dma_adv_config_t advConfig); -int MXC_DMA_RevB_SetSrcDst(mxc_dma_srcdst_t srcdst); -int MXC_DMA_RevB_GetSrcDst(mxc_dma_srcdst_t *srcdst); -int MXC_DMA_RevB_SetSrcReload(mxc_dma_srcdst_t srcdst); -int MXC_DMA_RevB_GetSrcReload(mxc_dma_srcdst_t *srcdst); -int MXC_DMA_RevB_SetCallback(int ch, void (*callback)(int, int)); -int MXC_DMA_RevB_ChannelEnableInt(int ch, int flags); -int MXC_DMA_RevB_ChannelDisableInt(int ch, int flags); -int MXC_DMA_RevB_ChannelGetFlags(int ch); -int MXC_DMA_RevB_ChannelClearFlags(int ch, int flags); -int MXC_DMA_RevB_EnableInt(int ch); -int MXC_DMA_RevB_DisableInt(int ch); -int MXC_DMA_RevB_Start(int ch); -int MXC_DMA_RevB_Stop(int ch); -mxc_dma_ch_regs_t *MXC_DMA_RevB_GetCHRegs(int ch); -void MXC_DMA_RevB_Handler(); -int MXC_DMA_RevB_MemCpy(void *dest, void *src, int len, mxc_dma_complete_cb_t callback); -int MXC_DMA_RevB_DoTransfer(mxc_dma_config_t config, mxc_dma_srcdst_t firstSrcDst, - mxc_dma_trans_chain_t callback); - -#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_DMA_DMA_REVB_H_ diff --git a/Libraries/PeriphDrivers/Source/SYS/nvic_table.c b/Libraries/PeriphDrivers/Source/SYS/nvic_table.c index 783f8ce7fc4..2b2a792f6ae 100644 --- a/Libraries/PeriphDrivers/Source/SYS/nvic_table.c +++ b/Libraries/PeriphDrivers/Source/SYS/nvic_table.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by * Analog Devices, Inc.), * Copyright (C) 2023-2024 Analog Devices, Inc. * @@ -35,15 +35,15 @@ __attribute__((aligned(512))) #endif static void (*ramVectorTable[MXC_IRQ_COUNT])(void); -void NVIC_SetRAM(void) -{ #if defined(__ICCARM__) - extern void (*const __isr_vector[])(void); +extern void (*const __isr_vector[])(void); #else - /* should be defined in starup_.S */ - extern uint32_t __isr_vector[MXC_IRQ_COUNT]; +/* should be defined in starup_.S */ +extern uint32_t __isr_vector[MXC_IRQ_COUNT]; #endif +void NVIC_SetRAM(void) +{ memcpy(&ramVectorTable, &__isr_vector, sizeof(ramVectorTable)); SCB->VTOR = (uint32_t)&ramVectorTable; } From d036f16d02086a23baa9ccb5903f0c7fd445f7e1 Mon Sep 17 00:00:00 2001 From: Sadik Ozer <46590392+ozersa@users.noreply.github.com> Date: Thu, 24 Oct 2024 22:09:39 +0300 Subject: [PATCH 13/37] fix(PeriphDrivers): Fix Zephyr build issue with GPIO pad definitions (#1234) Signed-off-by: Sadik Ozer --- Libraries/PeriphDrivers/Include/MAX32657/gpio.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Libraries/PeriphDrivers/Include/MAX32657/gpio.h b/Libraries/PeriphDrivers/Include/MAX32657/gpio.h index cf1a7ad6c8e..2c076b28caa 100644 --- a/Libraries/PeriphDrivers/Include/MAX32657/gpio.h +++ b/Libraries/PeriphDrivers/Include/MAX32657/gpio.h @@ -152,7 +152,9 @@ typedef enum { typedef enum { MXC_GPIO_PAD_NONE, /**< No pull-up or pull-down */ MXC_GPIO_PAD_WEAK_PULL_UP, /**< Set pad to weak pull-up */ - MXC_GPIO_PAD_WEAK_PULL_DOWN /**< Set pad to weak pull-down */ + MXC_GPIO_PAD_WEAK_PULL_DOWN, /**< Set pad to weak pull-down */ + MXC_GPIO_PAD_PULL_UP = MXC_GPIO_PAD_WEAK_PULL_UP, /**< Set pad to default (weak) pull-up */ + MXC_GPIO_PAD_PULL_DOWN = MXC_GPIO_PAD_WEAK_PULL_DOWN /**< Set pad to default (weak) pull-down */ } mxc_gpio_pad_t; /** From c75f2f7143b66b90dd6e699de4989b4437c893ae Mon Sep 17 00:00:00 2001 From: Brent K <129296493+BrentK-ADI@users.noreply.github.com> Date: Thu, 24 Oct 2024 15:10:10 -0400 Subject: [PATCH 14/37] fix(Other): Fix MAX32670 Timer Width for Zephyr build (#1232) Signed-off-by: Brent Kowal --- Libraries/zephyr/MAX/Include/wrap_max32_tmr.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Libraries/zephyr/MAX/Include/wrap_max32_tmr.h b/Libraries/zephyr/MAX/Include/wrap_max32_tmr.h index f3706dae731..310e90edfac 100644 --- a/Libraries/zephyr/MAX/Include/wrap_max32_tmr.h +++ b/Libraries/zephyr/MAX/Include/wrap_max32_tmr.h @@ -105,7 +105,8 @@ int Wrap_MXC_TMR_GetPendingInt(mxc_tmr_regs_t *tmr) (CONFIG_SOC_MAX32672) || (CONFIG_SOC_MAX32662) || (CONFIG_SOC_MAX32675) || \ (CONFIG_SOC_MAX32680) || (CONFIG_SOC_MAX32657) || (CONFIG_SOC_MAX78002) -#if defined(CONFIG_SOC_MAX32672) || (CONFIG_SOC_MAX32675) || (CONFIG_SOC_MAX32657) +#if defined(CONFIG_SOC_MAX32672) || (CONFIG_SOC_MAX32675) || (CONFIG_SOC_MAX32657) || \ + (CONFIG_SOC_MAX32670) /* All timers are 32bits */ #define WRAP_MXC_IS_32B_TIMER(idx) (1) #elif defined(CONFIG_SOC_MAX32662) From b329db03bf6dde1c203a9835e4f104b46b31120a Mon Sep 17 00:00:00 2001 From: EricB-ADI <122300463+EricB-ADI@users.noreply.github.com> Date: Fri, 25 Oct 2024 11:37:15 -0500 Subject: [PATCH 15/37] chore(Build): Grouped Common Source Files in libPeriphDriver.mk (#1238) Co-authored-by: EricB-ADI --- Libraries/CMSIS/Device/Maxim/GCC/mxc_version.mk | 6 +++--- Libraries/PeriphDrivers/Source/SYS/mxc_lock.c | 14 ++++++++++++-- Libraries/PeriphDrivers/libPeriphDriver.mk | 5 +++++ Libraries/PeriphDrivers/max32520_files.mk | 6 ------ Libraries/PeriphDrivers/max32570_files.mk | 5 ----- Libraries/PeriphDrivers/max32572_files.mk | 6 ------ Libraries/PeriphDrivers/max32650_files.mk | 6 ------ Libraries/PeriphDrivers/max32655_files.mk | 5 ----- Libraries/PeriphDrivers/max32657_files.mk | 5 ----- Libraries/PeriphDrivers/max32660_files.mk | 6 ------ Libraries/PeriphDrivers/max32662_files.mk | 6 ------ Libraries/PeriphDrivers/max32665_files.mk | 6 ------ Libraries/PeriphDrivers/max32670_files.mk | 6 ------ Libraries/PeriphDrivers/max32672_files.mk | 6 ------ Libraries/PeriphDrivers/max32675_files.mk | 6 ------ Libraries/PeriphDrivers/max32680_files.mk | 6 ------ Libraries/PeriphDrivers/max32690_files.mk | 6 ------ Libraries/PeriphDrivers/max78000_files.mk | 4 ---- Libraries/PeriphDrivers/max78002_files.mk | 15 +++------------ 19 files changed, 23 insertions(+), 102 deletions(-) diff --git a/Libraries/CMSIS/Device/Maxim/GCC/mxc_version.mk b/Libraries/CMSIS/Device/Maxim/GCC/mxc_version.mk index a517a803062..cde4ab47d13 100644 --- a/Libraries/CMSIS/Device/Maxim/GCC/mxc_version.mk +++ b/Libraries/CMSIS/Device/Maxim/GCC/mxc_version.mk @@ -16,9 +16,9 @@ # ############################################################################## # Autogenerated version info for build system. -MSDK_VERSION_STRING := v2024_02-149-gb9966ca6d8 -MSDK_VERSION_YEAR := 2024 -MSDK_VERSION_MONTH := 2 +MSDK_VERSION_STRING := v2023_10-307-gf557dbf1716 +MSDK_VERSION_YEAR := 2023 +MSDK_VERSION_MONTH := 10 # Add root MAXIM_PATH to IPATH so compiler can locate msdk_version.h IPATH += $(MAXIM_PATH) diff --git a/Libraries/PeriphDrivers/Source/SYS/mxc_lock.c b/Libraries/PeriphDrivers/Source/SYS/mxc_lock.c index 1c1034c6df2..b2afc9404a0 100644 --- a/Libraries/PeriphDrivers/Source/SYS/mxc_lock.c +++ b/Libraries/PeriphDrivers/Source/SYS/mxc_lock.c @@ -52,13 +52,23 @@ void MXC_FreeLock(uint32_t *lock) /* ************************************************************************** */ int MXC_GetLock(uint32_t *lock, uint32_t value) { -#warning "Unimplemented for RISCV" + __disable_irq(); + if (*lock) { + __enable_irq(); + return E_BUSY; + } + + *lock = value; + + __asm volatile("fence rw, rw"); + __enable_irq(); return E_NO_ERROR; } /* ************************************************************************** */ void MXC_FreeLock(uint32_t *lock) { -#warning "Unimplemented for RISCV" + __asm volatile("fence" ::: "memory"); + *lock = 0; } #endif diff --git a/Libraries/PeriphDrivers/libPeriphDriver.mk b/Libraries/PeriphDrivers/libPeriphDriver.mk index 4ebba45947e..4bed4f12325 100644 --- a/Libraries/PeriphDrivers/libPeriphDriver.mk +++ b/Libraries/PeriphDrivers/libPeriphDriver.mk @@ -61,6 +61,11 @@ endif include ${CMSIS_ROOT}/../PeriphDrivers/$(TARGET_LC)_files.mk +PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/mxc_assert.c +PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/mxc_delay.c +PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/nvic_table.c +PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/mxc_lock.c + # # Where to find header files for this project IPATH += $(PERIPH_DRIVER_INCLUDE_DIR) SRCS += $(PERIPH_DRIVER_C_FILES) diff --git a/Libraries/PeriphDrivers/max32520_files.mk b/Libraries/PeriphDrivers/max32520_files.mk index bb47b9673f9..d4cb52ceb63 100644 --- a/Libraries/PeriphDrivers/max32520_files.mk +++ b/Libraries/PeriphDrivers/max32520_files.mk @@ -49,10 +49,6 @@ PERIPH_DRIVER_INCLUDE_DIR += $(INCLUDE_DIR)/$(TARGET_UC)/ PINS_FILE ?= $(SOURCE_DIR)/SYS/pins_es17.c # Source files -PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/mxc_assert.c -PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/mxc_delay.c -PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/mxc_lock.c -PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/nvic_table.c PERIPH_DRIVER_C_FILES += $(PINS_FILE) PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/sys_es17.c @@ -113,5 +109,3 @@ PERIPH_DRIVER_INCLUDE_DIR += $(SOURCE_DIR)/WDT PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/WDT/wdt_common.c PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/WDT/wdt_es17.c PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/WDT/wdt_reva.c - - diff --git a/Libraries/PeriphDrivers/max32570_files.mk b/Libraries/PeriphDrivers/max32570_files.mk index 54859c12f26..928ec9dc2cd 100644 --- a/Libraries/PeriphDrivers/max32570_files.mk +++ b/Libraries/PeriphDrivers/max32570_files.mk @@ -52,9 +52,6 @@ PERIPH_DRIVER_INCLUDE_DIR += $(INCLUDE_DIR)/$(TARGET_UC)/ PINS_FILE ?= $(SOURCE_DIR)/SYS/pins_me13.c # Source files) -PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/mxc_assert.c -PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/mxc_delay.c -PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/mxc_lock.c PERIPH_DRIVER_C_FILES += $(PINS_FILE) PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/sys_me13.c PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/nvic_table.c @@ -169,5 +166,3 @@ PERIPH_DRIVER_INCLUDE_DIR += $(SOURCE_DIR)/WDT PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/WDT/wdt_common.c PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/WDT/wdt_me13.c PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/WDT/wdt_reva.c - - diff --git a/Libraries/PeriphDrivers/max32572_files.mk b/Libraries/PeriphDrivers/max32572_files.mk index 904c28b5531..6a3f462e496 100644 --- a/Libraries/PeriphDrivers/max32572_files.mk +++ b/Libraries/PeriphDrivers/max32572_files.mk @@ -49,10 +49,6 @@ PERIPH_DRIVER_INCLUDE_DIR += $(INCLUDE_DIR)/$(TARGET_UC)/ PINS_FILE ?= $(SOURCE_DIR)/SYS/pins_me55.c # Source files -PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/mxc_assert.c -PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/mxc_delay.c -PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/mxc_lock.c -PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/nvic_table.c PERIPH_DRIVER_C_FILES += $(PINS_FILE) PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/sys_me55.c @@ -131,5 +127,3 @@ PERIPH_DRIVER_INCLUDE_DIR += $(SOURCE_DIR)/WDT PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/WDT/wdt_common.c PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/WDT/wdt_me55.c PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/WDT/wdt_revb.c - - diff --git a/Libraries/PeriphDrivers/max32650_files.mk b/Libraries/PeriphDrivers/max32650_files.mk index c3281efbf4d..93eb9ebdf89 100644 --- a/Libraries/PeriphDrivers/max32650_files.mk +++ b/Libraries/PeriphDrivers/max32650_files.mk @@ -50,10 +50,6 @@ PERIPH_DRIVER_INCLUDE_DIR += $(INCLUDE_DIR)/$(TARGET_UC)/ PINS_FILE ?= $(SOURCE_DIR)/SYS/pins_me10.c # Source files -PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/mxc_assert.c -PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/mxc_delay.c -PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/mxc_lock.c -PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/nvic_table.c PERIPH_DRIVER_C_FILES += $(PINS_FILE) PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/sys_me10.c @@ -160,5 +156,3 @@ PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/UART/uart_common.c PERIPH_DRIVER_INCLUDE_DIR += $(SOURCE_DIR)/WDT PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/WDT/wdt_me10.c PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/WDT/wdt_reva.c - - diff --git a/Libraries/PeriphDrivers/max32655_files.mk b/Libraries/PeriphDrivers/max32655_files.mk index b3f2e9ef953..19707aa9b77 100644 --- a/Libraries/PeriphDrivers/max32655_files.mk +++ b/Libraries/PeriphDrivers/max32655_files.mk @@ -49,10 +49,6 @@ PERIPH_DRIVER_INCLUDE_DIR += $(INCLUDE_DIR)/$(TARGET_UC)/ PINS_FILE ?= $(SOURCE_DIR)/SYS/pins_me17.c # Source files -PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/mxc_assert.c -PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/mxc_delay.c -PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/mxc_lock.c -PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/nvic_table.c PERIPH_DRIVER_C_FILES += $(PINS_FILE) PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/sys_me17.c @@ -147,4 +143,3 @@ PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/WDT/wdt_revb.c PERIPH_DRIVER_INCLUDE_DIR += $(SOURCE_DIR)/WUT PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/WUT/wut_me17.c PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/WUT/wut_reva.c - diff --git a/Libraries/PeriphDrivers/max32657_files.mk b/Libraries/PeriphDrivers/max32657_files.mk index c50d8cdb285..a0b88d43d59 100644 --- a/Libraries/PeriphDrivers/max32657_files.mk +++ b/Libraries/PeriphDrivers/max32657_files.mk @@ -47,10 +47,6 @@ PERIPH_DRIVER_INCLUDE_DIR += $(INCLUDE_DIR)/$(TARGET_UC)/ PINS_FILE ?= $(SOURCE_DIR)/SYS/sys_me30.c # Source files -PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/mxc_assert.c -PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/mxc_delay.c -PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/mxc_lock.c -PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/nvic_table.c PERIPH_DRIVER_C_FILES += $(PINS_FILE) PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/pins_me30.c @@ -127,4 +123,3 @@ PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/WDT/wdt_revb.c PERIPH_DRIVER_INCLUDE_DIR += $(SOURCE_DIR)/WUT PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/WUT/wut_me30.c PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/WUT/wut_reva.c - diff --git a/Libraries/PeriphDrivers/max32660_files.mk b/Libraries/PeriphDrivers/max32660_files.mk index 6c3f4f962d2..20a159fbfbe 100644 --- a/Libraries/PeriphDrivers/max32660_files.mk +++ b/Libraries/PeriphDrivers/max32660_files.mk @@ -49,10 +49,6 @@ PERIPH_DRIVER_INCLUDE_DIR += $(INCLUDE_DIR)/$(TARGET_UC)/ PINS_FILE ?= $(SOURCE_DIR)/SYS/pins_me11.c # Source files -PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/mxc_assert.c -PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/mxc_delay.c -PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/mxc_lock.c -PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/nvic_table.c PERIPH_DRIVER_C_FILES += $(PINS_FILE) PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/sys_me11.c @@ -111,5 +107,3 @@ PERIPH_DRIVER_INCLUDE_DIR += $(SOURCE_DIR)/WDT PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/WDT/wdt_common.c PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/WDT/wdt_me11.c PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/WDT/wdt_reva.c - - diff --git a/Libraries/PeriphDrivers/max32662_files.mk b/Libraries/PeriphDrivers/max32662_files.mk index 1e3b99be274..b9eacfa3d43 100644 --- a/Libraries/PeriphDrivers/max32662_files.mk +++ b/Libraries/PeriphDrivers/max32662_files.mk @@ -49,10 +49,6 @@ PERIPH_DRIVER_INCLUDE_DIR += $(INCLUDE_DIR)/$(TARGET_UC)/ PINS_FILE ?= $(SOURCE_DIR)/SYS/pins_me12.c # Source files -PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/mxc_assert.c -PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/mxc_delay.c -PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/mxc_lock.c -PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/nvic_table.c PERIPH_DRIVER_C_FILES += $(PINS_FILE) PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/sys_me12.c @@ -128,5 +124,3 @@ PERIPH_DRIVER_INCLUDE_DIR += $(SOURCE_DIR)/WDT PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/WDT/wdt_common.c PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/WDT/wdt_me12.c PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/WDT/wdt_revb.c - - diff --git a/Libraries/PeriphDrivers/max32665_files.mk b/Libraries/PeriphDrivers/max32665_files.mk index 69bdaef7463..8cc656a7c5b 100644 --- a/Libraries/PeriphDrivers/max32665_files.mk +++ b/Libraries/PeriphDrivers/max32665_files.mk @@ -49,10 +49,6 @@ PERIPH_DRIVER_INCLUDE_DIR += $(INCLUDE_DIR)/$(TARGET_UC)/ PINS_FILE ?= $(SOURCE_DIR)/SYS/pins_me14.c # Source files -PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/mxc_assert.c -PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/mxc_delay.c -PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/mxc_lock.c -PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/nvic_table.c PERIPH_DRIVER_C_FILES += $(PINS_FILE) PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/sys_me14.c @@ -160,5 +156,3 @@ PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/WDT/wdt_reva.c PERIPH_DRIVER_INCLUDE_DIR += $(SOURCE_DIR)/WUT PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/WUT/wut_me14.c PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/WUT/wut_reva.c - - diff --git a/Libraries/PeriphDrivers/max32670_files.mk b/Libraries/PeriphDrivers/max32670_files.mk index 8def0d29439..0b14bac3865 100644 --- a/Libraries/PeriphDrivers/max32670_files.mk +++ b/Libraries/PeriphDrivers/max32670_files.mk @@ -49,10 +49,6 @@ PERIPH_DRIVER_INCLUDE_DIR += $(INCLUDE_DIR)/$(TARGET_UC)/ PINS_FILE ?= $(SOURCE_DIR)/SYS/pins_me15.c # Source files -PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/mxc_assert.c -PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/mxc_delay.c -PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/mxc_lock.c -PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/nvic_table.c PERIPH_DRIVER_C_FILES += $(PINS_FILE) PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/sys_me15.c @@ -120,5 +116,3 @@ PERIPH_DRIVER_INCLUDE_DIR += $(SOURCE_DIR)/WDT PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/WDT/wdt_common.c PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/WDT/wdt_me15.c PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/WDT/wdt_revb.c - - diff --git a/Libraries/PeriphDrivers/max32672_files.mk b/Libraries/PeriphDrivers/max32672_files.mk index 8d26f621350..aa23bd5ed6b 100644 --- a/Libraries/PeriphDrivers/max32672_files.mk +++ b/Libraries/PeriphDrivers/max32672_files.mk @@ -49,10 +49,6 @@ PERIPH_DRIVER_INCLUDE_DIR += $(INCLUDE_DIR)/$(TARGET_UC)/ PINS_FILE ?= $(SOURCE_DIR)/SYS/pins_me21.c # Source files -PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/mxc_assert.c -PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/mxc_delay.c -PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/mxc_lock.c -PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/nvic_table.c PERIPH_DRIVER_C_FILES += $(PINS_FILE) PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/sys_me21.c @@ -129,5 +125,3 @@ PERIPH_DRIVER_INCLUDE_DIR += $(SOURCE_DIR)/WDT PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/WDT/wdt_common.c PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/WDT/wdt_me21.c PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/WDT/wdt_revb.c - - diff --git a/Libraries/PeriphDrivers/max32675_files.mk b/Libraries/PeriphDrivers/max32675_files.mk index 7c0b0bddc92..06d746fc7de 100644 --- a/Libraries/PeriphDrivers/max32675_files.mk +++ b/Libraries/PeriphDrivers/max32675_files.mk @@ -49,10 +49,6 @@ PERIPH_DRIVER_INCLUDE_DIR += $(INCLUDE_DIR)/$(TARGET_UC)/ PINS_FILE ?= $(SOURCE_DIR)/SYS/pins_me16.c # Source files -PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/mxc_assert.c -PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/mxc_delay.c -PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/mxc_lock.c -PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/nvic_table.c PERIPH_DRIVER_C_FILES += $(PINS_FILE) PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/sys_me15.c @@ -123,5 +119,3 @@ PERIPH_DRIVER_INCLUDE_DIR += $(SOURCE_DIR)/WDT PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/WDT/wdt_common.c PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/WDT/wdt_me15.c PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/WDT/wdt_revb.c - - diff --git a/Libraries/PeriphDrivers/max32680_files.mk b/Libraries/PeriphDrivers/max32680_files.mk index c3d3fa15ace..915b38bfd7d 100644 --- a/Libraries/PeriphDrivers/max32680_files.mk +++ b/Libraries/PeriphDrivers/max32680_files.mk @@ -49,10 +49,6 @@ PERIPH_DRIVER_INCLUDE_DIR += $(INCLUDE_DIR)/$(TARGET_UC)/ PINS_FILE ?= $(SOURCE_DIR)/SYS/pins_me20.c # Source files -PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/mxc_assert.c -PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/mxc_delay.c -PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/mxc_lock.c -PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/nvic_table.c PERIPH_DRIVER_C_FILES += $(PINS_FILE) PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/sys_me17.c @@ -152,5 +148,3 @@ PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/WDT/wdt_revb.c PERIPH_DRIVER_INCLUDE_DIR += $(SOURCE_DIR)/WUT PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/WUT/wut_me17.c PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/WUT/wut_reva.c - - diff --git a/Libraries/PeriphDrivers/max32690_files.mk b/Libraries/PeriphDrivers/max32690_files.mk index 8c10ea90ee8..a95e3c54286 100644 --- a/Libraries/PeriphDrivers/max32690_files.mk +++ b/Libraries/PeriphDrivers/max32690_files.mk @@ -49,10 +49,6 @@ PERIPH_DRIVER_INCLUDE_DIR += $(INCLUDE_DIR)/$(TARGET_UC)/ PINS_FILE ?= $(SOURCE_DIR)/SYS/pins_me18.c # Source files -PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/mxc_assert.c -PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/mxc_delay.c -PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/mxc_lock.c -PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/nvic_table.c PERIPH_DRIVER_C_FILES += $(PINS_FILE) PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/sys_me18.c @@ -175,5 +171,3 @@ PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/WDT/wdt_revb.c PERIPH_DRIVER_INCLUDE_DIR += $(SOURCE_DIR)/WUT PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/WUT/wut_me18.c PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/WUT/wut_reva.c - - diff --git a/Libraries/PeriphDrivers/max78000_files.mk b/Libraries/PeriphDrivers/max78000_files.mk index c1489dbf8d2..d8b781edb3c 100644 --- a/Libraries/PeriphDrivers/max78000_files.mk +++ b/Libraries/PeriphDrivers/max78000_files.mk @@ -49,10 +49,6 @@ PERIPH_DRIVER_INCLUDE_DIR += $(INCLUDE_DIR)/$(TARGET_UC)/ PINS_FILE ?= $(SOURCE_DIR)/SYS/pins_ai85.c # Source files -PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/mxc_assert.c -PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/mxc_delay.c -PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/mxc_lock.c -PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/nvic_table.c PERIPH_DRIVER_C_FILES += $(PINS_FILE) PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/sys_ai85.c diff --git a/Libraries/PeriphDrivers/max78002_files.mk b/Libraries/PeriphDrivers/max78002_files.mk index 8c0eca237b8..7add3b5bef2 100644 --- a/Libraries/PeriphDrivers/max78002_files.mk +++ b/Libraries/PeriphDrivers/max78002_files.mk @@ -49,16 +49,9 @@ PERIPH_DRIVER_INCLUDE_DIR += $(INCLUDE_DIR)/$(TARGET_UC)/ PINS_FILE ?= $(SOURCE_DIR)/SYS/pins_ai87.c # Source files -PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/mxc_assert.c -PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/mxc_delay.c -# TODO(JC): Implement mxc_lock for RISC-V. Skip for now. -ifneq "$(RISCV_CORE)" "1" -ifneq "$(RISCV_CORE)" "RV32" -# ^ NOTE(JC): Some legacy Makefiles use "RV32". We recommend using "1" in the UG -PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/mxc_lock.c -endif -endif -PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/nvic_table.c + + + PERIPH_DRIVER_C_FILES += $(PINS_FILE) PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/sys_ai87.c @@ -180,5 +173,3 @@ PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/WDT/wdt_revb.c PERIPH_DRIVER_INCLUDE_DIR += $(SOURCE_DIR)/WUT PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/WUT/wut_ai87.c PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/WUT/wut_reva.c - - From 1ee96f58a0d9635530b01686c5e2a3691232b6cd Mon Sep 17 00:00:00 2001 From: EricB-ADI <122300463+EricB-ADI@users.noreply.github.com> Date: Fri, 25 Oct 2024 11:37:32 -0500 Subject: [PATCH 16/37] feat(CMSIS): Added NVIC_GetEnableIRQ for RV32 (#1240) --- .../CMSIS/5.9.0/Core/Include/core_rv32.h | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/Libraries/CMSIS/5.9.0/Core/Include/core_rv32.h b/Libraries/CMSIS/5.9.0/Core/Include/core_rv32.h index f05f9506884..7d880bb5022 100644 --- a/Libraries/CMSIS/5.9.0/Core/Include/core_rv32.h +++ b/Libraries/CMSIS/5.9.0/Core/Include/core_rv32.h @@ -394,7 +394,31 @@ __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) MXC_EVENT->event1_enable &= ~(1 << (IRQn - 32)); } } +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if((int32_t)(IRQn) < 0) + { + return 0u; + } + + const uint32_t irq_mask = (1 << IRQn); + if(IRQn < 32) + { + return (MXC_INTR->irq0_enable & irq_mask) && (MXC_EVENT->event0_enable && irq_mask) ? 1 : 0; + + } + + return (MXC_INTR->irq1_enable & irq_mask) && (MXC_EVENT->event1_enable && irq_mask) ? 1 : 0; +} __STATIC_INLINE void NVIC_EnableEVENT(IRQn_Type EVENT) { if (EVENT < 32) From 0f2ade3810f96f10bb659a07f1d31a258b6a9504 Mon Sep 17 00:00:00 2001 From: Brent K <129296493+BrentK-ADI@users.noreply.github.com> Date: Fri, 25 Oct 2024 15:32:32 -0400 Subject: [PATCH 17/37] feat(Examples): Add MAX32690 TinyUSB MSC + External Flash Example (#1230) --- .../USB/TinyUSB/msc_ext_flash/.cproject | 86 ++++ .../USB/TinyUSB/msc_ext_flash/.project | 26 ++ .../.settings/language.settings.xml | 15 + .../org.eclipse.cdt.codan.core.prefs | 93 +++++ .../.settings/org.eclipse.cdt.core.prefs | 15 + .../TinyUSB/msc_ext_flash/.vscode/README.md | 47 +++ .../.vscode/c_cpp_properties.json | 53 +++ .../TinyUSB/msc_ext_flash/.vscode/flash.gdb | 17 + .../TinyUSB/msc_ext_flash/.vscode/launch.json | 133 ++++++ .../msc_ext_flash/.vscode/settings.json | 89 ++++ .../TinyUSB/msc_ext_flash/.vscode/tasks.json | 115 ++++++ .../USB/TinyUSB/msc_ext_flash/Makefile | 382 ++++++++++++++++++ .../USB/TinyUSB/msc_ext_flash/README.md | 39 ++ .../MAX32690/USB/TinyUSB/msc_ext_flash/main.c | 175 ++++++++ .../USB/TinyUSB/msc_ext_flash/msc_ext_flash.c | 283 +++++++++++++ .../msc_ext_flash/msc_ext_flash.launch | 62 +++ .../USB/TinyUSB/msc_ext_flash/project.mk | 22 + .../USB/TinyUSB/msc_ext_flash/tusb_config.h | 107 +++++ .../TinyUSB/msc_ext_flash/usb_descriptors.c | 206 ++++++++++ .../Boards/MAX32690/APARD/Source/board.c | 9 +- .../PeriphDrivers/Source/SPIXF/spixf_me18.c | 3 +- 21 files changed, 1975 insertions(+), 2 deletions(-) create mode 100644 Examples/MAX32690/USB/TinyUSB/msc_ext_flash/.cproject create mode 100644 Examples/MAX32690/USB/TinyUSB/msc_ext_flash/.project create mode 100644 Examples/MAX32690/USB/TinyUSB/msc_ext_flash/.settings/language.settings.xml create mode 100644 Examples/MAX32690/USB/TinyUSB/msc_ext_flash/.settings/org.eclipse.cdt.codan.core.prefs create mode 100644 Examples/MAX32690/USB/TinyUSB/msc_ext_flash/.settings/org.eclipse.cdt.core.prefs create mode 100644 Examples/MAX32690/USB/TinyUSB/msc_ext_flash/.vscode/README.md create mode 100644 Examples/MAX32690/USB/TinyUSB/msc_ext_flash/.vscode/c_cpp_properties.json create mode 100644 Examples/MAX32690/USB/TinyUSB/msc_ext_flash/.vscode/flash.gdb create mode 100644 Examples/MAX32690/USB/TinyUSB/msc_ext_flash/.vscode/launch.json create mode 100644 Examples/MAX32690/USB/TinyUSB/msc_ext_flash/.vscode/settings.json create mode 100644 Examples/MAX32690/USB/TinyUSB/msc_ext_flash/.vscode/tasks.json create mode 100644 Examples/MAX32690/USB/TinyUSB/msc_ext_flash/Makefile create mode 100644 Examples/MAX32690/USB/TinyUSB/msc_ext_flash/README.md create mode 100644 Examples/MAX32690/USB/TinyUSB/msc_ext_flash/main.c create mode 100644 Examples/MAX32690/USB/TinyUSB/msc_ext_flash/msc_ext_flash.c create mode 100644 Examples/MAX32690/USB/TinyUSB/msc_ext_flash/msc_ext_flash.launch create mode 100644 Examples/MAX32690/USB/TinyUSB/msc_ext_flash/project.mk create mode 100644 Examples/MAX32690/USB/TinyUSB/msc_ext_flash/tusb_config.h create mode 100644 Examples/MAX32690/USB/TinyUSB/msc_ext_flash/usb_descriptors.c diff --git a/Examples/MAX32690/USB/TinyUSB/msc_ext_flash/.cproject b/Examples/MAX32690/USB/TinyUSB/msc_ext_flash/.cproject new file mode 100644 index 00000000000..d3ed5521b15 --- /dev/null +++ b/Examples/MAX32690/USB/TinyUSB/msc_ext_flash/.cproject @@ -0,0 +1,86 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Examples/MAX32690/USB/TinyUSB/msc_ext_flash/.project b/Examples/MAX32690/USB/TinyUSB/msc_ext_flash/.project new file mode 100644 index 00000000000..bc695b2bb1d --- /dev/null +++ b/Examples/MAX32690/USB/TinyUSB/msc_ext_flash/.project @@ -0,0 +1,26 @@ + + + msc_ext_flash + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + diff --git a/Examples/MAX32690/USB/TinyUSB/msc_ext_flash/.settings/language.settings.xml b/Examples/MAX32690/USB/TinyUSB/msc_ext_flash/.settings/language.settings.xml new file mode 100644 index 00000000000..d32717b6f37 --- /dev/null +++ b/Examples/MAX32690/USB/TinyUSB/msc_ext_flash/.settings/language.settings.xml @@ -0,0 +1,15 @@ + + + + + + + + + + + + + + + diff --git a/Examples/MAX32690/USB/TinyUSB/msc_ext_flash/.settings/org.eclipse.cdt.codan.core.prefs b/Examples/MAX32690/USB/TinyUSB/msc_ext_flash/.settings/org.eclipse.cdt.codan.core.prefs new file mode 100644 index 00000000000..59c0b37ba75 --- /dev/null +++ b/Examples/MAX32690/USB/TinyUSB/msc_ext_flash/.settings/org.eclipse.cdt.codan.core.prefs @@ -0,0 +1,93 @@ +eclipse.preferences.version=1 +org.eclipse.cdt.codan.checkers.errnoreturn=Warning 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+org.eclipse.cdt.codan.checkers.nolinecomment.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Line comments\\")"} +org.eclipse.cdt.codan.checkers.noreturn=Error +org.eclipse.cdt.codan.checkers.noreturn.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"No return value\\")",implicit\=>false} +org.eclipse.cdt.codan.internal.checkers.AbstractClassCreation=Error +org.eclipse.cdt.codan.internal.checkers.AbstractClassCreation.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Abstract class cannot be instantiated\\")"} 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redefinition\\")"} +org.eclipse.cdt.codan.internal.checkers.ReturnStyleProblem=-Warning +org.eclipse.cdt.codan.internal.checkers.ReturnStyleProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Return with parenthesis\\")"} +org.eclipse.cdt.codan.internal.checkers.ScanfFormatStringSecurityProblem=-Warning +org.eclipse.cdt.codan.internal.checkers.ScanfFormatStringSecurityProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Format String Vulnerability\\")"} +org.eclipse.cdt.codan.internal.checkers.StatementHasNoEffectProblem=Warning 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a/Examples/MAX32690/USB/TinyUSB/msc_ext_flash/.settings/org.eclipse.cdt.core.prefs b/Examples/MAX32690/USB/TinyUSB/msc_ext_flash/.settings/org.eclipse.cdt.core.prefs new file mode 100644 index 00000000000..d3d72624abe --- /dev/null +++ b/Examples/MAX32690/USB/TinyUSB/msc_ext_flash/.settings/org.eclipse.cdt.core.prefs @@ -0,0 +1,15 @@ +eclipse.preferences.version=1 +environment/project/cdt.managedbuild.toolchain.gnu.cross.base.1028364529/BOARD/delimiter=; +environment/project/cdt.managedbuild.toolchain.gnu.cross.base.1028364529/BOARD/operation=append +environment/project/cdt.managedbuild.toolchain.gnu.cross.base.1028364529/BOARD/value=EvKit_V1 +environment/project/cdt.managedbuild.toolchain.gnu.cross.base.1028364529/GCC_PREFIX/delimiter=; +environment/project/cdt.managedbuild.toolchain.gnu.cross.base.1028364529/GCC_PREFIX/operation=replace +environment/project/cdt.managedbuild.toolchain.gnu.cross.base.1028364529/GCC_PREFIX/value=arm-none-eabi- +environment/project/cdt.managedbuild.toolchain.gnu.cross.base.1028364529/PROJECT/delimiter=; +environment/project/cdt.managedbuild.toolchain.gnu.cross.base.1028364529/PROJECT/operation=append +environment/project/cdt.managedbuild.toolchain.gnu.cross.base.1028364529/PROJECT/value=msc_ext_flash +environment/project/cdt.managedbuild.toolchain.gnu.cross.base.1028364529/TARGET/delimiter=; +environment/project/cdt.managedbuild.toolchain.gnu.cross.base.1028364529/TARGET/operation=append +environment/project/cdt.managedbuild.toolchain.gnu.cross.base.1028364529/TARGET/value=MAX32690 +environment/project/cdt.managedbuild.toolchain.gnu.cross.base.1028364529/append=true +environment/project/cdt.managedbuild.toolchain.gnu.cross.base.1028364529/appendContributed=true diff --git a/Examples/MAX32690/USB/TinyUSB/msc_ext_flash/.vscode/README.md b/Examples/MAX32690/USB/TinyUSB/msc_ext_flash/.vscode/README.md new file mode 100644 index 00000000000..5b355bd51c9 --- /dev/null +++ b/Examples/MAX32690/USB/TinyUSB/msc_ext_flash/.vscode/README.md @@ -0,0 +1,47 @@ +# VSCode-Maxim + +_(If you're viewing this document from within Visual Studio Code you can press `CTRL+SHIFT+V` to open a Markdown preview window.)_ + +## Quick Links + +* [MSDK User Guide](https://analogdevicesinc.github.io/msdk/USERGUIDE/) +* [VSCode-Maxim Github](https://github.com/analogdevicesinc/VSCode-Maxim) + +## Introduction + +VSCode-Maxim is a set of [Visual Studio Code](https://code.visualstudio.com/) project configurations and utilities for enabling embedded development for [Analog Device's MSDK](https://github.com/analogdevicesinc/msdk) and the [MAX32xxx/MAX78xxx microcontrollers](https://www.analog.com/en/product-category/microcontrollers.html). + +The following features are supported: + +* Code editing with intellisense down to the register level +* Code compilation with the ability to easily re-target a project for different microcontrollers and boards +* Flashing programs +* GUI and command-line debugging + +## Dependencies + +* [Visual Studio Code](https://code.visualstudio.com/) + * [C/C++ VSCode Extension](https://marketplace.visualstudio.com/items?itemName=ms-vscode.cpptools) + * [Cortex-Debug Extension](https://marketplace.visualstudio.com/items?itemName=marus25.cortex-debug) +* [Analog Devices MSDK](https://analogdevicesinc.github.io/msdk/) + +## Installation + +Install the MSDK, then set `"MAXIM_PATH"` in your _user_ VS Code settings. + +See [Getting Started with Visual Studio Code](https://analogdevicesinc.github.io/msdk/USERGUIDE/#getting-started-with-visual-studio-code) in the MSDK User Guide for detailed instructions. + +## Usage + +See the [MSDK User Guide](https://analogdevicesinc.github.io/msdk/USERGUIDE/#visual-studio-code) for detailed usage info. + +## Issue Tracker + +Bug reports, feature requests, and contributions are welcome via the [issues](https://github.com/analogdevicesinc/VSCode-Maxim/issues) tracker on Github. + +New issues should contain _at minimum_ the following information: + +* Visual Studio Code version #s (see `Help -> About`) +* C/C++ Extension version # +* Target microcontroller and evaluation platform +* The projects `.vscode` folder and `Makefile` (where applicable). Standard compression formats such as `.zip`, `.rar`, `.tar.gz`, etc. are all acceptable. diff --git a/Examples/MAX32690/USB/TinyUSB/msc_ext_flash/.vscode/c_cpp_properties.json b/Examples/MAX32690/USB/TinyUSB/msc_ext_flash/.vscode/c_cpp_properties.json new file mode 100644 index 00000000000..dfbed47b581 --- /dev/null +++ b/Examples/MAX32690/USB/TinyUSB/msc_ext_flash/.vscode/c_cpp_properties.json @@ -0,0 +1,53 @@ +{ + "configurations": [ + { + "name": "Win32", + "includePath": [ + "${default}" + ], + "defines": [ + "${default}" + ], + "intelliSenseMode": "gcc-arm", + "compilerPath": "${config:ARM_GCC_path}/bin/arm-none-eabi-gcc.exe", + "browse": { + "path": [ + "${default}" + ] + } + }, + { + "name": "Linux", + "includePath": [ + "${default}" + ], + "defines": [ + "${default}" + ], + "intelliSenseMode": "gcc-arm", + "compilerPath": "${config:ARM_GCC_path}/bin/arm-none-eabi-gcc", + "browse": { + "path": [ + "${default}" + ] + } + }, + { + "name": "Mac", + "includePath": [ + "${default}" + ], + "defines": [ + "${default}" + ], + "intelliSenseMode": "gcc-arm", + "compilerPath": "${config:ARM_GCC_path}/bin/arm-none-eabi-gcc", + "browse": { + "path": [ + "${default}" + ] + } + } + ], + "version": 4 +} \ No newline at end of file diff --git a/Examples/MAX32690/USB/TinyUSB/msc_ext_flash/.vscode/flash.gdb b/Examples/MAX32690/USB/TinyUSB/msc_ext_flash/.vscode/flash.gdb new file mode 100644 index 00000000000..8f22801a47d --- /dev/null +++ b/Examples/MAX32690/USB/TinyUSB/msc_ext_flash/.vscode/flash.gdb @@ -0,0 +1,17 @@ +define flash_m4 + set architecture armv7e-m + set remotetimeout 10 + target remote | openocd -c "gdb_port pipe;log_output flash.log" -s $arg0/scripts -f interface/$arg1 -f target/$arg2 -c "init; reset halt" + load + compare-sections + monitor reset halt +end + +define flash_m4_run + set architecture armv7e-m + set remotetimeout 10 + target remote | openocd -c "gdb_port pipe;log_output flash.log" -s $arg0/scripts -f interface/$arg1 -f target/$arg2 -c "init; reset halt" + load + compare-sections + monitor resume +end diff --git a/Examples/MAX32690/USB/TinyUSB/msc_ext_flash/.vscode/launch.json b/Examples/MAX32690/USB/TinyUSB/msc_ext_flash/.vscode/launch.json new file mode 100644 index 00000000000..01fe5199048 --- /dev/null +++ b/Examples/MAX32690/USB/TinyUSB/msc_ext_flash/.vscode/launch.json @@ -0,0 +1,133 @@ +{ + "configurations": [ + { + "name": "Debug Arm (Cortex-debug)", + "cwd":"${workspaceRoot}", + "executable": "${workspaceFolder}/build/${config:program_file}", + "loadFiles": ["${workspaceFolder}/build/${config:program_file}"], + "symbolFiles": [{ + "file": "${workspaceFolder}/build/${config:symbol_file}" + }], + "request": "launch", + "type": "cortex-debug", + "servertype": "openocd", + "linux": { + "gdbPath": "${config:ARM_GCC_path}/bin/arm-none-eabi-gdb", + "serverpath": "${config:OCD_path}/openocd", + }, + "windows": { + "gdbPath": "${config:ARM_GCC_path}/bin/arm-none-eabi-gdb.exe", + "serverpath": "${config:OCD_path}/openocd.exe", + }, + "osx": { + "gdbPath": "${config:ARM_GCC_path}/bin/arm-none-eabi-gdb", + "serverpath": "${config:OCD_path}/openocd", + }, + "searchDir": ["${config:OCD_path}/scripts"], + "configFiles": ["interface/${config:M4_OCD_interface_file}", "target/${config:M4_OCD_target_file}"], + "interface": "swd", + "runToEntryPoint": "main", + "svdFile": "${config:MAXIM_PATH}/Libraries/CMSIS/Device/Maxim/${config:target}/Include/${config:target}.svd" + }, + { + "name": "GDB (Arm M4)", + "type": "cppdbg", + "request": "launch", + "program": "${workspaceFolder}/build/${config:program_file}", + "args": [], + "stopAtEntry": true, + "cwd": "${workspaceFolder}", + "environment": [], + "externalConsole": false, + "MIMode": "gdb", + "linux": { + "miDebuggerPath": "${config:ARM_GCC_path}/bin/arm-none-eabi-gdb", + "debugServerPath": "${config:OCD_path}/openocd", + }, + "windows": { + "miDebuggerPath": "${config:ARM_GCC_path}/bin/arm-none-eabi-gdb.exe", + "debugServerPath": "${config:OCD_path}/openocd.exe", + }, + "osx": { + "miDebuggerPath": "${config:ARM_GCC_path}/bin/arm-none-eabi-gdb", + "debugServerPath": "${config:OCD_path}/bin/openocd", + }, + "logging": { + "exceptions": true, + "trace": false, + "traceResponse": false, + "engineLogging": false + }, + "miDebuggerServerAddress": "localhost:3333", + "debugServerArgs": "-s ${config:OCD_path}/scripts -f interface/${config:M4_OCD_interface_file} -f target/${config:M4_OCD_target_file} -c \"init; reset halt\"", + "serverStarted": "Info : Listening on port 3333 for gdb connections", + "filterStderr": true, + "targetArchitecture": "arm", + "customLaunchSetupCommands": [ + {"text":"-list-features"} + ], + "setupCommands": [ + { "text":"set logging overwrite on"}, + { "text":"set logging file debug-arm.log"}, + { "text":"set logging on"}, + { "text":"cd ${workspaceFolder}" }, + { "text":"exec-file build/${config:program_file}" }, + { "text":"symbol-file build/${config:symbol_file}" }, + { "text":"target remote localhost:3333" }, + { "text":"monitor reset halt" }, + { "text":"set $pc=Reset_Handler"}, + { "text":"b main" } + ] + }, + { + "name": "GDB (RISC-V)", + "type": "cppdbg", + "request": "launch", + "program": "${workspaceFolder}/buildrv/${config:program_file}", + "args": [], + "stopAtEntry": false, + "cwd": "${workspaceFolder}", + "environment": [], + "externalConsole": false, + "MIMode": "gdb", + "linux": { + "miDebuggerPath": "${config:xPack_GCC_path}/bin/riscv-none-elf-gdb", + "debugServerPath": "${config:OCD_path}/openocd", + }, + "windows": { + "miDebuggerPath": "${config:xPack_GCC_path}/bin/riscv-none-elf-gdb.exe", + "debugServerPath": "${config:OCD_path}/openocd.exe", + }, + "osx": { + "miDebuggerPath": "${config:xPack_GCC_path}/bin/riscv-none-elf-gdb", + "debugServerPath": "${config:OCD_path}/bin/openocd", + }, + "logging": { + "exceptions": true, + "trace": false, + "traceResponse": false, + "engineLogging": false + }, + "miDebuggerServerAddress": "localhost:3334", + "debugServerArgs": "-c \"gdb_port 3334\" -s ${config:OCD_path}/scripts -f interface/${config:RV_OCD_interface_file} -f target/${config:RV_OCD_target_file}", + "serverStarted": "Info : Listening on port 3334 for gdb connections", + "filterStderr": true, + "customLaunchSetupCommands": [ + {"text":"-list-features"} + ], + "targetArchitecture": "arm", + "setupCommands": [ + { "text":"set logging overwrite on"}, + { "text":"set logging file debug-riscv.log"}, + { "text":"set logging on"}, + { "text":"cd ${workspaceFolder}" }, + { "text": "set architecture riscv:rv32", "ignoreFailures": false }, + { "text":"exec-file build/${config:program_file}", "ignoreFailures": false }, + { "text":"symbol-file buildrv/${config:symbol_file}", "ignoreFailures": false }, + { "text":"target remote localhost:3334" }, + { "text":"b main" }, + { "text": "set $pc=Reset_Handler","ignoreFailures": false } + ] + } + ] +} diff --git a/Examples/MAX32690/USB/TinyUSB/msc_ext_flash/.vscode/settings.json b/Examples/MAX32690/USB/TinyUSB/msc_ext_flash/.vscode/settings.json new file mode 100644 index 00000000000..289c72d1f70 --- /dev/null +++ b/Examples/MAX32690/USB/TinyUSB/msc_ext_flash/.vscode/settings.json @@ -0,0 +1,89 @@ +{ + "terminal.integrated.env.windows": { + "Path":"${config:OCD_path};${config:ARM_GCC_path}/bin;${config:xPack_GCC_path}/bin;${config:MSYS_path}/usr/bin;${config:Make_path};${env:PATH}", + "MAXIM_PATH":"${config:MAXIM_PATH}" + }, + "terminal.integrated.defaultProfile.windows": "Command Prompt", + + "terminal.integrated.env.linux": { + "PATH":"${config:OCD_path}:${config:ARM_GCC_path}/bin:${config:xPack_GCC_path}/bin:${config:Make_path}:${env:PATH}", + "MAXIM_PATH":"${config:MAXIM_PATH}" + }, + "terminal.integrated.env.osx": { + "PATH":"${config:OCD_path}/bin:${config:ARM_GCC_path}/bin:${config:xPack_GCC_path}/bin:${config:Make_path}:${env:PATH}", + "MAXIM_PATH":"${config:MAXIM_PATH}" + }, + + "target":"MAX32690", + "board":"APARD", + + "project_name":"${workspaceFolderBasename}", + + "program_file":"${config:project_name}.elf", + "symbol_file":"${config:program_file}", + + "M4_OCD_interface_file":"cmsis-dap.cfg", + "M4_OCD_target_file":"max32690.cfg", + "RV_OCD_interface_file":"ftdi/olimex-arm-usb-ocd-h.cfg", + "RV_OCD_target_file":"${config:target}_riscv.cfg", + + "v_Arm_GCC":"10.3", + "v_xPack_GCC":"12.2.0-3.1", + + "OCD_path":"${config:MAXIM_PATH}/Tools/OpenOCD", + "ARM_GCC_path":"${config:MAXIM_PATH}/Tools/GNUTools/${config:v_Arm_GCC}", + "xPack_GCC_path":"${config:MAXIM_PATH}/Tools/xPack/riscv-none-elf-gcc/${config:v_xPack_GCC}", + "Make_path":"${config:MAXIM_PATH}/Tools/GNUTools/Make", + "MSYS_path":"${config:MAXIM_PATH}/Tools/MSYS2", + + "C_Cpp.default.includePath": [ + "${workspaceFolder}", + "${workspaceFolder}/**", + "${config:MAXIM_PATH}/Libraries/Boards/${config:target}/Include", + "${config:MAXIM_PATH}/Libraries/Boards/${config:target}/${config:board}/Include", + "${config:MAXIM_PATH}/Libraries/CMSIS/Device/Maxim/${config:target}/Include", + "${config:MAXIM_PATH}/Libraries/CMSIS/Include", + "${config:ARM_GCC_path}/arm-none-eabi/include", + "${config:ARM_GCC_path}/lib/gcc/arm-none-eabi/${config:v_Arm_GCC}/include", + "${config:MAXIM_PATH}/Libraries/PeriphDrivers/Include/${config:target}", + "${config:MAXIM_PATH}/Libraries/MiscDrivers/Camera", + "${config:MAXIM_PATH}/Libraries/MiscDrivers/Display", + "${config:MAXIM_PATH}/Libraries/MiscDrivers/Display/fonts", + "${config:MAXIM_PATH}/Libraries/MiscDrivers/ExtMemory", + "${config:MAXIM_PATH}/Libraries/MiscDrivers/LED", + "${config:MAXIM_PATH}/Libraries/MiscDrivers/PMIC", + "${config:MAXIM_PATH}/Libraries/MiscDrivers/PushButton", + "${config:MAXIM_PATH}/Libraries/MiscDrivers/Touchscreen", + "${config:MAXIM_PATH}/Libraries/MAXUSB/include", + "${config:MAXIM_PATH}/Libraries/MAXUSB/include/core", + "${config:MAXIM_PATH}/Libraries/MAXUSB/include/dgb_log", + "${config:MAXIM_PATH}/Libraries/MAXUSB/include/devclass", + "${config:MAXIM_PATH}/Libraries/MAXUSB/include/enumerate", + "${config:MAXIM_PATH}/Libraries/MAXUSB/include/core/musbhsfc" + ], + "C_Cpp.default.browse.path": [ + "${workspaceFolder}", + "${config:MAXIM_PATH}/Libraries/Boards/${config:target}/Source", + "${config:MAXIM_PATH}/Libraries/Boards/${config:target}/${config:board}/Source", + "${config:MAXIM_PATH}/Libraries/PeriphDrivers/Source", + "${config:MAXIM_PATH}/Libraries/MiscDrivers/Camera", + "${config:MAXIM_PATH}/Libraries/MiscDrivers/Display", + "${config:MAXIM_PATH}/Libraries/MiscDrivers/Display/fonts", + "${config:MAXIM_PATH}/Libraries/MiscDrivers/LED", + "${config:MAXIM_PATH}/Libraries/MiscDrivers/PMIC", + "${config:MAXIM_PATH}/Libraries/MiscDrivers/PushButton", + "${config:MAXIM_PATH}/Libraries/MiscDrivers/Touchscreen", + "${config:MAXIM_PATH}/Libraries/MiscDrivers", + "${config:MAXIM_PATH}/Libraries/MAXUSB/src/core", + "${config:MAXIM_PATH}/Libraries/MAXUSB/src/dbg_log", + "${config:MAXIM_PATH}/Libraries/MAXUSB/src/devclass", + "${config:MAXIM_PATH}/Libraries/MAXUSB/src/enumerate" + ], + "C_Cpp.default.defines": [ + + ], + "C_Cpp.default.forcedInclude": [ + "${workspaceFolder}/build/project_defines.h" + ] +} + diff --git a/Examples/MAX32690/USB/TinyUSB/msc_ext_flash/.vscode/tasks.json b/Examples/MAX32690/USB/TinyUSB/msc_ext_flash/.vscode/tasks.json new file mode 100644 index 00000000000..e95445e2b3e --- /dev/null +++ b/Examples/MAX32690/USB/TinyUSB/msc_ext_flash/.vscode/tasks.json @@ -0,0 +1,115 @@ +{ + "version": "2.0.0", + "tasks": [ + { + "label": "build", + "type": "shell", + "command": "make -r -j 8 --output-sync=target --no-print-directory TARGET=${config:target} BOARD=${config:board} MAXIM_PATH=${config:MAXIM_PATH} MAKE=make PROJECT=${config:project_name}", + "osx":{ + "command": "source ~/.zshrc && make -r -j 8 --output-sync=target --no-print-directory TARGET=${config:target} BOARD=${config:board} MAXIM_PATH=${config:MAXIM_PATH} MAKE=make PROJECT=${config:project_name}" + }, + "group": "build", + "problemMatcher": [] + }, + { + "label": "clean", + "type": "shell", + "command": "make -j 8 clean --output-sync=target --no-print-directory TARGET=${config:target} BOARD=${config:board} MAXIM_PATH=${config:MAXIM_PATH} MAKE=make PROJECT=${config:project_name}", + "osx":{ + "command": "source ~/.zshrc && make -j 8 clean --output-sync=target --no-print-directory TARGET=${config:target} BOARD=${config:board} MAXIM_PATH=${config:MAXIM_PATH} MAKE=make PROJECT=${config:project_name}" + }, + "group": "build", + "problemMatcher": [] + }, + { + "label": "clean-periph", + "type": "shell", + "command": "make -j 8 distclean --output-sync=target --no-print-directory TARGET=${config:target} BOARD=${config:board} MAXIM_PATH=${config:MAXIM_PATH} MAKE=make PROJECT=${config:project_name}", + "osx":{ + "command": "source ~/.zshrc && make -j 8 distclean --output-sync=target --no-print-directory TARGET=${config:target} BOARD=${config:board} MAXIM_PATH=${config:MAXIM_PATH} MAKE=make PROJECT=${config:project_name}" + }, + "group": "build", + "problemMatcher": [] + }, + { + "label": "flash", + "type": "shell", + "command": "arm-none-eabi-gdb", + "args": [ + "--cd=\"${workspaceFolder}\"", + "--se=\"build/${config:program_file}\"", + "--symbols=build/${config:symbol_file}", + "-x=\"${workspaceFolder}/.vscode/flash.gdb\"", + "--ex=\"flash_m4 ${config:OCD_path} ${config:M4_OCD_interface_file} ${config:M4_OCD_target_file}\"", + "--batch" + ], + "group": "build", + "problemMatcher": [], + "dependsOn":["build"] + }, + { + "label": "flash & run", + "type": "shell", + "command": "arm-none-eabi-gdb", + "args": [ + "--cd=\"${workspaceFolder}\"", + "--se=\"build/${config:program_file}\"", + "--symbols=build/${config:symbol_file}", + "-x=\"${workspaceFolder}/.vscode/flash.gdb\"", + "--ex=\"flash_m4_run ${config:OCD_path} ${config:M4_OCD_interface_file} ${config:M4_OCD_target_file}\"", + "--batch" + ], + "group": "build", + "problemMatcher": [], + "dependsOn":["build"] + }, + { + "label": "erase flash", + "type": "shell", + "command": "openocd", + "args": [ + "-s", "${config:OCD_path}/scripts", + "-f", "interface/${config:M4_OCD_interface_file}", + "-f", "target/${config:M4_OCD_target_file}", + "-c", "\"init; reset halt; max32xxx mass_erase 0;\"", + "-c", "exit" + ], + "group":"build", + "problemMatcher": [], + "dependsOn":[] + }, + { + "label": "openocd (m4)", + "type": "shell", + "command": "openocd", + "args": [ + "-s", + "${config:OCD_path}/scripts", + "-f", + "interface/${config:M4_OCD_interface_file}", + "-f", + "target/${config:M4_OCD_target_file}", + "-c", + "\"init; reset halt\"" + ], + "problemMatcher": [], + "dependsOn":[] + }, + { + "label": "gdb (m4)", + "type": "shell", + "command": "arm-none-eabi-gdb", + "args": [ + "--ex=\"cd ${workspaceFolder}\"", + "--se=\"build/${config:program_file}\"", + "--symbols=build/${config:symbol_file}", + "--ex=\"target remote localhost:3333\"", + "--ex=\"monitor reset halt\"", + "--ex=\"b main\"", + "--ex=\"c\"" + ], + "problemMatcher": [], + "dependsOn":[] + }, + ] +} \ No newline at end of file diff --git a/Examples/MAX32690/USB/TinyUSB/msc_ext_flash/Makefile b/Examples/MAX32690/USB/TinyUSB/msc_ext_flash/Makefile new file mode 100644 index 00000000000..b210c698c06 --- /dev/null +++ b/Examples/MAX32690/USB/TinyUSB/msc_ext_flash/Makefile @@ -0,0 +1,382 @@ +############################################################################### + # + # Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + # Analog Devices, Inc.), + # Copyright (C) 2023-2024 Analog Devices, Inc. + # + # Licensed under the Apache License, Version 2.0 (the "License"); + # you may not use this file except in compliance with the License. + # You may obtain a copy of the License at + # + # http://www.apache.org/licenses/LICENSE-2.0 + # + # Unless required by applicable law or agreed to in writing, software + # distributed under the License is distributed on an "AS IS" BASIS, + # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + # See the License for the specific language governing permissions and + # limitations under the License. + # + ############################################################################## + +# ** Readme! ** +# Don't edit this file! This is the core Makefile for a MaximSDK +# project. The available configuration options can be overridden +# in "project.mk", on the command-line, or with system environment +# variables. + +# See https://analogdevicesinc.github.io/msdk/USERGUIDE/#build-system +# for more detailed instructions on how to use this system. + +# The detailed instructions mentioned above are easier to read than +# this file, but the comments found in this file also outline the +# available configuration variables. This file is organized into +# sub-sections, some of which expose config variables. + + +# ******************************************************************************* +# Set the target microcontroller and board to compile for. + +# Every TARGET microcontroller has some Board Support Packages (BSPs) that are +# available for it under the MaximSDK/Libraries/Boards/TARGET folder. The BSP +# that gets selected is MaximSDK/Libraries/Boards/TARGET/BOARD. + +# Configuration Variables: +# - TARGET : Override the default target microcontroller. Ex: TARGET=MAX78000 +# - BOARD : Override the default BSP (case sensitive). Ex: BOARD=EvKit_V1, BOARD=FTHR_RevA + + +ifeq "$(TARGET)" "" +# Default target microcontroller +TARGET := MAX32690 +TARGET_UC := MAX32690 +TARGET_LC := max32690 +else +# "TARGET" has been overridden in the environment or on the command-line. +# We need to calculate an upper and lowercase version of the part number, +# because paths on Linux and MacOS are case-sensitive. +TARGET_UC := $(subst m,M,$(subst a,A,$(subst x,X,$(TARGET)))) +TARGET_LC := $(subst M,m,$(subst A,a,$(subst X,x,$(TARGET)))) +endif + +# Default board. +BOARD ?= APARD + +# ******************************************************************************* +# Locate the MaximSDK + +# This Makefile needs to know where to find the MaximSDK, and the MAXIM_PATH variable +# should point to the root directory of the MaximSDK installation. Setting this manually +# is usually only required if you're working on the command-line. + +# If MAXIM_PATH is not specified, we assume the project still lives inside of the MaximSDK +# and move up from this project's original location. + +# Configuration Variables: +# - MAXIM_PATH : Tell this Makefile where to find the MaximSDK. Ex: MAXIM_PATH=C:/MaximSDK + + +ifneq "$(MAXIM_PATH)" "" +# Sanitize MAXIM_PATH for backslashes +MAXIM_PATH := $(subst \,/,$(MAXIM_PATH)) +# Locate some other useful paths... +LIBS_DIR := $(abspath $(MAXIM_PATH)/Libraries) +CMSIS_ROOT := $(LIBS_DIR)/CMSIS +endif + +# ******************************************************************************* +# Include project Makefile. We do this after formulating TARGET, BOARD, and MAXIM_PATH +# in case project.mk needs to reference those values. However, we also include +# this as early as possible in the Makefile so that it can append to or override +# the variables below. + + +PROJECTMK ?= $(abspath ./project.mk) +include $(PROJECTMK) +$(info Loaded project.mk) +# PROJECTMK is also used by implicit rules and other libraries to add project.mk as a watch file + +# ******************************************************************************* +# Final path sanitization and re-calculation. No options here. + +ifeq "$(MAXIM_PATH)" "" +# MAXIM_PATH is still not defined... +DEPTH := ../../../../ +MAXIM_PATH := $(abspath $(DEPTH)) +$(warning Warning: MAXIM_PATH is not set! Set MAXIM_PATH in your environment or in project.mk to clear this warning.) +$(warning Warning: Attempting to use $(MAXIM_PATH) calculated from relative path) +else +# Sanitize MAXIM_PATH for backslashes +MAXIM_PATH := $(subst \,/,$(MAXIM_PATH)) +endif + +# Final recalculation of LIBS_DIR/CMSIS_ROOT +LIBS_DIR := $(abspath $(MAXIM_PATH)/Libraries) +CMSIS_ROOT := $(LIBS_DIR)/CMSIS + +# One final UC/LC check in case user set TARGET in project.mk +TARGET_UC := $(subst m,M,$(subst a,A,$(subst x,X,$(TARGET)))) +TARGET_LC := $(subst M,m,$(subst A,a,$(subst X,x,$(TARGET)))) + +export TARGET +export TARGET_UC +export TARGET_LC +export CMSIS_ROOT +# TODO: Remove dependency on exports for these variables. + +# ******************************************************************************* +# Set up search paths, and auto-detect all source code on those paths. + +# The following paths are searched by default, where "./" is the project directory. +# ./ +# |- *.h +# |- *.c +# |-include (optional) +# |- *.h +# |-src (optional) +# |- *.c + +# Configuration Variables: +# - VPATH : Tell this Makefile to search additional locations for source (.c) files. +# You should use the "+=" operator with this option. +# Ex: VPATH += your/new/path +# - IPATH : Tell this Makefile to search additional locations for header (.h) files. +# You should use the "+=" operator with this option. +# Ex: VPATH += your/new/path +# - SRCS : Tell this Makefile to explicitly add a source (.c) file to the build. +# This is really only useful if you want to add a source file that isn't +# on any VPATH, in which case you can add the full path to the file here. +# You should use the "+=" operator with this option. +# Ex: SRCS += your/specific/source/file.c +# - AUTOSEARCH : Set whether this Makefile should automatically detect .c files on +# VPATH and add them to the build. This is enabled by default. Set +# to 0 to disable. If autosearch is disabled, source files must be +# manually added to SRCS. +# Ex: AUTOSEARCH = 0 + + +# Where to find source files for this project. +VPATH += . +VPATH += src +VPATH := $(VPATH) + +# Where to find header files for this project +IPATH += . +IPATH += include +IPATH := $(IPATH) + +AUTOSEARCH ?= 1 +ifeq ($(AUTOSEARCH), 1) +# Auto-detect all C/C++ source files on VPATH +SRCS += $(wildcard $(addsuffix /*.c, $(VPATH))) +SRCS += $(wildcard $(addsuffix /*.cpp, $(VPATH))) +endif + +# Collapse SRCS before passing them on to the next stage +SRCS := $(SRCS) + +# ******************************************************************************* +# Set the output filename + +# Configuration Variables: +# - PROJECT : Override the default output filename. Ex: PROJECT=MyProject + + +# The default value creates a file named after the target micro. Ex: MAX78000.elf +PROJECT ?= $(TARGET_LC) + +# ******************************************************************************* +# Compiler options + +# Configuration Variables: +# - DEBUG : Set DEBUG=1 to build explicitly for debugging. This adds some additional +# symbols and sets -Og as the default optimization level. +# - MXC_OPTIMIZE_CFLAGS : Override the default compiler optimization level. +# Ex: MXC_OPTIMIZE_CFLAGS = -O2 +# - PROJ_CFLAGS : Add additional compiler flags to the build. +# You should use the "+=" operator with this option. +# Ex: PROJ_CFLAGS += -Wextra +# - MFLOAT_ABI : Set the floating point acceleration level. +# The only options are "hard", "soft", or "softfp". +# Ex: MFLOAT_ABI = hard +# - LINKERFILE : Override the default linkerfile. +# Ex: LINKERFILE = customlinkerfile.ld +# - LINKERPATH : Override the default search location for $(LINKERFILE) +# The default search location is $(CMSIS_ROOT)/Device/Maxim/$(TARGET_UC)/Source/GCC +# If $(LINKERFILE) cannot be found at this path, then the root project +# directory will be used as a fallback. + +# Select 'GCC' or 'IAR' compiler +ifeq "$(COMPILER)" "" +COMPILER := GCC +endif + +# Set default compiler optimization levels +ifeq "$(MAKECMDGOALS)" "release" +# Default optimization level for "release" builds (make release) +MXC_OPTIMIZE_CFLAGS ?= -O2 +DEBUG = 0 +endif + +ifeq ($(DEBUG),1) +# Optimizes for debugging as recommended +# by GNU for code-edit-debug cycles +# https://gcc.gnu.org/onlinedocs/gcc/Optimize-Options.html#Optimize-Options +MXC_OPTIMIZE_CFLAGS := -Og +endif + +# Default level if not building for release or explicitly for debug +MXC_OPTIMIZE_CFLAGS ?= -Og + +# Set compiler flags +PROJ_CFLAGS += -Wall # Enable warnings +PROJ_CFLAGS += -DMXC_ASSERT_ENABLE + +# Set hardware floating point acceleration. +# Options are: +# - hard +# - soft +# - softfp (default if MFLOAT_ABI is not set) +MFLOAT_ABI ?= softfp +# MFLOAT_ABI must be exported to other Makefiles +export MFLOAT_ABI + +# This path contains system-level intialization files for the target micro. Add to the build. +VPATH += $(CMSIS_ROOT)/Device/Maxim/$(TARGET_UC)/Source + +# ******************************************************************************* +# Secure Boot Tools (SBT) + +# This section integrates the Secure Boot Tools. It's intended for use with +# microcontrollers that have a secure bootloader. + +# Enabling SBT integration will add some special rules, such as "make sla", "make scpa", etc. + +# Configuration variables: +# SBT : Toggle SBT integration. Set to 1 to enable, or 0 +# to disable +# MAXIM_SBT_DIR : Specify the location of the SBT tool binaries. This defaults to +# Tools/SBT in the MaximSDK. The standalone SBT installer will override +# this via an environment variable. +# TARGET_SEC : Specify the part number to be passed into the SBT. This should match +# the secure variant part #. The default value will depend on TARGET. +# For example, TARGET=MAX32650 will result in TARGET_SEC=MAX32651, and +# the default selection happens in Tools/SBT/SBT-config. +# However, if there are multiple secure part #s for the target +# microcontroller this variable may need to be changed. + +SBT ?= 0 +ifeq ($(SBT), 1) +MAXIM_SBT_DIR ?= $(MAXIM_PATH)/Tools/SBT +MAXIM_SBT_DIR := $(subst \,/,$(MAXIM_SBT_DIR)) +# ^ Must sanitize path for \ on Windows, since this may come from an environment +# variable. + +export MAXIM_SBT_DIR # SBTs must have this environment variable defined to work + +# SBT-config.mk and SBT-rules.mk are included further down this Makefile. + +endif # SBT + +# ******************************************************************************* +# Default goal selection. This section allows you to override the default goal +# that will run if no targets are specified on the command-line. +# (ie. just running 'make' instead of 'make all') + +# Configuration variables: +# .DEFAULT_GOAL : Set the default goal if no targets were specified on the +# command-line +# ** "override" must be used with this variable. ** +# Ex: "override .DEFAULT_GOAL = mygoal" + +ifeq "$(.DEFAULT_GOAL)" "" +ifeq ($(SBT),1) +override .DEFAULT_GOAL := sla +else +override .DEFAULT_GOAL := all +endif +endif + +# Developer note: 'override' is used above for legacy Makefile compatibility. +# gcc.mk/gcc_riscv.mk need to hard-set 'all' internally, so this new system +# uses 'override' to come in over the top without breaking old projects. + +# It's also necessary to explicitly set MAKECMDGOALS... +ifeq "$(MAKECMDGOALS)" "" +MAKECMDGOALS:=$(.DEFAULT_GOAL) +endif + +# Enable colors when --sync-output is used. +# See https://www.gnu.org/software/make/manual/make.html#Terminal-Output (section 13.2) +ifneq ($(MAKE_TERMOUT),) +PROJ_CFLAGS += -fdiagnostics-color=always +endif + +ifneq ($(FORCE_COLOR),) +PROJ_CFLAGS += -fdiagnostics-color=always +endif + +# ******************************************************************************* +# Include SBT config. We need to do this here because it needs to know +# the current MAKECMDGOAL. +ifeq ($(SBT),1) +include $(MAXIM_PATH)/Tools/SBT/SBT-config.mk +endif + +# ******************************************************************************* +# Libraries + +# This section offers "toggle switches" to include or exclude the libraries that +# are available in the MaximSDK. Set a configuration variable to 1 to include the +# library in the build, or 0 to exclude. + +# Each library may also have its own library specific configuration variables. See +# Libraries/libs.mk for more details. + +# Configuration variables: +# - LIB_BOARD : Include the Board-Support Package (BSP) library. (Enabled by default) +# - LIB_PERIPHDRIVERS : Include the peripheral driver library. (Enabled by default) +# - LIB_CMSIS_DSP : Include the CMSIS-DSP library. +# - LIB_CORDIO : Include the Cordio BLE library +# - LIB_FCL : Include the Free Cryptographic Library (FCL) +# - LIB_FREERTOS : Include the FreeRTOS and FreeRTOS-Plus-CLI libraries +# - LIB_LC3 : Include the Low Complexity Communication Codec (LC3) library +# - LIB_LITTLEFS : Include the "little file system" (littleFS) library +# - LIB_LWIP : Include the lwIP library +# - LIB_MAXUSB : Include the MAXUSB library +# - LIB_SDHC : Include the SDHC library + +include $(LIBS_DIR)/libs.mk + + +# ******************************************************************************* +# Rules + +# Include the rules for building for this target. All other makefiles should be +# included before this one. +include $(CMSIS_ROOT)/Device/Maxim/$(TARGET_UC)/Source/$(COMPILER)/$(TARGET_LC).mk + +# Include the rules that integrate the SBTs. SBTs are a special case that must be +# include after the core gcc rules to extend them. +ifeq ($(SBT), 1) +include $(MAXIM_PATH)/Tools/SBT/SBT-rules.mk +endif + + +# Get .DEFAULT_GOAL working. +ifeq "$(MAKECMDGOALS)" "" +MAKECMDGOALS:=$(.DEFAULT_GOAL) +endif + + +all: +# Extend the functionality of the "all" recipe here + arm-none-eabi-size --format=berkeley $(BUILD_DIR)/$(PROJECT).elf + +libclean: + $(MAKE) -f ${PERIPH_DRIVER_DIR}/periphdriver.mk clean.periph + +clean: +# Extend the functionality of the "clean" recipe here + +# The rule to clean out all the build products. +distclean: clean libclean diff --git a/Examples/MAX32690/USB/TinyUSB/msc_ext_flash/README.md b/Examples/MAX32690/USB/TinyUSB/msc_ext_flash/README.md new file mode 100644 index 00000000000..7efab027ec6 --- /dev/null +++ b/Examples/MAX32690/USB/TinyUSB/msc_ext_flash/README.md @@ -0,0 +1,39 @@ +## Description + +The example demonstrates the use of USB Mass Storage driver class with TinyUSB. +The storage driver is connected to the External Flash device on the AD-APARD32690-SL board. + + +## Software + +### Project Usage + +Universal instructions on building, flashing, and debugging this project can be found in the **[MSDK User Guide](https://analogdevicesinc.github.io/msdk/USERGUIDE/)**. + +### Project-Specific Build Notes + +tusb_config.h by default has logging disabled via the CFG_TUSB_DEBUG definition. +For TinyUSB console logging, set the debug level to 1, 2, or 3, with a higher value +indicating more verbose logging. + +## Required Connections + + +If using the AD-APARD32690-SL: +- Connect a USB cable between the PC and the P10 (USB-C) connector. +- Connect a MAXPICO Debug adapter to P9 (SWD Connector) +- Open a terminal application on the PC and connect to the MAXPICO's console UART at 115200, 8-N-1. + +## Expected Output + +By default, the console UART does not output any message. With CFG_TUSB_DEBUG set +to '2', the Console UART of the device will output these messages: + +``` +USBD init on controller 0, Highspeed = 1024 +sizeof(usbd_device_t) = 69 +sizeof(dcd_event_t) = 12 +sizeof(tu_fifo_t) = 12 +sizeof(tu_edpt_stream_t) = 24 +MSC init +``` diff --git a/Examples/MAX32690/USB/TinyUSB/msc_ext_flash/main.c b/Examples/MAX32690/USB/TinyUSB/msc_ext_flash/main.c new file mode 100644 index 00000000000..804d11e1447 --- /dev/null +++ b/Examples/MAX32690/USB/TinyUSB/msc_ext_flash/main.c @@ -0,0 +1,175 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2019 Ha Thach (tinyusb.org) + * Copyright (c) 2024 Analog Devices, Inc + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + */ + +#include +#include +#include + +#include "bsp/board_api.h" +#include "tusb.h" +#include "led.h" +#include "pb.h" +#include "mxc_device.h" +#include "gcr_regs.h" +#include "mcr_regs.h" +#include "mxc_sys.h" +#include "Ext_Flash.h" + +//--------------------------------------------------------------------+ +// MACRO CONSTANT TYPEDEF PROTYPES +//--------------------------------------------------------------------+ + +/* Blink pattern + * - 250 ms : device not mounted + * - 1000 ms : device mounted + * - 2500 ms : device is suspended + */ +enum { + BLINK_NOT_MOUNTED = 250, + BLINK_MOUNTED = 1000, + BLINK_SUSPENDED = 2500, +}; + +static uint32_t blink_interval_ms = BLINK_NOT_MOUNTED; + +void led_blinking_task(void); +void spixf_disk_init(void); + +/*------------- MAIN -------------*/ +int main(void) +{ + board_init(); + + // init device stack on configured roothub port + tud_init(BOARD_TUD_RHPORT); + + if (board_init_after_tusb) { + board_init_after_tusb(); + } + + while (1) { + tud_task(); // tinyusb device task + led_blinking_task(); + } +} + +//--------------------------------------------------------------------+ +// Device callbacks +//--------------------------------------------------------------------+ + +// Invoked when device is mounted +void tud_mount_cb(void) +{ + blink_interval_ms = BLINK_MOUNTED; +} + +// Invoked when device is unmounted +void tud_umount_cb(void) +{ + blink_interval_ms = BLINK_NOT_MOUNTED; +} + +// Invoked when usb bus is suspended +// remote_wakeup_en : if host allow us to perform remote wakeup +// Within 7ms, device must draw an average of current less than 2.5 mA from bus +void tud_suspend_cb(bool remote_wakeup_en) +{ + (void)remote_wakeup_en; + blink_interval_ms = BLINK_SUSPENDED; +} + +// Invoked when usb bus is resumed +void tud_resume_cb(void) +{ + blink_interval_ms = tud_mounted() ? BLINK_MOUNTED : BLINK_NOT_MOUNTED; +} + +//--------------------------------------------------------------------+ +// BLINKING TASK +//--------------------------------------------------------------------+ +void led_blinking_task(void) +{ + static uint32_t start_ms = 0; + static bool led_state = false; + + // Blink every interval ms + if (board_millis() - start_ms < blink_interval_ms) + return; // not enough time + start_ms += blink_interval_ms; + + board_led_write(led_state); + led_state = 1 - led_state; // toggle +} + +//------------------------------------------------------------------------------ +// Wrapper functions to bridge TinyUSB BSP with MSDK BSP +//------------------------------------------------------------------------------ +void board_init(void) +{ + // 1ms tick timer + SysTick_Config(SystemCoreClock / 1000); + + MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_IPO); + MXC_MCR->ldoctrl |= MXC_F_MCR_LDOCTRL_0P9EN; + MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_USB); + MXC_SYS_Reset_Periph(MXC_SYS_RESET0_USB); + + spixf_disk_init(); +} + +void board_led_write(bool state) +{ + if (state) { + LED_On(0); + } else { + LED_Off(0); + } +} + +uint32_t board_button_read(void) +{ + return PB_Get(0); +} + +//--------------------------------------------------------------------+ +// Forward USB interrupt events to TinyUSB IRQ Handler +//--------------------------------------------------------------------+ +void USB_IRQHandler(void) +{ + tud_int_handler(0); +} + +volatile uint32_t system_ticks = 0; + +void SysTick_Handler(void) +{ + system_ticks++; +} + +uint32_t board_millis(void) +{ + return system_ticks; +} diff --git a/Examples/MAX32690/USB/TinyUSB/msc_ext_flash/msc_ext_flash.c b/Examples/MAX32690/USB/TinyUSB/msc_ext_flash/msc_ext_flash.c new file mode 100644 index 00000000000..e604c4cd1cf --- /dev/null +++ b/Examples/MAX32690/USB/TinyUSB/msc_ext_flash/msc_ext_flash.c @@ -0,0 +1,283 @@ +/****************************************************************************** + * + * Copyright (C) 2023-2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#include "bsp/board_api.h" +#include "tusb.h" + +#include "Ext_Flash.h" +#include "spixf.h" + +#define LBA_SIZE 512 /* Size of "logical blocks" in bytes */ +#define LBA_SIZE_SHIFT 9 /* The shift value used to convert between addresses and block numbers */ + +#if defined(EXT_FLASH_MX25) +#undef EXT_FLASH_BAUD +#define EXT_FLASH_BAUD 5000000 /* SPI clock rate to communicate with the external flash */ + +#define EXT_FLASH_SECTOR_SIZE 4096 /* Number of bytes in one sector of the external flash */ +#define EXT_FLASH_SECTOR_SIZE_SHIFT \ + 12 /* The shift value used to convert between addresses and block numbers */ +#define EXT_FLASH_NUM_SECTORS 2048 /* Total number of sectors in the external flash */ + +#define MXC_SPIXF_WIDTH Ext_Flash_DataLine_Quad /*Number of data lines*/ +#else +#error "Defined flash device not yet implemented!" +#endif + +#define LBA_PER_SECTOR (EXT_FLASH_SECTOR_SIZE >> LBA_SIZE_SHIFT) +#define INVALID_SECTOR \ + EXT_FLASH_NUM_SECTORS /* Use a sector number past the end of memory to indicate invalid */ + +#define NUM_LBA (EXT_FLASH_NUM_SECTORS * LBA_PER_SECTOR) + +static bool is_running = false; +static bool is_initialized = false; +static uint32_t active_sector_num = INVALID_SECTOR; +static uint8_t active_sector[EXT_FLASH_SECTOR_SIZE]; +static bool active_sector_dirty = false; + +void spixf_disk_init(void); +static uint32_t spixf_disk_get_sect_num(uint32_t lba); +static uint32_t spixf_disk_get_sect_addr(uint32_t lba); +static uint32_t spixf_disk_get_sect(uint32_t num); + +// Invoked to determine max LUN +uint8_t tud_msc_get_maxlun_cb(void) +{ + return 1; // single LUN +} + +// Invoked when received SCSI_CMD_INQUIRY +// Application fill vendor id, product id and revision with string up to 8, 16, 4 characters respectively +void tud_msc_inquiry_cb(uint8_t lun, uint8_t vendor_id[8], uint8_t product_id[16], + uint8_t product_rev[4]) +{ + (void)lun; // use same ID for both LUNs + + const char vid[] = "TinyUSB"; + const char pid[] = "Mass Storage"; + const char rev[] = "1.0"; + + memcpy(vendor_id, vid, strlen(vid)); + memcpy(product_id, pid, strlen(pid)); + memcpy(product_rev, rev, strlen(rev)); +} + +// Invoked when received Test Unit Ready command. +// return true allowing host to read/write this LUN e.g SD card inserted +bool tud_msc_test_unit_ready_cb(uint8_t lun) +{ + return is_initialized; +} + +// Invoked when received SCSI_CMD_READ_CAPACITY_10 and SCSI_CMD_READ_FORMAT_CAPACITY to determine the disk size +// Application update block count and block size +void tud_msc_capacity_cb(uint8_t lun, uint32_t *block_count, uint16_t *block_size) +{ + (void)lun; + + *block_count = NUM_LBA; + *block_size = LBA_SIZE; +} + +// Invoked when received Start Stop Unit command +// - Start = 0 : stopped power mode, if load_eject = 1 : unload disk storage +// - Start = 1 : active mode, if load_eject = 1 : load disk storage +bool tud_msc_start_stop_cb(uint8_t lun, uint8_t power_condition, bool start, bool load_eject) +{ + (void)lun; + (void)power_condition; + + if (load_eject) { + if (start) { + // load disk storage + is_running = true; + } else { + // unload disk storage + //Sync dirty sector if any + spixf_disk_get_sect(INVALID_SECTOR); + is_running = false; + } + } + + return is_initialized; +} + +// Callback invoked when received READ10 command. +// Copy disk's data to buffer (up to bufsize) and return number of copied bytes. +int32_t tud_msc_read10_cb(uint8_t lun, uint32_t lba, uint32_t offset, void *buffer, + uint32_t bufsize) +{ + uint32_t addr; + uint32_t s_num; + + if (lba >= NUM_LBA) { + return -1; + } + + /* Convert to external flash sector number. */ + s_num = spixf_disk_get_sect_num(lba); + + if (spixf_disk_get_sect(s_num)) { + /* Failed to write/read from external flash */ + return -1; + } + + /* Get the offset into the current sector */ + addr = spixf_disk_get_sect_addr(lba); + + memcpy(buffer, active_sector + addr + offset, bufsize); + + return (int32_t)bufsize; +} + +bool tud_msc_is_writable_cb(uint8_t lun) +{ + (void)lun; + + return true; +} + +// Callback invoked when received WRITE10 command. +// Process data in buffer to disk's storage and return number of written bytes +int32_t tud_msc_write10_cb(uint8_t lun, uint32_t lba, uint32_t offset, uint8_t *buffer, + uint32_t bufsize) +{ + uint32_t addr; + uint32_t s_num; + + // out of ramdisk + if (lba >= NUM_LBA) { + return -1; + } + + /* Convert to external flash sector number. */ + s_num = spixf_disk_get_sect_num(lba); + + if (spixf_disk_get_sect(s_num)) { + /* Failed to write/read from external flash */ + return -1; + } + + /* Get the offset into the current sector */ + addr = spixf_disk_get_sect_addr(lba); + + memcpy(active_sector + addr + offset, buffer, bufsize); + active_sector_dirty = 1; + + return (int32_t)bufsize; +} + +// Callback invoked when received an SCSI command not in built-in list below +// - READ_CAPACITY10, READ_FORMAT_CAPACITY, INQUIRY, MODE_SENSE6, REQUEST_SENSE +// - READ10 and WRITE10 has their own callbacks (MUST not be handled here) +int32_t tud_msc_scsi_cb(uint8_t lun, uint8_t const scsi_cmd[16], void *buffer, uint16_t bufsize) +{ + void const *response = NULL; + int32_t resplen = 0; + + // most scsi handled is input + bool in_xfer = true; + + switch (scsi_cmd[0]) { + default: + // Set Sense = Invalid Command Operation + tud_msc_set_sense(lun, SCSI_SENSE_ILLEGAL_REQUEST, 0x20, 0x00); + + // negative means error -> tinyusb could stall and/or response with failed status + return -1; + } + + // return resplen must not larger than bufsize + if (resplen > bufsize) + resplen = bufsize; + + if (response && (resplen > 0)) { + if (in_xfer) { + memcpy(buffer, response, (size_t)resplen); + } else { + // SCSI output + } + } + + return resplen; +} + +void spixf_disk_init() +{ + uint32_t id; + if (!is_initialized) { + Ext_Flash_Init(); + Ext_Flash_Reset(); + + if (MXC_SPIXF_WIDTH == Ext_Flash_DataLine_Quad) { + Ext_Flash_Quad(1); + } else { + Ext_Flash_Quad(0); + } + + id = Ext_Flash_ID(); + + is_initialized = true; + } +} + +static uint32_t spixf_disk_get_sect_num(uint32_t lba) +{ + /* Absolute_address = lba * LBA_SIZE */ + /* Sector_num = Absolute_address / EXT_FLASH_SECTOR_SIZE */ + /* Sector_num = lba * 512 / 4096 */ + return lba >> (EXT_FLASH_SECTOR_SIZE_SHIFT - LBA_SIZE_SHIFT); +} + +static uint32_t spixf_disk_get_sect_addr(uint32_t lba) +{ + /* eight 512 byte blocks in each sector */ + return (lba & (LBA_PER_SECTOR - 1)) << LBA_SIZE_SHIFT; +} + +static uint32_t spixf_disk_get_sect(uint32_t num) +{ + /* New sector requested? */ + if (active_sector_num != num) { + /* Is the current sector real? */ + if (active_sector_num != INVALID_SECTOR) { + /* Was it written to after it was read from memory? */ + if (active_sector_dirty) { + /* Erase the old data. */ + Ext_Flash_Erase(active_sector_num << EXT_FLASH_SECTOR_SIZE_SHIFT, + Ext_Flash_Erase_4K); + /* Write the new */ + Ext_Flash_Program_Page(active_sector_num << EXT_FLASH_SECTOR_SIZE_SHIFT, + active_sector, EXT_FLASH_SECTOR_SIZE, MXC_SPIXF_WIDTH); + /* Mark data as clean */ + active_sector_dirty = false; + } + } + + /* Requesting a new valid sector? */ + if (num != INVALID_SECTOR) { + Ext_Flash_Read(num << EXT_FLASH_SECTOR_SIZE_SHIFT, active_sector, EXT_FLASH_SECTOR_SIZE, + MXC_SPIXF_WIDTH); + active_sector_dirty = false; + active_sector_num = num; + } + } + + return 0; +} diff --git a/Examples/MAX32690/USB/TinyUSB/msc_ext_flash/msc_ext_flash.launch b/Examples/MAX32690/USB/TinyUSB/msc_ext_flash/msc_ext_flash.launch new file mode 100644 index 00000000000..2c69317c25d --- /dev/null +++ b/Examples/MAX32690/USB/TinyUSB/msc_ext_flash/msc_ext_flash.launch @@ -0,0 +1,62 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Examples/MAX32690/USB/TinyUSB/msc_ext_flash/project.mk b/Examples/MAX32690/USB/TinyUSB/msc_ext_flash/project.mk new file mode 100644 index 00000000000..b23b3de6915 --- /dev/null +++ b/Examples/MAX32690/USB/TinyUSB/msc_ext_flash/project.mk @@ -0,0 +1,22 @@ +# This file can be used to set build configuration +# variables. These variables are defined in a file called +# "Makefile" that is located next to this one. + +# For instructions on how to use this system, see +# https://analogdevicesinc.github.io/msdk/USERGUIDE/#build-system + +# ********************************************************** + +# If you have secure version of MCU, set SBT=1 to generate signed binary +# For more information on how sing process works, see +# https://www.analog.com/en/education/education-library/videos/6313214207112.html +SBT=0 + +# Enable TINYUSB library +LIB_TINYUSB=1 +TINYUSB_CONFIG_DIR = ./ + +# The APARD board is the only EvKit with onboard SPIXF Flash +ifneq ($(BOARD),APARD) +$(error ERR_NOTSUPPORTED: This project is only supported for the AD-APARD32690 board) +endif diff --git a/Examples/MAX32690/USB/TinyUSB/msc_ext_flash/tusb_config.h b/Examples/MAX32690/USB/TinyUSB/msc_ext_flash/tusb_config.h new file mode 100644 index 00000000000..2554a6586b8 --- /dev/null +++ b/Examples/MAX32690/USB/TinyUSB/msc_ext_flash/tusb_config.h @@ -0,0 +1,107 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2019 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + */ + +#ifndef EXAMPLES_MAX32690_USB_TINYUSB_MSC_EXT_FLASH_TUSB_CONFIG_H_ +#define EXAMPLES_MAX32690_USB_TINYUSB_MSC_EXT_FLASH_TUSB_CONFIG_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +//--------------------------------------------------------------------+ +// Board Specific Configuration +//--------------------------------------------------------------------+ + +// RHPort number used for device can be defined by board.mk, default to port 0 +#ifndef BOARD_TUD_RHPORT +#define BOARD_TUD_RHPORT 0 +#endif + +// RHPort max operational speed can defined by board.mk +#ifndef BOARD_TUD_MAX_SPEED +#define BOARD_TUD_MAX_SPEED OPT_MODE_DEFAULT_SPEED +#endif + +//-------------------------------------------------------------------- +// COMMON CONFIGURATION +//-------------------------------------------------------------------- + +// defined by compiler flags for flexibility +#ifndef CFG_TUSB_MCU +#error CFG_TUSB_MCU must be defined +#endif + +#ifndef CFG_TUSB_OS +#define CFG_TUSB_OS OPT_OS_NONE +#endif + +#ifndef CFG_TUSB_DEBUG +#define CFG_TUSB_DEBUG 0 +#endif + +// Enable Device stack +#define CFG_TUD_ENABLED 1 + +// Default is max speed that hardware controller could support with on-chip PHY +#define CFG_TUD_MAX_SPEED BOARD_TUD_MAX_SPEED + +/* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment. + * Tinyusb use follows macros to declare transferring memory so that they can be put + * into those specific section. + * e.g + * - CFG_TUSB_MEM SECTION : __attribute__ (( section(".usb_ram") )) + * - CFG_TUSB_MEM_ALIGN : __attribute__ ((aligned(4))) + */ +#ifndef CFG_TUSB_MEM_SECTION +#define CFG_TUSB_MEM_SECTION +#endif + +#ifndef CFG_TUSB_MEM_ALIGN +#define CFG_TUSB_MEM_ALIGN __attribute__((aligned(4))) +#endif + +//-------------------------------------------------------------------- +// DEVICE CONFIGURATION +//-------------------------------------------------------------------- + +#ifndef CFG_TUD_ENDPOINT0_SIZE +#define CFG_TUD_ENDPOINT0_SIZE 64 +#endif + +//------------- CLASS -------------// +#define CFG_TUD_CDC 0 +#define CFG_TUD_MSC 1 +#define CFG_TUD_HID 0 +#define CFG_TUD_MIDI 0 +#define CFG_TUD_VENDOR 0 + +// MSC Buffer size of Device Mass storage +#define CFG_TUD_MSC_EP_BUFSIZE 512 + +#ifdef __cplusplus +} +#endif + +#endif // EXAMPLES_MAX32690_USB_TINYUSB_MSC_EXT_FLASH_TUSB_CONFIG_H_ diff --git a/Examples/MAX32690/USB/TinyUSB/msc_ext_flash/usb_descriptors.c b/Examples/MAX32690/USB/TinyUSB/msc_ext_flash/usb_descriptors.c new file mode 100644 index 00000000000..0c6bfd7fa64 --- /dev/null +++ b/Examples/MAX32690/USB/TinyUSB/msc_ext_flash/usb_descriptors.c @@ -0,0 +1,206 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2019 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + */ + +#include "bsp/board_api.h" +#include "tusb.h" + +/* A combination of interfaces must have a unique product id, since PC will save device driver after the first plug. + * Same VID/PID with different interface e.g MSC (first), then CDC (later) will possibly cause system error on PC. + * + * Auto ProductID layout's Bitmap: + * [MSB] HID | MSC | CDC [LSB] + */ +#define _PID_MAP(itf, n) ((CFG_TUD_##itf) << (n)) +#define USB_PID \ + (0x4000 | _PID_MAP(CDC, 0) | _PID_MAP(MSC, 1) | _PID_MAP(HID, 2) | _PID_MAP(MIDI, 3) | \ + _PID_MAP(VENDOR, 4)) + +//--------------------------------------------------------------------+ +// Device Descriptors +//--------------------------------------------------------------------+ +tusb_desc_device_t const desc_device = { .bLength = sizeof(tusb_desc_device_t), + .bDescriptorType = TUSB_DESC_DEVICE, + .bcdUSB = 0x0200, + .bDeviceClass = 0x00, + .bDeviceSubClass = 0x00, + .bDeviceProtocol = 0x00, + .bMaxPacketSize0 = CFG_TUD_ENDPOINT0_SIZE, + + .idVendor = 0xCafe, + .idProduct = USB_PID, + .bcdDevice = 0x0100, + + .iManufacturer = 0x01, + .iProduct = 0x02, + .iSerialNumber = 0x03, + + .bNumConfigurations = 0x01 }; + +// Invoked when received GET DEVICE DESCRIPTOR +// Application return pointer to descriptor +uint8_t const *tud_descriptor_device_cb(void) +{ + return (uint8_t const *)&desc_device; +} + +//--------------------------------------------------------------------+ +// Configuration Descriptor +//--------------------------------------------------------------------+ + +enum { ITF_NUM_MSC, ITF_NUM_TOTAL }; + +#define CONFIG_TOTAL_LEN (TUD_CONFIG_DESC_LEN + TUD_MSC_DESC_LEN) + +#if CFG_TUSB_MCU == OPT_MCU_LPC175X_6X || CFG_TUSB_MCU == OPT_MCU_LPC177X_8X || \ + CFG_TUSB_MCU == OPT_MCU_LPC40XX +// LPC 17xx and 40xx endpoint type (bulk/interrupt/iso) are fixed by its number +// 0 control, 1 In, 2 Bulk, 3 Iso, 4 In, 5 Bulk etc ... +#define EPNUM_MSC_OUT 0x02 +#define EPNUM_MSC_IN 0x82 + +#elif CFG_TUSB_MCU == OPT_MCU_SAMG +// SAMG doesn't support a same endpoint number with different direction IN and OUT +// e.g EP1 OUT & EP1 IN cannot exist together +#define EPNUM_MSC_OUT 0x01 +#define EPNUM_MSC_IN 0x82 + +#elif CFG_TUSB_MCU == OPT_MCU_FT90X || CFG_TUSB_MCU == OPT_MCU_FT93X +// FT9XX doesn't support a same endpoint number with different direction IN and OUT +// e.g EP1 OUT & EP1 IN cannot exist together +#define EPNUM_MSC_OUT 0x01 +#define EPNUM_MSC_IN 0x82 + +#elif CFG_TUSB_MCU == OPT_MCU_MAX32690 || CFG_TUSB_MCU == OPT_MCU_MAX32650 || \ + CFG_TUSB_MCU == OPT_MCU_MAX32666 || CFG_TUSB_MCU == OPT_MCU_MAX78002 +// MAX32 doesn't support a same endpoint number with different direction IN and OUT +// e.g EP1 OUT & EP1 IN cannot exist together +#define EPNUM_MSC_OUT 0x01 +#define EPNUM_MSC_IN 0x82 + +#else +#define EPNUM_MSC_OUT 0x01 +#define EPNUM_MSC_IN 0x81 + +#endif + +uint8_t const desc_fs_configuration[] = { + // Config number, interface count, string index, total length, attribute, power in mA + TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100), + + // Interface number, string index, EP Out & EP In address, EP size + TUD_MSC_DESCRIPTOR(ITF_NUM_MSC, 0, EPNUM_MSC_OUT, EPNUM_MSC_IN, 64), +}; + +#if TUD_OPT_HIGH_SPEED +uint8_t const desc_hs_configuration[] = { + // Config number, interface count, string index, total length, attribute, power in mA + TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100), + + // Interface number, string index, EP Out & EP In address, EP size + TUD_MSC_DESCRIPTOR(ITF_NUM_MSC, 0, EPNUM_MSC_OUT, EPNUM_MSC_IN, 512), +}; +#endif + +// Invoked when received GET CONFIGURATION DESCRIPTOR +// Application return pointer to descriptor +// Descriptor contents must exist long enough for transfer to complete +uint8_t const *tud_descriptor_configuration_cb(uint8_t index) +{ + (void)index; // for multiple configurations + +#if TUD_OPT_HIGH_SPEED + // Although we are highspeed, host may be fullspeed. + return (tud_speed_get() == TUSB_SPEED_HIGH) ? desc_hs_configuration : desc_fs_configuration; +#else + return desc_fs_configuration; +#endif +} + +//--------------------------------------------------------------------+ +// String Descriptors +//--------------------------------------------------------------------+ + +// String Descriptor Index +enum { + STRID_LANGID = 0, + STRID_MANUFACTURER, + STRID_PRODUCT, + STRID_SERIAL, +}; + +// array of pointer to string descriptors +char const *string_desc_arr[] = { + (const char[]){ 0x09, 0x04 }, // 0: is supported language is English (0x0409) + "TinyUSB", // 1: Manufacturer + "TinyUSB Device", // 2: Product + NULL, // 3: Serials will use unique ID if possible +}; + +static uint16_t _desc_str[32 + 1]; + +// Invoked when received GET STRING DESCRIPTOR request +// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete +uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) +{ + (void)langid; + size_t chr_count; + + switch (index) { + case STRID_LANGID: + memcpy(&_desc_str[1], string_desc_arr[0], 2); + chr_count = 1; + break; + + case STRID_SERIAL: + chr_count = board_usb_get_serial(_desc_str + 1, 32); + break; + + default: + // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors. + // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors + + if (!(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0]))) + return NULL; + + const char *str = string_desc_arr[index]; + + // Cap at max char + chr_count = strlen(str); + size_t const max_count = sizeof(_desc_str) / sizeof(_desc_str[0]) - 1; // -1 for string type + if (chr_count > max_count) + chr_count = max_count; + + // Convert ASCII string into UTF-16 + for (size_t i = 0; i < chr_count; i++) { + _desc_str[1 + i] = str[i]; + } + break; + } + + // first byte is length (including header), second byte is string type + _desc_str[0] = (uint16_t)((TUSB_DESC_STRING << 8) | (2 * chr_count + 2)); + + return _desc_str; +} diff --git a/Libraries/Boards/MAX32690/APARD/Source/board.c b/Libraries/Boards/MAX32690/APARD/Source/board.c index 0889bad3443..249e68aef6e 100644 --- a/Libraries/Boards/MAX32690/APARD/Source/board.c +++ b/Libraries/Boards/MAX32690/APARD/Source/board.c @@ -85,7 +85,14 @@ __weak void GPIO2_IRQHandler(void) /******************************************************************************/ static int ext_flash_board_init(void) { - return MXC_SPIXF_Init(0, EXT_FLASH_BAUD); + int err; + + err = MXC_SPIXF_Init(0x0B, EXT_FLASH_BAUD); + + if (err == E_NO_ERROR) { + MXC_SPIXF_Enable(); + } + return err; } /******************************************************************************/ diff --git a/Libraries/PeriphDrivers/Source/SPIXF/spixf_me18.c b/Libraries/PeriphDrivers/Source/SPIXF/spixf_me18.c index 361429a705a..6c295cb0119 100644 --- a/Libraries/PeriphDrivers/Source/SPIXF/spixf_me18.c +++ b/Libraries/PeriphDrivers/Source/SPIXF/spixf_me18.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by * Analog Devices, Inc.), * Copyright (C) 2023-2024 Analog Devices, Inc. * @@ -35,6 +35,7 @@ int MXC_SPIXF_Init(uint32_t cmdval, uint32_t frequency) #ifndef MSDK_NO_GPIO_CLK_INIT MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_SPIXIP); // SPIX MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_SPIXIPC); // SPIXFC + MXC_GPIO_Config(&gpio_cfg_spixf); #endif return MXC_SPIXF_RevA_Init((mxc_spixfc_reva_regs_t *)MXC_SPIXFC, From c0561a995c4b007bf8c9e39215a79c5fe6d8071a Mon Sep 17 00:00:00 2001 From: Sihyung Woo <75494566+sihyung-maxim@users.noreply.github.com> Date: Fri, 25 Oct 2024 15:52:30 -0500 Subject: [PATCH 18/37] fix(Other): Add `delete me warning` in PR template (#1189) --- .github/pull_request_template.md | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/.github/pull_request_template.md b/.github/pull_request_template.md index e443c4cb48c..1643dca9959 100644 --- a/.github/pull_request_template.md +++ b/.github/pull_request_template.md @@ -1,5 +1,3 @@ -## Pull Request Template - ### Description Please include a summary of the changes and related issues. Please also include relevant motivation and context. @@ -11,6 +9,12 @@ Please include a summary of the changes and related issues. Please also include - [ ] (Optional) Link any related GitHub issues [using a keyword](https://docs.github.com/en/issues/tracking-your-work-with-issues/linking-a-pull-request-to-an-issue#linking-a-pull-request-to-an-issue-using-a-keyword) - [ ] (Optional) Provide info on any relevant functional testing/validation. For API changes or significant features, this is not optional. +_______________________________________________________________________________ + +> [!WARNING] +> This is a template. Delete everything below the line when submitting a pull request. + + ### PR Title Guidelines The MSDK repo follows a custom rule set based on the [Conventional Commits](https://www.conventionalcommits.org/en/v1.0.0/) standard. The pull request titles will follow this format: From 1eba0397fd5078b8de5442c93edb4978a947c15f Mon Sep 17 00:00:00 2001 From: Lorne Smith <65424047+lorne-maxim@users.noreply.github.com> Date: Fri, 25 Oct 2024 16:06:51 -0500 Subject: [PATCH 19/37] build(Other): Fix incorrect variable name used for NFC library selection for MAX32670, MAX32671, and MAX32672 (#1244) --- Libraries/libs.mk | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Libraries/libs.mk b/Libraries/libs.mk index bb5428c64de..0e2c97e7a2f 100644 --- a/Libraries/libs.mk +++ b/Libraries/libs.mk @@ -281,13 +281,13 @@ ifneq ($(DEV_LIB_NFC),1) # Add to include directory list IPATH += $(LIB_NFC_PCD_PBM_DIR)/include PROJ_LDFLAGS += -L$(LIB_NFC_PCD_PBM_DIR) -PROJ_LIBS += nfc_pcd_pbm_$(LIBRARY_VARIANT) +PROJ_LIBS += nfc_pcd_pbm_$(MFLOAT_ABI) # Add to include directory list IPATH += $(LIB_NFC_PCD_RF_DRIVER_DIR)/include IPATH += $(LIB_NFC_PCD_RF_DRIVER_DIR)/include/nfc PROJ_LDFLAGS += -L$(LIB_NFC_PCD_RF_DRIVER_DIR) -PROJ_LIBS += nfc_pcd_rf_driver_MAX32570_$(LIBRARY_VARIANT) +PROJ_LIBS += nfc_pcd_rf_driver_MAX32570_$(MFLOAT_ABI) else # Development setup (DEV_LIB_NFC=1) for building libraries From be46ff67f58f2bb2e82be70deab18a47eb4642c4 Mon Sep 17 00:00:00 2001 From: EricB-ADI <122300463+EricB-ADI@users.noreply.github.com> Date: Mon, 4 Nov 2024 15:22:10 -0600 Subject: [PATCH 20/37] chore(BLE): Added Declaration for PalBbIsEnabled (#1252) --- Libraries/Cordio/platform/include/pal_bb.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/Libraries/Cordio/platform/include/pal_bb.h b/Libraries/Cordio/platform/include/pal_bb.h index 0fc16a6661a..aba61dbedaf 100644 --- a/Libraries/Cordio/platform/include/pal_bb.h +++ b/Libraries/Cordio/platform/include/pal_bb.h @@ -210,6 +210,15 @@ void PalBbRestore(void); /*************************************************************************************************/ void PalBbEnable(void); +/*************************************************************************************************/ +/*! + * \brief Checks to see if BB is enabled. + * + * \return true is BB is enabled + */ +/*************************************************************************************************/ +bool PalBbIsEnabled(void); + /*************************************************************************************************/ /*! * \brief Disable the BB hardware. From 092782af683c4e6e666bef9190b0b2ab16673df1 Mon Sep 17 00:00:00 2001 From: Jake Carter Date: Tue, 5 Nov 2024 13:00:57 -0700 Subject: [PATCH 21/37] fix(Build): Fix `IPATH` not Affecting PeriphDriver Sub-Makes (#1256) --- Libraries/PeriphDrivers/periphdriver.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Libraries/PeriphDrivers/periphdriver.mk b/Libraries/PeriphDrivers/periphdriver.mk index 6e873ef2c89..a1ed9bff8a4 100644 --- a/Libraries/PeriphDrivers/periphdriver.mk +++ b/Libraries/PeriphDrivers/periphdriver.mk @@ -99,7 +99,7 @@ export PERIPH_DRIVER_BUILD_DIR LIBS += ${PERIPH_DRIVER_BUILD_DIR}/${PERIPH_DRIVER_LIB} # Add rule to build the Driver Library ${PERIPH_DRIVER_BUILD_DIR}/${PERIPH_DRIVER_LIB}: ${PERIPH_DRIVER_C_FILES} ${PERIPH_DRIVER_A_FILES} ${PROJECTMK} - @$(MAKE) -f ${PERIPH_DRIVER_DIR}/libPeriphDriver.mk lib BUILD_DIR=${PERIPH_DRIVER_BUILD_DIR} PROJ_CFLAGS="$(PROJ_CFLAGS)" PROJ_LDFLAGS="$(PROJ_LDFLAGS)" MXC_OPTIMIZE_CFLAGS=$(MXC_OPTIMIZE_CFLAGS) MFLOAT_ABI=$(MFLOAT_ABI) DUAL_CORE=$(DUAL_CORE) RISCV_CORE=$(RISCV_CORE) PROJECTMK=$(PROJECTMK) PERIPH_DRIVER_LIB_FILENAME=$(PERIPH_DRIVER_LIB_FILENAME) + @$(MAKE) -f ${PERIPH_DRIVER_DIR}/libPeriphDriver.mk lib BUILD_DIR=${PERIPH_DRIVER_BUILD_DIR} PROJ_CFLAGS="$(PROJ_CFLAGS)" PROJ_LDFLAGS="$(PROJ_LDFLAGS)" MXC_OPTIMIZE_CFLAGS=$(MXC_OPTIMIZE_CFLAGS) IPATH="$(IPATH)" MFLOAT_ABI=$(MFLOAT_ABI) DUAL_CORE=$(DUAL_CORE) RISCV_CORE=$(RISCV_CORE) PROJECTMK=$(PROJECTMK) PERIPH_DRIVER_LIB_FILENAME=$(PERIPH_DRIVER_LIB_FILENAME) clean.periph: @$(MAKE) -f ${PERIPH_DRIVER_DIR}/libPeriphDriver.mk BUILD_DIR=${PERIPH_DRIVER_BUILD_DIR} PERIPH_DRIVER_LIB_FILENAME=$(PERIPH_DRIVER_LIB_FILENAME) clean From e0967e11ac83a6e47d753aa60281ad1fcb2a4196 Mon Sep 17 00:00:00 2001 From: Kevin Gillespie Date: Wed, 6 Nov 2024 17:01:37 -0600 Subject: [PATCH 22/37] feat(BLE): Adding Bluetooth example for MAX32657 (#1246) --- .../MAX32657/Bluetooth/BLE5_ctr/.cproject | 93 + Examples/MAX32657/Bluetooth/BLE5_ctr/.project | 26 + .../BLE5_ctr/.settings/language.settings.xml | 15 + .../org.eclipse.cdt.codan.core.prefs | 93 + .../.settings/org.eclipse.cdt.core.prefs | 15 + .../Bluetooth/BLE5_ctr/.vscode/README.md | 47 + .../BLE5_ctr/.vscode/c_cpp_properties.json | 53 + .../Bluetooth/BLE5_ctr/.vscode/flash.gdb | 17 + .../Bluetooth/BLE5_ctr/.vscode/launch.json | 133 + .../Bluetooth/BLE5_ctr/.vscode/settings.json | 101 + .../Bluetooth/BLE5_ctr/.vscode/tasks.json | 115 + .../Bluetooth/BLE5_ctr/ARM/Abstract.txt | 1 + .../MAX32657/Bluetooth/BLE5_ctr/ARM/BLE.sct | 49 + .../BLE5_ctr/ARM/BTLE_BLE5_ctr.uvoptx | 268 + .../BLE5_ctr/ARM/BTLE_BLE5_ctr.uvprojx | 564 +++ .../BLE5_ctr/ARM/EventRecorderStub.scvd | 9 + .../Bluetooth/BLE5_ctr/BLE5_ctr.launch | 62 + .../Bluetooth/BLE5_ctr/IAR/BTLE_BLE5_ctr.ewd | 2974 +++++++++++ .../Bluetooth/BLE5_ctr/IAR/BTLE_BLE5_ctr.ewp | 4402 +++++++++++++++++ Examples/MAX32657/Bluetooth/BLE5_ctr/Makefile | 382 ++ .../MAX32657/Bluetooth/BLE5_ctr/README.md | 38 + Examples/MAX32657/Bluetooth/BLE5_ctr/main.c | 295 ++ .../MAX32657/Bluetooth/BLE5_ctr/project.mk | 40 + Libraries/libs.mk | 50 +- 24 files changed, 9810 insertions(+), 32 deletions(-) create mode 100644 Examples/MAX32657/Bluetooth/BLE5_ctr/.cproject create mode 100644 Examples/MAX32657/Bluetooth/BLE5_ctr/.project create mode 100644 Examples/MAX32657/Bluetooth/BLE5_ctr/.settings/language.settings.xml create mode 100644 Examples/MAX32657/Bluetooth/BLE5_ctr/.settings/org.eclipse.cdt.codan.core.prefs create mode 100644 Examples/MAX32657/Bluetooth/BLE5_ctr/.settings/org.eclipse.cdt.core.prefs create mode 100755 Examples/MAX32657/Bluetooth/BLE5_ctr/.vscode/README.md create mode 100755 Examples/MAX32657/Bluetooth/BLE5_ctr/.vscode/c_cpp_properties.json create mode 100755 Examples/MAX32657/Bluetooth/BLE5_ctr/.vscode/flash.gdb create mode 100755 Examples/MAX32657/Bluetooth/BLE5_ctr/.vscode/launch.json create mode 100755 Examples/MAX32657/Bluetooth/BLE5_ctr/.vscode/settings.json create mode 100755 Examples/MAX32657/Bluetooth/BLE5_ctr/.vscode/tasks.json create mode 100644 Examples/MAX32657/Bluetooth/BLE5_ctr/ARM/Abstract.txt create mode 100644 Examples/MAX32657/Bluetooth/BLE5_ctr/ARM/BLE.sct create mode 100644 Examples/MAX32657/Bluetooth/BLE5_ctr/ARM/BTLE_BLE5_ctr.uvoptx create mode 100644 Examples/MAX32657/Bluetooth/BLE5_ctr/ARM/BTLE_BLE5_ctr.uvprojx create mode 100644 Examples/MAX32657/Bluetooth/BLE5_ctr/ARM/EventRecorderStub.scvd create mode 100644 Examples/MAX32657/Bluetooth/BLE5_ctr/BLE5_ctr.launch create mode 100644 Examples/MAX32657/Bluetooth/BLE5_ctr/IAR/BTLE_BLE5_ctr.ewd create mode 100644 Examples/MAX32657/Bluetooth/BLE5_ctr/IAR/BTLE_BLE5_ctr.ewp create mode 100644 Examples/MAX32657/Bluetooth/BLE5_ctr/Makefile create mode 100644 Examples/MAX32657/Bluetooth/BLE5_ctr/README.md create mode 100644 Examples/MAX32657/Bluetooth/BLE5_ctr/main.c create mode 100644 Examples/MAX32657/Bluetooth/BLE5_ctr/project.mk diff --git a/Examples/MAX32657/Bluetooth/BLE5_ctr/.cproject b/Examples/MAX32657/Bluetooth/BLE5_ctr/.cproject new file mode 100644 index 00000000000..9dce635ec3f --- /dev/null +++ b/Examples/MAX32657/Bluetooth/BLE5_ctr/.cproject @@ -0,0 +1,93 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Examples/MAX32657/Bluetooth/BLE5_ctr/.project b/Examples/MAX32657/Bluetooth/BLE5_ctr/.project new file mode 100644 index 00000000000..3ec8a6bd77c --- /dev/null +++ b/Examples/MAX32657/Bluetooth/BLE5_ctr/.project @@ -0,0 +1,26 @@ + + + BLE5_ctr + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + diff --git a/Examples/MAX32657/Bluetooth/BLE5_ctr/.settings/language.settings.xml b/Examples/MAX32657/Bluetooth/BLE5_ctr/.settings/language.settings.xml new file mode 100644 index 00000000000..d32717b6f37 --- /dev/null +++ b/Examples/MAX32657/Bluetooth/BLE5_ctr/.settings/language.settings.xml @@ -0,0 +1,15 @@ + + + + + + + + + + + + + + + diff --git a/Examples/MAX32657/Bluetooth/BLE5_ctr/.settings/org.eclipse.cdt.codan.core.prefs b/Examples/MAX32657/Bluetooth/BLE5_ctr/.settings/org.eclipse.cdt.codan.core.prefs new file mode 100644 index 00000000000..59c0b37ba75 --- /dev/null +++ b/Examples/MAX32657/Bluetooth/BLE5_ctr/.settings/org.eclipse.cdt.codan.core.prefs @@ -0,0 +1,93 @@ +eclipse.preferences.version=1 +org.eclipse.cdt.codan.checkers.errnoreturn=Warning +org.eclipse.cdt.codan.checkers.errnoreturn.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"No return\\")",implicit\=>false} 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+org.eclipse.cdt.codan.internal.checkers.VariableResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Symbol is not resolved\\")"} +org.eclipse.cdt.codan.internal.checkers.VirtualMethodCallProblem=-Error +org.eclipse.cdt.codan.internal.checkers.VirtualMethodCallProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Virtual method call in constructor/destructor\\")"} +org.eclipse.cdt.qt.core.qtproblem=Warning +org.eclipse.cdt.qt.core.qtproblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>false,RUN_ON_INC_BUILD\=>false,RUN_ON_FILE_OPEN\=>true,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>null} diff --git a/Examples/MAX32657/Bluetooth/BLE5_ctr/.settings/org.eclipse.cdt.core.prefs b/Examples/MAX32657/Bluetooth/BLE5_ctr/.settings/org.eclipse.cdt.core.prefs new file mode 100644 index 00000000000..f009d7302df --- /dev/null +++ b/Examples/MAX32657/Bluetooth/BLE5_ctr/.settings/org.eclipse.cdt.core.prefs @@ -0,0 +1,15 @@ +eclipse.preferences.version=1 +environment/project/cdt.managedbuild.toolchain.gnu.cross.base.1028364529/BOARD/delimiter=; +environment/project/cdt.managedbuild.toolchain.gnu.cross.base.1028364529/BOARD/operation=append +environment/project/cdt.managedbuild.toolchain.gnu.cross.base.1028364529/BOARD/value=EvKit_V1 +environment/project/cdt.managedbuild.toolchain.gnu.cross.base.1028364529/GCC_PREFIX/delimiter=; +environment/project/cdt.managedbuild.toolchain.gnu.cross.base.1028364529/GCC_PREFIX/operation=replace +environment/project/cdt.managedbuild.toolchain.gnu.cross.base.1028364529/GCC_PREFIX/value=arm-none-eabi- +environment/project/cdt.managedbuild.toolchain.gnu.cross.base.1028364529/PROJECT/delimiter=; +environment/project/cdt.managedbuild.toolchain.gnu.cross.base.1028364529/PROJECT/operation=append +environment/project/cdt.managedbuild.toolchain.gnu.cross.base.1028364529/PROJECT/value=BLE5_ctr +environment/project/cdt.managedbuild.toolchain.gnu.cross.base.1028364529/TARGET/delimiter=; +environment/project/cdt.managedbuild.toolchain.gnu.cross.base.1028364529/TARGET/operation=append +environment/project/cdt.managedbuild.toolchain.gnu.cross.base.1028364529/TARGET/value=MAX32657 +environment/project/cdt.managedbuild.toolchain.gnu.cross.base.1028364529/append=true +environment/project/cdt.managedbuild.toolchain.gnu.cross.base.1028364529/appendContributed=true diff --git a/Examples/MAX32657/Bluetooth/BLE5_ctr/.vscode/README.md b/Examples/MAX32657/Bluetooth/BLE5_ctr/.vscode/README.md new file mode 100755 index 00000000000..5b355bd51c9 --- /dev/null +++ b/Examples/MAX32657/Bluetooth/BLE5_ctr/.vscode/README.md @@ -0,0 +1,47 @@ +# VSCode-Maxim + +_(If you're viewing this document from within Visual Studio Code you can press `CTRL+SHIFT+V` to open a Markdown preview window.)_ + +## Quick Links + +* [MSDK User Guide](https://analogdevicesinc.github.io/msdk/USERGUIDE/) +* [VSCode-Maxim Github](https://github.com/analogdevicesinc/VSCode-Maxim) + +## Introduction + +VSCode-Maxim is a set of [Visual Studio Code](https://code.visualstudio.com/) project configurations and utilities for enabling embedded development for [Analog Device's MSDK](https://github.com/analogdevicesinc/msdk) and the [MAX32xxx/MAX78xxx microcontrollers](https://www.analog.com/en/product-category/microcontrollers.html). + +The following features are supported: + +* Code editing with intellisense down to the register level +* Code compilation with the ability to easily re-target a project for different microcontrollers and boards +* Flashing programs +* GUI and command-line debugging + +## Dependencies + +* [Visual Studio Code](https://code.visualstudio.com/) + * [C/C++ VSCode Extension](https://marketplace.visualstudio.com/items?itemName=ms-vscode.cpptools) + * [Cortex-Debug Extension](https://marketplace.visualstudio.com/items?itemName=marus25.cortex-debug) +* [Analog Devices MSDK](https://analogdevicesinc.github.io/msdk/) + +## Installation + +Install the MSDK, then set `"MAXIM_PATH"` in your _user_ VS Code settings. + +See [Getting Started with Visual Studio Code](https://analogdevicesinc.github.io/msdk/USERGUIDE/#getting-started-with-visual-studio-code) in the MSDK User Guide for detailed instructions. + +## Usage + +See the [MSDK User Guide](https://analogdevicesinc.github.io/msdk/USERGUIDE/#visual-studio-code) for detailed usage info. + +## Issue Tracker + +Bug reports, feature requests, and contributions are welcome via the [issues](https://github.com/analogdevicesinc/VSCode-Maxim/issues) tracker on Github. + +New issues should contain _at minimum_ the following information: + +* Visual Studio Code version #s (see `Help -> About`) +* C/C++ Extension version # +* Target microcontroller and evaluation platform +* The projects `.vscode` folder and `Makefile` (where applicable). Standard compression formats such as `.zip`, `.rar`, `.tar.gz`, etc. are all acceptable. diff --git a/Examples/MAX32657/Bluetooth/BLE5_ctr/.vscode/c_cpp_properties.json b/Examples/MAX32657/Bluetooth/BLE5_ctr/.vscode/c_cpp_properties.json new file mode 100755 index 00000000000..dfbed47b581 --- /dev/null +++ b/Examples/MAX32657/Bluetooth/BLE5_ctr/.vscode/c_cpp_properties.json @@ -0,0 +1,53 @@ +{ + "configurations": [ + { + "name": "Win32", + "includePath": [ + "${default}" + ], + "defines": [ + "${default}" + ], + "intelliSenseMode": "gcc-arm", + "compilerPath": "${config:ARM_GCC_path}/bin/arm-none-eabi-gcc.exe", + "browse": { + "path": [ + "${default}" + ] + } + }, + { + "name": "Linux", + "includePath": [ + "${default}" + ], + "defines": [ + "${default}" + ], + "intelliSenseMode": "gcc-arm", + "compilerPath": "${config:ARM_GCC_path}/bin/arm-none-eabi-gcc", + "browse": { + "path": [ + "${default}" + ] + } + }, + { + "name": "Mac", + "includePath": [ + "${default}" + ], + "defines": [ + "${default}" + ], + "intelliSenseMode": "gcc-arm", + "compilerPath": "${config:ARM_GCC_path}/bin/arm-none-eabi-gcc", + "browse": { + "path": [ + "${default}" + ] + } + } + ], + "version": 4 +} \ No newline at end of file diff --git a/Examples/MAX32657/Bluetooth/BLE5_ctr/.vscode/flash.gdb b/Examples/MAX32657/Bluetooth/BLE5_ctr/.vscode/flash.gdb new file mode 100755 index 00000000000..8f22801a47d --- /dev/null +++ b/Examples/MAX32657/Bluetooth/BLE5_ctr/.vscode/flash.gdb @@ -0,0 +1,17 @@ +define flash_m4 + set architecture armv7e-m + set remotetimeout 10 + target remote | openocd -c "gdb_port pipe;log_output flash.log" -s $arg0/scripts -f interface/$arg1 -f target/$arg2 -c "init; reset halt" + load + compare-sections + monitor reset halt +end + +define flash_m4_run + set architecture armv7e-m + set remotetimeout 10 + target remote | openocd -c "gdb_port pipe;log_output flash.log" -s $arg0/scripts -f interface/$arg1 -f target/$arg2 -c "init; reset halt" + load + compare-sections + monitor resume +end diff --git a/Examples/MAX32657/Bluetooth/BLE5_ctr/.vscode/launch.json b/Examples/MAX32657/Bluetooth/BLE5_ctr/.vscode/launch.json new file mode 100755 index 00000000000..01fe5199048 --- /dev/null +++ b/Examples/MAX32657/Bluetooth/BLE5_ctr/.vscode/launch.json @@ -0,0 +1,133 @@ +{ + "configurations": [ + { + "name": "Debug Arm (Cortex-debug)", + "cwd":"${workspaceRoot}", + "executable": "${workspaceFolder}/build/${config:program_file}", + "loadFiles": ["${workspaceFolder}/build/${config:program_file}"], + "symbolFiles": [{ + "file": "${workspaceFolder}/build/${config:symbol_file}" + }], + "request": "launch", + "type": "cortex-debug", + "servertype": "openocd", + "linux": { + "gdbPath": "${config:ARM_GCC_path}/bin/arm-none-eabi-gdb", + "serverpath": "${config:OCD_path}/openocd", + }, + "windows": { + "gdbPath": "${config:ARM_GCC_path}/bin/arm-none-eabi-gdb.exe", + "serverpath": "${config:OCD_path}/openocd.exe", + }, + "osx": { + "gdbPath": "${config:ARM_GCC_path}/bin/arm-none-eabi-gdb", + "serverpath": "${config:OCD_path}/openocd", + }, + "searchDir": ["${config:OCD_path}/scripts"], + "configFiles": ["interface/${config:M4_OCD_interface_file}", "target/${config:M4_OCD_target_file}"], + "interface": "swd", + "runToEntryPoint": "main", + "svdFile": "${config:MAXIM_PATH}/Libraries/CMSIS/Device/Maxim/${config:target}/Include/${config:target}.svd" + }, + { + "name": "GDB (Arm M4)", + "type": "cppdbg", + "request": "launch", + "program": "${workspaceFolder}/build/${config:program_file}", + "args": [], + "stopAtEntry": true, + "cwd": "${workspaceFolder}", + "environment": [], + "externalConsole": false, + "MIMode": "gdb", + "linux": { + "miDebuggerPath": "${config:ARM_GCC_path}/bin/arm-none-eabi-gdb", + "debugServerPath": "${config:OCD_path}/openocd", + }, + "windows": { + "miDebuggerPath": "${config:ARM_GCC_path}/bin/arm-none-eabi-gdb.exe", + "debugServerPath": "${config:OCD_path}/openocd.exe", + }, + "osx": { + "miDebuggerPath": "${config:ARM_GCC_path}/bin/arm-none-eabi-gdb", + "debugServerPath": "${config:OCD_path}/bin/openocd", + }, + "logging": { + "exceptions": true, + "trace": false, + "traceResponse": false, + "engineLogging": false + }, + "miDebuggerServerAddress": "localhost:3333", + "debugServerArgs": "-s ${config:OCD_path}/scripts -f interface/${config:M4_OCD_interface_file} -f target/${config:M4_OCD_target_file} -c \"init; reset halt\"", + "serverStarted": "Info : Listening on port 3333 for gdb connections", + "filterStderr": true, + "targetArchitecture": "arm", + "customLaunchSetupCommands": [ + {"text":"-list-features"} + ], + "setupCommands": [ + { "text":"set logging overwrite on"}, + { "text":"set logging file debug-arm.log"}, + { "text":"set logging on"}, + { "text":"cd ${workspaceFolder}" }, + { "text":"exec-file build/${config:program_file}" }, + { "text":"symbol-file build/${config:symbol_file}" }, + { "text":"target remote localhost:3333" }, + { "text":"monitor reset halt" }, + { "text":"set $pc=Reset_Handler"}, + { "text":"b main" } + ] + }, + { + "name": "GDB (RISC-V)", + "type": "cppdbg", + "request": "launch", + "program": "${workspaceFolder}/buildrv/${config:program_file}", + "args": [], + "stopAtEntry": false, + "cwd": "${workspaceFolder}", + "environment": [], + "externalConsole": false, + "MIMode": "gdb", + "linux": { + "miDebuggerPath": "${config:xPack_GCC_path}/bin/riscv-none-elf-gdb", + "debugServerPath": "${config:OCD_path}/openocd", + }, + "windows": { + "miDebuggerPath": "${config:xPack_GCC_path}/bin/riscv-none-elf-gdb.exe", + "debugServerPath": "${config:OCD_path}/openocd.exe", + }, + "osx": { + "miDebuggerPath": "${config:xPack_GCC_path}/bin/riscv-none-elf-gdb", + "debugServerPath": "${config:OCD_path}/bin/openocd", + }, + "logging": { + "exceptions": true, + "trace": false, + "traceResponse": false, + "engineLogging": false + }, + "miDebuggerServerAddress": "localhost:3334", + "debugServerArgs": "-c \"gdb_port 3334\" -s ${config:OCD_path}/scripts -f interface/${config:RV_OCD_interface_file} -f target/${config:RV_OCD_target_file}", + "serverStarted": "Info : Listening on port 3334 for gdb connections", + "filterStderr": true, + "customLaunchSetupCommands": [ + {"text":"-list-features"} + ], + "targetArchitecture": "arm", + "setupCommands": [ + { "text":"set logging overwrite on"}, + { "text":"set logging file debug-riscv.log"}, + { "text":"set logging on"}, + { "text":"cd ${workspaceFolder}" }, + { "text": "set architecture riscv:rv32", "ignoreFailures": false }, + { "text":"exec-file build/${config:program_file}", "ignoreFailures": false }, + { "text":"symbol-file buildrv/${config:symbol_file}", "ignoreFailures": false }, + { "text":"target remote localhost:3334" }, + { "text":"b main" }, + { "text": "set $pc=Reset_Handler","ignoreFailures": false } + ] + } + ] +} diff --git a/Examples/MAX32657/Bluetooth/BLE5_ctr/.vscode/settings.json b/Examples/MAX32657/Bluetooth/BLE5_ctr/.vscode/settings.json new file mode 100755 index 00000000000..fc871e1f90a --- /dev/null +++ b/Examples/MAX32657/Bluetooth/BLE5_ctr/.vscode/settings.json @@ -0,0 +1,101 @@ +{ + "terminal.integrated.env.windows": { + "Path":"${config:OCD_path};${config:ARM_GCC_path}/bin;${config:xPack_GCC_path}/bin;${config:MSYS_path}/usr/bin;${config:Make_path};${env:PATH}", + "MAXIM_PATH":"${config:MAXIM_PATH}" + }, + "terminal.integrated.defaultProfile.windows": "Command Prompt", + + "terminal.integrated.env.linux": { + "PATH":"${config:OCD_path}:${config:ARM_GCC_path}/bin:${config:xPack_GCC_path}/bin:${config:Make_path}:${env:PATH}", + "MAXIM_PATH":"${config:MAXIM_PATH}" + }, + "terminal.integrated.env.osx": { + "PATH":"${config:OCD_path}/bin:${config:ARM_GCC_path}/bin:${config:xPack_GCC_path}/bin:${config:Make_path}:${env:PATH}", + "MAXIM_PATH":"${config:MAXIM_PATH}" + }, + + "target":"MAX32657", + "board":"EvKit_V1", + + "project_name":"${workspaceFolderBasename}", + + "program_file":"${config:project_name}.elf", + "symbol_file":"${config:program_file}", + + "M4_OCD_interface_file":"cmsis-dap.cfg", + "M4_OCD_target_file":"max32657.cfg", + "RV_OCD_interface_file":"ftdi/olimex-arm-usb-ocd-h.cfg", + "RV_OCD_target_file":"${config:target}_riscv.cfg", + + "v_Arm_GCC":"10.3", + "v_xPack_GCC":"12.2.0-3.1", + + "OCD_path":"${config:MAXIM_PATH}/Tools/OpenOCD", + "ARM_GCC_path":"${config:MAXIM_PATH}/Tools/GNUTools/${config:v_Arm_GCC}", + "xPack_GCC_path":"${config:MAXIM_PATH}/Tools/xPack/riscv-none-elf-gcc/${config:v_xPack_GCC}", + "Make_path":"${config:MAXIM_PATH}/Tools/GNUTools/Make", + "MSYS_path":"${config:MAXIM_PATH}/Tools/MSYS2", + + "C_Cpp.default.includePath": [ + "${workspaceFolder}", + "${workspaceFolder}/**", + "${config:MAXIM_PATH}/Libraries/Boards/${config:target}/Include", + "${config:MAXIM_PATH}/Libraries/Boards/${config:target}/${config:board}/Include", + "${config:MAXIM_PATH}/Libraries/CMSIS/Device/Maxim/${config:target}/Include", + "${config:MAXIM_PATH}/Libraries/CMSIS/Include", + "${config:ARM_GCC_path}/arm-none-eabi/include", + "${config:ARM_GCC_path}/lib/gcc/arm-none-eabi/${config:v_Arm_GCC}/include", + "${config:MAXIM_PATH}/Libraries/PeriphDrivers/Include/${config:target}", + "${config:MAXIM_PATH}/Libraries/MiscDrivers/Camera", + "${config:MAXIM_PATH}/Libraries/MiscDrivers/Display", + "${config:MAXIM_PATH}/Libraries/MiscDrivers/Display/fonts", + "${config:MAXIM_PATH}/Libraries/MiscDrivers/ExtMemory", + "${config:MAXIM_PATH}/Libraries/MiscDrivers/LED", + "${config:MAXIM_PATH}/Libraries/MiscDrivers/PMIC", + "${config:MAXIM_PATH}/Libraries/MiscDrivers/PushButton", + "${config:MAXIM_PATH}/Libraries/MiscDrivers/Touchscreen", + "${config:MAXIM_PATH}/Libraries/Cordio/ble-host/include", + "${config:MAXIM_PATH}/Libraries/Cordio/ble-host/sources/stack/cfg", + "${config:MAXIM_PATH}/Libraries/Cordio/ble-mesh-apps/include", + "${config:MAXIM_PATH}/Libraries/Cordio/ble-mesh-model/include", + "${config:MAXIM_PATH}/Libraries/Cordio/ble-mesh-profile/include", + "${config:MAXIM_PATH}/Libraries/Cordio/ble-profiles/include", + "${config:MAXIM_PATH}/Libraries/Cordio/controller/include/ble", + "${config:MAXIM_PATH}/Libraries/Cordio/controller/include/common", + "${config:MAXIM_PATH}/Libraries/Cordio/platform/include", + "${config:MAXIM_PATH}/Libraries/Cordio/ble-host/sources/hci/dual_chip", + "${config:MAXIM_PATH}/Libraries/Cordio/ble-host/sources/hci/exactle", + "${config:MAXIM_PATH}/Libraries/Cordio/wsf/include", + "${config:MAXIM_PATH}/Libraries/Cordio/wsf/include/util" + ], + "C_Cpp.default.browse.path": [ + "${workspaceFolder}", + "${config:MAXIM_PATH}/Libraries/Boards/${config:target}/Source", + "${config:MAXIM_PATH}/Libraries/Boards/${config:target}/${config:board}/Source", + "${config:MAXIM_PATH}/Libraries/PeriphDrivers/Source", + "${config:MAXIM_PATH}/Libraries/MiscDrivers/Camera", + "${config:MAXIM_PATH}/Libraries/MiscDrivers/Display", + "${config:MAXIM_PATH}/Libraries/MiscDrivers/Display/fonts", + "${config:MAXIM_PATH}/Libraries/MiscDrivers/LED", + "${config:MAXIM_PATH}/Libraries/MiscDrivers/PMIC", + "${config:MAXIM_PATH}/Libraries/MiscDrivers/PushButton", + "${config:MAXIM_PATH}/Libraries/MiscDrivers/Touchscreen", + "${config:MAXIM_PATH}/Libraries/MiscDrivers", + "${config:MAXIM_PATH}/Libraries/Cordio/ble-apps/sources", + "${config:MAXIM_PATH}/Libraries/Cordio/ble-host/sources", + "${config:MAXIM_PATH}/Libraries/Cordio/ble-mesh-apps/sources", + "${config:MAXIM_PATH}/Libraries/Cordio/ble-mesh-model/sources", + "${config:MAXIM_PATH}/Libraries/Cordio/ble-mesh-profile/sources", + "${config:MAXIM_PATH}/Libraries/Cordio/ble-profiles/sources", + "${config:MAXIM_PATH}/Libraries/Cordio/controller/sources", + "${config:MAXIM_PATH}/Libraries/Cordio/wsf/sources", + "${config:MAXIM_PATH}/Libraries/Cordio/platform/targets/maxim/max32657/sources" + ], + "C_Cpp.default.defines": [ + + ], + "C_Cpp.default.forcedInclude": [ + "${workspaceFolder}/build/project_defines.h" + ] +} + diff --git a/Examples/MAX32657/Bluetooth/BLE5_ctr/.vscode/tasks.json b/Examples/MAX32657/Bluetooth/BLE5_ctr/.vscode/tasks.json new file mode 100755 index 00000000000..e95445e2b3e --- /dev/null +++ b/Examples/MAX32657/Bluetooth/BLE5_ctr/.vscode/tasks.json @@ -0,0 +1,115 @@ +{ + "version": "2.0.0", + "tasks": [ + { + "label": "build", + "type": "shell", + "command": "make -r -j 8 --output-sync=target --no-print-directory TARGET=${config:target} BOARD=${config:board} MAXIM_PATH=${config:MAXIM_PATH} MAKE=make PROJECT=${config:project_name}", + "osx":{ + "command": "source ~/.zshrc && make -r -j 8 --output-sync=target --no-print-directory TARGET=${config:target} BOARD=${config:board} MAXIM_PATH=${config:MAXIM_PATH} MAKE=make PROJECT=${config:project_name}" + }, + "group": "build", + "problemMatcher": [] + }, + { + "label": "clean", + "type": "shell", + "command": "make -j 8 clean --output-sync=target --no-print-directory TARGET=${config:target} BOARD=${config:board} MAXIM_PATH=${config:MAXIM_PATH} MAKE=make PROJECT=${config:project_name}", + "osx":{ + "command": "source ~/.zshrc && make -j 8 clean --output-sync=target --no-print-directory TARGET=${config:target} BOARD=${config:board} MAXIM_PATH=${config:MAXIM_PATH} MAKE=make PROJECT=${config:project_name}" + }, + "group": "build", + "problemMatcher": [] + }, + { + "label": "clean-periph", + "type": "shell", + "command": "make -j 8 distclean --output-sync=target --no-print-directory TARGET=${config:target} BOARD=${config:board} MAXIM_PATH=${config:MAXIM_PATH} MAKE=make PROJECT=${config:project_name}", + "osx":{ + "command": "source ~/.zshrc && make -j 8 distclean --output-sync=target --no-print-directory TARGET=${config:target} BOARD=${config:board} MAXIM_PATH=${config:MAXIM_PATH} MAKE=make PROJECT=${config:project_name}" + }, + "group": "build", + "problemMatcher": [] + }, + { + "label": "flash", + "type": "shell", + "command": "arm-none-eabi-gdb", + "args": [ + "--cd=\"${workspaceFolder}\"", + "--se=\"build/${config:program_file}\"", + "--symbols=build/${config:symbol_file}", + "-x=\"${workspaceFolder}/.vscode/flash.gdb\"", + "--ex=\"flash_m4 ${config:OCD_path} ${config:M4_OCD_interface_file} ${config:M4_OCD_target_file}\"", + "--batch" + ], + "group": "build", + "problemMatcher": [], + "dependsOn":["build"] + }, + { + "label": "flash & run", + "type": "shell", + "command": "arm-none-eabi-gdb", + "args": [ + "--cd=\"${workspaceFolder}\"", + "--se=\"build/${config:program_file}\"", + "--symbols=build/${config:symbol_file}", + "-x=\"${workspaceFolder}/.vscode/flash.gdb\"", + "--ex=\"flash_m4_run ${config:OCD_path} ${config:M4_OCD_interface_file} ${config:M4_OCD_target_file}\"", + "--batch" + ], + "group": "build", + "problemMatcher": [], + "dependsOn":["build"] + }, + { + "label": "erase flash", + "type": "shell", + "command": "openocd", + "args": [ + "-s", "${config:OCD_path}/scripts", + "-f", "interface/${config:M4_OCD_interface_file}", + "-f", "target/${config:M4_OCD_target_file}", + "-c", "\"init; reset halt; max32xxx mass_erase 0;\"", + "-c", "exit" + ], + "group":"build", + "problemMatcher": [], + "dependsOn":[] + }, + { + "label": "openocd (m4)", + "type": "shell", + "command": "openocd", + "args": [ + "-s", + "${config:OCD_path}/scripts", + "-f", + "interface/${config:M4_OCD_interface_file}", + "-f", + "target/${config:M4_OCD_target_file}", + "-c", + "\"init; reset halt\"" + ], + "problemMatcher": [], + "dependsOn":[] + }, + { + "label": "gdb (m4)", + "type": "shell", + "command": "arm-none-eabi-gdb", + "args": [ + "--ex=\"cd ${workspaceFolder}\"", + "--se=\"build/${config:program_file}\"", + "--symbols=build/${config:symbol_file}", + "--ex=\"target remote localhost:3333\"", + "--ex=\"monitor reset halt\"", + "--ex=\"b main\"", + "--ex=\"c\"" + ], + "problemMatcher": [], + "dependsOn":[] + }, + ] +} \ No newline at end of file diff --git a/Examples/MAX32657/Bluetooth/BLE5_ctr/ARM/Abstract.txt b/Examples/MAX32657/Bluetooth/BLE5_ctr/ARM/Abstract.txt new file mode 100644 index 00000000000..095573d468d --- /dev/null +++ b/Examples/MAX32657/Bluetooth/BLE5_ctr/ARM/Abstract.txt @@ -0,0 +1 @@ +BLE BLE5-ctr example diff --git a/Examples/MAX32657/Bluetooth/BLE5_ctr/ARM/BLE.sct b/Examples/MAX32657/Bluetooth/BLE5_ctr/ARM/BLE.sct new file mode 100644 index 00000000000..6781f33a46a --- /dev/null +++ b/Examples/MAX32657/Bluetooth/BLE5_ctr/ARM/BLE.sct @@ -0,0 +1,49 @@ +#! armcc -E -I .\..\ + +#include "sct_config.h" + +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +; /*-Memory Regions-*/ +;#define IROM_start__ 0x00000000 +;#define IROM_size__ 0x00010000 +;#define IFLASH_start__ 0x10000000 +;#define IFLASH_size__ 0x00080000 +;#define CODE_size__ 0x00077FFF +;#define PAL_NVM_DB_START__ 0x10078000 +;#define PAL_NVM_SIZE 0x00008000 +;#define IRAM_start__ 0x20000000 +;#define IRAM_size__ 0x00020000 + + + +; /*-Sizes */ +;#define size_cstack__ 0x6000 +;#define size_heap__ 0x2000 +; /**** End of ICF editor section. ###ICF###*/ + +#define memory mem with size = 4G; + + +LR_IFLASH IFLASH_start__ IFLASH_size__ { ; load region size_region + + ER_IFLASH IFLASH_start__ CODE_size__{ ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + .ANY (+XO) + } + + PAL_NVM PAL_NVM_DB_START__ PAL_NVM_SIZE { ; RW data + .ANY (+RO) + } + + RW_IRAM1 IRAM_start__ IRAM_size__ { ; RW data + .ANY (+RW +ZI) + } + + + +} \ No newline at end of file diff --git a/Examples/MAX32657/Bluetooth/BLE5_ctr/ARM/BTLE_BLE5_ctr.uvoptx b/Examples/MAX32657/Bluetooth/BLE5_ctr/ARM/BTLE_BLE5_ctr.uvoptx new file mode 100644 index 00000000000..58b51355f48 --- /dev/null +++ b/Examples/MAX32657/Bluetooth/BLE5_ctr/ARM/BTLE_BLE5_ctr.uvoptx @@ -0,0 +1,268 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Flash Debug + 0x4 + ARM-ADS + + 96000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + CMSIS_AGDI + -X"CMSIS-DAP v1" -U0409170241ffcce80000000000000000 -O238 -S10 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO23 -FD20000000 -FC1000 -FN1 -FF0MAX32657.FLM -FS010000000 -FL0100000 -FP0($$Device:MAX32657$Flash\MAX32657.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 1 + 1 + 2 + 2000000 + + + + + + Source + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + ..\main.c + main.c + 0 + 0 + + + 1 + 2 + 5 + 0 + 0 + 0 + .\Abstract.txt + Abstract.txt + 0 + 0 + + + + + ::BSP + 0 + 0 + 0 + 1 + + + + ::Bluetooth + 1 + 0 + 0 + 1 + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + + ::Device + 1 + 0 + 0 + 1 + + + diff --git a/Examples/MAX32657/Bluetooth/BLE5_ctr/ARM/BTLE_BLE5_ctr.uvprojx b/Examples/MAX32657/Bluetooth/BLE5_ctr/ARM/BTLE_BLE5_ctr.uvprojx new file mode 100644 index 00000000000..71b305b6c99 --- /dev/null +++ b/Examples/MAX32657/Bluetooth/BLE5_ctr/ARM/BTLE_BLE5_ctr.uvprojx @@ -0,0 +1,564 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Flash Debug + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 + + + MAX32657:Cortex-M4 + Maxim + Maxim.MAX32657.1.0.0 + http://www.mxim.net/microcontroller/pack/ + IRAM(0x20000000,0x00080000) IROM(0x10000000,0x00100000) CPUTYPE("Cortex-M4") FPU2 CLOCK(96000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + 0 + $$Device:MAX32657$Libraries\Device\Maxim\MAX32657\Include\max32657.h + + + + + + + + + + $$Device:MAX32657$SVD\MAX32657\max32657.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + BLE_BLE5_ctr + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DCM.DLL + -pCM4 + SARMCM3.DLL + + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 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WSF_ASSERT_ENABLED=0 HCI_UART=0 TERMINAL_UART=2 USER_UART=1 BB_CLK_RATE_HZ=1000000 LCTR_CONN_NO_TIFS_REASSEMBLY=1 CHCI_TR_UART=1 UART_BAUD=115200 UART_HWFC=0 BB_ENABLE_INLINE_ENC_TX=1 BB_ENABLE_INLINE_DEC_RX=1 PAL_MAX_RTC_COUNTER_VAL=0xFFFFFFFF LL_WW_RX_DEVIATION_USEC=0 BOARD=EvKit_V1 TARGET=32657 TARGET_REV=0x4131 + + ..\..\BLE5-ctr + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x10000000 + 0x20000000 + + .\BLE.sct + + + + + + + + + + + Source + + + main.c + 1 + ..\main.c + + + Abstract.txt + 5 + .\Abstract.txt + + + + + ::BSP + + + ::Bluetooth + + + ::CMSIS + + + ::Device + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + --diag_suppress 1295 --diag_suppress 550 --diag_suppress 188 --diag_suppress 546 --diag_suppress 550 --diag_suppress 188 --diag_suppress 111 --diag_suppress 1293 + + + + + + + + RTE\Device\MAX32657\max32657.h + + + + + + RTE\Device\MAX32657\startup_max32657.s + + + + + + RTE\Device\MAX32657\sub_main.c + + + + + + RTE\Device\MAX32657\system_max32657.c + + + + + + RTE\Device\MAX32657_Cortex-M4\max32657.h + + + + + + + + RTE\Device\MAX32657_Cortex-M4\startup_max32657.s + + + + + + + + RTE\Device\MAX32657_Cortex-M4\system_max32657.c + + + + + + + + + + diff --git a/Examples/MAX32657/Bluetooth/BLE5_ctr/ARM/EventRecorderStub.scvd b/Examples/MAX32657/Bluetooth/BLE5_ctr/ARM/EventRecorderStub.scvd new file mode 100644 index 00000000000..2956b296838 --- /dev/null +++ b/Examples/MAX32657/Bluetooth/BLE5_ctr/ARM/EventRecorderStub.scvd @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/Examples/MAX32657/Bluetooth/BLE5_ctr/BLE5_ctr.launch b/Examples/MAX32657/Bluetooth/BLE5_ctr/BLE5_ctr.launch new file mode 100644 index 00000000000..1086436ffb3 --- /dev/null +++ b/Examples/MAX32657/Bluetooth/BLE5_ctr/BLE5_ctr.launch @@ -0,0 +1,62 @@ + + + + + + + + + + + + + + + + + + + + + + + + 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$PROJ_DIR$\RTE\Device\MAX32657_Cortex-M4\startup_max32657.s + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/PeriphDrivers/Source/SYS/sys_me17.c + + + $PROJ_DIR$\RTE\Device\MAX32657_Cortex-M4\system_max32657.c + + + + Maxim Maxim API _Device.SPI_1.0.0 + CMSISPack.Component + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/PeriphDrivers/Source/SPI/spi_me17.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/PeriphDrivers/Source/SPI/spi_reva.c + + + + Maxim Maxim API _Device.GPIO_1.0.0 + CMSISPack.Component + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/PeriphDrivers/Source/GPIO/gpio_common.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/PeriphDrivers/Source/GPIO/gpio_me17.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/PeriphDrivers/Source/GPIO/gpio_reva.c + + + + Maxim Maxim API _Device.FLC_1.0.0 + CMSISPack.Component + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/PeriphDrivers/Source/FLC/flc_common.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/PeriphDrivers/Source/FLC/flc_me17.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/PeriphDrivers/Source/FLC/flc_reva.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/PeriphDrivers/Source/FLC/flc_revb.c + + + + Maxim Maxim API _Device.DMA_1.0.0 + CMSISPack.Component + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/PeriphDrivers/Source/DMA/dma_me17.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/PeriphDrivers/Source/DMA/dma_reva.c + + + + Maxim Maxim API _Device.ADC_1.0.0 + CMSISPack.Component + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/PeriphDrivers/Source/ADC/adc_me17.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/PeriphDrivers/Source/ADC/adc_reva.c + + + + Maxim MAX32657 BSP _BSP.EvKit V1_1.0.0 + CMSISPack.Component + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Boards/MAX32657/EvKit_V1/Source/board.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Boards/MAX32657/Source/led.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Boards/MAX32657/Source/pb.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Boards/MAX32657/Source/stdio.c + + + + Maxim Maxim BTLE _Bluetooth.Bluetooth LE_1.0.0 + CMSISPack.Component + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/ble-profiles/sources/profiles/anpc/anpc_main.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/ble-profiles/sources/af/common/app_db.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/ble-profiles/sources/af/app_disc.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/ble-profiles/sources/af/common/app_hw.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/ble-profiles/sources/af/app_main.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/ble-profiles/sources/af/app_master.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/ble-profiles/sources/af/app_master_ae.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/ble-profiles/sources/af/app_master_leg.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/ble-profiles/sources/af/app_server.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/ble-profiles/sources/af/app_slave.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/ble-profiles/sources/af/app_slave_ae.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/ble-profiles/sources/af/app_slave_leg.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/ble-profiles/sources/af/app_terminal.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/ble-profiles/sources/af/common/app_ui.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/ble-profiles/sources/profiles/atpc/atpc_main.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/ble-profiles/sources/profiles/atps/atps_main.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/ble-host/sources/stack/att/att_eatt.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/ble-host/sources/stack/att/att_main.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/ble-host/sources/stack/att/att_uuid.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/ble-host/sources/stack/att/attc_disc.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/ble-host/sources/stack/att/attc_eatt.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/ble-host/sources/stack/att/attc_main.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/ble-host/sources/stack/att/attc_proc.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/ble-host/sources/stack/att/attc_read.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/ble-host/sources/stack/att/attc_sign.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/ble-host/sources/stack/att/attc_write.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/ble-host/sources/stack/att/atts_ccc.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/ble-host/sources/stack/att/atts_csf.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/ble-host/sources/stack/att/atts_dyn.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/ble-host/sources/stack/att/atts_eatt.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/ble-host/sources/stack/att/atts_ind.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/ble-host/sources/stack/att/atts_main.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/ble-host/sources/stack/att/atts_proc.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/ble-host/sources/stack/att/atts_read.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/ble-host/sources/stack/att/atts_sign.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/ble-host/sources/stack/att/atts_write.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/ble-profiles/sources/profiles/bas/bas_main.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/controller/sources/ble/bb/bb_ble_adv_master.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/controller/sources/ble/bb/bb_ble_adv_master_ae.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/controller/sources/ble/bb/bb_ble_adv_slave.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/controller/sources/ble/bb/bb_ble_adv_slave_ae.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/controller/sources/ble/bb/bb_ble_bis_master.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/controller/sources/ble/bb/bb_ble_bis_slave.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/controller/sources/ble/bb/bb_ble_cis.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/controller/sources/ble/bb/bb_ble_cis_master.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/controller/sources/ble/bb/bb_ble_cis_slave.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/controller/sources/ble/bb/bb_ble_conn.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/controller/sources/ble/bb/bb_ble_conn_master.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/controller/sources/ble/bb/bb_ble_conn_slave.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/controller/sources/ble/bb/bb_ble_dtm.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/controller/sources/ble/bb/bb_ble_main.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/controller/sources/ble/bb/bb_ble_pdufilt.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/controller/sources/ble/bb/bb_ble_periodiclist.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/controller/sources/ble/bb/bb_ble_reslist.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/controller/sources/ble/bb/bb_ble_sniffer.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/controller/sources/ble/bb/bb_ble_whitelist.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/controller/sources/common/bb/bb_main.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/wsf/sources/util/bda.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/ble-profiles/sources/profiles/blpc/blpc_main.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/ble-profiles/sources/profiles/blps/blps_main.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/wsf/sources/util/bstream.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/wsf/sources/util/calc128.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/ble-host/sources/stack/cfg/cfg_stack.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/controller/sources/common/chci/chci_tr.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/ble-profiles/sources/profiles/cpp/cpps_main.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/wsf/sources/util/crc32.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/ble-profiles/sources/profiles/cscp/cscps_main.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/ble-profiles/sources/profiles/dis/dis_main.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/ble-host/sources/stack/dm/dm_adv.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/ble-host/sources/stack/dm/dm_adv_ae.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/ble-host/sources/stack/dm/dm_adv_leg.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/ble-host/sources/stack/dm/dm_bis_master.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/ble-host/sources/stack/dm/dm_bis_slave.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/ble-host/sources/stack/dm/dm_cis.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/ble-host/sources/stack/dm/dm_cis_master.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/ble-host/sources/stack/dm/dm_cis_slave.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/ble-host/sources/stack/dm/dm_cis_sm.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/ble-host/sources/stack/dm/dm_conn.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/ble-host/sources/stack/dm/dm_conn_cte.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/ble-host/sources/stack/dm/dm_conn_master.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/ble-host/sources/stack/dm/dm_conn_master_ae.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/ble-host/sources/stack/dm/dm_conn_master_leg.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/ble-host/sources/stack/dm/dm_conn_slave.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/ble-host/sources/stack/dm/dm_conn_slave_ae.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/ble-host/sources/stack/dm/dm_conn_slave_leg.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/ble-host/sources/stack/dm/dm_conn_sm.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/ble-host/sources/stack/dm/dm_dev.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/ble-host/sources/stack/dm/dm_dev_priv.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/ble-host/sources/stack/dm/dm_main.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/ble-host/sources/stack/dm/dm_past.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/ble-host/sources/stack/dm/dm_phy.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/ble-host/sources/stack/dm/dm_priv.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/ble-host/sources/stack/dm/dm_scan.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/ble-host/sources/stack/dm/dm_scan_ae.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/ble-host/sources/stack/dm/dm_scan_leg.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/ble-host/sources/stack/dm/dm_sec.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/ble-host/sources/stack/dm/dm_sec_lesc.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/ble-host/sources/stack/dm/dm_sec_master.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/ble-host/sources/stack/dm/dm_sec_slave.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/ble-host/sources/stack/dm/dm_sync_ae.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/wsf/sources/util/fcs.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/ble-profiles/sources/profiles/fmpl/fmpl_main.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/ble-profiles/sources/profiles/gap/gap_main.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/ble-profiles/sources/profiles/gatt/gatt_main.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/ble-profiles/sources/profiles/glpc/glpc_main.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/ble-profiles/sources/profiles/glps/glps_db.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/ble-profiles/sources/profiles/glps/glps_main.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/ble-profiles/sources/profiles/sensor/gyro_main.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/ble-host/sources/hci/exactle/hci_cmd.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/ble-host/sources/hci/exactle/hci_cmd_ae.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/ble-host/sources/hci/exactle/hci_cmd_bis.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/ble-host/sources/hci/exactle/hci_cmd_cis.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/ble-host/sources/hci/exactle/hci_cmd_cte.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/ble-host/sources/hci/exactle/hci_cmd_enc.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/ble-host/sources/hci/exactle/hci_cmd_master.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/ble-host/sources/hci/exactle/hci_cmd_master_ae.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/ble-host/sources/hci/exactle/hci_cmd_past.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/ble-host/sources/hci/exactle/hci_cmd_phy.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/ble-host/sources/hci/common/hci_core.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/ble-host/sources/hci/exactle/hci_core_ps.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/ble-host/sources/hci/exactle/hci_evt.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/ble-host/sources/stack/hci/hci_main.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/ble-host/sources/hci/common/hci_tr.c + + + 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${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/controller/sources/ble/init/init_ctr.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/ble-host/sources/stack/l2c/l2c_coc.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/ble-host/sources/stack/l2c/l2c_main.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/ble-host/sources/stack/l2c/l2c_master.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/ble-host/sources/stack/l2c/l2c_slave.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/controller/sources/ble/lctr/lctr_act_adv_master.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/controller/sources/ble/lctr/lctr_act_adv_master_ae.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/controller/sources/ble/lctr/lctr_act_adv_slave.c + + + ${CMSIS_PACK_PATH_Maxim#MAX32657#1.0.0}$\Libraries/Cordio/controller/sources/ble/lctr/lctr_act_adv_slave_ae.c + + + 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version="1.0.0"/> + <file category="sourceC" deviceDependent="1" name="Libraries/PeriphDrivers/Source/SYS/nvic_table.c" version="1.0.0"/> + </component> + <component Cbundle="Maxim API" Cbundleversion="1.0.0" Cclass="Device" Cgroup="Timers" Cvendor="Maxim" Cversion="1.0.0" deviceDependent="1"> + <package name="MAX32657" url="http://www.mxim.net/microcontroller/pack/" vendor="Maxim" version="1.0.0"/> + <file category="sourceC" deviceDependent="1" name="Libraries/PeriphDrivers/Source/TMR/tmr_me17.c" version="1.0.0"/> + <file category="sourceC" deviceDependent="1" name="Libraries/PeriphDrivers/Source/TMR/tmr_revb.c" version="1.0.0"/> + <file category="sourceC" deviceDependent="1" name="Libraries/PeriphDrivers/Source/TMR/tmr_common.c" version="1.0.0"/> + </component> + <component Cbundle="Maxim API" Cbundleversion="1.0.0" Cclass="Device" Cgroup="TRNG" Cvendor="Maxim" Cversion="1.0.0" deviceDependent="1"> + <package name="MAX32657" url="http://www.mxim.net/microcontroller/pack/" vendor="Maxim" version="1.0.0"/> + <file category="sourceC" deviceDependent="1" name="Libraries/PeriphDrivers/Source/TRNG/trng_me17.c" version="1.0.0"/> + <file category="sourceC" deviceDependent="1" name="Libraries/PeriphDrivers/Source/TRNG/trng_revb.c" version="1.0.0"/> + </component> + <component Cbundle="Maxim API" Cbundleversion="1.0.0" Cclass="Device" Cgroup="UART" Cvendor="Maxim" Cversion="1.0.0" deviceDependent="1"> + <package name="MAX32657" url="http://www.mxim.net/microcontroller/pack/" vendor="Maxim" version="1.0.0"/> + <file category="sourceC" deviceDependent="1" name="Libraries/PeriphDrivers/Source/UART/uart_me17.c" version="1.0.0"/> + <file category="sourceC" deviceDependent="1" name="Libraries/PeriphDrivers/Source/UART/uart_revb.c" version="1.0.0"/> + <file category="sourceC" deviceDependent="1" name="Libraries/PeriphDrivers/Source/UART/uart_common.c" version="1.0.0"/> + </component> + <component Cbundle="Maxim API" Cbundleversion="1.0.0" Cclass="Device" Cgroup="WUT" Cvendor="Maxim" Cversion="1.0.0" deviceDependent="1"> + <package name="MAX32657" url="http://www.mxim.net/microcontroller/pack/" vendor="Maxim" version="1.0.0"/> + <file category="sourceC" deviceDependent="1" name="Libraries/PeriphDrivers/Source/WUT/wut_me17.c" version="1.0.0"/> + <file category="sourceC" deviceDependent="1" name="Libraries/PeriphDrivers/Source/WUT/wut_reva.c" version="1.0.0"/> + </component> + </components> + <apis/> +</configuration> + + + diff --git a/Examples/MAX32657/Bluetooth/BLE5_ctr/Makefile b/Examples/MAX32657/Bluetooth/BLE5_ctr/Makefile new file mode 100644 index 00000000000..62fb5aa2561 --- /dev/null +++ b/Examples/MAX32657/Bluetooth/BLE5_ctr/Makefile @@ -0,0 +1,382 @@ +############################################################################### + # + # Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + # Analog Devices, Inc.), + # Copyright (C) 2023-2024 Analog Devices, Inc. + # + # Licensed under the Apache License, Version 2.0 (the "License"); + # you may not use this file except in compliance with the License. + # You may obtain a copy of the License at + # + # http://www.apache.org/licenses/LICENSE-2.0 + # + # Unless required by applicable law or agreed to in writing, software + # distributed under the License is distributed on an "AS IS" BASIS, + # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + # See the License for the specific language governing permissions and + # limitations under the License. + # + ############################################################################## + +# ** Readme! ** +# Don't edit this file! This is the core Makefile for a MaximSDK +# project. The available configuration options can be overridden +# in "project.mk", on the command-line, or with system environment +# variables. + +# See https://analogdevicesinc.github.io/msdk/USERGUIDE/#build-system +# for more detailed instructions on how to use this system. + +# The detailed instructions mentioned above are easier to read than +# this file, but the comments found in this file also outline the +# available configuration variables. This file is organized into +# sub-sections, some of which expose config variables. + + +# ******************************************************************************* +# Set the target microcontroller and board to compile for. + +# Every TARGET microcontroller has some Board Support Packages (BSPs) that are +# available for it under the MaximSDK/Libraries/Boards/TARGET folder. The BSP +# that gets selected is MaximSDK/Libraries/Boards/TARGET/BOARD. + +# Configuration Variables: +# - TARGET : Override the default target microcontroller. Ex: TARGET=MAX78000 +# - BOARD : Override the default BSP (case sensitive). Ex: BOARD=EvKit_V1, BOARD=FTHR_RevA + + +ifeq "$(TARGET)" "" +# Default target microcontroller +TARGET := MAX32657 +TARGET_UC := MAX32657 +TARGET_LC := max32657 +else +# "TARGET" has been overridden in the environment or on the command-line. +# We need to calculate an upper and lowercase version of the part number, +# because paths on Linux and MacOS are case-sensitive. +TARGET_UC := $(subst m,M,$(subst a,A,$(subst x,X,$(TARGET)))) +TARGET_LC := $(subst M,m,$(subst A,a,$(subst X,x,$(TARGET)))) +endif + +# Default board. +BOARD ?= EvKit_V1 + +# ******************************************************************************* +# Locate the MaximSDK + +# This Makefile needs to know where to find the MaximSDK, and the MAXIM_PATH variable +# should point to the root directory of the MaximSDK installation. Setting this manually +# is usually only required if you're working on the command-line. + +# If MAXIM_PATH is not specified, we assume the project still lives inside of the MaximSDK +# and move up from this project's original location. + +# Configuration Variables: +# - MAXIM_PATH : Tell this Makefile where to find the MaximSDK. Ex: MAXIM_PATH=C:/MaximSDK + + +ifneq "$(MAXIM_PATH)" "" +# Sanitize MAXIM_PATH for backslashes +MAXIM_PATH := $(subst \,/,$(MAXIM_PATH)) +# Locate some other useful paths... +LIBS_DIR := $(abspath $(MAXIM_PATH)/Libraries) +CMSIS_ROOT := $(LIBS_DIR)/CMSIS +endif + +# ******************************************************************************* +# Include project Makefile. We do this after formulating TARGET, BOARD, and MAXIM_PATH +# in case project.mk needs to reference those values. However, we also include +# this as early as possible in the Makefile so that it can append to or override +# the variables below. + + +PROJECTMK ?= $(abspath ./project.mk) +include $(PROJECTMK) +$(info Loaded project.mk) +# PROJECTMK is also used by implicit rules and other libraries to add project.mk as a watch file + +# ******************************************************************************* +# Final path sanitization and re-calculation. No options here. + +ifeq "$(MAXIM_PATH)" "" +# MAXIM_PATH is still not defined... +DEPTH := ../../../../ +MAXIM_PATH := $(abspath $(DEPTH)) +$(warning Warning: MAXIM_PATH is not set! Set MAXIM_PATH in your environment or in project.mk to clear this warning.) +$(warning Warning: Attempting to use $(MAXIM_PATH) calculated from relative path) +else +# Sanitize MAXIM_PATH for backslashes +MAXIM_PATH := $(subst \,/,$(MAXIM_PATH)) +endif + +# Final recalculation of LIBS_DIR/CMSIS_ROOT +LIBS_DIR := $(abspath $(MAXIM_PATH)/Libraries) +CMSIS_ROOT := $(LIBS_DIR)/CMSIS + +# One final UC/LC check in case user set TARGET in project.mk +TARGET_UC := $(subst m,M,$(subst a,A,$(subst x,X,$(TARGET)))) +TARGET_LC := $(subst M,m,$(subst A,a,$(subst X,x,$(TARGET)))) + +export TARGET +export TARGET_UC +export TARGET_LC +export CMSIS_ROOT +# TODO: Remove dependency on exports for these variables. + +# ******************************************************************************* +# Set up search paths, and auto-detect all source code on those paths. + +# The following paths are searched by default, where "./" is the project directory. +# ./ +# |- *.h +# |- *.c +# |-include (optional) +# |- *.h +# |-src (optional) +# |- *.c + +# Configuration Variables: +# - VPATH : Tell this Makefile to search additional locations for source (.c) files. +# You should use the "+=" operator with this option. +# Ex: VPATH += your/new/path +# - IPATH : Tell this Makefile to search additional locations for header (.h) files. +# You should use the "+=" operator with this option. +# Ex: VPATH += your/new/path +# - SRCS : Tell this Makefile to explicitly add a source (.c) file to the build. +# This is really only useful if you want to add a source file that isn't +# on any VPATH, in which case you can add the full path to the file here. +# You should use the "+=" operator with this option. +# Ex: SRCS += your/specific/source/file.c +# - AUTOSEARCH : Set whether this Makefile should automatically detect .c files on +# VPATH and add them to the build. This is enabled by default. Set +# to 0 to disable. If autosearch is disabled, source files must be +# manually added to SRCS. +# Ex: AUTOSEARCH = 0 + + +# Where to find source files for this project. +VPATH += . +VPATH += src +VPATH := $(VPATH) + +# Where to find header files for this project +IPATH += . +IPATH += include +IPATH := $(IPATH) + +AUTOSEARCH ?= 1 +ifeq ($(AUTOSEARCH), 1) +# Auto-detect all C/C++ source files on VPATH +SRCS += $(wildcard $(addsuffix /*.c, $(VPATH))) +SRCS += $(wildcard $(addsuffix /*.cpp, $(VPATH))) +endif + +# Collapse SRCS before passing them on to the next stage +SRCS := $(SRCS) + +# ******************************************************************************* +# Set the output filename + +# Configuration Variables: +# - PROJECT : Override the default output filename. Ex: PROJECT=MyProject + + +# The default value creates a file named after the target micro. Ex: MAX78000.elf +PROJECT ?= $(TARGET_LC) + +# ******************************************************************************* +# Compiler options + +# Configuration Variables: +# - DEBUG : Set DEBUG=1 to build explicitly for debugging. This adds some additional +# symbols and sets -Og as the default optimization level. +# - MXC_OPTIMIZE_CFLAGS : Override the default compiler optimization level. +# Ex: MXC_OPTIMIZE_CFLAGS = -O2 +# - PROJ_CFLAGS : Add additional compiler flags to the build. +# You should use the "+=" operator with this option. +# Ex: PROJ_CFLAGS += -Wextra +# - MFLOAT_ABI : Set the floating point acceleration level. +# The only options are "hard", "soft", or "softfp". +# Ex: MFLOAT_ABI = hard +# - LINKERFILE : Override the default linkerfile. +# Ex: LINKERFILE = customlinkerfile.ld +# - LINKERPATH : Override the default search location for $(LINKERFILE) +# The default search location is $(CMSIS_ROOT)/Device/Maxim/$(TARGET_UC)/Source/GCC +# If $(LINKERFILE) cannot be found at this path, then the root project +# directory will be used as a fallback. + +# Select 'GCC' or 'IAR' compiler +ifeq "$(COMPILER)" "" +COMPILER := GCC +endif + +# Set default compiler optimization levels +ifeq "$(MAKECMDGOALS)" "release" +# Default optimization level for "release" builds (make release) +MXC_OPTIMIZE_CFLAGS ?= -O2 +DEBUG = 0 +endif + +ifeq ($(DEBUG),1) +# Optimizes for debugging as recommended +# by GNU for code-edit-debug cycles +# https://gcc.gnu.org/onlinedocs/gcc/Optimize-Options.html#Optimize-Options +MXC_OPTIMIZE_CFLAGS := -Og +endif + +# Default level if not building for release or explicitly for debug +MXC_OPTIMIZE_CFLAGS ?= -Og + +# Set compiler flags +PROJ_CFLAGS += -Wall # Enable warnings +PROJ_CFLAGS += -DMXC_ASSERT_ENABLE + +# Set hardware floating point acceleration. +# Options are: +# - hard +# - soft +# - softfp (default if MFLOAT_ABI is not set) +MFLOAT_ABI ?= softfp +# MFLOAT_ABI must be exported to other Makefiles +export MFLOAT_ABI + +# This path contains system-level intialization files for the target micro. Add to the build. +VPATH += $(CMSIS_ROOT)/Device/Maxim/$(TARGET_UC)/Source + +# ******************************************************************************* +# Secure Boot Tools (SBT) + +# This section integrates the Secure Boot Tools. It's intended for use with +# microcontrollers that have a secure bootloader. + +# Enabling SBT integration will add some special rules, such as "make sla", "make scpa", etc. + +# Configuration variables: +# SBT : Toggle SBT integration. Set to 1 to enable, or 0 +# to disable +# MAXIM_SBT_DIR : Specify the location of the SBT tool binaries. This defaults to +# Tools/SBT in the MaximSDK. The standalone SBT installer will override +# this via an environment variable. +# TARGET_SEC : Specify the part number to be passed into the SBT. This should match +# the secure variant part #. The default value will depend on TARGET. +# For example, TARGET=MAX32650 will result in TARGET_SEC=MAX32651, and +# the default selection happens in Tools/SBT/SBT-config. +# However, if there are multiple secure part #s for the target +# microcontroller this variable may need to be changed. + +SBT ?= 0 +ifeq ($(SBT), 1) +MAXIM_SBT_DIR ?= $(MAXIM_PATH)/Tools/SBT +MAXIM_SBT_DIR := $(subst \,/,$(MAXIM_SBT_DIR)) +# ^ Must sanitize path for \ on Windows, since this may come from an environment +# variable. + +export MAXIM_SBT_DIR # SBTs must have this environment variable defined to work + +# SBT-config.mk and SBT-rules.mk are included further down this Makefile. + +endif # SBT + +# ******************************************************************************* +# Default goal selection. This section allows you to override the default goal +# that will run if no targets are specified on the command-line. +# (ie. just running 'make' instead of 'make all') + +# Configuration variables: +# .DEFAULT_GOAL : Set the default goal if no targets were specified on the +# command-line +# ** "override" must be used with this variable. ** +# Ex: "override .DEFAULT_GOAL = mygoal" + +ifeq "$(.DEFAULT_GOAL)" "" +ifeq ($(SBT),1) +override .DEFAULT_GOAL := sla +else +override .DEFAULT_GOAL := all +endif +endif + +# Developer note: 'override' is used above for legacy Makefile compatibility. +# gcc.mk/gcc_riscv.mk need to hard-set 'all' internally, so this new system +# uses 'override' to come in over the top without breaking old projects. + +# It's also necessary to explicitly set MAKECMDGOALS... +ifeq "$(MAKECMDGOALS)" "" +MAKECMDGOALS:=$(.DEFAULT_GOAL) +endif + +# Enable colors when --sync-output is used. +# See https://www.gnu.org/software/make/manual/make.html#Terminal-Output (section 13.2) +ifneq ($(MAKE_TERMOUT),) +PROJ_CFLAGS += -fdiagnostics-color=always +endif + +ifneq ($(FORCE_COLOR),) +PROJ_CFLAGS += -fdiagnostics-color=always +endif + +# ******************************************************************************* +# Include SBT config. We need to do this here because it needs to know +# the current MAKECMDGOAL. +ifeq ($(SBT),1) +include $(MAXIM_PATH)/Tools/SBT/SBT-config.mk +endif + +# ******************************************************************************* +# Libraries + +# This section offers "toggle switches" to include or exclude the libraries that +# are available in the MaximSDK. Set a configuration variable to 1 to include the +# library in the build, or 0 to exclude. + +# Each library may also have its own library specific configuration variables. See +# Libraries/libs.mk for more details. + +# Configuration variables: +# - LIB_BOARD : Include the Board-Support Package (BSP) library. (Enabled by default) +# - LIB_PERIPHDRIVERS : Include the peripheral driver library. (Enabled by default) +# - LIB_CMSIS_DSP : Include the CMSIS-DSP library. +# - LIB_CORDIO : Include the Cordio BLE library +# - LIB_FCL : Include the Free Cryptographic Library (FCL) +# - LIB_FREERTOS : Include the FreeRTOS and FreeRTOS-Plus-CLI libraries +# - LIB_LC3 : Include the Low Complexity Communication Codec (LC3) library +# - LIB_LITTLEFS : Include the "little file system" (littleFS) library +# - LIB_LWIP : Include the lwIP library +# - LIB_MAXUSB : Include the MAXUSB library +# - LIB_SDHC : Include the SDHC library + +include $(LIBS_DIR)/libs.mk + + +# ******************************************************************************* +# Rules + +# Include the rules for building for this target. All other makefiles should be +# included before this one. +include $(CMSIS_ROOT)/Device/Maxim/$(TARGET_UC)/Source/$(COMPILER)/$(TARGET_LC).mk + +# Include the rules that integrate the SBTs. SBTs are a special case that must be +# include after the core gcc rules to extend them. +ifeq ($(SBT), 1) +include $(MAXIM_PATH)/Tools/SBT/SBT-rules.mk +endif + + +# Get .DEFAULT_GOAL working. +ifeq "$(MAKECMDGOALS)" "" +MAKECMDGOALS:=$(.DEFAULT_GOAL) +endif + + +all: +# Extend the functionality of the "all" recipe here + $(PREFIX)-size --format=berkeley $(BUILD_DIR)/$(PROJECT).elf + +libclean: + $(MAKE) -f ${PERIPH_DRIVER_DIR}/periphdriver.mk clean.periph + +clean: +# Extend the functionality of the "clean" recipe here + +# The rule to clean out all the build products. +distclean: clean libclean diff --git a/Examples/MAX32657/Bluetooth/BLE5_ctr/README.md b/Examples/MAX32657/Bluetooth/BLE5_ctr/README.md new file mode 100644 index 00000000000..111b9ec84e2 --- /dev/null +++ b/Examples/MAX32657/Bluetooth/BLE5_ctr/README.md @@ -0,0 +1,38 @@ +# Description + +Bluetooth version 5.2 controller, accepts HCI commands via Serial Port. + +Refer to the [BLE5_ctr](../../../../Libraries/Cordio/docs/Applications/BLE5_ctr.md) documentation in the Cordio Library. + +## Software + +### Project Usage + +Universal instructions on building, flashing, and debugging this project can be found in the **[MSDK User Guide](https://analogdevicesinc.github.io/msdk/USERGUIDE/)**. + +### Required Connections +- Connect a USB cable between the PC and the (USB/PWR - UART) connector. +- Use an external USB-to-UART adapter to access HCI UART. Connect a USB cable between the PC or BLE Tester + and USB side of the adapter. Connect UART side of the adapter to board TX,RX and GND header pins. +- Optionally you can reconfigure the UART definitions in board.h to use the on-board USB to UART + adapter for the HCI UART. + +### Project-Specific Build Notes +* Setting `TRACE=1` in [**project.mk**](project.mk) initializes the on-board USB-to-UART adapter for +viewing the trace messages and interacting with the application. Port uses settings: + - Baud : 115200 + - Char size : 8 + - Parity : None + - Stop bits : 1 + - HW Flow Control : No + - SW Flow Control : No +* The HCI serial port is used for HCI communication with BLE controller. Require +external USB-to-UART adapter configured to the following settings: + - Baud : 115200 + - Char size : 8 + - Parity : None + - Stop bits : 1 + - HW Flow Control : No + - SW Flow Control : No +* HCI commands can be send to Controller by BLE tester, or from PC as illustrated in +Tools/Bluetooth/BLE_hci.py. The script has built in help options to describe the usage. diff --git a/Examples/MAX32657/Bluetooth/BLE5_ctr/main.c b/Examples/MAX32657/Bluetooth/BLE5_ctr/main.c new file mode 100644 index 00000000000..60957a6b529 --- /dev/null +++ b/Examples/MAX32657/Bluetooth/BLE5_ctr/main.c @@ -0,0 +1,295 @@ +/*************************************************************************************************/ +/*! + * @file main.c + * @brief Bluetooth version 5.2 controller, accepts HCI commands via Serial Port. + * + * Copyright (c) 2013-2019 Arm Ltd. All Rights Reserved. + * + * Copyright (c) 2019-2020 Packetcraft, Inc. + * + * Portions Copyright (c) 2022-2023 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/*************************************************************************************************/ + +#include "ll_init_api.h" +#include "chci_tr.h" +#include "lhci_api.h" +#include "hci_defs.h" +#include "wsf_assert.h" +#include "wsf_buf.h" +#include "wsf_heap.h" +#include "wsf_timer.h" +#include "wsf_trace.h" +#include "wsf_bufio.h" +#include "wsf_types.h" +#include "wsf_os.h" +#include "wsf_cs.h" +#include "bb_ble_sniffer_api.h" +#include "pal_bb.h" +#include "pal_cfg.h" +#include "mxc_device.h" +#include "uart.h" +#include "nvic_table.h" +#include "board.h" +#include "pal_timer.h" + +#define MAX_PRIORITY ((0x1 << __NVIC_PRIO_BITS) - 1) + +/*! \brief UART TX buffer size */ +#define PLATFORM_UART_TERMINAL_BUFFER_SIZE 2048U + +#define DEFAULT_TX_POWER 0 /* dBm */ + +/************************************************************************************************** + Global Variables +**************************************************************************************************/ + +/*! \brief Persistent BB runtime configuration. */ +static BbRtCfg_t mainBbRtCfg; + +/*! \brief Persistent LL runtime configuration. */ +static LlRtCfg_t mainLlRtCfg; + +/************************************************************************************************** + Functions +**************************************************************************************************/ + +/*************************************************************************************************/ +/*! + * \brief Load runtime configuration. + */ +/*************************************************************************************************/ +static void mainLoadConfiguration(void) +{ + PalBbLoadCfg((PalBbCfg_t *)&mainBbRtCfg); + LlGetDefaultRunTimeCfg(&mainLlRtCfg); + PalCfgLoadData(PAL_CFG_ID_LL_PARAM, &mainLlRtCfg.maxAdvSets, sizeof(LlRtCfg_t) - 9); + PalCfgLoadData(PAL_CFG_ID_BLE_PHY, (uint8_t *)&mainLlRtCfg.phy2mSup, 4); + + /* Set 5.0 requirements. */ + mainLlRtCfg.btVer = BT_VER; + + /* Set the 32k sleep clock accuracy into one of the following bins, default is 20 + HCI_CLOCK_500PPM + HCI_CLOCK_250PPM + HCI_CLOCK_150PPM + HCI_CLOCK_100PPM + HCI_CLOCK_75PPM + HCI_CLOCK_50PPM + HCI_CLOCK_30PPM + HCI_CLOCK_20PPM + */ + mainBbRtCfg.clkPpm = 20; + + /* Set the default connection power level */ + mainLlRtCfg.defTxPwrLvl = DEFAULT_TX_POWER; + + /* Adjust the extended advertising and ISO settings */ + mainLlRtCfg.maxAdvSets = 2; + mainLlRtCfg.maxAdvReports = 4; + mainLlRtCfg.numIsoTxBuf = 8; + mainLlRtCfg.maxCis = 2; + mainLlRtCfg.maxBis = 2; +} + +/*************************************************************************************************/ +/*! + * \brief Initialize WSF. + */ +/*************************************************************************************************/ +static void mainWsfInit(void) +{ + uint32_t llmemUsed, memUsed; + + mainLoadConfiguration(); + + /* +12 for message headroom, + 2 event header, +255 maximum parameter length. */ + const uint16_t maxRptBufSize = 12 + 2 + 255; + + /* +12 for message headroom, +ISO Data Load, +4 for header. */ + const uint16_t dataBufSize = + 12 + HCI_ISO_DL_MAX_LEN + mainLlRtCfg.maxAclLen + 4 + BB_DATA_PDU_TAILROOM; + + /* Use single pool for data buffers. */ +#if (BT_VER > 9) && INIT_FEAT_ISO + mainLlRtCfg.maxIsoSduLen = mainLlRtCfg.maxAclLen; +#endif + + /* Ensure pool buffers are ordered correctly. */ + WSF_ASSERT(maxRptBufSize < dataBufSize); + + wsfBufPoolDesc_t poolDesc[] = { + { 16, 8 }, + { 32, 4 }, + { 128, mainLlRtCfg.maxAdvReports }, + { maxRptBufSize, mainLlRtCfg.maxAdvReports }, /* Extended reports. */ + { dataBufSize, mainLlRtCfg.numTxBufs + mainLlRtCfg.numRxBufs + mainLlRtCfg.numIsoTxBuf + + mainLlRtCfg.numIsoRxBuf } + }; + + const uint8_t numPools = sizeof(poolDesc) / sizeof(poolDesc[0]); + + /* Calculate how much memory we will need for the LL initialization */ + WsfCsEnter(); + + LlInitRtCfg_t llCfg = { + .pBbRtCfg = &mainBbRtCfg, + .wlSizeCfg = 4, + .rlSizeCfg = 4, + .plSizeCfg = 4, + .pLlRtCfg = &mainLlRtCfg, + /* Not significant yet, only being used for memory size requirement calculation. */ + .pFreeMem = WsfHeapGetFreeStartAddress(), + /* Not significant yet, only being used for memory size requirement calculation. */ + .freeMemAvail = WsfHeapCountAvailable() + }; + + llmemUsed = LlInitSetRtCfg(&llCfg); + + WsfCsExit(); + + /* Initial buffer configuration. */ + WsfCsEnter(); + memUsed = WsfBufCalcSize(numPools, poolDesc); + WsfHeapAlloc(memUsed); + WsfBufInit(numPools, poolDesc); + WsfCsExit(); + + WsfOsInit(); + WsfTimerInit(); + +#if (WSF_TRACE_ENABLED == TRUE) + WsfCsEnter(); + WsfHeapAlloc(PLATFORM_UART_TERMINAL_BUFFER_SIZE); + WsfBufIoUartInit(WsfHeapGetFreeStartAddress(), PLATFORM_UART_TERMINAL_BUFFER_SIZE); + WsfCsExit(); + + WsfTraceRegisterHandler(WsfBufIoWrite); + WsfTraceEnable(TRUE); +#endif + + /* Complete the LL initialization */ + WsfCsEnter(); + + /* Allocate the memory */ + WsfHeapAlloc(llmemUsed); + + /* Set the free memory pointers */ + llCfg.pFreeMem = WsfHeapGetFreeStartAddress(); + llCfg.freeMemAvail = WsfHeapCountAvailable(); + + /* Run the initialization with properly set the free memory pointers */ + if (llmemUsed != LlInitControllerInit(&llCfg)) { + WSF_ASSERT(0); + } + + WsfCsExit(); +} + +/*************************************************************************************************/ +/*! + * \brief Check and service tokens (Trace and sniffer). + * + * \return TRUE if there is token pending. + */ +/*************************************************************************************************/ +static bool mainCheckServiceTokens(void) +{ + bool_t eventPending = FALSE; + +#if (WSF_TOKEN_ENABLED == TRUE) || (BB_SNIFFER_ENABLED == TRUE) + eventPending = LhciIsEventPending(); +#endif + +#if WSF_TOKEN_ENABLED == TRUE + /* Allow only a single token to be processed at a time. */ + if (!eventPending) { + eventPending = WsfTokenService(); + } +#endif + +#if (BB_SNIFFER_ENABLED == TRUE) + /* Service one sniffer packet, if in the buffer. */ + if (!eventPending) { + eventPending = LhciSnifferHandler(); + } +#endif + + return eventPending; +} + +/*************************************************************************************************/ +/*! + * \brief Adjust interrupt priorities to let HCI UART interrupt have second highest after PAL timer + * + * \return None + */ +/*************************************************************************************************/ +void setInterruptPriority(void) +{ + /* Interrupts using FreeRTOS functions must have priorities between MAX_PRIORITY and + configMAX_SYSCALL_INTERRUPT_PRIORITY, lower priority number is higher priority */ + + /* Setup BLE hardware interrupt priorities */ + NVIC_SetPriority(BTLE_TX_DONE_IRQn, (MAX_PRIORITY - 2)); + NVIC_SetPriority(BTLE_RX_RCVD_IRQn, (MAX_PRIORITY - 2)); + NVIC_SetPriority(BTLE_RX_ENG_DET_IRQn, (MAX_PRIORITY - 2)); + NVIC_SetPriority(BTLE_SFD_DET_IRQn, (MAX_PRIORITY - 2)); + NVIC_SetPriority(BTLE_SFD_TO_IRQn, (MAX_PRIORITY - 2)); + NVIC_SetPriority(BTLE_GP_EVENT_IRQn, (MAX_PRIORITY - 2)); + NVIC_SetPriority(BTLE_CFO_IRQn, (MAX_PRIORITY - 2)); + NVIC_SetPriority(BTLE_SIG_DET_IRQn, (MAX_PRIORITY - 2)); + NVIC_SetPriority(BTLE_AGC_EVENT_IRQn, (MAX_PRIORITY - 2)); + NVIC_SetPriority(BTLE_RFFE_SPIM_IRQn, (MAX_PRIORITY - 2)); + NVIC_SetPriority(BTLE_TX_AES_IRQn, (MAX_PRIORITY - 2)); + NVIC_SetPriority(BTLE_RX_AES_IRQn, (MAX_PRIORITY - 2)); + NVIC_SetPriority(BTLE_INV_APB_ADDR_IRQn, (MAX_PRIORITY - 2)); + NVIC_SetPriority(BTLE_IQ_DATA_VALID_IRQn, (MAX_PRIORITY - 2)); + + /* Setup scheduler timer priorities */ + NVIC_SetPriority(TMR0_IRQn, (MAX_PRIORITY - 1)); + NVIC_SetPriority(TMR1_IRQn, (MAX_PRIORITY - 1)); + + NVIC_SetPriority(WUT0_IRQn, (MAX_PRIORITY - 1)); + NVIC_SetPriority(WUT1_IRQn, (MAX_PRIORITY - 1)); + + /* Setup additional peripheral timer priorities */ + NVIC_SetPriority(UART_IRQn, (MAX_PRIORITY - 0)); + + NVIC_SetPriority(GPIO0_IRQn, (MAX_PRIORITY - 0)); +} +/*************************************************************************************************/ +/*! + * \brief Main entry point. + */ +/*************************************************************************************************/ +int main(void) +{ + mainWsfInit(); + + bdAddr_t bdAddr; + PalCfgLoadData(PAL_CFG_ID_BD_ADDR, bdAddr, sizeof(bdAddr_t)); + /* Coverity[uninit_use_in_call] */ + LlSetBdAddr((uint8_t *)&bdAddr); + LlSetAdvTxPower(DEFAULT_TX_POWER); + + WsfOsRegisterSleepCheckFunc(mainCheckServiceTokens); + WsfOsRegisterSleepCheckFunc(ChciTrService); + setInterruptPriority(); + WsfOsEnterMainLoop(); + + /* Does not return. */ + return 0; +} diff --git a/Examples/MAX32657/Bluetooth/BLE5_ctr/project.mk b/Examples/MAX32657/Bluetooth/BLE5_ctr/project.mk new file mode 100644 index 00000000000..e41ee807593 --- /dev/null +++ b/Examples/MAX32657/Bluetooth/BLE5_ctr/project.mk @@ -0,0 +1,40 @@ +############################################################################### + # + # Copyright (C) 2024 Analog Devices, Inc. + # + # Licensed under the Apache License, Version 2.0 (the "License"); + # you may not use this file except in compliance with the License. + # You may obtain a copy of the License at + # + # http://www.apache.org/licenses/LICENSE-2.0 + # + # Unless required by applicable law or agreed to in writing, software + # distributed under the License is distributed on an "AS IS" BASIS, + # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + # See the License for the specific language governing permissions and + # limitations under the License. + # + ############################################################################## +# This file can be used to set build configuration +# variables. These variables are defined in a file called +# "Makefile" that is located next to this one. + +# For instructions on how to use this system, see +# https://analogdevicesinc.github.io/msdk/USERGUIDE/#build-system + +# ********************************************************** + +# Enable Cordio library +LIB_CORDIO = 1 + +CORDIO_DIR = $(LIBS_DIR)/Packetcraft-ADI +RF_PHY_DIR = $(LIBS_DIR)/RF-PHY + +# Cordio library options +BLE_HOST = 0 +BLE_CONTROLLER = 1 + +# TRACE option +# Set to 0 to disable +# Set to 2 to enable serial port trace messages +TRACE = 2 diff --git a/Libraries/libs.mk b/Libraries/libs.mk index 0e2c97e7a2f..121f83a9f53 100644 --- a/Libraries/libs.mk +++ b/Libraries/libs.mk @@ -71,9 +71,13 @@ endif # Cordio (Disabled by default) # ************************ LIB_CORDIO ?= 0 -CODED_PHY_DEMO ?= 0 -INIT_EXTENDED ?= 0 ifeq ($(LIB_CORDIO), 1) +# Include extended advertising features +INIT_EXTENDED ?= 0 + +# Default directory for libphy +LIB_PHY_DIR ?= $(LIBS_DIR)/BlePhy + # Include the Cordio Library CORDIO_DIR ?= $(LIBS_DIR)/Cordio include $(CORDIO_DIR)/platform/targets/maxim/build/cordio_lib.mk @@ -83,52 +87,34 @@ ifeq ($(INIT_EXTENDED),1) PROJ_CFLAGS += -DINIT_EXTENDED=1 endif -CHIP_REVISION ?= b -export CHIP_REVISION - -# for CHIP_REVISION a *********************************************** -ifeq ($(CHIP_REVISION),a) +# Default libphy ifeq ($(RISCV_CORE),) - ifeq ($(MFLOAT_ABI),hard) -LIBS += $(LIBS_DIR)/BlePhy/$(CHIP_UC)/libphy_a1_hard.a +LIB_PHY = $(LIB_PHY_DIR)/$(CHIP_UC)/libphy_hard.a else -LIBS += $(LIBS_DIR)/BlePhy/$(CHIP_UC)/libphy_a1.a +LIB_PHY = $(LIB_PHY_DIR)/$(CHIP_UC)/libphy.a endif - else -LIBS += $(LIBS_DIR)/BlePhy/$(CHIP_UC)/libphy_a1_riscv.a +LIB_PHY = $(LIB_PHY_DIR)/$(CHIP_UC)/libphy_riscv.a endif -#********************************************************************* - -# for CHIP_REVISION b *************************************************** -else ifeq ($(CHIP_REVISION),b) - - +# libphy for MAX32655 A1 +ifeq ($(TARGET),MAX32655) +ifeq ($(TARGET_REV),0x4131) ifeq ($(RISCV_CORE),) - ifeq ($(MFLOAT_ABI),hard) -LIBS += $(LIBS_DIR)/BlePhy/$(CHIP_UC)/libphy_hard.a +LIB_PHY = $(LIB_PHY_DIR)/$(CHIP_UC)/libphy_a1_hard.a else -LIBS += $(LIBS_DIR)/BlePhy/$(CHIP_UC)/libphy.a +LIB_PHY = $(LIB_PHY_DIR)/$(CHIP_UC)/libphy_a1.a endif - else -LIBS += $(LIBS_DIR)/BlePhy/$(CHIP_UC)/libphy_riscv.a +LIB_PHY = $(LIB_PHY_DIR)/$(CHIP_UC)/libphy_a1_riscv.a endif -#************************************************************************** endif - -#********************************************************************* - - -ifeq ($(CODED_PHY_DEMO),1) -PROJ_CFLAGS += -DAPP_CODED_PHY_DEMO=1 -else -PROJ_CFLAGS += -DAPP_CODED_PHY_DEMO=0 endif +LIBS += $(LIB_PHY) + query: query.cordio endif From 7ab2d18a79bc027f2507c0bb6ebbb483d9e6726a Mon Sep 17 00:00:00 2001 From: EricB-ADI <122300463+EricB-ADI@users.noreply.github.com> Date: Thu, 7 Nov 2024 15:51:39 -0600 Subject: [PATCH 23/37] fix(Examples): Fixed PHY selection bug in RF Test (#1254) Co-authored-by: EricB-ADI --- Examples/MAX32655/Bluetooth/RF_Test/main.c | 4 ++++ Examples/MAX32665/Bluetooth/RF_Test/main.c | 4 ++++ Examples/MAX32690/Bluetooth/RF_Test/main.c | 4 ++++ 3 files changed, 12 insertions(+) diff --git a/Examples/MAX32655/Bluetooth/RF_Test/main.c b/Examples/MAX32655/Bluetooth/RF_Test/main.c index e4387d401e0..f2919ceb67c 100644 --- a/Examples/MAX32655/Bluetooth/RF_Test/main.c +++ b/Examples/MAX32655/Bluetooth/RF_Test/main.c @@ -706,6 +706,10 @@ void txTestTask(void *pvParameters) if (testConfig.testType == BLE_TX_TEST) { res = LlEnhancedTxTest(testConfig.channel, packetLen, packetType, phy, 0); } else { + // Transmitters decision if it is S2 or S8. + if (phy == LL_PHY_LE_CODED_S8 || phy == LL_PHY_LE_CODED_S2) { + phy = LL_PHY_LE_CODED; + } res = LlEnhancedRxTest(testConfig.channel, phy, 0, 0); } xTaskResumeAll(); //Restore scheduler diff --git a/Examples/MAX32665/Bluetooth/RF_Test/main.c b/Examples/MAX32665/Bluetooth/RF_Test/main.c index 1659783e480..87cd83fe309 100644 --- a/Examples/MAX32665/Bluetooth/RF_Test/main.c +++ b/Examples/MAX32665/Bluetooth/RF_Test/main.c @@ -709,6 +709,10 @@ void txTestTask(void *pvParameters) if (testConfig.testType == BLE_TX_TEST) { res = LlEnhancedTxTest(testConfig.channel, packetLen, packetType, phy, 0); } else { + // Transmitters decision if it is S2 or S8. + if (phy == LL_PHY_LE_CODED_S8 || phy == LL_PHY_LE_CODED_S2) { + phy = LL_PHY_LE_CODED; + } res = LlEnhancedRxTest(testConfig.channel, phy, 0, 0); } xTaskResumeAll(); //Restore scheduler diff --git a/Examples/MAX32690/Bluetooth/RF_Test/main.c b/Examples/MAX32690/Bluetooth/RF_Test/main.c index a6c78d8b502..05335263ec9 100644 --- a/Examples/MAX32690/Bluetooth/RF_Test/main.c +++ b/Examples/MAX32690/Bluetooth/RF_Test/main.c @@ -710,6 +710,10 @@ void txTestTask(void *pvParameters) if (testConfig.testType == BLE_TX_TEST) { res = LlEnhancedTxTest(testConfig.channel, packetLen, packetType, phy, 0); } else { + // Transmitters decision if it is S2 or S8. + if (phy == LL_PHY_LE_CODED_S8 || phy == LL_PHY_LE_CODED_S2) { + phy = LL_PHY_LE_CODED; + } res = LlEnhancedRxTest(testConfig.channel, phy, 0, 0); } xTaskResumeAll(); //Restore scheduler From ca32bc2ec833cac81662f2d2ea59002f95527c84 Mon Sep 17 00:00:00 2001 From: EricB-ADI <122300463+EricB-ADI@users.noreply.github.com> Date: Fri, 8 Nov 2024 09:07:53 -0600 Subject: [PATCH 24/37] fix(Examples): BLE FreeRTOS Tickless (#1258) Co-authored-by: EricB-ADI --- Libraries/BlePhy/MAX32665/libphy.a | Bin 543138 -> 531176 bytes Libraries/BlePhy/MAX32665/libphy_hard.a | Bin 543094 -> 114324 bytes 2 files changed, 0 insertions(+), 0 deletions(-) diff --git a/Libraries/BlePhy/MAX32665/libphy.a b/Libraries/BlePhy/MAX32665/libphy.a index 7087392eb6c876d5fd4e9b027dbb0b69c3b7c12d..012c56a7d88335b1416aa2a668dc975fb0f63cb7 100644 GIT binary patch delta 152712 zcmb@v2YeLO-Ud8pc6WAmcTy(Frjte>A(Vt3Ac2So2uP74(o29K0YZ-y7Xc}Xhz>HS zAlOk*5Y%uL1r>Y4?zN)Wd%KF|>i0ZnPPpjxec$`t@7rI_KIdP~|NKv#GiT3Cu6Oc3 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zdc$XJSYJa(ANiDH`aXm!tZy^ueEMz$Kdf(MNFTbiukTB^59{k3MBjrkeH%jhaO>-P zKBkXjLca8UC#LU=kUq}zY<_=>d*(Zdi*6q-TV|x~{oA;IH*%%OEc0s}^>InjI(u7$ zn{fHHA$?quWP8EVlb=3*A8f-=2N&7iLO?4w2{++*e~res8UBoS zI4t&B5QM?|qO%ky>O&L~C)mEb7M Date: Fri, 8 Nov 2024 14:05:50 -0600 Subject: [PATCH 25/37] fix(Examples): RF Test (#1260) --- Examples/MAX32655/Bluetooth/RF_Test/main.c | 2 +- Examples/MAX32665/Bluetooth/RF_Test/main.c | 2 +- Examples/MAX32690/Bluetooth/RF_Test/main.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/Examples/MAX32655/Bluetooth/RF_Test/main.c b/Examples/MAX32655/Bluetooth/RF_Test/main.c index f2919ceb67c..dfc79fea45a 100644 --- a/Examples/MAX32655/Bluetooth/RF_Test/main.c +++ b/Examples/MAX32655/Bluetooth/RF_Test/main.c @@ -707,7 +707,7 @@ void txTestTask(void *pvParameters) res = LlEnhancedTxTest(testConfig.channel, packetLen, packetType, phy, 0); } else { // Transmitters decision if it is S2 or S8. - if (phy == LL_PHY_LE_CODED_S8 || phy == LL_PHY_LE_CODED_S2) { + if (phy == LL_TEST_PHY_LE_CODED_S8 || phy == LL_TEST_PHY_LE_CODED_S2) { phy = LL_PHY_LE_CODED; } res = LlEnhancedRxTest(testConfig.channel, phy, 0, 0); diff --git a/Examples/MAX32665/Bluetooth/RF_Test/main.c b/Examples/MAX32665/Bluetooth/RF_Test/main.c index 87cd83fe309..eb3f0453d55 100644 --- a/Examples/MAX32665/Bluetooth/RF_Test/main.c +++ b/Examples/MAX32665/Bluetooth/RF_Test/main.c @@ -710,7 +710,7 @@ void txTestTask(void *pvParameters) res = LlEnhancedTxTest(testConfig.channel, packetLen, packetType, phy, 0); } else { // Transmitters decision if it is S2 or S8. - if (phy == LL_PHY_LE_CODED_S8 || phy == LL_PHY_LE_CODED_S2) { + if (phy == LL_TEST_PHY_LE_CODED_S8 || phy == LL_TEST_PHY_LE_CODED_S2) { phy = LL_PHY_LE_CODED; } res = LlEnhancedRxTest(testConfig.channel, phy, 0, 0); diff --git a/Examples/MAX32690/Bluetooth/RF_Test/main.c b/Examples/MAX32690/Bluetooth/RF_Test/main.c index 05335263ec9..c709d93a23a 100644 --- a/Examples/MAX32690/Bluetooth/RF_Test/main.c +++ b/Examples/MAX32690/Bluetooth/RF_Test/main.c @@ -711,7 +711,7 @@ void txTestTask(void *pvParameters) res = LlEnhancedTxTest(testConfig.channel, packetLen, packetType, phy, 0); } else { // Transmitters decision if it is S2 or S8. - if (phy == LL_PHY_LE_CODED_S8 || phy == LL_PHY_LE_CODED_S2) { + if (phy == LL_TEST_PHY_LE_CODED_S8 || phy == LL_TEST_PHY_LE_CODED_S2) { phy = LL_PHY_LE_CODED; } res = LlEnhancedRxTest(testConfig.channel, phy, 0, 0); From d2480e18f148a307b1e70ce16b07a4d674ff82b9 Mon Sep 17 00:00:00 2001 From: EricB-ADI <122300463+EricB-ADI@users.noreply.github.com> Date: Fri, 8 Nov 2024 15:33:35 -0600 Subject: [PATCH 26/37] feat(Build): Added CXX_STANDARD flag to override default when compiling for C++ (#1259) --- Libraries/CMSIS/Device/Maxim/GCC/gcc.mk | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Libraries/CMSIS/Device/Maxim/GCC/gcc.mk b/Libraries/CMSIS/Device/Maxim/GCC/gcc.mk index 09c3046c596..ebba9d7c636 100644 --- a/Libraries/CMSIS/Device/Maxim/GCC/gcc.mk +++ b/Libraries/CMSIS/Device/Maxim/GCC/gcc.mk @@ -405,10 +405,11 @@ CFLAGS=-mthumb \ # The flags passed to the C++ compiler. CXXFLAGS := $(CFLAGS) +CXX_STANDARD?=17 CXXFLAGS += \ -fno-rtti \ -fno-exceptions \ - -std=c++11 \ + -std=c++$(CXX_STANDARD) # On GCC version > 4.8.0 use the -fno-isolate-erroneous-paths-dereference flag ifeq "$(GCCVERSIONGTEQ4)" "1" From d63fdfa43a279f7187e4e957568a51291b2c954b Mon Sep 17 00:00:00 2001 From: EricB-ADI <122300463+EricB-ADI@users.noreply.github.com> Date: Mon, 11 Nov 2024 13:37:02 -0600 Subject: [PATCH 27/37] fix(PeriphDrivers): Fix SDHC CFG register fields and C++ definitions for MAX32665 (#1264) --- Libraries/CMSIS/Device/Maxim/MAX32665/Include/adc_regs.h | 6 +++++- .../CMSIS/Device/Maxim/MAX32665/Include/aeskeys_regs.h | 6 +++++- Libraries/CMSIS/Device/Maxim/MAX32665/Include/dma_regs.h | 6 +++++- Libraries/CMSIS/Device/Maxim/MAX32665/Include/dvs_regs.h | 6 +++++- Libraries/CMSIS/Device/Maxim/MAX32665/Include/fcr_regs.h | 6 +++++- Libraries/CMSIS/Device/Maxim/MAX32665/Include/flc_regs.h | 6 +++++- Libraries/CMSIS/Device/Maxim/MAX32665/Include/gcr_regs.h | 6 +++++- Libraries/CMSIS/Device/Maxim/MAX32665/Include/gpio_regs.h | 6 +++++- Libraries/CMSIS/Device/Maxim/MAX32665/Include/htmr_regs.h | 6 +++++- Libraries/CMSIS/Device/Maxim/MAX32665/Include/i2c_regs.h | 6 +++++- Libraries/CMSIS/Device/Maxim/MAX32665/Include/icc_regs.h | 6 +++++- Libraries/CMSIS/Device/Maxim/MAX32665/Include/mcr_regs.h | 6 +++++- Libraries/CMSIS/Device/Maxim/MAX32665/Include/owm_regs.h | 6 +++++- Libraries/CMSIS/Device/Maxim/MAX32665/Include/pt_regs.h | 6 +++++- Libraries/CMSIS/Device/Maxim/MAX32665/Include/ptg_regs.h | 6 +++++- Libraries/CMSIS/Device/Maxim/MAX32665/Include/pwrseq_regs.h | 6 +++++- Libraries/CMSIS/Device/Maxim/MAX32665/Include/rpu_regs.h | 6 +++++- Libraries/CMSIS/Device/Maxim/MAX32665/Include/rtc_regs.h | 6 +++++- Libraries/CMSIS/Device/Maxim/MAX32665/Include/sdhc_regs.h | 6 +++++- Libraries/CMSIS/Device/Maxim/MAX32665/Include/sema_regs.h | 6 +++++- Libraries/CMSIS/Device/Maxim/MAX32665/Include/simo_regs.h | 6 +++++- Libraries/CMSIS/Device/Maxim/MAX32665/Include/sir_regs.h | 6 +++++- Libraries/CMSIS/Device/Maxim/MAX32665/Include/smon_regs.h | 6 +++++- Libraries/CMSIS/Device/Maxim/MAX32665/Include/spi_regs.h | 6 +++++- .../CMSIS/Device/Maxim/MAX32665/Include/spixfc_fifo_regs.h | 6 +++++- Libraries/CMSIS/Device/Maxim/MAX32665/Include/spixfc_regs.h | 6 +++++- Libraries/CMSIS/Device/Maxim/MAX32665/Include/spixfm_regs.h | 6 +++++- Libraries/CMSIS/Device/Maxim/MAX32665/Include/spixr_regs.h | 6 +++++- Libraries/CMSIS/Device/Maxim/MAX32665/Include/srcc_regs.h | 6 +++++- Libraries/CMSIS/Device/Maxim/MAX32665/Include/tmr_regs.h | 6 +++++- Libraries/CMSIS/Device/Maxim/MAX32665/Include/tpu_regs.h | 6 +++++- .../CMSIS/Device/Maxim/MAX32665/Include/trimsir_regs.h | 6 +++++- Libraries/CMSIS/Device/Maxim/MAX32665/Include/trng_regs.h | 6 +++++- Libraries/CMSIS/Device/Maxim/MAX32665/Include/uart_regs.h | 6 +++++- Libraries/CMSIS/Device/Maxim/MAX32665/Include/usbhs_regs.h | 6 +++++- Libraries/CMSIS/Device/Maxim/MAX32665/Include/wdt_regs.h | 6 +++++- Libraries/CMSIS/Device/Maxim/MAX32665/Include/wut_regs.h | 6 +++++- 37 files changed, 185 insertions(+), 37 deletions(-) diff --git a/Libraries/CMSIS/Device/Maxim/MAX32665/Include/adc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32665/Include/adc_regs.h index 851db41e82d..4e868f4b35f 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32665/Include/adc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32665/Include/adc_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32665/Include/aeskeys_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32665/Include/aeskeys_regs.h index cacc4c83e14..77b16a9fe43 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32665/Include/aeskeys_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32665/Include/aeskeys_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32665/Include/dma_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32665/Include/dma_regs.h index 5e11de9b1c5..771600c50e0 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32665/Include/dma_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32665/Include/dma_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32665/Include/dvs_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32665/Include/dvs_regs.h index fb763033e7e..6b58cce1e23 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32665/Include/dvs_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32665/Include/dvs_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32665/Include/fcr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32665/Include/fcr_regs.h index cd85a68dafe..e2eb3aa7eaf 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32665/Include/fcr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32665/Include/fcr_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32665/Include/flc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32665/Include/flc_regs.h index 7caf5d1df11..964d56ab128 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32665/Include/flc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32665/Include/flc_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32665/Include/gcr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32665/Include/gcr_regs.h index a79038e7576..deeb1bf9f4c 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32665/Include/gcr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32665/Include/gcr_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32665/Include/gpio_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32665/Include/gpio_regs.h index 323b210e3d8..1ca772ebccb 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32665/Include/gpio_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32665/Include/gpio_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32665/Include/htmr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32665/Include/htmr_regs.h index adb5b213ed4..3f55ef697a3 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32665/Include/htmr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32665/Include/htmr_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32665/Include/i2c_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32665/Include/i2c_regs.h index 16868a9120d..a11c1f31945 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32665/Include/i2c_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32665/Include/i2c_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32665/Include/icc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32665/Include/icc_regs.h index b447df86a86..b8a3571c512 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32665/Include/icc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32665/Include/icc_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32665/Include/mcr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32665/Include/mcr_regs.h index 195e91bbcf6..d6d34b3572c 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32665/Include/mcr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32665/Include/mcr_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32665/Include/owm_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32665/Include/owm_regs.h index 2a9f5783221..91065d3b1cf 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32665/Include/owm_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32665/Include/owm_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32665/Include/pt_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32665/Include/pt_regs.h index 93b8d0a9a5f..79bebf39821 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32665/Include/pt_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32665/Include/pt_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32665/Include/ptg_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32665/Include/ptg_regs.h index 1ddd4ea45ad..39253147a8b 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32665/Include/ptg_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32665/Include/ptg_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32665/Include/pwrseq_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32665/Include/pwrseq_regs.h index fde552d2658..3080978e32e 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32665/Include/pwrseq_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32665/Include/pwrseq_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32665/Include/rpu_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32665/Include/rpu_regs.h index e1c3a829efd..3a1457e3c2c 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32665/Include/rpu_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32665/Include/rpu_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32665/Include/rtc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32665/Include/rtc_regs.h index 3a4162c0b55..98191bf08d5 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32665/Include/rtc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32665/Include/rtc_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32665/Include/sdhc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32665/Include/sdhc_regs.h index 123191e1f2f..787fe6cec77 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32665/Include/sdhc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32665/Include/sdhc_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32665/Include/sema_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32665/Include/sema_regs.h index 4696c10f0eb..9f9863edd97 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32665/Include/sema_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32665/Include/sema_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32665/Include/simo_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32665/Include/simo_regs.h index a6910d957c0..99009ac60e0 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32665/Include/simo_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32665/Include/simo_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32665/Include/sir_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32665/Include/sir_regs.h index 70db2add187..83d03fe71ab 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32665/Include/sir_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32665/Include/sir_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32665/Include/smon_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32665/Include/smon_regs.h index 583a3ab6034..8aa946bc7db 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32665/Include/smon_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32665/Include/smon_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32665/Include/spi_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32665/Include/spi_regs.h index 9e509042ea0..75c0b8aff20 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32665/Include/spi_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32665/Include/spi_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32665/Include/spixfc_fifo_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32665/Include/spixfc_fifo_regs.h index 516d037ad70..d0892848ed8 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32665/Include/spixfc_fifo_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32665/Include/spixfc_fifo_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32665/Include/spixfc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32665/Include/spixfc_regs.h index c645b7ca54b..dc166a2be58 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32665/Include/spixfc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32665/Include/spixfc_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32665/Include/spixfm_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32665/Include/spixfm_regs.h index 2f104cf7a7f..1561f50d9a4 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32665/Include/spixfm_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32665/Include/spixfm_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32665/Include/spixr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32665/Include/spixr_regs.h index 0b4350719eb..d564e9e7397 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32665/Include/spixr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32665/Include/spixr_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32665/Include/srcc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32665/Include/srcc_regs.h index cba5aa0b35e..39c1e6e07ce 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32665/Include/srcc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32665/Include/srcc_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32665/Include/tmr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32665/Include/tmr_regs.h index 84c50e19a12..23918e839a4 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32665/Include/tmr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32665/Include/tmr_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32665/Include/tpu_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32665/Include/tpu_regs.h index 90e52976391..57bd07f1968 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32665/Include/tpu_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32665/Include/tpu_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32665/Include/trimsir_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32665/Include/trimsir_regs.h index 0c0bfc79c7c..3b76d5acb0c 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32665/Include/trimsir_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32665/Include/trimsir_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32665/Include/trng_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32665/Include/trng_regs.h index b6dd963bc8b..74a1d8bfc78 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32665/Include/trng_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32665/Include/trng_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32665/Include/uart_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32665/Include/uart_regs.h index 480b1d9d150..d2f3a5d615a 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32665/Include/uart_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32665/Include/uart_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32665/Include/usbhs_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32665/Include/usbhs_regs.h index 6486f7f6eb6..9517fd38c58 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32665/Include/usbhs_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32665/Include/usbhs_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32665/Include/wdt_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32665/Include/wdt_regs.h index b66fbdbe349..fad161369bf 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32665/Include/wdt_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32665/Include/wdt_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32665/Include/wut_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32665/Include/wut_regs.h index 81bff28353e..d89a79a99b7 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32665/Include/wut_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32665/Include/wut_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile From da894c7a86ea50cd73fb1a0ba2f7b65ebfa44e6c Mon Sep 17 00:00:00 2001 From: EricB-ADI <122300463+EricB-ADI@users.noreply.github.com> Date: Mon, 11 Nov 2024 13:45:27 -0600 Subject: [PATCH 28/37] fix(PeriphDrivers): Fix infinite loop check with STOP condition in I2C RevA (#1263) --- Libraries/PeriphDrivers/Source/I2C/i2c_reva.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Libraries/PeriphDrivers/Source/I2C/i2c_reva.c b/Libraries/PeriphDrivers/Source/I2C/i2c_reva.c index c28aa3be13e..c2c2e172aac 100644 --- a/Libraries/PeriphDrivers/Source/I2C/i2c_reva.c +++ b/Libraries/PeriphDrivers/Source/I2C/i2c_reva.c @@ -994,7 +994,7 @@ int MXC_I2C_RevA_MasterTransaction(mxc_i2c_reva_req_t *req) } else { i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_STOP; - while (!(i2c->mstctrl & MXC_F_I2C_REVA_MSTCTRL_STOP)) {} + while ((i2c->mstctrl & MXC_F_I2C_REVA_MSTCTRL_STOP)) {} // Wait for Transaction to finish } From 9bb8b5042bcb70100e9b8449fbba74fbba9801c0 Mon Sep 17 00:00:00 2001 From: EricB-ADI <122300463+EricB-ADI@users.noreply.github.com> Date: Wed, 13 Nov 2024 10:59:37 -0600 Subject: [PATCH 29/37] chore(PeriphDrivers): Fix C++ definitions, Update FCR registers to latest design, and add BLE LDO SVD Enumerations for MAX32657(#1262) Co-authored-by: Woo --- .../Device/Maxim/MAX32657/Include/aes_regs.h | 6 +- .../Maxim/MAX32657/Include/aeskeys_regs.h | 6 +- .../Maxim/MAX32657/Include/boost_regs.h | 6 +- .../Device/Maxim/MAX32657/Include/crc_regs.h | 6 +- .../Device/Maxim/MAX32657/Include/dma_regs.h | 6 +- .../Device/Maxim/MAX32657/Include/fcr_regs.h | 20 +++--- .../Device/Maxim/MAX32657/Include/flc_regs.h | 6 +- .../Device/Maxim/MAX32657/Include/gcr_regs.h | 22 ++++++- .../Device/Maxim/MAX32657/Include/gpio_regs.h | 6 +- .../Device/Maxim/MAX32657/Include/i3c_regs.h | 6 +- .../Device/Maxim/MAX32657/Include/icc_regs.h | 6 +- .../Maxim/MAX32657/Include/max32657.svd | 64 ++++++++++++++----- .../Device/Maxim/MAX32657/Include/mcr_regs.h | 6 +- .../Device/Maxim/MAX32657/Include/mpc_regs.h | 6 +- .../Device/Maxim/MAX32657/Include/nspc_regs.h | 6 +- .../Maxim/MAX32657/Include/pwrseq_regs.h | 6 +- .../Device/Maxim/MAX32657/Include/rstz_regs.h | 6 +- .../Device/Maxim/MAX32657/Include/rtc_regs.h | 6 +- .../Device/Maxim/MAX32657/Include/sir_regs.h | 6 +- .../Device/Maxim/MAX32657/Include/spc_regs.h | 6 +- .../Device/Maxim/MAX32657/Include/spi_regs.h | 6 +- .../Device/Maxim/MAX32657/Include/tmr_regs.h | 6 +- .../Maxim/MAX32657/Include/trimsir_regs.h | 6 +- .../Device/Maxim/MAX32657/Include/trng_regs.h | 6 +- .../Device/Maxim/MAX32657/Include/uart_regs.h | 6 +- .../Device/Maxim/MAX32657/Include/wdt_regs.h | 6 +- .../Device/Maxim/MAX32657/Include/wut_regs.h | 6 +- .../PeriphDrivers/Source/SYS/SVD/fcr_me30.svd | 20 ++---- .../PeriphDrivers/Source/SYS/SVD/gcr_me30.svd | 44 +++++++++++++ 29 files changed, 246 insertions(+), 68 deletions(-) diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/aes_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/aes_regs.h index d76e19f69ad..42275a34f74 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/aes_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/aes_regs.h @@ -48,7 +48,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/aeskeys_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/aeskeys_regs.h index 3e030d4cceb..85a60d26d06 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/aeskeys_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/aeskeys_regs.h @@ -48,7 +48,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/boost_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/boost_regs.h index f501eddd823..05f1eb8a6c5 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/boost_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/boost_regs.h @@ -48,7 +48,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/crc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/crc_regs.h index 8f2430af694..6681c1a942e 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/crc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/crc_regs.h @@ -48,7 +48,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/dma_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/dma_regs.h index 7c196348590..8e6c2b89a53 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/dma_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/dma_regs.h @@ -48,7 +48,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/fcr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/fcr_regs.h index 62b4e1f24ad..3103f26202e 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/fcr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/fcr_regs.h @@ -48,7 +48,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile @@ -114,12 +118,6 @@ typedef struct { * @brief Function Control 0 Register. * @{ */ -#define MXC_F_FCR_CTRL_BTLELDO_RF_POS 0 /**< CTRL_BTLELDO_RF Position */ -#define MXC_F_FCR_CTRL_BTLELDO_RF ((uint32_t)(0x1FUL << MXC_F_FCR_CTRL_BTLELDO_RF_POS)) /**< CTRL_BTLELDO_RF Mask */ - -#define MXC_F_FCR_CTRL_BTLELDO_BB_POS 8 /**< CTRL_BTLELDO_BB Position */ -#define MXC_F_FCR_CTRL_BTLELDO_BB ((uint32_t)(0x1FUL << MXC_F_FCR_CTRL_BTLELDO_BB_POS)) /**< CTRL_BTLELDO_BB Mask */ - #define MXC_F_FCR_CTRL_I3CDGEN0_POS 20 /**< CTRL_I3CDGEN0 Position */ #define MXC_F_FCR_CTRL_I3CDGEN0 ((uint32_t)(0x1UL << MXC_F_FCR_CTRL_I3CDGEN0_POS)) /**< CTRL_I3CDGEN0 Mask */ @@ -215,8 +213,8 @@ typedef struct { * @brief Interrupt Flag Register. * @{ */ -#define MXC_F_FCR_INTFL_ERTOC_RDY_POS 0 /**< INTFL_ERTOC_RDY Position */ -#define MXC_F_FCR_INTFL_ERTOC_RDY ((uint32_t)(0x1UL << MXC_F_FCR_INTFL_ERTOC_RDY_POS)) /**< INTFL_ERTOC_RDY Mask */ +#define MXC_F_FCR_INTFL_ERFO_RDY_POS 0 /**< INTFL_ERFO_RDY Position */ +#define MXC_F_FCR_INTFL_ERFO_RDY ((uint32_t)(0x1UL << MXC_F_FCR_INTFL_ERFO_RDY_POS)) /**< INTFL_ERFO_RDY Mask */ #define MXC_F_FCR_INTFL_FRQCNT_POS 1 /**< INTFL_FRQCNT Position */ #define MXC_F_FCR_INTFL_FRQCNT ((uint32_t)(0x1UL << MXC_F_FCR_INTFL_FRQCNT_POS)) /**< INTFL_FRQCNT Mask */ @@ -229,8 +227,8 @@ typedef struct { * @brief Interrupt Enable Register. * @{ */ -#define MXC_F_FCR_INTEN_ERTOC_RDY_POS 0 /**< INTEN_ERTOC_RDY Position */ -#define MXC_F_FCR_INTEN_ERTOC_RDY ((uint32_t)(0x1UL << MXC_F_FCR_INTEN_ERTOC_RDY_POS)) /**< INTEN_ERTOC_RDY Mask */ +#define MXC_F_FCR_INTEN_ERFO_RDY_POS 0 /**< INTEN_ERFO_RDY Position */ +#define MXC_F_FCR_INTEN_ERFO_RDY ((uint32_t)(0x1UL << MXC_F_FCR_INTEN_ERFO_RDY_POS)) /**< INTEN_ERFO_RDY Mask */ #define MXC_F_FCR_INTEN_FRQCNT_POS 1 /**< INTEN_FRQCNT Position */ #define MXC_F_FCR_INTEN_FRQCNT ((uint32_t)(0x1UL << MXC_F_FCR_INTEN_FRQCNT_POS)) /**< INTEN_FRQCNT Mask */ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/flc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/flc_regs.h index 491a95737d0..1894e55095f 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/flc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/flc_regs.h @@ -48,7 +48,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/gcr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/gcr_regs.h index d49be0aa3be..3c5536ea231 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/gcr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/gcr_regs.h @@ -48,7 +48,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile @@ -571,6 +575,14 @@ typedef struct { #define MXC_F_GCR_BTLELDOCTRL_BB_VSEL_POS 2 /**< BTLELDOCTRL_BB_VSEL Position */ #define MXC_F_GCR_BTLELDOCTRL_BB_VSEL ((uint32_t)(0x3UL << MXC_F_GCR_BTLELDOCTRL_BB_VSEL_POS)) /**< BTLELDOCTRL_BB_VSEL Mask */ +#define MXC_V_GCR_BTLELDOCTRL_BB_VSEL_0_9 ((uint32_t)0x0UL) /**< BTLELDOCTRL_BB_VSEL_0_9 Value */ +#define MXC_S_GCR_BTLELDOCTRL_BB_VSEL_0_9 (MXC_V_GCR_BTLELDOCTRL_BB_VSEL_0_9 << MXC_F_GCR_BTLELDOCTRL_BB_VSEL_POS) /**< BTLELDOCTRL_BB_VSEL_0_9 Setting */ +#define MXC_V_GCR_BTLELDOCTRL_BB_VSEL_1_0 ((uint32_t)0x1UL) /**< BTLELDOCTRL_BB_VSEL_1_0 Value */ +#define MXC_S_GCR_BTLELDOCTRL_BB_VSEL_1_0 (MXC_V_GCR_BTLELDOCTRL_BB_VSEL_1_0 << MXC_F_GCR_BTLELDOCTRL_BB_VSEL_POS) /**< BTLELDOCTRL_BB_VSEL_1_0 Setting */ +#define MXC_V_GCR_BTLELDOCTRL_BB_VSEL_1_1 ((uint32_t)0x2UL) /**< BTLELDOCTRL_BB_VSEL_1_1 Value */ +#define MXC_S_GCR_BTLELDOCTRL_BB_VSEL_1_1 (MXC_V_GCR_BTLELDOCTRL_BB_VSEL_1_1 << MXC_F_GCR_BTLELDOCTRL_BB_VSEL_POS) /**< BTLELDOCTRL_BB_VSEL_1_1 Setting */ +#define MXC_V_GCR_BTLELDOCTRL_BB_VSEL_1_2 ((uint32_t)0x3UL) /**< BTLELDOCTRL_BB_VSEL_1_2 Value */ +#define MXC_S_GCR_BTLELDOCTRL_BB_VSEL_1_2 (MXC_V_GCR_BTLELDOCTRL_BB_VSEL_1_2 << MXC_F_GCR_BTLELDOCTRL_BB_VSEL_POS) /**< BTLELDOCTRL_BB_VSEL_1_2 Setting */ #define MXC_F_GCR_BTLELDOCTRL_RF_EN_POS 4 /**< BTLELDOCTRL_RF_EN Position */ #define MXC_F_GCR_BTLELDOCTRL_RF_EN ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_RF_EN_POS)) /**< BTLELDOCTRL_RF_EN Mask */ @@ -580,6 +592,14 @@ typedef struct { #define MXC_F_GCR_BTLELDOCTRL_RF_VSEL_POS 6 /**< BTLELDOCTRL_RF_VSEL Position */ #define MXC_F_GCR_BTLELDOCTRL_RF_VSEL ((uint32_t)(0x3UL << MXC_F_GCR_BTLELDOCTRL_RF_VSEL_POS)) /**< BTLELDOCTRL_RF_VSEL Mask */ +#define MXC_V_GCR_BTLELDOCTRL_RF_VSEL_0_9 ((uint32_t)0x0UL) /**< BTLELDOCTRL_RF_VSEL_0_9 Value */ +#define MXC_S_GCR_BTLELDOCTRL_RF_VSEL_0_9 (MXC_V_GCR_BTLELDOCTRL_RF_VSEL_0_9 << MXC_F_GCR_BTLELDOCTRL_RF_VSEL_POS) /**< BTLELDOCTRL_RF_VSEL_0_9 Setting */ +#define MXC_V_GCR_BTLELDOCTRL_RF_VSEL_1_0 ((uint32_t)0x1UL) /**< BTLELDOCTRL_RF_VSEL_1_0 Value */ +#define MXC_S_GCR_BTLELDOCTRL_RF_VSEL_1_0 (MXC_V_GCR_BTLELDOCTRL_RF_VSEL_1_0 << MXC_F_GCR_BTLELDOCTRL_RF_VSEL_POS) /**< BTLELDOCTRL_RF_VSEL_1_0 Setting */ +#define MXC_V_GCR_BTLELDOCTRL_RF_VSEL_1_1 ((uint32_t)0x2UL) /**< BTLELDOCTRL_RF_VSEL_1_1 Value */ +#define MXC_S_GCR_BTLELDOCTRL_RF_VSEL_1_1 (MXC_V_GCR_BTLELDOCTRL_RF_VSEL_1_1 << MXC_F_GCR_BTLELDOCTRL_RF_VSEL_POS) /**< BTLELDOCTRL_RF_VSEL_1_1 Setting */ +#define MXC_V_GCR_BTLELDOCTRL_RF_VSEL_1_2 ((uint32_t)0x3UL) /**< BTLELDOCTRL_RF_VSEL_1_2 Value */ +#define MXC_S_GCR_BTLELDOCTRL_RF_VSEL_1_2 (MXC_V_GCR_BTLELDOCTRL_RF_VSEL_1_2 << MXC_F_GCR_BTLELDOCTRL_RF_VSEL_POS) /**< BTLELDOCTRL_RF_VSEL_1_2 Setting */ #define MXC_F_GCR_BTLELDOCTRL_RF_BP_EN_POS 8 /**< BTLELDOCTRL_RF_BP_EN Position */ #define MXC_F_GCR_BTLELDOCTRL_RF_BP_EN ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_RF_BP_EN_POS)) /**< BTLELDOCTRL_RF_BP_EN Mask */ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/gpio_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/gpio_regs.h index 6005fb79828..bd4852c526e 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/gpio_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/gpio_regs.h @@ -48,7 +48,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/i3c_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/i3c_regs.h index 02d2f94eae4..29bf4ed462c 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/i3c_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/i3c_regs.h @@ -48,7 +48,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/icc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/icc_regs.h index e7691d55499..d0f36434632 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/icc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/icc_regs.h @@ -48,7 +48,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.svd b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.svd index ecfcfda3e4c..0beab42655e 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.svd +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.svd @@ -1265,18 +1265,6 @@ 0x00 read-write - - BTLELDO_RF - BTLE LDO RF Trim. - 0 - 5 - - - BTLELDO_BB - BTLE LDO BB Trim. - 8 - 5 - I3CDGEN0 I3C SDA Glitch Filter Enable. @@ -1504,8 +1492,8 @@ read-write - ERTOC_RDY - ERTCO 32K Ready. + ERFO_RDY + ERFO Ready. 0 1 @@ -1524,8 +1512,8 @@ read-write - ERTOC_RDY - ERTCO 32K Ready Interrupt Enable. + ERFO_RDY + ERFO Ready Interrupt Enable. 0 1 @@ -2808,6 +2796,28 @@ Voltage Selection for BB LDO. 2 2 + + + 0_9 + 0.9V + 0 + + + 1_0 + 1.0V + 1 + + + 1_1 + 1.1V + 2 + + + 1_2 + 1.2V + 3 + + RF_EN @@ -2826,6 +2836,28 @@ LDO RF Voltage Setting. 6 2 + + + 0_9 + 0.9V + 0 + + + 1_0 + 1.0V + 1 + + + 1_1 + 1.1V + 2 + + + 1_2 + 1.2V + 3 + + RF_BP_EN diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/mcr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/mcr_regs.h index 039c79405e8..a463cd22cc8 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/mcr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/mcr_regs.h @@ -48,7 +48,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/mpc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/mpc_regs.h index 5944ce49d4e..3d61fa74a14 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/mpc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/mpc_regs.h @@ -48,7 +48,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/nspc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/nspc_regs.h index fd2b7bb166f..070c5e3fbf7 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/nspc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/nspc_regs.h @@ -48,7 +48,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/pwrseq_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/pwrseq_regs.h index 216ede9b620..0ee8c4d5627 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/pwrseq_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/pwrseq_regs.h @@ -48,7 +48,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/rstz_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/rstz_regs.h index 5920d77a627..62f5a9d3c25 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/rstz_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/rstz_regs.h @@ -48,7 +48,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/rtc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/rtc_regs.h index f54cf7b4c25..02232d7035a 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/rtc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/rtc_regs.h @@ -48,7 +48,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/sir_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/sir_regs.h index 8be7861a5a4..2d3a8ae58d1 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/sir_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/sir_regs.h @@ -48,7 +48,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/spc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/spc_regs.h index 69408b70f41..34b24863af7 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/spc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/spc_regs.h @@ -48,7 +48,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/spi_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/spi_regs.h index 75860a7efce..5f8ecaad1f7 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/spi_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/spi_regs.h @@ -48,7 +48,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/tmr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/tmr_regs.h index 61b8e57c73e..94bf7f6dfcb 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/tmr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/tmr_regs.h @@ -48,7 +48,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/trimsir_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/trimsir_regs.h index 63a2682e7a6..8c2fb8dc93a 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/trimsir_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/trimsir_regs.h @@ -48,7 +48,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/trng_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/trng_regs.h index 362dd3551ef..f76ab2eaa73 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/trng_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/trng_regs.h @@ -48,7 +48,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/uart_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/uart_regs.h index 831c2a57deb..98bacabc316 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/uart_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/uart_regs.h @@ -48,7 +48,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/wdt_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/wdt_regs.h index 1e62996109f..99d6039e89a 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/wdt_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/wdt_regs.h @@ -48,7 +48,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/wut_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/wut_regs.h index 37f3861f463..8969ba670af 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/wut_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/wut_regs.h @@ -48,7 +48,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/PeriphDrivers/Source/SYS/SVD/fcr_me30.svd b/Libraries/PeriphDrivers/Source/SYS/SVD/fcr_me30.svd index 005effeba81..e540a715e12 100644 --- a/Libraries/PeriphDrivers/Source/SYS/SVD/fcr_me30.svd +++ b/Libraries/PeriphDrivers/Source/SYS/SVD/fcr_me30.svd @@ -16,18 +16,6 @@ 0x00 read-write - - BTLELDO_RF - BTLE LDO RF Trim. - 0 - 5 - - - BTLELDO_BB - BTLE LDO BB Trim. - 8 - 5 - I3CDGEN0 I3C SDA Glitch Filter Enable. @@ -255,8 +243,8 @@ read-write - ERTOC_RDY - ERTCO 32K Ready. + ERFO_RDY + ERFO Ready. 0 1 @@ -275,8 +263,8 @@ read-write - ERTOC_RDY - ERTCO 32K Ready Interrupt Enable. + ERFO_RDY + ERFO Ready Interrupt Enable. 0 1 diff --git a/Libraries/PeriphDrivers/Source/SYS/SVD/gcr_me30.svd b/Libraries/PeriphDrivers/Source/SYS/SVD/gcr_me30.svd index a580c6ad643..86ff7156d96 100644 --- a/Libraries/PeriphDrivers/Source/SYS/SVD/gcr_me30.svd +++ b/Libraries/PeriphDrivers/Source/SYS/SVD/gcr_me30.svd @@ -896,6 +896,28 @@ Voltage Selection for BB LDO. 2 2 + + + 0_9 + 0.9V + 0 + + + 1_0 + 1.0V + 1 + + + 1_1 + 1.1V + 2 + + + 1_2 + 1.2V + 3 + + RF_EN @@ -914,6 +936,28 @@ LDO RF Voltage Setting. 6 2 + + + 0_9 + 0.9V + 0 + + + 1_0 + 1.0V + 1 + + + 1_1 + 1.1V + 2 + + + 1_2 + 1.2V + 3 + + RF_BP_EN From bde1c220037bfecf1b810ad3ea0bcdbf373ef011 Mon Sep 17 00:00:00 2001 From: Rob Cornall <147884137+rcornall-adi@users.noreply.github.com> Date: Thu, 14 Nov 2024 06:33:47 -0800 Subject: [PATCH 30/37] fix(BLE): Zephyr: enable aes driver when BT selected. (#1268) --- Libraries/zephyr/MAX/Source/MAX32655/CMakeLists.txt | 6 +++++- Libraries/zephyr/MAX/Source/MAX32657/CMakeLists.txt | 6 +++++- 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/Libraries/zephyr/MAX/Source/MAX32655/CMakeLists.txt b/Libraries/zephyr/MAX/Source/MAX32655/CMakeLists.txt index c78155ea5c1..3dcf1822f32 100644 --- a/Libraries/zephyr/MAX/Source/MAX32655/CMakeLists.txt +++ b/Libraries/zephyr/MAX/Source/MAX32655/CMakeLists.txt @@ -176,11 +176,15 @@ zephyr_library_sources( ) endif() -if (CONFIG_CRYPTO_MAX32) +if (CONFIG_CRYPTO_MAX32 OR CONFIG_BT) zephyr_library_sources( ${MSDK_PERIPH_SRC_DIR}/AES/aes_me17.c ${MSDK_PERIPH_SRC_DIR}/AES/aes_revb.c +) +endif() +if (CONFIG_CRYPTO_MAX32) +zephyr_library_sources( ${MSDK_PERIPH_SRC_DIR}/CRC/crc_me17.c ${MSDK_PERIPH_SRC_DIR}/CRC/crc_reva.c ) diff --git a/Libraries/zephyr/MAX/Source/MAX32657/CMakeLists.txt b/Libraries/zephyr/MAX/Source/MAX32657/CMakeLists.txt index b05b325a44d..c037d8a699f 100644 --- a/Libraries/zephyr/MAX/Source/MAX32657/CMakeLists.txt +++ b/Libraries/zephyr/MAX/Source/MAX32657/CMakeLists.txt @@ -142,11 +142,15 @@ zephyr_library_sources( ) endif() -if (CONFIG_CRYPTO_MAX32) +if (CONFIG_CRYPTO_MAX32 OR CONFIG_BT) zephyr_library_sources( ${MSDK_PERIPH_SRC_DIR}/AES/aes_me30.c ${MSDK_PERIPH_SRC_DIR}/AES/aes_revb.c +) +endif() +if (CONFIG_CRYPTO_MAX32) +zephyr_library_sources( ${MSDK_PERIPH_SRC_DIR}/CRC/crc_me30.c ${MSDK_PERIPH_SRC_DIR}/CRC/crc_reva.c ) From f6f5edd4ef0dfccacb2bc409a9a527c08bdb2755 Mon Sep 17 00:00:00 2001 From: Kevin Gillespie Date: Thu, 14 Nov 2024 09:52:07 -0600 Subject: [PATCH 31/37] fix(BLE): Setting dtmRxSyncMs to 10. (#1267) --- .../Cordio/platform/targets/maxim/max32655/sources/pal_cfg.c | 2 +- .../Cordio/platform/targets/maxim/max32665/sources/pal_cfg.c | 2 +- .../Cordio/platform/targets/maxim/max32690/sources/pal_cfg.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/Libraries/Cordio/platform/targets/maxim/max32655/sources/pal_cfg.c b/Libraries/Cordio/platform/targets/maxim/max32655/sources/pal_cfg.c index 6bfe17eb0e7..42bbaeea4ee 100644 --- a/Libraries/Cordio/platform/targets/maxim/max32655/sources/pal_cfg.c +++ b/Libraries/Cordio/platform/targets/maxim/max32655/sources/pal_cfg.c @@ -172,7 +172,7 @@ void palCfgLoadLlParams(uint8_t *pConfig) pCfg->cisSubEvtSpaceDelay = 0; pCfg->maxBig = 0; pCfg->maxBis = 0; - pCfg->dtmRxSyncMs = 1; /* effect PER */ + pCfg->dtmRxSyncMs = 10; /* effect PER */ #endif } diff --git a/Libraries/Cordio/platform/targets/maxim/max32665/sources/pal_cfg.c b/Libraries/Cordio/platform/targets/maxim/max32665/sources/pal_cfg.c index 54094e11f5a..fa9e15b3dac 100644 --- a/Libraries/Cordio/platform/targets/maxim/max32665/sources/pal_cfg.c +++ b/Libraries/Cordio/platform/targets/maxim/max32665/sources/pal_cfg.c @@ -172,7 +172,7 @@ void palCfgLoadLlParams(uint8_t *pConfig) pCfg->cisSubEvtSpaceDelay = 0; pCfg->maxBig = 0; pCfg->maxBis = 0; - pCfg->dtmRxSyncMs = 1; /* effect PER */ + pCfg->dtmRxSyncMs = 10; /* effect PER */ #endif } diff --git a/Libraries/Cordio/platform/targets/maxim/max32690/sources/pal_cfg.c b/Libraries/Cordio/platform/targets/maxim/max32690/sources/pal_cfg.c index 959fde118cd..2432a1b4ea5 100644 --- a/Libraries/Cordio/platform/targets/maxim/max32690/sources/pal_cfg.c +++ b/Libraries/Cordio/platform/targets/maxim/max32690/sources/pal_cfg.c @@ -172,7 +172,7 @@ void palCfgLoadLlParams(uint8_t *pConfig) pCfg->cisSubEvtSpaceDelay = 0; pCfg->maxBig = 0; pCfg->maxBis = 0; - pCfg->dtmRxSyncMs = 1; /* effect PER */ + pCfg->dtmRxSyncMs = 10; /* effect PER */ #endif } From 35e98e279e6eb4fd582aeffd67d6bdce60d918ee Mon Sep 17 00:00:00 2001 From: Sihyung Woo <75494566+sihyung-maxim@users.noreply.github.com> Date: Thu, 14 Nov 2024 10:49:36 -0600 Subject: [PATCH 32/37] feat(workflow): Add MAX32657 and Zephyr labels to labeler workflow (#1269) --- .github/labeler.yml | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/.github/labeler.yml b/.github/labeler.yml index 2dfae66a471..fbe9ed64070 100644 --- a/.github/labeler.yml +++ b/.github/labeler.yml @@ -9,8 +9,7 @@ # # Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by # Analog Devices, Inc.), - # Copyright (C) 2023-2024 Analog Devices, Inc. All Rights Reserved. This software - # is proprietary to Analog Devices, Inc. and its licensors. + # Copyright (C) 2023-2024 Analog Devices, Inc. All Rights Reserved. # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. @@ -73,6 +72,14 @@ - '**/Libraries/PeriphDrivers/max32655_files.mk' - '**/Libraries/PeriphDrivers/Include/MAX32655/**/*' +'MAX32657': +- '**/Examples/MAX32657/**/*' +- '**/*me30*.*' +- '**/Libraries/Boards/MAX32657/**/*' +- '**/Libraries/CMSIS/Device/Maxim/MAX32657/**/*' +- '**/Libraries/PeriphDrivers/max32657_files.mk' +- '**/Libraries/PeriphDrivers/Include/MAX32657/**/*' + 'MAX32660': - '**/Examples/MAX32660/**/*' - '**/*me11*.*' @@ -221,3 +228,6 @@ 'Workflow': - '**/.github/workflows/**/*' - '**/.github/**/*' + +'Zephyr': +- '**/Libraries/zephyr/**/*' From 51f8b115cb3ad0fea6f2df253e67460f030a4178 Mon Sep 17 00:00:00 2001 From: Kevin Gillespie Date: Thu, 14 Nov 2024 10:57:07 -0600 Subject: [PATCH 33/37] fix(CMSIS): Checking for definition of MXC_DMA1. (#1270) --- Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h index 5b38135c1b5..bc0bc07c944 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h @@ -705,7 +705,7 @@ We may want to handle GET_IRQ better... #define MXC_BASE_DMA0 MXC_BASE_DMA0_NS #define MXC_DMA0 MXC_DMA0_NS /* MXC_DMA1 is not defined because Non-Secure Code can only access DMA0. */ -#if MXC_DMA1 +#ifdef MXC_DMA1 #warning "Secure DMA (DMA1) is not accessible from Non-Secure world." #endif From 3eba814816893de7f3d57359fc436b9b8234670e Mon Sep 17 00:00:00 2001 From: EricB-ADI <122300463+EricB-ADI@users.noreply.github.com> Date: Thu, 14 Nov 2024 11:00:41 -0600 Subject: [PATCH 34/37] chore(CMSIS): Generate Registers (#1228) Co-authored-by: sihyung-maxim Co-authored-by: Woo --- .../Maxim/MAX32520/Include/aeskeys_regs.h | 6 +- .../Device/Maxim/MAX32520/Include/ctb_regs.h | 6 +- .../Device/Maxim/MAX32520/Include/dma_regs.h | 8 +- .../Device/Maxim/MAX32520/Include/fcr_regs.h | 6 +- .../Device/Maxim/MAX32520/Include/flc_regs.h | 6 +- .../Device/Maxim/MAX32520/Include/gcr_regs.h | 6 +- .../Device/Maxim/MAX32520/Include/gpio_regs.h | 6 +- .../Device/Maxim/MAX32520/Include/i2c_regs.h | 6 +- .../Device/Maxim/MAX32520/Include/icc_regs.h | 6 +- .../Device/Maxim/MAX32520/Include/mcr_regs.h | 6 +- .../Maxim/MAX32520/Include/pwrseq_regs.h | 6 +- .../Device/Maxim/MAX32520/Include/sfe_regs.h | 6 +- .../Device/Maxim/MAX32520/Include/sir_regs.h | 6 +- .../Device/Maxim/MAX32520/Include/smon_regs.h | 6 +- .../Device/Maxim/MAX32520/Include/spi_regs.h | 6 +- .../Device/Maxim/MAX32520/Include/tmr_regs.h | 6 +- .../Device/Maxim/MAX32520/Include/trng_regs.h | 6 +- .../Device/Maxim/MAX32520/Include/uart_regs.h | 6 +- .../Device/Maxim/MAX32520/Include/wdt_regs.h | 6 +- .../Device/Maxim/MAX32570/Include/adc_regs.h | 25 +- .../Maxim/MAX32570/Include/aeskeys_regs.h | 97 + .../Maxim/MAX32570/Include/cameraif_regs.h | 25 +- .../Device/Maxim/MAX32570/Include/ctb_regs.h | 25 +- .../Device/Maxim/MAX32570/Include/dma_regs.h | 27 +- .../Device/Maxim/MAX32570/Include/emac_regs.h | 25 +- .../Device/Maxim/MAX32570/Include/fcr_regs.h | 25 +- .../Device/Maxim/MAX32570/Include/flc_regs.h | 25 +- .../Device/Maxim/MAX32570/Include/gcr_regs.h | 25 +- .../Device/Maxim/MAX32570/Include/gpio_regs.h | 25 +- .../Device/Maxim/MAX32570/Include/ha_regs.h | 25 +- .../Device/Maxim/MAX32570/Include/htmr_regs.h | 25 +- .../Device/Maxim/MAX32570/Include/i2c_regs.h | 25 +- .../Device/Maxim/MAX32570/Include/icc_regs.h | 25 +- .../Maxim/MAX32570/Include/max32570.svd | 21013 +++++++--------- .../Device/Maxim/MAX32570/Include/mcr_regs.h | 25 +- .../Device/Maxim/MAX32570/Include/owm_regs.h | 25 +- .../Device/Maxim/MAX32570/Include/pt_regs.h | 25 +- .../Device/Maxim/MAX32570/Include/ptg_regs.h | 93 +- .../Maxim/MAX32570/Include/pwrseq_regs.h | 25 +- .../Device/Maxim/MAX32570/Include/rtc_regs.h | 25 +- .../Device/Maxim/MAX32570/Include/sdhc_regs.h | 27 +- .../Device/Maxim/MAX32570/Include/sema_regs.h | 25 +- .../Device/Maxim/MAX32570/Include/sir_regs.h | 25 +- .../Device/Maxim/MAX32570/Include/skbd_regs.h | 25 +- .../Device/Maxim/MAX32570/Include/smon_regs.h | 25 +- .../Device/Maxim/MAX32570/Include/spi_regs.h | 25 +- .../Maxim/MAX32570/Include/spixfc_fifo_regs.h | 25 +- .../Maxim/MAX32570/Include/spixfc_regs.h | 25 +- .../Maxim/MAX32570/Include/spixfm_regs.h | 25 +- .../Maxim/MAX32570/Include/spixr_regs.h | 25 +- .../Device/Maxim/MAX32570/Include/srcc_regs.h | 89 +- .../Device/Maxim/MAX32570/Include/tmr_regs.h | 25 +- .../Maxim/MAX32570/Include/trimsir_regs.h | 25 +- .../Device/Maxim/MAX32570/Include/trng_regs.h | 82 +- .../Device/Maxim/MAX32570/Include/uart_regs.h | 25 +- .../Maxim/MAX32570/Include/usbhs_regs.h | 63 +- .../Device/Maxim/MAX32570/Include/wdt_regs.h | 25 +- .../Device/Maxim/MAX32572/Include/adc_regs.h | 567 +- .../Device/Maxim/MAX32572/Include/aes_regs.h | 224 + .../Maxim/MAX32572/Include/aeskeys_regs.h | 6 +- .../Device/Maxim/MAX32572/Include/ctb_regs.h | 135 +- .../Device/Maxim/MAX32572/Include/dma_regs.h | 134 +- .../Device/Maxim/MAX32572/Include/fcr_regs.h | 231 +- .../Device/Maxim/MAX32572/Include/flc_regs.h | 290 + .../Device/Maxim/MAX32572/Include/gcr_regs.h | 461 +- .../Device/Maxim/MAX32572/Include/gpio_regs.h | 270 +- .../Device/Maxim/MAX32572/Include/htmr_regs.h | 6 +- .../Device/Maxim/MAX32572/Include/i2c_regs.h | 29 +- .../Device/Maxim/MAX32572/Include/i2s_regs.h | 294 + .../Device/Maxim/MAX32572/Include/icc_regs.h | 162 + .../Maxim/MAX32572/Include/max32672.svd | 13165 ++++++++++ .../Device/Maxim/MAX32572/Include/mcr_regs.h | 333 +- .../Maxim/MAX32572/Include/msradc_regs.h | 6 +- .../Device/Maxim/MAX32572/Include/otp_regs.h | 6 +- .../Device/Maxim/MAX32572/Include/pt_regs.h | 6 +- .../Device/Maxim/MAX32572/Include/ptg_regs.h | 6 +- .../Maxim/MAX32572/Include/pwrseq_regs.h | 234 +- .../Device/Maxim/MAX32572/Include/qdec_regs.h | 326 + .../Device/Maxim/MAX32572/Include/rtc_regs.h | 24 +- .../Device/Maxim/MAX32572/Include/scn_regs.h | 6 +- .../Device/Maxim/MAX32572/Include/sema_regs.h | 6 +- .../Device/Maxim/MAX32572/Include/sfcc_regs.h | 6 +- .../Device/Maxim/MAX32572/Include/sir_regs.h | 86 +- .../Device/Maxim/MAX32572/Include/skbd_regs.h | 6 +- .../Device/Maxim/MAX32572/Include/smon_regs.h | 6 +- .../Device/Maxim/MAX32572/Include/spi_regs.h | 86 +- .../Maxim/MAX32572/Include/spixfc_fifo_regs.h | 6 +- .../Maxim/MAX32572/Include/spixfc_regs.h | 6 +- .../Maxim/MAX32572/Include/spixfm_regs.h | 6 +- .../Maxim/MAX32572/Include/sys_aeskeys_regs.h | 113 + .../Device/Maxim/MAX32572/Include/tmr_regs.h | 366 +- .../Maxim/MAX32572/Include/trimsir_regs.h | 69 +- .../Device/Maxim/MAX32572/Include/trng_regs.h | 136 +- .../Device/Maxim/MAX32572/Include/uart_regs.h | 88 +- .../Maxim/MAX32572/Include/usbhs_regs.h | 6 +- .../Maxim/MAX32572/Include/usr_aeskeys_regs.h | 105 + .../Device/Maxim/MAX32572/Include/wdt_regs.h | 12 +- .../Device/Maxim/MAX32650/Include/adc_regs.h | 6 +- .../Maxim/MAX32650/Include/aeskeys_regs.h | 6 +- .../Device/Maxim/MAX32650/Include/bbfc_regs.h | 6 +- .../Device/Maxim/MAX32650/Include/clcd_regs.h | 6 +- .../Device/Maxim/MAX32650/Include/dma_regs.h | 8 +- .../Device/Maxim/MAX32650/Include/emcc_regs.h | 6 +- .../Device/Maxim/MAX32650/Include/flc_regs.h | 6 +- .../Device/Maxim/MAX32650/Include/gcr_regs.h | 6 +- .../Device/Maxim/MAX32650/Include/gpio_regs.h | 6 +- .../Device/Maxim/MAX32650/Include/hpb_regs.h | 6 +- .../Device/Maxim/MAX32650/Include/i2c_regs.h | 6 +- .../Device/Maxim/MAX32650/Include/icc_regs.h | 6 +- .../Maxim/MAX32650/Include/nbbfc_regs.h | 6 +- .../Device/Maxim/MAX32650/Include/owm_regs.h | 6 +- .../Device/Maxim/MAX32650/Include/pt_regs.h | 6 +- .../Device/Maxim/MAX32650/Include/ptg_regs.h | 6 +- .../Maxim/MAX32650/Include/pwrseq_regs.h | 6 +- .../Device/Maxim/MAX32650/Include/rtc_regs.h | 6 +- .../Device/Maxim/MAX32650/Include/sdhc_regs.h | 6 +- .../Device/Maxim/MAX32650/Include/sema_regs.h | 6 +- .../Device/Maxim/MAX32650/Include/sir_regs.h | 6 +- .../Device/Maxim/MAX32650/Include/smon_regs.h | 6 +- .../Device/Maxim/MAX32650/Include/spi_regs.h | 6 +- .../Maxim/MAX32650/Include/spimss_regs.h | 6 +- .../Maxim/MAX32650/Include/spixf_regs.h | 6 +- .../Maxim/MAX32650/Include/spixfc_fifo_regs.h | 6 +- .../Maxim/MAX32650/Include/spixfc_regs.h | 6 +- .../Maxim/MAX32650/Include/spixr_regs.h | 6 +- .../Device/Maxim/MAX32650/Include/tmr_regs.h | 6 +- .../Device/Maxim/MAX32650/Include/tpu_regs.h | 6 +- .../Maxim/MAX32650/Include/trimsir_regs.h | 6 +- .../Device/Maxim/MAX32650/Include/trng_regs.h | 6 +- .../Device/Maxim/MAX32650/Include/uart_regs.h | 6 +- .../Maxim/MAX32650/Include/usbhs_regs.h | 6 +- .../Device/Maxim/MAX32650/Include/wdt_regs.h | 6 +- .../Device/Maxim/MAX32655/Include/adc_regs.h | 6 +- .../Device/Maxim/MAX32655/Include/aes_regs.h | 6 +- .../Maxim/MAX32655/Include/aeskeys_regs.h | 6 +- .../Device/Maxim/MAX32655/Include/crc_regs.h | 10 +- .../Device/Maxim/MAX32655/Include/dma_regs.h | 8 +- .../Device/Maxim/MAX32655/Include/dvs_regs.h | 6 +- .../Device/Maxim/MAX32655/Include/fcr_regs.h | 6 +- .../Device/Maxim/MAX32655/Include/flc_regs.h | 6 +- .../Device/Maxim/MAX32655/Include/gcfr_regs.h | 6 +- .../Device/Maxim/MAX32655/Include/gcr_regs.h | 6 +- .../Device/Maxim/MAX32655/Include/gpio_regs.h | 6 +- .../Device/Maxim/MAX32655/Include/i2c_regs.h | 6 +- .../Device/Maxim/MAX32655/Include/i2s_regs.h | 6 +- .../Device/Maxim/MAX32655/Include/icc_regs.h | 6 +- .../Maxim/MAX32655/Include/lpcmp_regs.h | 14 +- .../Maxim/MAX32655/Include/lpgcr_regs.h | 6 +- .../Maxim/MAX32655/Include/max32655.svd | 12 +- .../Device/Maxim/MAX32655/Include/mcr_regs.h | 6 +- .../Device/Maxim/MAX32655/Include/owm_regs.h | 6 +- .../Device/Maxim/MAX32655/Include/pt_regs.h | 6 +- .../Device/Maxim/MAX32655/Include/ptg_regs.h | 6 +- .../Maxim/MAX32655/Include/pwrseq_regs.h | 6 +- .../Device/Maxim/MAX32655/Include/rtc_regs.h | 6 +- .../Device/Maxim/MAX32655/Include/sema_regs.h | 6 +- .../Device/Maxim/MAX32655/Include/simo_regs.h | 6 +- .../Device/Maxim/MAX32655/Include/sir_regs.h | 6 +- .../Device/Maxim/MAX32655/Include/spi_regs.h | 6 +- .../Device/Maxim/MAX32655/Include/tmr_regs.h | 6 +- .../Maxim/MAX32655/Include/trimsir_regs.h | 6 +- .../Device/Maxim/MAX32655/Include/trng_regs.h | 6 +- .../Device/Maxim/MAX32655/Include/uart_regs.h | 6 +- .../Device/Maxim/MAX32655/Include/wdt_regs.h | 6 +- .../Device/Maxim/MAX32655/Include/wut_regs.h | 6 +- .../Device/Maxim/MAX32660/Include/dma_regs.h | 8 +- .../Device/Maxim/MAX32660/Include/fcr_regs.h | 6 +- .../Device/Maxim/MAX32660/Include/flc_regs.h | 6 +- .../Device/Maxim/MAX32660/Include/gcr_regs.h | 6 +- .../Device/Maxim/MAX32660/Include/gpio_regs.h | 6 +- .../Device/Maxim/MAX32660/Include/i2c_regs.h | 6 +- .../Device/Maxim/MAX32660/Include/icc_regs.h | 6 +- .../Maxim/MAX32660/Include/pwrseq_regs.h | 6 +- .../Device/Maxim/MAX32660/Include/rtc_regs.h | 6 +- .../Device/Maxim/MAX32660/Include/sir_regs.h | 6 +- .../Device/Maxim/MAX32660/Include/spi_regs.h | 6 +- .../Maxim/MAX32660/Include/spimss_regs.h | 6 +- .../Device/Maxim/MAX32660/Include/tmr_regs.h | 6 +- .../Device/Maxim/MAX32660/Include/uart_regs.h | 6 +- .../Device/Maxim/MAX32660/Include/wdt_regs.h | 6 +- .../Device/Maxim/MAX32662/Include/adc_regs.h | 6 +- .../Device/Maxim/MAX32662/Include/aes_regs.h | 6 +- .../Maxim/MAX32662/Include/aeskeys_regs.h | 6 +- .../Device/Maxim/MAX32662/Include/can_regs.h | 6 +- .../Device/Maxim/MAX32662/Include/dma_regs.h | 8 +- .../Device/Maxim/MAX32662/Include/fcr_regs.h | 6 +- .../Device/Maxim/MAX32662/Include/flc_regs.h | 6 +- .../Device/Maxim/MAX32662/Include/gcr_regs.h | 6 +- .../Device/Maxim/MAX32662/Include/gpio_regs.h | 6 +- .../Device/Maxim/MAX32662/Include/i2c_regs.h | 6 +- .../Device/Maxim/MAX32662/Include/i2s_regs.h | 6 +- .../Device/Maxim/MAX32662/Include/icc_regs.h | 6 +- .../Device/Maxim/MAX32662/Include/mcr_regs.h | 6 +- .../Device/Maxim/MAX32662/Include/pt_regs.h | 6 +- .../Device/Maxim/MAX32662/Include/ptg_regs.h | 6 +- .../Maxim/MAX32662/Include/pwrseq_regs.h | 6 +- .../Device/Maxim/MAX32662/Include/rtc_regs.h | 6 +- .../Device/Maxim/MAX32662/Include/sir_regs.h | 6 +- .../Device/Maxim/MAX32662/Include/spi_regs.h | 6 +- .../Device/Maxim/MAX32662/Include/tmr_regs.h | 6 +- .../Maxim/MAX32662/Include/trimsir_regs.h | 6 +- .../Device/Maxim/MAX32662/Include/trng_regs.h | 6 +- .../Device/Maxim/MAX32662/Include/uart_regs.h | 6 +- .../Device/Maxim/MAX32662/Include/wdt_regs.h | 6 +- .../Device/Maxim/MAX32670/Include/aes_regs.h | 6 +- .../Maxim/MAX32670/Include/aeskeys_regs.h | 6 +- .../Device/Maxim/MAX32670/Include/crc_regs.h | 10 +- .../Device/Maxim/MAX32670/Include/dma_regs.h | 8 +- .../Device/Maxim/MAX32670/Include/ecc_regs.h | 6 +- .../Device/Maxim/MAX32670/Include/fcr_regs.h | 6 +- .../Device/Maxim/MAX32670/Include/flc_regs.h | 6 +- .../Device/Maxim/MAX32670/Include/gcr_regs.h | 6 +- .../Device/Maxim/MAX32670/Include/gpio_regs.h | 6 +- .../Device/Maxim/MAX32670/Include/i2c_regs.h | 6 +- .../Device/Maxim/MAX32670/Include/i2s_regs.h | 6 +- .../Device/Maxim/MAX32670/Include/icc_regs.h | 6 +- .../Maxim/MAX32670/Include/max32670.svd | 8 +- .../Device/Maxim/MAX32670/Include/mcr_regs.h | 6 +- .../Maxim/MAX32670/Include/pwrseq_regs.h | 6 +- .../Device/Maxim/MAX32670/Include/rtc_regs.h | 6 +- .../Device/Maxim/MAX32670/Include/sir_regs.h | 6 +- .../Device/Maxim/MAX32670/Include/spi_regs.h | 6 +- .../Device/Maxim/MAX32670/Include/tmr_regs.h | 6 +- .../Device/Maxim/MAX32670/Include/trng_regs.h | 6 +- .../Device/Maxim/MAX32670/Include/uart_regs.h | 6 +- .../Device/Maxim/MAX32670/Include/wdt_regs.h | 6 +- .../Device/Maxim/MAX32672/Include/adc_regs.h | 6 +- .../Device/Maxim/MAX32672/Include/aes_regs.h | 6 +- .../Device/Maxim/MAX32672/Include/ctb_regs.h | 6 +- .../Device/Maxim/MAX32672/Include/dma_regs.h | 8 +- .../Device/Maxim/MAX32672/Include/fcr_regs.h | 6 +- .../Device/Maxim/MAX32672/Include/flc_regs.h | 6 +- .../Device/Maxim/MAX32672/Include/gcr_regs.h | 6 +- .../Device/Maxim/MAX32672/Include/gpio_regs.h | 6 +- .../Device/Maxim/MAX32672/Include/i2c_regs.h | 6 +- .../Device/Maxim/MAX32672/Include/i2s_regs.h | 6 +- .../Device/Maxim/MAX32672/Include/icc_regs.h | 6 +- .../Maxim/MAX32672/Include/max32672.svd | 2 +- .../Device/Maxim/MAX32672/Include/mcr_regs.h | 6 +- .../Maxim/MAX32672/Include/pwrseq_regs.h | 6 +- .../Device/Maxim/MAX32672/Include/qdec_regs.h | 6 +- .../Device/Maxim/MAX32672/Include/rtc_regs.h | 6 +- .../Device/Maxim/MAX32672/Include/sir_regs.h | 6 +- .../Device/Maxim/MAX32672/Include/spi_regs.h | 6 +- .../Maxim/MAX32672/Include/sys_aeskeys_regs.h | 6 +- .../Device/Maxim/MAX32672/Include/tmr_regs.h | 6 +- .../Maxim/MAX32672/Include/trimsir_regs.h | 6 +- .../Device/Maxim/MAX32672/Include/trng_regs.h | 6 +- .../Device/Maxim/MAX32672/Include/uart_regs.h | 10 +- .../Maxim/MAX32672/Include/usr_aeskeys_regs.h | 6 +- .../Device/Maxim/MAX32672/Include/wdt_regs.h | 6 +- .../Device/Maxim/MAX32675/Include/aes_regs.h | 6 +- .../Maxim/MAX32675/Include/aeskeys_regs.h | 6 +- .../Maxim/MAX32675/Include/afe_adc_one_regs.h | 6 +- .../MAX32675/Include/afe_adc_zero_regs.h | 6 +- .../Maxim/MAX32675/Include/afe_dac_regs.h | 6 +- .../Maxim/MAX32675/Include/afe_hart_regs.h | 6 +- .../Device/Maxim/MAX32675/Include/crc_regs.h | 6 +- .../Device/Maxim/MAX32675/Include/dma_regs.h | 6 +- .../Device/Maxim/MAX32675/Include/ecc_regs.h | 6 +- .../Device/Maxim/MAX32675/Include/fcr_regs.h | 6 +- .../Device/Maxim/MAX32675/Include/flc_regs.h | 6 +- .../Device/Maxim/MAX32675/Include/gcr_regs.h | 6 +- .../Device/Maxim/MAX32675/Include/gpio_regs.h | 6 +- .../Device/Maxim/MAX32675/Include/i2c_regs.h | 6 +- .../Device/Maxim/MAX32675/Include/i2s_regs.h | 6 +- .../Device/Maxim/MAX32675/Include/icc_regs.h | 6 +- .../Device/Maxim/MAX32675/Include/mcr_regs.h | 6 +- .../Maxim/MAX32675/Include/pwrseq_regs.h | 6 +- .../Device/Maxim/MAX32675/Include/rtc_regs.h | 6 +- .../Device/Maxim/MAX32675/Include/sir_regs.h | 6 +- .../Device/Maxim/MAX32675/Include/spi_regs.h | 6 +- .../Device/Maxim/MAX32675/Include/tmr_regs.h | 6 +- .../Device/Maxim/MAX32675/Include/trng_regs.h | 6 +- .../Device/Maxim/MAX32675/Include/uart_regs.h | 6 +- .../Device/Maxim/MAX32675/Include/wdt_regs.h | 6 +- .../Device/Maxim/MAX32680/Include/adc_regs.h | 6 +- .../Device/Maxim/MAX32680/Include/aes_regs.h | 6 +- .../Maxim/MAX32680/Include/aeskeys_regs.h | 6 +- .../Maxim/MAX32680/Include/afe_adc_one_regs.h | 6 +- .../MAX32680/Include/afe_adc_zero_regs.h | 6 +- .../Maxim/MAX32680/Include/afe_dac_regs.h | 6 +- .../Maxim/MAX32680/Include/afe_hart_regs.h | 6 +- .../Device/Maxim/MAX32680/Include/crc_regs.h | 6 +- .../Device/Maxim/MAX32680/Include/dma_regs.h | 6 +- .../Device/Maxim/MAX32680/Include/dvs_regs.h | 6 +- .../Device/Maxim/MAX32680/Include/fcr_regs.h | 6 +- .../Device/Maxim/MAX32680/Include/flc_regs.h | 6 +- .../Device/Maxim/MAX32680/Include/gcfr_regs.h | 6 +- .../Device/Maxim/MAX32680/Include/gcr_regs.h | 6 +- .../Device/Maxim/MAX32680/Include/gpio_regs.h | 6 +- .../Device/Maxim/MAX32680/Include/i2c_regs.h | 6 +- .../Device/Maxim/MAX32680/Include/i2s_regs.h | 6 +- .../Device/Maxim/MAX32680/Include/icc_regs.h | 6 +- .../Maxim/MAX32680/Include/lpcmp_regs.h | 6 +- .../Maxim/MAX32680/Include/lpgcr_regs.h | 6 +- .../Device/Maxim/MAX32680/Include/mcr_regs.h | 6 +- .../Device/Maxim/MAX32680/Include/owm_regs.h | 6 +- .../Device/Maxim/MAX32680/Include/pt_regs.h | 6 +- .../Device/Maxim/MAX32680/Include/ptg_regs.h | 6 +- .../Maxim/MAX32680/Include/pwrseq_regs.h | 6 +- .../Device/Maxim/MAX32680/Include/rtc_regs.h | 6 +- .../Device/Maxim/MAX32680/Include/sema_regs.h | 6 +- .../Device/Maxim/MAX32680/Include/simo_regs.h | 6 +- .../Device/Maxim/MAX32680/Include/sir_regs.h | 6 +- .../Device/Maxim/MAX32680/Include/spi_regs.h | 6 +- .../Device/Maxim/MAX32680/Include/tmr_regs.h | 6 +- .../Maxim/MAX32680/Include/trimsir_regs.h | 6 +- .../Device/Maxim/MAX32680/Include/trng_regs.h | 6 +- .../Device/Maxim/MAX32680/Include/uart_regs.h | 6 +- .../Device/Maxim/MAX32680/Include/wdt_regs.h | 6 +- .../Device/Maxim/MAX32680/Include/wut_regs.h | 6 +- .../Device/Maxim/MAX32690/Include/adc_regs.h | 6 +- .../Maxim/MAX32690/Include/aeskeys_regs.h | 6 +- .../Device/Maxim/MAX32690/Include/can_regs.h | 6 +- .../Device/Maxim/MAX32690/Include/ctb_regs.h | 6 +- .../Device/Maxim/MAX32690/Include/dma_regs.h | 8 +- .../Device/Maxim/MAX32690/Include/emcc_regs.h | 6 +- .../Device/Maxim/MAX32690/Include/fcr_regs.h | 6 +- .../Device/Maxim/MAX32690/Include/flc_regs.h | 6 +- .../Device/Maxim/MAX32690/Include/gcfr_regs.h | 6 +- .../Device/Maxim/MAX32690/Include/gcr_regs.h | 6 +- .../Device/Maxim/MAX32690/Include/gpio_regs.h | 6 +- .../Device/Maxim/MAX32690/Include/hpb_regs.h | 6 +- .../Device/Maxim/MAX32690/Include/i2c_regs.h | 6 +- .../Device/Maxim/MAX32690/Include/i2s_regs.h | 6 +- .../Device/Maxim/MAX32690/Include/icc_regs.h | 6 +- .../Maxim/MAX32690/Include/lpcmp_regs.h | 14 +- .../Maxim/MAX32690/Include/lpgcr_regs.h | 6 +- .../Maxim/MAX32690/Include/max32690.svd | 30 +- .../Device/Maxim/MAX32690/Include/mcr_regs.h | 6 +- .../Device/Maxim/MAX32690/Include/owm_regs.h | 6 +- .../Device/Maxim/MAX32690/Include/pt_regs.h | 6 +- .../Device/Maxim/MAX32690/Include/ptg_regs.h | 6 +- .../Maxim/MAX32690/Include/pwrseq_regs.h | 6 +- .../Device/Maxim/MAX32690/Include/rtc_regs.h | 6 +- .../Device/Maxim/MAX32690/Include/sema_regs.h | 6 +- .../Device/Maxim/MAX32690/Include/sir_regs.h | 6 +- .../Device/Maxim/MAX32690/Include/smon_regs.h | 6 +- .../Device/Maxim/MAX32690/Include/spi_regs.h | 6 +- .../Maxim/MAX32690/Include/spixfc_fifo_regs.h | 6 +- .../Maxim/MAX32690/Include/spixfc_regs.h | 6 +- .../Maxim/MAX32690/Include/spixfm_regs.h | 6 +- .../Maxim/MAX32690/Include/spixr_regs.h | 6 +- .../Device/Maxim/MAX32690/Include/tmr_regs.h | 6 +- .../Maxim/MAX32690/Include/trimsir_regs.h | 6 +- .../Device/Maxim/MAX32690/Include/trng_regs.h | 6 +- .../Device/Maxim/MAX32690/Include/uart_regs.h | 6 +- .../Maxim/MAX32690/Include/usbhs_regs.h | 6 +- .../Device/Maxim/MAX32690/Include/wdt_regs.h | 6 +- .../Device/Maxim/MAX32690/Include/wut_regs.h | 6 +- .../Device/Maxim/MAX78000/Include/adc_regs.h | 6 +- .../Device/Maxim/MAX78000/Include/aes_regs.h | 6 +- .../Maxim/MAX78000/Include/aeskeys_regs.h | 6 +- .../Maxim/MAX78000/Include/cameraif_regs.h | 6 +- .../Device/Maxim/MAX78000/Include/crc_regs.h | 10 +- .../Device/Maxim/MAX78000/Include/dma_regs.h | 8 +- .../Device/Maxim/MAX78000/Include/dvs_regs.h | 6 +- .../Device/Maxim/MAX78000/Include/fcr_regs.h | 6 +- .../Device/Maxim/MAX78000/Include/flc_regs.h | 6 +- .../Device/Maxim/MAX78000/Include/gcfr_regs.h | 6 +- .../Device/Maxim/MAX78000/Include/gcr_regs.h | 6 +- .../Device/Maxim/MAX78000/Include/gpio_regs.h | 6 +- .../Device/Maxim/MAX78000/Include/i2c_regs.h | 6 +- .../Device/Maxim/MAX78000/Include/i2s_regs.h | 6 +- .../Device/Maxim/MAX78000/Include/icc_regs.h | 6 +- .../Maxim/MAX78000/Include/lpcmp_regs.h | 14 +- .../Maxim/MAX78000/Include/lpgcr_regs.h | 6 +- .../Maxim/MAX78000/Include/max78000.svd | 12 +- .../Device/Maxim/MAX78000/Include/mcr_regs.h | 6 +- .../Device/Maxim/MAX78000/Include/owm_regs.h | 6 +- .../Device/Maxim/MAX78000/Include/pt_regs.h | 6 +- .../Device/Maxim/MAX78000/Include/ptg_regs.h | 6 +- .../Maxim/MAX78000/Include/pwrseq_regs.h | 6 +- .../Device/Maxim/MAX78000/Include/rtc_regs.h | 6 +- .../Device/Maxim/MAX78000/Include/sema_regs.h | 6 +- .../Device/Maxim/MAX78000/Include/simo_regs.h | 6 +- .../Device/Maxim/MAX78000/Include/sir_regs.h | 6 +- .../Device/Maxim/MAX78000/Include/spi_regs.h | 6 +- .../Device/Maxim/MAX78000/Include/tmr_regs.h | 6 +- .../Maxim/MAX78000/Include/trimsir_regs.h | 6 +- .../Device/Maxim/MAX78000/Include/trng_regs.h | 6 +- .../Device/Maxim/MAX78000/Include/uart_regs.h | 6 +- .../Device/Maxim/MAX78000/Include/wdt_regs.h | 6 +- .../Device/Maxim/MAX78000/Include/wut_regs.h | 6 +- .../Device/Maxim/MAX78002/Include/adc_regs.h | 6 +- .../Device/Maxim/MAX78002/Include/aes_regs.h | 6 +- .../Maxim/MAX78002/Include/aeskeys_regs.h | 6 +- .../Maxim/MAX78002/Include/cameraif_regs.h | 6 +- .../Device/Maxim/MAX78002/Include/crc_regs.h | 10 +- .../Device/Maxim/MAX78002/Include/csi2_regs.h | 6 +- .../Device/Maxim/MAX78002/Include/dma_regs.h | 8 +- .../Device/Maxim/MAX78002/Include/dvs_regs.h | 6 +- .../Device/Maxim/MAX78002/Include/fcr_regs.h | 6 +- .../Device/Maxim/MAX78002/Include/flc_regs.h | 6 +- .../Device/Maxim/MAX78002/Include/gcfr_regs.h | 6 +- .../Device/Maxim/MAX78002/Include/gcr_regs.h | 6 +- .../Device/Maxim/MAX78002/Include/gpio_regs.h | 6 +- .../Device/Maxim/MAX78002/Include/i2c_regs.h | 6 +- .../Device/Maxim/MAX78002/Include/i2s_regs.h | 6 +- .../Device/Maxim/MAX78002/Include/icc_regs.h | 6 +- .../Maxim/MAX78002/Include/lpcmp_regs.h | 14 +- .../Maxim/MAX78002/Include/lpgcr_regs.h | 6 +- .../Maxim/MAX78002/Include/max78002.svd | 14 +- .../Device/Maxim/MAX78002/Include/mcr_regs.h | 6 +- .../Device/Maxim/MAX78002/Include/owm_regs.h | 6 +- .../Device/Maxim/MAX78002/Include/pt_regs.h | 6 +- .../Device/Maxim/MAX78002/Include/ptg_regs.h | 6 +- .../Maxim/MAX78002/Include/pwrseq_regs.h | 6 +- .../Device/Maxim/MAX78002/Include/rtc_regs.h | 6 +- .../Device/Maxim/MAX78002/Include/sdhc_regs.h | 6 +- .../Device/Maxim/MAX78002/Include/sema_regs.h | 6 +- .../Device/Maxim/MAX78002/Include/simo_regs.h | 6 +- .../Device/Maxim/MAX78002/Include/sir_regs.h | 6 +- .../Device/Maxim/MAX78002/Include/spi_regs.h | 6 +- .../Device/Maxim/MAX78002/Include/tmr_regs.h | 6 +- .../Maxim/MAX78002/Include/trimsir_regs.h | 6 +- .../Device/Maxim/MAX78002/Include/trng_regs.h | 6 +- .../Device/Maxim/MAX78002/Include/uart_regs.h | 10 +- .../Maxim/MAX78002/Include/usbhs_regs.h | 6 +- .../Device/Maxim/MAX78002/Include/wdt_regs.h | 6 +- .../Device/Maxim/MAX78002/Include/wut_regs.h | 6 +- .../PeriphDrivers/Source/UART/uart_ai87.c | 3 +- .../PeriphDrivers/Source/UART/uart_me21.c | 2 +- 424 files changed, 28724 insertions(+), 13734 deletions(-) create mode 100644 Libraries/CMSIS/Device/Maxim/MAX32570/Include/aeskeys_regs.h create mode 100644 Libraries/CMSIS/Device/Maxim/MAX32572/Include/aes_regs.h create mode 100644 Libraries/CMSIS/Device/Maxim/MAX32572/Include/flc_regs.h create mode 100644 Libraries/CMSIS/Device/Maxim/MAX32572/Include/i2s_regs.h create mode 100644 Libraries/CMSIS/Device/Maxim/MAX32572/Include/icc_regs.h create mode 100644 Libraries/CMSIS/Device/Maxim/MAX32572/Include/max32672.svd create mode 100644 Libraries/CMSIS/Device/Maxim/MAX32572/Include/qdec_regs.h create mode 100644 Libraries/CMSIS/Device/Maxim/MAX32572/Include/sys_aeskeys_regs.h create mode 100644 Libraries/CMSIS/Device/Maxim/MAX32572/Include/usr_aeskeys_regs.h diff --git a/Libraries/CMSIS/Device/Maxim/MAX32520/Include/aeskeys_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32520/Include/aeskeys_regs.h index ef24ad9635e..da614bb6b21 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32520/Include/aeskeys_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32520/Include/aeskeys_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32520/Include/ctb_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32520/Include/ctb_regs.h index 4d0f8be27e4..4228bf6860e 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32520/Include/ctb_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32520/Include/ctb_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32520/Include/dma_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32520/Include/dma_regs.h index 0604cd72a8d..c31a69507f9 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32520/Include/dma_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32520/Include/dma_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile @@ -88,7 +92,7 @@ typedef struct { __IO uint32_t cn; /**< \b 0x000: DMA CN Register */ __I uint32_t intr; /**< \b 0x004: DMA INTR Register */ __R uint32_t rsv_0x8_0xff[62]; - __IO mxc_dma_ch_regs_t ch[8]; /**< \b 0x100: DMA CH Register */ + __IO mxc_dma_ch_regs_t ch[8]; /**< \b 0x100: DMA CH Register */ } mxc_dma_regs_t; /* Register offsets for module DMA */ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32520/Include/fcr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32520/Include/fcr_regs.h index 5a445485b71..22d31cbb43f 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32520/Include/fcr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32520/Include/fcr_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32520/Include/flc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32520/Include/flc_regs.h index 37277ed8043..0dbb893a5fb 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32520/Include/flc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32520/Include/flc_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32520/Include/gcr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32520/Include/gcr_regs.h index d37e1ac812b..8c6b1f79eb0 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32520/Include/gcr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32520/Include/gcr_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32520/Include/gpio_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32520/Include/gpio_regs.h index 3de904f5573..116b9a568cb 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32520/Include/gpio_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32520/Include/gpio_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32520/Include/i2c_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32520/Include/i2c_regs.h index 6fd31c204f2..e386398e6d6 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32520/Include/i2c_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32520/Include/i2c_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32520/Include/icc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32520/Include/icc_regs.h index edd539931b2..adf8b7828c7 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32520/Include/icc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32520/Include/icc_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32520/Include/mcr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32520/Include/mcr_regs.h index e76a50c4477..e38361efe90 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32520/Include/mcr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32520/Include/mcr_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32520/Include/pwrseq_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32520/Include/pwrseq_regs.h index f4458eadb9b..70b50fb7ae3 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32520/Include/pwrseq_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32520/Include/pwrseq_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32520/Include/sfe_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32520/Include/sfe_regs.h index 3cae74402d4..88c17439bd0 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32520/Include/sfe_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32520/Include/sfe_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32520/Include/sir_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32520/Include/sir_regs.h index 58b5b0667d7..3ee490f22cb 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32520/Include/sir_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32520/Include/sir_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32520/Include/smon_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32520/Include/smon_regs.h index 5ae6aff115a..fe4a0ca052d 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32520/Include/smon_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32520/Include/smon_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32520/Include/spi_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32520/Include/spi_regs.h index fd7bbf91a0c..9f1201c1221 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32520/Include/spi_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32520/Include/spi_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32520/Include/tmr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32520/Include/tmr_regs.h index 19a42e09f3a..657fb0372e4 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32520/Include/tmr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32520/Include/tmr_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32520/Include/trng_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32520/Include/trng_regs.h index a48d10fa24b..5e226ebcb08 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32520/Include/trng_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32520/Include/trng_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32520/Include/uart_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32520/Include/uart_regs.h index b837fb2be37..d44a60f1914 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32520/Include/uart_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32520/Include/uart_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32520/Include/wdt_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32520/Include/wdt_regs.h index 835a8c40fa7..8e4ef542e21 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32520/Include/wdt_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32520/Include/wdt_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32570/Include/adc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32570/Include/adc_regs.h index 73afe1f185c..d4e0bc313d2 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32570/Include/adc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32570/Include/adc_regs.h @@ -2,25 +2,18 @@ * @file adc_regs.h * @brief Registers, Bit Masks and Bit Positions for the ADC Peripheral Module. * @note This file is @generated. + * @ingroup adc_registers */ /****************************************************************************** * - * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by - * Analog Devices, Inc.), - * Copyright (C) 2023-2024 Analog Devices, Inc. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at +/****************************************************************************** * - * http://www.apache.org/licenses/LICENSE-2.0 + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. All Rights Reserved. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. + * This software is proprietary to Analog Devices, Inc. and its licensors. * ******************************************************************************/ @@ -49,7 +42,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32570/Include/aeskeys_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32570/Include/aeskeys_regs.h new file mode 100644 index 00000000000..40bd2187577 --- /dev/null +++ b/Libraries/CMSIS/Device/Maxim/MAX32570/Include/aeskeys_regs.h @@ -0,0 +1,97 @@ +/** + * @file aeskeys_regs.h + * @brief Registers, Bit Masks and Bit Positions for the AESKEYS Peripheral Module. + * @note This file is @generated. + * @ingroup aeskeys_registers + */ + +/****************************************************************************** + * +/****************************************************************************** + * + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. All Rights Reserved. + * + * This software is proprietary to Analog Devices, Inc. and its licensors. + * + ******************************************************************************/ + +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32570_INCLUDE_AESKEYS_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32570_INCLUDE_AESKEYS_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup aeskeys + * @ingroup aes + * @defgroup aeskeys_registers AESKEYS_Registers + * @brief Registers, Bit Masks and Bit Positions for the AESKEYS Peripheral Module. + * @details AES Keys. + */ + +/** + * @ingroup aeskeys_registers + * Structure type to access the AESKEYS Registers. + */ +typedef struct { + __IO uint32_t sram_key; /**< \b 0x00: AESKEYS SRAM_KEY Register */ + __R uint32_t rsv_0x4_0x1f[7]; + __IO uint32_t code_key; /**< \b 0x20: AESKEYS CODE_KEY Register */ + __R uint32_t rsv_0x24_0x3f[7]; + __IO uint32_t data_key; /**< \b 0x40: AESKEYS DATA_KEY Register */ +} mxc_aeskeys_regs_t; + +/* Register offsets for module AESKEYS */ +/** + * @ingroup aeskeys_registers + * @defgroup AESKEYS_Register_Offsets Register Offsets + * @brief AESKEYS Peripheral Register Offsets from the AESKEYS Base Peripheral Address. + * @{ + */ +#define MXC_R_AESKEYS_SRAM_KEY ((uint32_t)0x00000000UL) /**< Offset from AESKEYS Base Address: 0x0000 */ +#define MXC_R_AESKEYS_CODE_KEY ((uint32_t)0x00000020UL) /**< Offset from AESKEYS Base Address: 0x0020 */ +#define MXC_R_AESKEYS_DATA_KEY ((uint32_t)0x00000040UL) /**< Offset from AESKEYS Base Address: 0x0040 */ +/**@} end of group aeskeys_registers */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32570_INCLUDE_AESKEYS_REGS_H_ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32570/Include/cameraif_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32570/Include/cameraif_regs.h index 306fd514123..7dd7ec490ef 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32570/Include/cameraif_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32570/Include/cameraif_regs.h @@ -2,25 +2,18 @@ * @file cameraif_regs.h * @brief Registers, Bit Masks and Bit Positions for the CAMERAIF Peripheral Module. * @note This file is @generated. + * @ingroup cameraif_registers */ /****************************************************************************** * - * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by - * Analog Devices, Inc.), - * Copyright (C) 2023-2024 Analog Devices, Inc. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at +/****************************************************************************** * - * http://www.apache.org/licenses/LICENSE-2.0 + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. All Rights Reserved. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. + * This software is proprietary to Analog Devices, Inc. and its licensors. * ******************************************************************************/ @@ -49,7 +42,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32570/Include/ctb_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32570/Include/ctb_regs.h index 44f076a61aa..15bc9737a5f 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32570/Include/ctb_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32570/Include/ctb_regs.h @@ -2,25 +2,18 @@ * @file ctb_regs.h * @brief Registers, Bit Masks and Bit Positions for the CTB Peripheral Module. * @note This file is @generated. + * @ingroup ctb_registers */ /****************************************************************************** * - * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by - * Analog Devices, Inc.), - * Copyright (C) 2023-2024 Analog Devices, Inc. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at +/****************************************************************************** * - * http://www.apache.org/licenses/LICENSE-2.0 + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. All Rights Reserved. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. + * This software is proprietary to Analog Devices, Inc. and its licensors. * ******************************************************************************/ @@ -49,7 +42,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32570/Include/dma_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32570/Include/dma_regs.h index c57f9db461b..98c2536b38d 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32570/Include/dma_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32570/Include/dma_regs.h @@ -2,25 +2,18 @@ * @file dma_regs.h * @brief Registers, Bit Masks and Bit Positions for the DMA Peripheral Module. * @note This file is @generated. + * @ingroup dma_registers */ /****************************************************************************** * - * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by - * Analog Devices, Inc.), - * Copyright (C) 2023-2024 Analog Devices, Inc. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at +/****************************************************************************** * - * http://www.apache.org/licenses/LICENSE-2.0 + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. All Rights Reserved. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. + * This software is proprietary to Analog Devices, Inc. and its licensors. * ******************************************************************************/ @@ -49,7 +42,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile @@ -87,7 +84,7 @@ typedef struct { __IO uint32_t cn; /**< \b 0x000: DMA CN Register */ __I uint32_t intr; /**< \b 0x004: DMA INTR Register */ __R uint32_t rsv_0x8_0xff[62]; - __IO mxc_dma_ch_regs_t ch[8]; /**< \b 0x100: DMA CH Register */ + __IO mxc_dma_ch_regs_t ch[8]; /**< \b 0x100: DMA CH Register */ } mxc_dma_regs_t; /* Register offsets for module DMA */ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32570/Include/emac_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32570/Include/emac_regs.h index a33d2e77be8..95c02660e00 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32570/Include/emac_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32570/Include/emac_regs.h @@ -2,25 +2,18 @@ * @file emac_regs.h * @brief Registers, Bit Masks and Bit Positions for the EMAC Peripheral Module. * @note This file is @generated. + * @ingroup emac_registers */ /****************************************************************************** * - * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by - * Analog Devices, Inc.), - * Copyright (C) 2023-2024 Analog Devices, Inc. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at +/****************************************************************************** * - * http://www.apache.org/licenses/LICENSE-2.0 + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. All Rights Reserved. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. + * This software is proprietary to Analog Devices, Inc. and its licensors. * ******************************************************************************/ @@ -49,7 +42,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32570/Include/fcr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32570/Include/fcr_regs.h index 8f1e414ef3b..96f48d00f6e 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32570/Include/fcr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32570/Include/fcr_regs.h @@ -2,25 +2,18 @@ * @file fcr_regs.h * @brief Registers, Bit Masks and Bit Positions for the FCR Peripheral Module. * @note This file is @generated. + * @ingroup fcr_registers */ /****************************************************************************** * - * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by - * Analog Devices, Inc.), - * Copyright (C) 2023-2024 Analog Devices, Inc. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at +/****************************************************************************** * - * http://www.apache.org/licenses/LICENSE-2.0 + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. All Rights Reserved. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. + * This software is proprietary to Analog Devices, Inc. and its licensors. * ******************************************************************************/ @@ -49,7 +42,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32570/Include/flc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32570/Include/flc_regs.h index 23e8802bce3..ea3f00d4f0b 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32570/Include/flc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32570/Include/flc_regs.h @@ -2,25 +2,18 @@ * @file flc_regs.h * @brief Registers, Bit Masks and Bit Positions for the FLC Peripheral Module. * @note This file is @generated. + * @ingroup flc_registers */ /****************************************************************************** * - * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by - * Analog Devices, Inc.), - * Copyright (C) 2023-2024 Analog Devices, Inc. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at +/****************************************************************************** * - * http://www.apache.org/licenses/LICENSE-2.0 + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. All Rights Reserved. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. + * This software is proprietary to Analog Devices, Inc. and its licensors. * ******************************************************************************/ @@ -49,7 +42,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32570/Include/gcr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32570/Include/gcr_regs.h index b691ec0445b..0d4ab8baa65 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32570/Include/gcr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32570/Include/gcr_regs.h @@ -2,25 +2,18 @@ * @file gcr_regs.h * @brief Registers, Bit Masks and Bit Positions for the GCR Peripheral Module. * @note This file is @generated. + * @ingroup gcr_registers */ /****************************************************************************** * - * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by - * Analog Devices, Inc.), - * Copyright (C) 2023-2024 Analog Devices, Inc. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at +/****************************************************************************** * - * http://www.apache.org/licenses/LICENSE-2.0 + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. All Rights Reserved. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. + * This software is proprietary to Analog Devices, Inc. and its licensors. * ******************************************************************************/ @@ -49,7 +42,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32570/Include/gpio_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32570/Include/gpio_regs.h index 3061df6632a..477fe6c6d79 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32570/Include/gpio_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32570/Include/gpio_regs.h @@ -2,25 +2,18 @@ * @file gpio_regs.h * @brief Registers, Bit Masks and Bit Positions for the GPIO Peripheral Module. * @note This file is @generated. + * @ingroup gpio_registers */ /****************************************************************************** * - * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by - * Analog Devices, Inc.), - * Copyright (C) 2023-2024 Analog Devices, Inc. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at +/****************************************************************************** * - * http://www.apache.org/licenses/LICENSE-2.0 + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. All Rights Reserved. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. + * This software is proprietary to Analog Devices, Inc. and its licensors. * ******************************************************************************/ @@ -49,7 +42,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32570/Include/ha_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32570/Include/ha_regs.h index 595506ba364..fabfff2c19e 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32570/Include/ha_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32570/Include/ha_regs.h @@ -2,25 +2,18 @@ * @file ha_regs.h * @brief Registers, Bit Masks and Bit Positions for the HA Peripheral Module. * @note This file is @generated. + * @ingroup ha_registers */ /****************************************************************************** * - * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by - * Analog Devices, Inc.), - * Copyright (C) 2023-2024 Analog Devices, Inc. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at +/****************************************************************************** * - * http://www.apache.org/licenses/LICENSE-2.0 + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. All Rights Reserved. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. + * This software is proprietary to Analog Devices, Inc. and its licensors. * ******************************************************************************/ @@ -49,7 +42,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32570/Include/htmr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32570/Include/htmr_regs.h index 33cb177db08..20aa53a2dd8 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32570/Include/htmr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32570/Include/htmr_regs.h @@ -2,25 +2,18 @@ * @file htmr_regs.h * @brief Registers, Bit Masks and Bit Positions for the HTMR Peripheral Module. * @note This file is @generated. + * @ingroup htmr_registers */ /****************************************************************************** * - * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by - * Analog Devices, Inc.), - * Copyright (C) 2023-2024 Analog Devices, Inc. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at +/****************************************************************************** * - * http://www.apache.org/licenses/LICENSE-2.0 + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. All Rights Reserved. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. + * This software is proprietary to Analog Devices, Inc. and its licensors. * ******************************************************************************/ @@ -49,7 +42,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32570/Include/i2c_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32570/Include/i2c_regs.h index 2c06c6676d4..2dc05aa3d7f 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32570/Include/i2c_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32570/Include/i2c_regs.h @@ -2,25 +2,18 @@ * @file i2c_regs.h * @brief Registers, Bit Masks and Bit Positions for the I2C Peripheral Module. * @note This file is @generated. + * @ingroup i2c_registers */ /****************************************************************************** * - * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by - * Analog Devices, Inc.), - * Copyright (C) 2023-2024 Analog Devices, Inc. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at +/****************************************************************************** * - * http://www.apache.org/licenses/LICENSE-2.0 + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. All Rights Reserved. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. + * This software is proprietary to Analog Devices, Inc. and its licensors. * ******************************************************************************/ @@ -49,7 +42,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32570/Include/icc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32570/Include/icc_regs.h index e89860807af..01b7524b75d 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32570/Include/icc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32570/Include/icc_regs.h @@ -2,25 +2,18 @@ * @file icc_regs.h * @brief Registers, Bit Masks and Bit Positions for the ICC Peripheral Module. * @note This file is @generated. + * @ingroup icc_registers */ /****************************************************************************** * - * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by - * Analog Devices, Inc.), - * Copyright (C) 2023-2024 Analog Devices, Inc. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at +/****************************************************************************** * - * http://www.apache.org/licenses/LICENSE-2.0 + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. All Rights Reserved. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. + * This software is proprietary to Analog Devices, Inc. and its licensors. * ******************************************************************************/ @@ -49,7 +42,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32570/Include/max32570.svd b/Libraries/CMSIS/Device/Maxim/MAX32570/Include/max32570.svd index e22e66c49f6..796b8d59892 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32570/Include/max32570.svd +++ b/Libraries/CMSIS/Device/Maxim/MAX32570/Include/max32570.svd @@ -362,616 +362,731 @@ - ADC9 - Magnetic Strip Reader - 9 bit ADC - 0x4002B000 - 32 - read-write + AESKEYS + AES Keys. + 0x40005000 - 0 - 0x1000 + 0x00 + 0x400 registers - - ADC9 - ADC IRQ - 22 - - CFG - ADC Control - 0x0000 + SRAM_KEY + AES SRAM KEY + 0x00 + 32 + + + CODE_KEY + AES CODE Key + 0x20 + + + DATA_KEY + AES DATA KEY + 0x40 + + + + + + FCR + Function Control Register. + 0x40000800 + + 0x00 + 0x400 + registers + + + + FCTRL0 + Register 0. + 0x00 read-write - CLKDIV - ADC Clock Divider. - [7:0] - read-write - - - ACHSEL - A Channel ADC Input Pin Selection. - [10:8] - read-write + USB_EXTCLK_SEL + USB External Core Clock Select. + 16 + 1 - INVALID_000 + sys + Generated clock from system clock. 0 - IN0 + dig + Digital clock from a GPIO. 1 - - IN1 - 2 - - - IN2 - 3 - - - IN3 - 4 - - - IN4 - 5 - - - IN5 - 6 - - - INVALID_111 - 7 - - - BCHSEL - B Channel ADC Input Pin Selection. - [13:11] - read-write - - - CCHSEL - C Channel ADC Input Pin Selection. - [16:14] - read-write - - - DCHSEL - D Channel ADC Input Pin Selection. - [19:17] - read-write - - - ECHSEL - E Channel ADC Input Pin Selection. - [22:20] - read-write - - - FCHSEL - F Channel ADC Input Pin Selection. - [25:23] - read-write - - - GCHSEL - G Channel ADC Input Pin Selection. - [28:26] - read-write - - - HCHSEL - H Channel ADC Input Pin Selection. - [31:29] - read-write - - - - - CMD - MSRADC Command - 0x0004 - read-write - - RST - ADC Reset. - [0:0] - read-write + I2C0_SDA_FILTER_EN + I2C0 SDA Glitch Filter Enable. + 20 + 1 - NO_RESET + dis + Filter disabled. 0 - RESET + en + Filter enabled. 1 - SNGLSMPL - Single Sample Mode. - [1:1] - read-write + I2C0_SCL_FILTER_EN + I2C0 SCL Glitch Filter Enable. + 21 + 1 - NO_EFFECT + dis + Filter disabled. 0 - SINGLE_SMPL + en + Filter enabled. 1 - CONTSMPL - Continuous Sample Mode Enable. - [2:2] - read-write + I2C1_SDA_FILTER_EN + I2C1 SDA Glitch Filter Enable. + 22 + 1 - NO_CONTINUOUS_SMPL_MODE + dis + Filter disabled. 0 - CONTINUOUS_SMPL_MODE + en + Filter enabled. 1 - ROTLIMIT - Rotation Limit. - [6:4] - read-write + I2C1_SCL_FILTER_EN + I2C1 SCL Glitch Filter Enable. + 23 + 1 - 1_channel + dis + Filter disabled. 0 - 2_channels + en + Filter enabled. 1 + + + + I2C2AF2_SDA_FILTER_EN + I2C2 AF2 SDA Glitch Filter Enable. + 24 + 1 + - 3_channels - 2 - - - 4_channels - 3 - - - 5_channels - 4 + dis + Filter disabled. + 0 - 6_channels - 5 + en + Filter enabled. + 1 + + + + I2C2AF2_SCL_FILTER_EN + I2C2 AF2 SCL Glitch Filter Enable. + 25 + 1 + - 7_channels - 6 + dis + Filter disabled. + 0 - 8_channels - 7 + en + Filter enabled. + 1 - CLKSEL - Clock Select. - [10:8] - read-write + I2C2AF3_SDA_FILTER_EN + I2C2 AF3 SDA Glitch Filter Enable. + 26 + 1 - 3_samples + dis + Filter disabled. 0 - 5_samples + en + Filter enabled. 1 + + + + I2C2AF3_SCL_FILTER_EN + I2C2 AF3 SCL Glitch Filter Enable. + 27 + 1 + - 4_samples - 2 + dis + Filter disabled. + 0 - 8_samples - 3 + en + Filter enabled. + 1 + + + + I2C2AF4_SDA_FILTER_EN + I2C2 AF4 SDA Glitch Filter Enable + 28 + 1 + - 16_samples - 4 + dis + Filter disabled. + 0 - 32_samples - 5 + en + Filter enabled. + 1 + + + + I2C2AF4_SCL_FILTER_EN + I2C2 AF4 SCL Glitch Filter Enable + 29 + 1 + - 64_samples - 6 + dis + Filter disabled. + 0 - 128_samples - 7 + en + Filter enabled. + 1 - FIFO - ADC FIFO - 0x0008 + AUTOCAL0 + Register 1. + 0x04 read-write - SAMPLE - ADC Converted Sample Data Output - [8:0] - read-only - - - SMPLIN - ADC Sample Pin - [11:9] - read-only + SEL + Auto-calibration Enable. + 0 + 1 - INVALID_000 + dis + Disabled. 0 - IN0 + en + Enabled. 1 - - IN1 - 2 - - - IN2 - 3 - - - IN3 - 4 - - - IN4 - 5 - - - IN5 - 6 - - - INVALID_111 - 7 - - - - - INTR - ADC Interrupt Enable Register - 0x000C - read-write - - FIFOLVL - Set FIFO Interrupt Level. - [2:0] - read-write + EN + Autocalibration Run. + 1 + 1 - at_least_1 + not + Not Running. 0 - at_least_2 + run + Running. 1 - - at_least_3 - 2 - - - at_least_4 - 3 - - - at_least_5 - 4 - - - at_least_6 - 5 - - - at_least_7 - 6 - - - at_least_8 - 7 - - DMAREQEN - DMA Request Enable. - [3:3] - read-write + LOAD + Load Trim. + 2 + 1 + + + INVERT + Invert Gain. + 3 + 1 - DISABLED + not + Not Running. 0 - ENABLED + run + Running. 1 - OVERFIE - FIFO Overflow Interrupt Enable. - [6:6] - read-write + ATOMIC + Atomic mode. + 4 + 1 - DISABLED + not + Not Running. 0 - ENABLED + run + Running. 1 - UNDRFIE - FIFO Underflow Interrupt Enable. - [7:7] - read-write + GAIN + MU value. + 8 + 12 + + + TRIM + 150MHz HFIO Auto Calibration Trim + 23 + 9 + + + + + AUTOCAL1 + Register 2. + 0x08 + read-write + + + NFC_FWD_EN + Enabled FWD mode for NFC block + 0 + 1 + + + NFC_CLK_EN + Enabled the NFC blocks clock divider in Analog + 1 + 1 + + + NFC_FWD_TX_DATA_OVR + FWD input for NFC block + 2 + 1 + + + XO_EN_DGL + TBD + 3 + 1 + + + RX_BIAS_PD + Power down enable for NFC receiver analog block + 4 + 1 + + + RX_BIAS_EN + Enable the NFC receiver analog blocks + 5 + 1 + + + RX_TM_VBG_VABUS + TBD + 6 + 1 + + + RX_TM_BIAS + TBD + 7 + 1 + + + NFC_FWD_DOUT + FWD output from FNC block + 8 + 1 + + + + + AUTOCAL2 + Register 3. + 0x0C + read-write + + + RUNTIME + Automatic Calibration Run Time. + 0 + 8 + + + + + + + + TRIMSIR + Trim System Initilazation Registers + 0x40005400 + + 0x00 + 0x400 + registers + + + + rsv0 + RFU + 0x00 + + + BB_SIR2 + System Init. Configuration Register 2. + 0x08 + read-only + + + BB_SIR3 + System Init. Configuration Register 3. + 0x0C + read-only + + + + + + MCR + Misc Control. + 0x40006C00 + + 0x00 + 0x400 + registers + + + + ECCEN + ECC Enable Register + 0x00 + + + SYSRAM0ECCEN + ECC System RAM Enable. + 0 + 1 - DISABLED + dis + disabled. 0 - ENABLED + en + enabled. 1 - FIFOLVLIE - FIFO Level Interrupt Enable. - [8:8] - read-write + SYSRAM1ECCEN + ECC System RAM Enable. + 1 + 1 - DISABLED + dis + disabled. 0 - ENABLED + en + enabled. 1 - GLOBIE - ADC Global Interrupt Enable. - [9:9] - read-write + SYSRAM2ECCEN + ECC System RAM Enable. + 2 + 1 - DISABLED + dis + disabled. 0 - ENABLED + en + enabled. 1 - - - - STAT - ADC Interrupt Flag Register. - read-write - 0x0010 - - FIFOCNT - FIFO Count. - [3:0] - read-only + SYSRAM3ECCEN + ECC System RAM Enable. + 3 + 1 - FIFO_EMPTY + dis + disabled. 0 - ONE_SAMPLE + en + enabled. 1 + + + + SYSRAM4ECCEN + ECC System RAM Enable. + 4 + 1 + - TWO_SAMPLE - 2 - - - THREE_SAMPLE - 3 - - - FOUR_SAMPLE - 4 - - - FIVE_SAMPLE - 5 + dis + disabled. + 0 - SIX_SAMPLE - 6 + en + enabled. + 1 + + + + SYSRAM5ECCEN + ECC System RAM Enable. + 5 + 1 + - SEVEN_SAMPLE - 7 + dis + disabled. + 0 - EIGHT_SAMPLE - 8 + en + enabled. + 1 - FULL - FIFO Full Status. - [4:4] - read-only + IC0ECCEN + Icache0 ECC Enable. + 8 + 1 - FIFO_NOT_FULL + dis + disabled. 0 - FIFO_FULL + en + enabled. 1 - EMPTY - FIFO Empty Status. - [5:5] - read-only + ICXIPECCEN + IcacheXIP ECC Enable. + 10 + 1 - FIFO_NOT_EMPTY + dis + disabled. 0 - FIFO_EMPTY + en + enabled. 1 - OVERFINT - FIFO Overflow Status. - [6:6] - read-only + FL0ECCEN + Flash0 ECC Enable. + 11 + 1 - NOT_FIFO_OVERFLOW + dis + disabled. 0 - FIFO_OVERFLOW + en + enabled. 1 - UNDRFINT - FIFO Underflow Status. - [7:7] - read-only + FL1ECCEN + Flash1 ECC Enable. + 12 + 1 - NOT_FIFO_UNDERFLOW + dis + disabled. 0 - FIFO_UNDERFLOW + en + enabled. 1 + + + + PDOWN + PDOWN Drive Strength + 0x08 + + + PDOWNDS + PDOWN Drive Strength + 0 + 2 + - FIFOLVLST - FIFO Level Status. - [8:8] - read-only + PDOWNVS + PDOWN Voltage Select + 2 + 1 + + + + + CTRL + Misc Power State Control Register + 0x10 + + + VDDCSW + Controls switching of VCORE + 1 + 2 + + + USBSWEN_N + USB Switch Control + 3 + 1 - BELOW_LVL - 0 + off + USB SW off in LP modes + 1 - ABOVE_LVL - 1 + on + USB SW On + 0 - GLOBINT - ADC Global Interrupt Status. - [9:9] - read-only + P1M + Enable the Reset Pad Pull Up Resistors + 9 + 1 - NOT_ACTIVE + 1m + 1MOhm Pullup 0 - ACTIVE + 25k + 25kOhm Pullup. 1 + + rstn_voltage_sel + Error! Description not Found! + 10 + 1 + - - - AES - AES Keys. - 0x40005000 - - 0x00 - 0x400 - registers - - - - AES_SRAM_KEY - AES SRAM KEY - 0x000 - 32 - - - AES_CODE_KEY - AES CODE Key - 0x080 - - - AES_DATA_KEY - AES DATA KEY - 0x100 - - - - + CAMERAIF Parallel Camera Interface. @@ -1105,7 +1220,7 @@ RX_DMA DMA Enable. - 16 + 10 1 read-write @@ -1124,21 +1239,14 @@ RX_DMA_THRSH DMA Threshold. - 17 + 11 4 read-write - - THREE_CH_EN - Three-channel mode enable. - 30 - 1 - read-write - PCIF_SYS PCIF Control. - 31 + 15 1 read-write @@ -1266,7150 +1374,5198 @@ - CLCD - Color LCD Controller - 0x40031000 + CTB + The Cryptographic Toolbox is a combination of cryptographic engines and a secure cryptographic accelerator (SCA) used to provide advanced cryptographic security. + 0x40001000 0x00 0x1000 registers + + Crypto_Engine + Crypto Engine interrupt. + 27 + - CLK - LCD Clock Control Register - 0x000 + CRYPTO_CTRL + Crypto Control Register. + 0x00 + 0xC0000000 - CLKDIV - Clock divsor + RST + Reset. This bit is used to reset the crypto accelerator. All crypto internal states and related registers are reset to their default reset values. Control register such as CRYPTO_CTRL, CIPHER_CTRL, HASH_CTRL, CRC_CTRL, MAA_CTRL (with the exception of the STC bit), HASH_MSG_SZ_[3:0] and MAA_MAWS will retain their values. This bit will automatically clear itself after one cycle. 0 - 8 - - - ACB - ACB - 8 - 8 - - - DPOL - D Polarity - 16 1 + reset_write + write - ACTIVEHI - Active Hi - 0 - - - ACTIVELO - Active Low + reset + Starts reset operation. 1 - - - VPOL - V Polarity - 17 - 1 + reset_read + read - ACTIVEHI - Active Hi - 1 - - - ACTIVELO - Active Low + reset_done + Reset complete. 0 - - - - HPOL - H Polarity - 18 - 1 - - ACTIVEHI - Active Hi + busy + Reset in progress. 1 - - ACTIVELO - Active Low - 0 - - EDGE - Edge Selection - 19 + INTR + Interrupt Enable. Generates an interrupt when done or error set. + 1 1 - RISEEDGE - Rising edge + dis + Disable 0 - FALLEDGE - Falling Edge + en + Enable 1 - PASCLK - Clock Active on Data - 20 + SRC + Source Select. This bit selects the hash function and CRC generator input source. + 2 1 - ALWAYSACTIVE - Always Active + inputFIFO + Input FIFO 0 - ACTIVEONDATA - ACTIVE ON DATA + outputFIFO + Output FIFO 1 - - - - VTIM_0 - LCD Vertical Timing 0 Register - 0x004 - - - VLINES - V Lines - 0 - 8 - - - VBACKPORCH - V BACK PORCH - 16 - 8 - - - - - VTIM_1 - LCD Vertical Timing 1 Register - 0x008 - - - VSYNCWIDTH - V Sync Width - 0 - 8 - - - VFRONTPORCH - V Front PORCH - 16 - 8 - - - - - HTIM - LCD Horizontal Timing Register. - 0x00C - - - HSYNCWIDTH - Horizontal Sync Width in CLCD Clocks from 1 to 256 HSync Width = HSYNCWIDTH+1 Clocks - 0 - 8 - - - HFRONTPORCH - Horizontal Front Porch size in lines from 1 to 256 - 8 - 8 + + BSO + Byte Swap Output. Note. No byte swap will occur if there is not a full word. + 4 + 1 - - HSIZE - Horizontal Front Porch Size in Pixels = (HSIZE + 1) *16 - 16 - 8 + + BSI + Byte Swap Input. Note. No byte swap will occur if there is not a full word. + 5 + 1 - - HBACKPORCH - Horizontal Back Porch size in CLCD Clocks from 1 to 256 -> HBP= (HBACKPORCH+1) - 24 - 8 + + WAIT_EN + Wait Pin Enable. This can be used to hold off the crypto DMA until an external memory is ready. This is useful for transferring pages from NAND flash which may take several microseconds to become ready. + 6 + 1 - - - - CTRL - LCD Control Register - 0x010 - - LCDEN - LCD Enable - 0 + WAIT_POL + Wait Pin Polarity. When the wait pin is enabled, this bit selects its active state. + 7 1 - DISABLE - Disable + activeLo + Active Low. 0 - ENABLE - Enable + activeHi + Active High. 1 - VISEL - VI Select - 1 + WRSRC + Write FIFO Source Select. This field determines where data written to the write FIFO comes from. When data is written to the write FIFO, it is always written out the DMA. To decrypt or encrypt data, the write FIFO source should be set to the cipher output. To implement memcpy() or memset() functions, or to fill memory with random data, the write FIFO source should be set to the read FIFO. When calculating a HASH or CMAC, the write FIFO should be disabled. + 8 2 - ONVERTSYNC - On Vertical Sync + none + None. 0 - ONVERTBACKPORCH - On Vertical Back Porch + cipherOutput + Cipher Output. 1 - ONACTIVEVIDEO - On Active Video + readFIFO + Read FIFO. 2 - - ONVERTFRONTPORCH - On Vertical Front Porch - 3 - - DISPTYPE - Display Type - 4 - 4 + RDSRC + Read FIFO Source Select. This field selects the source of the read FIFO. Typically, it is set to use the DMA. To implement a memset() function, the read FIFO DMA should be disabled. To fill memory with random data or to hash random numbers, the read FIFO source should be set to the random number generator. + 10 + 2 - STNCOLOR8BIT - STN Color 8 bit - 4 + dmaDisabled + DMA Disable. + 0 - CLCD - CLCD - 8 + dmaOrApb + DMA Or APB. + 1 + + + rng + RNG. + 2 - BPP - BPP - 8 - 3 + FLAG_MODE + Done Flag Mode. This bit configures the access behavior of the individual CRYPTO_CTRL Done flags (CRYPTO_CTRL[27:24]). This bit is cleared only on reset to limit upkeep, i.e. once set, it will remain set until a reset occurs. + 14 + 1 - BPP1 - BPP 1 + unres_wr + Unrestricted write (0 or 1) of CRYPTO_CTRL[27:24] flags. 0 - BPP2 - BPP 2 + res_wr + Access to CRYPTO_CTRL[27:24] are write 1 to clear/write 0 no effect. 1 - - BPP4 - BPP 4 - 2 - - - BPP8 - BPP 8 - 3 - - - BPP16 - BPP 16 - 4 - - - BPP24 - BPP 24 - 5 - - MODE565 - MODE565 - 11 + DMADNEMSK + DMA Done Flag Mask. This bit masks the DMA_DONE flag from being used to generate the CRYPTO_CTRL.DONE flag, and this disables a DMA_DONE condition from generating and interrupt. The DMA_DONE flag itself is unaffected and still may be monitored. This allows more optimal interrupt-driven crypto operations using DMA. + 15 1 - BGR556 - MODE 556 + not_used + DMA_DONE not used in setting CRYPTO_CTRL.DONE bit. 0 - RGB565 - MODE 565 + used + DMA_DONE used in setting CRYPTO_CTRL.DONE bit. 1 - EMODE - EMODE - 12 - 2 + DMA_DONE + DMA Done. DMA write/read operation is complete. This bit must be cleared before starting a DMA operation. + 24 + 1 - LLBP - LLBP + notDone + Not Done. 0 - BBBP - BBBP + done + Done. 1 - - LBBP - LBBP - 2 - - - RFU - RFU - 3 - - - C24 - C24 - 15 + + GLS_DONE + Galois Done. FIFO is full and CRC or Hamming Code Generator is enabled. This bit must be cleared before starting a CRC operation Note that DMA_DONE must be polled instead of this bit to determine the end of DMA operation during the utilization of Hamming Code Generator. + 25 + 1 + + + HSH_DONE + Hash Done. SHA operation is complete. This bit must be cleared before starting a HASH operation. + 26 + 1 + + + CPH_DONE + Cipher Done. Either AES or DES encryption/decryption operation is complete. This bit must be cleared before starting a cipher operation. + 27 1 - BURST - BURST - 19 - 2 + ERR + AHB Bus Error. This bit is set when the DMA encounters a bus error during a read or write operation. Once this bit is set, the DMA will stop. This bit can only be cleared by resetting the crypto block. + 29 + 1 + read-only - WORDS4 - WORDS4 + noError + No Error. 0 - WORDS8 - WORDS8 + error + Error. 1 - LPOL - LPOL - 21 + RDY + Ready. Crypto block ready for more data. + 30 1 + read-only - ACTIVEHI - ACTIVE HIGH + busy + Busy. 0 - ACTIVELO - ACTIVE LOW + ready + Ready. 1 - - PEN - PEN - 22 - 1 - - - - - FR - FRBUF - 0x18 - - - INT_EN - LCD Interrupt Enable Register. - 0x020 - - - UFLO - Under FLow Interupt Enable - 0 - 1 - - - ADRRDY - Address Ready Interupt Enable - 1 - 1 - - - VCI - VCI Interupt Enable - 2 - 1 - - - BERR - BERR Interupt Enable - 3 + + DONE + Done. One or more cryptographic calculations complete (logical OR of done flags). + 31 1 + read-only - STAT - LCD Status Register. - 0x024 - oneToClear + CIPHER_CTRL + Cipher Control Register. + 0x04 - UFLO - Under FLow Interupt Status + ENC + Encrypt. Select encryption or decryption of input data. 0 1 - read - Inactive - No interrupt pending + encrypt + Encrypt. 0 - Pending - Interrupt pending - 1 - - - - write - - Clear - Clears the interrupt flag + decrypt + Decrypt. 1 - ADRRDY - Address Ready Interupt Status + KEY + Load Key from crypto DMA. This bit is automatically cleared by hardware after the DMA has completed loading the key. When the DMA operation is done, it sets the appropriate crypto DMA Done flag. 1 1 - read - Inactive - No interrupt pending + complete + No operation/complete. 0 - Pending - Interrupt pending - 1 - - - - write - - Clear - Clears the interrupt flag + start + Start operation. 1 - VCI - VCI Interupt Status + SRC + Source of Random key. 2 - 1 + 2 - read - Inactive - No interrupt pending + cipherKey + User cipher key (0x4000_1060). 0 - Pending - Interrupt pending - 1 - - - - write + regFile + Key from battery-backed register file (0x4000_5000 to 0x4000_501F). + 2 + - Clear - Clears the interrupt flag - 1 + qspiKey_regFile + Key from battery-backed register file (0x4000_5020 to 0x4000_502F). + 3 - BERR - BERR Interupt Status - 3 - 1 + CIPHER + Cipher Operation Select. Symmetric Block Cipher algorithm selection or memory operation. + 4 + 3 - read - Inactive - No interrupt pending + dis + Disabled. 0 - Pending - Interrupt pending + aes128 + AES 128. 1 - - - write - Clear - Clears the interrupt flag - 1 + aes192 + AES 192. + 2 + + + aes256 + AES 256. + 3 + + + des + DES. + 4 + + + tdes + Triple DES. + 5 - LCDIDLE - LCD IDLE Staus + MODE + Mode Select. Mode of operation for block cipher or memory operation. DES/TDES cannot be used in CFB, OFB or CTR modes. 8 - 1 + 3 - BUSY - BUSY + ECB + ECB Mode. 0 - READY - READY + CBC + CBC Mode. 1 + + CFB + CFB (AES only). + 2 + + + OFB + OFB (AES only). + 3 + + + CTR + CTR (AES only). + 4 + - - - - 256 - 4 - PALETTE[%s] - Palette - 0x400 - - RED - Red Data for Pallet Entry. - 0 - 8 + HVC + H Vector Computation. + 11 + 1 + read-only - GREEN - Green Data for Pallet Entry. - 8 - 8 + DTYPE + GCM/CCM data type. + 12 + 1 + read-only - BLUE - Blue Data for Pallet Entry. + CCMM + CCM M Parameter. + 13 + 3 + read-only + + + CCML + CCM L Parameter. 16 - 8 + 3 + read-only - - - - - CTB - The Cryptographic Toolbox is a combination of cryptographic engines and a secure cryptographic accelerator (SCA) used to provide advanced cryptographic security. - 0x40001000 - - 0x00 - 0x1000 - registers - - - Crypto_Engine - Crypto Engine interrupt. - 27 - - - CRYPTO_CTRL - Crypto Control Register. - 0x00 - 0xC0000000 + HASH_CTRL + HASH Control Register. + 0x08 - RST - Reset. This bit is used to reset the crypto accelerator. All crypto internal states and related registers are reset to their default reset values. Control register such as CRYPTO_CTRL, CIPHER_CTRL, HASH_CTRL, CRC_CTRL, MAA_CTRL (with the exception of the STC bit), HASH_MSG_SZ_[3:0] and MAA_MAWS will retain their values. This bit will automatically clear itself after one cycle. + INIT + Initialize. Initializes hash registers with standard constants. 0 1 - reset_write - write - - reset - Starts reset operation. - 1 - - - - reset_read - read - reset_done - Reset complete. + nop + No operation/complete. 0 - busy - Reset in progress. + start + Start operation. 1 - INTR - Interrupt Enable. Generates an interrupt when done or error set. + XOR + XOR data with IV from cipher block. Useful when calculating HMAC to XOR the input pad and output pad. 1 1 dis - Disable + Disable. 0 en - Enable + Enable. 1 - SRC - Source Select. This bit selects the hash function and CRC generator input source. + HASH + Hash function selection. 2 - 1 + 3 - inputFIFO - Input FIFO + dis + Disabled. 0 - outputFIFO - Output FIFO + sha1 + SHA-1. 1 + + sha224 + SHA 224. + 2 + + + sha256 + SHA 256. + 3 + + + sha384 + SHA 384. + 4 + + + sha512 + SHA 512. + 5 + - - BSO - Byte Swap Output. Note. No byte swap will occur if there is not a full word. - 4 - 1 - - - BSI - Byte Swap Input. Note. No byte swap will occur if there is not a full word. - 5 - 1 - - - WAIT_EN - Wait Pin Enable. This can be used to hold off the crypto DMA until an external memory is ready. This is useful for transferring pages from NAND flash which may take several microseconds to become ready. - 6 - 1 - - WAIT_POL - Wait Pin Polarity. When the wait pin is enabled, this bit selects its active state. - 7 + LAST + Last Message Bit. This bit shall be set along with the HASH_MSG_SZ register prior to hashing the last 512 or 1024-bit block of the message data. It will allow automatic preprocessing of the last message padding, which includes the trailing bit 1, followed by the respective number of zero bits for the last block size and finally the message length represented in bytes. The bit will be automatically cleared at the same time the HASH DONE is set, designating the completion of the last message hash. + 5 1 - activeLo - Active Low. + noEffect + No Effect. 0 - activeHi - Active High. + lastMsgData + Last Message Data. 1 + + + + CRC_CTRL + CRC Control Register. + 0x0C + - WRSRC - Write FIFO Source Select. This field determines where data written to the write FIFO comes from. When data is written to the write FIFO, it is always written out the DMA. To decrypt or encrypt data, the write FIFO source should be set to the cipher output. To implement memcpy() or memset() functions, or to fill memory with random data, the write FIFO source should be set to the read FIFO. When calculating a HASH or CMAC, the write FIFO should be disabled. - 8 - 2 + CRC + Cyclic Redundancy Check Enable. The CRC cannot be enabled if the PRNG is enabled. + 0 + 1 - none - None. + dis + Disable. 0 - cipherOutput - Cipher Output. + en + Enable. 1 - - readFIFO - Read FIFO. - 2 - - RDSRC - Read FIFO Source Select. This field selects the source of the read FIFO. Typically, it is set to use the DMA. To implement a memset() function, the read FIFO DMA should be disabled. To fill memory with random data or to hash random numbers, the read FIFO source should be set to the random number generator. - 10 - 2 - - - dmaDisabled - DMA Disable. - 0 - - - dmaOrApb - DMA Or APB. - 1 - - - rng - RNG. - 2 - - - - - FLAG_MODE - Done Flag Mode. This bit configures the access behavior of the individual CRYPTO_CTRL Done flags (CRYPTO_CTRL[27:24]). This bit is cleared only on reset to limit upkeep, i.e. once set, it will remain set until a reset occurs. - 14 + MSB + MSB select. This bit selects the order of calculating CRC on data. + 1 1 - unres_wr - Unrestricted write (0 or 1) of CRYPTO_CTRL[27:24] flags. + lsbFirst + LSB First. 0 - res_wr - Access to CRYPTO_CTRL[27:24] are write 1 to clear/write 0 no effect. + msbFirst + MSB First. 1 - - DMADNEMSK - DMA Done Flag Mask. This bit masks the DMA_DONE flag from being used to generate the CRYPTO_CTRL.DONE flag, and this disables a DMA_DONE condition from generating and interrupt. The DMA_DONE flag itself is unaffected and still may be monitored. This allows more optimal interrupt-driven crypto operations using DMA. - 15 + + PRNG + Pseudo Random Number Generator Enable. If entropy is disabled, this outputs one byte of pseudo random data per clock cycle. If entropy is enabled, data is output at a rate of one bit per clock cycle. + 2 + 1 + + + ENT + Entropy Enable. If the PRNG is enabled, this mixes the high frequency ring oscillator with the LFSR. If the PRNG is disabled, the raw entropy data is output at a rate of 1 bit per clock. This makes it possible to characterize the quality of the entropy source. + 3 + 1 + + + HAM + Hamming Code Enable. Enable hamming code calculation. + 4 1 - - - not_used - DMA_DONE not used in setting CRYPTO_CTRL.DONE bit. - 0 - - - used - DMA_DONE used in setting CRYPTO_CTRL.DONE bit. - 1 - - - DMA_DONE - DMA Done. DMA write/read operation is complete. This bit must be cleared before starting a DMA operation. - 24 + HRST + Hamming Reset. Reset Hamming code ECC generator for next block. + 5 1 + write-only + write - notDone - Not Done. - 0 - - - done - Done. + reset + Starts reset operation. 1 - - GLS_DONE - Galois Done. FIFO is full and CRC or Hamming Code Generator is enabled. This bit must be cleared before starting a CRC operation Note that DMA_DONE must be polled instead of this bit to determine the end of DMA operation during the utilization of Hamming Code Generator. - 25 - 1 + + + + DMA_SRC + Crypto DMA Source Address. + 0x10 + + + ADDR + DMA Source Address. + 0 + 32 - - HSH_DONE - Hash Done. SHA operation is complete. This bit must be cleared before starting a HASH operation. - 26 - 1 + + + + DMA_DEST + Crypto DMA Destination Address. + 0x14 + + + ADDR + DMA Destination Address. + 0 + 32 - - CPH_DONE - Cipher Done. Either AES or DES encryption/decryption operation is complete. This bit must be cleared before starting a cipher operation. - 27 - 1 + + + + DMA_CNT + Crypto DMA Byte Count. + 0x18 + + + COUNT + DMA Byte Address. + 0 + 32 + + + + 4 + 4 + CRYPTO_DIN[%s] + Crypto Data Input. Data input can be written to this register instead of using the DMA. This register writes to the FIFO. This register occupies four successive words to allow the use of multi-store instructions. Words can be written to any location, they will be placed in the FIFO in the order they are written. The endian swap input control bit affects this register. + 0x20 + write-only + - ERR - AHB Bus Error. This bit is set when the DMA encounters a bus error during a read or write operation. Once this bit is set, the DMA will stop. This bit can only be cleared by resetting the crypto block. - 29 - 1 - read-only - - - noError - No Error. - 0 - - - error - Error. - 1 - - + DATA + Crypto Data Input. Input can be written to this register instead of using DMA. + 0 + 32 + + + + 4 + 4 + CRYPTO_DOUT[%s] + Crypto Data Output. Resulting data from cipher calculation. Data is placed in the lower words of these four registers depending on the algorithm. For block cipher modes, this register holds the result of most recent encryption or decryption operation. These registers are affected by the endian swap bits. + 0x30 + read-only + - RDY - Ready. Crypto block ready for more data. - 30 - 1 - read-only - - - busy - Busy. - 0 - - - ready - Ready. - 1 - - + DATA + Crypto Data Output. Resulting data from cipher calculation. Data is placed in the lower words of these four registers depending on algorithm. + 0 + 32 - - DONE - Done. One or more cryptographic calculations complete (logical OR of done flags). - 31 - 1 - read-only + + + + CRC_POLY + CRC Polynomial. The polynomial to be used for Galois Field calculations (CRC or LFSR) should be written to this register. This register is affected by the MSB control bit. + 0x40 + 0xEDB88320 + + + DATA + CRC Polynomial. The polynomial to be used for Galois Field calculations (CRC or LFSR) should be written to this register. This register is affected by the MSB control bit. + 0 + 32 - CIPHER_CTRL - Cipher Control Register. - 0x04 + CRC_VAL + CRC Value. This is the state for the Galois Field. This register holds the result of a CRC calculation or the current state of the LFSR. This register is affected by the MSB control bit. + 0x44 + 0xFFFFFFFF - ENC - Encrypt. Select encryption or decryption of input data. + VAL + CRC Value. This is the state for the Galois Field. This register holds the result of a CRC calculation or the current state of LFSR. This register is affected by the MSB control bit. + 0 + 32 + + + + + HAM_ECC + Hamming ECC Register. + 0x4C + + + ECC + Hamming ECC Value. These bits are the even parity of their corresponding bit groups. 0 + 16 + + + PAR + Parity. This is the parity of the entire array. + 16 1 - encrypt - Encrypt. + even + Even. 0 - decrypt - Decrypt. + odd + Odd. 1 - - KEY - Load Key from crypto DMA. This bit is automatically cleared by hardware after the DMA has completed loading the key. When the DMA operation is done, it sets the appropriate crypto DMA Done flag. - 1 - 1 - - - complete - No operation/complete. - 0 - - - start - Start operation. - 1 - - + + + + 4 + 4 + CIPHER_INIT[%s] + Initial Vector. For block cipher operations that use CBC, CFB, OFB, or CNTR modes, this register holds the initial value. This register is updated with each encryption or decryption operation. This register is affected by the endian swap bits. + 0x50 + + + IVEC + Initial Vector. For block cipher operations that use CBC, CFB, OFB, or CNTR modes, this register holds the initial value. This register is updated with each encryption or decryption operation. This register is affected by the endian swap bits. + 0 + 32 + + + + 8 + 4 + CIPHER_KEY[%s] + Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter key lengths. This register is affected by the endian swap input control bits. + 0x60 + write-only + - SRC - Source of Random key. - 2 - 2 - - - cipherKey - User cipher key (0x4000_1060). - 0 - - - regFile - Key from battery-backed register file (0x4000_5000 to 0x4000_501F). - 2 - - - qspiKey_regFile - Key from battery-backed register file (0x4000_5020 to 0x4000_502F). - 3 - - + KEY + Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter kye lengths. This register is affected by the endian swap input control bits. + 0 + 32 + + + + 16 + 4 + HASH_DIGEST[%s] + This register holds the calculated hash value. This register is affected by the endian swap bits. + 0x80 + - CIPHER - Cipher Operation Select. Symmetric Block Cipher algorithm selection or memory operation. - 4 - 3 - - - dis - Disabled. - 0 - - - aes128 - AES 128. - 1 - - - aes192 - AES 192. - 2 - - - aes256 - AES 256. - 3 - - - des - DES. - 4 - - - tdes - Triple DES. - 5 - - + HASH + This register holds the calculated hash value. This register is affected by the endian swap bits. + 0 + 32 + + + + 4 + 4 + HASH_MSG_SZ[%s] + Message Size. This register holds the lowest 32-bit of message size in bytes. + 0xC0 + - MODE - Mode Select. Mode of operation for block cipher or memory operation. DES/TDES cannot be used in CFB, OFB or CTR modes. - 8 - 3 - - - ECB - ECB Mode. - 0 - - - CBC - CBC Mode. - 1 - - - CFB - CFB (AES only). - 2 - - - OFB - OFB (AES only). - 3 - - - CTR - CTR (AES only). - 4 - - + MSGSZ + Message Size. This register holds the lowest 32-bit of message size in bytes. + 0 + 32 + + + + AAD_LENGTH_0 + .AAD Length Register 0. + 0xD0 + 0x0 + - HVC - H Vector Computation. - 11 - 1 - read-only + LENGTH + AAD length in bytes for AES GCM and CCM operations. + 0 + 32 + + + + AAD_LENGTH_1 + .AAD Length Register 1. + 0xD4 + 0x0 + - DTYPE - GCM/CCM data type. - 12 - 1 - read-only + LENGTH + AAD length in bytes for AES GCM and CCM operations. + 0 + 32 + + + + + PLD_LENGTH_0 + .PLD Length Register 0. + 0xD8 + 0x0 + + + LENGTH + PLD length in bytes for AES GCM and CCM operations. + 0 + 32 + + + + PLD_LENGTH_1 + .LENGTH. + 0xDC + 0x0 + - CCMM - CCM M Parameter. - 13 - 3 - read-only + LENGTH + PLD length in bytes for AES GCM and CCM operations. + 0 + 32 + + + + 4 + 4 + TAGMIC[%s] + TAG/MIC Registers. + 0xE0 + - CCML - CCM L Parameter. - 16 - 3 - read-only + LENGTH + TAG/MIC output for AES GCM and CCM operations. + 0 + 32 - HASH_CTRL - HASH Control Register. - 0x08 + SCA_CTRL0 + SCA Control 0 Register. + 0x100 - INIT - Initialize. Initializes hash registers with standard constants. + STC + Start Calculation. 0 1 + + + SCAIE + SCA Interrupt Enable. + 1 + 1 - nop - No operation/complete. + disable + Disable 0 - start - Start operation. + enable + Enable 1 - XOR - XOR data with IV from cipher block. Useful when calculating HMAC to XOR the input pad and output pad. - 1 + ABORT + Abort Operation. + 2 1 - - - dis - Disable. - 0 - - - en - Enable. - 1 - - - HASH - Hash function selection. - 2 - 3 - - - dis - Disabled. - 0 - - - sha1 - SHA-1. - 1 - - - sha224 - SHA 224. - 2 - - - sha256 - SHA 256. - 3 - - - sha384 - SHA 384. - 4 - - - sha512 - SHA 512. - 5 - - + ERMEM + Erase Cryptographic Memory. + 4 + 1 - LAST - Last Message Bit. This bit shall be set along with the HASH_MSG_SZ register prior to hashing the last 512 or 1024-bit block of the message data. It will allow automatic preprocessing of the last message padding, which includes the trailing bit 1, followed by the respective number of zero bits for the last block size and finally the message length represented in bytes. The bit will be automatically cleared at the same time the HASH DONE is set, designating the completion of the last message hash. + MANPARAM + ECC Parameter Source. 5 1 - - - noEffect - No Effect. - 0 - - - lastMsgData - Last Message Data. - 1 - - + + + HWKEY + Hardware Key Select. + 6 + 1 + + + OPCODE + SCA Opcode. + 8 + 5 + + + MODADDR + MODULO Address Offset. + 16 + 5 + + + ECCSIZE + ECC Size. + 24 + 2 - CRC_CTRL - CRC Control Register. - 0x0C + SCA_CTRL1 + SCA Advanced Control Register. + 0x104 - CRC - Cyclic Redundancy Check Enable. The CRC cannot be enabled if the PRNG is enabled. + MAN + SCA Mode. 0 1 - dis - Disable. + auto + Auto Mode 0 - en - Enable. + manual + Manual Mode 1 - MSB - MSB select. This bit selects the order of calculating CRC on data. + AUTOCARRY + Automatically propagate the carry for the next operation. 1 1 - - - lsbFirst - LSB First. - 0 - - - msbFirst - MSB First. - 1 - - - - PRNG - Pseudo Random Number Generator Enable. If entropy is disabled, this outputs one byte of pseudo random data per clock cycle. If entropy is enabled, data is output at a rate of one bit per clock cycle. + + PLUSONE + Enable Carry propagation for the next operation. 2 1 - - ENT - Entropy Enable. If the PRNG is enabled, this mixes the high frequency ring oscillator with the LFSR. If the PRNG is disabled, the raw entropy data is output at a rate of 1 bit per clock. This makes it possible to characterize the quality of the entropy source. + + RESSELECT + ALU Selection. + 3 + 2 + + + CARRYPOS + To set Carry location. + 8 + 10 + + + + + SCA_STAT + SCA Status Register. + 0x108 + + + BUSY + SCA Busy. + 0 + 1 + + + SCAIF + SCA Interrupt Flag. + 1 + 1 + + + PVF1 + Point 1 Verification Failed. + 2 + 1 + + + PVF2 + Point 2 Verification Failed. 3 1 - - HAM - Hamming Code Enable. Enable hamming code calculation. + + FSMERR + FSM Transition Error. 4 1 - HRST - Hamming Reset. Reset Hamming code ECC generator for next block. + COMPERR + EC Computation Error. 5 1 - write-only - - write - - reset - Starts reset operation. - 1 - - + + + MEMERR + SCA Memory Access Error. + 6 + 1 + + + CARRY + Carry on ongoing operation. + 8 + 1 + + + GTE2I2 + Modulo 2x Result. + 9 + 1 + + + ALUNEG1 + ALU 2 SubSign of the subtraction result for ALU_2. + 10 + 1 + + + ALUNEG2 + ALU 2 SubSign of the subtraction result for ALU_2. + 11 + 1 - DMA_SRC - Crypto DMA Source Address. - 0x10 + SCA_PPX_ADDR + PPX Coordinate Data Pointer Register. + 0x10C + 0x0 ADDR - DMA Source Address. + Point P Coordinate Data Pointer. 0 32 - DMA_DEST - Crypto DMA Destination Address. - 0x14 + SCA_PPY_ADDR + PPY Coordinate Data Pointer Register. + 0x110 + 0x0 ADDR - DMA Destination Address. + Point P Coordinate Data Pointer. 0 32 - DMA_CNT - Crypto DMA Byte Count. - 0x18 - - - COUNT - DMA Byte Address. - 0 - 32 - - - - - 4 - 4 - CRYPTO_DIN[%s] - Crypto Data Input. Data input can be written to this register instead of using the DMA. This register writes to the FIFO. This register occupies four successive words to allow the use of multi-store instructions. Words can be written to any location, they will be placed in the FIFO in the order they are written. The endian swap input control bit affects this register. - 0x20 - write-only - - - DATA - Crypto Data Input. Input can be written to this register instead of using DMA. - 0 - 32 - - - - - 4 - 4 - CRYPTO_DOUT[%s] - Crypto Data Output. Resulting data from cipher calculation. Data is placed in the lower words of these four registers depending on the algorithm. For block cipher modes, this register holds the result of most recent encryption or decryption operation. These registers are affected by the endian swap bits. - 0x30 - read-only - - - DATA - Crypto Data Output. Resulting data from cipher calculation. Data is placed in the lower words of these four registers depending on algorithm. - 0 - 32 - - - - - CRC_POLY - CRC Polynomial. The polynomial to be used for Galois Field calculations (CRC or LFSR) should be written to this register. This register is affected by the MSB control bit. - 0x40 - 0xEDB88320 + SCA_PPZ_ADDR + PPZ Coordinate Data Pointer Register. + 0x114 + 0x0 - DATA - CRC Polynomial. The polynomial to be used for Galois Field calculations (CRC or LFSR) should be written to this register. This register is affected by the MSB control bit. + ADDR + Point P Coordinate Data Pointer. 0 32 - CRC_VAL - CRC Value. This is the state for the Galois Field. This register holds the result of a CRC calculation or the current state of the LFSR. This register is affected by the MSB control bit. - 0x44 - 0xFFFFFFFF + SCA_PQX_ADDR + PQX Coordinate Data Pointer Register. + 0x118 + 0x0 - VAL - CRC Value. This is the state for the Galois Field. This register holds the result of a CRC calculation or the current state of LFSR. This register is affected by the MSB control bit. + ADDR + Point Q Coordinate Data Pointer. 0 32 - HAM_ECC - Hamming ECC Register. - 0x4C - - - ECC - Hamming ECC Value. These bits are the even parity of their corresponding bit groups. - 0 - 16 - - - PAR - Parity. This is the parity of the entire array. - 16 - 1 - - - even - Even. - 0 - - - odd - Odd. - 1 - - - - - - - 4 - 4 - CIPHER_INIT[%s] - Initial Vector. For block cipher operations that use CBC, CFB, OFB, or CNTR modes, this register holds the initial value. This register is updated with each encryption or decryption operation. This register is affected by the endian swap bits. - 0x50 + SCA_PQY_ADDR + PQY Coordinate Data Pointer Register. + 0x11C + 0x0 - IVEC - Initial Vector. For block cipher operations that use CBC, CFB, OFB, or CNTR modes, this register holds the initial value. This register is updated with each encryption or decryption operation. This register is affected by the endian swap bits. + ADDR + Point Q Coordinate Data Pointer. 0 32 - 8 - 4 - CIPHER_KEY[%s] - Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter key lengths. This register is affected by the endian swap input control bits. - 0x60 - write-only + SCA_PQZ_ADDR + PQZ Coordinate Data Pointer Register. + 0x120 + 0x0 - KEY - Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter kye lengths. This register is affected by the endian swap input control bits. + ADDR + Point Q Coordinate Data Pointer. 0 32 - 16 - 4 - HASH_DIGEST[%s] - This register holds the calculated hash value. This register is affected by the endian swap bits. - 0x80 + SCA_RDSA_ADDR + SCA RDSA Address Register. + 0x124 + 0x0 - HASH - This register holds the calculated hash value. This register is affected by the endian swap bits. + ADDR + The starting address of the R portion for R, S ECDSA signature. 0 32 - 4 - 4 - HASH_MSG_SZ[%s] - Message Size. This register holds the lowest 32-bit of message size in bytes. - 0xC0 + SCA_RES_ADDR + SCA Result Address Register. + 0x128 + 0x0 - MSGSZ - Message Size. This register holds the lowest 32-bit of message size in bytes. + ADDR + Starting address of result storage. 0 32 - AAD_LENGTH_0 - .AAD Length Register 0. - 0xD0 + SCA_OP_BUFF_ADDR + SCA Operation Buffer Address Register. + 0x12C 0x0 - LENGTH - AAD length in bytes for AES GCM and CCM operations. + ADDR + Starting address of operation buffer. 0 32 - AAD_LENGTH_1 - .AAD Length Register 1. - 0xD4 + SCA_MODDATA + SCA Modulo Data Input Register. + 0x130 0x0 - LENGTH - AAD length in bytes for AES GCM and CCM operations. + DATA + Used to load the SCA modulo for modular operations. 0 32 + + + + + DMA + DMA Controller Fully programmable, chaining capable DMA channels. + 0x40028000 + 32 + + 0x00 + 0x1000 + registers + + + DMA0 + 28 + + + DMA1 + 29 + + + DMA2 + 30 + + + DMA3 + 31 + + + DMA4 + 68 + + + DMA5 + 69 + + + DMA6 + 70 + + + DMA7 + 71 + + + DMA8 + 72 + + + DMA9 + 73 + + + DMA10 + 74 + + + DMA11 + 75 + + + DMA12 + 76 + + + DMA13 + 77 + + + DMA14 + 78 + + + DMA15 + 79 + + - PLD_LENGTH_0 - .PLD Length Register 0. - 0xD8 - 0x0 + CN + DMA Control Register. + 0x000 - LENGTH - PLD length in bytes for AES GCM and CCM operations. - 0 - 32 - - - - - PLD_LENGTH_1 - .LENGTH. - 0xDC - 0x0 - - - LENGTH - PLD length in bytes for AES GCM and CCM operations. - 0 - 32 - - - - - 4 - 4 - TAGMIC[%s] - TAG/MIC Registers. - 0xE0 - - - LENGTH - TAG/MIC output for AES GCM and CCM operations. - 0 - 32 - - - - - SCA_CTRL0 - SCA Control 0 Register. - 0x100 - - - STC - Start Calculation. + CH0_IEN + Channel 0 Interrupt Enable. 0 1 - - - SCAIE - SCA Interrupt Enable. - 1 - 1 - disable - Disable + dis + Disable. 0 - enable - Enable + en + Enable. 1 - - ABORT - Abort Operation. + + CH2_IEN + Channel 2 Interrupt Enable. 2 1 - - ERMEM - Erase Cryptographic Memory. + + CH3_IEN + Channel 3 Interrupt Enable. + 3 + 1 + + + CH4_IEN + Channel 4 Interrupt Enable. 4 1 - - MANPARAM - ECC Parameter Source. + + CH5_IEN + Channel 5 Interrupt Enable. 5 1 - - HWKEY - Hardware Key Select. + + CH6_IEN + Channel 6 Interrupt Enable. 6 1 - - OPCODE - SCA Opcode. - 8 - 5 - - - MODADDR - MODULO Address Offset. - 16 - 5 - - - ECCSIZE - ECC Size. - 24 - 2 + + CH7_IEN + Channel 7 Interrupt Enable. + 7 + 1 - SCA_CTRL1 - SCA Advanced Control Register. - 0x104 + INTR + DMA Interrupt Register. + 0x004 + read-only - MAN - SCA Mode. + CH0_IPEND + Channel Interrupt. To clear an interrupt, all active interrupt bits of the DMA_ST must be cleared. The interrupt bits are set only if their corresponding interrupt enable bits are set in DMA_CN. 0 1 - auto - Auto Mode + inactive + No interrupt is pending. 0 - manual - Manual Mode + pending + An interrupt is pending. 1 - - AUTOCARRY - Automatically propagate the carry for the next operation. - 1 - 1 - - - PLUSONE - Enable Carry propagation for the next operation. - 2 - 1 - - - RESSELECT - ALU Selection. - 3 - 2 - - - CARRYPOS - To set Carry location. - 8 - 10 - - - - - SCA_STAT - SCA Status Register. - 0x108 - - - BUSY - SCA Busy. - 0 - 1 - - - SCAIF - SCA Interrupt Flag. + + CH1_IPEND 1 1 - - PVF1 - Point 1 Verification Failed. + + CH2_IPEND 2 1 - - PVF2 - Point 2 Verification Failed. + + CH3_IPEND 3 1 - - FSMERR - FSM Transition Error. + + CH4_IPEND 4 1 - - COMPERR - EC Computation Error. + + CH5_IPEND 5 1 - - MEMERR - SCA Memory Access Error. + + CH6_IPEND 6 1 - - CARRY - Carry on ongoing operation. - 8 - 1 - - - GTE2I2 - Modulo 2x Result. - 9 - 1 - - - ALUNEG1 - ALU 2 SubSign of the subtraction result for ALU_2. - 10 - 1 - - - ALUNEG2 - ALU 2 SubSign of the subtraction result for ALU_2. - 11 + + CH7_IPEND + 7 1 - - SCA_PPX_ADDR - PPX Coordinate Data Pointer Register. - 0x10C - 0x0 - - - ADDR - Point P Coordinate Data Pointer. - 0 - 32 - - - - - SCA_PPY_ADDR - PPY Coordinate Data Pointer Register. - 0x110 - 0x0 - - - ADDR - Point P Coordinate Data Pointer. - 0 - 32 - - - - - SCA_PPZ_ADDR - PPZ Coordinate Data Pointer Register. - 0x114 - 0x0 - - - ADDR - Point P Coordinate Data Pointer. - 0 - 32 - - - - - SCA_PQX_ADDR - PQX Coordinate Data Pointer Register. - 0x118 - 0x0 - - - ADDR - Point Q Coordinate Data Pointer. - 0 - 32 - - - - - SCA_PQY_ADDR - PQY Coordinate Data Pointer Register. - 0x11C - 0x0 - - - ADDR - Point Q Coordinate Data Pointer. - 0 - 32 - - - - - SCA_PQZ_ADDR - PQZ Coordinate Data Pointer Register. - 0x120 - 0x0 - - - ADDR - Point Q Coordinate Data Pointer. - 0 - 32 - - - - - SCA_RDSA_ADDR - SCA RDSA Address Register. - 0x124 - 0x0 - - - ADDR - The starting address of the R portion for R, S ECDSA signature. - 0 - 32 - - - - - SCA_RES_ADDR - SCA Result Address Register. - 0x128 - 0x0 - - - ADDR - Starting address of result storage. - 0 - 32 - - - - - SCA_OP_BUFF_ADDR - SCA Operation Buffer Address Register. - 0x12C - 0x0 - - - ADDR - Starting address of operation buffer. - 0 - 32 - - - - - SCA_MODDATA - SCA Modulo Data Input Register. - 0x130 - 0x0 - - - DATA - Used to load the SCA modulo for modular operations. - 0 - 32 - - - - - - - - DMA - DMA Controller Fully programmable, chaining capable DMA channels. - 0x40028000 - 32 - - 0x00 - 0x1000 - registers - - - DMA0 - 28 - - - DMA1 - 29 - - - DMA2 - 30 - - - DMA3 - 31 - - - DMA4 - 68 - - - DMA5 - 69 - - - DMA6 - 70 - - - DMA7 - 71 - - - DMA8 - 72 - - - DMA9 - 73 - - - DMA10 - 74 - - - DMA11 - 75 - - - DMA12 - 76 - - - DMA13 - 77 - - - DMA14 - 78 - - - DMA15 - 79 - - - - CN - DMA Control Register. - 0x000 - - - CH0_IEN - Channel 0 Interrupt Enable. - 0 - 1 - - - dis - Disable. - 0 - - - en - Enable. - 1 - - - - - CH2_IEN - Channel 2 Interrupt Enable. - 2 - 1 - - - CH3_IEN - Channel 3 Interrupt Enable. - 3 - 1 - - - CH4_IEN - Channel 4 Interrupt Enable. - 4 - 1 - - - CH5_IEN - Channel 5 Interrupt Enable. - 5 - 1 - - - CH6_IEN - Channel 6 Interrupt Enable. - 6 - 1 - - - CH7_IEN - Channel 7 Interrupt Enable. - 7 - 1 - - - - - INTR - DMA Interrupt Register. - 0x004 - read-only - - - CH0_IPEND - Channel Interrupt. To clear an interrupt, all active interrupt bits of the DMA_ST must be cleared. The interrupt bits are set only if their corresponding interrupt enable bits are set in DMA_CN. - 0 - 1 - - - inactive - No interrupt is pending. - 0 - - - pending - An interrupt is pending. - 1 - - - - - CH1_IPEND - 1 - 1 - - - CH2_IPEND - 2 - 1 - - - CH3_IPEND - 3 - 1 - - - CH4_IPEND - 4 - 1 - - - CH5_IPEND - 5 - 1 - - - CH6_IPEND - 6 - 1 - - - CH7_IPEND - 7 - 1 - - - - - 8 - 0x20 - CH[%s] - DMA Channel registers. - dma_ch - 0x100 - read-write - - CFG - DMA Channel Configuration Register. - 0x000 - - - CHEN - Channel Enable. This bit is automatically cleared when DMA_ST.CH_ST changes from 1 to 0. - 0 - 1 - - - dis - Disable. - 0 - - - en - Enable. - 1 - - - - - RLDEN - Reload Enable. Setting this bit to 1 enables DMA_SRC, DMA_DST and DMA_CNT to be reloaded with their corresponding reload registers upon count-to-zero. This bit is also writeable in the Count Reload Register. Refer to the description on Buffer Chaining for use of this bit. If buffer chaining is not used this bit must be written with a 0. This bit should be set after the reload registers have been programmed. - 1 - 1 - - - dis - Disable. - 0 - - - en - Enable. - 1 - - - - - PRI - DMA Priority. - 2 - 2 - - - high - Highest Priority. - 0 - - - medHigh - Medium High Priority. - 1 - - - medLow - Medium Low Priority. - 2 - - - low - Lowest Priority. - 3 - - - - - REQSEL - Request Select. Select DMA request line for this channel. If memory-to-memory is selected, the channel operates as if the request is always active. - 4 - 6 - - - MEMTOMEM - Memory To Memory - 0x00 - - - SPI0RX - SPI0 RX - 0x01 - - - SPI1RX - SPI1 RX - 0x02 - - - UART0RX - UART0 RX - 0x04 - - - UART1RX - UART1 RX - 0x05 - - - I2C0RX - I2C0 RX - 0x07 - - - I2C1RX - I2C1 RX - 0x08 - - - ADC - Analog-to-Digital Converter Channel - 0x09 - - - I2C2RX - I2C2 RX - 0x0A - - - UART2RX - UART2 RX - 0x0E - - - SPI2RX - SPI2 RX - 0x0F - - - USBRXEP1 - USB Endpoint 1 RX - 0x11 - - - USBRXEP2 - USB Endpoint 2 RX - 0x12 - - - USBRXEP3 - USB Endpoint 3 RX - 0x13 - - - USBRXEP4 - USB Endpoint 4 RX - 0x14 - - - USBRXEP5 - USB Endpoint 5 RX - 0x15 - - - USBRXEP6 - USB Endpoint 6 RX - 0x16 - - - USBRXEP7 - USB Endpoint 7 RX - 0x17 - - - USBRXEP8 - USB Endpoint 8 RX - 0x18 - - - USBRXEP9 - USB Endpoint 9 RX - 0x19 - - - USBRXEP10 - USB Endpoint 10 RX - 0x1A - - - USBRXEP11 - USB Endpoint 11 RX - 0x1B - - - SPI0TX - SPI0 TX - 0x21 - - - SPI1TX - SPI1 TX - 0x22 - - - UART0TX - UART0 TX - 0x24 - - - UART1TX - UART1 TX - 0x25 - - - I2C0TX - I2C0 TX - 0x27 - - - I2C1TX - I2C1 TX - 0x28 - - - I2C2TX - I2C2 TX - 0x2A - - - UART2TX - UART2 TX - 0x2E - - - SPI2TX - SPI3 TX - 0x2F - - - USBTXEP1 - USB Endpoint 1 TX - 0x31 - - - USBTXEP2 - USB Endpoint 2 TX - 0x32 - - - USBTXEP3 - USB Endpoint 3 TX - 0x33 - - - USBTXEP4 - USB Endpoint 4 TX - 0x34 - - - USBTXEP5 - USB Endpoint 5 TX - 0x35 - - - USBTXEP6 - USB Endpoint 6 TX - 0x36 - - - USBTXEP7 - USB Endpoint 7 TX - 0x37 - - - USBTXEP8 - USB Endpoint 8 TX - 0x38 - - - USBTXEP9 - USB Endpoint 9 TX - 0x39 - - - USBTXEP10 - USB Endpoint 10 TX - 0x3A - - - USBTXEP11 - USB Endpoint 11 TX - 0x3B - - - - - REQWAIT - Request Wait Enable. When enabled, delay timer start until DMA request transitions from active to inactive. - 10 - 1 - - - dis - Disable. - 0 - - - en - Enable. - 1 - - - - - TOSEL - Timeout Period Select. - 11 - 3 - - - to4 - Timeout of 3 to 4 prescale clocks. - 0 - - - to8 - Timeout of 7 to 8 prescale clocks. - 1 - - - to16 - Timeout of 15 to 16 prescale clocks. - 2 - - - to32 - Timeout of 31 to 32 prescale clocks. - 3 - - - to64 - Timeout of 63 to 64 prescale clocks. - 4 - - - to128 - Timeout of 127 to 128 prescale clocks. - 5 - - - to256 - Timeout of 255 to 256 prescale clocks. - 6 - - - to512 - Timeout of 511 to 512 prescale clocks. - 7 - - - - - PSSEL - Pre-Scale Select. Selects the Pre-Scale divider for timer clock input. - 14 - 2 - - - dis - Disable timer. - 0 - - - div256 - hclk / 256. - 1 - - - div64k - hclk / 64k. - 2 - - - div16M - hclk / 16M. - 3 - - - - - SRCWD - Source Width. In most cases, this will be the data width of each AHB transactions. However, the width will be reduced in the cases where DMA_CNT indicates a smaller value. - 16 - 2 - - - byte - Byte. - 0 - - - halfWord - Halfword. - 1 - - - word - Word. - 2 - - - - - SRCINC - Source Increment Enable. This bit enables DMA_SRC increment upon every AHB transaction. This bit is forced to 0 for DMA receive from peripherals. - 18 - 1 - - - dis - Disable. - 0 - - - en - Enable. - 1 - - - - - DSTWD - Destination Width. Indicates the width of the each AHB transactions to the destination peripheral or memory. (The actual width may be less than this if there are insufficient bytes in the DMA FIFO for the full width). - 20 - 2 - - - byte - Byte. - 0 - - - halfWord - Halfword. - 1 - - - word - Word. - 2 - - - - - DSTINC - Destination Increment Enable. This bit enables DMA_DST increment upon every AHB transaction. This bit is forced to 0 for DMA transmit to peripherals. - 22 - 1 - - - dis - Disable. - 0 - - - en - Enable. - 1 - - - - - BRST - Burst Size. The number of bytes to be transferred into and out of the DMA FIFO in a single burst. Burst size equals 1 + value stored in this field. - 24 - 5 - - - CHDIEN - Channel Disable Interrupt Enable. When enabled, the IPEND will be set to 1 whenever CH_ST changes from 1 to 0. - 30 - 1 - - - dis - Disable. - 0 - - - en - Enable. - 1 - - - - - CTZIEN - Count-to-zero Interrupts Enable. When enabled, the IPEND will be set to 1 whenever a count-to-zero event occurs. - 31 - 1 - - - dis - Disable. - 0 - - - en - Enable. - 1 - - - - - - - ST - DMA Channel Status Register. - 0x004 - - - CH_ST - Channel Status. This bit is used to indicate to the programmer when it is safe to change the configuration, address, and count registers for the channel. Whenever this bit is cleared by hardware, the DMA_CFG.CHEN bit is also cleared (if not cleared already). - 0 - 1 - read-only - - - dis - Disable. - 0 - - - en - Enable. - 1 - - - - - IPEND - Channel Interrupt. - 1 - 1 - read-only - - - inactive - No interrupt is pending. - 0 - - - pending - An interrupt is pending. - 1 - - - - - CTZ_ST - Count-to-Zero (CTZ) Event Interrupt Flag - 2 - 1 - oneToClear - - - RLD_ST - Reload Event Interrupt Flag. - 3 - 1 - oneToClear - - - BUS_ERR - Bus Error. Indicates that an AHB abort was received and the channel has been disabled. - 4 - 1 - oneToClear - - - TO_ST - Time-Out Event Interrupt Flag. - 6 - 1 - oneToClear - - - - - SRC - Source Device Address. If SRCINC=1, the counter bits are incremented by 1,2, or 4, depending on the data width of each AHB cycle. For peripheral transfers, some or all of the actual address bits are fixed. If SRCINC=0, this register remains constant. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with the contents of DMA_SRC_RLD. - 0x008 - - - SRC - 0 - 32 - - - - - DST - Destination Device Address. For peripheral transfers, some or all of the actual address bits are fixed. If DSTINC=1, this register is incremented on every AHB write out of the DMA FIFO. They are incremented by 1, 2, or 4, depending on the data width of each AHB cycle. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with DMA_DST_RLD. - 0x00C - - - DST - 0 - 32 - - - - - CNT - DMA Counter. The user loads this register with the number of bytes to transfer. This counter decreases on every AHB cycle into the DMA FIFO. The decrement will be 1, 2, or 4 depending on the data width of each AHB cycle. When the counter reaches 0, a count-to-zero condition is triggered. - 0x010 - - - CNT - DMA Counter. - 0 - 24 - - - - - SRC_RLD - Source Address Reload Value. The value of this register is loaded into DMA0_SRC upon a count-to-zero condition. - 0x014 - - - SRC_RLD - Source Address Reload Value. - 0 - 31 - - - - - DST_RLD - Destination Address Reload Value. The value of this register is loaded into DMA0_DST upon a count-to-zero condition. - 0x018 - - - DST_RLD - Destination Address Reload Value. - 0 - 31 - - - - - CNT_RLD - DMA Channel Count Reload Register. - 0x01C - - - CNT_RLD - Count Reload Value. The value of this register is loaded into DMA0_CNT upon a count-to-zero condition. - 0 - 24 - - - RLDEN - Reload Enable. This bit should be set after the address reload registers have been programmed. This bit is automatically cleared to 0 when reload occurs. - 31 - 1 - - - dis - Disable. - 0 - - - en - Enable. - 1 - - - - - - - - - - - EMAC - 10/100 Ethernet MAC. - 0x4004F000 - - 0 - 0x1000 - registers - - - EMAC - EMAC IRQ - 64 - - - - CN - Network Control Register. - 0x00 - 0x00 - - - LB - Loopback. - 0 - 1 - read-write - - - LBL - Loopback local. - 1 - 1 - read-write - - - RXEN - Receive Enable. - 2 - 1 - read-write - - - TXEN - Transmit Enable. - 3 - 1 - read-write - - - MPEN - Management Port Enable. - 4 - 1 - read-write - - - CLST - Clear Statistics. - 5 - 1 - write-only - - - INCST - Increment Statistics. - 6 - 1 - write-only - - - WREN - Write enable for statistics registers. - 7 - 1 - read-write - - - BP - Back pressure. - 8 - 1 - read-write - - - TXSTART - Transmission start. - 9 - 1 - write-only - - - TXHALT - Transmit halt. - 10 - 1 - write-only - - - TXPF - Transmit pause frame. - 11 - 1 - write-only - - - TXZQPF - Transmit zero quantum pause frame. - 12 - 1 - write-only - - - - - CFG - Network Configuration Register. - 0x04 - - - SPEED - Speed Select. - 0 - 1 - read-write - - - FULLDPLX - Full Duplex. If set to 1 the transmit block ignores the state of collision and carrier sense and allows Rx while transmitting. - 1 - 1 - read-write - - - BITRATE - Bit Rate. Writing 1 to this bit configures the interface for serial operation. - 2 - 1 - read-write - - - JUMBOFR - Jumbo Frames. Writing 1 to this bit enables jumbo frames of up to 10,240 bytes to be accepted. - 3 - 1 - read-write - - - COPYAF - Copy All Frames. If 1, all valid frames will be received. - 4 - 1 - read-write - - - NOBC - No Broadcast. If 1, frames addressed to the broadcast address of all ones will not be received. - 5 - 1 - write-only - - - MHEN - Multicast Hash Enable. If 1, multicast frames will be received when the 6 bit hash function of the destination address points to a bit that is set in the hash register. - 6 - 1 - write-only - - - UHEN - Unicast Hash Enable. If 1, unicast frames will be received when the 6 bit hash function of the destination address points to a bit that is set in the hash register. - 7 - 1 - read-write - - - RXFR - Receive 1536 Byte Frames. Writing 1 to this bit means the MAC receives packets up to 1536 bytes in length. Normally the MAC rejects any packet above 1518 bytes - 8 - 1 - read-write - - - MDCCLK - MDC Frequency. Set according to PCLK speed. This field determines by what number PCLK is divided to generate MDC. - 10 - 2 - write-only - - - div8 - PCLK up to 20MHz - 0 - - - div16 - PCLK up to 40MHz - 1 - - - div32 - PCLK up to 80MHz - 2 - - - div64 - PCLK up to 160MHz - 3 - - - - - RTTST - Retry Test. Must be set to zero for normal operation. If set to 1, the back-off between collisions is always one slot time. - 12 - 1 - write-only - - - PAUSEEN - Pause Enable. If 1, Ethernet packet transmission pauses when a valid pause packet is received. - 13 - 1 - write-only - - - RXBUFFOFS - Receive buffer offset. These bits indicate the number of bytes by which the received data is offset from the start of the first receive buffer. - 14 - 2 - write-only - - - RXLFCEN - Receive length field checking enable. If 1, packets with measured lengths shorter than their length fields are discarded. Packets containing a type ID in bytes 13 and 14 (length/type field >=0600) are not counted as length errors. - 16 - 1 - write-only - - - DCRXFCS - Discard receive FCS. If 1, the FCS field of received frames will not be copied to memory. - 17 - 1 - write-only - - - HDPLXRXEN - Enable packets to be received in half-duplex mode while transmitting. - 18 - 1 - write-only - - - IGNRXFCS - Ignore RX FCS. If 1, packets with FCS/CRC errors are not rejected and no FCS error statistics are counted. For normal operation, this bit must be set to 0. - 19 - 1 - write-only - - - - - STATUS - Network Status Register. - 0x08 - read-only - - - LINK - LINK pin status. Returns status of EMAC_LINK pin. - 0 - 1 - read-only - - - MDIO - MDIO pin status. Returns status of the EMAC_MDIO pin. Use the PHY maintenance register for reading managed frames rather than this bit. - 1 - 1 - read-only - - - IDLE - PHY management logic status. - 2 - 1 - read-only - - - - - TX_ST - Transmit Status Register. - 0x14 - - - UBR - Used Bit Read. Set when a transmit buffer descriptor is read with its used bit set. Write 1 to clear this bit. - 0 - 1 - read-write - - - COLS - Collision Occurred. Set when a collision occurs. Write 1 to clear this bit. - 1 - 1 - read-write - - - RTYLIM - Retry Limit Exceeded. Set when the retry limit has been exceeded. Write 1 to clear this bit. - 2 - 1 - read-write - - - TXGO - Transmit Go. If 1, transmit is active. - 3 - 1 - read-write - - - BEMF - Buffers Exhausted Mid Frame. If the buffers run out during transmission of a frame then transmission stops, FCS shall be bad and EMAC_TXER asserted. Write 1 to clear this bit. - 4 - 1 - read-write - - - TXCMPL - Transmit Complete. Set when a frame has been transmitted. Write 1 to clear this bit. - 5 - 1 - read-write - - - TXUR - Transmit Underrun. Set when the MAC transmit FIFO was read while was empty. If this happens the transmitter forces bad. Write 1 to clear this bit. - 6 - 1 - read-write - - - - - RXBUF_PTR - Receive Buffer Queue Pointer Register. - 0x18 - - - RXBUF - Receive buffer queue pointer. Written with the address of the start of the receive queue, reads as a pointer to the current buffer being used. - 2 - 30 - read-write - - - - - TXBUF_PTR - Transmit Buffer Queue Pointer Register. - 0x1C - - - TXBUF - Transmit buffer queue pointer. Written with the address of the start of the transmit queue, reads as a pointer to the first buffer of the frame being transmitted or about to be transmitted. - 2 - 30 - read-write - - - - - RX_ST - Receive Status Register. - 0x20 - - - BNA - Buffer Not Available. An attempt was made to get a new buffer and the pointer indicated that it was owned by the processor. The DMA will reread the pointer each time a new frame starts until a valid pointer is found. This bit will be set at each attempt that fails even if it has not had a successful pointer read since it has been cleared. Write 1 to clear this bit. - 0 - 1 - read-write - - - FR - Frame Received. One or more frames have been received and placed in memory. Write 1 to clear this bit. - 1 - 1 - read-write - - - RXOR - Receive Overrun. The DMA block was unable to store the receive frame to memory. Either because the AHB bus was not granted in time or because a not OK hresp was returned. The buffer will be recovered if this happens. Write 1 to clear this bit. - 2 - 1 - read-write - - - - - INT_ST - Interrupt Status Register. - 0x24 - - - MPS - Management Packet Sent Interrupt Status. The PHY maintenance register has completed its operation. Cleared when read. - 0 - 1 - read-write - - - RXCMPL - Receive Complete Interrupt Status. Set when a frame has been stored in memory. Cleared when read. - 1 - 1 - read-write - - - RXUBR - RX Used Bit Read Interrupt Status. Set when a receive buffer descriptor is read with its used bit set. Cleared when read. - 2 - 1 - read-write - - - TXUBR - TX Used Bit Read Interrupt Status. Set when a transmit buffer descriptor is read with its used bit set. Cleared when read - 3 - 1 - read-write - - - TXUR - Ethernet Transmit Underrun Interrupt Status. Set when the MAC transmit FIFO was read while was empty. If this happens the transmitter forces bad CRC and forces EMAC_TXER high. Cleared when read. - 4 - 1 - read-write - - - RLE - Retry Limit Exceeded Interrupt Status. Transmit error. Cleared when read. - 5 - 1 - read-write - - - TXERR - Transmit Buffers Exhausted In Mid-frame Interrupt Status. Transmit error. Cleared when read. - 6 - 1 - read-write - - - TXCMPL - Transmit Complete Interrupt Status. Set when a frame has been transmitted. Cleared when read. - 7 - 1 - read-write - - - LC - Link Change Interrupt Status. Set when the external link signal changes. Cleared when read. - 9 - 1 - read-write - - - RXOR - Receive Overrun Interrupt Status. Set when the receive overrun status bit gets set. Cleared when read. - 10 - 1 - read-write - - - HRESPNO - hresp not OK Interrupt Status. Set when the DMA block sees hresp not OK. Cleared when read. - 11 - 1 - read-write - - - PPR - Pause Packet Received Interrupt Status. Indicates a valid pause packet has been received. Cleared when read. - 12 - 1 - read-write - - - PTZ - Pause Time Zero Interrupt Status. Set when the MAC Pause Time register (MAC_PT) decrements to zero. Cleared when read. - 13 - 1 - read-write - - - - - INT_EN - Interrupt Enable Register. - 0x28 - write-only - - - MPS - Management Packet Sent Interrupt Enable - 0 - 1 - write-only - - - RXCMPL - Receive Complete Interrupt Enable - 1 - 1 - write-only - - - RXUBR - RX Used Bit Read Interrupt Enable - 2 - 1 - write-only - - - TXUBR - TX Used Bit Read Interrupt Enable - 3 - 1 - write-only - - - TXUR - Ethernet Transmit Underrun Interrupt Enable - 4 - 1 - write-only - - - RLE - Retry Limit Exceeded Interrupt Enable - 5 - 1 - write-only - - - TXERR - Transmit Buffers Exhausted In Mid-frame Interrupt Enable - 6 - 1 - write-only - - - TXCMPL - Transmit Complete Interrupt Enable - 7 - 1 - write-only - - - LC - Link Change Interrupt Enable - 9 - 1 - write-only - - - RXOR - Receive Overrun Interrupt Enable - 10 - 1 - write-only - - - HRESPNO - hresp not OK Interrupt Enable - 11 - 1 - write-only - - - PPR - Pause Packet Received Interrupt Enable - 12 - 1 - write-only - - - PTZ - Pause Time Zero Interrupt Enable - 13 - 1 - write-only - - - - - INT_DIS - Interrupt Disable Register. - 0x2C - write-only - - - MPS - Management Packet Sent Interrupt Disable - 0 - 1 - write-only - - - RXCMPL - Receive Complete Interrupt Disable - 1 - 1 - write-only - - - RXUBR - RX Used Bit Read Interrupt Disable - 2 - 1 - write-only - - - TXUBR - TX Used Bit Read Interrupt Disable - 3 - 1 - write-only - - - TXUR - Ethernet Transmit Underrun Interrupt Disable - 4 - 1 - write-only - - - RLE - Retry Limit Exceeded Interrupt Disable - 5 - 1 - write-only - - - TXERR - Transmit Buffers Exhausted In Mid-frame Interrupt Disable - 6 - 1 - write-only - - - TXCMPL - Transmit Complete Interrupt Disable - 7 - 1 - write-only - - - LC - Link Change Interrupt Disable - 9 - 1 - write-only - - - RXOR - Receive Overrun Interrupt Disable - 10 - 1 - write-only - - - HRESPNO - hresp not OK Interrupt Disable - 11 - 1 - write-only - - - PPR - Pause Packet Received Interrupt Disable - 12 - 1 - write-only - - - PTZ - Pause Time Zero Interrupt Disable - 13 - 1 - write-only - - - - - INT_MASK - Interrupt Mask Register. - 0x30 - read-only - - - MPS - Management Packet Sent Interrupt Mask - 0 - 1 - read-only - - - RXCMPL - Receive Complete Interrupt Mask - 1 - 1 - read-only - - - RXUBR - RX Used Bit Read Interrupt Mask - 2 - 1 - read-only - - - TXUBR - TX Used Bit Read Interrupt Mask - 3 - 1 - read-only - - - TXUR - Ethernet Transmit Underrun Interrupt Mask - 4 - 1 - read-only - - - RLE - Retry Limit Exceeded Interrupt Mask - 5 - 1 - read-only - - - TXERR - Transmit Buffers Exhausted In Mid-frame Interrupt Mask - 6 - 1 - read-only - - - TXCMPL - Transmit Complete Interrupt Mask - 7 - 1 - read-only - - - LC - Link Change Interrupt Mask - 9 - 1 - read-only - - - RXOR - Receive Overrun Interrupt Mask - 10 - 1 - read-only - - - HRESPNO - hresp not OK Interrupt Mask - 11 - 1 - read-only - - - PPR - Pause Packet Received Interrupt Mask - 12 - 1 - read-only - - - PTZ - Pause Time Zero Interrupt Mask - 13 - 1 - read-only - - - - - PHY_MT - PHY Maintenance Register. - 0x34 - - - DATA - PHY Data. For a write operation this field is the data to be written to the PHY. - 0 - 16 - read-write - - - REGADDR - Register Address. Specifies the register in the PHY to access. - 18 - 5 - read-write - - - PHYADDR - PHY Address. Specifies the PHY to access. - 23 - 5 - read-write - - - OP - Operation - 28 - 2 - read-write - - - write - Write - 1 - - - read - Read - 2 - - - - - SOP - TBD - 30 - 2 - read-write - - - - - PT - Pause Time Register. - 0x38 - read-only - - - TIME - Pause Time. Stores the current value of the pause time register, which is decremented every 512 bit times. - 0 - 16 - read-only - - - - - PFR - Pause Frame Received OK. - 0x3C - - - PFR - Pause Frames Received OK. A 16-bit register counting the number of good pause frames received. - 0 - 16 - read-write - - - - - FTOK - Frames Transmitted OK. - 0x40 - - - FTOK - Frames Transmitted OK. A 32-bit register counting the number of frames successfully transmitted, i.e. no underrun and not too many retries. - 0 - 32 - read-write - - - - - SCF - Single Collision Frames. - 0x44 - - - SCF - Single Collision Frames. A 16-bit register counting the number of frames experiencing a single collision before being successfully transmitted, i.e. no underrun. - 0 - 16 - read-write - - - - - MCF - Multiple Collision Frames. - 0x48 - - - MCF - Multiple Collision Frames. A 16-bit register counting the number of frames experiencing between two and fifteen collisions prior to being successfully transmitted, i.e. no underrun and not too many retries. - 0 - 16 - read-write - - - - - FROK - Fames Received OK. - 0x4C - - - FROK - Frames Received OK. A 24-bit register counting the number of good packets received - 0 - 24 - read-write - - - - - FCS_ERR - Frame Check Sequence Errors. - 0x50 - - - FCSERR - Frame Check Sequence Errors. - 0 - 8 - read-write - - - - - ALGN_ERR - Alignment Errors. - 0x54 - - - ALGNERR - Alignment Errors. - 0 - 8 - read-write - - - - - DFTXF - Deferred Transmission Frames. - 0x58 - - - DFTXF - Deferred Transmission Frames. A 16-bit register counting the number of packets experiencing deferral due to carrier sense being active on their first attempt at transmission - 0 - 16 - read-write - - - - - LC - Late Collisions. - 0x5C - - - LC - Late Collisions. An 8-bit register counting the number of packets that experience a collision after the slot time (512 bits) has expired. - 0 - 8 - read-write - - - - - EC - Excessive Collisions. - 0x60 - - - EC - Excessive Collisions. An 8-bit register counting the number of packets that failed to be transmitted because they experienced 16 collisions. - 0 - 8 - read-write - - - - - TUR_ERR - Transmit Underrun Errors. - 0x64 - - - TURERR - Transmit Underrun Error. An 8-bit register counting the number of packets not transmitted due to a transmit FIFO underrun. - 0 - 8 - read-write - - - - - CS_ERR - Carrier Sense Errors. - 0x68 - - - CSERR - An 8-bit register counting the number of packets transmitted where carrier sense was not seen during transmission or where carrier sense was deasserted after being asserted in a transmit packet without collision (no underrun). - 0 - 8 - read-write - - - - - RR_ERR - Receive Resource Errors. - 0x6C - - - RRERR - Receive Resource Errors. A 16 bit register counting the number of frames that were address matched but could not be copied to memory because no receive buffer was available. - 0 - 16 - read-write - - - - - ROR_ERR - Receive Overrun Errors. - 0x70 - - - RORERR - Receive Overruns. An 8 bit register counting the number of frames that are address recognized but were not copied to memory due to a receive DMA overrun. - 0 - 8 - read-write - - - - - RS_ERR - Receive Symbol Errors. - 0x74 - - - RSERR - Receive Symbol Errors. An 8-bit register counting the number of packets that had EMAC_RXER asserted during reception. - 0 - 8 - read-write - - - - - EL_ERR - Excessive Length Errors. - 0x78 - - - ELERR - Excessive Length Errors. An 8-bit register counting the number of packets received exceeding 1518 bytes in length (1536 if RXFR is set in the MAC_CFG register; - 0 - 8 - read-write - - - - - RJ - Receive Jabber. - 0x7C - - - RJERR - Receive Jabbers. An 8-bit register counting the number of packets received exceeding 1518 bytes in length (1536 if RXFR is set in the MAC_CFG register; - 0 - 8 - read-write - - - - - USF - Undersize Frames. - 0x80 - - - USF - Undersize Frames. An 8-bit register counting the number of packets received less than 64 bytes in length but do not have either a CRC error, an alignment error or a receive symbol error. - 0 - 8 - read-write - - - - - SQE_ERR - SQE Test Errors. - 0x84 - - - SQEERR - SQE Test Errors. An 8-bit register counting the number of packets where collision was not asserted within 96 bit times (an interframe gap) of EMAC_TXEN being deasserted in half duplex mode. - 0 - 8 - read-write - - - - - RLFM - Received Length Field Mismatch. - 0x88 - - - RLFM - Receive length field mismatch - 0 - 8 - read-write - - - - - TPF - Transmitted Pause Frames. - 0x8C - - - TPF - Transmitted Pause Frames. A 16-bit register counting the number of pause packets transmitted. - 0 - 16 - read-write - - - - - HASHL - Hash Register Bottom [31:0]. - 0x90 - - - HASH - Bits 31:0 of the hash address register. See Hash Addressing - 0 - 32 - read-write - - - - - HASHH - Hash Register top [63:32]. - 0x94 - - - HASH - Bits 63:32 of the hash address register. See Hash Addressing - 0 - 32 - read-write - - - - - SA1L - Specific Address 1 Bottom. - 0x98 - - - ADDR - MAC Specific Address 1 [31:0]. Least significant bits of the MAC specific address 1, i.e. bits 31:0. This field is used for transmission of pause packets - 0 - 32 - read-write - - - - - SA1H - Specific Address 1 Top. - 0x9C - - - ADDR - MAC Specific Address 1 [47:32]. Most significant bits of the MAC specific address 1, i.e. bits 47:32. - 0 - 16 - read-write - - - - - SA2L - Specific Address 2 Bottom. - 0xA0 - - - ADDR - MAC Specific Address 2 [31:0]. Least significant bits of the MAC specific address 2, i.e. bits 31:0. This field is used for transmission of pause packets - 0 - 32 - read-write - - - - - SA2H - Specific Address 2 Top. - 0xA4 - - - ADDR - MAC Specific Address 2 [47:32]. Most significant bits of the MAC specific address 2, i.e. bits 47:32. - 0 - 16 - read-write - - - - - SA3L - Specific Address 3 Bottom. - 0xA8 - - - ADDR - MAC Specific Address 3 [31:0]. Least significant bits of the MAC specific address 3, i.e. bits 31:0. This field is used for transmission of pause packets - 0 - 32 - read-write - - - - - SA3H - Specific Address 3 Top. - 0xAC - - - ADDR - MAC Specific Address 3 [47:32]. Most significant bits of the MAC specific address 3, i.e. bits 47:32. - 0 - 16 - read-write - - - - - SA4L - Specific Address 4 Bottom. - 0xB0 - - - ADDR - MAC Specific Address 4 [31:0]. Least significant bits of the MAC specific address 4, i.e. bits 31:0. This field is used for transmission of pause packets - 0 - 32 - read-write - - - - - SA4H - Specific Address 4 Top. - 0xB4 - - - ADDR - MAC Specific Address 4 [47:32]. Most significant bits of the MAC specific address 4, i.e. bits 47:32. - 0 - 16 - read-write - - - - - TID_CK - Type ID Checking. - 0xB8 - - - TID - Type ID Checking. For use in comparisons with received frames TypeID/Length field. - 0 - 16 - read-write - - - - - TPQ - Transmit Pause Quantum. - 0xBC - - - TPQ - Transmit Pause Quantum. Used in hardware generation of transmitted pause packets as value for pause quantum - 0 - 16 - read-write - - - - - REV - Revision register. - 0xFC - read-only - - - REV - Revision Reference. Fixed two byte value specific to revision of design. - 0 - 16 - read-only - - - PART - Part Reference. For Ethernet MAC design, this is fixed at 0x01. - 16 - 16 - read-only - - - + + 8 + 0x20 + CH[%s] + DMA Channel registers. + dma_ch + 0x100 + read-write + + CFG + DMA Channel Configuration Register. + 0x000 + + + CHEN + Channel Enable. This bit is automatically cleared when DMA_ST.CH_ST changes from 1 to 0. + 0 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + RLDEN + Reload Enable. Setting this bit to 1 enables DMA_SRC, DMA_DST and DMA_CNT to be reloaded with their corresponding reload registers upon count-to-zero. This bit is also writeable in the Count Reload Register. Refer to the description on Buffer Chaining for use of this bit. If buffer chaining is not used this bit must be written with a 0. This bit should be set after the reload registers have been programmed. + 1 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + PRI + DMA Priority. + 2 + 2 + + + high + Highest Priority. + 0 + + + medHigh + Medium High Priority. + 1 + + + medLow + Medium Low Priority. + 2 + + + low + Lowest Priority. + 3 + + + + + REQSEL + Request Select. Select DMA request line for this channel. If memory-to-memory is selected, the channel operates as if the request is always active. + 4 + 6 + + + MEMTOMEM + Memory To Memory + 0x00 + + + SPI0RX + SPI0 RX + 0x01 + + + SPI1RX + SPI1 RX + 0x02 + + + UART0RX + UART0 RX + 0x04 + + + UART1RX + UART1 RX + 0x05 + + + I2C0RX + I2C0 RX + 0x07 + + + I2C1RX + I2C1 RX + 0x08 + + + ADC + Analog-to-Digital Converter Channel + 0x09 + + + I2C2RX + I2C2 RX + 0x0A + + + UART2RX + UART2 RX + 0x0E + + + SPI2RX + SPI2 RX + 0x0F + + + USBRXEP1 + USB Endpoint 1 RX + 0x11 + + + USBRXEP2 + USB Endpoint 2 RX + 0x12 + + + USBRXEP3 + USB Endpoint 3 RX + 0x13 + + + USBRXEP4 + USB Endpoint 4 RX + 0x14 + + + USBRXEP5 + USB Endpoint 5 RX + 0x15 + + + USBRXEP6 + USB Endpoint 6 RX + 0x16 + + + USBRXEP7 + USB Endpoint 7 RX + 0x17 + + + USBRXEP8 + USB Endpoint 8 RX + 0x18 + + + USBRXEP9 + USB Endpoint 9 RX + 0x19 + + + USBRXEP10 + USB Endpoint 10 RX + 0x1A + + + USBRXEP11 + USB Endpoint 11 RX + 0x1B + + + SPI0TX + SPI0 TX + 0x21 + + + SPI1TX + SPI1 TX + 0x22 + + + UART0TX + UART0 TX + 0x24 + + + UART1TX + UART1 TX + 0x25 + + + I2C0TX + I2C0 TX + 0x27 + + + I2C1TX + I2C1 TX + 0x28 + + + I2C2TX + I2C2 TX + 0x2A + + + UART2TX + UART2 TX + 0x2E + + + SPI2TX + SPI3 TX + 0x2F + + + USBTXEP1 + USB Endpoint 1 TX + 0x31 + + + USBTXEP2 + USB Endpoint 2 TX + 0x32 + + + USBTXEP3 + USB Endpoint 3 TX + 0x33 + + + USBTXEP4 + USB Endpoint 4 TX + 0x34 + + + USBTXEP5 + USB Endpoint 5 TX + 0x35 + + + USBTXEP6 + USB Endpoint 6 TX + 0x36 + + + USBTXEP7 + USB Endpoint 7 TX + 0x37 + + + USBTXEP8 + USB Endpoint 8 TX + 0x38 + + + USBTXEP9 + USB Endpoint 9 TX + 0x39 + + + USBTXEP10 + USB Endpoint 10 TX + 0x3A + + + USBTXEP11 + USB Endpoint 11 TX + 0x3B + + + + + REQWAIT + Request Wait Enable. When enabled, delay timer start until DMA request transitions from active to inactive. + 10 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + TOSEL + Timeout Period Select. + 11 + 3 + + + to4 + Timeout of 3 to 4 prescale clocks. + 0 + + + to8 + Timeout of 7 to 8 prescale clocks. + 1 + + + to16 + Timeout of 15 to 16 prescale clocks. + 2 + + + to32 + Timeout of 31 to 32 prescale clocks. + 3 + + + to64 + Timeout of 63 to 64 prescale clocks. + 4 + + + to128 + Timeout of 127 to 128 prescale clocks. + 5 + + + to256 + Timeout of 255 to 256 prescale clocks. + 6 + + + to512 + Timeout of 511 to 512 prescale clocks. + 7 + + + + + PSSEL + Pre-Scale Select. Selects the Pre-Scale divider for timer clock input. + 14 + 2 + + + dis + Disable timer. + 0 + + + div256 + hclk / 256. + 1 + + + div64k + hclk / 64k. + 2 + + + div16M + hclk / 16M. + 3 + + + + + SRCWD + Source Width. In most cases, this will be the data width of each AHB transactions. However, the width will be reduced in the cases where DMA_CNT indicates a smaller value. + 16 + 2 + + + byte + Byte. + 0 + + + halfWord + Halfword. + 1 + + + word + Word. + 2 + + + + + SRCINC + Source Increment Enable. This bit enables DMA_SRC increment upon every AHB transaction. This bit is forced to 0 for DMA receive from peripherals. + 18 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + DSTWD + Destination Width. Indicates the width of the each AHB transactions to the destination peripheral or memory. (The actual width may be less than this if there are insufficient bytes in the DMA FIFO for the full width). + 20 + 2 + + + byte + Byte. + 0 + + + halfWord + Halfword. + 1 + + + word + Word. + 2 + + + + + DSTINC + Destination Increment Enable. This bit enables DMA_DST increment upon every AHB transaction. This bit is forced to 0 for DMA transmit to peripherals. + 22 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + BRST + Burst Size. The number of bytes to be transferred into and out of the DMA FIFO in a single burst. Burst size equals 1 + value stored in this field. + 24 + 5 + + + CHDIEN + Channel Disable Interrupt Enable. When enabled, the IPEND will be set to 1 whenever CH_ST changes from 1 to 0. + 30 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + CTZIEN + Count-to-zero Interrupts Enable. When enabled, the IPEND will be set to 1 whenever a count-to-zero event occurs. + 31 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + + + ST + DMA Channel Status Register. + 0x004 + + + CH_ST + Channel Status. This bit is used to indicate to the programmer when it is safe to change the configuration, address, and count registers for the channel. Whenever this bit is cleared by hardware, the DMA_CFG.CHEN bit is also cleared (if not cleared already). + 0 + 1 + read-only + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + IPEND + Channel Interrupt. + 1 + 1 + read-only + + + inactive + No interrupt is pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + CTZ_ST + Count-to-Zero (CTZ) Event Interrupt Flag + 2 + 1 + oneToClear + + + RLD_ST + Reload Event Interrupt Flag. + 3 + 1 + oneToClear + + + BUS_ERR + Bus Error. Indicates that an AHB abort was received and the channel has been disabled. + 4 + 1 + oneToClear + + + TO_ST + Time-Out Event Interrupt Flag. + 6 + 1 + oneToClear + + + + + SRC + Source Device Address. If SRCINC=1, the counter bits are incremented by 1,2, or 4, depending on the data width of each AHB cycle. For peripheral transfers, some or all of the actual address bits are fixed. If SRCINC=0, this register remains constant. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with the contents of DMA_SRC_RLD. + 0x008 + + + SRC + 0 + 32 + + + + + DST + Destination Device Address. For peripheral transfers, some or all of the actual address bits are fixed. If DSTINC=1, this register is incremented on every AHB write out of the DMA FIFO. They are incremented by 1, 2, or 4, depending on the data width of each AHB cycle. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with DMA_DST_RLD. + 0x00C + + + DST + 0 + 32 + + + + + CNT + DMA Counter. The user loads this register with the number of bytes to transfer. This counter decreases on every AHB cycle into the DMA FIFO. The decrement will be 1, 2, or 4 depending on the data width of each AHB cycle. When the counter reaches 0, a count-to-zero condition is triggered. + 0x010 + + + CNT + DMA Counter. + 0 + 24 + + + + + SRC_RLD + Source Address Reload Value. The value of this register is loaded into DMA0_SRC upon a count-to-zero condition. + 0x014 + + + SRC_RLD + Source Address Reload Value. + 0 + 31 + + + + + DST_RLD + Destination Address Reload Value. The value of this register is loaded into DMA0_DST upon a count-to-zero condition. + 0x018 + + + DST_RLD + Destination Address Reload Value. + 0 + 31 + + + + + CNT_RLD + DMA Channel Count Reload Register. + 0x01C + + + CNT_RLD + Count Reload Value. The value of this register is loaded into DMA0_CNT upon a count-to-zero condition. + 0 + 24 + + + RLDEN + Reload Enable. This bit should be set after the address reload registers have been programmed. This bit is automatically cleared to 0 when reload occurs. + 31 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + + - - - FCR - Function Control Register. - 0x40000800 + + + EMAC + 10/100 Ethernet MAC. + 0x4004F000 - 0x00 - 0x400 + 0 + 0x1000 registers + + EMAC + EMAC IRQ + 64 + - FCTRL0 - Register 0. + CN + Network Control Register. 0x00 - read-write + 0x00 - USB_EXTCLK_SEL - USB External Core Clock Select. - 16 - 1 - - - sys - Generated clock from system clock. - 0 - - - dig - Digital clock from a GPIO. - 1 - - - - - I2C0_SDA_FILTER_EN - I2C0 SDA Glitch Filter Enable. - 20 - 1 - - - dis - Filter disabled. - 0 - - - en - Filter enabled. - 1 - - - - - I2C0_SCL_FILTER_EN - I2C0 SCL Glitch Filter Enable. - 21 - 1 - - - dis - Filter disabled. - 0 - - - en - Filter enabled. - 1 - - - - - I2C1_SDA_FILTER_EN - I2C1 SDA Glitch Filter Enable. - 22 - 1 - - - dis - Filter disabled. - 0 - - - en - Filter enabled. - 1 - - - - - I2C1_SCL_FILTER_EN - I2C1 SCL Glitch Filter Enable. - 23 - 1 - - - dis - Filter disabled. - 0 - - - en - Filter enabled. - 1 - - - - - I2C2AF2_SDA_FILTER_EN - I2C2 AF2 SDA Glitch Filter Enable. - 24 + LB + Loopback. + 0 1 - - - dis - Filter disabled. - 0 - - - en - Filter enabled. - 1 - - + read-write - I2C2AF2_SCL_FILTER_EN - I2C2 AF2 SCL Glitch Filter Enable. - 25 + LBL + Loopback local. + 1 1 - - - dis - Filter disabled. - 0 - - - en - Filter enabled. - 1 - - + read-write - I2C2AF3_SDA_FILTER_EN - I2C2 AF3 SDA Glitch Filter Enable. - 26 + RXEN + Receive Enable. + 2 1 - - - dis - Filter disabled. - 0 - - - en - Filter enabled. - 1 - - + read-write - I2C2AF3_SCL_FILTER_EN - I2C2 AF3 SCL Glitch Filter Enable. - 27 + TXEN + Transmit Enable. + 3 1 - - - dis - Filter disabled. - 0 - - - en - Filter enabled. - 1 - - + read-write - I2C2AF4_SDA_FILTER_EN - I2C2 AF4 SDA Glitch Filter Enable - 28 + MPEN + Management Port Enable. + 4 1 - - - dis - Filter disabled. - 0 - - - en - Filter enabled. - 1 - - + read-write - I2C2AF4_SCL_FILTER_EN - I2C2 AF4 SCL Glitch Filter Enable - 29 + CLST + Clear Statistics. + 5 1 - - - dis - Filter disabled. - 0 - - - en - Filter enabled. - 1 - - + write-only - - - - AUTOCAL0 - Register 1. - 0x04 - read-write - - SEL - Auto-calibration Enable. - 0 + INCST + Increment Statistics. + 6 1 - - - dis - Disabled. - 0 - - - en - Enabled. - 1 - - + write-only - EN - Autocalibration Run. - 1 + WREN + Write enable for statistics registers. + 7 1 - - - not - Not Running. - 0 - - - run - Running. - 1 - - + read-write - LOAD - Load Trim. - 2 + BP + Back pressure. + 8 1 + read-write - INVERT - Invert Gain. - 3 + TXSTART + Transmission start. + 9 1 - - - not - Not Running. - 0 - - - run - Running. - 1 - - + write-only - ATOMIC - Atomic mode. - 4 + TXHALT + Transmit halt. + 10 1 - - - not - Not Running. - 0 - - - run - Running. - 1 - - + write-only - GAIN - MU value. - 8 - 12 + TXPF + Transmit pause frame. + 11 + 1 + write-only - TRIM - 150MHz HFIO Auto Calibration Trim - 23 - 9 + TXZQPF + Transmit zero quantum pause frame. + 12 + 1 + write-only - AUTOCAL1 - Register 2. - 0x08 - read-write + CFG + Network Configuration Register. + 0x04 - NFC_FWD_EN - Enabled FWD mode for NFC block + SPEED + Speed Select. 0 1 + read-write - NFC_CLK_EN - Enabled the NFC blocks clock divider in Analog + FULLDPLX + Full Duplex. If set to 1 the transmit block ignores the state of collision and carrier sense and allows Rx while transmitting. 1 1 + read-write - NFC_FWD_TX_DATA_OVR - FWD input for NFC block + BITRATE + Bit Rate. Writing 1 to this bit configures the interface for serial operation. 2 1 + read-write - XO_EN_DGL - TBD + JUMBOFR + Jumbo Frames. Writing 1 to this bit enables jumbo frames of up to 10,240 bytes to be accepted. 3 1 + read-write - RX_BIAS_PD - Power down enable for NFC receiver analog block + COPYAF + Copy All Frames. If 1, all valid frames will be received. 4 1 + read-write - RX_BIAS_EN - Enable the NFC receiver analog blocks + NOBC + No Broadcast. If 1, frames addressed to the broadcast address of all ones will not be received. 5 1 + write-only - RX_TM_VBG_VABUS - TBD + MHEN + Multicast Hash Enable. If 1, multicast frames will be received when the 6 bit hash function of the destination address points to a bit that is set in the hash register. 6 1 + write-only - RX_TM_BIAS - TBD + UHEN + Unicast Hash Enable. If 1, unicast frames will be received when the 6 bit hash function of the destination address points to a bit that is set in the hash register. 7 1 + read-write - NFC_FWD_DOUT - FWD output from FNC block + RXFR + Receive 1536 Byte Frames. Writing 1 to this bit means the MAC receives packets up to 1536 bytes in length. Normally the MAC rejects any packet above 1518 bytes 8 1 + read-write - - - - AUTOCAL2 - Register 3. - 0x0C - read-write - - - RUNTIME - Automatic Calibration Run Time. - 0 - 8 - - - - - - - - FLC - Flash Memory Control. - FLSH_ - 0x40029000 - - 0x00 - 0x400 - registers - - - Flash_Controller - Flash Controller interrupt. - 23 - - - - ADDR - Flash Write Address. - 0x00 - - - ADDR - Address for next operation. - 0 - 32 - - - - - CLKDIV - Flash Clock Divide. The clock (PLL0) is divided by this value to generate a 1 MHz clock for Flash controller. - 0x04 - 0x00000064 - - - CLKDIV - Flash Clock Divide. The clock is divided by this value to generate a 1MHz clock for flash controller. - 0 - 8 - - - - - CN - Flash Control Register. - 0x08 - - WR - Write. This bit is automatically cleared after the operation. - 0 - 1 + MDCCLK + MDC Frequency. Set according to PCLK speed. This field determines by what number PCLK is divided to generate MDC. + 10 + 2 + write-only - complete - No operation/complete. + div8 + PCLK up to 20MHz 0 - start - Start operation. + div16 + PCLK up to 40MHz 1 + + div32 + PCLK up to 80MHz + 2 + + + div64 + PCLK up to 160MHz + 3 + - - ME - Mass Erase. This bit is automatically cleared after the operation. - 1 + + RTTST + Retry Test. Must be set to zero for normal operation. If set to 1, the back-off between collisions is always one slot time. + 12 + 1 + write-only + + + PAUSEEN + Pause Enable. If 1, Ethernet packet transmission pauses when a valid pause packet is received. + 13 + 1 + write-only + + + RXBUFFOFS + Receive buffer offset. These bits indicate the number of bytes by which the received data is offset from the start of the first receive buffer. + 14 + 2 + write-only + + + RXLFCEN + Receive length field checking enable. If 1, packets with measured lengths shorter than their length fields are discarded. Packets containing a type ID in bytes 13 and 14 (length/type field >=0600) are not counted as length errors. + 16 + 1 + write-only + + + DCRXFCS + Discard receive FCS. If 1, the FCS field of received frames will not be copied to memory. + 17 + 1 + write-only + + + HDPLXRXEN + Enable packets to be received in half-duplex mode while transmitting. + 18 1 + write-only - - PGE - Page Erase. This bit is automatically cleared after the operation. - 2 + + IGNRXFCS + Ignore RX FCS. If 1, packets with FCS/CRC errors are not rejected and no FCS error statistics are counted. For normal operation, this bit must be set to 0. + 19 1 + write-only + + + + STATUS + Network Status Register. + 0x08 + read-only + - ERASE_CODE - Erase Code. The ERASE_CODE must be set up property before erase operation can be initiated. These bits are automatically cleared after the operation is complete. - 8 - 8 - - - nop - No operation. - 0 - - - erasePage - Enable Page Erase. - 0x55 - - - eraseAll - Enable Mass Erase. The debug port must be enabled. - 0xAA - - + LINK + LINK pin status. Returns status of EMAC_LINK pin. + 0 + 1 + read-only - PEND - Flash Pending. When Flash operation is in progress (busy), Flash reads and writes will fail. When PEND is set, write to all Flash registers, with exception of the Flash interrupt register, are ignored. - 24 + MDIO + MDIO pin status. Returns status of the EMAC_MDIO pin. Use the PHY maintenance register for reading managed frames rather than this bit. + 1 1 read-only - - - idle - Idle. - 0 - - - busy - Busy. - 1 - - - UNLOCK - Flash Unlock. The correct unlock code must be written to these four bits before any Flash write or erase operation is allowed. - 28 - 4 - - - unlocked - Flash Unlocked. - 2 - - - locked - Flash Locked. - 3 - - + IDLE + PHY management logic status. + 2 + 1 + read-only - INTR - Flash Interrupt Register. - 0x24 + TX_ST + Transmit Status Register. + 0x14 - DONE - Flash Done Interrupt. This bit is set to 1 upon Flash write or erase completion. + UBR + Used Bit Read. Set when a transmit buffer descriptor is read with its used bit set. Write 1 to clear this bit. 0 1 - - - inactive - No interrupt is pending. - 0 - - - pending - An interrupt is pending. - 1 - - + read-write - AF - Flash Access Fail. This bit is set when an attempt is made to write the flash while the flash is busy or the flash is locked. This bit can only be set to 1 by hardware. + COLS + Collision Occurred. Set when a collision occurs. Write 1 to clear this bit. 1 1 - - - noError - No Failure. - 0 - - - error - Failure occurs. - 1 - - + read-write - DONEIE - Flash Done Interrupt Enable. - 8 + RTYLIM + Retry Limit Exceeded. Set when the retry limit has been exceeded. Write 1 to clear this bit. + 2 1 - - - disable - Disable. - 0 - - - enable - Enable. - 1 - - + read-write - - AFIE - 9 + + TXGO + Transmit Go. If 1, transmit is active. + 3 + 1 + read-write + + + BEMF + Buffers Exhausted Mid Frame. If the buffers run out during transmission of a frame then transmission stops, FCS shall be bad and EMAC_TXER asserted. Write 1 to clear this bit. + 4 + 1 + read-write + + + TXCMPL + Transmit Complete. Set when a frame has been transmitted. Write 1 to clear this bit. + 5 + 1 + read-write + + + TXUR + Transmit Underrun. Set when the MAC transmit FIFO was read while was empty. If this happens the transmitter forces bad. Write 1 to clear this bit. + 6 1 + read-write - ECC_DATA - ECC Data Register. - 0x28 + RXBUF_PTR + Receive Buffer Queue Pointer Register. + 0x18 - ECC_EVEN - Error Correction Code Odd Data. - 0 - 9 + RXBUF + Receive buffer queue pointer. Written with the address of the start of the receive queue, reads as a pointer to the current buffer being used. + 2 + 30 + read-write + + + + TXBUF_PTR + Transmit Buffer Queue Pointer Register. + 0x1C + - ECC_ODD - Error Correction Code Even Data. - 16 - 9 + TXBUF + Transmit buffer queue pointer. Written with the address of the start of the transmit queue, reads as a pointer to the first buffer of the frame being transmitted or about to be transmitted. + 2 + 30 + read-write - 4 - 4 - DATA[%s] - Flash Write Data. - 0x30 + RX_ST + Receive Status Register. + 0x20 - DATA - Data next operation. + BNA + Buffer Not Available. An attempt was made to get a new buffer and the pointer indicated that it was owned by the processor. The DMA will reread the pointer each time a new frame starts until a valid pointer is found. This bit will be set at each attempt that fails even if it has not had a successful pointer read since it has been cleared. Write 1 to clear this bit. 0 - 32 + 1 + read-write - - - - - - - FLC1 - Flash Memory Control. 1 - 0x40029400 - - FLC1 - FLC1 IRQ - 87 - - - - - GCR - Global Control Registers. - 0x40000000 - - 0 - 0x400 - registers - - + + FR + Frame Received. One or more frames have been received and placed in memory. Write 1 to clear this bit. + 1 + 1 + read-write + + + RXOR + Receive Overrun. The DMA block was unable to store the receive frame to memory. Either because the AHB bus was not granted in time or because a not OK hresp was returned. The buffer will be recovered if this happens. Write 1 to clear this bit. + 2 + 1 + read-write + + + - SYSCTRL - System Control. - 0x00 - 0xFFFFFFFE + INT_ST + Interrupt Status Register. + 0x24 - BSTAPEN - Boundary Scan TAP enable. When enabled, the JTAG port is connected to the Boundary Scan TAP. Otherwise, the port is connected to the ARM ICE function. This bit is reset by the POR. Reset value and access depend on the part number. + MPS + Management Packet Sent Interrupt Status. The PHY maintenance register has completed its operation. Cleared when read. 0 1 - - - dis - Boundary Scan TAP port disabled. - 0 - - - en - Boundary Scan TAP port enabled. - 1 - - + read-write - SBUSARB - System bus abritration scheme. These bits are used to select between Fixed-burst abritration and Round-Robin scheme. The Round-Robin scheme is selected by default. These bits are reset by the system reset. + RXCMPL + Receive Complete Interrupt Status. Set when a frame has been stored in memory. Cleared when read. 1 - 2 - - - fix - Fixed Burst abritration. - 0 - - - round - Round-robin scheme. - 1 - - + 1 + read-write - FLASH0_PAGE_FLIP - Flips the Flash bottom and top halves. (Depending on the total flash size, each half is either 256K or 512K). Initiating a flash page flip will cause a flush of both the data buffer on the DCODE bus and the internal instruction buffer. + RXUBR + RX Used Bit Read Interrupt Status. Set when a receive buffer descriptor is read with its used bit set. Cleared when read. + 2 + 1 + read-write + + + TXUBR + TX Used Bit Read Interrupt Status. Set when a transmit buffer descriptor is read with its used bit set. Cleared when read + 3 + 1 + read-write + + + TXUR + Ethernet Transmit Underrun Interrupt Status. Set when the MAC transmit FIFO was read while was empty. If this happens the transmitter forces bad CRC and forces EMAC_TXER high. Cleared when read. 4 1 - - - normal - Physical layout matches logical layout. - 0 - - - swapped - Bottom half mapped to logical top half and vice versa. - 1 - - + read-write - FPU_DIS - Cortex M4 Floating Point Disable This bit is used to disable the floating-point unit of the Cortex-M4. + RLE + Retry Limit Exceeded Interrupt Status. Transmit error. Cleared when read. 5 1 + read-write - ICC0_FLUSH - Code Cache Flush. This bit is used to flush the code caches and the instruction buffer of the Cortex-M4. + TXERR + Transmit Buffers Exhausted In Mid-frame Interrupt Status. Transmit error. Cleared when read. 6 1 - - - normal - Normal Code Cache Operation - 0 - - - flush - Code Caches and CPU instruction buffer are flushed - 1 - - + read-write - SRCC_FLUSH - Data Cache Flush. The system cache (s) will be flushed when this bit is set. + TXCMPL + Transmit Complete Interrupt Status. Set when a frame has been transmitted. Cleared when read. 7 1 - - - normal - Normal System Cache Operation - 0 - - - flush - System Cache is flushed - 1 - - + read-write - SRCC_DIS - Data Cache Disable. The system cache (s) will be completely disabled when this bit is set. + LC + Link Change Interrupt Status. Set when the external link signal changes. Cleared when read. 9 1 - - - en - Is enabled. - 0 - - - dis - Is Disabled. - 1 - - + read-write - CCHK - Compute ROM Checksum. This bit is self-cleared when calculation is completed. Once set, software clearing this bit is ignored and the bit will remain set until the operation is completed. - 13 + RXOR + Receive Overrun Interrupt Status. Set when the receive overrun status bit gets set. Cleared when read. + 10 1 - - - complete - No operation/complete. - 0 - - - start - Start operation. - 1 - - + read-write - CHKRES - ROM Checksum Result. This bit is only valid when CHKRD=1. - 15 + HRESPNO + hresp not OK Interrupt Status. Set when the DMA block sees hresp not OK. Cleared when read. + 11 1 - - - pass - ROM Checksum Correct. - 0 - - - fail - ROM Checksum Fail. - 1 - - + read-write + + + PPR + Pause Packet Received Interrupt Status. Indicates a valid pause packet has been received. Cleared when read. + 12 + 1 + read-write + + + PTZ + Pause Time Zero Interrupt Status. Set when the MAC Pause Time register (MAC_PT) decrements to zero. Cleared when read. + 13 + 1 + read-write - RST0 - Reset. - 0x04 + INT_EN + Interrupt Enable Register. + 0x28 + write-only - DMA - DMA Reset. + MPS + Management Packet Sent Interrupt Enable 0 1 + write-only - - WDT0 - Watchdog Timer Reset. + + RXCMPL + Receive Complete Interrupt Enable 1 1 + write-only - - GPIO0 - GPIO0 Reset. Setting this bit to 1 resets GPIO0 pins to their default states. + + RXUBR + RX Used Bit Read Interrupt Enable 2 1 + write-only - - GPIO1 - GPIO1 Reset. Setting this bit to 1 resets GPIO1 pins to their default states. + + TXUBR + TX Used Bit Read Interrupt Enable 3 1 + write-only - - GPIO2 - GPIO2 Reset. Setting this bit to 1 resets GPIO2 pins to their default states. + + TXUR + Ethernet Transmit Underrun Interrupt Enable 4 1 + write-only - - TMR0 - Timer0 Reset. Setting this bit to 1 resets Timer 0 blocks. + + RLE + Retry Limit Exceeded Interrupt Enable 5 1 + write-only - - TMR1 - Timer1 Reset. Setting this bit to 1 resets Timer 1 blocks. + + TXERR + Transmit Buffers Exhausted In Mid-frame Interrupt Enable 6 1 + write-only - - TMR2 - Timer2 Reset. Setting this bit to 1 resets Timer 2 blocks. + + TXCMPL + Transmit Complete Interrupt Enable 7 1 - - - TMR3 - Timer3 Reset. Setting this bit to 1 resets Timer 3 blocks. - 8 - 1 - - - TMR4 - Timer4 Reset. Setting this bit to 1 resets Timer 4 blocks. + write-only + + + LC + Link Change Interrupt Enable 9 1 + write-only - - TMR5 - Timer5 Reset. Setting this bit to 1 resets Timer 5 blocks. + + RXOR + Receive Overrun Interrupt Enable 10 1 + write-only - - UART0 - UART0 Reset. Setting this bit to 1 resets all UART 0 blocks. + + HRESPNO + hresp not OK Interrupt Enable 11 1 + write-only - - UART1 - UART1 Reset. Setting this bit to 1 resets all UART 1 blocks. + + PPR + Pause Packet Received Interrupt Enable 12 1 + write-only - - SPI0 - SPI0 Reset. Setting this bit to 1 resets all SPI 0 blocks. + + PTZ + Pause Time Zero Interrupt Enable 13 1 + write-only - - SPI1 - SPI1 Reset. Setting this bit to 1 resets all SPI 1 blocks. - 14 - 1 - - - SPI2 - SPI2 Reset. Setting this bit to 1 resets all SPI 2 blocks. - 15 - 1 - - - I2C0 - I2C0 Reset. - 16 - 1 - - - RTC - Real Time Clock Reset. - 17 - 1 - - - CRYPTO - Cryptographic Reset. Setting this bit to 1 resets the AES block, the SHA block and the DES block. - 18 + + + + INT_DIS + Interrupt Disable Register. + 0x2C + write-only + + + MPS + Management Packet Sent Interrupt Disable + 0 1 + write-only - - TMR6 - Timer6 Reset. Setting this bit to 1 resets Timer 6 blocks. - 20 + + RXCMPL + Receive Complete Interrupt Disable + 1 1 + write-only - - TMR7 - Timer7 Reset. Setting this bit to 1 resets Timer 7 blocks. - 21 + + RXUBR + RX Used Bit Read Interrupt Disable + 2 1 + write-only - - CLCD - CLCD Reset. Setting this bit to 1 resets the CLCD block. - 22 + + TXUBR + TX Used Bit Read Interrupt Disable + 3 1 + write-only - - USB - USB Reset. Setting this bit resets both USB blocks. - 23 + + TXUR + Ethernet Transmit Underrun Interrupt Disable + 4 1 + write-only - - ADC - Analog to Digital Reset. - 26 + + RLE + Retry Limit Exceeded Interrupt Disable + 5 1 + write-only - - UART2 - UART2 Reset. Setting this bit to 1 resets all UART 2 blocks. - 28 + + TXERR + Transmit Buffers Exhausted In Mid-frame Interrupt Disable + 6 1 + write-only - - SOFT - Soft Reset. Setting this bit to 1 resets everything except the CPU and the watchdog timer. - 29 + + TXCMPL + Transmit Complete Interrupt Disable + 7 1 + write-only - - PERIPH - Peripheral Reset. Setting this bit to 1 resets all peripherals. The CPU core, the watchdog timer, and all GPIO pins are unaffected by this reset. - 30 + + LC + Link Change Interrupt Disable + 9 1 + write-only - - SYS - System Reset. Setting this bit to 1 resets the CPU core and all peripherals, including the watchdog timer. - 31 + + RXOR + Receive Overrun Interrupt Disable + 10 1 + write-only - - - - CLKCTRL - Clock Control. - 0x08 - 0x00000008 - - SYSCLK_DIV - Prescaler Select. This 3 bit field sets the system operating frequency by controlling the prescaler that divides the output of the PLL0. - 6 - 3 - - - div1 - Divide by 1. - 0 - - - div2 - Divide by 2. - 1 - - - div4 - Divide by 4. - 2 - - - div8 - Divide by 8. - 3 - - - div16 - Divide by 16. - 4 - - - div32 - Divide by 32. - 5 - - - div64 - Divide by 64. - 6 - - - div128 - Divide by 128. - 7 - - + HRESPNO + hresp not OK Interrupt Disable + 11 + 1 + write-only - SYSCLK_SEL - Clock Source Select. This 3 bit field selects the source for the system clock. - 9 - 3 - - - ISO - Internal Secondary Oscilatior Clock - 0 - - - ERFO - 27MHz Crystal is used for the system clock. - 2 - - - INRO - 8kHz Internal Nano Ring Oscillator is used for the system clock. - 3 - - - IPO - The internal Primary oscillator is used for the system clock. - 4 - - - IBRO - The internal Baud Rate oscillator is used for the system clock. - 5 - - - ERTCO - 32kHz is used for the system clock. - 6 - - + PPR + Pause Packet Received Interrupt Disable + 12 + 1 + write-only - SYSCLK_RDY - Clock Ready. This read only bit reflects whether the currently selected system clock source is running. + PTZ + Pause Time Zero Interrupt Disable 13 1 + write-only + + + + + INT_MASK + Interrupt Mask Register. + 0x30 + read-only + + + MPS + Management Packet Sent Interrupt Mask + 0 + 1 read-only - - - busy - Switchover to the new clock source (as selected by CLKSEL) has not yet occurred. - 0 - - - ready - System clock running from CLKSEL clock source. - 1 - - - CCD - Cryptographic clock divider - 15 + RXCMPL + Receive Complete Interrupt Mask + 1 1 read-only - - - non_div - The cryptographic accelerator clock is running in non-divided mode. - 0 - - - div - The cryptographic accelerator clock is running in divided mode. - 1 - - - ERFO_EN - 27MHz Crystal Oscillator Enable. - 16 + RXUBR + RX Used Bit Read Interrupt Mask + 2 1 - - - dis - Is Disabled. - 0 - - - en - Is Enabled. - 1 - - + read-only - ERTCO_EN - 32kHz Crystal Oscillator Enable. - 17 + TXUBR + TX Used Bit Read Interrupt Mask + 3 1 + read-only - - ISO_EN - 60MHz High Frequency Internal Reference Clock Enable. - 18 + + TXUR + Ethernet Transmit Underrun Interrupt Mask + 4 1 + read-only - - IPO_EN - 96MHz High Frequency Internal Reference Clock Enable. - 19 + + RLE + Retry Limit Exceeded Interrupt Mask + 5 1 + read-only - - IBRO_EN - 8MHz High Frequency Internal Reference Clock Enable. - 20 + + TXERR + Transmit Buffers Exhausted In Mid-frame Interrupt Mask + 6 1 + read-only - IBRO_VS - 7.3728MHz Internal Oscillator Voltage Source Select - 21 + TXCMPL + Transmit Complete Interrupt Mask + 7 1 + read-only - ERFO_RDY - 27MHz Crystal Oscillator Ready - 24 + LC + Link Change Interrupt Mask + 9 1 read-only - - - not - Is not Ready. - 0 - - - ready - Is Ready. - 1 - - - ERTCO_RDY - 32kHz Crystal Oscillator Ready - 25 + RXOR + Receive Overrun Interrupt Mask + 10 + 1 + read-only + + + HRESPNO + hresp not OK Interrupt Mask + 11 + 1 + read-only + + + PPR + Pause Packet Received Interrupt Mask + 12 + 1 + read-only + + + PTZ + Pause Time Zero Interrupt Mask + 13 1 read-only + + + + + PHY_MT + PHY Maintenance Register. + 0x34 + + + DATA + PHY Data. For a write operation this field is the data to be written to the PHY. + 0 + 16 + read-write + + + REGADDR + Register Address. Specifies the register in the PHY to access. + 18 + 5 + read-write + + + PHYADDR + PHY Address. Specifies the PHY to access. + 23 + 5 + read-write + + + OP + Operation + 28 + 2 + read-write - not - Is not Ready. - 0 + write + Write + 1 - ready - Is Ready. - 1 + read + Read + 2 - - ISO_RDY - 60MHz ISO Ready. - 26 - 1 + + SOP + TBD + 30 + 2 + read-write + + + + + PT + Pause Time Register. + 0x38 + read-only + + + TIME + Pause Time. Stores the current value of the pause time register, which is decremented every 512 bit times. + 0 + 16 + read-only + + + + + PFR + Pause Frame Received OK. + 0x3C + + + PFR + Pause Frames Received OK. A 16-bit register counting the number of good pause frames received. + 0 + 16 + read-write + + + + + FTOK + Frames Transmitted OK. + 0x40 + + + FTOK + Frames Transmitted OK. A 32-bit register counting the number of frames successfully transmitted, i.e. no underrun and not too many retries. + 0 + 32 + read-write + + + + + SCF + Single Collision Frames. + 0x44 + + + SCF + Single Collision Frames. A 16-bit register counting the number of frames experiencing a single collision before being successfully transmitted, i.e. no underrun. + 0 + 16 + read-write + + + + + MCF + Multiple Collision Frames. + 0x48 + + + MCF + Multiple Collision Frames. A 16-bit register counting the number of frames experiencing between two and fifteen collisions prior to being successfully transmitted, i.e. no underrun and not too many retries. + 0 + 16 + read-write - - IPO_RDY - Internal Primary Oscillator Ready. - 27 - 1 + + + + FROK + Fames Received OK. + 0x4C + + + FROK + Frames Received OK. A 24-bit register counting the number of good packets received + 0 + 24 + read-write - - IBRO_RDY - Internal Baud Rate Oscillator Ready. - 28 - 1 + + + + FCS_ERR + Frame Check Sequence Errors. + 0x50 + + + FCSERR + Frame Check Sequence Errors. + 0 + 8 + read-write - - INRO_RDY - Internal Nano Ring Oscillator Low Frequency Reference Clock Ready. - 29 - 1 + + + + ALGN_ERR + Alignment Errors. + 0x54 + + + ALGNERR + Alignment Errors. + 0 + 8 + read-write - PM - Power Management. - 0x0C + DFTXF + Deferred Transmission Frames. + 0x58 - MODE - Operating Mode. This two bit field selects the current operating mode for the device. Note that code execution only occurs during ACTIVE mode. + DFTXF + Deferred Transmission Frames. A 16-bit register counting the number of packets experiencing deferral due to carrier sense being active on their first attempt at transmission 0 - 3 - - - active - Active Mode. - 0 - - - deepsleep - DeepSleep Mode. - 2 - - - shutdown - Shutdown Mode. - 3 - - - backup - Backup Mode. - 4 - - + 16 + read-write + + + + LC + Late Collisions. + 0x5C + - GPIO_WE - GPIO Wake Up Enable. This bit enables all GPIO pins as potential wakeup sources. Any GPIO configured for wakeup is capable of causing an exit from IDLE or STANDBY modes when this bit is set. - 4 - 1 + LC + Late Collisions. An 8-bit register counting the number of packets that experience a collision after the slot time (512 bits) has expired. + 0 + 8 + read-write - - RTC_WE - RTC Alarm Wake Up Enable. This bit enables RTC alarm as wakeup source. If enabled, the desired RTC alarm must be configured via the RTC control registers. - 5 - 1 + + + + EC + Excessive Collisions. + 0x60 + + + EC + Excessive Collisions. An 8-bit register counting the number of packets that failed to be transmitted because they experienced 16 collisions. + 0 + 8 + read-write - - USB_WE - USB Wake Up Enable. This bit enables USB activity as wakeup source. - 6 - 1 + + + + TUR_ERR + Transmit Underrun Errors. + 0x64 + + + TURERR + Transmit Underrun Error. An 8-bit register counting the number of packets not transmitted due to a transmit FIFO underrun. + 0 + 8 + read-write - - HA0_WE - Hardware Accelerator 0 Wake Up Enable. This bit enables USB activity as wakeup source. - 7 - 1 + + + + CS_ERR + Carrier Sense Errors. + 0x68 + + + CSERR + An 8-bit register counting the number of packets transmitted where carrier sense was not seen during transmission or where carrier sense was deasserted after being asserted in a transmit packet without collision (no underrun). + 0 + 8 + read-write - - HA1_WE - Hardware Accelerator 1 Wake Up Enable. This bit enables USB activity as wakeup source. - 9 - 1 + + + + RR_ERR + Receive Resource Errors. + 0x6C + + + RRERR + Receive Resource Errors. A 16 bit register counting the number of frames that were address matched but could not be copied to memory because no receive buffer was available. + 0 + 16 + read-write + + + + ROR_ERR + Receive Overrun Errors. + 0x70 + - ERFO_PD - Radio Frequency oscilator Crystal Power Down. This bit selects the power state in DEEPSLEEP mode. - 12 - 1 - - - active - Mode is Active. - 0 - - - deepsleep - Powered down in DEEPSLEEP. - 1 - - + RORERR + Receive Overruns. An 8 bit register counting the number of frames that are address recognized but were not copied to memory due to a receive DMA overrun. + 0 + 8 + read-write + + + + RS_ERR + Receive Symbol Errors. + 0x74 + - ISO_PD - Internal Secondary Oscilator Power Down. This bit selects the power state in DEEPSLEEP mode. - 15 - 1 - - - active - Mode is Active. - 0 - - - deepsleep - Powered down in DEEPSLEEP. - 1 - - + RSERR + Receive Symbol Errors. An 8-bit register counting the number of packets that had EMAC_RXER asserted during reception. + 0 + 8 + read-write + + + + EL_ERR + Excessive Length Errors. + 0x78 + - IPO_PD - Internal Primary Oscilatory power down. This bit selects the power state in DEEPSLEEP mode. - 16 - 1 - - - active - Mode is Active. - 0 - - - deepsleep - Powered down in DEEPSLEEP. - 1 - - + ELERR + Excessive Length Errors. An 8-bit register counting the number of packets received exceeding 1518 bytes in length (1536 if RXFR is set in the MAC_CFG register; + 0 + 8 + read-write + + + + RJ + Receive Jabber. + 0x7C + - IBRO_PD - Internal Baud Rate Oscillator power down. This bit selects the power state in DEEPSLEEP mode. - 17 - 1 - - - active - Mode is Active. - 0 - - - deepsleep - Powered down in DEEPSLEEP. - 1 - - + RJERR + Receive Jabbers. An 8-bit register counting the number of packets received exceeding 1518 bytes in length (1536 if RXFR is set in the MAC_CFG register; + 0 + 8 + read-write + + + + USF + Undersize Frames. + 0x80 + - NFC_PD - When set, the NFC radio becomes inactive when the upon entering DEEPSLEEP mode - 18 - 1 - - - active - Mode is Active. - 0 - - - deepsleep - Powered down in DEEPSLEEP. - 1 - - + USF + Undersize Frames. An 8-bit register counting the number of packets received less than 64 bytes in length but do not have either a CRC error, an alignment error or a receive symbol error. + 0 + 8 + read-write + + + + SQE_ERR + SQE Test Errors. + 0x84 + - XTALBP - XTAL Bypass - 20 - 1 - - - normal - Normal - 0 - - - bypass - Bypass - 1 - - + SQEERR + SQE Test Errors. An 8-bit register counting the number of packets where collision was not asserted within 96 bit times (an interframe gap) of EMAC_TXEN being deasserted in half duplex mode. + 0 + 8 + read-write - PCLKDIV - Peripheral Clock Divider. - 0x18 - 0x00000001 + RLFM + Received Length Field Mismatch. + 0x88 - PCF - These bits determine the clock frequency for the UART, I2C and Key Pad peripherals. These peripherals have an adaptive clock generator that dynamically adjusts the peripheral frequency based on the main system bus frequency. These bits are dynamically updated when the PLL0 is selected as the system clock source and are set by hardware. These bits determine the clock frequency for the UART, I2C and Key Pad peripherals. These peripherals have an adaptive clock generator that dynamically adjusts the peripheral frequency based on the main system bus frequency. These bits are dynamically updated when the PLL0 is selected as the system clock source and are set by hardware. + RLFM + Receive length field mismatch 0 - 3 - - - 96MHz - 2 - - - 48MHz - 3 - - - 24MHz - 4 - - - 12MHz - 5 - - - 6MHz - 6 - - - 3MHz - 7 - - + 8 + read-write + + + + TPF + Transmitted Pause Frames. + 0x8C + - PCFWEN - PCF Write Enable. This bit allows the PCF Register bits to be updated by Software. - 3 - 1 - - - blocked - Writes to PCF are blocked. - 0 - - - allowed - Writes to PCF are allowed - 1 - - + TPF + Transmitted Pause Frames. A 16-bit register counting the number of pause packets transmitted. + 0 + 16 + read-write + + + + HASHL + Hash Register Bottom [31:0]. + 0x90 + - SDHCFRQ - SDHC Clock Frequency. This bits defines the clock frequency of SDHC. - 7 - 1 - - - 48MHz - 0 - - - 24MHz - 1 - - + HASH + Bits 31:0 of the hash address register. See Hash Addressing + 0 + 32 + read-write + + + + HASHH + Hash Register top [63:32]. + 0x94 + - ADCFRQ - ADC clock Frequency. These bits define the ADC clock frequency. FADC = FPCLK/ (ADCFRQ). - 10 - 4 + HASH + Bits 63:32 of the hash address register. See Hash Addressing + 0 + 32 + read-write - - AON_CLKDIV - Always-ON (AON) domain CLock Divider. These bits define the AON domain clock divider. - 14 - 2 - - - div_4 - PCLK divide by 4. - 0 - - - div_8 - PCLK divide by 8. - 1 - - - div_16 - PCLK divide by 16. - 2 - - - div_32 - PCLK divide by 32. - 3 - - + + + + SA1L + Specific Address 1 Bottom. + 0x98 + + + ADDR + MAC Specific Address 1 [31:0]. Least significant bits of the MAC specific address 1, i.e. bits 31:0. This field is used for transmission of pause packets + 0 + 32 + read-write - PCLKDIS0 - Peripheral Clock Disable. - 0x24 + SA1H + Specific Address 1 Top. + 0x9C - GPIO0 - GPIO0 Clock Disable. + ADDR + MAC Specific Address 1 [47:32]. Most significant bits of the MAC specific address 1, i.e. bits 47:32. 0 - 1 - - - en - enable it. - 0 - - - dis - disable it. - 1 - - - - - GPIO1 - GPIO1 Disable. - 1 - 1 - - - GPIO2 - GPIO2 Disable. - 2 - 1 - - - USB - USB Disable. - 3 - 1 - - - CLCD - CLCD Disable. - 4 - 1 + 16 + read-write - - DMA - DMA Disable. - 5 - 1 + + + + SA2L + Specific Address 2 Bottom. + 0xA0 + + + ADDR + MAC Specific Address 2 [31:0]. Least significant bits of the MAC specific address 2, i.e. bits 31:0. This field is used for transmission of pause packets + 0 + 32 + read-write - - SPI0 - SPI 0 Disable. - 6 - 1 + + + + SA2H + Specific Address 2 Top. + 0xA4 + + + ADDR + MAC Specific Address 2 [47:32]. Most significant bits of the MAC specific address 2, i.e. bits 47:32. + 0 + 16 + read-write - - SPI1 - SPI 1 Disable. - 7 - 1 + + + + SA3L + Specific Address 3 Bottom. + 0xA8 + + + ADDR + MAC Specific Address 3 [31:0]. Least significant bits of the MAC specific address 3, i.e. bits 31:0. This field is used for transmission of pause packets + 0 + 32 + read-write - - SPI2 - SPI 2 Disable. - 8 - 1 + + + + SA3H + Specific Address 3 Top. + 0xAC + + + ADDR + MAC Specific Address 3 [47:32]. Most significant bits of the MAC specific address 3, i.e. bits 47:32. + 0 + 16 + read-write - - UART0 - UART 0 Disable. - 9 - 1 + + + + SA4L + Specific Address 4 Bottom. + 0xB0 + + + ADDR + MAC Specific Address 4 [31:0]. Least significant bits of the MAC specific address 4, i.e. bits 31:0. This field is used for transmission of pause packets + 0 + 32 + read-write - - UART1 - UART 1 Disable. - 10 - 1 + + + + SA4H + Specific Address 4 Top. + 0xB4 + + + ADDR + MAC Specific Address 4 [47:32]. Most significant bits of the MAC specific address 4, i.e. bits 47:32. + 0 + 16 + read-write - - I2C0 - I2C 0 Disable. - 13 - 1 + + + + TID_CK + Type ID Checking. + 0xB8 + + + TID + Type ID Checking. For use in comparisons with received frames TypeID/Length field. + 0 + 16 + read-write - - CRYPTO - Crypto Disable. - 14 - 1 + + + + TPQ + Transmit Pause Quantum. + 0xBC + + + TPQ + Transmit Pause Quantum. Used in hardware generation of transmitted pause packets as value for pause quantum + 0 + 16 + read-write - - TMR0 - Timer 0 Disable. - 15 - 1 + + + + REV + Revision register. + 0xFC + read-only + + + REV + Revision Reference. Fixed two byte value specific to revision of design. + 0 + 16 + read-only - - TMR1 - Timer 1 Disable. + + PART + Part Reference. For Ethernet MAC design, this is fixed at 0x01. 16 - 1 - - - TMR2 - Timer 2 Disable. - 17 - 1 - - - TMR3 - Timer 3 Disable. - 18 - 1 - - - TMR4 - Timer 4 Disable. - 19 - 1 + 16 + read-only - - TMR5 - Timer 5 Disable. - 20 - 1 + + + + + + + SRCC + SPIX Cache Controller Registers. + 0x40033000 + + 0x00 + 0x1000 + registers + + + + INFO + Cache ID Register. + 0x0000 + read-only + + + RELNUM + Release Number. Identifies the RTL release version. + 0 + 6 - - KBD - Secure Keyboard Disable. - 22 - 1 + + PARTNUM + Part Number. This field reflects the value of C_ID_PART_NUMBER configuration parameter. + 6 + 4 - - ADC - ADC Disable. - 23 - 1 + + ID + Cache ID. This field reflects the value of the C_ID_CACHEID configuration parameter. + 10 + 6 - - TMR6 - Timer 6 Disable. - 24 - 1 + + + + SZ + Memory Configuration Register. + 0x0004 + read-only + 0x00080008 + + + CCH + Cache Size. Indicates total size in Kbytes of cache. + 0 + 16 - - TMR7 - Timer 7 Disable. - 25 - 1 + + MEM + Main Memory Size. Indicates the total size, in units of 128 Kbytes, of code memory accessible to the cache controller. + 16 + 16 - - HTMR0 - HTimer 0 Disable. - 26 + + + + CTRL + Cache Control and Status Register. + 0x0100 + + + EN + Cache Enable. Controls whether the cache is bypassed or is in use. Changing the state of this bit will cause the instruction cache to be flushed and its contents invalidated. + 0 1 + + + dis + Cache Bypassed. Instruction data is stored in the line fill buffer but is not written to main cache memory array. + 0 + + + en + Cache Enabled. + 1 + + - - HTMR1 - HTimer 1 Disable. - 27 + + WR_ALLOC_EN + Write Allocate Enable. This bit only writable while the cache is disabled. + 1 1 + + + dis + Write-no-allocate. + 0 + + + en + Write-allocate enabled. + 1 + + - - I2C1 - I2C 1 Disable. - 28 + + CWFST_DIS + Critical word first and streaming disable. This bit only writeable while the cache is disabled. + 2 1 + + + dis + Critical word first and streaming disabled. + 1 + + + en + Critical word first and streaming enabled. + 0 + + - - PT - PT Clock Disable. - 29 + + RDY + Cache Ready flag. Cleared by hardware when at any time the cache as a whole is invalidated (including a system reset). When this bit is 0, the cache is effectively in bypass mode (instruction fetches will come from main memory or from the line fill buffer). Set by hardware when the invalidate operation is complete and the cache is ready. + 16 1 + + + notReady + Not Ready. + 0 + + + ready + Ready. + 1 + + - - SPIXIP - SPI XiP Disable. - 30 - 1 + + + + INVALIDATE + Invalidate All Cache Contents. Any time this register location is written (regardless of the data value), the cache controller immediately begins invalidating the entire contents of the cache memory. The cache will be in bypass mode until the invalidate operation is complete. System software can examine the Cache Ready bit (CACHE_CTRL.CACHE_RDY) to determine when the invalidate operation is complete. Note that it is not necessary to disable the cache controller prior to beginning this operation. Reads from this register always return 0. + 0x0700 + + + INVALID + Invalidate all cache contents. + 0 + 32 - - SPIM - SPI XiP Master Controller Disable. - 31 - 1 + + + + + + + FLC + Flash Memory Control. + FLSH_ + 0x40029000 + + 0x00 + 0x400 + registers + + + Flash_Controller + Flash Controller interrupt. + 23 + + + + ADDR + Flash Write Address. + 0x00 + + + ADDR + Address for next operation. + 0 + 32 - MEMCTRL - Memory Clock Control Register. - 0x28 + CLKDIV + Flash Clock Divide. The clock (PLL0) is divided by this value to generate a 1 MHz clock for Flash controller. + 0x04 + 0x00000064 - FWS - Flash Wait State. These bits define the number of wait-state cycles per Flash data read access. Minimum wait state is 2. + CLKDIV + Flash Clock Divide. The clock is divided by this value to generate a 1MHz clock for flash controller. 0 - 3 + 8 + + + + CN + Flash Control Register. + 0x08 + - RAMWS_EN - SRAM Wait State Enable - 4 + WR + Write. This bit is automatically cleared after the operation. + 0 + 1 + + + complete + No operation/complete. + 0 + + + start + Start operation. + 1 + + + + + ME + Mass Erase. This bit is automatically cleared after the operation. + 1 + 1 + + + PGE + Page Erase. This bit is automatically cleared after the operation. + 2 1 - RAM0LS_EN - System RAM 0 Light Sleep Mode. - 16 - 1 + ERASE_CODE + Erase Code. The ERASE_CODE must be set up property before erase operation can be initiated. These bits are automatically cleared after the operation is complete. + 8 + 8 - active - RAM is active. + nop + No operation. 0 - light_sleep - RAM is in Light Sleep mode. - 1 + erasePage + Enable Page Erase. + 0x55 + + + eraseAll + Enable Mass Erase. The debug port must be enabled. + 0xAA - - RAM1LS_EN - System RAM 1 Light Sleep Mode. - 17 - 1 - - - RAM2LS_EN - System RAM 2 Light Sleep Mode. - 18 - 1 - - - RAM3LS_EN - System RAM 3 Light Sleep Mode. - 19 - 1 - - - RAM4LS_EN - System RAM 4 Light Sleep Mode. - 20 - 1 - - - RAM5LS_EN - System RAM 5 Light Sleep Mode. - 21 - 1 - - - ICC0LS_EN - ICache RAM Light Sleep Mode. + + PEND + Flash Pending. When Flash operation is in progress (busy), Flash reads and writes will fail. When PEND is set, write to all Flash registers, with exception of the Flash interrupt register, are ignored. 24 1 + read-only + + + idle + Idle. + 0 + + + busy + Busy. + 1 + + - - ICCXIPLS_EN - ICACHE-XIP RAM Light Sleep Mode. - 25 - 1 - - - SRCCLS_EN - SysCache RAM Light Sleep Mode. - 26 - 1 - - - CRYPTOLS_EN - CRYPTO RAM Light Sleep Mode. - 27 - 1 - - - USBLS_EN - USB FIFO Light Sleep Mode. + + UNLOCK + Flash Unlock. The correct unlock code must be written to these four bits before any Flash write or erase operation is allowed. 28 - 1 - - - ROMLS_EN - ROM Light Sleep Mode. - 29 - 1 + 4 + + + unlocked + Flash Unlocked. + 2 + + + locked + Flash Locked. + 3 + + - MEMZ - Memory Zeroize Control. - 0x2C + INTR + Flash Interrupt Register. + 0x24 - RAM0 - System RAM Block 0. + DONE + Flash Done Interrupt. This bit is set to 1 upon Flash write or erase completion. 0 1 - nop - No operation/complete. + inactive + No interrupt is pending. 0 - start - Start operation. + pending + An interrupt is pending. 1 - - RAM1 - System RAM Block 1. + + AF + Flash Access Fail. This bit is set when an attempt is made to write the flash while the flash is busy or the flash is locked. This bit can only be set to 1 by hardware. 1 1 + + + noError + No Failure. + 0 + + + error + Failure occurs. + 1 + + - - RAM2 - System RAM Block 2. - 2 - 1 - - - RAM3 - System RAM Block 3. - 3 - 1 - - - RAM4 - System RAM Block 4. - 4 - 1 - - - RAM5 - System RAM Block 5. - 5 - 1 - - - RAM6 - System RAM Block 6. - 6 - 1 - - - ICC0 - Instruction Cache. + + DONEIE + Flash Done Interrupt Enable. 8 1 + + + disable + Disable. + 0 + + + enable + Enable. + 1 + + - - ICCXIP - Instruction Cache XIP Data and Tag Ram zeroizatoin. + + AFIE 9 1 - - SCACHEDATA - System Cache Data Ram Zeroization. - 10 - 1 - - - SCACHETAG - System Cache Tag Zeroization. - 11 - 1 - - - CRYPTO - Crypto (MAA) Memory. - 12 - 1 - - - USBFIFO - USB FIFO Zeroization. - 13 - 1 - - SCCK - Smart Card Clock Control. - 0x34 - 0x00000000 + ECC_DATA + ECC Data Register. + 0x28 - SC0CD - Smart Card0 Clock Divider + ECC_EVEN + Error Correction Code Odd Data. 0 - 6 + 9 + + + ECC_ODD + Error Correction Code Even Data. + 16 + 9 + + + + 4 + 4 + DATA[%s] + Flash Write Data. + 0x30 + - SC1CD - Smart Card1 Clock Divider - 8 - 6 + DATA + Data next operation. + 0 + 32 + + + + + GCR + Global Control Registers. + 0x40000000 + + 0 + 0x400 + registers + + - SYSST - System Status Register. - 0x40 + SYSCTRL + System Control. + 0x00 + 0xFFFFFFFE - ICELOCK - ARM ICE Lock Status. + BSTAPEN + Boundary Scan TAP enable. When enabled, the JTAG port is connected to the Boundary Scan TAP. Otherwise, the port is connected to the ARM ICE function. This bit is reset by the POR. Reset value and access depend on the part number. 0 1 - unlocked - ICE is unlocked. + dis + Boundary Scan TAP port disabled. 0 - locked - ICE is locked. + en + Boundary Scan TAP port enabled. 1 - CODEINTERR - Code Integrity Error Flag. This bit indicates a code integrity error has occured in XiP interface. + SBUSARB + System bus abritration scheme. These bits are used to select between Fixed-burst abritration and Round-Robin scheme. The Round-Robin scheme is selected by default. These bits are reset by the system reset. 1 - 1 + 2 - norm - Normal Operating Condition. + fix + Fixed Burst abritration. 0 - code - Code Integrity Error. + round + Round-robin scheme. 1 - SCMEMF - System Cache Memory Fault Flag. This bit indicates a memory fault has occured in the System Cache while receiving data from the Hyperbus Interface. - 5 + FLASH0_PAGE_FLIP + Flips the Flash bottom and top halves. (Depending on the total flash size, each half is either 256K or 512K). Initiating a flash page flip will cause a flush of both the data buffer on the DCODE bus and the internal instruction buffer. + 4 1 - norm - Normal Operating Condition. + normal + Physical layout matches logical layout. 0 - memory - Memory Fault. + swapped + Bottom half mapped to logical top half and vice versa. 1 - - - - RST1 - Reset 1. - 0x44 - - I2C1 - I2C1 Reset. - 0 - 1 - - - PT - PT Reset. - 1 - 1 - - - SPIXIP - SPI XiP Master Reset. - 3 - 1 - - - XSPIM - GSPI XiP Master Controller Reset. - 4 - 1 - - - GPIO3 - GPIO3 Reset. + FPU_DIS + Cortex M4 Floating Point Disable This bit is used to disable the floating-point unit of the Cortex-M4. 5 1 - - SDHC - SDHC/SDIO Reset. + + ICC0_FLUSH + Code Cache Flush. This bit is used to flush the code caches and the instruction buffer of the Cortex-M4. 6 1 + + + normal + Normal Code Cache Operation + 0 + + + flush + Code Caches and CPU instruction buffer are flushed + 1 + + - - OWIRE - OWIRE Reset. + + SRCC_FLUSH + Data Cache Flush. The system cache (s) will be flushed when this bit is set. 7 1 + + + normal + Normal System Cache Operation + 0 + + + flush + System Cache is flushed + 1 + + - - WDT1 - WDT1 Reset. - 8 - 1 - - - SPI3 - SPI3 Reset. - 9 - 1 - - - AC - AC Reset. - 14 - 1 - - - SPIXMEM - SPIXMEM Reset. - 15 - 1 - - - I2C2 - I2C2 Reset. - 17 - 1 - - - UART3 - UART3 Reset. - 18 - 1 - - - UART4 - UART4 Reset. - 19 - 1 - - - UART5 - UART5 Reset. - 20 - 1 - - - KBD - KBD Reset. - 21 - 1 - - - ADC9 - ADC9 Reset. - 22 - 1 - - - SC0 - SC0 Reset. - 23 - 1 - - - SC1 - SC1 Reset. - 24 - 1 - - - NFC - NFC Reset. - 25 - 1 - - - EMAC - EMAC Reset. - 26 - 1 - - - PCIF - PCIF Reset. - 27 - 1 - - - HTMR0 - HTIMER0 Reset. - 28 - 1 - - - HTMR1 - HTIMER1 Reset. - 29 - 1 - - - - - PCLKDIS1 - Peripheral Clock Disable. - 0x48 - - UART2 - UART2 Disable. - 1 + SRCC_DIS + Data Cache Disable. The system cache (s) will be completely disabled when this bit is set. + 9 1 en - Enable. + Is enabled. 0 dis - Disable. + Is Disabled. 1 - - TRNG - TRNG Disable. - 2 - 1 - - - WDT0 - WDT0 Clock Disable - 4 - 1 - - - WDT1 - WDT1 Clock Disable - 5 - 1 - - - GPIO3 - GPIO3 Disable - 6 - 1 - - - SCACHE - System Cache Clock Disable. - 7 - 1 - - - HA0 - Hardware Accelerator 0 Clock Disable. - 8 - 1 - - - SDHC - SDHC/SDIO Clock Disable. - 10 - 1 - - - ICC0 - ICache Clock Disable. - 11 - 1 - - - ICCXIP - ICache XIP Clock Disable. - 12 - 1 - - - OWIRE - One-Wire Clock Disable. + + CCHK + Compute ROM Checksum. This bit is self-cleared when calculation is completed. Once set, software clearing this bit is ignored and the bit will remain set until the operation is completed. 13 1 + + + complete + No operation/complete. + 0 + + + start + Start operation. + 1 + + - - SPI3 - SPI3 Clock Disable. - 14 - 1 - - - SPIXIP - SPI-XIP Data Clock Disable - 20 - 1 - - - I2C2 - I2C2 Clock Disable - 21 - 1 - - - UART3 - UART3 Clock Disable - 22 - 1 - - - UART4 - UART4 Clock Disable - 23 - 1 - - - UART5 - UART5 Clock Disable - 24 - 1 - - - ADC9 - ADC9 Clock Disable - 25 + + CHKRES + ROM Checksum Result. This bit is only valid when CHKRD=1. + 15 1 + + + pass + ROM Checksum Correct. + 0 + + + fail + ROM Checksum Fail. + 1 + + - - SC0 - SC0 Clock Disable - 26 + + + + RST0 + Reset. + 0x04 + + + DMA + DMA Reset. + 0 1 - - SC1 - SC1 Clock Disable - 27 + + WDT0 + Watchdog Timer Reset. + 1 1 - - NFC - NFC Clock Disable - 28 + + GPIO0 + GPIO0 Reset. Setting this bit to 1 resets GPIO0 pins to their default states. + 2 1 - - EMAC - EMAC Clock Disable - 29 + + GPIO1 + GPIO1 Reset. Setting this bit to 1 resets GPIO1 pins to their default states. + 3 1 - - HA1 - Hardware Accelerator 1 Clock Disable - 30 + + GPIO2 + GPIO2 Reset. Setting this bit to 1 resets GPIO2 pins to their default states. + 4 1 - - PCIF - PCIF Clock Disable - 31 + + TMR0 + Timer0 Reset. Setting this bit to 1 resets Timer 0 blocks. + 5 1 - - - - EVENTEN - Event Enable Register. - 0x4C - - - DMA - Enable DMA event. When this bit is set, a DMA event will cause an RXEV event to wake the CPU from WFE sleep mode. - 0 + + TMR1 + Timer1 Reset. Setting this bit to 1 resets Timer 1 blocks. + 6 1 - - RX - Enable RXEV pin event. When this bit is set, a logic high of GPIO0[24] will cause an RXEV event to wake the CPU from WFE sleep mode. - 1 + + TMR2 + Timer2 Reset. Setting this bit to 1 resets Timer 2 blocks. + 7 1 - - TX - Enable TXEV pin event. When this bit is set, TXEV event from the CPU is output to GPIO[25]. - 2 + + TMR3 + Timer3 Reset. Setting this bit to 1 resets Timer 3 blocks. + 8 1 - - - - REVISION - Revision Register. - 0x50 - read-only - - - REVISION - Manufacturer Chip Revision. - 0 - 16 - - - - - SYSIE - System Status Interrupt Enable Register. - 0x54 - - - ICEUNLOCK - ARM ICE Unlock Interrupt Enable. - 0 - 1 - - - dis - disabled. - 0 - - - en - enabled. - 1 - - + + TMR4 + Timer4 Reset. Setting this bit to 1 resets Timer 4 blocks. + 9 + 1 - - CIE - Code Integrity Error Interrupt Enable. - 1 + + TMR5 + Timer5 Reset. Setting this bit to 1 resets Timer 5 blocks. + 10 1 - - SCMF - System Cache Memory Fault Interrupt Enable. - 5 + + UART0 + UART0 Reset. Setting this bit to 1 resets all UART 0 blocks. + 11 1 - - - - IPOCNT - IPO Warmup Count Register. - 0x58 - - - WMUPCNT - TBD - 0 - 10 + + UART1 + UART1 Reset. Setting this bit to 1 resets all UART 1 blocks. + 12 + 1 - - - - ECCERR - ECC Error Register - 0x64 - - - RAM0 - ECC System RAM0 Error Flag. Write 1 to clear. - 0 + + SPI0 + SPI0 Reset. Setting this bit to 1 resets all SPI 0 blocks. + 13 1 - - RAM1 - ECC System RAM1 Error Flag. Write 1 to clear. - 1 + + SPI1 + SPI1 Reset. Setting this bit to 1 resets all SPI 1 blocks. + 14 1 - - RAM2 - ECC System RAM2 Error Flag. Write 1 to clear. - 2 + + SPI2 + SPI2 Reset. Setting this bit to 1 resets all SPI 2 blocks. + 15 1 - - RAM3 - ECC System RAM3 Error Flag. Write 1 to clear. - 3 + + I2C0 + I2C0 Reset. + 16 1 - - RAM4 - ECC System RAM4 Error Flag. Write 1 to clear. - 4 + + RTC + Real Time Clock Reset. + 17 1 - - RAM5 - ECC System RAM5 Error Flag. Write 1 to clear. - 5 + + CRYPTO + Cryptographic Reset. Setting this bit to 1 resets the AES block, the SHA block and the DES block. + 18 1 - - ICC0 - ECC Icache0 Error Flag. Write 1 to clear. - 8 + + TMR6 + Timer6 Reset. Setting this bit to 1 resets Timer 6 blocks. + 20 1 - - ICSPIXF - ECC SFCC Instruction Cache Error Flag. Write 1 to clear. - 10 + + TMR7 + Timer7 Reset. Setting this bit to 1 resets Timer 7 blocks. + 21 1 - - FLASH0 - ECC Flash0 Error Flag. Write 1 to clear. - 11 + + CLCD + CLCD Reset. Setting this bit to 1 resets the CLCD block. + 22 1 - - FLASH1 - ECC Flash1 Error Flag. Write 1 to clear. - 12 + + USB + USB Reset. Setting this bit resets both USB blocks. + 23 1 - - - - ECCCED - ECC Not Double Error Detect Register - 0x68 - - - RAM0 - ECC System RAM0 Error Flag. Write 1 to clear. - 0 + + ADC + Analog to Digital Reset. + 26 1 - - RAM1 - ECC System RAM1 Not Double Error Detect. Write 1 to clear. - 1 + + UART2 + UART2 Reset. Setting this bit to 1 resets all UART 2 blocks. + 28 1 - - RAM2 - ECC System RAM2 Not Double Error Detect. Write 1 to clear. - 2 + + SOFT + Soft Reset. Setting this bit to 1 resets everything except the CPU and the watchdog timer. + 29 1 - - RAM3 - ECC System RAM3 Not Double Error Detect. Write 1 to clear. - 3 + + PERIPH + Peripheral Reset. Setting this bit to 1 resets all peripherals. The CPU core, the watchdog timer, and all GPIO pins are unaffected by this reset. + 30 1 - - RAM4 - ECC System RAM4 Not Double Error Detect. Write 1 to clear. - 4 + + SYS + System Reset. Setting this bit to 1 resets the CPU core and all peripherals, including the watchdog timer. + 31 1 + + + + CLKCTRL + Clock Control. + 0x08 + 0x00000008 + - RAM5 - ECC System RAM5 Not Double Error Detect. Write 1 to clear. - 5 - 1 + SYSCLK_DIV + Prescaler Select. This 3 bit field sets the system operating frequency by controlling the prescaler that divides the output of the PLL0. + 6 + 3 + + + div1 + Divide by 1. + 0 + + + div2 + Divide by 2. + 1 + + + div4 + Divide by 4. + 2 + + + div8 + Divide by 8. + 3 + + + div16 + Divide by 16. + 4 + + + div32 + Divide by 32. + 5 + + + div64 + Divide by 64. + 6 + + + div128 + Divide by 128. + 7 + + + + + SYSCLK_SEL + Clock Source Select. This 3 bit field selects the source for the system clock. + 9 + 3 + + + ISO + Internal Secondary Oscilatior Clock + 0 + + + ERFO + 27MHz Crystal is used for the system clock. + 2 + + + INRO + 8kHz Internal Nano Ring Oscillator is used for the system clock. + 3 + + + IPO + The internal Primary oscillator is used for the system clock. + 4 + + + IBRO + The internal Baud Rate oscillator is used for the system clock. + 5 + + + ERTCO + 32kHz is used for the system clock. + 6 + + - ICC0 - ECC Icache0 Not Double Error Detect. Write 1 to clear. - 8 + SYSCLK_RDY + Clock Ready. This read only bit reflects whether the currently selected system clock source is running. + 13 1 + read-only + + + busy + Switchover to the new clock source (as selected by CLKSEL) has not yet occurred. + 0 + + + ready + System clock running from CLKSEL clock source. + 1 + + - ICSPIXF - ECC IcacheXIP Not Double Error Detect. Write 1 to clear. - 10 + CCD + Cryptographic clock divider + 15 1 + read-only + + + non_div + The cryptographic accelerator clock is running in non-divided mode. + 0 + + + div + The cryptographic accelerator clock is running in divided mode. + 1 + + - FLASH0 - ECC Flash0 Not Double Error Detect. Write 1 to clear. - 11 + ERFO_EN + 27MHz Crystal Oscillator Enable. + 16 1 + + + dis + Is Disabled. + 0 + + + en + Is Enabled. + 1 + + - FLASH1 - ECC Flash1 Not Double Error Detect. Write 1 to clear. - 12 + ERTCO_EN + 32kHz Crystal Oscillator Enable. + 17 1 - - - - ECCIE - ECC IRQ Enable Register - 0x6C - - - RAM0 - ECC System RAM0 Interrupt Enable. - 0 + + ISO_EN + 60MHz High Frequency Internal Reference Clock Enable. + 18 1 - - RAM1 - ECC System RAM1 Interrupt Enable. - 1 + + IPO_EN + 96MHz High Frequency Internal Reference Clock Enable. + 19 1 - - RAM2 - ECC System RAM2 Interrupt Enable. - 2 + + IBRO_EN + 8MHz High Frequency Internal Reference Clock Enable. + 20 1 - RAM3 - ECC System RAM3 Interrupt Enable. - 3 + IBRO_VS + 7.3728MHz Internal Oscillator Voltage Source Select + 21 1 - RAM4 - ECC System RAM4 Interrupt Enable. - 4 + ERFO_RDY + 27MHz Crystal Oscillator Ready + 24 1 + read-only + + + not + Is not Ready. + 0 + + + ready + Is Ready. + 1 + + - RAM5 - ECC System RAM5 Interrupt Enable. - 5 + ERTCO_RDY + 32kHz Crystal Oscillator Ready + 25 1 + read-only + + + not + Is not Ready. + 0 + + + ready + Is Ready. + 1 + + - - ICC0 - ECC Icache0 Interrupt Enable. - 8 + + ISO_RDY + 60MHz ISO Ready. + 26 1 - - ICSPIXF - ECC IcacheXIP Interrupt Enable. - 10 + + IPO_RDY + Internal Primary Oscillator Ready. + 27 1 - - FLASH0 - ECC Flash0 Interrupt Enable. - 11 + + IBRO_RDY + Internal Baud Rate Oscillator Ready. + 28 1 - - FLASH1 - ECC Flash1 Interrupt Enable. - 12 + + INRO_RDY + Internal Nano Ring Oscillator Low Frequency Reference Clock Ready. + 29 1 - ECCADDR - ECC Error Address Register - 0x70 + PM + Power Management. + 0x0C - DATARAMADDR - ECC Error Address/DATA RAM Error Address + MODE + Operating Mode. This two bit field selects the current operating mode for the device. Note that code execution only occurs during ACTIVE mode. 0 - 14 - - - DATARAMBANK - ECC Error Address/DATA RAM Error Bank - 14 - 1 - - - DATARAMERR - DATA RAM ERROR - 15 - 1 - - - TAGRAMADDR - ECC Error Address/TAG RAM Error Address - 16 - 14 - - - TAGRAMBANK - ECC Error Address/TAG RAM Error Bank - 30 - 1 - - - TAGRAMERR - TAG RAM ERROR - 31 - 1 + 3 + + + active + Active Mode. + 0 + + + deepsleep + DeepSleep Mode. + 2 + + + shutdown + Shutdown Mode. + 3 + + + backup + Backup Mode. + 4 + + - - - - NFC_LDOCR - NFC LDO Control Register - 0x74 - - EN - Enabled the dedicated NFC LDO + GPIO_WE + GPIO Wake Up Enable. This bit enables all GPIO pins as potential wakeup sources. Any GPIO configured for wakeup is capable of causing an exit from IDLE or STANDBY modes when this bit is set. 4 1 - - PULLD - Enabled the dedicated NFC LDO pin pulldown + + RTC_WE + RTC Alarm Wake Up Enable. This bit enables RTC alarm as wakeup source. If enabled, the desired RTC alarm must be configured via the RTC control registers. 5 1 - - VSEL - Voltage Selection for NFC LDO + + USB_WE + USB Wake Up Enable. This bit enables USB activity as wakeup source. 6 - 2 + 1 - - BYPEN - Bypass enable - 8 + + HA0_WE + Hardware Accelerator 0 Wake Up Enable. This bit enables USB activity as wakeup source. + 7 1 - - DISCH - TBD + + HA1_WE + Hardware Accelerator 1 Wake Up Enable. This bit enables USB activity as wakeup source. 9 1 - EN_DLY - TBD - 15 + ERFO_PD + Radio Frequency oscilator Crystal Power Down. This bit selects the power state in DEEPSLEEP mode. + 12 1 + + + active + Mode is Active. + 0 + + + deepsleep + Powered down in DEEPSLEEP. + 1 + + - BYP_EN_DLY - TBD - 14 + ISO_PD + Internal Secondary Oscilator Power Down. This bit selects the power state in DEEPSLEEP mode. + 15 1 + + + active + Mode is Active. + 0 + + + deepsleep + Powered down in DEEPSLEEP. + 1 + + - - - - NFCLDO_DLY - NFC LDO Delay Register - 0x78 - - BYPCNT - TBD - 0 - 8 + IPO_PD + Internal Primary Oscilatory power down. This bit selects the power state in DEEPSLEEP mode. + 16 + 1 + + + active + Mode is Active. + 0 + + + deepsleep + Powered down in DEEPSLEEP. + 1 + + - ENCNT - TBD - 8 - 8 + IBRO_PD + Internal Baud Rate Oscillator power down. This bit selects the power state in DEEPSLEEP mode. + 17 + 1 + + + active + Mode is Active. + 0 + + + deepsleep + Powered down in DEEPSLEEP. + 1 + + - - - - - - - GPIO0 - Individual I/O for each GPIO - GPIO - 0x40008000 - - 0x00 - 0x1000 - registers - - - GPIO0 - GPIO0 interrupt. - 24 - - - - EN0 - GPIO Function Enable Register. Each bit controls the GPIO_EN setting for one GPIO pin on the associated port. - 0x00 - - GPIO_EN - Mask of all of the pins on the port. - 0 - 32 + NFC_PD + When set, the NFC radio becomes inactive when the upon entering DEEPSLEEP mode + 18 + 1 - ALTERNATE - Alternate function enabled. + active + Mode is Active. 0 - GPIO - GPIO function is enabled. + deepsleep + Powered down in DEEPSLEEP. 1 - - - - EN0_SET - GPIO Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN to 1, without affecting other bits in that register. - 0x04 - - ALL - Mask of all of the pins on the port. - 0 - 32 + XTALBP + XTAL Bypass + 20 + 1 + + + normal + Normal + 0 + + + bypass + Bypass + 1 + + - EN0_CLR - GPIO Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN to 0, without affecting other bits in that register. - 0x08 + PCLKDIV + Peripheral Clock Divider. + 0x18 + 0x00000001 - ALL - Mask of all of the pins on the port. + PCF + These bits determine the clock frequency for the UART, I2C and Key Pad peripherals. These peripherals have an adaptive clock generator that dynamically adjusts the peripheral frequency based on the main system bus frequency. These bits are dynamically updated when the PLL0 is selected as the system clock source and are set by hardware. These bits determine the clock frequency for the UART, I2C and Key Pad peripherals. These peripherals have an adaptive clock generator that dynamically adjusts the peripheral frequency based on the main system bus frequency. These bits are dynamically updated when the PLL0 is selected as the system clock source and are set by hardware. 0 - 32 + 3 + + + 96MHz + 2 + + + 48MHz + 3 + + + 24MHz + 4 + + + 12MHz + 5 + + + 6MHz + 6 + + + 3MHz + 7 + + - - - - OUT_EN - GPIO Output Enable Register. Each bit controls the GPIO_OUT_EN setting for one GPIO pin in the associated port. - 0x0C - - GPIO_OUT_EN - Mask of all of the pins on the port. - 0 - 32 + PCFWEN + PCF Write Enable. This bit allows the PCF Register bits to be updated by Software. + 3 + 1 - dis - GPIO Output Disable + blocked + Writes to PCF are blocked. 0 - en - GPIO Output Enable + allowed + Writes to PCF are allowed + 1 + + + + + SDHCFRQ + SDHC Clock Frequency. This bits defines the clock frequency of SDHC. + 7 + 1 + + + 48MHz + 0 + + + 24MHz 1 - - - - OUT_EN_SET - GPIO Output Enable Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT_EN to 1, without affecting other bits in that register. - 0x10 - - - ALL - Mask of all of the pins on the port. - 0 - 32 - - - - - OUT_EN_CLR - GPIO Output Enable Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT_EN to 0, without affecting other bits in that register. - 0x14 - - ALL - Mask of all of the pins on the port. - 0 - 32 + ADCFRQ + ADC clock Frequency. These bits define the ADC clock frequency. FADC = FPCLK/ (ADCFRQ). + 10 + 4 - - - - OUT - GPIO Output Register. Each bit controls the GPIO_OUT setting for one pin in the associated port. This register can be written either directly, or by using the GPIO_OUT_SET and GPIO_OUT_CLR registers. - 0x18 - - GPIO_OUT - Mask of all of the pins on the port. - 0 - 32 + AON_CLKDIV + Always-ON (AON) domain CLock Divider. These bits define the AON domain clock divider. + 14 + 2 - low - Drive Logic 0 (low) on GPIO output. + div_4 + PCLK divide by 4. 0 - high - Drive logic 1 (high) on GPIO output. + div_8 + PCLK divide by 8. 1 + + div_16 + PCLK divide by 16. + 2 + + + div_32 + PCLK divide by 32. + 3 + - OUT_SET - GPIO Output Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT to 1, without affecting other bits in that register. - 0x1C - write-only + PCLKDIS0 + Peripheral Clock Disable. + 0x24 - GPIO_OUT_SET - Mask of all of the pins on the port. + GPIO0 + GPIO0 Clock Disable. 0 - 32 + 1 - no - No Effect. + en + enable it. 0 - set - Set GPIO_OUT bit in this position to '1' + dis + disable it. 1 - - - - OUT_CLR - GPIO Output Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT to 0, without affecting other bits in that register. - 0x20 - write-only - - - GPIO_OUT_CLR - Mask of all of the pins on the port. - 0 - 32 + + GPIO1 + GPIO1 Disable. + 1 + 1 + + + GPIO2 + GPIO2 Disable. + 2 + 1 + + + USB + USB Disable. + 3 + 1 + + + CLCD + CLCD Disable. + 4 + 1 + + + DMA + DMA Disable. + 5 + 1 + + + SPI0 + SPI 0 Disable. + 6 + 1 + + + SPI1 + SPI 1 Disable. + 7 + 1 + + + SPI2 + SPI 2 Disable. + 8 + 1 + + + UART0 + UART 0 Disable. + 9 + 1 + + + UART1 + UART 1 Disable. + 10 + 1 + + + I2C0 + I2C 0 Disable. + 13 + 1 + + + CRYPTO + Crypto Disable. + 14 + 1 + + + TMR0 + Timer 0 Disable. + 15 + 1 + + + TMR1 + Timer 1 Disable. + 16 + 1 + + + TMR2 + Timer 2 Disable. + 17 + 1 + + + TMR3 + Timer 3 Disable. + 18 + 1 + + + TMR4 + Timer 4 Disable. + 19 + 1 + + + TMR5 + Timer 5 Disable. + 20 + 1 + + + KBD + Secure Keyboard Disable. + 22 + 1 + + + ADC + ADC Disable. + 23 + 1 + + + TMR6 + Timer 6 Disable. + 24 + 1 + + + TMR7 + Timer 7 Disable. + 25 + 1 + + + HTMR0 + HTimer 0 Disable. + 26 + 1 + + + HTMR1 + HTimer 1 Disable. + 27 + 1 + + + I2C1 + I2C 1 Disable. + 28 + 1 + + + PT + PT Clock Disable. + 29 + 1 + + + SPIXIP + SPI XiP Disable. + 30 + 1 - - - - IN - GPIO Input Register. Read-only register to read from the logic states of the GPIO pins on this port. - 0x24 - read-only - - - GPIO_IN - Mask of all of the pins on the port. - 0 - 32 + + SPIM + SPI XiP Master Controller Disable. + 31 + 1 - INT_MODE - GPIO Interrupt Mode Register. Each bit in this register controls the interrupt mode setting for the associated GPIO pin on this port. + MEMCTRL + Memory Clock Control Register. 0x28 - GPIO_INT_MODE - Mask of all of the pins on the port. + FWS + Flash Wait State. These bits define the number of wait-state cycles per Flash data read access. Minimum wait state is 2. 0 - 32 - - - level - Interrupts for this pin are level triggered. - 0 - - - edge - Interrupts for this pin are edge triggered. - 1 - - + 3 - - - - INT_POL - GPIO Interrupt Polarity Register. Each bit in this register controls the interrupt polarity setting for one GPIO pin in the associated port. - 0x2C - - GPIO_INT_POL - Mask of all of the pins on the port. - 0 - 32 + RAMWS_EN + SRAM Wait State Enable + 4 + 1 + + + RAM0LS_EN + System RAM 0 Light Sleep Mode. + 16 + 1 - falling - Interrupts are latched on a falling edge or low level condition for this pin. + active + RAM is active. 0 - rising - Interrupts are latched on a rising edge or high condition for this pin. + light_sleep + RAM is in Light Sleep mode. 1 + + RAM1LS_EN + System RAM 1 Light Sleep Mode. + 17 + 1 + + + RAM2LS_EN + System RAM 2 Light Sleep Mode. + 18 + 1 + + + RAM3LS_EN + System RAM 3 Light Sleep Mode. + 19 + 1 + + + RAM4LS_EN + System RAM 4 Light Sleep Mode. + 20 + 1 + + + RAM5LS_EN + System RAM 5 Light Sleep Mode. + 21 + 1 + + + ICC0LS_EN + ICache RAM Light Sleep Mode. + 24 + 1 + + + ICCXIPLS_EN + ICACHE-XIP RAM Light Sleep Mode. + 25 + 1 + + + SRCCLS_EN + SysCache RAM Light Sleep Mode. + 26 + 1 + + + CRYPTOLS_EN + CRYPTO RAM Light Sleep Mode. + 27 + 1 + + + USBLS_EN + USB FIFO Light Sleep Mode. + 28 + 1 + + + ROMLS_EN + ROM Light Sleep Mode. + 29 + 1 + - IN_EN - GPIO Input Enable - 0x30 - - - INT_EN - GPIO Interrupt Enable Register. Each bit in this register controls the GPIO interrupt enable for the associated pin on the GPIO port. - 0x34 + MEMZ + Memory Zeroize Control. + 0x2C - GPIO_INT_EN - Mask of all of the pins on the port. + RAM0 + System RAM Block 0. 0 - 32 + 1 - dis - Interrupts are disabled for this GPIO pin. + nop + No operation/complete. 0 - en - Interrupts are enabled for this GPIO pin. + start + Start operation. 1 + + RAM1 + System RAM Block 1. + 1 + 1 + + + RAM2 + System RAM Block 2. + 2 + 1 + + + RAM3 + System RAM Block 3. + 3 + 1 + + + RAM4 + System RAM Block 4. + 4 + 1 + + + RAM5 + System RAM Block 5. + 5 + 1 + + + RAM6 + System RAM Block 6. + 6 + 1 + + + ICC0 + Instruction Cache. + 8 + 1 + + + ICCXIP + Instruction Cache XIP Data and Tag Ram zeroizatoin. + 9 + 1 + + + SCACHEDATA + System Cache Data Ram Zeroization. + 10 + 1 + + + SCACHETAG + System Cache Tag Zeroization. + 11 + 1 + + + CRYPTO + Crypto (MAA) Memory. + 12 + 1 + + + USBFIFO + USB FIFO Zeroization. + 13 + 1 + - INT_EN_SET - GPIO Interrupt Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_INT_EN to 1, without affecting other bits in that register. - 0x38 - - - GPIO_INT_EN_SET - Mask of all of the pins on the port. - 0 - 32 - - - no - No effect. - 0 - - - set - Set GPIO_INT_EN bit in this position to '1' - 1 - - + SCCK + Smart Card Clock Control. + 0x34 + 0x00000000 + + + SC0CD + Smart Card0 Clock Divider + 0 + 6 + + + SC1CD + Smart Card1 Clock Divider + 8 + 6 - INT_EN_CLR - GPIO Interrupt Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_EN to 0, without affecting other bits in that register. - 0x3C + SYSST + System Status Register. + 0x40 - GPIO_INT_EN_CLR - Mask of all of the pins on the port. + ICELOCK + ARM ICE Lock Status. 0 - 32 + 1 - no - No Effect. + unlocked + ICE is unlocked. 0 - clear - Clear GPIO_INT_EN bit in this position to '0' + locked + ICE is locked. 1 - - - - INT_STAT - GPIO Interrupt Status Register. Each bit in this register contains the pending interrupt status for the associated GPIO pin in this port. - 0x40 - read-only - - GPIO_INT_STAT - Mask of all of the pins on the port. - 0 - 32 + CODEINTERR + Code Integrity Error Flag. This bit indicates a code integrity error has occured in XiP interface. + 1 + 1 - no - No Interrupt is pending on this GPIO pin. + norm + Normal Operating Condition. 0 - pending - An Interrupt is pending on this GPIO pin. + code + Code Integrity Error. 1 - - - - INT_CLR - GPIO Status Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_STAT to 0, without affecting other bits in that register. - 0x48 - - - ALL - Mask of all of the pins on the port. - 0 - 32 - - - - - WAKE_EN - GPIO Wake Enable Register. Each bit in this register controls the PMU wakeup enable for the associated GPIO pin in this port. - 0x4C - - GPIO_WAKE_EN - Mask of all of the pins on the port. - 0 - 32 + SCMEMF + System Cache Memory Fault Flag. This bit indicates a memory fault has occured in the System Cache while receiving data from the Hyperbus Interface. + 5 + 1 - dis - PMU wakeup for this GPIO is disabled. + norm + Normal Operating Condition. 0 - en - PMU wakeup for this GPIO is enabled. + memory + Memory Fault. 1 @@ -8417,573 +6573,758 @@ - WAKE_EN_SET - GPIO Wake Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_WAKE_EN to 1, without affecting other bits in that register. - 0x50 + RST1 + Reset 1. + 0x44 - ALL - Mask of all of the pins on the port. + I2C1 + I2C1 Reset. 0 - 32 + 1 - - - - WAKE_EN_CLR - GPIO Wake Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_WAKE_EN to 0, without affecting other bits in that register. - 0x54 - - - ALL - Mask of all of the pins on the port. - 0 - 32 + + PT + PT Reset. + 1 + 1 + + + SPIXIP + SPI XiP Master Reset. + 3 + 1 + + + XSPIM + GSPI XiP Master Controller Reset. + 4 + 1 + + + GPIO3 + GPIO3 Reset. + 5 + 1 + + + SDHC + SDHC/SDIO Reset. + 6 + 1 + + + OWIRE + OWIRE Reset. + 7 + 1 + + + WDT1 + WDT1 Reset. + 8 + 1 + + + SPI3 + SPI3 Reset. + 9 + 1 + + + AC + AC Reset. + 14 + 1 + + + SPIXMEM + SPIXMEM Reset. + 15 + 1 + + + I2C2 + I2C2 Reset. + 17 + 1 + + + UART3 + UART3 Reset. + 18 + 1 + + + UART4 + UART4 Reset. + 19 + 1 + + + UART5 + UART5 Reset. + 20 + 1 + + + KBD + KBD Reset. + 21 + 1 + + + ADC9 + ADC9 Reset. + 22 + 1 + + + SC0 + SC0 Reset. + 23 + 1 + + + SC1 + SC1 Reset. + 24 + 1 + + + NFC + NFC Reset. + 25 + 1 + + + EMAC + EMAC Reset. + 26 + 1 + + + PCIF + PCIF Reset. + 27 + 1 + + + HTMR0 + HTIMER0 Reset. + 28 + 1 + + + HTMR1 + HTIMER1 Reset. + 29 + 1 - INT_DUAL_EDGE - GPIO Interrupt Dual Edge Mode Register. Each bit in this register selects dual edge mode for the associated GPIO pin in this port. - 0x5C + PCLKDIS1 + Peripheral Clock Disable. + 0x48 - GPIO_INT_DUAL_EDGE - Mask of all of the pins on the port. - 0 - 32 + UART2 + UART2 Disable. + 1 + 1 - - no - No Effect. - 0 - en - Dual Edge mode is enabled. If edge-triggered interrupts are enabled on this GPIO pin, then both rising and falling edges will trigger interrupts regardless of the GPIO_INT_POL setting. - 1 - - - - - - - PAD_CFG1 - GPIO Input Mode Config 1. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port. - 0x60 - - - GPIO_PAD_CFG1 - The two bits in GPIO_PAD_CFG1 and GPIO_PAD_CFG2 for each GPIO pin work together to determine the pad mode when the GPIO is set to input mode. - 0 - 32 - - - impedance - High Impedance. + Enable. 0 - pu - Weak pull-up mode. + dis + Disable. 1 - - pd - weak pull-down mode. - 2 - - - - - PAD_CFG2 - GPIO Input Mode Config 2. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port. - 0x64 - - - GPIO_PAD_CFG2 - The two bits in GPIO_PAD_CFG1 and GPIO_PAD_CFG2 for each GPIO pin work together to determine the pad mode when the GPIO is set to input mode. - 0 - 32 - - - impedance - High Impedance. - 0 - - - pu - Weak pull-up mode. - 1 - - - pd - weak pull-down mode. - 2 - - + + TRNG + TRNG Disable. + 2 + 1 - - - - EN1 - GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port. - 0x68 - - - GPIO_EN1 - Mask of all of the pins on the port. - 0 - 32 - - - primary - Primary function selected. - 0 - - - secondary - Secondary function selected. - 1 - - + + WDT0 + WDT0 Clock Disable + 4 + 1 - - - - EN1_SET - GPIO Alternate Function Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN1 to 1, without affecting other bits in that register. - 0x6C - - - ALL - Mask of all of the pins on the port. - 0 - 32 + + WDT1 + WDT1 Clock Disable + 5 + 1 - - - - EN1_CLR - GPIO Alternate Function Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN1 to 0, without affecting other bits in that register. - 0x70 - - - ALL - Mask of all of the pins on the port. - 0 - 32 + + GPIO3 + GPIO3 Disable + 6 + 1 + + + SCACHE + System Cache Clock Disable. + 7 + 1 + + + HA0 + Hardware Accelerator 0 Clock Disable. + 8 + 1 + + + SDHC + SDHC/SDIO Clock Disable. + 10 + 1 + + + ICC0 + ICache Clock Disable. + 11 + 1 + + + ICCXIP + ICache XIP Clock Disable. + 12 + 1 + + + OWIRE + One-Wire Clock Disable. + 13 + 1 + + + SPI3 + SPI3 Clock Disable. + 14 + 1 + + + SPIXIP + SPI-XIP Data Clock Disable + 20 + 1 + + + I2C2 + I2C2 Clock Disable + 21 + 1 + + + UART3 + UART3 Clock Disable + 22 + 1 + + + UART4 + UART4 Clock Disable + 23 + 1 + + + UART5 + UART5 Clock Disable + 24 + 1 + + + ADC9 + ADC9 Clock Disable + 25 + 1 + + + SC0 + SC0 Clock Disable + 26 + 1 + + + SC1 + SC1 Clock Disable + 27 + 1 + + + NFC + NFC Clock Disable + 28 + 1 + + + EMAC + EMAC Clock Disable + 29 + 1 + + + HA1 + Hardware Accelerator 1 Clock Disable + 30 + 1 + + + PCIF + PCIF Clock Disable + 31 + 1 - EN2 - GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port. - 0x74 + EVENTEN + Event Enable Register. + 0x4C - GPIO_EN2 - Mask of all of the pins on the port. + DMA + Enable DMA event. When this bit is set, a DMA event will cause an RXEV event to wake the CPU from WFE sleep mode. 0 - 32 - - - primary - Primary function selected. - 0 - - - secondary - Secondary function selected. - 1 - - + 1 - - - - EN2_SET - GPIO Alternate Function 2 Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN2 to 1, without affecting other bits in that register. - 0x78 - - ALL - Mask of all of the pins on the port. - 0 - 32 + RX + Enable RXEV pin event. When this bit is set, a logic high of GPIO0[24] will cause an RXEV event to wake the CPU from WFE sleep mode. + 1 + 1 + + + TX + Enable TXEV pin event. When this bit is set, TXEV event from the CPU is output to GPIO[25]. + 2 + 1 - EN2_CLR - GPIO Wake Alternate Function Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN2 to 0, without affecting other bits in that register. - 0x7C + REVISION + Revision Register. + 0x50 + read-only - ALL - Mask of all of the pins on the port. + REVISION + Manufacturer Chip Revision. 0 - 32 + 16 - DS - GPIO Drive Strength Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode. - 0xB0 + SYSIE + System Status Interrupt Enable Register. + 0x54 - GPIO_DS - Mask of all of the pins on the port. + ICEUNLOCK + ARM ICE Unlock Interrupt Enable. 0 - 32 + 1 - ld - GPIO port pin is in low-drive mode. + dis + disabled. 0 - hd - GPIO port pin is in high-drive mode. + en + enabled. 1 - - - - DS1 - GPIO Drive Strength 1 Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode. - 0xB4 - - - GPIO_DS1 - Mask of all of the pins on the port. - 0 - 32 + + CIE + Code Integrity Error Interrupt Enable. + 1 + 1 + + + SCMF + System Cache Memory Fault Interrupt Enable. + 5 + 1 - PS - GPIO Pull Select Mode. - 0xB8 + IPOCNT + IPO Warmup Count Register. + 0x58 - ALL - Mask of all of the pins on the port. + WMUPCNT + TBD 0 - 32 + 10 - VSSEL - GPIO Voltage Select. - 0xC0 + ECCERR + ECC Error Register + 0x64 - ALL - Mask of all of the pins on the port. + RAM0 + ECC System RAM0 Error Flag. Write 1 to clear. 0 - 32 + 1 - - - - - - - GPIO1 - Individual I/O for each GPIO 1 - 0x40009000 - - GPIO1 - GPIO1 IRQ - 25 - - - - - GPIO2 - Individual I/O for each GPIO 2 - 0x4000A000 - - GPIO2 - GPIO2 IRQ - 26 - - - - - GPIO3 - Individual I/O for each GPIO 3 - 0x4000B000 - - GPIO3 - GPIO3 IRQ - 58 - - - - - HA - Hardware Accelerator - 0x40036000 - - 0x00 - 0x1000 - registers - - - HA - Smart DMA interrupt. - 60 - - - - IP - Q30E Instruction Pointer. - 0x00 - read-only - - - SP - Q30E Stack Pointer. - 0x04 - read-only - - - DP0 - Q30E Data Pointer 0. - 0x08 - read-only - - - DP1 - Q30E Data Pointer 1. - 0x0C - read-only - - - BP - Q30E Frame Pointer Base. - 0x10 - read-only - - - OFFS - Q30E Frame Pointer Offset. - 0x14 - read-only - - - LC0 - Q30E Loop Counter 0. - 0x18 - read-only - - - LC1 - Q30E Loop Counter 1. - 0x1C - read-only - - - A0 - Q30E Accumulator 0. - 0x20 - read-only - - - A1 - Q30E Accumulator 1. - 0x24 - read-only - - - A2 - Q30E Accumulator 2. - 0x28 - read-only - - - A3 - Q30E Accumulator 3. - 0x2C - read-only + + RAM1 + ECC System RAM1 Error Flag. Write 1 to clear. + 1 + 1 + + + RAM2 + ECC System RAM2 Error Flag. Write 1 to clear. + 2 + 1 + + + RAM3 + ECC System RAM3 Error Flag. Write 1 to clear. + 3 + 1 + + + RAM4 + ECC System RAM4 Error Flag. Write 1 to clear. + 4 + 1 + + + RAM5 + ECC System RAM5 Error Flag. Write 1 to clear. + 5 + 1 + + + ICC0 + ECC Icache0 Error Flag. Write 1 to clear. + 8 + 1 + + + ICSPIXF + ECC SFCC Instruction Cache Error Flag. Write 1 to clear. + 10 + 1 + + + FLASH0 + ECC Flash0 Error Flag. Write 1 to clear. + 11 + 1 + + + FLASH1 + ECC Flash1 Error Flag. Write 1 to clear. + 12 + 1 + + - WDCN - Q30E Watchdog Control. - 0x30 - read-only + ECCCED + ECC Not Double Error Detect Register + 0x68 + + + RAM0 + ECC System RAM0 Error Flag. Write 1 to clear. + 0 + 1 + + + RAM1 + ECC System RAM1 Not Double Error Detect. Write 1 to clear. + 1 + 1 + + + RAM2 + ECC System RAM2 Not Double Error Detect. Write 1 to clear. + 2 + 1 + + + RAM3 + ECC System RAM3 Not Double Error Detect. Write 1 to clear. + 3 + 1 + + + RAM4 + ECC System RAM4 Not Double Error Detect. Write 1 to clear. + 4 + 1 + + + RAM5 + ECC System RAM5 Not Double Error Detect. Write 1 to clear. + 5 + 1 + + + ICC0 + ECC Icache0 Not Double Error Detect. Write 1 to clear. + 8 + 1 + + + ICSPIXF + ECC IcacheXIP Not Double Error Detect. Write 1 to clear. + 10 + 1 + + + FLASH0 + ECC Flash0 Not Double Error Detect. Write 1 to clear. + 11 + 1 + + + FLASH1 + ECC Flash1 Not Double Error Detect. Write 1 to clear. + 12 + 1 + + - INT_MUX_CTRL0 - Interrupt Mux Control 0. - 0x80 - read-write + ECCIE + ECC IRQ Enable Register + 0x6C - INTSEL16 - Interrupt Selection For 16th Interrupt. + RAM0 + ECC System RAM0 Interrupt Enable. 0 - 8 + 1 - INTSEL17 - Interrupt Selection For 17th Interrupt. + RAM1 + ECC System RAM1 Interrupt Enable. + 1 + 1 + + + RAM2 + ECC System RAM2 Interrupt Enable. + 2 + 1 + + + RAM3 + ECC System RAM3 Interrupt Enable. + 3 + 1 + + + RAM4 + ECC System RAM4 Interrupt Enable. + 4 + 1 + + + RAM5 + ECC System RAM5 Interrupt Enable. + 5 + 1 + + + ICC0 + ECC Icache0 Interrupt Enable. 8 - 8 + 1 - INTSEL18 - Interrupt Selection For 18th Interrupt. - 16 - 8 + ICSPIXF + ECC IcacheXIP Interrupt Enable. + 10 + 1 - INTSEL19 - Interrupt Selection For 19th Interrupt. - 24 - 8 + FLASH0 + ECC Flash0 Interrupt Enable. + 11 + 1 + + + FLASH1 + ECC Flash1 Interrupt Enable. + 12 + 1 - INT_MUX_CTRL1 - Interrupt Mux Control 1. - 0x84 - read-write + ECCADDR + ECC Error Address Register + 0x70 - INTSEL20 - Interrupt Selection For 20th Interrupt. + DATARAMADDR + ECC Error Address/DATA RAM Error Address 0 - 8 + 14 - INTSEL21 - Interrupt Selection For 21st Interrupt. - 8 - 8 + DATARAMBANK + ECC Error Address/DATA RAM Error Bank + 14 + 1 - INTSEL22 - Interrupt Selection For 22nd Interrupt. + DATARAMERR + DATA RAM ERROR + 15 + 1 + + + TAGRAMADDR + ECC Error Address/TAG RAM Error Address 16 - 8 + 14 - INTSEL23 - Interrupt Selection For 23rd Interrupt. - 24 - 8 + TAGRAMBANK + ECC Error Address/TAG RAM Error Bank + 30 + 1 + + + TAGRAMERR + TAG RAM ERROR + 31 + 1 - INT_MUX_CTRL2 - Interrupt Mux Control 2. - 0x88 - read-write + NFC_LDOCR + NFC LDO Control Register + 0x74 - INTSEL24 - Interrupt Selection For 24th Interrupt. - 0 - 8 + EN + Enabled the dedicated NFC LDO + 4 + 1 + + + PULLD + Enabled the dedicated NFC LDO pin pulldown + 5 + 1 + + + VSEL + Voltage Selection for NFC LDO + 6 + 2 - INTSEL25 - Interrupt Selection For 25th Interrupt. + BYPEN + Bypass enable 8 - 8 + 1 - INTSEL26 - Interrupt Selection For 26th Interrupt. - 16 - 8 + DISCH + TBD + 9 + 1 - INTSEL27 - Interrupt Selection For 27th Interrupt. - 24 - 8 + EN_DLY + TBD + 15 + 1 + + + BYP_EN_DLY + TBD + 14 + 1 - INT_MUX_CTRL3 - Interrupt Mux Control 3. - 0x8C - read-write + NFCLDO_DLY + NFC LDO Delay Register + 0x78 - INTSEL28 - Interrupt Selection For 28th Interrupt. + BYPCNT + TBD 0 8 - INTSEL29 - Interrupt Selection For 29th Interrupt. + ENCNT + TBD 8 8 - - INTSEL30 - Interrupt Selection For 30th Interrupt. - 16 - 8 - - - INTSEL31 - Interrupt Selection For 31st Interrupt. - 24 - 8 - + + + + + GPIO0 + Individual I/O for each GPIO + GPIO + 0x40008000 + + 0x00 + 0x1000 + registers + + + GPIO0 + GPIO0 interrupt. + 24 + + - IP_ADDR - Configurable starting IP address for Q30E. - 0x90 - read-write + EN0 + GPIO Function Enable Register. Each bit controls the GPIO_EN setting for one GPIO pin on the associated port. + 0x00 - START_IP_ADDR - Starting IP address for Q30E + GPIO_EN + Mask of all of the pins on the port. 0 32 - - - - - CTRL - Control Register. - 0x94 - read-write - - - EN - Enable SDMA. - 0 - 1 - dis - Disable SDMA. + ALTERNATE + Alternate function enabled. 0 - en - Enable SDMA. + GPIO + GPIO function is enabled. 1 @@ -8991,51 +7332,50 @@ - INT_IN_CTRL - Interrupt Input From CPU Control Register. - 0xA0 - read-write + EN0_SET + GPIO Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN to 1, without affecting other bits in that register. + 0x04 - INTSET - Set Interrupt Flag. + ALL + Mask of all of the pins on the port. 0 - 1 - - - dis - Set interrupt Flag to 0. - 0 - - - set - Set Interrupt Flag to 1. - 1 - - + 32 - INT_IN_FLAG - Interrupt Input From CPU Flag. - 0xA4 - read-write + EN0_CLR + GPIO Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN to 0, without affecting other bits in that register. + 0x08 - INTFLAG - Interrupt Flag. + ALL + Mask of all of the pins on the port. 0 - 1 + 32 + + + + + OUT_EN + GPIO Output Enable Register. Each bit controls the GPIO_OUT_EN setting for one GPIO pin in the associated port. + 0x0C + + + GPIO_OUT_EN + Mask of all of the pins on the port. + 0 + 32 - no_eff - No Effect. + dis + GPIO Output Disable 0 - clear - INT_IN_FLAG =0 + en + GPIO Output Enable 1 @@ -9043,965 +7383,1219 @@ - INT_IN_IE - Interrupt Input From CPU Enable. - 0xA8 - read-write - - - INT_IN_EN - Interrupt Enable. - 0 - 1 - - - - - IRQ_FLAG - Interrupt Output To CPU Flag. - 0xB0 - read-write + OUT_EN_SET + GPIO Output Enable Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT_EN to 1, without affecting other bits in that register. + 0x10 - IRQ_FLAG - Interrupt Flag. + ALL + Mask of all of the pins on the port. 0 - 1 + 32 - IRQ_IE - Interrupt Output To CPU Control Register. - 0xB4 - read-write + OUT_EN_CLR + GPIO Output Enable Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT_EN to 0, without affecting other bits in that register. + 0x14 - IRQ_EN - Interrupt Enable. + ALL + Mask of all of the pins on the port. 0 - 1 + 32 - - - - - HTMR - High Speed Timer Module. - 0x4001B000 - - 0x00 - 0xFFF - registers - - - HTimer - HTimer interrupt. - 93 - - - SEC - HTimer Long-Interval Counter. This register contains the 32 most significant bits of the counter. - 0x00 - 0x00000000 + OUT + GPIO Output Register. Each bit controls the GPIO_OUT setting for one pin in the associated port. This register can be written either directly, or by using the GPIO_OUT_SET and GPIO_OUT_CLR registers. + 0x18 - RTS - HTimer Long Interval Counter. + GPIO_OUT + Mask of all of the pins on the port. 0 32 + + + low + Drive Logic 0 (low) on GPIO output. + 0 + + + high + Drive logic 1 (high) on GPIO output. + 1 + + - SSEC - HTimer Short Interval Counter. This counter ticks every t_htclk (16.48uS). HTIMER_SEC is incremented when this register rolls over from 0xFF to 0x00. - 0x04 - 0x00000000 + OUT_SET + GPIO Output Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT to 1, without affecting other bits in that register. + 0x1C + write-only - RTSS - HTimer Short Interval Counter. + GPIO_OUT_SET + Mask of all of the pins on the port. 0 - 8 + 32 + + + no + No Effect. + 0 + + + set + Set GPIO_OUT bit in this position to '1' + 1 + + - RAS - Long Interval Alarm. - 0x08 - 0x00000000 + OUT_CLR + GPIO Output Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT to 0, without affecting other bits in that register. + 0x20 + write-only - RAS - HTimer Long Interval Alarm. An Alarm is triggered when this value matches HTIMER_SEC[19:0] + GPIO_OUT_CLR + Mask of all of the pins on the port. 0 - 20 + 32 - RSSA - HTimer Short Interval Alarm. This register contains the reload value for the short interval alarm, HTIMER_CTRL.alarm_ss_fl is raised on rollover. - 0x0C - 0x00000000 + IN + GPIO Input Register. Read-only register to read from the logic states of the GPIO pins on this port. + 0x24 + read-only - RSSA - This register contains the reload value for the short interval alarm. + GPIO_IN + Mask of all of the pins on the port. 0 32 - CTRL - HTimer Control Register. - 0x10 - 0x00000008 - 0xFFFFFF38 + INT_MODE + GPIO Interrupt Mode Register. Each bit in this register controls the interrupt mode setting for the associated GPIO pin on this port. + 0x28 - HTEN - HTimer Enable. This bit enables the Real Time Clock. This bit can only be written when WE=1 and BUSY =0. Change to this bit is effective only after BUSY is cleared from 1 to 0. + GPIO_INT_MODE + Mask of all of the pins on the port. 0 - 1 + 32 - dis - Disable. + level + Interrupts for this pin are level triggered. 0 - en - Enable. + edge + Interrupts for this pin are edge triggered. 1 + + + + INT_POL + GPIO Interrupt Polarity Register. Each bit in this register controls the interrupt polarity setting for one GPIO pin in the associated port. + 0x2C + - ADE - Long Interval Alarm Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0. - 1 - 1 + GPIO_INT_POL + Mask of all of the pins on the port. + 0 + 32 - dis - Disable. + falling + Interrupts are latched on a falling edge or low level condition for this pin. 0 - en - Enable. + rising + Interrupts are latched on a rising edge or high condition for this pin. 1 + + + + IN_EN + GPIO Input Enable + 0x30 + + + INT_EN + GPIO Interrupt Enable Register. Each bit in this register controls the GPIO interrupt enable for the associated pin on the GPIO port. + 0x34 + - ASE - Short Interval Alarm Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0. - 2 - 1 + GPIO_INT_EN + Mask of all of the pins on the port. + 0 + 32 dis - Disable. + Interrupts are disabled for this GPIO pin. 0 en - Enable. - 1 - - - - - BUSY - HTimer Busy. This bit is set to 1 by hardware when changes to HTimer registers required a synchronized version of the register to be in place. This bit is automatically cleared by hardware. - 3 - 1 - read-only - - - idle - Idle. - 0 - - - busy - Busy. + Interrupts are enabled for this GPIO pin. 1 + + + + INT_EN_SET + GPIO Interrupt Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_INT_EN to 1, without affecting other bits in that register. + 0x38 + - RDY - HTimer Ready. This bit is set to 1 by hardware when the HTimer count registers update. It can be cleared to 0 by software at any time. It will also be cleared to 0 by hardware just prior to an update of the HTimer count register. - 4 - 1 + GPIO_INT_EN_SET + Mask of all of the pins on the port. + 0 + 32 - busy - Register has not updated. + no + No effect. 0 - ready - Ready. + set + Set GPIO_INT_EN bit in this position to '1' 1 + + + + INT_EN_CLR + GPIO Interrupt Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_EN to 0, without affecting other bits in that register. + 0x3C + - RDYE - HTimer Ready Interrupt Enable. - 5 - 1 + GPIO_INT_EN_CLR + Mask of all of the pins on the port. + 0 + 32 - dis - Disable. + no + No Effect. 0 - en - Enable. + clear + Clear GPIO_INT_EN bit in this position to '0' 1 + + + + INT_STAT + GPIO Interrupt Status Register. Each bit in this register contains the pending interrupt status for the associated GPIO pin in this port. + 0x40 + read-only + - ALDF - Long Interval Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor. - 6 - 1 - read-only + GPIO_INT_STAT + Mask of all of the pins on the port. + 0 + 32 - inactive - Not active. + no + No Interrupt is pending on this GPIO pin. 0 pending - Active. + An Interrupt is pending on this GPIO pin. 1 + + + + INT_CLR + GPIO Status Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_STAT to 0, without affecting other bits in that register. + 0x48 + - ALSF - Short Interval Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor. - 7 - 1 - read-only - - - inactive - Not active. - 0 - - - Pending - Active. - 1 - - + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + WAKE_EN + GPIO Wake Enable Register. Each bit in this register controls the PMU wakeup enable for the associated GPIO pin in this port. + 0x4C + - WE - Write Enable. This register bit serves as a protection mechanism against unintentional writes to critical HTimer bits. - 15 - 1 + GPIO_WAKE_EN + Mask of all of the pins on the port. + 0 + 32 dis - Not active. + PMU wakeup for this GPIO is disabled. 0 en - . + PMU wakeup for this GPIO is enabled. 1 - - - - - HTMR1 - High Speed Timer Module. 1 - 0x4001C000 - - HTMR1 - HTMR1 IRQ - 94 - - - - - I2C0 - Inter-Integrated Circuit. - I2C - 0x4001D000 - 32 - - 0x00 - 0x1000 - registers - - - I2C0 - I2C0 IRQ - 13 - - - CTRL - Control Register0. - 0x00 + WAKE_EN_SET + GPIO Wake Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_WAKE_EN to 1, without affecting other bits in that register. + 0x50 - I2C_EN - I2C Enable. - [0:0] - read-write + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + WAKE_EN_CLR + GPIO Wake Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_WAKE_EN to 0, without affecting other bits in that register. + 0x54 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + INT_DUAL_EDGE + GPIO Interrupt Dual Edge Mode Register. Each bit in this register selects dual edge mode for the associated GPIO pin in this port. + 0x5C + + + GPIO_INT_DUAL_EDGE + Mask of all of the pins on the port. + 0 + 32 - dis - Disable I2C. + no + No Effect. 0 en - Enable I2C. + Dual Edge mode is enabled. If edge-triggered interrupts are enabled on this GPIO pin, then both rising and falling edges will trigger interrupts regardless of the GPIO_INT_POL setting. 1 + + + + PAD_CFG1 + GPIO Input Mode Config 1. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port. + 0x60 + - MST - Master Mode Enable. - [1:1] - read-write + GPIO_PAD_CFG1 + The two bits in GPIO_PAD_CFG1 and GPIO_PAD_CFG2 for each GPIO pin work together to determine the pad mode when the GPIO is set to input mode. + 0 + 32 - slave_mode - Slave Mode. + impedance + High Impedance. 0 - master_mode - Master Mode. + pu + Weak pull-up mode. 1 - - - - GEN_CALL_ADDR - General Call Address Enable. - [2:2] - read-write - - - dis - Ignore Gneral Call Address. - 0 - - en - Acknowledge general call address. - 1 + pd + weak pull-down mode. + 2 + + + + PAD_CFG2 + GPIO Input Mode Config 2. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port. + 0x64 + - RX_MODE - Interactive Receive Mode. - [3:3] - read-write + GPIO_PAD_CFG2 + The two bits in GPIO_PAD_CFG1 and GPIO_PAD_CFG2 for each GPIO pin work together to determine the pad mode when the GPIO is set to input mode. + 0 + 32 - dis - Disable Interactive Receive Mode. + impedance + High Impedance. 0 - en - Enable Interactive Receive Mode. + pu + Weak pull-up mode. 1 + + pd + weak pull-down mode. + 2 + + + + + EN1 + GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port. + 0x68 + - RX_MODE_ACK - Data Acknowledge. This bit defines the acknowledge bit returned by the I2C receiver while IRXM = 1 HW forces ACK to 0 when IRXM = 0. - [4:4] - read-write + GPIO_EN1 + Mask of all of the pins on the port. + 0 + 32 - ack - return ACK (pulling SDA LOW). + primary + Primary function selected. 0 - nack - return NACK (leaving SDA HIGH). + secondary + Secondary function selected. 1 + + + + EN1_SET + GPIO Alternate Function Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN1 to 1, without affecting other bits in that register. + 0x6C + - SCL_OUT - SCL Output. This bits control SCL output when SWOE =1. - [6:6] - read-write + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + EN1_CLR + GPIO Alternate Function Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN1 to 0, without affecting other bits in that register. + 0x70 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + EN2 + GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port. + 0x74 + + + GPIO_EN2 + Mask of all of the pins on the port. + 0 + 32 - drive_scl_low - Drive SCL low. + primary + Primary function selected. 0 - release_scl - Release SCL. + secondary + Secondary function selected. 1 + + + + EN2_SET + GPIO Alternate Function 2 Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN2 to 1, without affecting other bits in that register. + 0x78 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + EN2_CLR + GPIO Wake Alternate Function Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN2 to 0, without affecting other bits in that register. + 0x7C + - SDA_OUT - SDA Output. This bits control SDA output when SWOE = 1. - [7:7] - read-write + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + DS + GPIO Drive Strength Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode. + 0xB0 + + + GPIO_DS + Mask of all of the pins on the port. + 0 + 32 - drive_sda_low - Drive SDA low. + ld + GPIO port pin is in low-drive mode. 0 - release_sda - Release SDA. + hd + GPIO port pin is in high-drive mode. 1 + + + + DS1 + GPIO Drive Strength 1 Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode. + 0xB4 + - SCL - SCL status. This bit reflects the logic gate of SCL signal. - [8:8] - read-only + GPIO_DS1 + Mask of all of the pins on the port. + 0 + 32 + + + + PS + GPIO Pull Select Mode. + 0xB8 + - SDA - SDA status. THis bit reflects the logic gate of SDA signal. - [9:9] - read-only + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + VSSEL + GPIO Voltage Select. + 0xC0 + - SW_OUT_EN - Software Output Enable. - [10:10] - read-write - - - outputs_disable - I2C Outputs SCLO and SDAO disabled. - 0 - - - outputs_enable - I2C Outputs SCLO and SDAO enabled. - 1 - - + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + + + + GPIO1 + Individual I/O for each GPIO 1 + 0x40009000 + + GPIO1 + GPIO1 IRQ + 25 + + + + + GPIO2 + Individual I/O for each GPIO 2 + 0x4000A000 + + GPIO2 + GPIO2 IRQ + 26 + + + + + GPIO3 + Individual I/O for each GPIO 3 + 0x4000B000 + + GPIO3 + GPIO3 IRQ + 58 + + + + + HTMR + High Speed Timer Module. + 0x4001B000 + + 0x00 + 0xFFF + registers + + + HTimer + HTimer interrupt. + 93 + + + + SEC + HTimer Long-Interval Counter. This register contains the 32 most significant bits of the counter. + 0x00 + 0x00000000 + + + RTS + HTimer Long Interval Counter. + 0 + 32 + + + + SSEC + HTimer Short Interval Counter. This counter ticks every t_htclk (16.48uS). HTIMER_SEC is incremented when this register rolls over from 0xFF to 0x00. + 0x04 + 0x00000000 + - READ - Read. This bit reflects the R/W bit of an address match (AMI = 1) or general call match (GCI = 1). This bit is valid 3 cycles after the relevant interrupt bit is set. - [11:11] - read-only + RTSS + HTimer Short Interval Counter. + 0 + 8 + + + + + RAS + Long Interval Alarm. + 0x08 + 0x00000000 + + + RAS + HTimer Long Interval Alarm. An Alarm is triggered when this value matches HTIMER_SEC[19:0] + 0 + 20 + + + + + RSSA + HTimer Short Interval Alarm. This register contains the reload value for the short interval alarm, HTIMER_CTRL.alarm_ss_fl is raised on rollover. + 0x0C + 0x00000000 + + + RSSA + This register contains the reload value for the short interval alarm. + 0 + 32 + + + + + CTRL + HTimer Control Register. + 0x10 + 0x00000008 + 0xFFFFFF38 + + + HTEN + HTimer Enable. This bit enables the Real Time Clock. This bit can only be written when WE=1 and BUSY =0. Change to this bit is effective only after BUSY is cleared from 1 to 0. + 0 + 1 - write - Write. + dis + Disable. 0 - read - Read. + en + Enable. 1 - SCL_CLK_STRETCH_DIS - This bit will disable slave clock stretching when set. - [12:12] - read-write + ADE + Long Interval Alarm Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0. + 1 + 1 - en - Slave clock stretching enabled. + dis + Disable. 0 - dis - Slave clock stretching disabled. + en + Enable. 1 - SCL_PP_MODE - SCL Push-Pull Mode. This bit controls whether SCL is operated in a the I2C standard open-drain mode, or in a non-standard push-pull mode where the Hi-Z output isreplaced with Drive-1. The non-standard mode should only be used when operating as a master and communicating with slaves that are guaranteed to never drive SCL low. - [13:13] - read-write + ASE + Short Interval Alarm Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0. + 2 + 1 dis - Standard open-drain operation: - drive low for 0, Hi-Z for 1 + Disable. 0 en - Non-standard push-pull operation: - drive low for 0, drive high for 1 + Enable. 1 - - - - STATUS - Status Register. - 0x04 - - BUS - Bus Status. - [0:0] + BUSY + HTimer Busy. This bit is set to 1 by hardware when changes to HTimer registers required a synchronized version of the register to be in place. This bit is automatically cleared by hardware. + 3 + 1 read-only idle - I2C Bus Idle. + Idle. 0 busy - I2C Bus Busy. + Busy. 1 - - RX_EMPTY - RX empty. - [1:1] - read-only + + RDY + HTimer Ready. This bit is set to 1 by hardware when the HTimer count registers update. It can be cleared to 0 by software at any time. It will also be cleared to 0 by hardware just prior to an update of the HTimer count register. + 4 + 1 - not_empty - Not Empty. + busy + Register has not updated. 0 - empty - Empty. + ready + Ready. 1 - RX_FULL - RX Full. - [2:2] - read-only + RDYE + HTimer Ready Interrupt Enable. + 5 + 1 - not_full - Not Full. + dis + Disable. 0 - full - Full. + en + Enable. 1 - TX_EMPTY - TX Empty. - [3:3] + ALDF + Long Interval Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor. + 6 + 1 + read-only - not_empty - Not Empty. + inactive + Not active. 0 - empty - Empty. + pending + Active. 1 - TX_FULL - TX Full. - [4:4] + ALSF + Short Interval Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor. + 7 + 1 + read-only - not_empty - Not Empty. + inactive + Not active. 0 - empty - Empty. + Pending + Active. 1 - CLK_MODE - Clock Mode. - [5:5] - read-only + WE + Write Enable. This register bit serves as a protection mechanism against unintentional writes to critical HTimer bits. + 15 + 1 - not_actively_driving_scl_clock - Device not actively driving SCL clock cycles. + dis + Not active. 0 - actively_driving_scl_clock - Device operating as master and actively driving SCL clock cycles. + en + . 1 + + + + + HTMR1 + High Speed Timer Module. 1 + 0x4001C000 + + HTMR1 + HTMR1 IRQ + 94 + + + + + I2C0 + Inter-Integrated Circuit. + I2C + 0x4001D000 + 32 + + 0x00 + 0x1000 + registers + + + I2C0 + I2C0 IRQ + 13 + + - INT_FL0 - Interrupt Status Register. - 0x08 + CTRL + Control Register0. + 0x00 - DONE - Transfer Done Interrupt. + I2C_EN + I2C Enable. [0:0] + read-write - inactive - No Interrupt is Pending. + dis + Disable I2C. 0 - pending - An interrupt is pending. + en + Enable I2C. 1 - RX_MODE - Interactive Receive Interrupt. + MST + Master Mode Enable. [1:1] + read-write - inactive - No Interrupt is Pending. + slave_mode + Slave Mode. 0 - pending - An interrupt is pending. + master_mode + Master Mode. 1 GEN_CALL_ADDR - Slave General Call Address Match Interrupt. + General Call Address Enable. [2:2] + read-write - inactive - No Interrupt is Pending. + dis + Ignore Gneral Call Address. 0 - pending - An interrupt is pending. + en + Acknowledge general call address. 1 - ADDR_MATCH - Slave Address Match Interrupt. + RX_MODE + Interactive Receive Mode. [3:3] + read-write - inactive - No Interrupt is Pending. + dis + Disable Interactive Receive Mode. 0 - pending - An interrupt is pending. + en + Enable Interactive Receive Mode. 1 - RX_THRESH - Receive Threshold Interrupt. This bit is automaticcaly cleared when RX_FIFO is below the threshold level. + RX_MODE_ACK + Data Acknowledge. This bit defines the acknowledge bit returned by the I2C receiver while IRXM = 1 HW forces ACK to 0 when IRXM = 0. [4:4] + read-write - inactive - No interrupt is pending. - 0 - - - pending - An interrupt is pending. RX_FIFO equal or more bytes than the threshold. - 1 - - - - - TX_THRESH - Transmit Threshold Interrupt. This bit is automaticcaly cleared when TX_FIFO is above the threshold level. - [5:5] - - - inactive - No interrupt is pending. + ack + return ACK (pulling SDA LOW). 0 - pending - An interrupt is pending. TX_FIFO has equal or less bytes than the threshold. + nack + return NACK (leaving SDA HIGH). 1 - STOP - STOP Interrupt. + SCL_OUT + SCL Output. This bits control SCL output when SWOE =1. [6:6] + read-write - inactive - No interrupt is pending. + drive_scl_low + Drive SCL low. 0 - pending - An interrupt is pending. TX_FIFO has equal or less bytes than the threshold. + release_scl + Release SCL. 1 - ADDR_ACK - Address Acknowledge Interrupt. + SDA_OUT + SDA Output. This bits control SDA output when SWOE = 1. [7:7] + read-write - inactive - No Interrupt is Pending. + drive_sda_low + Drive SDA low. 0 - pending - An interrupt is pending. + release_sda + Release SDA. 1 - ARB_ER - Arbritation error Interrupt. + SCL + SCL status. This bit reflects the logic gate of SCL signal. [8:8] + read-only + + + SDA + SDA status. THis bit reflects the logic gate of SDA signal. + [9:9] + read-only + + + SW_OUT_EN + Software Output Enable. + [10:10] + read-write - inactive - No Interrupt is Pending. + outputs_disable + I2C Outputs SCLO and SDAO disabled. 0 - pending - An interrupt is pending. + outputs_enable + I2C Outputs SCLO and SDAO enabled. 1 - TO_ER - timeout Error Interrupt. - [9:9] + READ + Read. This bit reflects the R/W bit of an address match (AMI = 1) or general call match (GCI = 1). This bit is valid 3 cycles after the relevant interrupt bit is set. + [11:11] + read-only - inactive - No Interrupt is Pending. + write + Write. 0 - pending - An interrupt is pending. + read + Read. 1 - ADDR_NACK_ER - Address NACK Error Interrupt. - [10:10] + SCL_CLK_STRETCH_DIS + This bit will disable slave clock stretching when set. + [12:12] + read-write - inactive - No Interrupt is Pending. + en + Slave clock stretching enabled. 0 - pending - An interrupt is pending. + dis + Slave clock stretching disabled. 1 - DATA_ER - Data NACK Error Interrupt. - [11:11] + SCL_PP_MODE + SCL Push-Pull Mode. This bit controls whether SCL is operated in a the I2C standard open-drain mode, or in a non-standard push-pull mode where the Hi-Z output isreplaced with Drive-1. The non-standard mode should only be used when operating as a master and communicating with slaves that are guaranteed to never drive SCL low. + [13:13] + read-write - inactive - No Interrupt is Pending. + dis + Standard open-drain operation: + drive low for 0, Hi-Z for 1 0 - pending - An interrupt is pending. + en + Non-standard push-pull operation: + drive low for 0, drive high for 1 1 + + + + STATUS + Status Register. + 0x04 + - DO_NOT_RESP_ER - Do Not Respond Error Interrupt. - [12:12] + BUS + Bus Status. + [0:0] + read-only - inactive - No Interrupt is Pending. + idle + I2C Bus Idle. 0 - pending - An interrupt is pending. + busy + I2C Bus Busy. 1 - START_ER - Start Error Interrupt. - [13:13] + RX_EMPTY + RX empty. + [1:1] + read-only - inactive - No Interrupt is Pending. + not_empty + Not Empty. 0 - pending - An interrupt is pending. + empty + Empty. 1 - STOP_ER - Stop Error Interrupt. - [14:14] + RX_FULL + RX Full. + [2:2] + read-only - inactive - No Interrupt is Pending. + not_full + Not Full. 0 - pending - An interrupt is pending. + full + Full. 1 - TX_LOCK_OUT - Transmit Lock Out Interrupt. - [15:15] + TX_EMPTY + TX Empty. + [3:3] - unlocked - TX FIFO not locked. + not_empty + Not Empty. 0 - locked - TX FIFO locked. + empty + Empty. 1 - RD_ADDR_MATCH - Slave Read Address Match Interrupt - [22:22] + TX_FULL + TX Full. + [4:4] - no_match - No address match. + not_empty + Not Empty. 0 - match - Address match. + empty + Empty. 1 - WR_ADDR_MATCH - Slave Write Address Match Interrupt - [23:23] + CLK_MODE + Clock Mode. + [5:5] + read-only - no_match - No address match. + not_actively_driving_scl_clock + Device not actively driving SCL clock cycles. 0 - match - Address match. + actively_driving_scl_clock + Device operating as master and actively driving SCL clock cycles. 1 @@ -10009,285 +8603,278 @@ - INT_EN0 - Interrupt Enable Register. - 0x0C - read-write + INT_FL0 + Interrupt Status Register. + 0x08 DONE - Transfer Done Interrupt Enable. + Transfer Done Interrupt. [0:0] - read-write - dis - Interrupt disabled. + inactive + No Interrupt is Pending. 0 - en - Interrupt enabled when DONE = 1. + pending + An interrupt is pending. 1 RX_MODE - Description not available. + Interactive Receive Interrupt. [1:1] - read-write - dis - Interrupt disabled. + inactive + No Interrupt is Pending. 0 - en - Interrupt enabled when RX_MODE = 1. + pending + An interrupt is pending. 1 GEN_CALL_ADDR - Slave mode general call address match received input enable. + Slave General Call Address Match Interrupt. [2:2] - read-write - dis - Interrupt disabled. + inactive + No Interrupt is Pending. 0 - en - Interrupt enabled when GEN_CTRL_ADDR = 1. + pending + An interrupt is pending. 1 ADDR_MATCH - Slave mode incoming address match interrupt. + Slave Address Match Interrupt. [3:3] - read-write - dis - Interrupt disabled. + inactive + No Interrupt is Pending. 0 - en - Interrupt enabled when ADDR_MATCH = 1. + pending + An interrupt is pending. 1 RX_THRESH - RX FIFO Above Treshold Level Interrupt Enable. + Receive Threshold Interrupt. This bit is automaticcaly cleared when RX_FIFO is below the threshold level. [4:4] - read-write - dis - Interrupt disabled. + inactive + No interrupt is pending. 0 - en - Interrupt enabled. + pending + An interrupt is pending. RX_FIFO equal or more bytes than the threshold. 1 TX_THRESH - TX FIFO Below Treshold Level Interrupt Enable. + Transmit Threshold Interrupt. This bit is automaticcaly cleared when TX_FIFO is above the threshold level. [5:5] - dis - Interrupt disabled. + inactive + No interrupt is pending. 0 - en - Interrupt enabled. + pending + An interrupt is pending. TX_FIFO has equal or less bytes than the threshold. 1 STOP - Stop Interrupt Enable + STOP Interrupt. [6:6] - read-write - dis - Interrupt disabled. + inactive + No interrupt is pending. 0 - en - Interrupt enabled when STOP = 1. + pending + An interrupt is pending. TX_FIFO has equal or less bytes than the threshold. 1 ADDR_ACK - Received Address ACK from Slave Interrupt. + Address Acknowledge Interrupt. [7:7] - dis - Interrupt disabled. + inactive + No Interrupt is Pending. 0 - en - Interrupt enabled. + pending + An interrupt is pending. 1 ARB_ER - Master Mode Arbitration Lost Interrupt. + Arbritation error Interrupt. [8:8] - dis - Interrupt disabled. + inactive + No Interrupt is Pending. 0 - en - Interrupt enabled. + pending + An interrupt is pending. 1 TO_ER - Timeout Error Interrupt Enable. + timeout Error Interrupt. [9:9] - dis - Interrupt disabled. + inactive + No Interrupt is Pending. 0 - en - Interrupt enabled. + pending + An interrupt is pending. 1 - ADDR_NACK_ERR - Master Mode Address NACK Received Interrupt. + ADDR_NACK_ER + Address NACK Error Interrupt. [10:10] - dis - Interrupt disabled. + inactive + No Interrupt is Pending. 0 - en - Interrupt enabled. + pending + An interrupt is pending. 1 DATA_ER - Master Mode Data NACK Received Interrupt. + Data NACK Error Interrupt. [11:11] - dis - Interrupt disabled. + inactive + No Interrupt is Pending. 0 - en - Interrupt enabled. + pending + An interrupt is pending. 1 DO_NOT_RESP_ER - Slave Mode Do Not Respond Interrupt. + Do Not Respond Error Interrupt. [12:12] - dis - Interrupt disabled. + inactive + No Interrupt is Pending. 0 - en - Interrupt enabled. + pending + An interrupt is pending. 1 START_ER - Out of Sequence START condition detected interrupt. + Start Error Interrupt. [13:13] - dis - Interrupt disabled. + inactive + No Interrupt is Pending. 0 - en - Interrupt enabled. + pending + An interrupt is pending. 1 STOP_ER - Out of Sequence STOP condition detected interrupt. + Stop Error Interrupt. [14:14] - dis - Interrupt disabled. + inactive + No Interrupt is Pending. 0 - en - Interrupt enabled. + pending + An interrupt is pending. 1 TX_LOCK_OUT - TX FIFO Locked Out Interrupt. + Transmit Lock Out Interrupt. [15:15] - dis - Interrupt disabled. + unlocked + TX FIFO not locked. 0 - en - Interrupt enabled. + locked + TX FIFO locked. 1 @@ -10298,13 +8885,13 @@ [22:22] - dis - Interrupt disabled. + no_match + No address match. 0 - en - Interrupt enabled. + match + Address match. 1 @@ -10315,13 +8902,13 @@ [23:23] - dis - Interrupt disabled. + no_match + No address match. 0 - en - Interrupt enabled. + match + Address match. 1 @@ -10329,388 +8916,377 @@ - INT_FL1 - Interrupt Status Register 1. - 0x10 + INT_EN0 + Interrupt Enable Register. + 0x0C + read-write - RX_OVERFLOW - Receiver Overflow Interrupt. When operating as a slave receiver, this bit is set when you reach the first data bit and the RX FIFO and shift register are both full. + DONE + Transfer Done Interrupt Enable. [0:0] + read-write - inactive - No Interrupt is Pending. + dis + Interrupt disabled. 0 - pending - An interrupt is pending. + en + Interrupt enabled when DONE = 1. 1 - TX_UNDERFLOW - Transmit Underflow Interrupt. When operating as a slave transmitter, this bit is set when you reach the first data bit and the TX FIFO is empty and the master is still asking for more data (i.e the master hasn't sent a NACK yet). + RX_MODE + Description not available. [1:1] + read-write - inactive - No Interrupt is Pending. + dis + Interrupt disabled. 0 - pending - An interrupt is pending. + en + Interrupt enabled when RX_MODE = 1. 1 - START - START Condition Status Flag. + GEN_CALL_ADDR + Slave mode general call address match received input enable. [2:2] + read-write - not_detected - START condition not detected. + dis + Interrupt disabled. 0 - detected - START condition detected. + en + Interrupt enabled when GEN_CTRL_ADDR = 1. 1 - - - - INT_EN1 - Interrupt Staus Register 1. - 0x14 - read-write - - RX_OVERFLOW - Receiver Overflow Interrupt Enable. - [0:0] + ADDR_MATCH + Slave mode incoming address match interrupt. + [3:3] + read-write dis - No Interrupt is Pending. + Interrupt disabled. 0 en - An interrupt is pending. + Interrupt enabled when ADDR_MATCH = 1. 1 - TX_UNDERFLOW - Transmit Underflow Interrupt Enable. - [1:1] + RX_THRESH + RX FIFO Above Treshold Level Interrupt Enable. + [4:4] + read-write dis - No Interrupt is Pending. + Interrupt disabled. 0 en - An interrupt is pending. + Interrupt enabled. 1 - START - START Condition Interrupt Enable. - [2:2] + TX_THRESH + TX FIFO Below Treshold Level Interrupt Enable. + [5:5] dis - Disable START condition interrupt. + Interrupt disabled. 0 en - Enable START condition interrupt. + Interrupt enabled. 1 - - - - FIFO_LEN - FIFO Configuration Register. - 0x18 - - - RX_LEN - Receive FIFO Length. - [7:0] - read-only - - - TX_LEN - Transmit FIFO Length. - [15:8] - read-only - - - - - RX_CTRL0 - Receive Control Register 0. - 0x1C - - DNR - Do Not Respond. - [0:0] + STOP + Stop Interrupt Enable + [6:6] + read-write - respond - Always respond to address match. + dis + Interrupt disabled. 0 - not_respond_rx_fifo_empty - Do not respond to address match when RX_FIFO is not empty. + en + Interrupt enabled when STOP = 1. 1 - RX_FLUSH - Receive FIFO Flush. This bit is automatically cleared to 0 after the operation. Setting this bit to 1 will affect RX_FIFO status. + ADDR_ACK + Received Address ACK from Slave Interrupt. [7:7] - not_flushed - FIFO not flushed. + dis + Interrupt disabled. 0 - flush - Flush RX_FIFO. + en + Interrupt enabled. 1 - RX_THRESH - Receive FIFO Threshold. These bits define the RX_FIFO interrupt threshold. - [11:8] - - - - - RX_CTRL1 - Receive Control Register 1. - 0x20 - - - RX_CNT - Receive Count Bits. These bits define the number of bytes to be received in a transaction, except for the case RXCNT = 0. RXCNT = 0 means 256 bytes to be received in a transaction. - [7:0] - - - RX_FIFO - Receive FIFO Count. These bits reflect the number of byte in the RX_FIFO. These bits are flushed when I2CEN = 0. - [11:8] - read-only - - - - - TX_CTRL0 - Transmit Control Register 0. - 0x24 - - - TX_PRELOAD - Transmit FIFO Preaload Mode. Setting this bit will allow for high speed application to preload the transmit FIFO prior to Slave Address Match. - [0:0] + ARB_ER + Master Mode Arbitration Lost Interrupt. + [8:8] + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled. + 1 + + - TX_READY_MODE - Transmit FIFO Ready Manual Mode. - [1:1] + TO_ER + Timeout Error Interrupt Enable. + [9:9] - en - HW control of I2CTXRDY enabled. + dis + Interrupt disabled. 0 - dis - HW control of I2CTXRDY disabled. + en + Interrupt enabled. 1 - TX_AMGC_AFD - TX FIFO General Call Address Match Auto Flush Disable. - [2:2] + ADDR_NACK_ERR + Master Mode Address NACK Received Interrupt. + [10:10] - en - Enabled. + dis + Interrupt disabled. 0 - dis - Disabled. + en + Interrupt enabled. 1 - TX_AMW_AFD - TX FIFO Slave Address Match Write Auto Flush Disable. - [3:3] + DATA_ER + Master Mode Data NACK Received Interrupt. + [11:11] - en - Enabled. + dis + Interrupt disabled. 0 - dis - Disabled. + en + Interrupt enabled. 1 - TX_AMR_AFD - TX FIFO Slave Address Match Read Auto Flush Disable. - [4:4] + DO_NOT_RESP_ER + Slave Mode Do Not Respond Interrupt. + [12:12] - en - Enabled. + dis + Interrupt disabled. 0 - dis - Disabled. + en + Interrupt enabled. 1 - TX_NACK_AFD - TX FIFO received NACK Auto Flush Disable. - [5:5] + START_ER + Out of Sequence START condition detected interrupt. + [13:13] - en - Enabled. + dis + Interrupt disabled. 0 - dis - Disabled. + en + Interrupt enabled. 1 - TX_FLUSH - Transmit FIFO Flush. This bit is automatically cleared to 0 after the operation. - [7:7] + STOP_ER + Out of Sequence STOP condition detected interrupt. + [14:14] - not_flushed - FIFO not flushed. + dis + Interrupt disabled. 0 - flush - Flush TX_FIFO. + en + Interrupt enabled. 1 - TX_THRESH - Transmit FIFO Threshold. These bits define the TX_FIFO interrupt threshold. - [11:8] - - - - - TX_CTRL1 - Transmit Control Register 1. - 0x28 - - - TX_READY - Transmit FIFO Preload Ready. - [0:0] + TX_LOCK_OUT + TX FIFO Locked Out Interrupt. + [15:15] + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled. + 1 + + - TX_FIFO - Transmit FIFO Count. These bits reflect the number of bytes in the TX_FIFO. - [11:8] - read-only + RD_ADDR_MATCH + Slave Read Address Match Interrupt + [22:22] + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled. + 1 + + - - - - FIFO - Data Register. - 0x2C - - DATA - Data is read from or written to this location. Transmit and receive FIFO are separate but both are addressed at this location. - 0 - 8 + WR_ADDR_MATCH + Slave Write Address Match Interrupt + [23:23] + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled. + 1 + + - MASTER_CTRL - Master Control Register. - 0x30 + INT_FL1 + Interrupt Status Register 1. + 0x10 - START - Setting this bit to 1 will start a master transfer. + RX_OVERFLOW + Receiver Overflow Interrupt. When operating as a slave receiver, this bit is set when you reach the first data bit and the RX FIFO and shift register are both full. [0:0] + + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + - RESTART - Setting this bit to 1 will generate a repeated START. + TX_UNDERFLOW + Transmit Underflow Interrupt. When operating as a slave transmitter, this bit is set when you reach the first data bit and the TX FIFO is empty and the master is still asking for more data (i.e the master hasn't sent a NACK yet). [1:1] + + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + - STOP - Setting this bit to 1 will generate a STOP condition. + START + START Condition Status Flag. [2:2] - - - SL_EX_ADDR - Slave Extend Address Select. - [7:7] - 7_bits_address - 7-bit address. + not_detected + START condition not detected. 0 - 10_bits_address - 10-bit address. + detected + START condition detected. 1 @@ -10718,528 +9294,585 @@ - CLK_LO - Clock Low Register. - 0x34 - - - SCL_LO - Clock low. In master mode, these bits define the SCL low period. In slave mode, these bits define the time SCL will be held low after data is outputted. - [8:0] - - - - - CLK_HI - Clock high Register. - 0x38 - - - SCL_HI - Clock High. In master mode, these bits define the SCL high period. - [8:0] - - - - - TIMEOUT - Timeout Register - 0x40 - - - TO - Timeout - [15:0] - - - - - DMA - DMA Register. - 0x48 + INT_EN1 + Interrupt Staus Register 1. + 0x14 + read-write - TX_EN - TX channel enable. + RX_OVERFLOW + Receiver Overflow Interrupt Enable. [0:0] dis - Disable. + No Interrupt is Pending. 0 en - Enable. + An interrupt is pending. 1 - RX_EN - RX channel enable. + TX_UNDERFLOW + Transmit Underflow Interrupt Enable. [1:1] dis - Disable. + No Interrupt is Pending. 0 en - Enable. + An interrupt is pending. 1 - - - - SLAVE_ADDR - Slave Address Register. - 0x4C - - - SLAVE_ADDR - Slave Address. - [9:0] - - EX_ADDR - Extended Address Select. - [15:15] + START + START Condition Interrupt Enable. + [2:2] - 7_bits_address - 7-bit address. + dis + Disable START condition interrupt. 0 - 10_bits_address - 10-bit address. + en + Enable START condition interrupt. 1 - - - - - I2C1 - Inter-Integrated Circuit. 1 - 0x4001E000 - - I2C1 - I2C1 IRQ - 36 - - - - - I2C2 - Inter-Integrated Circuit. 2 - 0x4001F000 - - I2C2 - I2C2 IRQ - 62 - - - - - ICC0 - Instruction Cache Controller Registers - 0x4002A000 - - 0x00 - 0x1000 - registers - - - - CACHE_ID - Cache ID Register. - 0x0000 - read-only - - - RELNUM - Release Number. Identifies the RTL release version. - 0 - 6 - - - PARTNUM - Part Number. This field reflects the value of C_ID_PART_NUMBER configuration parameter. - 6 - 4 - - - CCHID - Cache ID. This field reflects the value of the C_ID_CACHEID configuration parameter. - 10 - 6 - - - - MEMCFG - Memory Configuration Register. - 0x0004 - read-only - 0x00080008 + FIFO_LEN + FIFO Configuration Register. + 0x18 - CCHSZ - Cache Size. Indicates total size in Kbytes of cache. - 0 - 16 + RX_LEN + Receive FIFO Length. + [7:0] + read-only - MEMSZ - Main Memory Size. Indicates the total size, in units of 128 Kbytes, of code memory accessible to the cache controller. - 16 - 16 + TX_LEN + Transmit FIFO Length. + [15:8] + read-only - CACHE_CTRL - Cache Control and Status Register. - 0x0100 + RX_CTRL0 + Receive Control Register 0. + 0x1C - EN - Cache Enable. Controls whether the cache is bypassed or is in use. Changing the state of this bit will cause the instruction cache to be flushed and its contents invalidated. - 0 - 1 + DNR + Do Not Respond. + [0:0] - dis - Cache Bypassed. Instruction data is stored in the line fill buffer but is not written to main cache memory array. + respond + Always respond to address match. 0 - en - Cache Enabled. + not_respond_rx_fifo_empty + Do not respond to address match when RX_FIFO is not empty. 1 - RDY - Cache Ready flag. Cleared by hardware when at any time the cache as a whole is invalidated (including a system reset). When this bit is 0, the cache is effectively in bypass mode (instruction fetches will come from main memory or from the line fill buffer). Set by hardware when the invalidate operation is complete and the cache is ready. - 16 - 1 - read-only + RX_FLUSH + Receive FIFO Flush. This bit is automatically cleared to 0 after the operation. Setting this bit to 1 will affect RX_FIFO status. + [7:7] - invalid - Not Ready. + not_flushed + FIFO not flushed. 0 - ready - Ready. + flush + Flush RX_FIFO. 1 + + RX_THRESH + Receive FIFO Threshold. These bits define the RX_FIFO interrupt threshold. + [11:8] + - INVALIDATE - Invalidate All Registers. - 0x0700 - read-write + RX_CTRL1 + Receive Control Register 1. + 0x20 - INVALID - Invalidate. - 0 - 32 + RX_CNT + Receive Count Bits. These bits define the number of bytes to be received in a transaction, except for the case RXCNT = 0. RXCNT = 0 means 256 bytes to be received in a transaction. + [7:0] + + + RX_FIFO + Receive FIFO Count. These bits reflect the number of byte in the RX_FIFO. These bits are flushed when I2CEN = 0. + [11:8] + read-only - - - - - MCR - Misc Control. - 0x40006C00 - - 0x00 - 0x400 - registers - - - ECCEN - ECC Enable Register - 0x00 + TX_CTRL0 + Transmit Control Register 0. + 0x24 - SYSRAM0ECCEN - ECC System RAM Enable. - 0 - 1 + TX_PRELOAD + Transmit FIFO Preaload Mode. Setting this bit will allow for high speed application to preload the transmit FIFO prior to Slave Address Match. + [0:0] + + + TX_READY_MODE + Transmit FIFO Ready Manual Mode. + [1:1] + + en + HW control of I2CTXRDY enabled. + 0 + dis - disabled. + HW control of I2CTXRDY disabled. + 1 + + + + + TX_AMGC_AFD + TX FIFO General Call Address Match Auto Flush Disable. + [2:2] + + + en + Enabled. 0 + + dis + Disabled. + 1 + + + + + TX_AMW_AFD + TX FIFO Slave Address Match Write Auto Flush Disable. + [3:3] + en - enabled. + Enabled. + 0 + + + dis + Disabled. 1 - SYSRAM1ECCEN - ECC System RAM Enable. - 1 - 1 + TX_AMR_AFD + TX FIFO Slave Address Match Read Auto Flush Disable. + [4:4] - dis - disabled. + en + Enabled. 0 - en - enabled. + dis + Disabled. 1 - SYSRAM2ECCEN - ECC System RAM Enable. - 2 - 1 + TX_NACK_AFD + TX FIFO received NACK Auto Flush Disable. + [5:5] - dis - disabled. + en + Enabled. 0 - en - enabled. + dis + Disabled. 1 - SYSRAM3ECCEN - ECC System RAM Enable. - 3 - 1 + TX_FLUSH + Transmit FIFO Flush. This bit is automatically cleared to 0 after the operation. + [7:7] - dis - disabled. + not_flushed + FIFO not flushed. 0 - en - enabled. + flush + Flush TX_FIFO. 1 - SYSRAM4ECCEN - ECC System RAM Enable. - 4 - 1 + TX_THRESH + Transmit FIFO Threshold. These bits define the TX_FIFO interrupt threshold. + [11:8] + + + + + TX_CTRL1 + Transmit Control Register 1. + 0x28 + + + TX_READY + Transmit FIFO Preload Ready. + [0:0] + + + TX_FIFO + Transmit FIFO Count. These bits reflect the number of bytes in the TX_FIFO. + [11:8] + read-only + + + + + FIFO + Data Register. + 0x2C + + + DATA + Data is read from or written to this location. Transmit and receive FIFO are separate but both are addressed at this location. + 0 + 8 + + + + + MASTER_CTRL + Master Control Register. + 0x30 + + + START + Setting this bit to 1 will start a master transfer. + [0:0] + + + RESTART + Setting this bit to 1 will generate a repeated START. + [1:1] + + + STOP + Setting this bit to 1 will generate a STOP condition. + [2:2] + + + SL_EX_ADDR + Slave Extend Address Select. + [7:7] - dis - disabled. + 7_bits_address + 7-bit address. 0 - en - enabled. + 10_bits_address + 10-bit address. 1 + + + + CLK_LO + Clock Low Register. + 0x34 + - SYSRAM5ECCEN - ECC System RAM Enable. - 5 - 1 + SCL_LO + Clock low. In master mode, these bits define the SCL low period. In slave mode, these bits define the time SCL will be held low after data is outputted. + [8:0] + + + + + CLK_HI + Clock high Register. + 0x38 + + + SCL_HI + Clock High. In master mode, these bits define the SCL high period. + [8:0] + + + + + TIMEOUT + Timeout Register + 0x40 + + + TO + Timeout + [15:0] + + + + + DMA + DMA Register. + 0x48 + + + TX_EN + TX channel enable. + [0:0] dis - disabled. + Disable. 0 en - enabled. + Enable. 1 - IC0ECCEN - Icache0 ECC Enable. - 8 - 1 + RX_EN + RX channel enable. + [1:1] dis - disabled. + Disable. 0 en - enabled. + Enable. 1 + + + + SLAVE_ADDR + Slave Address Register. + 0x4C + - ICXIPECCEN - IcacheXIP ECC Enable. - 10 - 1 + SLAVE_ADDR + Slave Address. + [9:0] + + + EX_ADDR + Extended Address Select. + [15:15] - dis - disabled. + 7_bits_address + 7-bit address. 0 - en - enabled. + 10_bits_address + 10-bit address. 1 + + + + + + + I2C1 + Inter-Integrated Circuit. 1 + 0x4001E000 + + I2C1 + I2C1 IRQ + 36 + + + + + I2C2 + Inter-Integrated Circuit. 2 + 0x4001F000 + + I2C2 + I2C2 IRQ + 62 + + + + + ICC0 + Instruction Cache Controller Registers + 0x4002A000 + + 0x00 + 0x1000 + registers + + + + CACHE_ID + Cache ID Register. + 0x0000 + read-only + + + RELNUM + Release Number. Identifies the RTL release version. + 0 + 6 + - FL0ECCEN - Flash0 ECC Enable. - 11 - 1 - - - dis - disabled. - 0 - - - en - enabled. - 1 - - + PARTNUM + Part Number. This field reflects the value of C_ID_PART_NUMBER configuration parameter. + 6 + 4 - FL1ECCEN - Flash1 ECC Enable. - 12 - 1 - - - dis - disabled. - 0 - - - en - enabled. - 1 - - + CCHID + Cache ID. This field reflects the value of the C_ID_CACHEID configuration parameter. + 10 + 6 - PDOWN - PDOWN Drive Strength - 0x08 + MEMCFG + Memory Configuration Register. + 0x0004 + read-only + 0x00080008 - PDOWNDS - PDOWN Drive Strength + CCHSZ + Cache Size. Indicates total size in Kbytes of cache. 0 - 2 + 16 - PDOWNVS - PDOWN Voltage Select - 2 - 1 + MEMSZ + Main Memory Size. Indicates the total size, in units of 128 Kbytes, of code memory accessible to the cache controller. + 16 + 16 - CTRL - Misc Power State Control Register - 0x10 + CACHE_CTRL + Cache Control and Status Register. + 0x0100 - VDDCSW - Controls switching of VCORE - 1 - 2 - - - USBSWEN_N - USB Switch Control - 3 + EN + Cache Enable. Controls whether the cache is bypassed or is in use. Changing the state of this bit will cause the instruction cache to be flushed and its contents invalidated. + 0 1 - off - USB SW off in LP modes - 1 + dis + Cache Bypassed. Instruction data is stored in the line fill buffer but is not written to main cache memory array. + 0 - on - USB SW On - 0 + en + Cache Enabled. + 1 - P1M - Enable the Reset Pad Pull Up Resistors - 9 + RDY + Cache Ready flag. Cleared by hardware when at any time the cache as a whole is invalidated (including a system reset). When this bit is 0, the cache is effectively in bypass mode (instruction fetches will come from main memory or from the line fill buffer). Set by hardware when the invalidate operation is complete and the cache is ready. + 16 1 + read-only - 1m - 1MOhm Pullup + invalid + Not Ready. 0 - 25k - 25kOhm Pullup. + ready + Ready. 1 + + + + INVALIDATE + Invalidate All Registers. + 0x0700 + read-write + - rstn_voltage_sel - Error! Description not Found! - 10 - 1 + INVALID + Invalidate. + 0 + 32 - + OWM 1-Wire Master Interface. @@ -11365,7 +9998,7 @@ presence_detect Presence Pulse Detected. - [5:5] + [7:7] read-only @@ -11423,503 +10056,495 @@ - INTEN - 1-Wire Master Interrupt Enables. - 0x0014 + INTEN + 1-Wire Master Interrupt Enables. + 0x0014 + read-write + + + ow_reset_done + OW Reset Sequence Completed. + [0:0] + read-write + oneToClear + + + tx_data_empty + Tx Data Empty Interrupt Enable. + [1:1] + read-write + oneToClear + + + rx_data_ready + Rx Data Ready Interrupt Enable. + [2:2] + read-write + oneToClear + + + line_short + OW Line Short Detected Interrupt Enable. + [3:3] + read-write + oneToClear + + + line_low + OW Line Low Detected Interrupt Enable. + [4:4] + read-write + oneToClear + + + + + + + + PTG + Pulse Train Generation + Pulse_Train + 0x4003C000 + 32 + read-write + + 0 + 0x0020 + registers + + + PT + Pulse Train IRQ + 59 + + + + ENABLE + Global Enable/Disable Controls for All Pulse Trains + 0x0000 + read-write + + + pt0 + Enable/Disable control for PT0 + 0 + 1 + read-write + + + pt1 + Enable/Disable control for PT1 + 1 + 1 + read-write + + + pt2 + Enable/Disable control for PT2 + 2 + 1 + read-write + + + pt3 + Enable/Disable control for PT3 + 3 + 1 + read-write + + + pt4 + Enable/Disable control for PT4 + 4 + 1 + read-write + + + pt5 + Enable/Disable control for PT5 + 5 + 1 + read-write + + + pt6 + Enable/Disable control for PT6 + 6 + 1 + read-write + + + pt7 + Enable/Disable control for PT7 + 7 + 1 + read-write + + + + + RESYNC + Global Resync (All Pulse Trains) Control + 0x0004 read-write - ow_reset_done - OW Reset Sequence Completed. - [0:0] + pt0 + Resync control for PT0 + 0 + 1 read-write - oneToClear - tx_data_empty - Tx Data Empty Interrupt Enable. - [1:1] + pt1 + Resync control for PT1 + 1 + 1 read-write - oneToClear - rx_data_ready - Rx Data Ready Interrupt Enable. - [2:2] + pt2 + Resync control for PT2 + 2 + 1 read-write - oneToClear - line_short - OW Line Short Detected Interrupt Enable. - [3:3] + pt3 + Resync control for PT3 + 3 + 1 read-write - oneToClear - line_low - OW Line Low Detected Interrupt Enable. - [4:4] + pt4 + Resync control for PT4 + 4 + 1 read-write - oneToClear - - - - - - - PT - Pulse Train - Pulse_Train - 0x4003C020 - 32 - read-write - - 0 - 0x0010 - registers - - - - RATE_LENGTH - Pulse Train Configuration - 0x0000 - read-write - - rate_control - Pulse Train Enable and Rate Control. Set to 0 to disable the Pulse Train. - 0 - 27 + pt5 + Resync control for PT5 + 5 + 1 read-write - mode - Pulse Train Output Mode/Train Length - 27 - 5 + pt6 + Resync control for PT6 + 6 + 1 + read-write + + + pt7 + Resync control for PT7 + 7 + 1 read-write - - - 32_BIT - Pulse train, 32 bit pattern. - 0 - - - SQUARE_WAVE - Square wave mode. - 1 - - - 2_BIT - Pulse train, 2 bit pattern. - 2 - - - 3_BIT - Pulse train, 3 bit pattern. - 3 - - - 4_BIT - Pulse train, 4 bit pattern. - 4 - - - 5_BIT - Pulse train, 5 bit pattern. - 5 - - - 6_BIT - Pulse train, 6 bit pattern. - 6 - - - 7_BIT - Pulse train, 7 bit pattern. - 7 - - - 8_BIT - Pulse train, 8 bit pattern. - 8 - - - 9_BIT - Pulse train, 9 bit pattern. - 9 - - - 10_BIT - Pulse train, 10 bit pattern. - 10 - - - 11_BIT - Pulse train, 11 bit pattern. - 11 - - - 12_BIT - Pulse train, 12 bit pattern. - 12 - - - 13_BIT - Pulse train, 13 bit pattern. - 13 - - - 14_BIT - Pulse train, 14 bit pattern. - 14 - - - 15_BIT - Pulse train, 15 bit pattern. - 15 - - - 16_BIT - Pulse train, 16 bit pattern. - 16 - - - 17_BIT - Pulse train, 17 bit pattern. - 17 - - - 18_BIT - Pulse train, 18 bit pattern. - 18 - - - 19_BIT - Pulse train, 19 bit pattern. - 19 - - - 20_BIT - Pulse train, 20 bit pattern. - 20 - - - 21_BIT - Pulse train, 21 bit pattern. - 21 - - - 22_BIT - Pulse train, 22 bit pattern. - 22 - - - 23_BIT - Pulse train, 23 bit pattern. - 23 - - - 24_BIT - Pulse train, 24 bit pattern. - 24 - - - 25_BIT - Pulse train, 25 bit pattern. - 25 - - - 26_BIT - Pulse train, 26 bit pattern. - 26 - - - 27_BIT - Pulse train, 27 bit pattern. - 27 - - - 28_BIT - Pulse train, 28 bit pattern. - 28 - - - 29_BIT - Pulse train, 29 bit pattern. - 29 - - - 30_BIT - Pulse train, 30 bit pattern. - 30 - - - 31_BIT - Pulse train, 31 bit pattern. - 31 - - - TRAIN - Write the repeating bit pattern that is shifted out, LSB first, when configured in Pulse Train mode. See PT_RATE_LENGTH.mode for setting the length. - 0x0004 - read-write - - - LOOP - Pulse Train Loop Count + INTFL + Pulse Train Interrupt Flags 0x0008 read-write - count - Number of loops for this pulse train to repeat. + pt0 + Pulse Train 0 Stopped Interrupt Flag 0 - 16 + 1 read-write - delay - Delay between loops of the Pulse Train in PT Peripheral Clock cycles - 16 - 12 + pt1 + Pulse Train 1 Stopped Interrupt Flag + 1 + 1 + read-write + + + pt2 + Pulse Train 2 Stopped Interrupt Flag + 2 + 1 + read-write + + + pt3 + Pulse Train 3 Stopped Interrupt Flag + 3 + 1 + read-write + + + pt4 + Pulse Train 4 Stopped Interrupt Flag + 4 + 1 + read-write + + + pt5 + Pulse Train 5 Stopped Interrupt Flag + 5 + 1 + read-write + + + pt6 + Pulse Train 6 Stopped Interrupt Flag + 6 + 1 + read-write + + + pt7 + Pulse Train 7 Stopped Interrupt Flag + 7 + 1 read-write - RESTART - Pulse Train Auto-Restart Configuration. + INTEN + Pulse Train Interrupt Enable/Disable 0x000C read-write - pt_x_select - Auto-Restart PT X Select + pt0 + Pulse Train 0 Stopped Interrupt Enable/Disable 0 - 5 + 1 read-write - on_pt_x_loop_exit - Enable Auto-Restart on PT X Loop Exit - 7 + pt1 + Pulse Train 1 Stopped Interrupt Enable/Disable + 1 1 read-write - pt_y_select - Auto-Restart PT Y Select - 8 - 5 + pt2 + Pulse Train 2 Stopped Interrupt Enable/Disable + 2 + 1 read-write - on_pt_y_loop_exit - Enable Auto-Restart on PT Y Loop Exit - 15 + pt3 + Pulse Train 3 Stopped Interrupt Enable/Disable + 3 + 1 + read-write + + + pt4 + Pulse Train 4 Stopped Interrupt Enable/Disable + 4 + 1 + read-write + + + pt5 + Pulse Train 5 Stopped Interrupt Enable/Disable + 5 + 1 + read-write + + + pt6 + Pulse Train 6 Stopped Interrupt Enable/Disable + 6 + 1 + read-write + + + pt7 + Pulse Train 7 Stopped Interrupt Enable/Disable + 7 1 read-write - - - - - PT1 - Pulse Train 1 - 0x4003C040 - - - - PT2 - Pulse Train 2 - 0x4003C060 - - - - PT3 - Pulse Train 3 - 0x4003C080 - - - - PT4 - Pulse Train 4 - 0x4003C0A0 - - - - PT5 - Pulse Train 5 - 0x4003C0C0 - - - - PT6 - Pulse Train 6 - 0x4003C0E0 - - - - PT7 - Pulse Train 7 - 0x4003C100 - - - - PT8 - Pulse Train 8 - - - - - PTG - Pulse Train Generation - Pulse_Train - 0x4003C000 - 32 - read-write - - 0 - 0x0018 - registers - - - PT - Pulse Train IRQ - 59 - - - ENABLE - Global Enable/Disable Controls for All Pulse Trains - 0x0000 - read-write + SAFE_EN + Pulse Train Global Safe Enable. + 0x0010 + write-only + + + PT0 + 0 + 1 + write-only + + + PT1 + 1 + 1 + write-only + + + PT2 + 2 + 1 + write-only + + + PT3 + 3 + 1 + write-only + + + PT4 + 4 + 1 + write-only + + + PT5 + 5 + 1 + write-only + + + PT6 + 6 + 1 + write-only + + + PT7 + 7 + 1 + write-only + + + + + SAFE_DIS + Pulse Train Global Safe Disable. + 0x0014 + write-only - pt0 - Enable/Disable control for PT0 + PT0 0 1 - read-write + write-only - pt1 - Enable/Disable control for PT1 + PT1 1 1 - read-write + write-only - pt2 - Enable/Disable control for PT2 + PT2 2 1 - read-write + write-only - pt3 - Enable/Disable control for PT3 + PT3 3 1 - read-write + write-only - pt4 - Enable/Disable control for PT4 + PT4 4 1 - read-write + write-only - pt5 - Enable/Disable control for PT5 + PT5 5 1 - read-write + write-only - pt6 - Enable/Disable control for PT6 + PT6 6 1 - read-write + write-only - pt7 - Enable/Disable control for PT7 + PT7 7 1 - read-write + write-only - RESYNC - Global Resync (All Pulse Trains) Control - 0x0004 + READY_INTFL + Pulse Train Ready Interrupt Flags + 0x0018 read-write pt0 - Resync control for PT0 + Pulse Train 0 Stopped Interrupt Flag 0 1 read-write pt1 - Resync control for PT1 + Pulse Train 1 Stopped Interrupt Flag 1 1 read-write pt2 - Resync control for PT2 + Pulse Train 2 Stopped Interrupt Flag 2 1 read-write pt3 - Resync control for PT3 + Pulse Train 3 Stopped Interrupt Flag 3 1 read-write pt4 - Resync control for PT4 + Pulse Train 4 Stopped Interrupt Flag 4 1 read-write pt5 - Resync control for PT5 + Pulse Train 5 Stopped Interrupt Flag 5 1 read-write pt6 - Resync control for PT6 + Pulse Train 6 Stopped Interrupt Flag 6 1 read-write pt7 - Resync control for PT7 + Pulse Train 7 Stopped Interrupt Flag 7 1 read-write @@ -11927,248 +10552,384 @@ - INTFL - Pulse Train Interrupt Flags - 0x0008 + READY_INTEN + Pulse Train Ready Interrupt Enable/Disable + 0x001C read-write pt0 - Pulse Train 0 Stopped Interrupt Flag + Pulse Train 0 Stopped Interrupt Enable/Disable 0 1 read-write pt1 - Pulse Train 1 Stopped Interrupt Flag + Pulse Train 1 Stopped Interrupt Enable/Disable 1 1 read-write pt2 - Pulse Train 2 Stopped Interrupt Flag + Pulse Train 2 Stopped Interrupt Enable/Disable 2 1 read-write pt3 - Pulse Train 3 Stopped Interrupt Flag + Pulse Train 3 Stopped Interrupt Enable/Disable 3 1 read-write pt4 - Pulse Train 4 Stopped Interrupt Flag + Pulse Train 4 Stopped Interrupt Enable/Disable 4 1 read-write pt5 - Pulse Train 5 Stopped Interrupt Flag + Pulse Train 5 Stopped Interrupt Enable/Disable 5 1 read-write pt6 - Pulse Train 6 Stopped Interrupt Flag + Pulse Train 6 Stopped Interrupt Enable/Disable 6 1 read-write pt7 - Pulse Train 7 Stopped Interrupt Flag + Pulse Train 7 Stopped Interrupt Enable/Disable 7 1 read-write + + + + + PT + Pulse Train + Pulse_Train + 0x4003C020 + 32 + read-write + + 0 + 0x0010 + registers + + + + RATE_LENGTH + Pulse Train Configuration + 0x0000 + read-write + + + rate_control + Pulse Train Enable and Rate Control. Set to 0 to disable the Pulse Train. + 0 + 27 + read-write + + + mode + Pulse Train Output Mode/Train Length + 27 + 5 + read-write + + + 32_BIT + Pulse train, 32 bit pattern. + 0 + + + SQUARE_WAVE + Square wave mode. + 1 + + + 2_BIT + Pulse train, 2 bit pattern. + 2 + + + 3_BIT + Pulse train, 3 bit pattern. + 3 + + + 4_BIT + Pulse train, 4 bit pattern. + 4 + + + 5_BIT + Pulse train, 5 bit pattern. + 5 + + + 6_BIT + Pulse train, 6 bit pattern. + 6 + + + 7_BIT + Pulse train, 7 bit pattern. + 7 + + + 8_BIT + Pulse train, 8 bit pattern. + 8 + + + 9_BIT + Pulse train, 9 bit pattern. + 9 + + + 10_BIT + Pulse train, 10 bit pattern. + 10 + + + 11_BIT + Pulse train, 11 bit pattern. + 11 + + + 12_BIT + Pulse train, 12 bit pattern. + 12 + + + 13_BIT + Pulse train, 13 bit pattern. + 13 + + + 14_BIT + Pulse train, 14 bit pattern. + 14 + + + 15_BIT + Pulse train, 15 bit pattern. + 15 + + + 16_BIT + Pulse train, 16 bit pattern. + 16 + + + 17_BIT + Pulse train, 17 bit pattern. + 17 + + + 18_BIT + Pulse train, 18 bit pattern. + 18 + + + 19_BIT + Pulse train, 19 bit pattern. + 19 + + + 20_BIT + Pulse train, 20 bit pattern. + 20 + + + 21_BIT + Pulse train, 21 bit pattern. + 21 + + + 22_BIT + Pulse train, 22 bit pattern. + 22 + + + 23_BIT + Pulse train, 23 bit pattern. + 23 + + + 24_BIT + Pulse train, 24 bit pattern. + 24 + + + 25_BIT + Pulse train, 25 bit pattern. + 25 + + + 26_BIT + Pulse train, 26 bit pattern. + 26 + + + 27_BIT + Pulse train, 27 bit pattern. + 27 + + + 28_BIT + Pulse train, 28 bit pattern. + 28 + + + 29_BIT + Pulse train, 29 bit pattern. + 29 + + + 30_BIT + Pulse train, 30 bit pattern. + 30 + + + 31_BIT + Pulse train, 31 bit pattern. + 31 + + + + + - INTEN - Pulse Train Interrupt Enable/Disable - 0x000C + TRAIN + Write the repeating bit pattern that is shifted out, LSB first, when configured in Pulse Train mode. See PT_RATE_LENGTH.mode for setting the length. + 0x0004 + read-write + + + LOOP + Pulse Train Loop Count + 0x0008 read-write - pt0 - Pulse Train 0 Stopped Interrupt Enable/Disable + count + Number of loops for this pulse train to repeat. 0 - 1 - read-write - - - pt1 - Pulse Train 1 Stopped Interrupt Enable/Disable - 1 - 1 - read-write - - - pt2 - Pulse Train 2 Stopped Interrupt Enable/Disable - 2 - 1 - read-write - - - pt3 - Pulse Train 3 Stopped Interrupt Enable/Disable - 3 - 1 - read-write - - - pt4 - Pulse Train 4 Stopped Interrupt Enable/Disable - 4 - 1 - read-write - - - pt5 - Pulse Train 5 Stopped Interrupt Enable/Disable - 5 - 1 - read-write - - - pt6 - Pulse Train 6 Stopped Interrupt Enable/Disable - 6 - 1 + 16 read-write - pt7 - Pulse Train 7 Stopped Interrupt Enable/Disable - 7 - 1 + delay + Delay between loops of the Pulse Train in PT Peripheral Clock cycles + 16 + 12 read-write - SAFE_EN - Pulse Train Global Safe Enable. - 0x0010 - write-only + RESTART + Pulse Train Auto-Restart Configuration. + 0x000C + read-write - PT0 + pt_x_select + Auto-Restart PT X Select 0 - 1 - write-only - - - PT1 - 1 - 1 - write-only - - - PT2 - 2 - 1 - write-only - - - PT3 - 3 - 1 - write-only - - - PT4 - 4 - 1 - write-only - - - PT5 - 5 - 1 - write-only - - - PT6 - 6 - 1 - write-only + 5 + read-write - PT7 + on_pt_x_loop_exit + Enable Auto-Restart on PT X Loop Exit 7 1 - write-only - - - - - SAFE_DIS - Pulse Train Global Safe Disable. - 0x0014 - write-only - - - PT0 - 0 - 1 - write-only - - - PT1 - 1 - 1 - write-only - - - PT2 - 2 - 1 - write-only - - - PT3 - 3 - 1 - write-only - - - PT4 - 4 - 1 - write-only - - - PT5 - 5 - 1 - write-only + read-write - PT6 - 6 - 1 - write-only + pt_y_select + Auto-Restart PT Y Select + 8 + 5 + read-write - PT7 - 7 + on_pt_y_loop_exit + Enable Auto-Restart on PT Y Loop Exit + 15 1 - write-only + read-write - + + + PT1 + Pulse Train 1 + 0x4003C040 + + + + PT2 + Pulse Train 2 + 0x4003C060 + + + + PT3 + Pulse Train 3 + 0x4003C080 + + + + PT4 + Pulse Train 4 + 0x4003C0A0 + + + + PT5 + Pulse Train 5 + 0x4003C0C0 + + + + PT6 + Pulse Train 6 + 0x4003C0E0 + + + + PT7 + Pulse Train 7 + 0x4003C100 + + + + PT8 + Pulse Train 8 + + + PWRSEQ Power Sequencer / Low Power Control Register. @@ -13126,443 +11887,352 @@ - SCN - Smart Card Interface. - SCN - 0x4002C000 + SIR + System Initialization Registers. + 0x40000400 + read-only 0x00 - 0x1000 + 0x400 registers - - SC0 - SC0 IRQ - 11 - - CR - Control Register. + SISTAT + System Initialization Status Register. 0x00 + read-only - CONV - Convention Select Bit. + MAGIC + Magic Word Validation. This bit is set by the system initialization block following power-up. 0 1 + read-only + + read + + magicNotSet + Magic word was not set (OTP has not been initialized properly). + 0 + + + magicSet + Magic word was set (OTP contains valid settings). + 1 + + - CREP - Character Repeat Enable Bit. + CRCERR + CRC Error Status. This bit is set by the system initialization block following power-up. 1 1 - - - WTEN - Wait Time Counter Enable Bit. - 2 - 1 - - - UART - Smart Card Mode Bit. - 3 - 1 - - - CCEN - Clock Counter Enable Bit. - 4 - 1 - - - RXFLUSH - Receive FIFO Flush. - 5 - 1 - - - TXFLUSH - Transmit FIFO Flush. - 6 - 1 - - - RXTHD - Receive FIFO Depth. - 8 - 4 - - - TXTHD - Transmit FIFO Depth. - 12 - 4 + read-only + + read + + noError + No CRC errors occurred during the read of the OTP memory block. + 0 + + + error + A CRC error occurred while reading the OTP. The address of the failure location in the OTP memory is stored in the ERRADDR register. + 1 + + - SR - Status Register. + ERRADDR + Read-only field set by the SIB block if a CRC error occurs during the read of the OTP memory. Contains the failing address in OTP memory (when CRCERR equals 1). 0x04 + read-only - PAR - Parity Error Detector Flag. + ERRADDR 0 - 1 - - - WTOV - Waiting Time Counter Overflow. - 1 - 1 - - - CCOV - Clock Counter Overflow Flag. - 2 - 1 - - - TXCF - Transmit Complete Flag. - 3 - 1 - - - RXEMPTY - Receive FIFO Empty Flag. - 4 - 1 - - - RXFULL - Receive FIFO Full Flag. - 5 - 1 - - - TXEMPTY - Transmit FIFO Empty Flag. - 6 - 1 - - - TXFULL - Transmit FIFO Full Flag. - 7 - 1 - - - RXELT - Number of Bytes in the Receive FIFO. - 8 - 4 - - - TXELT - Number of Bytes in the Transmit FIFO. - 12 - 4 + 32 - PN - Pin Register, - 0x08 + FSTAT + funcstat register. + 0x100 + read-only - CRDRST - Smart Card Reset Pin Control. + FPU + FPU Function. 0 1 + + + no + 0 + + + yes + 1 + + - CRDCLK - Smart Card Clock Piin Control. + USB + USB Device. 1 1 + + + no + 0 + + + yes + 1 + + - CRDIO - Smart Card IO Pin Control. + ADC + 10-bit Sigma Delta ADC. 2 1 + + + no + 0 + + + yes + 1 + + - CRDC4 - Smart Card SCn_C4 Pin Control. + XIP + XiP function. 3 1 + + + no + 0 + + + yes + 1 + + - CRDC8 - Smart Card SCn_C8 Pin Control. - 4 - 1 - - - CLKSEL - Smart Card Clock Select. - 5 - 1 - - - - - ETUR - ETU Register. - 0x0C - - - ETU - Elemental Time Unit Value. - 0 - 15 - - - COMP - Compensation Mode Enable Bit. - 15 - 1 - - - HALF - Half ETU Count Selection Bit. - 16 - 1 - - - - - GTR - Guard Time Register. - 0x10 - - - GT - Guard Time. - 0 - 16 - - - - - WT0R - Waiting Time 0 Register. - 0x14 - - - WT - Wait Time. - 0 - 32 - - - - - WT1R - Waiting Time 1 Register. - 0x18 - - - WT - Wait Time. - 0 - 8 - - - - - IER - Interrupt Enable Register. - 0x1C - - - PARIE - Parity Error Interrupt Enable. - 0 - 1 - - - WTIE - Waiting Time Overflow Interrupt Enable. - 1 - 1 - - - CTIE - Clock Counter Overflow Interrupt Enable. - 2 - 1 - - - TCIE - Character Transmission Completion Interrupt Enable. - 3 + SDHC + SDHC function. + 6 1 + + + no + 0 + + + yes + 1 + + - RXEIE - Receive FIFO Empty Interrupt Enable. - 4 + SMPHR + SMPHR function. + 7 1 + + + no + 0 + + + yes + 1 + + - RXTIE - Receive FIFO Threshold Reached Interrupt Enable. - 5 + SRCC + SRCC function. + 8 1 + + + no + 0 + + + yes + 1 + + - RXFIE - Receive FIFO Full Interrupt Enable. - 6 + ADC9 + ADC9 function. + 9 1 + + + no + 0 + + + yes + 1 + + - TXEIE - Transmit FIFO Empty Interrupt Enable. - 7 + SC + SC function. + 10 1 + + + no + 0 + + + yes + 1 + + - TXTIE - Transmit FIFO Threshold Reached Interrupt Enable. - 8 + NMI + NMI function. + 12 1 + + + no + 0 + + + yes + 1 + + - ISR - Interrupt Status Register. - 0x20 + SFSTAT + secfuncstat register. + 0x104 + read-only - PARIS - Parity Error Interrupt Status Flag. + SBD + SBD function. 0 1 + + + no + 0 + + + yes + 1 + + - WTIS - Waiting Time Overflow Interrupt Status Flag. + SLD + SLD function. 1 1 + + + no + 0 + + + yes + 1 + + - CTIS - Clock Counter Overflow Interrupt Status Flag. + TRNGD + TRNG function. 2 1 + + + no + 0 + + + yes + 1 + + - TCIS - Character Transmission Completion Interrupt Status Flag. + AESD + AES function. 3 1 + + + no + 0 + + + yes + 1 + + - RXEIS - Receive FIFO Empty Interrupt Status Flag. + SHAD + SHA function. 4 1 + + + no + 0 + + + yes + 1 + + - RXTIS - Receive FIFO Threshold Reached Interrupt Status Flag. - 5 - 1 - - - RXFIS - Receive FIFO Full Interrupt Status Flag. - 6 - 1 - - - TXEIS - Transmit FIFO Empty Interrupt Status Flag. + SMD + SMD function. 7 1 - - - TXTIS - Transmit FIFO Threshold Reached Interrupt Status Flag. - 8 - 1 - - - - - TXR - Transmit Register. - 0x24 - - - DATA - Transmit Data. - 0 - 8 - - - - - RXR - Receive Register. - 0x28 - - - DATA - Receive Data. - 0 - 8 - - - PARER - Parity Error Detect Bit. - 8 - 1 - - - - - CCR - Clock Counter Register, - 0x2C - - - CCYC - Number of Clock Cycles to Count. - 0 - 24 - - - MAN - Manual Mode. - 31 - 1 + + + no + 0 + + + yes + 1 + + - - - SCN1 - Smart Card Interface. 1 - 0x4002D000 - - SCN1 - SCN1 IRQ - 37 - - - + SDHC SDHC/SDIO Controller @@ -15306,749 +13976,453 @@ read-only - - - SLOT_INT - Slot Interrupt Status. - 0x0FC - 16 - read-only - - - INT_SIGNALS - Interrupt Signal For Each Slot. - 0 - 1 - read-only - - - - - HOST_CN_VER - Host Controller Version. - 0x0FE - 16 - - - SPEC_VER - Specification Version Number. - 0 - 8 - - - VEND_VER - Vendor Version Number. - 8 - 8 - - - - - - - - SEMA - The Semaphore peripheral allows multiple cores in a system to cooperate when accessing shred resources. - The peripheral contains eight semaphores that can be atomically set and cleared. It is left to the discretion of the software - architect to decide how and when the semaphores are used and how they are allocated. Existing hardware does not have to be - - modified for this type of cooperative sharing, and the use of semaphores is exclusively within the software domain. - 0x4003E000 - - 0x00 - 0x1000 - registers - - + - 8 - 0x04 - SEMAPHORES[%s] - Read to test and set, returns prior value. Write 0 to clear semaphore. - 0x000 - 32 + SLOT_INT + Slot Interrupt Status. + 0x0FC + 16 + read-only - sema + INT_SIGNALS + Interrupt Signal For Each Slot. 0 1 + read-only - status - Semaphore status bits. 0 indicates the semaphore is free, 1 indicates taken. - 0x100 - 32 + HOST_CN_VER + Host Controller Version. + 0x0FE + 16 - STATUS + SPEC_VER + Specification Version Number. 0 8 + + VEND_VER + Vendor Version Number. + 8 + 8 + - + - SIR - System Initialization Registers. - 0x40000400 - read-only + HA + Hardware Accelerator + 0x40036000 0x00 - 0x400 + 0x1000 registers + + HA + Smart DMA interrupt. + 60 + - SISTAT - System Initialization Status Register. + IP + Q30E Instruction Pointer. 0x00 read-only - - - MAGIC - Magic Word Validation. This bit is set by the system initialization block following power-up. - 0 - 1 - read-only - - read - - magicNotSet - Magic word was not set (OTP has not been initialized properly). - 0 - - - magicSet - Magic word was set (OTP contains valid settings). - 1 - - - - - CRCERR - CRC Error Status. This bit is set by the system initialization block following power-up. - 1 - 1 - read-only - - read - - noError - No CRC errors occurred during the read of the OTP memory block. - 0 - - - error - A CRC error occurred while reading the OTP. The address of the failure location in the OTP memory is stored in the ERRADDR register. - 1 - - - - - ERRADDR - Read-only field set by the SIB block if a CRC error occurs during the read of the OTP memory. Contains the failing address in OTP memory (when CRCERR equals 1). + SP + Q30E Stack Pointer. 0x04 read-only - - - ERRADDR - 0 - 32 - - - FSTAT - funcstat register. - 0x100 + DP0 + Q30E Data Pointer 0. + 0x08 read-only - - - FPU - FPU Function. - 0 - 1 - - - no - 0 - - - yes - 1 - - - - - USB - USB Device. - 1 - 1 - - - no - 0 - - - yes - 1 - - - - - ADC - 10-bit Sigma Delta ADC. - 2 - 1 - - - no - 0 - - - yes - 1 - - - - - XIP - XiP function. - 3 - 1 - - - no - 0 - - - yes - 1 - - - - - SDHC - SDHC function. - 6 - 1 - - - no - 0 - - - yes - 1 - - - + + + DP1 + Q30E Data Pointer 1. + 0x0C + read-only + + + BP + Q30E Frame Pointer Base. + 0x10 + read-only + + + OFFS + Q30E Frame Pointer Offset. + 0x14 + read-only + + + LC0 + Q30E Loop Counter 0. + 0x18 + read-only + + + LC1 + Q30E Loop Counter 1. + 0x1C + read-only + + + A0 + Q30E Accumulator 0. + 0x20 + read-only + + + A1 + Q30E Accumulator 1. + 0x24 + read-only + + + A2 + Q30E Accumulator 2. + 0x28 + read-only + + + A3 + Q30E Accumulator 3. + 0x2C + read-only + + + WDCN + Q30E Watchdog Control. + 0x30 + read-only + + + INT_MUX_CTRL0 + Interrupt Mux Control 0. + 0x80 + read-write + - SMPHR - SMPHR function. - 7 - 1 - - - no - 0 - - - yes - 1 - - + INTSEL16 + Interrupt Selection For 16th Interrupt. + 0 + 8 - SRCC - SRCC function. + INTSEL17 + Interrupt Selection For 17th Interrupt. 8 - 1 - - - no - 0 - - - yes - 1 - - - - - ADC9 - ADC9 function. - 9 - 1 - - - no - 0 - - - yes - 1 - - + 8 - SC - SC function. - 10 - 1 - - - no - 0 - - - yes - 1 - - + INTSEL18 + Interrupt Selection For 18th Interrupt. + 16 + 8 - NMI - NMI function. - 12 - 1 - - - no - 0 - - - yes - 1 - - + INTSEL19 + Interrupt Selection For 19th Interrupt. + 24 + 8 - SFSTAT - secfuncstat register. - 0x104 - read-only + INT_MUX_CTRL1 + Interrupt Mux Control 1. + 0x84 + read-write - SBD - SBD function. + INTSEL20 + Interrupt Selection For 20th Interrupt. 0 - 1 - - - no - 0 - - - yes - 1 - - - - - SLD - SLD function. - 1 - 1 - - - no - 0 - - - yes - 1 - - - - - TRNGD - TRNG function. - 2 - 1 - - - no - 0 - - - yes - 1 - - + 8 - AESD - AES function. - 3 - 1 - - - no - 0 - - - yes - 1 - - + INTSEL21 + Interrupt Selection For 21st Interrupt. + 8 + 8 - SHAD - SHA function. - 4 - 1 - - - no - 0 - - - yes - 1 - - + INTSEL22 + Interrupt Selection For 22nd Interrupt. + 16 + 8 - SMD - SMD function. - 7 - 1 - - - no - 0 - - - yes - 1 - - + INTSEL23 + Interrupt Selection For 23rd Interrupt. + 24 + 8 - - - - - SKBD - Secure Keyboard - 0x40032000 - - 0x00 - 0x1000 - registers - - - Secure_Keypad - Secure Keypad interrupt - 19 - - - CR0 - Input Output Select Bits. Each bit of IOSEL selects the pin direction for the corresponding KBDIO pin. If IOSEL[0] = 1, KBDIO0 is an output. - 0x00 + INT_MUX_CTRL2 + Interrupt Mux Control 2. + 0x88 + read-write - KBDIO_0 - Input Output Select for KBDIO0 pin. + INTSEL24 + Interrupt Selection For 24th Interrupt. 0 - 10 - - - input - Input - 0 - - - output - Output - 1 - - + 8 + + + INTSEL25 + Interrupt Selection For 25th Interrupt. + 8 + 8 + + + INTSEL26 + Interrupt Selection For 26th Interrupt. + 16 + 8 + + + INTSEL27 + Interrupt Selection For 27th Interrupt. + 24 + 8 - CR1 - Control Register 1 - 0x04 + INT_MUX_CTRL3 + Interrupt Mux Control 3. + 0x8C + read-write - AUTOEN - Automatic Keyboard Scan Enable + INTSEL28 + Interrupt Selection For 28th Interrupt. 0 - 1 - - - disable - Disable - 0 - - - enable - Enable - 1 - - - - - CLEAR - Auto Clear Bit - 1 - 1 + 8 - OUTNB - Output Number. Number of KBDIO pins selected as outputs. NOTE: - Output pins must be allocated contiguously starting with KBDIO0 and continuing through to KBDIO7. + INTSEL29 + Interrupt Selection For 29th Interrupt. 8 - 3 + 8 - DBTM - Debounce Time. Number of milliseconds a keypress event must be active before it is considered actual. NOTE: - Debounce time values based on system running from an external 12MHz clock source with PLL0 enabled. Other external crystal values will cause the debounce time to scale linearly. - 13 - 3 - - - time4ms - 4.1 ms - 0 - - - time5ms - 5.3 ms - 1 - - - time6ms - 6.5 ms - 2 - - - time7ms - 7.6 ms - 3 - - - time8ms - 8.8 ms - 4 - - - time10ms - 10.0 ms - 5 - - - time11ms - 11.2 ms - 6 - - - time12ms - 12.3 ms - 7 - - + INTSEL30 + Interrupt Selection For 30th Interrupt. + 16 + 8 + + + INTSEL31 + Interrupt Selection For 31st Interrupt. + 24 + 8 - SR - Status Register - 0x08 - read-only + IP_ADDR + Configurable starting IP address for Q30E. + 0x90 + read-write - BUSY - Busy bit. This bit is set by hardware when the automatic keyboard scan is enabled and running. This bit is clear at all other times. + START_IP_ADDR + Starting IP address for Q30E 0 - 1 - - - idle - Idle - 0 - - - busy - Busy - 1 - - + 32 - IER - Interrupt Enable Register - 0x0C + CTRL + Control Register. + 0x94 + read-write - PUSHIE - Push Event Enable Bit. When set, this bit enables an interrupt to be generated on a key push event. Automatic keyboard scan must be enabled. + EN + Enable SDMA. 0 1 - disable - Disable + dis + Disable SDMA. 0 - enable - Enable + en + Enable SDMA. 1 - - RELEASEIE - Release Event Enable Bit. When set, this bit enables an interrupt to be generated on a key release event. Automatic keyboard scan must be enabled. - 1 - 1 - - - OVERIE - Overrun Event Enable Bit. When set, this bit enables an interrupt to be generated on an overrun event. Automatic keyboard scan must be enabled. - 2 - 1 - - ISR - Interrupt Status Register - 0x10 + INT_IN_CTRL + Interrupt Input From CPU Control Register. + 0xA0 + read-write - PUSHIS - Push Interrupt Flag. This bit is set by hardware when a key has been pushed. If the interrupt is enabled for this flag, a system interrupt will be fired. If the interrupt enable is not set, the flag will be set, but no interrupt will fire. This bit must be cleared by software. + INTSET + Set Interrupt Flag. 0 1 - inactive - No interrupt is pending. + dis + Set interrupt Flag to 0. 0 - pending - An interrupt is pending. + set + Set Interrupt Flag to 1. 1 - - RELEASEIS - Release Interrupt Flag. This bit is set by hardware when a key has been released. If the interrupt is enabled for this flag, a system interrupt will be fired. If the interrupt enable is not set, the flag will be set, but no interrupt will fire. This bit must be cleared by software. - 1 - 1 - - - OVERIS - Overrun Event Enable Bit. This bit is set by hardware when an overrun event has occurred. If the interrupt is enabled for this flag, a system interrupt will be fired. If the interrupt enable is not set, the flag will be set, but no interrupt will fire. This bit must be cleared by software. - 2 - 1 - - 4 - 4 - EVENT[%s] - Key Register - 0x14 - read-only - 0x00000C00 + INT_IN_FLAG + Interrupt Input From CPU Flag. + 0xA4 + read-write - IOIN - IO Input. Input pin of key event. - 0 - 3 - - - IOOUT - IO Output. Output pin of key event. - 5 - 3 - - - PUSH - If set to 1 the key has been released. If set to 0 the key has been pushed. - 10 - 1 - - - pushed - Pushed - 0 - - - released - Released - 1 - - - - - READ - If set to 1 this register has been read. If set to 0 the key register has not been read since its last change. - 11 - 1 - - - notRead - This register has not been read since its last change. - 0 - - - read - This register has been read. - 1 - - - - - NEXT - If set to 1 one of the next key registers (x+1 to 3) contains a key event. - 12 + INTFLAG + Interrupt Flag. + 0 1 - none - No more key register contain a key event. + no_eff + No Effect. 0 - more - Other key registers contain a key event. + clear + INT_IN_FLAG =0 1 + + INT_IN_IE + Interrupt Input From CPU Enable. + 0xA8 + read-write + + + INT_IN_EN + Interrupt Enable. + 0 + 1 + + + + + IRQ_FLAG + Interrupt Output To CPU Flag. + 0xB0 + read-write + + + IRQ_FLAG + Interrupt Flag. + 0 + 1 + + + + + IRQ_IE + Interrupt Output To CPU Control Register. + 0xB4 + read-write + + + IRQ_EN + Interrupt Enable. + 0 + 1 + + + - + + + SEMA + The Semaphore peripheral allows multiple cores in a system to cooperate when accessing shred resources. + The peripheral contains eight semaphores that can be atomically set and cleared. It is left to the discretion of the software + architect to decide how and when the semaphores are used and how they are allocated. Existing hardware does not have to be + + modified for this type of cooperative sharing, and the use of semaphores is exclusively within the software domain. + 0x4003E000 + + 0x00 + 0x1000 + registers + + + + 8 + 0x04 + SEMAPHORES[%s] + Read to test and set, returns prior value. Write 0 to clear semaphore. + 0x000 + 32 + + + sema + 0 + 1 + + + + + status + Semaphore status bits. 0 indicates the semaphore is free, 1 indicates taken. + 0x100 + 32 + + + STATUS + 0 + 8 + + + + + + SMON The Security Monitor block used to monitor system threat conditions. @@ -17463,18 +15837,14 @@ - SPI - SPI peripheral. - 0x40046000 + SPIXR + SPIXR peripheral. + 0x4003A000 0x00 0x1000 registers - - SPI0 - 16 - DATA32 @@ -17484,7 +15854,7 @@ read-write - QSPIFIFO + DATA Read to pull from RX FIFO, write to put into TX FIFO. 0 32 @@ -17502,7 +15872,7 @@ read-write - QSPIFIFO + DATA Read to pull from RX FIFO, write to put into TX FIFO. 0 16 @@ -17520,7 +15890,7 @@ read-write - QSPIFIFO + DATA Read to pull from RX FIFO, write to put into TX FIFO. 0 8 @@ -17528,13 +15898,13 @@ - CTRL0 + CTRL1 Register for controlling SPI peripheral. 0x04 read-write - EN + SPIEN SPI Enable. 0 1 @@ -17552,7 +15922,7 @@ - MASTER + MMEN Master Mode Enable. 1 1 @@ -17570,8 +15940,10 @@ - SS_IO - Slave Select 0, IO direction, to support Multi-Master mode,Slave Select 0 can be input in Master mode. This bit has no effect in slave mode. + SSIO + Slave Select 0, IO direction, to support Multi-Master mode, + Slave Select 0 can be input in Master mode. This bit has no + effect in slave mode. 4 1 @@ -17588,31 +15960,36 @@ - START + TX_START Start Transmit. 5 1 start - Master Initiates a transaction, this bit is self clearing when transactions are done. If a transaction cimpletes, and the TX FIFO is empty, the Master halts, if a transaction completes, and the TX FIFO is not empty, the Master initiates another transaction. + Master Initiates a transaction, this bit is + self clearing when transactions are done. If + a transaction completes, and the TX FIFO + is empty, the Master halts, if a transaction + completes, and the TX FIFO is not empty, + the Master initiates another transaction. 1 SS_CTRL - Start Select Control. Used in Master mode to control the behavior of the Slave Select signal at the end of a transaction. + Slave Select Control. 8 1 - DEASSERT - SPI De-asserts Slave Select at the end of a transaction. + deassert + SPI de-asserts Slave Select at the end of a transaction. 0 - ASSERT + assert SPI leaves Slave Select asserted at the end of a transaction. 1 @@ -17620,9 +15997,10 @@ SS - Slave Select, when in Master mode selects which Slave devices are selected. More than one Slave device can be selected. + Slave Select, when in Master mode selects which Slave devices are + selected. More than one Slave device can be selected. 16 - 4 + 8 SS0 @@ -17644,12 +16022,32 @@ SS3 is selected. 0x8 + + SS4 + SS4 is selected. + 0x10 + + + SS5 + SS5 is selected. + 0x20 + + + SS6 + SS6 is selected. + 0x40 + + + SS7 + SS7 is selected. + 0x80 + - CTRL1 + CTRL2 Register for controlling SPI peripheral. 0x08 read-write @@ -17669,7 +16067,7 @@ - CTRL2 + CTRL3 Register for controlling SPI peripheral. 0x0C read-write @@ -17679,33 +16077,27 @@ Clock Phase. 0 1 - - - Rising_Edge - Data Sampled on clock rising edge. Use when in SPI Mode 0 and Mode 2 - 0 - - - Falling_Edge - Data Sampled on clock falling edge. Use when in SPI Mode 1 and Mode 3 - 1 - - CPOL Clock Polarity. 1 1 + + + SCLK_FB_INV + Invert SCLK Feedback in Master Mode. + 4 + 1 - Normal - Normal Clock. Use when in SPI Mode 0 and Mode 1 + NON_INV + SCLK is not inverted to Line Receiver. 0 - Inverted - Inverted Clock. Use when in SPI Mode 2 and Mode 3 + INV + SCLK is inverted to Line Receiver. 1 @@ -17765,10 +16157,10 @@ - SS_POL + SSPOL Slave Select Polarity, each Slave Select can have unique polarity. 16 - 4 + 8 SS0_high @@ -17790,19 +16182,39 @@ SS3 active high. 0x8 + + SS4_high + SS4 active high. + 0x10 + + + SS5_high + SS5 active high. + 0x20 + + + SS6_high + SS6 active high. + 0x40 + + + SS7_high + SS7 active high. + 0x80 + SS_TIME - Register for controlling SPI peripheral/Slave Select Timing. + Register for controlling SPI peripheral. 0x10 read-write - PRE - Slave Select Pre delay 1. + SSACT1 + Slave Select Action delay 1. 0 8 @@ -17814,8 +16226,8 @@ - POST - Slave Select Post delay 2. + SSACT2 + Slave Select Action delay 2. 8 8 @@ -17827,7 +16239,7 @@ - INACT + SSINACT Slave Select Inactive delay. 16 8 @@ -17842,13 +16254,13 @@ - CLK_CFG + BRG_CTRL Register for controlling SPI clock rate. 0x14 read-write - LO + LOW Low duty cycle control. In timer mode, reload[7:0]. 0 8 @@ -17889,7 +16301,9 @@ TX_FIFO_LEVEL - Transmit FIFO level that will trigger a DMA request, also level for threshold status. When TX FIFO has fewer than this many bytes, the associated events and conditions are triggered. + Transmit FIFO level that will trigger a DMA request, also level for + threshold status. When TX FIFO has fewer than this many bytes, the + associated events and conditions are triggered. 0 5 @@ -17914,8 +16328,8 @@ TX_FIFO_CLEAR Clear TX FIFO, clear is accomplished by resetting the read and write - pointers. This should be done when FIFO is not being accessed on the SPI side. - . + pointers. This should be done when FIFO is not being accessed on the SPI side. + 7 1 @@ -17930,8 +16344,7 @@ TX_FIFO_CNT Count of entries in TX FIFO. 8 - 6 - read-only + 5 TX_DMA_EN @@ -17953,9 +16366,11 @@ RX_FIFO_LEVEL - Receive FIFO level that will trigger a DMA request, also level for threshold status. When RX FIFO has more than this many bytes, the associated events and conditions are triggered. + Receive FIFO level that will trigger a DMA request, also level for + threshold status. When RX FIFO has more than this many bytes, the + associated events and conditions are triggered. 16 - 5 + 6 RX_FIFO_EN @@ -17977,13 +16392,14 @@ RX_FIFO_CLEAR - Clear RX FIFO, clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side. + Clear RX FIFO, clear is accomplished by resetting the read and write + pointers. This should be done when FIFO is not being accessed on the SPI side. 23 1 CLEAR - Clear the Receive FIFO, clears any pending RX FIFO status. + Clear the Receive FIFIO, clears any pending RX FIFO status. 1 @@ -17993,7 +16409,6 @@ Count of entries in RX FIFO. 24 6 - read-only RX_DMA_EN @@ -18140,7 +16555,8 @@ TX_OVR - Transmit FIFO Overrun, set when the AMBA side attempts to write data to a full transmit FIFO. + Transmit FIFO Overrun, set when the AMBA side attempts to write data + to a full transmit FIFO. 12 1 @@ -18153,7 +16569,8 @@ TX_UND - Transmit FIFO Underrun, set when the SPI side attempts to read data from an empty transmit FIFO. + Transmit FIFO Underrun, set when the SPI side attempts to read data + from an empty transmit FIFO. 13 1 @@ -18582,816 +16999,571 @@ BUSY - SPI active status. In Master mode, set when transaction starts, cleared when last bit of last character is acted upon and Slave Select de-assertion would occur. In Slave mode, set when Slave Select is asserted, cleared when Slave Select is de-asserted. Not used in Timer mode. - 0 - 1 - - - not - SPI not active. - 0 - - - active - SPI active. - 1 - - - - - - - - - - SPI1 - SPI peripheral. 1 - 0x40047000 - - SPI1 - SPI1 IRQ - 17 - - - - - SPI2 - SPI peripheral. 2 - 0x40048000 - - SPI2 - SPI2 IRQ - 18 - - - - - SPIXR - SPIXR peripheral. - 0x4003A000 - - 0x00 - 0x1000 - registers - - - - DATA32 - Register for reading and writing the FIFO. - 0x00 - 32 - read-write - - - DATA - Read to pull from RX FIFO, write to put into TX FIFO. - 0 - 32 - - - - - 2 - 2 - DATA16[%s] - Register for reading and writing the FIFO. - DATA32 - 0x00 - 16 - read-write - - - DATA - Read to pull from RX FIFO, write to put into TX FIFO. - 0 - 16 - - - - - 4 - 1 - DATA8[%s] - Register for reading and writing the FIFO. - DATA32 - 0x00 - 8 - read-write - - - DATA - Read to pull from RX FIFO, write to put into TX FIFO. - 0 - 8 - - - - - CTRL1 - Register for controlling SPI peripheral. - 0x04 - read-write - - - SPIEN - SPI Enable. - 0 - 1 - - - dis - SPI is disabled. - 0 - - - en - SPI is enabled. - 1 - - - - - MMEN - Master Mode Enable. - 1 - 1 - - - dis - SPI is Slave mode. - 0 - - - en - SPI is Master mode. - 1 - - - - - SSIO - Slave Select 0, IO direction, to support Multi-Master mode, - Slave Select 0 can be input in Master mode. This bit has no - effect in slave mode. - 4 - 1 - - - output - Slave select 0 is output. - 0 - - - input - Slave Select 0 is input, only valid if MMEN=1. - 1 - - - - - TX_START - Start Transmit. - 5 - 1 - - - start - Master Initiates a transaction, this bit is - self clearing when transactions are done. If - a transaction completes, and the TX FIFO - is empty, the Master halts, if a transaction - completes, and the TX FIFO is not empty, - the Master initiates another transaction. - 1 - - - - - SS_CTRL - Slave Select Control. - 8 - 1 - - - deassert - SPI de-asserts Slave Select at the end of a transaction. - 0 - - - assert - SPI leaves Slave Select asserted at the end of a transaction. - 1 - - - - - SS - Slave Select, when in Master mode selects which Slave devices are - selected. More than one Slave device can be selected. - 16 - 8 - - - SS0 - SS0 is selected. - 0x1 - - - SS1 - SS1 is selected. - 0x2 - - - SS2 - SS2 is selected. - 0x4 - - - SS3 - SS3 is selected. - 0x8 - - - SS4 - SS4 is selected. - 0x10 - - - SS5 - SS5 is selected. - 0x20 - + SPI active status. In Master mode, set when transaction starts, + cleared when last bit of last character is acted upon and Slave Select + de-assertion would occur. In Slave mode, set when Slave Select is + asserted, cleared when Slave Select is de-asserted. Not used in Timer mode. + + 0 + 1 + - SS6 - SS6 is selected. - 0x40 + not + SPI not active. + 0 - SS7 - SS7 is selected. - 0x80 + active + SPI active. + 1 - CTRL2 - Register for controlling SPI peripheral. - 0x08 + XMEM_CTRL + Register to control external memory. + 0x34 read-write - TX_NUM_CHAR - Nubmer of Characters to transmit. + RD_CMD + Read command. 0 - 16 + 8 - RX_NUM_CHAR - Nubmer of Characters to receive. + WR_CMD + Write command. + 8 + 8 + + + DUMMY_CLK + Dummy clocks. 16 - 16 + 8 + + + XMEM_EN + XMEM enable. + 31 + 1 + + + + + SPIXFC + SPI XiP Flash Configuration Controller + 0x40027000 + + 0 + 0x1000 + registers + + + SPIXFC + SPIXFC IRQ + 38 + + - CTRL3 - Register for controlling SPI peripheral. - 0x0C - read-write + CFG + Configuration Register. + 0x00 - CPHA - Clock Phase. + SSEL + Slaves Select. 0 - 1 - - - CPOL - Clock Polarity. - 1 - 1 - - - SCLK_FB_INV - Invert SCLK Feedback in Master Mode. - 4 - 1 + 3 - NON_INV - SCLK is not inverted to Line Receiver. + Slave_0 + Slave 0 is selected. 0 - INV - SCLK is inverted to Line Receiver. + Slave_1 + Slave 1 is selected. 1 - NUMBITS - Number of Bits per character. - 8 - 4 + MODE + Defines SPI Mode, Only valid values are 0 and 3. + 4 + 2 - 0 - 16 bits per character. + SPIX_Mode_0 + SPIX Mode 0. CLK Polarity = 0, CLK Phase = 0. 0 + + SPIX_Mode_3 + SPIX Mode 3. CLK Polarity = 1, CLK Phase = 1. + 3 + - DATA_WIDTH - SPI Data width. - 12 + PAGE_SIZE + Page Size. + 6 2 - Mono - 1 data pin. + 4_bytes + 4 bytes. 0 - Dual - 2 data pins. + 8_bytes + 8 bytes. 1 - Quad - 4 data pins. + 16_bytes + 16 bytes. 2 - - - - THREE_WIRE - Three Wire mode. MOSI/MISO pin(s) shared. Only Mono mode suports Four-Wire. - 15 - 1 - - - dis - Use four wire mode (Mono only). - 0 - - en - Use three wire mode. - 1 + 32_bytes + 32 bytes. + 3 - SSPOL - Slave Select Polarity, each Slave Select can have unique polarity. - 16 - 8 + HI_CLK + SCLK High Clocks. Number of system clocks that SCLK will be high when SCLK pulses are generated. 0 Correspond to 16 system clocks and, all other values defines the number of system clock taht SCLK will be held high. + 8 + 4 - SS0_high - SS0 active high. - 0x1 - - - SS1_high - SS1 active high. - 0x2 - - - SS2_high - SS2 active high. - 0x4 - - - SS3_high - SS3 active high. - 0x8 - - - SS4_high - SS4 active high. - 0x10 - - - SS5_high - SS5 active high. - 0x20 - - - SS6_high - SS6 active high. - 0x40 - - - SS7_high - SS7 active high. - 0x80 + 16_SCLK + 16 system clocks. + 0 - - - - SS_TIME - Register for controlling SPI peripheral. - 0x10 - read-write - - SSACT1 - Slave Select Action delay 1. - 0 - 8 + LO_CLK + SCLK low Clocks. Number of system clocks that SCLK will be low when SCLK pulses are generated. 0 correspond to 16 system clocks and, all other values defines the number of system clock taht SCLK will be held low. + 12 + 4 - 256 - 256 system clocks between SS active and first serial clock edge. + 16_SCLK + 16 system clocks. 0 - SSACT2 - Slave Select Action delay 2. - 8 - 8 + SSACT + Slaves Select Activate Timing. + 16 + 2 - 256 - 256 system clocks between last serial clock edge and SS inactive. + 0_CLKS + 0 sytem clocks. 0 + + 2_CLKS + 2 sytem clocks. + 1 + + + 4_CLKS + 4 sytem clocks. + 2 + + + 8_CLKS + 8 sytem clocks. + 3 + - SSINACT - Slave Select Inactive delay. - 16 - 8 + SSIACT + Slaves Select Inactive Timing. + 18 + 2 - 256 - 256 system clocks between transactions. + 4_CLKS + 4 sytem clocks. 0 + + 6_CLKS + 6 sytem clocks. + 1 + + + 8_CLKS + 8 sytem clocks. + 2 + + + 12_CLKS + 12 sytem clocks. + 3 + + + IOSMPL + Sample Delay + 20 + 4 + - BRG_CTRL - Register for controlling SPI clock rate. - 0x14 - read-write + SS_POL + SPIX Controller Slave Select Polarity Register. + 0x04 - LOW - Low duty cycle control. In timer mode, reload[7:0]. + SSPOL_0 + Slave Select Polarity. 0 - 8 + 1 - Dis - Duty cycle control of serial clock generation is disabled. + lo + Active Low. 0 - - - - HI - High duty cycle control. In timer mode, reload[15:8]. - 8 - 8 - - Dis - Duty cycle control of serial clock generation is disabled. - 0 + hi + Active High. + 1 - - SCALE - System Clock scale factor. Scales the AMBA clock by 2^SCALE before generating serial clock. - 16 - 4 - - DMA - Register for controlling DMA. - 0x1C - read-write + GEN_CTRL + SPIX Controller General Controller Register. + 0x08 - TX_FIFO_LEVEL - Transmit FIFO level that will trigger a DMA request, also level for - threshold status. When TX FIFO has fewer than this many bytes, the - associated events and conditions are triggered. + ENABLE + SPI Master enable. 0 - 5 - - - TX_FIFO_EN - Transmit FIFO enabled for SPI transactions. - 6 1 dis - Transmit FIFO is not enabled. + Disable SPI Master, putting a reset state. 0 en - Transmit FIFO is enabled. + Enable SPI Master for processing transactions. 1 - TX_FIFO_CLEAR - Clear TX FIFO, clear is accomplished by resetting the read and write - pointers. This should be done when FIFO is not being accessed on the SPI side. - - 7 + TX_FIFO_EN + Transaction FIFO Enable. + 1 1 - CLEAR - Clear the Transmit FIFO, clears any pending TX FIFO status. + dis_txfifo + Disable Transaction FIFO. + 0 + + + en_txfifo + Enable Transaction FIFO. 1 - TX_FIFO_CNT - Count of entries in TX FIFO. - 8 - 5 - - - TX_DMA_EN - TX DMA Enable. - 15 + RX_FIFO_EN + Result FIFO Enable. + 2 1 - DIS - TX DMA requests are disabled, andy pending DMA requests are cleared. + dis_rxfifo + Disable Result FIFO. 0 - en - TX DMA requests are enabled. + en_rxfifo + Enable Result FIFO. 1 - RX_FIFO_LEVEL - Receive FIFO level that will trigger a DMA request, also level for - threshold status. When RX FIFO has more than this many bytes, the - associated events and conditions are triggered. - 16 - 6 - - - RX_FIFO_EN - Receive FIFO enabled for SPI transactions. - 22 + BBMODE + Bit-Bang Mode. + 3 1 - DIS - Receive FIFO is not enabled. + dis + Disable Bit-Bang Mode. 0 en - Receive FIFO is enabled. + Enable Bit-Bang Mode. 1 - RX_FIFO_CLEAR - Clear RX FIFO, clear is accomplished by resetting the read and write - pointers. This should be done when FIFO is not being accessed on the SPI side. - 23 + SSDR + This bits reflects the state of the currently selected slave select. + 4 1 - CLEAR - Clear the Receive FIFIO, clears any pending RX FIFO status. + output0 + Selected Slave select output = 0. + 0 + + + output1 + Selected Slave select output = 1. 1 - RX_FIFO_CNT - Count of entries in RX FIFO. - 24 - 6 - - - RX_DMA_EN - RX DMA Enable. - 31 + SCLK_DR + SSCLK Drive and State. + 6 1 - dis - RX DMA requests are disabled, any pending DMA requests are cleared. + SCLK_0 + SCLK is 0. 0 - en - RX DMA requests are enabled. + SCLK_1 + SCLK is 1. 1 - - - - INT_FL - Register for reading and clearing interrupt flags. All bits are write 1 to clear. - 0x20 - read-write - - TX_THRESH - TX FIFO Threshold Crossed. - 0 - 1 + SDIO_DATA_IN + SDIO Input Data Value. + 8 + 4 - clear - Flag is set when value read is 1. Write 1 to clear this flag. - 1 + SDIO0 + SDIO[0] + 0 - - - - TX_EMPTY - TX FIFO Empty. - 1 - 1 - - clear - Flag is set when value read is 1. Write 1 to clear this flag. + SDIO1 + SDIO[1] 1 - - - - RX_THRESH - RX FIFO Threshold Crossed. - 2 - 1 - - clear - Flag is set when value read is 1. Write 1 to clear this flag. - 1 + SDIO2 + SDIO[2] + 2 + + + SDIO3 + SDIO[3] + 3 - RX_FULL - RX FIFO FULL. - 3 - 1 + BB_DATA + No description available. + 12 + 4 - clear - Flag is set when value read is 1. Write 1 to clear this flag. + SDIO0 + SDIO[0] + 0 + + + SDIO1 + SDIO[1] 1 + + SDIO2 + SDIO[2] + 2 + + + SDIO3 + SDIO[3] + 3 + - SSA - Slave Select Asserted. - 4 - 1 + BB_DATA_OUT_EN + Bit Bang SDIO Output Enable. + 16 + 4 - clear - Flag is set when value read is 1. Write 1 to clear this flag. - 1 + SDIO0 + SDIO[0] + 0 - - - - SSD - Slave Select Deasserted. - 5 - 1 - - clear - Flag is set when value read is 1. Write 1 to clear this flag. + SDIO1 + SDIO[1] 1 + + SDIO2 + SDIO[2] + 2 + + + SDIO3 + SDIO[3] + 3 + - FAULT - Multi-Master Mode Fault. - 8 + SIMPLE + Simple Mode Enable. + 20 1 - - - clear - Flag is set when value read is 1. Write 1 to clear this flag. - 1 - - - ABORT - Slave Abort Detected. - 9 + SIMPLE_RX + Simple Receive Enable. + 21 1 - - - clear - Flag is set when value read is 1. Write 1 to clear this flag. - 1 - - - M_DONE - Master Done, set when SPI Master has completed any transactions. - 11 + SIMPLE_SS + Simple Mode Slave Select. + 22 1 - - - clear - Flag is set when value read is 1. Write 1 to clear this flag. - 1 - - - TX_OVR - Transmit FIFO Overrun, set when the AMBA side attempts to write data - to a full transmit FIFO. - 12 + SCLK_FB + Enable SCLK Feedback Mode. + 24 1 - clear - Flag is set when value read is 1. Write 1 to clear this flag. + dis + 0 + + + en 1 - TX_UND - Transmit FIFO Underrun, set when the SPI side attempts to read data - from an empty transmit FIFO. - 13 + SCLK_FB_INVERT + SCK Invert. + 25 1 - - - clear - Flag is set when value read is 1. Write 1 to clear this flag. - 1 - - + + + + + FIFO_CTRL + SPIX Controller FIFO Control and Status Register. + 0x0C + + + TX_FIFO_AE_LVL + Transaction FIFO Almost Empty Level. + 0 + 4 - RX_OVR - Receive FIFO Overrun, set when the SPI side attempts to write to a full receive FIFO. - 14 + TX_FIFO_CNT + Transaction FIFO Used. + 8 + 5 + + + RX_FIFO_AF_LVL + Results FIFO Almost Full Level. + 16 + 5 + + + RX_FIFO_CNT + Result FIFO Used. + 24 + 6 + + + + + SP_CTRL + SPIX Controller Special Control Register. + 0x10 + + + SAMPL + Setting this bit to a 1 enables the ability to drive SDIO outputs prior to the assertion of Slave Select. This bit must + only be set when the SPIXF bus is idle and the transaction FIFO is empty. This bit is automatically cleared by hardware after the + next slave select assertion. + 0 1 - - - clear - Flag is set when value read is 1. Write 1 to clear this flag. - 1 - - - RX_UND - Receive FIFO Underrun, set when the AMBA side attempts to read data from an empty receive FIFO. - 15 + SDIO_OUT + SDIO Output Value Sample Mode + 4 + 4 + + + SDIO_OUT_EN + SDIO Output Enable Sample Mode + 8 + 4 + + + SCLKINH3 + SCLK Inhibit Mode3. In SPI Mode 3, some SPI flash read timing diagrams show the last SCLK going low prior to de-assertion. The default is to support this additional falling edge of clock. When this bit is set and the device is in SPI Mode 3, the SPI clock is held high while Slave Select is de-asserted. This is to support some SPI flash write timing diagrams. + 16 1 - clear - Flag is set when value read is 1. Write 1 to clear this flag. + EN + Allow trailing SCLK low pulse prior to Slave Select de-assertion. + 0 + + + DIS + Inhibit trailing SCLK low pulse prior to Slave Select de-assertion. 1 @@ -19399,381 +17571,533 @@ - INT_EN - Register for enabling interrupts. - 0x24 - read-write + INT_FL + SPIX Controller Interrupt Status Register. + 0x14 - TX_THRESH - TX FIFO Threshold interrupt enable. + TX_STALLED + Transaction Stalled Interrupt Flag. 0 1 - dis - Interrupt is disabled. + CLR + Normal FIFO Transaction. 0 - en - Interrupt is enabled. + SET + Stalled FIFO Transaction. 1 - TX_EMPTY - TX FIFO Empty interrupt enable. + RX_STALLED + Results Stalled Interrupt Flag. 1 1 - dis - Interrupt is disabled. + CLR + Normal FIFO Operation. 0 - en - Interrupt is enabled. + SET + Stalled FIFO. 1 - RX_THRESH - RX FIFO Threshold Crossed interrupt enable. + TX_READY + Transaction Ready Interrupt Status. 2 1 - dis - Interrupt is disabled. + CLR + FIFO Transaction not ready. 0 - en - Interrupt is enabled. + SET + FIFO Transaction ready. 1 - RX_FULL - RX FIFO FULL interrupt enable. + RX_DONE + Results Done Interrupt Status. 3 1 - dis - Interrupt is disabled. + CLR + Results FIFO ready. 0 - en - Interrupt is enabled. + SET + Results FIFO Not ready. + 1 + + + + + TX_FIFO_AE + Transaction FIFO Almost Empty Flag. + 4 + 1 + + + CLR + Transaction FIFO not Almost Empty. + 0 + + + SET + Transaction FIFO Almost Empty. 1 - SSA - Slave Select Asserted interrupt enable. - 4 + RX_FIFO_AF + Results FIFO Almost Full Flag. + 5 1 - dis - Interrupt is disabled. + CLR + Results FIFO level below the Almost Full level. 0 - en - Interrupt is enabled. + SET + Results FIFO level at Almost Full level. 1 + + + + INT_EN + SPIX Controller Interrupt Enable Register. + 0x18 + - SSD - Slave Select Deasserted interrupt enable. - 5 + TX_STALLED + Transaction Stalled Interrupt Enable. + 0 1 - dis - Interrupt is disabled. + en + Disable Transaction Stalled Interrupt. 0 - en - Interrupt is enabled. + dis + Enable Transaction Stalled Interrupt. 1 - FAULT - Multi-Master Mode Fault interrupt enable. - 8 + RX_STALLED + Results Stalled Interrupt Enable. + 1 1 - dis - Interrupt is disabled. + en + Disable Results Stalled Interrupt. 0 - en - Interrupt is enabled. + dis + Enable Results Stalled Interrupt. 1 - ABORT - Slave Abort Detected interrupt enable. - 9 + TX_READY + Transaction Ready Interrupt Enable. + 2 1 - dis - Interrupt is disabled. + en + Disable FIFO Transaction Ready Interrupt. 0 - en - Interrupt is enabled. + dis + Enable FIFO Transaction Ready Interrupt. 1 - M_DONE - Master Done interrupt enable. - 11 + RX_DONE + Results Done Interrupt Enable. + 3 1 - dis - Interrupt is disabled. + en + Disable Results Done Interrupt. 0 - en - Interrupt is enabled. + dis + Enable Results Done Interrupt. 1 - TX_OVR - Transmit FIFO Overrun interrupt enable. - 12 + TX_FIFO_AE + Transaction FIFO Almost Empty Interrupt Enable. + 4 1 - dis - Interrupt is disabled. + en + Disable Transaction FIFO Almost Empty Interrupt. 0 - en - Interrupt is enabled. + dis + Enable Transaction FIFO Almost Empty Interrupt. 1 - TX_UND - Transmit FIFO Underrun interrupt enable. - 13 + RX_FIFO_AF + Results FIFO Almost Full Interrupt Enable. + 5 1 - dis - Interrupt is disabled. + en + Disable Results FIFO Almost Full Interrupt. 0 - en - Interrupt is enabled. + dis + Enable Results FIFO Almost Full Interrupt. 1 + + + + + + + SPIXFC_FIFO + SPI XiP Master Controller FIFO. + 0x400BC000 + + 0 + 0x1000 + registers + + + + TX_8 + SPI TX FIFO 8-Bit Write + 0x00 + 8 + uint8_t + + + TX_16 + SPI TX FIFO 16-Bit Write + TX_8 + 0x00 + 16 + uint16_t + + + TX_32 + SPI TX FIFO 32-Bit Write + TX_8 + 0x00 + 32 + uint32_t + + + RX_8 + SPI RX FIFO 8-Bit Access + 0x04 + 8 + uint8_t + + + RX_16 + SPI RX FIFO 16-Bit Access + RX_8 + 0x04 + 16 + uint16_t + + + RX_32 + SPI RX FIFO 32-Bit Access + RX_8 + 0x04 + 32 + uint32_t + + + + + + SPIXFM + SPIXF Master + 0x40026000 + + 0x00 + 0x1000 + registers + + + + CFG + SPIX Configuration Register. + 0x00 + - RX_OVR - Receive FIFO Overrun interrupt enable. - 14 - 1 + MODE + Defines SPI Mode, Only valid values are 0 and 3. + 0 + 2 - dis - Interrupt is disabled. + SCLK_HI_SAMPLE_RISING + Description not available. 0 - en - Interrupt is enabled. - 1 + SCLK_LO_SAMPLE_FAILLING + Description not available. + 3 - RX_UND - Receive FIFO Underrun interrupt enable. - 15 + SSPOL + Slave Select Polarity. + 2 1 - dis - Interrupt is disabled. + ACTIVE_HIGH + Slave Select is Active High. 0 - en - Interrupt is enabled. + ACTIVE_LOW + Slave Select is Active Low. 1 - - - - WAKE_FL - Register for wake up flags. All bits in this register are write 1 to clear. - 0x28 - read-write - - TX_THRESH - Wake on TX FIFO Threshold Crossed. - 0 - 1 + SSEL + Slave Select. Only valid value is zero. + 4 + 3 + + + LO_CLK + Number of system clocks that SCLK will be low when SCLK pulses are generated. + 8 + 4 + + + HI_CLK + Number of system clocks that SCLK will be high when SCLK pulses are generated. + 12 + 4 + + + SSACT + Slave Select Active Timing. + 16 + 2 - clear - Flag is set when value read is 1. Write 1 to clear this flag. + off + 0 system clocks. + 0 + + + for_2_mod_clk + 2 System clocks. 1 - - - - TX_EMPTY - Wake on TX FIFO Empty. - 1 - 1 - - clear - Flag is set when value read is 1. Write 1 to clear this flag. - 1 + for_4_mod_clk + 4 System clocks. + 2 - - - - RX_THRESH - Wake on RX FIFO Threshold Crossed. - 2 - 1 - - clear - Flag is set when value read is 1. Write 1 to clear this flag. - 1 + for_8_mod_clk + 8 System clocks. + 3 - RX_FULL - Wake on RX FIFO Full. - 3 - 1 + SSIACT + Slave Select Inactive Timing. + 18 + 2 - clear - Flag is set when value read is 1. Write 1 to clear this flag. + for_1_mod_clk + 1 system clocks. + 0 + + + for_3_mod_clk + 3 System clocks. 1 + + for_5_mod_clk + 5 System clocks. + 2 + + + for_9_mod_clk + 9 System clocks. + 3 + - WAKE_EN - Register for wake up enable. - 0x2C - read-write + FETCH_CTRL + SPIX Fetch Control Register. + 0x04 - TX_THRESH - Wake on TX FIFO Threshold Crossed Enable. + CMDVAL + Command Value sent to target to initiate fetching from SPI flash. 0 - 1 + 8 + + + CMD_WIDTH + Command Width. Number of data I/O used to send commands. + 8 + 2 - dis - Wakeup source disabled. + Single + Single SDIO. 0 - en - Wakeup source enabled. + Dual_IO + Dual SDIO. 1 + + Quad_IO + Quad SDIO. + 2 + + + Invalid + Invalid. + 3 + - TX_EMPTY - Wake on TX FIFO Empty Enable. - 1 - 1 + ADDR_WIDTH + Address Width. Number of data I/O used to send address, and mode/dummy clocks. + 10 + 2 - dis - Wakeup source disabled. + Single + Single SDIO. 0 - en - Wakeup source enabled. + Dual_IO + Dual SDIO. 1 + + Quad_IO + Quad SDIO. + 2 + + + Invalid + Invalid. + 3 + - RX_THRESH - Wake on RX FIFO Threshold Crossed Enable. - 2 - 1 + DATA_WIDTH + Data Width. Number of data I/O used to receive data. + 12 + 2 - dis - Wakeup source disabled. + Single + Single SDIO. 0 - en - Wakeup source enabled. + Dual_IO + Dual SDIO. 1 + + Quad_IO + Quad SDIO. + 2 + + + Invalid + Invalid. + 3 + - RX_FULL - Wake on RX FIFO Full Enable. - 3 + FOUR_BYTE_ADDR + Four Byte Address Mode. Enables 4-byte Flash Address Mode. + 16 1 - dis - Wakeup source disabled. + 3 + 3 Byte Address Mode. 0 - en - Wakeup source enabled. + 4 + 4 Byte Address Mode. 1 @@ -19781,693 +18105,801 @@ - STAT - SPI Status register. - 0x30 - read-only + MODE_CTRL + SPIX Mode Control Register. + 0x08 - BUSY - SPI active status. In Master mode, set when transaction starts, - cleared when last bit of last character is acted upon and Slave Select - de-assertion would occur. In Slave mode, set when Slave Select is - asserted, cleared when Slave Select is de-asserted. Not used in Timer mode. - + MDCLK + Mode Clocks. Number of SPI clocks needed during mode/dummy phase of fetch. 0 + 4 + + + NO_CMD + No Command Mode. + 8 1 - not - SPI not active. + always + Send read command every time SPI transaction is initiated. 0 - active - SPI active. + once + Send read command only once. NO read command in subsequent SPI transactions. 1 + + MODE_SEND + Mode Send. + 9 + 1 + - XMEM_CTRL - Register to control external memory. - 0x34 - read-write + MODE_DATA + SPIX Mode Data Register. + 0x0C - RD_CMD - Read command. + DATA + Mode Data. Specifies the data to send with the Dummy/Mode clocks. 0 - 8 - - - WR_CMD - Write command. - 8 - 8 + 16 - DUMMY_CLK - Dummy clocks. + OUT_EN + Mode Output Enable. Output enable state for each corresponding data bit in MD_DATA. 0: output enable off, I/O is tristate and 1: Output enable on, I/O is driving MD_DATA. 16 - 8 - - - XMEM_EN - XMEM enable. - 31 - 1 + 16 - - - - - SPIXFC - SPI XiP Flash Configuration Controller - 0x40027000 - - 0 - 0x1000 - registers - - - SPIXFC - SPIXFC IRQ - 38 - - - CFG - Configuration Register. - 0x00 + FB_CTRL + SPIX Feedback Control Register. + 0x10 - SSEL - Slaves Select. + FB_EN + Enable SCLK feedback mode. 0 - 3 + 1 - Slave_0 - Slave 0 is selected. + dis + Disable SCLK feedback mode. 0 - Slave_1 - Slave 1 is selected. + en + Enable SCLK feedback mode. 1 - MODE - Defines SPI Mode, Only valid values are 0 and 3. - 4 - 2 + INVERT_EN + Invert SCLK in feedback mode. + 1 + 1 - SPIX_Mode_0 - SPIX Mode 0. CLK Polarity = 0, CLK Phase = 0. + dis + Disable Invert SCLK feedback mode. 0 - SPIX_Mode_3 - SPIX Mode 3. CLK Polarity = 1, CLK Phase = 1. - 3 + en + Enable Invert SCLK feedback mode. + 1 + + + + IO_CTRL + SPIX IO Control Register. + 0x1C + - PAGE_SIZE - Page Size. - 6 - 2 + SCLK_DS + SCLK drive Strength. This bit controls the drive strength on the SCLK pin. + 0 + 1 - 4_bytes - 4 bytes. + Low + Low drive strength. 0 - 8_bytes - 8 bytes. + High + High drive strength. 1 - - 16_bytes - 16 bytes. - 2 - - - 32_bytes - 32 bytes. - 3 - - HI_CLK - SCLK High Clocks. Number of system clocks that SCLK will be high when SCLK pulses are generated. 0 Correspond to 16 system clocks and, all other values defines the number of system clock taht SCLK will be held high. - 8 - 4 + SS_DS + Slave Select Drive Strength. This bit controls the drive strength on the dedicated slave select pin. + 1 + 1 - 16_SCLK - 16 system clocks. + Low + Low drive strength. 0 + + High + High drive strength. + 1 + - LO_CLK - SCLK low Clocks. Number of system clocks that SCLK will be low when SCLK pulses are generated. 0 correspond to 16 system clocks and, all other values defines the number of system clock taht SCLK will be held low. - 12 - 4 + SDIO_DS + SDIO Drive Strength. This bit controls the drive strength of all SDIO pins. + 2 + 1 - 16_SCLK - 16 system clocks. + Low + Low drive strength. 0 + + High + High drive strength. + 1 + - SSACT - Slaves Select Activate Timing. - 16 + PU_PD_CTRL + IO Pullup/Pulldown Control. These bits control the pullups and pulldowns associated with all SPI XiP SDIO pins. + 3 2 - 0_CLKS - 0 sytem clocks. + tri_state + Tristate. 0 - 2_CLKS - 2 sytem clocks. + Pull_Up + Pull-Up. 1 - 4_CLKS - 4 sytem clocks. + Pull_down + Pull-Down. 2 - - 8_CLKS - 8 sytem clocks. - 3 - + + + + SEC_CTRL + SPIX Memory Security Control Register. + 0x20 + - SSIACT - Slaves Select Inactive Timing. - 18 - 2 + DEC_EN + Decryption Enable. + 0 + 1 - 4_CLKS - 4 sytem clocks. + dis + Disable decryption of SPIX data. 0 - 6_CLKS - 6 sytem clocks. + en + Enable decryption of SPIX data. 1 + + + + AUTH_DISABLE + Integrity Enable. + 1 + 1 + - 8_CLKS - 8 sytem clocks. - 2 + en + Integrity checking enabled. + 0 - 12_CLKS - 12 sytem clocks. - 3 + dis + Integrity checking disabled. + 1 + + + + BUS_IDLE + Bus Idle + 0x24 + - IOSMPL - Sample Delay - 20 - 4 + BUSIDLE + A 16-bit timer will be triggered for each external access. The timer will be + restarted if another access is performed before the timer expires. When the + timer expires, slave select will be deactivated. + 0 + 16 - SS_POL - SPIX Controller Slave Select Polarity Register. + AUTHOFFSET + Auth Offset + 0x28 + + + + + + SPI + SPI peripheral. + 0x40046000 + + 0x00 + 0x1000 + registers + + + SPI0 + 16 + + + + DATA32 + Register for reading and writing the FIFO. + 0x00 + 32 + read-write + + + QSPIFIFO + Read to pull from RX FIFO, write to put into TX FIFO. + 0 + 32 + + + + + 2 + 2 + DATA16[%s] + Register for reading and writing the FIFO. + DATA32 + 0x00 + 16 + read-write + + + QSPIFIFO + Read to pull from RX FIFO, write to put into TX FIFO. + 0 + 16 + + + + + 4 + 1 + DATA8[%s] + Register for reading and writing the FIFO. + DATA32 + 0x00 + 8 + read-write + + + QSPIFIFO + Read to pull from RX FIFO, write to put into TX FIFO. + 0 + 8 + + + + + CTRL0 + Register for controlling SPI peripheral. 0x04 + read-write - SSPOL_0 - Slave Select Polarity. + EN + SPI Enable. 0 1 - lo - Active Low. + dis + SPI is disabled. 0 - hi - Active High. + en + SPI is enabled. 1 - - - - GEN_CTRL - SPIX Controller General Controller Register. - 0x08 - - ENABLE - SPI Master enable. - 0 + MASTER + Master Mode Enable. + 1 1 dis - Disable SPI Master, putting a reset state. + SPI is Slave mode. 0 en - Enable SPI Master for processing transactions. + SPI is Master mode. 1 - TX_FIFO_EN - Transaction FIFO Enable. - 1 + SS_IO + Slave Select 0, IO direction, to support Multi-Master mode,Slave Select 0 can be input in Master mode. This bit has no effect in slave mode. + 4 1 - dis_txfifo - Disable Transaction FIFO. + output + Slave select 0 is output. 0 - en_txfifo - Enable Transaction FIFO. + input + Slave Select 0 is input, only valid if MMEN=1. 1 - RX_FIFO_EN - Result FIFO Enable. - 2 + START + Start Transmit. + 5 1 - dis_rxfifo - Disable Result FIFO. - 0 - - - en_rxfifo - Enable Result FIFO. + start + Master Initiates a transaction, this bit is self clearing when transactions are done. If a transaction cimpletes, and the TX FIFO is empty, the Master halts, if a transaction completes, and the TX FIFO is not empty, the Master initiates another transaction. 1 - BBMODE - Bit-Bang Mode. - 3 + SS_CTRL + Start Select Control. Used in Master mode to control the behavior of the Slave Select signal at the end of a transaction. + 8 1 - dis - Disable Bit-Bang Mode. + DEASSERT + SPI De-asserts Slave Select at the end of a transaction. 0 - en - Enable Bit-Bang Mode. + ASSERT + SPI leaves Slave Select asserted at the end of a transaction. 1 - SSDR - This bits reflects the state of the currently selected slave select. - 4 - 1 + SS + Slave Select, when in Master mode selects which Slave devices are selected. More than one Slave device can be selected. + 16 + 4 - output0 - Selected Slave select output = 0. - 0 + SS0 + SS0 is selected. + 0x1 - output1 - Selected Slave select output = 1. - 1 + SS1 + SS1 is selected. + 0x2 + + + SS2 + SS2 is selected. + 0x4 + + + SS3 + SS3 is selected. + 0x8 + + + + CTRL1 + Register for controlling SPI peripheral. + 0x08 + read-write + + + TX_NUM_CHAR + Nubmer of Characters to transmit. + 0 + 16 + - SCLK_DR - SSCLK Drive and State. - 6 + RX_NUM_CHAR + Nubmer of Characters to receive. + 16 + 16 + + + + + CTRL2 + Register for controlling SPI peripheral. + 0x0C + read-write + + + CPHA + Clock Phase. + 0 1 - SCLK_0 - SCLK is 0. + Rising_Edge + Data Sampled on clock rising edge. Use when in SPI Mode 0 and Mode 2 0 - SCLK_1 - SCLK is 1. + Falling_Edge + Data Sampled on clock falling edge. Use when in SPI Mode 1 and Mode 3 1 - SDIO_DATA_IN - SDIO Input Data Value. - 8 - 4 + CPOL + Clock Polarity. + 1 + 1 - SDIO0 - SDIO[0] + Normal + Normal Clock. Use when in SPI Mode 0 and Mode 1 0 - SDIO1 - SDIO[1] + Inverted + Inverted Clock. Use when in SPI Mode 2 and Mode 3 1 + + + + NUMBITS + Number of Bits per character. + 8 + 4 + - SDIO2 - SDIO[2] - 2 - - - SDIO3 - SDIO[3] - 3 + 0 + 16 bits per character. + 0 - BB_DATA - No description available. + DATA_WIDTH + SPI Data width. 12 - 4 + 2 - SDIO0 - SDIO[0] + Mono + 1 data pin. 0 - SDIO1 - SDIO[1] + Dual + 2 data pins. 1 - SDIO2 - SDIO[2] + Quad + 4 data pins. 2 - - SDIO3 - SDIO[3] - 3 - - BB_DATA_OUT_EN - Bit Bang SDIO Output Enable. - 16 - 4 + THREE_WIRE + Three Wire mode. MOSI/MISO pin(s) shared. Only Mono mode suports Four-Wire. + 15 + 1 - SDIO0 - SDIO[0] + dis + Use four wire mode (Mono only). 0 - SDIO1 - SDIO[1] + en + Use three wire mode. 1 - - SDIO2 - SDIO[2] - 2 - - - SDIO3 - SDIO[3] - 3 - - SIMPLE - Simple Mode Enable. - 20 - 1 - - - SIMPLE_RX - Simple Receive Enable. - 21 - 1 - - - SIMPLE_SS - Simple Mode Slave Select. - 22 - 1 - - - SCLK_FB - Enable SCLK Feedback Mode. - 24 - 1 + SS_POL + Slave Select Polarity, each Slave Select can have unique polarity. + 16 + 4 - dis - 0 + SS0_high + SS0 active high. + 0x1 - en - 1 + SS1_high + SS1 active high. + 0x2 + + + SS2_high + SS2 active high. + 0x4 + + + SS3_high + SS3 active high. + 0x8 - - SCLK_FB_INVERT - SCK Invert. - 25 - 1 - - FIFO_CTRL - SPIX Controller FIFO Control and Status Register. - 0x0C + SS_TIME + Register for controlling SPI peripheral/Slave Select Timing. + 0x10 + read-write - TX_FIFO_AE_LVL - Transaction FIFO Almost Empty Level. + PRE + Slave Select Pre delay 1. 0 - 4 + 8 + + + 256 + 256 system clocks between SS active and first serial clock edge. + 0 + + - TX_FIFO_CNT - Transaction FIFO Used. + POST + Slave Select Post delay 2. 8 - 5 + 8 + + + 256 + 256 system clocks between last serial clock edge and SS inactive. + 0 + + - RX_FIFO_AF_LVL - Results FIFO Almost Full Level. + INACT + Slave Select Inactive delay. 16 - 5 - - - RX_FIFO_CNT - Result FIFO Used. - 24 - 6 + 8 + + + 256 + 256 system clocks between transactions. + 0 + + - SP_CTRL - SPIX Controller Special Control Register. - 0x10 + CLK_CFG + Register for controlling SPI clock rate. + 0x14 + read-write - SAMPL - Setting this bit to a 1 enables the ability to drive SDIO outputs prior to the assertion of Slave Select. This bit must - only be set when the SPIXF bus is idle and the transaction FIFO is empty. This bit is automatically cleared by hardware after the - next slave select assertion. + LO + Low duty cycle control. In timer mode, reload[7:0]. 0 - 1 - - - SDIO_OUT - SDIO Output Value Sample Mode - 4 - 4 + 8 + + + Dis + Duty cycle control of serial clock generation is disabled. + 0 + + - SDIO_OUT_EN - SDIO Output Enable Sample Mode + HI + High duty cycle control. In timer mode, reload[15:8]. 8 - 4 - - - SCLKINH3 - SCLK Inhibit Mode3. In SPI Mode 3, some SPI flash read timing diagrams show the last SCLK going low prior to de-assertion. The default is to support this additional falling edge of clock. When this bit is set and the device is in SPI Mode 3, the SPI clock is held high while Slave Select is de-asserted. This is to support some SPI flash write timing diagrams. - 16 - 1 + 8 - EN - Allow trailing SCLK low pulse prior to Slave Select de-assertion. + Dis + Duty cycle control of serial clock generation is disabled. 0 - - DIS - Inhibit trailing SCLK low pulse prior to Slave Select de-assertion. - 1 - + + SCALE + System Clock scale factor. Scales the AMBA clock by 2^SCALE before generating serial clock. + 16 + 4 + - INT_FL - SPIX Controller Interrupt Status Register. - 0x14 + DMA + Register for controlling DMA. + 0x1C + read-write - TX_STALLED - Transaction Stalled Interrupt Flag. + TX_FIFO_LEVEL + Transmit FIFO level that will trigger a DMA request, also level for threshold status. When TX FIFO has fewer than this many bytes, the associated events and conditions are triggered. 0 + 5 + + + TX_FIFO_EN + Transmit FIFO enabled for SPI transactions. + 6 1 - CLR - Normal FIFO Transaction. + dis + Transmit FIFO is not enabled. 0 - SET - Stalled FIFO Transaction. + en + Transmit FIFO is enabled. 1 - RX_STALLED - Results Stalled Interrupt Flag. - 1 + TX_FIFO_CLEAR + Clear TX FIFO, clear is accomplished by resetting the read and write + pointers. This should be done when FIFO is not being accessed on the SPI side. + . + 7 1 - CLR - Normal FIFO Operation. - 0 - - - SET - Stalled FIFO. + CLEAR + Clear the Transmit FIFO, clears any pending TX FIFO status. 1 - TX_READY - Transaction Ready Interrupt Status. - 2 + TX_FIFO_CNT + Count of entries in TX FIFO. + 8 + 6 + read-only + + + TX_DMA_EN + TX DMA Enable. + 15 1 - CLR - FIFO Transaction not ready. + DIS + TX DMA requests are disabled, andy pending DMA requests are cleared. 0 - SET - FIFO Transaction ready. + en + TX DMA requests are enabled. 1 - RX_DONE - Results Done Interrupt Status. - 3 + RX_FIFO_LEVEL + Receive FIFO level that will trigger a DMA request, also level for threshold status. When RX FIFO has more than this many bytes, the associated events and conditions are triggered. + 16 + 5 + + + RX_FIFO_EN + Receive FIFO enabled for SPI transactions. + 22 1 - CLR - Results FIFO ready. + DIS + Receive FIFO is not enabled. 0 - SET - Results FIFO Not ready. + en + Receive FIFO is enabled. 1 - TX_FIFO_AE - Transaction FIFO Almost Empty Flag. - 4 + RX_FIFO_CLEAR + Clear RX FIFO, clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side. + 23 1 - CLR - Transaction FIFO not Almost Empty. - 0 - - - SET - Transaction FIFO Almost Empty. + CLEAR + Clear the Receive FIFO, clears any pending RX FIFO status. 1 - RX_FIFO_AF - Results FIFO Almost Full Flag. - 5 + RX_FIFO_CNT + Count of entries in RX FIFO. + 24 + 6 + read-only + + + RX_DMA_EN + RX DMA Enable. + 31 1 - CLR - Results FIFO level below the Almost Full level. + dis + RX DMA requests are disabled, any pending DMA requests are cleared. 0 - SET - Results FIFO level at Almost Full level. + en + RX DMA requests are enabled. 1 @@ -20475,644 +18907,418 @@ - INT_EN - SPIX Controller Interrupt Enable Register. - 0x18 + INT_FL + Register for reading and clearing interrupt flags. All bits are write 1 to clear. + 0x20 + read-write - TX_STALLED - Transaction Stalled Interrupt Enable. + TX_THRESH + TX FIFO Threshold Crossed. 0 1 - en - Disable Transaction Stalled Interrupt. - 0 - - - dis - Enable Transaction Stalled Interrupt. + clear + Flag is set when value read is 1. Write 1 to clear this flag. 1 - RX_STALLED - Results Stalled Interrupt Enable. + TX_EMPTY + TX FIFO Empty. 1 1 - en - Disable Results Stalled Interrupt. - 0 - - - dis - Enable Results Stalled Interrupt. + clear + Flag is set when value read is 1. Write 1 to clear this flag. 1 - TX_READY - Transaction Ready Interrupt Enable. + RX_THRESH + RX FIFO Threshold Crossed. 2 1 - en - Disable FIFO Transaction Ready Interrupt. - 0 - - - dis - Enable FIFO Transaction Ready Interrupt. + clear + Flag is set when value read is 1. Write 1 to clear this flag. 1 - RX_DONE - Results Done Interrupt Enable. + RX_FULL + RX FIFO FULL. 3 1 - en - Disable Results Done Interrupt. - 0 - - - dis - Enable Results Done Interrupt. + clear + Flag is set when value read is 1. Write 1 to clear this flag. 1 - TX_FIFO_AE - Transaction FIFO Almost Empty Interrupt Enable. + SSA + Slave Select Asserted. 4 1 - en - Disable Transaction FIFO Almost Empty Interrupt. - 0 - - - dis - Enable Transaction FIFO Almost Empty Interrupt. + clear + Flag is set when value read is 1. Write 1 to clear this flag. 1 - RX_FIFO_AF - Results FIFO Almost Full Interrupt Enable. + SSD + Slave Select Deasserted. 5 1 - en - Disable Results FIFO Almost Full Interrupt. - 0 - - - dis - Enable Results FIFO Almost Full Interrupt. + clear + Flag is set when value read is 1. Write 1 to clear this flag. 1 - - - - - - - SPIXFC_FIFO - SPI XiP Master Controller FIFO. - 0x400BC000 - - 0 - 0x1000 - registers - - - - TX_8 - SPI TX FIFO 8-Bit Write - 0x00 - 8 - uint8_t - - - TX_16 - SPI TX FIFO 16-Bit Write - TX_8 - 0x00 - 16 - uint16_t - - - TX_32 - SPI TX FIFO 32-Bit Write - TX_8 - 0x00 - 32 - uint32_t - - - RX_8 - SPI RX FIFO 8-Bit Access - 0x04 - 8 - uint8_t - - - RX_16 - SPI RX FIFO 16-Bit Access - RX_8 - 0x04 - 16 - uint16_t - - - RX_32 - SPI RX FIFO 32-Bit Access - RX_8 - 0x04 - 32 - uint32_t - - - - - - SPIXFM - SPIXF Master - 0x40026000 - - 0x00 - 0x1000 - registers - - - - CFG - SPIX Configuration Register. - 0x00 - - MODE - Defines SPI Mode, Only valid values are 0 and 3. - 0 - 2 + FAULT + Multi-Master Mode Fault. + 8 + 1 - SCLK_HI_SAMPLE_RISING - Description not available. - 0 - - - SCLK_LO_SAMPLE_FAILLING - Description not available. - 3 + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 - SSPOL - Slave Select Polarity. - 2 + ABORT + Slave Abort Detected. + 9 1 - ACTIVE_HIGH - Slave Select is Active High. - 0 - - - ACTIVE_LOW - Slave Select is Active Low. + clear + Flag is set when value read is 1. Write 1 to clear this flag. 1 - SSEL - Slave Select. Only valid value is zero. - 4 - 3 - - - LO_CLK - Number of system clocks that SCLK will be low when SCLK pulses are generated. - 8 - 4 + M_DONE + Master Done, set when SPI Master has completed any transactions. + 11 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + - HI_CLK - Number of system clocks that SCLK will be high when SCLK pulses are generated. + TX_OVR + Transmit FIFO Overrun, set when the AMBA side attempts to write data to a full transmit FIFO. 12 - 4 - - - SSACT - Slave Select Active Timing. - 16 - 2 + 1 - off - 0 system clocks. - 0 - - - for_2_mod_clk - 2 System clocks. + clear + Flag is set when value read is 1. Write 1 to clear this flag. 1 + + + + TX_UND + Transmit FIFO Underrun, set when the SPI side attempts to read data from an empty transmit FIFO. + 13 + 1 + - for_4_mod_clk - 4 System clocks. - 2 + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + RX_OVR + Receive FIFO Overrun, set when the SPI side attempts to write to a full receive FIFO. + 14 + 1 + - for_8_mod_clk - 8 System clocks. - 3 + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 - SSIACT - Slave Select Inactive Timing. - 18 - 2 + RX_UND + Receive FIFO Underrun, set when the AMBA side attempts to read data from an empty receive FIFO. + 15 + 1 - for_1_mod_clk - 1 system clocks. - 0 - - - for_3_mod_clk - 3 System clocks. + clear + Flag is set when value read is 1. Write 1 to clear this flag. 1 - - for_5_mod_clk - 5 System clocks. - 2 - - - for_9_mod_clk - 9 System clocks. - 3 - - FETCH_CTRL - SPIX Fetch Control Register. - 0x04 + INT_EN + Register for enabling interrupts. + 0x24 + read-write - CMDVAL - Command Value sent to target to initiate fetching from SPI flash. + TX_THRESH + TX FIFO Threshold interrupt enable. 0 - 8 - - - CMD_WIDTH - Command Width. Number of data I/O used to send commands. - 8 - 2 + 1 - Single - Single SDIO. + dis + Interrupt is disabled. 0 - Dual_IO - Dual SDIO. + en + Interrupt is enabled. 1 - - Quad_IO - Quad SDIO. - 2 - - - Invalid - Invalid. - 3 - - ADDR_WIDTH - Address Width. Number of data I/O used to send address, and mode/dummy clocks. - 10 - 2 + TX_EMPTY + TX FIFO Empty interrupt enable. + 1 + 1 - Single - Single SDIO. + dis + Interrupt is disabled. 0 - Dual_IO - Dual SDIO. + en + Interrupt is enabled. 1 - - Quad_IO - Quad SDIO. - 2 - - - Invalid - Invalid. - 3 - - DATA_WIDTH - Data Width. Number of data I/O used to receive data. - 12 - 2 + RX_THRESH + RX FIFO Threshold Crossed interrupt enable. + 2 + 1 - Single - Single SDIO. + dis + Interrupt is disabled. 0 - Dual_IO - Dual SDIO. + en + Interrupt is enabled. 1 - - Quad_IO - Quad SDIO. - 2 - - - Invalid - Invalid. - 3 - - FOUR_BYTE_ADDR - Four Byte Address Mode. Enables 4-byte Flash Address Mode. - 16 + RX_FULL + RX FIFO FULL interrupt enable. + 3 1 - 3 - 3 Byte Address Mode. + dis + Interrupt is disabled. 0 - 4 - 4 Byte Address Mode. + en + Interrupt is enabled. 1 - - - - MODE_CTRL - SPIX Mode Control Register. - 0x08 - - - MDCLK - Mode Clocks. Number of SPI clocks needed during mode/dummy phase of fetch. - 0 - 4 - - NO_CMD - No Command Mode. - 8 + SSA + Slave Select Asserted interrupt enable. + 4 1 - always - Send read command every time SPI transaction is initiated. + dis + Interrupt is disabled. 0 - once - Send read command only once. NO read command in subsequent SPI transactions. + en + Interrupt is enabled. 1 - MODE_SEND - Mode Send. - 9 - 1 - - - - - MODE_DATA - SPIX Mode Data Register. - 0x0C - - - DATA - Mode Data. Specifies the data to send with the Dummy/Mode clocks. - 0 - 16 - - - OUT_EN - Mode Output Enable. Output enable state for each corresponding data bit in MD_DATA. 0: output enable off, I/O is tristate and 1: Output enable on, I/O is driving MD_DATA. - 16 - 16 - - - - - FB_CTRL - SPIX Feedback Control Register. - 0x10 - - - FB_EN - Enable SCLK feedback mode. - 0 + SSD + Slave Select Deasserted interrupt enable. + 5 1 dis - Disable SCLK feedback mode. + Interrupt is disabled. 0 en - Enable SCLK feedback mode. + Interrupt is enabled. 1 - INVERT_EN - Invert SCLK in feedback mode. - 1 + FAULT + Multi-Master Mode Fault interrupt enable. + 8 1 dis - Disable Invert SCLK feedback mode. + Interrupt is disabled. 0 en - Enable Invert SCLK feedback mode. + Interrupt is enabled. 1 - - - - IO_CTRL - SPIX IO Control Register. - 0x1C - - SCLK_DS - SCLK drive Strength. This bit controls the drive strength on the SCLK pin. - 0 + ABORT + Slave Abort Detected interrupt enable. + 9 1 - Low - Low drive strength. + dis + Interrupt is disabled. 0 - High - High drive strength. + en + Interrupt is enabled. 1 - SS_DS - Slave Select Drive Strength. This bit controls the drive strength on the dedicated slave select pin. - 1 + M_DONE + Master Done interrupt enable. + 11 1 - Low - Low drive strength. + dis + Interrupt is disabled. 0 - High - High drive strength. + en + Interrupt is enabled. 1 - SDIO_DS - SDIO Drive Strength. This bit controls the drive strength of all SDIO pins. - 2 + TX_OVR + Transmit FIFO Overrun interrupt enable. + 12 1 - Low - Low drive strength. + dis + Interrupt is disabled. 0 - High - High drive strength. + en + Interrupt is enabled. 1 - PU_PD_CTRL - IO Pullup/Pulldown Control. These bits control the pullups and pulldowns associated with all SPI XiP SDIO pins. - 3 - 2 + TX_UND + Transmit FIFO Underrun interrupt enable. + 13 + 1 - tri_state - Tristate. + dis + Interrupt is disabled. 0 - Pull_Up - Pull-Up. + en + Interrupt is enabled. 1 - - Pull_down - Pull-Down. - 2 - - - - - SEC_CTRL - SPIX Memory Security Control Register. - 0x20 - - DEC_EN - Decryption Enable. - 0 + RX_OVR + Receive FIFO Overrun interrupt enable. + 14 1 dis - Disable decryption of SPIX data. + Interrupt is disabled. 0 en - Enable decryption of SPIX data. + Interrupt is enabled. 1 - AUTH_DISABLE - Integrity Enable. - 1 + RX_UND + Receive FIFO Underrun interrupt enable. + 15 1 - en - Integrity checking enabled. + dis + Interrupt is disabled. 0 - dis - Integrity checking disabled. + en + Interrupt is enabled. 1 @@ -21120,158 +19326,139 @@ - BUS_IDLE - Bus Idle - 0x24 - - - BUSIDLE - A 16-bit timer will be triggered for each external access. The timer will be - restarted if another access is performed before the timer expires. When the - timer expires, slave select will be deactivated. - 0 - 16 - - - - - AUTHOFFSET - Auth Offset + WAKE_FL + Register for wake up flags. All bits in this register are write 1 to clear. 0x28 - - - - - - SRCC - SPIX Cache Controller Registers. - 0x40033000 - - 0x00 - 0x1000 - registers - - - - CACHE_ID - Cache ID Register. - 0x0000 - read-only + read-write - RELNUM - Release Number. Identifies the RTL release version. + TX_THRESH + Wake on TX FIFO Threshold Crossed. 0 - 6 - - - PARTNUM - Part Number. This field reflects the value of C_ID_PART_NUMBER configuration parameter. - 6 - 4 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + - CCHID - Cache ID. This field reflects the value of the C_ID_CACHEID configuration parameter. - 10 - 6 + TX_EMPTY + Wake on TX FIFO Empty. + 1 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + - - - - MEMCFG - Memory Configuration Register. - 0x0004 - read-only - 0x00080008 - - CCHSZ - Cache Size. Indicates total size in Kbytes of cache. - 0 - 16 + RX_THRESH + Wake on RX FIFO Threshold Crossed. + 2 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + - MEMSZ - Main Memory Size. Indicates the total size, in units of 128 Kbytes, of code memory accessible to the cache controller. - 16 - 16 + RX_FULL + Wake on RX FIFO Full. + 3 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + - CACHE_CTRL - Cache Control and Status Register. - 0x0100 + WAKE_EN + Register for wake up enable. + 0x2C + read-write - CACHE_EN - Cache Enable. Controls whether the cache is bypassed or is in use. Changing the state of this bit will cause the instruction cache to be flushed and its contents invalidated. + TX_THRESH + Wake on TX FIFO Threshold Crossed Enable. 0 1 dis - Cache Bypassed. Instruction data is stored in the line fill buffer but is not written to main cache memory array. + Wakeup source disabled. 0 en - Cache Enabled. + Wakeup source enabled. 1 - WRITE_ALLOC_EN - Write Allocate Enable. This bit only writable while the cache is disabled. + TX_EMPTY + Wake on TX FIFO Empty Enable. 1 1 dis - Write-no-allocate. + Wakeup source disabled. 0 en - Write-allocate enabled. + Wakeup source enabled. 1 - CWFST_DIS - Critical word first and streaming disable. This bit only writeable while the cache is disabled. + RX_THRESH + Wake on RX FIFO Threshold Crossed Enable. 2 1 dis - Critical word first and streaming disabled. - 1 + Wakeup source disabled. + 0 en - Critical word first and streaming enabled. - 0 + Wakeup source enabled. + 1 - CACHE_RDY - Cache Ready flag. Cleared by hardware when at any time the cache as a whole is invalidated (including a system reset). When this bit is 0, the cache is effectively in bypass mode (instruction fetches will come from main memory or from the line fill buffer). Set by hardware when the invalidate operation is complete and the cache is ready. - 16 + RX_FULL + Wake on RX FIFO Full Enable. + 3 1 - notReady - Not Ready. + dis + Wakeup source disabled. 0 - ready - Ready. + en + Wakeup source enabled. 1 @@ -21279,21 +19466,56 @@ - INVALIDATE - Invalidate All Cache Contents. Any time this register location is written (regardless of the data value), the cache controller immediately begins invalidating the entire contents of the cache memory. The cache will be in bypass mode until the invalidate operation is complete. System software can examine the Cache Ready bit (CACHE_CTRL.CACHE_RDY) to determine when the invalidate operation is complete. Note that it is not necessary to disable the cache controller prior to beginning this operation. Reads from this register always return 0. - 0x0700 + STAT + SPI Status register. + 0x30 + read-only - IA - Invalidate all cache contents. + BUSY + SPI active status. In Master mode, set when transaction starts, cleared when last bit of last character is acted upon and Slave Select de-assertion would occur. In Slave mode, set when Slave Select is asserted, cleared when Slave Select is de-asserted. Not used in Timer mode. 0 - 32 + 1 + + + not + SPI not active. + 0 + + + active + SPI active. + 1 + + - + + + SPI1 + SPI peripheral. 1 + 0x40047000 + + SPI1 + SPI1 IRQ + 17 + + + + + SPI2 + SPI peripheral. 2 + 0x40048000 + + SPI2 + SPI2 IRQ + 18 + + + TMR0 32-bit reloadable timer that can be used for timing and event counting. @@ -21635,36 +19857,6 @@ - - TRIMSIR - Trim System Initilazation Registers - 0x40005400 - - 0x00 - 0x400 - registers - - - - rsv0 - RFU - 0x00 - - - BB_SIR2 - System Init. Configuration Register 2. - 0x08 - read-only - - - BB_SIR3 - System Init. Configuration Register 3. - 0x0C - read-only - - - - TRNG Random Number Generator. @@ -21681,73 +19873,91 @@ - CN + CTRL TRNG Control Register. 0x00 0x00000003 - RND_IRQ_EN + ODHT + On Demand Health Test. + 0 + 1 + + + RND_IE To enable IRQ generation when a new 32-bit Random number is ready. 1 1 - - - disable - Disable - 0 - - - enable - Enable - 1 - - - AESKG - AES Key Generate. + HEALTH_EN + Health Test Enable. + 2 + 1 + + + AESKG_USR + User block AES Key Gen. 3 1 - AESKG_MEMPROTE - AES Key Generate. When enabled, the key for securing NVSRAM is generated and transferred to the secure key register automatically without user visibility or intervention. This bit is cleared by hardware once the key has been transferred to the secure key register. + AESKG_SYS + System block AES Key Gen. 4 1 + + KEYWIPE + Wipe Key. + 15 + 1 + - ST + STATUS Data. The content of this register is valid only when RNG_IS = 1. When TRNG is disabled, read returns 0x0000 0000. 0x04 read-only - RND_RDY + RDY 32-bit random data is ready to read from TRNG_DATA register. Reading TRNG_DATA when RND_RDY=0 will return all 0's. IRQ is generated when RND_RDY=1 if TRNG_CN.RND_IRQ_EN=1. 0 1 - - - Busy - TRNG Busy - 0 - - - Ready - 32 bit random data is ready - 1 - - - AESKGD_MEU_S - Automatically AES transfer on going + ODHT + On demand health test. + 1 + 1 + + + HT + Health test status. + 2 + 1 + + + SRCFAIL + Source Fail. + 3 + 1 + + + AESKGD + AES Key Gen Status. 4 1 + + LD_CNT + Load Count. + 24 + 8 + @@ -23447,25 +21657,6 @@ - - DMAREQEN - DMA Request Enable - 4 - 1 - read-write - - - dis - Disable DMA for this IN endpoint. - 0 - - - en - Enable DMA for this IN endpoint. - 1 - - - FRCDATATOG Force In Data - Toggle @@ -23485,25 +21676,6 @@ - - DMAREQMODE - DMA Request Mode Enable - 2 - 1 - read-write - - - 0 - Enable DMA Request Mode 0. - 0 - - - 1 - Enable DMA Request Mode 1. - 1 - - - DPKTBUFDIS Double Packet Buffering Disable @@ -23619,24 +21791,12 @@ 1 read-write - - DMAREQEN - 5 - 1 - read-write - DISNYET 4 1 read-write - - DMAREQMODE - 3 - 1 - read-write - DPKTBUFDIS 1 @@ -23926,16 +22086,10 @@ RAMINFO - RAM width and DMA hardware information. + RAM width information. 0x79 8 - - DMACHANS - 4 - 4 - read-only - RAMBITS 0 @@ -23964,26 +22118,6 @@ - - EARLYDMA - DMA timing control register. - 0x7B - 8 - - - EDMAIN - 1 - 1 - read-write - - - EDMAOUT - 0 - 1 - read-write - - - CTUCH Chirp timeout timer setting. @@ -24259,41 +22393,123 @@ 0 1 + + + + + + + WDT0 + Watchdog Timer 0 + 0x40003000 + + 0x00 + 0x0400 + registers + + + WDT0 + 1 + + + + CTRL + Watchdog Timer Control Register. + 0x00 + 0x7FFFF000 + - DMA_INT - DMA_INT - 1 - 1 + INT_PERIOD + Watchdog Interrupt Period. The watchdog timer will assert an interrupt, if enabled, if the CPU does not write the watchdog reset sequence to the WDT_RST register before the watchdog timer has counted this time period since the last timer reset. + 0 + 4 + + + wdt2pow31 + 2**31 clock cycles. + 0 + + + wdt2pow30 + 2**30 clock cycles. + 1 + + + wdt2pow29 + 2**29 clock cycles. + 2 + + + wdt2pow28 + 2**28 clock cycles. + 3 + + + wdt2pow27 + 2^27 clock cycles. + 4 + + + wdt2pow26 + 2**26 clock cycles. + 5 + + + wdt2pow25 + 2**25 clock cycles. + 6 + + + wdt2pow24 + 2**24 clock cycles. + 7 + + + wdt2pow23 + 2**23 clock cycles. + 8 + + + wdt2pow22 + 2**22 clock cycles. + 9 + + + wdt2pow21 + 2**21 clock cycles. + 10 + + + wdt2pow20 + 2**20 clock cycles. + 11 + + + wdt2pow19 + 2**19 clock cycles. + 12 + + + wdt2pow18 + 2**18 clock cycles. + 13 + + + wdt2pow17 + 2**17 clock cycles. + 14 + + + wdt2pow16 + 2**16 clock cycles. + 15 + + - - - - - - - WDT0 - Watchdog Timer 0 - 0x40003000 - - 0x00 - 0x0400 - registers - - - WDT0 - 1 - - - - CTRL - Watchdog Timer Control Register. - 0x00 - 0x7FFFF000 - - INT_PERIOD - Watchdog Interrupt Period. The watchdog timer will assert an interrupt, if enabled, if the CPU does not write the watchdog reset sequence to the WDT_RST register before the watchdog timer has counted this time period since the last timer reset. - 0 + RST_PERIOD + Watchdog Reset Period. The watchdog timer will assert a reset, if enabled, if the CPU does not write the watchdog reset sequence to the WDT_RST register before the watchdog timer has counted this time period since the last timer reset. + 4 4 @@ -24379,117 +22595,339 @@ - RST_PERIOD - Watchdog Reset Period. The watchdog timer will assert a reset, if enabled, if the CPU does not write the watchdog reset sequence to the WDT_RST register before the watchdog timer has counted this time period since the last timer reset. - 4 - 4 + WDT_EN + Watchdog Timer Enable. + 8 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + INT_FLAG + Watchdog Timer Interrupt Flag. + 9 + 1 + oneToClear + + + inactive + No interrupt is pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + INT_EN + Watchdog Timer Interrupt Enable. + 10 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + RST_EN + Watchdog Timer Reset Enable. + 11 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + RST_FLAG + Watchdog Timer Reset Flag. + 31 + 1 + + read-write + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + + + RST + Watchdog Timer Reset Register. + 0x04 + write-only + + + WDT_RST + Writing the watchdog counter 'reset sequence' to this register resets the watchdog counter. If the watchdog count exceeds INT_PERIOD then a watchdog interrupt will occur, if enabled. If the watchdog count exceeds RST_PERIOD then a watchdog reset will occur, if enabled. + 0 + 8 + + + seq0 + The first value to be written to reset the WDT. + 0x000000A5 + + + seq1 + The second value to be written to reset the WDT. + 0x0000005A + + + + + + + + + + WDT1 + Watchdog Timer 0 1 + 0x40003400 + + WDT1 + WDT1 IRQ + 57 + + + + + SKBD + Secure Keyboard + 0x40032000 + + 0x00 + 0x1000 + registers + + + Secure_Keypad + Secure Keypad interrupt + 19 + + + + CR0 + Input Output Select Bits. Each bit of IOSEL selects the pin direction for the corresponding KBDIO pin. If IOSEL[0] = 1, KBDIO0 is an output. + 0x00 + + + KBDIO_0 + Input Output Select for KBDIO0 pin. + 0 + 10 + + + input + Input + 0 + + + output + Output + 1 + + + + + + + CR1 + Control Register 1 + 0x04 + + + AUTOEN + Automatic Keyboard Scan Enable + 0 + 1 + + + disable + Disable + 0 + + + enable + Enable + 1 + + + + + CLEAR + Auto Clear Bit + 1 + 1 + + + OUTNB + Output Number. Number of KBDIO pins selected as outputs. NOTE: + Output pins must be allocated contiguously starting with KBDIO0 and continuing through to KBDIO7. + 8 + 3 + + + DBTM + Debounce Time. Number of milliseconds a keypress event must be active before it is considered actual. NOTE: + Debounce time values based on system running from an external 12MHz clock source with PLL0 enabled. Other external crystal values will cause the debounce time to scale linearly. + 13 + 3 - wdt2pow31 - 2**31 clock cycles. + time4ms + 4.1 ms 0 - wdt2pow30 - 2**30 clock cycles. + time5ms + 5.3 ms 1 - wdt2pow29 - 2**29 clock cycles. + time6ms + 6.5 ms 2 - wdt2pow28 - 2**28 clock cycles. + time7ms + 7.6 ms 3 - wdt2pow27 - 2^27 clock cycles. + time8ms + 8.8 ms 4 - wdt2pow26 - 2**26 clock cycles. + time10ms + 10.0 ms 5 - wdt2pow25 - 2**25 clock cycles. + time11ms + 11.2 ms 6 - wdt2pow24 - 2**24 clock cycles. + time12ms + 12.3 ms 7 + + + + + + SR + Status Register + 0x08 + read-only + + + BUSY + Busy bit. This bit is set by hardware when the automatic keyboard scan is enabled and running. This bit is clear at all other times. + 0 + 1 + - wdt2pow23 - 2**23 clock cycles. - 8 - - - wdt2pow22 - 2**22 clock cycles. - 9 - - - wdt2pow21 - 2**21 clock cycles. - 10 - - - wdt2pow20 - 2**20 clock cycles. - 11 - - - wdt2pow19 - 2**19 clock cycles. - 12 - - - wdt2pow18 - 2**18 clock cycles. - 13 - - - wdt2pow17 - 2**17 clock cycles. - 14 + idle + Idle + 0 - wdt2pow16 - 2**16 clock cycles. - 15 + busy + Busy + 1 + + + + IER + Interrupt Enable Register + 0x0C + - WDT_EN - Watchdog Timer Enable. - 8 + PUSHIE + Push Event Enable Bit. When set, this bit enables an interrupt to be generated on a key push event. Automatic keyboard scan must be enabled. + 0 1 - dis - Disable. + disable + Disable 0 - en - Enable. + enable + Enable 1 + + RELEASEIE + Release Event Enable Bit. When set, this bit enables an interrupt to be generated on a key release event. Automatic keyboard scan must be enabled. + 1 + 1 + + + OVERIE + Overrun Event Enable Bit. When set, this bit enables an interrupt to be generated on an overrun event. Automatic keyboard scan must be enabled. + 2 + 1 + + + + + ISR + Interrupt Status Register + 0x10 + - INT_FLAG - Watchdog Timer Interrupt Flag. - 9 + PUSHIS + Push Interrupt Flag. This bit is set by hardware when a key has been pushed. If the interrupt is enabled for this flag, a system interrupt will be fired. If the interrupt enable is not set, the flag will be set, but no interrupt will fire. This bit must be cleared by software. + 0 1 - oneToClear inactive @@ -24503,102 +22941,99 @@ + + RELEASEIS + Release Interrupt Flag. This bit is set by hardware when a key has been released. If the interrupt is enabled for this flag, a system interrupt will be fired. If the interrupt enable is not set, the flag will be set, but no interrupt will fire. This bit must be cleared by software. + 1 + 1 + + + OVERIS + Overrun Event Enable Bit. This bit is set by hardware when an overrun event has occurred. If the interrupt is enabled for this flag, a system interrupt will be fired. If the interrupt enable is not set, the flag will be set, but no interrupt will fire. This bit must be cleared by software. + 2 + 1 + + + + + 4 + 4 + EVENT[%s] + Key Register + 0x14 + read-only + 0x00000C00 + + + IOIN + IO Input. Input pin of key event. + 0 + 3 + - INT_EN - Watchdog Timer Interrupt Enable. + IOOUT + IO Output. Output pin of key event. + 5 + 3 + + + PUSH + If set to 1 the key has been released. If set to 0 the key has been pushed. 10 1 - dis - Disable. + pushed + Pushed 0 - en - Enable. + released + Released 1 - RST_EN - Watchdog Timer Reset Enable. + READ + If set to 1 this register has been read. If set to 0 the key register has not been read since its last change. 11 1 - dis - Disable. + notRead + This register has not been read since its last change. 0 - en - Enable. + read + This register has been read. 1 - RST_FLAG - Watchdog Timer Reset Flag. - 31 + NEXT + If set to 1 one of the next key registers (x+1 to 3) contains a key event. + 12 1 - read-write - noEvent - The event has not occurred. + none + No more key register contain a key event. 0 - occurred - The event has occurred. + more + Other key registers contain a key event. 1 - - RST - Watchdog Timer Reset Register. - 0x04 - write-only - - - WDT_RST - Writing the watchdog counter 'reset sequence' to this register resets the watchdog counter. If the watchdog count exceeds INT_PERIOD then a watchdog interrupt will occur, if enabled. If the watchdog count exceeds RST_PERIOD then a watchdog reset will occur, if enabled. - 0 - 8 - - - seq0 - The first value to be written to reset the WDT. - 0x000000A5 - - - seq1 - The second value to be written to reset the WDT. - 0x0000005A - - - - - - - - WDT1 - Watchdog Timer 0 1 - 0x40003400 - - WDT1 - WDT1 IRQ - 57 - - - + diff --git a/Libraries/CMSIS/Device/Maxim/MAX32570/Include/mcr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32570/Include/mcr_regs.h index 3190537c26a..269653989bd 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32570/Include/mcr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32570/Include/mcr_regs.h @@ -2,25 +2,18 @@ * @file mcr_regs.h * @brief Registers, Bit Masks and Bit Positions for the MCR Peripheral Module. * @note This file is @generated. + * @ingroup mcr_registers */ /****************************************************************************** * - * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by - * Analog Devices, Inc.), - * Copyright (C) 2023-2024 Analog Devices, Inc. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at +/****************************************************************************** * - * http://www.apache.org/licenses/LICENSE-2.0 + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. All Rights Reserved. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. + * This software is proprietary to Analog Devices, Inc. and its licensors. * ******************************************************************************/ @@ -49,7 +42,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32570/Include/owm_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32570/Include/owm_regs.h index 2ee08fdffeb..f8826a56be2 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32570/Include/owm_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32570/Include/owm_regs.h @@ -2,25 +2,18 @@ * @file owm_regs.h * @brief Registers, Bit Masks and Bit Positions for the OWM Peripheral Module. * @note This file is @generated. + * @ingroup owm_registers */ /****************************************************************************** * - * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by - * Analog Devices, Inc.), - * Copyright (C) 2023-2024 Analog Devices, Inc. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at +/****************************************************************************** * - * http://www.apache.org/licenses/LICENSE-2.0 + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. All Rights Reserved. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. + * This software is proprietary to Analog Devices, Inc. and its licensors. * ******************************************************************************/ @@ -49,7 +42,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32570/Include/pt_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32570/Include/pt_regs.h index b6d6320c3a9..aa85c2bda9f 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32570/Include/pt_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32570/Include/pt_regs.h @@ -2,25 +2,18 @@ * @file pt_regs.h * @brief Registers, Bit Masks and Bit Positions for the PT Peripheral Module. * @note This file is @generated. + * @ingroup pt_registers */ /****************************************************************************** * - * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by - * Analog Devices, Inc.), - * Copyright (C) 2023-2024 Analog Devices, Inc. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at +/****************************************************************************** * - * http://www.apache.org/licenses/LICENSE-2.0 + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. All Rights Reserved. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. + * This software is proprietary to Analog Devices, Inc. and its licensors. * ******************************************************************************/ @@ -49,7 +42,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32570/Include/ptg_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32570/Include/ptg_regs.h index 52b750da5d4..eefdb2b48a4 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32570/Include/ptg_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32570/Include/ptg_regs.h @@ -2,25 +2,18 @@ * @file ptg_regs.h * @brief Registers, Bit Masks and Bit Positions for the PTG Peripheral Module. * @note This file is @generated. + * @ingroup ptg_registers */ /****************************************************************************** * - * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by - * Analog Devices, Inc.), - * Copyright (C) 2023-2024 Analog Devices, Inc. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at +/****************************************************************************** * - * http://www.apache.org/licenses/LICENSE-2.0 + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. All Rights Reserved. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. + * This software is proprietary to Analog Devices, Inc. and its licensors. * ******************************************************************************/ @@ -49,7 +42,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile @@ -79,6 +76,8 @@ typedef struct { __IO uint32_t inten; /**< \b 0x000C: PTG INTEN Register */ __O uint32_t safe_en; /**< \b 0x0010: PTG SAFE_EN Register */ __O uint32_t safe_dis; /**< \b 0x0014: PTG SAFE_DIS Register */ + __IO uint32_t ready_intfl; /**< \b 0x0018: PTG READY_INTFL Register */ + __IO uint32_t ready_inten; /**< \b 0x001C: PTG READY_INTEN Register */ } mxc_ptg_regs_t; /* Register offsets for module PTG */ @@ -94,6 +93,8 @@ typedef struct { #define MXC_R_PTG_INTEN ((uint32_t)0x0000000CUL) /**< Offset from PTG Base Address: 0x000C */ #define MXC_R_PTG_SAFE_EN ((uint32_t)0x00000010UL) /**< Offset from PTG Base Address: 0x0010 */ #define MXC_R_PTG_SAFE_DIS ((uint32_t)0x00000014UL) /**< Offset from PTG Base Address: 0x0014 */ +#define MXC_R_PTG_READY_INTFL ((uint32_t)0x00000018UL) /**< Offset from PTG Base Address: 0x0018 */ +#define MXC_R_PTG_READY_INTEN ((uint32_t)0x0000001CUL) /**< Offset from PTG Base Address: 0x001C */ /**@} end of group ptg_registers */ /** @@ -288,6 +289,70 @@ typedef struct { /**@} end of group PTG_SAFE_DIS_Register */ +/** + * @ingroup ptg_registers + * @defgroup PTG_READY_INTFL PTG_READY_INTFL + * @brief Pulse Train Ready Interrupt Flags + * @{ + */ +#define MXC_F_PTG_READY_INTFL_PT0_POS 0 /**< READY_INTFL_PT0 Position */ +#define MXC_F_PTG_READY_INTFL_PT0 ((uint32_t)(0x1UL << MXC_F_PTG_READY_INTFL_PT0_POS)) /**< READY_INTFL_PT0 Mask */ + +#define MXC_F_PTG_READY_INTFL_PT1_POS 1 /**< READY_INTFL_PT1 Position */ +#define MXC_F_PTG_READY_INTFL_PT1 ((uint32_t)(0x1UL << MXC_F_PTG_READY_INTFL_PT1_POS)) /**< READY_INTFL_PT1 Mask */ + +#define MXC_F_PTG_READY_INTFL_PT2_POS 2 /**< READY_INTFL_PT2 Position */ +#define MXC_F_PTG_READY_INTFL_PT2 ((uint32_t)(0x1UL << MXC_F_PTG_READY_INTFL_PT2_POS)) /**< READY_INTFL_PT2 Mask */ + +#define MXC_F_PTG_READY_INTFL_PT3_POS 3 /**< READY_INTFL_PT3 Position */ +#define MXC_F_PTG_READY_INTFL_PT3 ((uint32_t)(0x1UL << MXC_F_PTG_READY_INTFL_PT3_POS)) /**< READY_INTFL_PT3 Mask */ + +#define MXC_F_PTG_READY_INTFL_PT4_POS 4 /**< READY_INTFL_PT4 Position */ +#define MXC_F_PTG_READY_INTFL_PT4 ((uint32_t)(0x1UL << MXC_F_PTG_READY_INTFL_PT4_POS)) /**< READY_INTFL_PT4 Mask */ + +#define MXC_F_PTG_READY_INTFL_PT5_POS 5 /**< READY_INTFL_PT5 Position */ +#define MXC_F_PTG_READY_INTFL_PT5 ((uint32_t)(0x1UL << MXC_F_PTG_READY_INTFL_PT5_POS)) /**< READY_INTFL_PT5 Mask */ + +#define MXC_F_PTG_READY_INTFL_PT6_POS 6 /**< READY_INTFL_PT6 Position */ +#define MXC_F_PTG_READY_INTFL_PT6 ((uint32_t)(0x1UL << MXC_F_PTG_READY_INTFL_PT6_POS)) /**< READY_INTFL_PT6 Mask */ + +#define MXC_F_PTG_READY_INTFL_PT7_POS 7 /**< READY_INTFL_PT7 Position */ +#define MXC_F_PTG_READY_INTFL_PT7 ((uint32_t)(0x1UL << MXC_F_PTG_READY_INTFL_PT7_POS)) /**< READY_INTFL_PT7 Mask */ + +/**@} end of group PTG_READY_INTFL_Register */ + +/** + * @ingroup ptg_registers + * @defgroup PTG_READY_INTEN PTG_READY_INTEN + * @brief Pulse Train Ready Interrupt Enable/Disable + * @{ + */ +#define MXC_F_PTG_READY_INTEN_PT0_POS 0 /**< READY_INTEN_PT0 Position */ +#define MXC_F_PTG_READY_INTEN_PT0 ((uint32_t)(0x1UL << MXC_F_PTG_READY_INTEN_PT0_POS)) /**< READY_INTEN_PT0 Mask */ + +#define MXC_F_PTG_READY_INTEN_PT1_POS 1 /**< READY_INTEN_PT1 Position */ +#define MXC_F_PTG_READY_INTEN_PT1 ((uint32_t)(0x1UL << MXC_F_PTG_READY_INTEN_PT1_POS)) /**< READY_INTEN_PT1 Mask */ + +#define MXC_F_PTG_READY_INTEN_PT2_POS 2 /**< READY_INTEN_PT2 Position */ +#define MXC_F_PTG_READY_INTEN_PT2 ((uint32_t)(0x1UL << MXC_F_PTG_READY_INTEN_PT2_POS)) /**< READY_INTEN_PT2 Mask */ + +#define MXC_F_PTG_READY_INTEN_PT3_POS 3 /**< READY_INTEN_PT3 Position */ +#define MXC_F_PTG_READY_INTEN_PT3 ((uint32_t)(0x1UL << MXC_F_PTG_READY_INTEN_PT3_POS)) /**< READY_INTEN_PT3 Mask */ + +#define MXC_F_PTG_READY_INTEN_PT4_POS 4 /**< READY_INTEN_PT4 Position */ +#define MXC_F_PTG_READY_INTEN_PT4 ((uint32_t)(0x1UL << MXC_F_PTG_READY_INTEN_PT4_POS)) /**< READY_INTEN_PT4 Mask */ + +#define MXC_F_PTG_READY_INTEN_PT5_POS 5 /**< READY_INTEN_PT5 Position */ +#define MXC_F_PTG_READY_INTEN_PT5 ((uint32_t)(0x1UL << MXC_F_PTG_READY_INTEN_PT5_POS)) /**< READY_INTEN_PT5 Mask */ + +#define MXC_F_PTG_READY_INTEN_PT6_POS 6 /**< READY_INTEN_PT6 Position */ +#define MXC_F_PTG_READY_INTEN_PT6 ((uint32_t)(0x1UL << MXC_F_PTG_READY_INTEN_PT6_POS)) /**< READY_INTEN_PT6 Mask */ + +#define MXC_F_PTG_READY_INTEN_PT7_POS 7 /**< READY_INTEN_PT7 Position */ +#define MXC_F_PTG_READY_INTEN_PT7 ((uint32_t)(0x1UL << MXC_F_PTG_READY_INTEN_PT7_POS)) /**< READY_INTEN_PT7 Mask */ + +/**@} end of group PTG_READY_INTEN_Register */ + #ifdef __cplusplus } #endif diff --git a/Libraries/CMSIS/Device/Maxim/MAX32570/Include/pwrseq_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32570/Include/pwrseq_regs.h index b4469d0b94d..f515bc8234c 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32570/Include/pwrseq_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32570/Include/pwrseq_regs.h @@ -2,25 +2,18 @@ * @file pwrseq_regs.h * @brief Registers, Bit Masks and Bit Positions for the PWRSEQ Peripheral Module. * @note This file is @generated. + * @ingroup pwrseq_registers */ /****************************************************************************** * - * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by - * Analog Devices, Inc.), - * Copyright (C) 2023-2024 Analog Devices, Inc. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at +/****************************************************************************** * - * http://www.apache.org/licenses/LICENSE-2.0 + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. All Rights Reserved. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. + * This software is proprietary to Analog Devices, Inc. and its licensors. * ******************************************************************************/ @@ -49,7 +42,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32570/Include/rtc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32570/Include/rtc_regs.h index 6bb212915eb..85d0bf1b059 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32570/Include/rtc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32570/Include/rtc_regs.h @@ -2,25 +2,18 @@ * @file rtc_regs.h * @brief Registers, Bit Masks and Bit Positions for the RTC Peripheral Module. * @note This file is @generated. + * @ingroup rtc_registers */ /****************************************************************************** * - * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by - * Analog Devices, Inc.), - * Copyright (C) 2023-2024 Analog Devices, Inc. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at +/****************************************************************************** * - * http://www.apache.org/licenses/LICENSE-2.0 + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. All Rights Reserved. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. + * This software is proprietary to Analog Devices, Inc. and its licensors. * ******************************************************************************/ @@ -49,7 +42,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32570/Include/sdhc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32570/Include/sdhc_regs.h index 07ac635bf32..39d91af4b38 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32570/Include/sdhc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32570/Include/sdhc_regs.h @@ -2,25 +2,18 @@ * @file sdhc_regs.h * @brief Registers, Bit Masks and Bit Positions for the SDHC Peripheral Module. * @note This file is @generated. + * @ingroup sdhc_registers */ /****************************************************************************** * - * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by - * Analog Devices, Inc.), - * Copyright (C) 2023-2024 Analog Devices, Inc. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at +/****************************************************************************** * - * http://www.apache.org/licenses/LICENSE-2.0 + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. All Rights Reserved. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. + * This software is proprietary to Analog Devices, Inc. and its licensors. * ******************************************************************************/ @@ -49,7 +42,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile @@ -104,7 +101,7 @@ typedef struct { __O uint16_t force_cmd; /**< \b 0x050: SDHC FORCE_CMD Register */ __IO uint16_t force_event_int_stat; /**< \b 0x052: SDHC FORCE_EVENT_INT_STAT Register */ __IO uint8_t adma_er; /**< \b 0x054: SDHC ADMA_ER Register */ - __R uint8_t rsv_0x55_0x57[3]; + __R uint8_t rsv_0x55_0x57[3]; __IO uint32_t adma_addr_0; /**< \b 0x058: SDHC ADMA_ADDR_0 Register */ __IO uint32_t adma_addr_1; /**< \b 0x05C: SDHC ADMA_ADDR_1 Register */ __I uint16_t preset_0; /**< \b 0x060: SDHC PRESET_0 Register */ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32570/Include/sema_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32570/Include/sema_regs.h index f2b2eadf159..89b37e46697 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32570/Include/sema_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32570/Include/sema_regs.h @@ -2,25 +2,18 @@ * @file sema_regs.h * @brief Registers, Bit Masks and Bit Positions for the SEMA Peripheral Module. * @note This file is @generated. + * @ingroup sema_registers */ /****************************************************************************** * - * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by - * Analog Devices, Inc.), - * Copyright (C) 2023-2024 Analog Devices, Inc. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at +/****************************************************************************** * - * http://www.apache.org/licenses/LICENSE-2.0 + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. All Rights Reserved. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. + * This software is proprietary to Analog Devices, Inc. and its licensors. * ******************************************************************************/ @@ -49,7 +42,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32570/Include/sir_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32570/Include/sir_regs.h index 6171cdc0d65..ae0a5853abb 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32570/Include/sir_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32570/Include/sir_regs.h @@ -2,25 +2,18 @@ * @file sir_regs.h * @brief Registers, Bit Masks and Bit Positions for the SIR Peripheral Module. * @note This file is @generated. + * @ingroup sir_registers */ /****************************************************************************** * - * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by - * Analog Devices, Inc.), - * Copyright (C) 2023-2024 Analog Devices, Inc. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at +/****************************************************************************** * - * http://www.apache.org/licenses/LICENSE-2.0 + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. All Rights Reserved. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. + * This software is proprietary to Analog Devices, Inc. and its licensors. * ******************************************************************************/ @@ -49,7 +42,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32570/Include/skbd_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32570/Include/skbd_regs.h index 30e90cf4e04..bb3f8310cd3 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32570/Include/skbd_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32570/Include/skbd_regs.h @@ -2,25 +2,18 @@ * @file skbd_regs.h * @brief Registers, Bit Masks and Bit Positions for the SKBD Peripheral Module. * @note This file is @generated. + * @ingroup skbd_registers */ /****************************************************************************** * - * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by - * Analog Devices, Inc.), - * Copyright (C) 2023-2024 Analog Devices, Inc. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at +/****************************************************************************** * - * http://www.apache.org/licenses/LICENSE-2.0 + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. All Rights Reserved. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. + * This software is proprietary to Analog Devices, Inc. and its licensors. * ******************************************************************************/ @@ -49,7 +42,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32570/Include/smon_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32570/Include/smon_regs.h index 96e93c7d0a5..3b45ce3a343 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32570/Include/smon_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32570/Include/smon_regs.h @@ -2,25 +2,18 @@ * @file smon_regs.h * @brief Registers, Bit Masks and Bit Positions for the SMON Peripheral Module. * @note This file is @generated. + * @ingroup smon_registers */ /****************************************************************************** * - * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by - * Analog Devices, Inc.), - * Copyright (C) 2023-2024 Analog Devices, Inc. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at +/****************************************************************************** * - * http://www.apache.org/licenses/LICENSE-2.0 + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. All Rights Reserved. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. + * This software is proprietary to Analog Devices, Inc. and its licensors. * ******************************************************************************/ @@ -49,7 +42,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32570/Include/spi_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32570/Include/spi_regs.h index 6325e1b3a72..9ce7d032e3e 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32570/Include/spi_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32570/Include/spi_regs.h @@ -2,25 +2,18 @@ * @file spi_regs.h * @brief Registers, Bit Masks and Bit Positions for the SPI Peripheral Module. * @note This file is @generated. + * @ingroup spi_registers */ /****************************************************************************** * - * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by - * Analog Devices, Inc.), - * Copyright (C) 2023-2024 Analog Devices, Inc. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at +/****************************************************************************** * - * http://www.apache.org/licenses/LICENSE-2.0 + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. All Rights Reserved. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. + * This software is proprietary to Analog Devices, Inc. and its licensors. * ******************************************************************************/ @@ -49,7 +42,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32570/Include/spixfc_fifo_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32570/Include/spixfc_fifo_regs.h index 41c1ac75361..9d0bd08eb47 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32570/Include/spixfc_fifo_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32570/Include/spixfc_fifo_regs.h @@ -2,25 +2,18 @@ * @file spixfc_fifo_regs.h * @brief Registers, Bit Masks and Bit Positions for the SPIXFC_FIFO Peripheral Module. * @note This file is @generated. + * @ingroup spixfc_fifo_registers */ /****************************************************************************** * - * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by - * Analog Devices, Inc.), - * Copyright (C) 2023-2024 Analog Devices, Inc. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at +/****************************************************************************** * - * http://www.apache.org/licenses/LICENSE-2.0 + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. All Rights Reserved. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. + * This software is proprietary to Analog Devices, Inc. and its licensors. * ******************************************************************************/ @@ -49,7 +42,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32570/Include/spixfc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32570/Include/spixfc_regs.h index 4d3da112b29..6ecca2caa2a 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32570/Include/spixfc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32570/Include/spixfc_regs.h @@ -2,25 +2,18 @@ * @file spixfc_regs.h * @brief Registers, Bit Masks and Bit Positions for the SPIXFC Peripheral Module. * @note This file is @generated. + * @ingroup spixfc_registers */ /****************************************************************************** * - * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by - * Analog Devices, Inc.), - * Copyright (C) 2023-2024 Analog Devices, Inc. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at +/****************************************************************************** * - * http://www.apache.org/licenses/LICENSE-2.0 + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. All Rights Reserved. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. + * This software is proprietary to Analog Devices, Inc. and its licensors. * ******************************************************************************/ @@ -49,7 +42,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32570/Include/spixfm_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32570/Include/spixfm_regs.h index 58f578db585..ffd8112fadc 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32570/Include/spixfm_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32570/Include/spixfm_regs.h @@ -2,25 +2,18 @@ * @file spixfm_regs.h * @brief Registers, Bit Masks and Bit Positions for the SPIXFM Peripheral Module. * @note This file is @generated. + * @ingroup spixfm_registers */ /****************************************************************************** * - * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by - * Analog Devices, Inc.), - * Copyright (C) 2023-2024 Analog Devices, Inc. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at +/****************************************************************************** * - * http://www.apache.org/licenses/LICENSE-2.0 + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. All Rights Reserved. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. + * This software is proprietary to Analog Devices, Inc. and its licensors. * ******************************************************************************/ @@ -49,7 +42,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32570/Include/spixr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32570/Include/spixr_regs.h index f172c32ae12..db46b8ad917 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32570/Include/spixr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32570/Include/spixr_regs.h @@ -2,25 +2,18 @@ * @file spixr_regs.h * @brief Registers, Bit Masks and Bit Positions for the SPIXR Peripheral Module. * @note This file is @generated. + * @ingroup spixr_registers */ /****************************************************************************** * - * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by - * Analog Devices, Inc.), - * Copyright (C) 2023-2024 Analog Devices, Inc. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at +/****************************************************************************** * - * http://www.apache.org/licenses/LICENSE-2.0 + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. All Rights Reserved. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. + * This software is proprietary to Analog Devices, Inc. and its licensors. * ******************************************************************************/ @@ -49,7 +42,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32570/Include/srcc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32570/Include/srcc_regs.h index f403909e00f..c2b53eefdf7 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32570/Include/srcc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32570/Include/srcc_regs.h @@ -2,25 +2,18 @@ * @file srcc_regs.h * @brief Registers, Bit Masks and Bit Positions for the SRCC Peripheral Module. * @note This file is @generated. + * @ingroup srcc_registers */ /****************************************************************************** * - * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by - * Analog Devices, Inc.), - * Copyright (C) 2023-2024 Analog Devices, Inc. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at +/****************************************************************************** * - * http://www.apache.org/licenses/LICENSE-2.0 + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. All Rights Reserved. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. + * This software is proprietary to Analog Devices, Inc. and its licensors. * ******************************************************************************/ @@ -49,7 +42,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile @@ -73,10 +70,10 @@ extern "C" { * Structure type to access the SRCC Registers. */ typedef struct { - __I uint32_t cache_id; /**< \b 0x0000: SRCC CACHE_ID Register */ - __I uint32_t memcfg; /**< \b 0x0004: SRCC MEMCFG Register */ + __I uint32_t info; /**< \b 0x0000: SRCC INFO Register */ + __I uint32_t sz; /**< \b 0x0004: SRCC SZ Register */ __R uint32_t rsv_0x8_0xff[62]; - __IO uint32_t cache_ctrl; /**< \b 0x0100: SRCC CACHE_CTRL Register */ + __IO uint32_t ctrl; /**< \b 0x0100: SRCC CTRL Register */ __R uint32_t rsv_0x104_0x6ff[383]; __IO uint32_t invalidate; /**< \b 0x0700: SRCC INVALIDATE Register */ } mxc_srcc_regs_t; @@ -88,62 +85,62 @@ typedef struct { * @brief SRCC Peripheral Register Offsets from the SRCC Base Peripheral Address. * @{ */ -#define MXC_R_SRCC_CACHE_ID ((uint32_t)0x00000000UL) /**< Offset from SRCC Base Address: 0x0000 */ -#define MXC_R_SRCC_MEMCFG ((uint32_t)0x00000004UL) /**< Offset from SRCC Base Address: 0x0004 */ -#define MXC_R_SRCC_CACHE_CTRL ((uint32_t)0x00000100UL) /**< Offset from SRCC Base Address: 0x0100 */ +#define MXC_R_SRCC_INFO ((uint32_t)0x00000000UL) /**< Offset from SRCC Base Address: 0x0000 */ +#define MXC_R_SRCC_SZ ((uint32_t)0x00000004UL) /**< Offset from SRCC Base Address: 0x0004 */ +#define MXC_R_SRCC_CTRL ((uint32_t)0x00000100UL) /**< Offset from SRCC Base Address: 0x0100 */ #define MXC_R_SRCC_INVALIDATE ((uint32_t)0x00000700UL) /**< Offset from SRCC Base Address: 0x0700 */ /**@} end of group srcc_registers */ /** * @ingroup srcc_registers - * @defgroup SRCC_CACHE_ID SRCC_CACHE_ID + * @defgroup SRCC_INFO SRCC_INFO * @brief Cache ID Register. * @{ */ -#define MXC_F_SRCC_CACHE_ID_RELNUM_POS 0 /**< CACHE_ID_RELNUM Position */ -#define MXC_F_SRCC_CACHE_ID_RELNUM ((uint32_t)(0x3FUL << MXC_F_SRCC_CACHE_ID_RELNUM_POS)) /**< CACHE_ID_RELNUM Mask */ +#define MXC_F_SRCC_INFO_RELNUM_POS 0 /**< INFO_RELNUM Position */ +#define MXC_F_SRCC_INFO_RELNUM ((uint32_t)(0x3FUL << MXC_F_SRCC_INFO_RELNUM_POS)) /**< INFO_RELNUM Mask */ -#define MXC_F_SRCC_CACHE_ID_PARTNUM_POS 6 /**< CACHE_ID_PARTNUM Position */ -#define MXC_F_SRCC_CACHE_ID_PARTNUM ((uint32_t)(0xFUL << MXC_F_SRCC_CACHE_ID_PARTNUM_POS)) /**< CACHE_ID_PARTNUM Mask */ +#define MXC_F_SRCC_INFO_PARTNUM_POS 6 /**< INFO_PARTNUM Position */ +#define MXC_F_SRCC_INFO_PARTNUM ((uint32_t)(0xFUL << MXC_F_SRCC_INFO_PARTNUM_POS)) /**< INFO_PARTNUM Mask */ -#define MXC_F_SRCC_CACHE_ID_CCHID_POS 10 /**< CACHE_ID_CCHID Position */ -#define MXC_F_SRCC_CACHE_ID_CCHID ((uint32_t)(0x3FUL << MXC_F_SRCC_CACHE_ID_CCHID_POS)) /**< CACHE_ID_CCHID Mask */ +#define MXC_F_SRCC_INFO_ID_POS 10 /**< INFO_ID Position */ +#define MXC_F_SRCC_INFO_ID ((uint32_t)(0x3FUL << MXC_F_SRCC_INFO_ID_POS)) /**< INFO_ID Mask */ -/**@} end of group SRCC_CACHE_ID_Register */ +/**@} end of group SRCC_INFO_Register */ /** * @ingroup srcc_registers - * @defgroup SRCC_MEMCFG SRCC_MEMCFG + * @defgroup SRCC_SZ SRCC_SZ * @brief Memory Configuration Register. * @{ */ -#define MXC_F_SRCC_MEMCFG_CCHSZ_POS 0 /**< MEMCFG_CCHSZ Position */ -#define MXC_F_SRCC_MEMCFG_CCHSZ ((uint32_t)(0xFFFFUL << MXC_F_SRCC_MEMCFG_CCHSZ_POS)) /**< MEMCFG_CCHSZ Mask */ +#define MXC_F_SRCC_SZ_CCH_POS 0 /**< SZ_CCH Position */ +#define MXC_F_SRCC_SZ_CCH ((uint32_t)(0xFFFFUL << MXC_F_SRCC_SZ_CCH_POS)) /**< SZ_CCH Mask */ -#define MXC_F_SRCC_MEMCFG_MEMSZ_POS 16 /**< MEMCFG_MEMSZ Position */ -#define MXC_F_SRCC_MEMCFG_MEMSZ ((uint32_t)(0xFFFFUL << MXC_F_SRCC_MEMCFG_MEMSZ_POS)) /**< MEMCFG_MEMSZ Mask */ +#define MXC_F_SRCC_SZ_MEM_POS 16 /**< SZ_MEM Position */ +#define MXC_F_SRCC_SZ_MEM ((uint32_t)(0xFFFFUL << MXC_F_SRCC_SZ_MEM_POS)) /**< SZ_MEM Mask */ -/**@} end of group SRCC_MEMCFG_Register */ +/**@} end of group SRCC_SZ_Register */ /** * @ingroup srcc_registers - * @defgroup SRCC_CACHE_CTRL SRCC_CACHE_CTRL + * @defgroup SRCC_CTRL SRCC_CTRL * @brief Cache Control and Status Register. * @{ */ -#define MXC_F_SRCC_CACHE_CTRL_CACHE_EN_POS 0 /**< CACHE_CTRL_CACHE_EN Position */ -#define MXC_F_SRCC_CACHE_CTRL_CACHE_EN ((uint32_t)(0x1UL << MXC_F_SRCC_CACHE_CTRL_CACHE_EN_POS)) /**< CACHE_CTRL_CACHE_EN Mask */ +#define MXC_F_SRCC_CTRL_EN_POS 0 /**< CTRL_EN Position */ +#define MXC_F_SRCC_CTRL_EN ((uint32_t)(0x1UL << MXC_F_SRCC_CTRL_EN_POS)) /**< CTRL_EN Mask */ -#define MXC_F_SRCC_CACHE_CTRL_WRITE_ALLOC_EN_POS 1 /**< CACHE_CTRL_WRITE_ALLOC_EN Position */ -#define MXC_F_SRCC_CACHE_CTRL_WRITE_ALLOC_EN ((uint32_t)(0x1UL << MXC_F_SRCC_CACHE_CTRL_WRITE_ALLOC_EN_POS)) /**< CACHE_CTRL_WRITE_ALLOC_EN Mask */ +#define MXC_F_SRCC_CTRL_WR_ALLOC_EN_POS 1 /**< CTRL_WR_ALLOC_EN Position */ +#define MXC_F_SRCC_CTRL_WR_ALLOC_EN ((uint32_t)(0x1UL << MXC_F_SRCC_CTRL_WR_ALLOC_EN_POS)) /**< CTRL_WR_ALLOC_EN Mask */ -#define MXC_F_SRCC_CACHE_CTRL_CWFST_DIS_POS 2 /**< CACHE_CTRL_CWFST_DIS Position */ -#define MXC_F_SRCC_CACHE_CTRL_CWFST_DIS ((uint32_t)(0x1UL << MXC_F_SRCC_CACHE_CTRL_CWFST_DIS_POS)) /**< CACHE_CTRL_CWFST_DIS Mask */ +#define MXC_F_SRCC_CTRL_CWFST_DIS_POS 2 /**< CTRL_CWFST_DIS Position */ +#define MXC_F_SRCC_CTRL_CWFST_DIS ((uint32_t)(0x1UL << MXC_F_SRCC_CTRL_CWFST_DIS_POS)) /**< CTRL_CWFST_DIS Mask */ -#define MXC_F_SRCC_CACHE_CTRL_CACHE_RDY_POS 16 /**< CACHE_CTRL_CACHE_RDY Position */ -#define MXC_F_SRCC_CACHE_CTRL_CACHE_RDY ((uint32_t)(0x1UL << MXC_F_SRCC_CACHE_CTRL_CACHE_RDY_POS)) /**< CACHE_CTRL_CACHE_RDY Mask */ +#define MXC_F_SRCC_CTRL_RDY_POS 16 /**< CTRL_RDY Position */ +#define MXC_F_SRCC_CTRL_RDY ((uint32_t)(0x1UL << MXC_F_SRCC_CTRL_RDY_POS)) /**< CTRL_RDY Mask */ -/**@} end of group SRCC_CACHE_CTRL_Register */ +/**@} end of group SRCC_CTRL_Register */ /** * @ingroup srcc_registers @@ -158,8 +155,8 @@ typedef struct { * always return 0. * @{ */ -#define MXC_F_SRCC_INVALIDATE_IA_POS 0 /**< INVALIDATE_IA Position */ -#define MXC_F_SRCC_INVALIDATE_IA ((uint32_t)(0xFFFFFFFFUL << MXC_F_SRCC_INVALIDATE_IA_POS)) /**< INVALIDATE_IA Mask */ +#define MXC_F_SRCC_INVALIDATE_INVALID_POS 0 /**< INVALIDATE_INVALID Position */ +#define MXC_F_SRCC_INVALIDATE_INVALID ((uint32_t)(0xFFFFFFFFUL << MXC_F_SRCC_INVALIDATE_INVALID_POS)) /**< INVALIDATE_INVALID Mask */ /**@} end of group SRCC_INVALIDATE_Register */ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32570/Include/tmr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32570/Include/tmr_regs.h index d4bde3aa6f2..21642952a9b 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32570/Include/tmr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32570/Include/tmr_regs.h @@ -2,25 +2,18 @@ * @file tmr_regs.h * @brief Registers, Bit Masks and Bit Positions for the TMR Peripheral Module. * @note This file is @generated. + * @ingroup tmr_registers */ /****************************************************************************** * - * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by - * Analog Devices, Inc.), - * Copyright (C) 2023-2024 Analog Devices, Inc. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at +/****************************************************************************** * - * http://www.apache.org/licenses/LICENSE-2.0 + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. All Rights Reserved. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. + * This software is proprietary to Analog Devices, Inc. and its licensors. * ******************************************************************************/ @@ -49,7 +42,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32570/Include/trimsir_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32570/Include/trimsir_regs.h index 946343af296..9e376d4a6a9 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32570/Include/trimsir_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32570/Include/trimsir_regs.h @@ -2,25 +2,18 @@ * @file trimsir_regs.h * @brief Registers, Bit Masks and Bit Positions for the TRIMSIR Peripheral Module. * @note This file is @generated. + * @ingroup trimsir_registers */ /****************************************************************************** * - * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by - * Analog Devices, Inc.), - * Copyright (C) 2023-2024 Analog Devices, Inc. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at +/****************************************************************************** * - * http://www.apache.org/licenses/LICENSE-2.0 + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. All Rights Reserved. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. + * This software is proprietary to Analog Devices, Inc. and its licensors. * ******************************************************************************/ @@ -49,7 +42,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32570/Include/trng_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32570/Include/trng_regs.h index 1f02703dca0..6af6b451432 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32570/Include/trng_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32570/Include/trng_regs.h @@ -2,25 +2,18 @@ * @file trng_regs.h * @brief Registers, Bit Masks and Bit Positions for the TRNG Peripheral Module. * @note This file is @generated. + * @ingroup trng_registers */ /****************************************************************************** * - * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by - * Analog Devices, Inc.), - * Copyright (C) 2023-2024 Analog Devices, Inc. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at +/****************************************************************************** * - * http://www.apache.org/licenses/LICENSE-2.0 + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. All Rights Reserved. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. + * This software is proprietary to Analog Devices, Inc. and its licensors. * ******************************************************************************/ @@ -49,7 +42,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile @@ -73,8 +70,8 @@ extern "C" { * Structure type to access the TRNG Registers. */ typedef struct { - __IO uint32_t cn; /**< \b 0x00: TRNG CN Register */ - __I uint32_t st; /**< \b 0x04: TRNG ST Register */ + __IO uint32_t ctrl; /**< \b 0x00: TRNG CTRL Register */ + __I uint32_t status; /**< \b 0x04: TRNG STATUS Register */ __I uint32_t data; /**< \b 0x08: TRNG DATA Register */ } mxc_trng_regs_t; @@ -85,42 +82,63 @@ typedef struct { * @brief TRNG Peripheral Register Offsets from the TRNG Base Peripheral Address. * @{ */ -#define MXC_R_TRNG_CN ((uint32_t)0x00000000UL) /**< Offset from TRNG Base Address: 0x0000 */ -#define MXC_R_TRNG_ST ((uint32_t)0x00000004UL) /**< Offset from TRNG Base Address: 0x0004 */ +#define MXC_R_TRNG_CTRL ((uint32_t)0x00000000UL) /**< Offset from TRNG Base Address: 0x0000 */ +#define MXC_R_TRNG_STATUS ((uint32_t)0x00000004UL) /**< Offset from TRNG Base Address: 0x0004 */ #define MXC_R_TRNG_DATA ((uint32_t)0x00000008UL) /**< Offset from TRNG Base Address: 0x0008 */ /**@} end of group trng_registers */ /** * @ingroup trng_registers - * @defgroup TRNG_CN TRNG_CN + * @defgroup TRNG_CTRL TRNG_CTRL * @brief TRNG Control Register. * @{ */ -#define MXC_F_TRNG_CN_RND_IRQ_EN_POS 1 /**< CN_RND_IRQ_EN Position */ -#define MXC_F_TRNG_CN_RND_IRQ_EN ((uint32_t)(0x1UL << MXC_F_TRNG_CN_RND_IRQ_EN_POS)) /**< CN_RND_IRQ_EN Mask */ +#define MXC_F_TRNG_CTRL_ODHT_POS 0 /**< CTRL_ODHT Position */ +#define MXC_F_TRNG_CTRL_ODHT ((uint32_t)(0x1UL << MXC_F_TRNG_CTRL_ODHT_POS)) /**< CTRL_ODHT Mask */ -#define MXC_F_TRNG_CN_AESKG_POS 3 /**< CN_AESKG Position */ -#define MXC_F_TRNG_CN_AESKG ((uint32_t)(0x1UL << MXC_F_TRNG_CN_AESKG_POS)) /**< CN_AESKG Mask */ +#define MXC_F_TRNG_CTRL_RND_IE_POS 1 /**< CTRL_RND_IE Position */ +#define MXC_F_TRNG_CTRL_RND_IE ((uint32_t)(0x1UL << MXC_F_TRNG_CTRL_RND_IE_POS)) /**< CTRL_RND_IE Mask */ -#define MXC_F_TRNG_CN_AESKG_MEMPROTE_POS 4 /**< CN_AESKG_MEMPROTE Position */ -#define MXC_F_TRNG_CN_AESKG_MEMPROTE ((uint32_t)(0x1UL << MXC_F_TRNG_CN_AESKG_MEMPROTE_POS)) /**< CN_AESKG_MEMPROTE Mask */ +#define MXC_F_TRNG_CTRL_HEALTH_EN_POS 2 /**< CTRL_HEALTH_EN Position */ +#define MXC_F_TRNG_CTRL_HEALTH_EN ((uint32_t)(0x1UL << MXC_F_TRNG_CTRL_HEALTH_EN_POS)) /**< CTRL_HEALTH_EN Mask */ -/**@} end of group TRNG_CN_Register */ +#define MXC_F_TRNG_CTRL_AESKG_USR_POS 3 /**< CTRL_AESKG_USR Position */ +#define MXC_F_TRNG_CTRL_AESKG_USR ((uint32_t)(0x1UL << MXC_F_TRNG_CTRL_AESKG_USR_POS)) /**< CTRL_AESKG_USR Mask */ + +#define MXC_F_TRNG_CTRL_AESKG_SYS_POS 4 /**< CTRL_AESKG_SYS Position */ +#define MXC_F_TRNG_CTRL_AESKG_SYS ((uint32_t)(0x1UL << MXC_F_TRNG_CTRL_AESKG_SYS_POS)) /**< CTRL_AESKG_SYS Mask */ + +#define MXC_F_TRNG_CTRL_KEYWIPE_POS 15 /**< CTRL_KEYWIPE Position */ +#define MXC_F_TRNG_CTRL_KEYWIPE ((uint32_t)(0x1UL << MXC_F_TRNG_CTRL_KEYWIPE_POS)) /**< CTRL_KEYWIPE Mask */ + +/**@} end of group TRNG_CTRL_Register */ /** * @ingroup trng_registers - * @defgroup TRNG_ST TRNG_ST + * @defgroup TRNG_STATUS TRNG_STATUS * @brief Data. The content of this register is valid only when RNG_IS = 1. When TRNG is * disabled, read returns 0x0000 0000. * @{ */ -#define MXC_F_TRNG_ST_RND_RDY_POS 0 /**< ST_RND_RDY Position */ -#define MXC_F_TRNG_ST_RND_RDY ((uint32_t)(0x1UL << MXC_F_TRNG_ST_RND_RDY_POS)) /**< ST_RND_RDY Mask */ +#define MXC_F_TRNG_STATUS_RDY_POS 0 /**< STATUS_RDY Position */ +#define MXC_F_TRNG_STATUS_RDY ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_RDY_POS)) /**< STATUS_RDY Mask */ + +#define MXC_F_TRNG_STATUS_ODHT_POS 1 /**< STATUS_ODHT Position */ +#define MXC_F_TRNG_STATUS_ODHT ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_ODHT_POS)) /**< STATUS_ODHT Mask */ + +#define MXC_F_TRNG_STATUS_HT_POS 2 /**< STATUS_HT Position */ +#define MXC_F_TRNG_STATUS_HT ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_HT_POS)) /**< STATUS_HT Mask */ + +#define MXC_F_TRNG_STATUS_SRCFAIL_POS 3 /**< STATUS_SRCFAIL Position */ +#define MXC_F_TRNG_STATUS_SRCFAIL ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_SRCFAIL_POS)) /**< STATUS_SRCFAIL Mask */ + +#define MXC_F_TRNG_STATUS_AESKGD_POS 4 /**< STATUS_AESKGD Position */ +#define MXC_F_TRNG_STATUS_AESKGD ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_AESKGD_POS)) /**< STATUS_AESKGD Mask */ -#define MXC_F_TRNG_ST_AESKGD_MEU_S_POS 4 /**< ST_AESKGD_MEU_S Position */ -#define MXC_F_TRNG_ST_AESKGD_MEU_S ((uint32_t)(0x1UL << MXC_F_TRNG_ST_AESKGD_MEU_S_POS)) /**< ST_AESKGD_MEU_S Mask */ +#define MXC_F_TRNG_STATUS_LD_CNT_POS 24 /**< STATUS_LD_CNT Position */ +#define MXC_F_TRNG_STATUS_LD_CNT ((uint32_t)(0xFFUL << MXC_F_TRNG_STATUS_LD_CNT_POS)) /**< STATUS_LD_CNT Mask */ -/**@} end of group TRNG_ST_Register */ +/**@} end of group TRNG_STATUS_Register */ /** * @ingroup trng_registers diff --git a/Libraries/CMSIS/Device/Maxim/MAX32570/Include/uart_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32570/Include/uart_regs.h index c5fce759098..ee335cb8edb 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32570/Include/uart_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32570/Include/uart_regs.h @@ -2,25 +2,18 @@ * @file uart_regs.h * @brief Registers, Bit Masks and Bit Positions for the UART Peripheral Module. * @note This file is @generated. + * @ingroup uart_registers */ /****************************************************************************** * - * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by - * Analog Devices, Inc.), - * Copyright (C) 2023-2024 Analog Devices, Inc. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at +/****************************************************************************** * - * http://www.apache.org/licenses/LICENSE-2.0 + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. All Rights Reserved. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. + * This software is proprietary to Analog Devices, Inc. and its licensors. * ******************************************************************************/ @@ -49,7 +42,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32570/Include/usbhs_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32570/Include/usbhs_regs.h index 028c2589f98..10da7e91c09 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32570/Include/usbhs_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32570/Include/usbhs_regs.h @@ -2,25 +2,18 @@ * @file usbhs_regs.h * @brief Registers, Bit Masks and Bit Positions for the USBHS Peripheral Module. * @note This file is @generated. + * @ingroup usbhs_registers */ /****************************************************************************** * - * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by - * Analog Devices, Inc.), - * Copyright (C) 2023-2024 Analog Devices, Inc. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at +/****************************************************************************** * - * http://www.apache.org/licenses/LICENSE-2.0 + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. All Rights Reserved. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. + * This software is proprietary to Analog Devices, Inc. and its licensors. * ******************************************************************************/ @@ -49,7 +42,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile @@ -120,8 +117,7 @@ typedef struct { __IO uint8_t epinfo; /**< \b 0x78: USBHS EPINFO Register */ __IO uint8_t raminfo; /**< \b 0x79: USBHS RAMINFO Register */ __IO uint8_t softreset; /**< \b 0x7A: USBHS SOFTRESET Register */ - __IO uint8_t earlydma; /**< \b 0x7B: USBHS EARLYDMA Register */ - __R uint32_t rsv_0x7c; + __R uint8_t rsv_0x7b_0x7f[5]; __IO uint16_t ctuch; /**< \b 0x80: USBHS CTUCH Register */ __IO uint16_t cthsrtn; /**< \b 0x82: USBHS CTHSRTN Register */ __R uint32_t rsv_0x84_0x3ff[223]; @@ -216,7 +212,6 @@ typedef struct { #define MXC_R_USBHS_EPINFO ((uint32_t)0x00000078UL) /**< Offset from USBHS Base Address: 0x0078 */ #define MXC_R_USBHS_RAMINFO ((uint32_t)0x00000079UL) /**< Offset from USBHS Base Address: 0x0079 */ #define MXC_R_USBHS_SOFTRESET ((uint32_t)0x0000007AUL) /**< Offset from USBHS Base Address: 0x007A */ -#define MXC_R_USBHS_EARLYDMA ((uint32_t)0x0000007BUL) /**< Offset from USBHS Base Address: 0x007B */ #define MXC_R_USBHS_CTUCH ((uint32_t)0x00000080UL) /**< Offset from USBHS Base Address: 0x0080 */ #define MXC_R_USBHS_CTHSRTN ((uint32_t)0x00000082UL) /**< Offset from USBHS Base Address: 0x0082 */ #define MXC_R_USBHS_MXM_USB_REG_00 ((uint32_t)0x00000400UL) /**< Offset from USBHS Base Address: 0x0400 */ @@ -707,15 +702,9 @@ typedef struct { #define MXC_F_USBHS_INCSRU_MODE_POS 5 /**< INCSRU_MODE Position */ #define MXC_F_USBHS_INCSRU_MODE ((uint8_t)(0x1UL << MXC_F_USBHS_INCSRU_MODE_POS)) /**< INCSRU_MODE Mask */ -#define MXC_F_USBHS_INCSRU_DMAREQEN_POS 4 /**< INCSRU_DMAREQEN Position */ -#define MXC_F_USBHS_INCSRU_DMAREQEN ((uint8_t)(0x1UL << MXC_F_USBHS_INCSRU_DMAREQEN_POS)) /**< INCSRU_DMAREQEN Mask */ - #define MXC_F_USBHS_INCSRU_FRCDATATOG_POS 3 /**< INCSRU_FRCDATATOG Position */ #define MXC_F_USBHS_INCSRU_FRCDATATOG ((uint8_t)(0x1UL << MXC_F_USBHS_INCSRU_FRCDATATOG_POS)) /**< INCSRU_FRCDATATOG Mask */ -#define MXC_F_USBHS_INCSRU_DMAREQMODE_POS 2 /**< INCSRU_DMAREQMODE Position */ -#define MXC_F_USBHS_INCSRU_DMAREQMODE ((uint8_t)(0x1UL << MXC_F_USBHS_INCSRU_DMAREQMODE_POS)) /**< INCSRU_DMAREQMODE Mask */ - #define MXC_F_USBHS_INCSRU_DPKTBUFDIS_POS 1 /**< INCSRU_DPKTBUFDIS Position */ #define MXC_F_USBHS_INCSRU_DPKTBUFDIS ((uint8_t)(0x1UL << MXC_F_USBHS_INCSRU_DPKTBUFDIS_POS)) /**< INCSRU_DPKTBUFDIS Mask */ @@ -779,15 +768,9 @@ typedef struct { #define MXC_F_USBHS_OUTCSRU_ISO_POS 6 /**< OUTCSRU_ISO Position */ #define MXC_F_USBHS_OUTCSRU_ISO ((uint8_t)(0x1UL << MXC_F_USBHS_OUTCSRU_ISO_POS)) /**< OUTCSRU_ISO Mask */ -#define MXC_F_USBHS_OUTCSRU_DMAREQEN_POS 5 /**< OUTCSRU_DMAREQEN Position */ -#define MXC_F_USBHS_OUTCSRU_DMAREQEN ((uint8_t)(0x1UL << MXC_F_USBHS_OUTCSRU_DMAREQEN_POS)) /**< OUTCSRU_DMAREQEN Mask */ - #define MXC_F_USBHS_OUTCSRU_DISNYET_POS 4 /**< OUTCSRU_DISNYET Position */ #define MXC_F_USBHS_OUTCSRU_DISNYET ((uint8_t)(0x1UL << MXC_F_USBHS_OUTCSRU_DISNYET_POS)) /**< OUTCSRU_DISNYET Mask */ -#define MXC_F_USBHS_OUTCSRU_DMAREQMODE_POS 3 /**< OUTCSRU_DMAREQMODE Position */ -#define MXC_F_USBHS_OUTCSRU_DMAREQMODE ((uint8_t)(0x1UL << MXC_F_USBHS_OUTCSRU_DMAREQMODE_POS)) /**< OUTCSRU_DMAREQMODE Mask */ - #define MXC_F_USBHS_OUTCSRU_DPKTBUFDIS_POS 1 /**< OUTCSRU_DPKTBUFDIS Position */ #define MXC_F_USBHS_OUTCSRU_DPKTBUFDIS ((uint8_t)(0x1UL << MXC_F_USBHS_OUTCSRU_DPKTBUFDIS_POS)) /**< OUTCSRU_DPKTBUFDIS Mask */ @@ -1022,12 +1005,9 @@ typedef struct { /** * @ingroup usbhs_registers * @defgroup USBHS_RAMINFO USBHS_RAMINFO - * @brief RAM width and DMA hardware information. + * @brief RAM width information. * @{ */ -#define MXC_F_USBHS_RAMINFO_DMACHANS_POS 4 /**< RAMINFO_DMACHANS Position */ -#define MXC_F_USBHS_RAMINFO_DMACHANS ((uint8_t)(0xFUL << MXC_F_USBHS_RAMINFO_DMACHANS_POS)) /**< RAMINFO_DMACHANS Mask */ - #define MXC_F_USBHS_RAMINFO_RAMBITS_POS 0 /**< RAMINFO_RAMBITS Position */ #define MXC_F_USBHS_RAMINFO_RAMBITS ((uint8_t)(0xFUL << MXC_F_USBHS_RAMINFO_RAMBITS_POS)) /**< RAMINFO_RAMBITS Mask */ @@ -1047,20 +1027,6 @@ typedef struct { /**@} end of group USBHS_SOFTRESET_Register */ -/** - * @ingroup usbhs_registers - * @defgroup USBHS_EARLYDMA USBHS_EARLYDMA - * @brief DMA timing control register. - * @{ - */ -#define MXC_F_USBHS_EARLYDMA_EDMAIN_POS 1 /**< EARLYDMA_EDMAIN Position */ -#define MXC_F_USBHS_EARLYDMA_EDMAIN ((uint8_t)(0x1UL << MXC_F_USBHS_EARLYDMA_EDMAIN_POS)) /**< EARLYDMA_EDMAIN Mask */ - -#define MXC_F_USBHS_EARLYDMA_EDMAOUT_POS 0 /**< EARLYDMA_EDMAOUT Position */ -#define MXC_F_USBHS_EARLYDMA_EDMAOUT ((uint8_t)(0x1UL << MXC_F_USBHS_EARLYDMA_EDMAOUT_POS)) /**< EARLYDMA_EDMAOUT Mask */ - -/**@} end of group USBHS_EARLYDMA_Register */ - /** * @ingroup usbhs_registers * @defgroup USBHS_CTUCH USBHS_CTUCH @@ -1131,9 +1097,6 @@ typedef struct { #define MXC_F_USBHS_MXM_REG_A4_VRST_VDDB_N_A_POS 0 /**< MXM_REG_A4_VRST_VDDB_N_A Position */ #define MXC_F_USBHS_MXM_REG_A4_VRST_VDDB_N_A ((uint32_t)(0x1UL << MXC_F_USBHS_MXM_REG_A4_VRST_VDDB_N_A_POS)) /**< MXM_REG_A4_VRST_VDDB_N_A Mask */ -#define MXC_F_USBHS_MXM_REG_A4_DMA_INT_POS 1 /**< MXM_REG_A4_DMA_INT Position */ -#define MXC_F_USBHS_MXM_REG_A4_DMA_INT ((uint32_t)(0x1UL << MXC_F_USBHS_MXM_REG_A4_DMA_INT_POS)) /**< MXM_REG_A4_DMA_INT Mask */ - /**@} end of group USBHS_MXM_REG_A4_Register */ #ifdef __cplusplus diff --git a/Libraries/CMSIS/Device/Maxim/MAX32570/Include/wdt_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32570/Include/wdt_regs.h index 833fbb14a4a..9c90d0b8e50 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32570/Include/wdt_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32570/Include/wdt_regs.h @@ -2,25 +2,18 @@ * @file wdt_regs.h * @brief Registers, Bit Masks and Bit Positions for the WDT Peripheral Module. * @note This file is @generated. + * @ingroup wdt_registers */ /****************************************************************************** * - * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by - * Analog Devices, Inc.), - * Copyright (C) 2023-2024 Analog Devices, Inc. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at +/****************************************************************************** * - * http://www.apache.org/licenses/LICENSE-2.0 + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. All Rights Reserved. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. + * This software is proprietary to Analog Devices, Inc. and its licensors. * ******************************************************************************/ @@ -49,7 +42,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32572/Include/adc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32572/Include/adc_regs.h index 80f80854040..ba7c0cfc0b4 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32572/Include/adc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32572/Include/adc_regs.h @@ -25,8 +25,8 @@ * ******************************************************************************/ -#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_ADC_REGS_H_ -#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_ADC_REGS_H_ +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32672_INCLUDE_ADC_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32672_INCLUDE_ADC_REGS_H_ /* **** Includes **** */ #include @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile @@ -66,7 +70,7 @@ extern "C" { * @ingroup adc * @defgroup adc_registers ADC_Registers * @brief Registers, Bit Masks and Bit Positions for the ADC Peripheral Module. - * @details 10-bit Analog to Digital Converter + * @details Inter-Integrated Circuit. */ /** @@ -74,12 +78,30 @@ extern "C" { * Structure type to access the ADC Registers. */ typedef struct { - __IO uint32_t ctrl; /**< \b 0x0000: ADC CTRL Register */ - __IO uint32_t status; /**< \b 0x0004: ADC STATUS Register */ - __IO uint32_t data; /**< \b 0x0008: ADC DATA Register */ - __IO uint32_t intr; /**< \b 0x000C: ADC INTR Register */ - __IO uint32_t limit[4]; /**< \b 0x0010: ADC LIMIT Register */ - __IO uint32_t deccnt; /**< \b 0x0020: ADC DECCNT Register */ + __IO uint32_t ctrl0; /**< \b 0x00: ADC CTRL0 Register */ + __IO uint32_t ctrl1; /**< \b 0x04: ADC CTRL1 Register */ + __IO uint32_t clkctrl; /**< \b 0x08: ADC CLKCTRL Register */ + __IO uint32_t sampclkctrl; /**< \b 0x0C: ADC SAMPCLKCTRL Register */ + __IO uint32_t chsel0; /**< \b 0x10: ADC CHSEL0 Register */ + __IO uint32_t chsel1; /**< \b 0x14: ADC CHSEL1 Register */ + __IO uint32_t chsel2; /**< \b 0x18: ADC CHSEL2 Register */ + __IO uint32_t chsel3; /**< \b 0x1C: ADC CHSEL3 Register */ + __R uint32_t rsv_0x20_0x2f[4]; + __IO uint32_t restart; /**< \b 0x30: ADC RESTART Register */ + __R uint32_t rsv_0x34_0x3b[2]; + __IO uint32_t datafmt; /**< \b 0x3C: ADC DATAFMT Register */ + __IO uint32_t fifodmactrl; /**< \b 0x40: ADC FIFODMACTRL Register */ + __IO uint32_t data; /**< \b 0x44: ADC DATA Register */ + __IO uint32_t status; /**< \b 0x48: ADC STATUS Register */ + __IO uint32_t chstatus; /**< \b 0x4C: ADC CHSTATUS Register */ + __IO uint32_t inten; /**< \b 0x50: ADC INTEN Register */ + __IO uint32_t intfl; /**< \b 0x54: ADC INTFL Register */ + __R uint32_t rsv_0x58_0x5f[2]; + __IO uint32_t sfraddroffset; /**< \b 0x60: ADC SFRADDROFFSET Register */ + __IO uint32_t sfraddr; /**< \b 0x64: ADC SFRADDR Register */ + __IO uint32_t sfrwrdata; /**< \b 0x68: ADC SFRWRDATA Register */ + __IO uint32_t sfrrddata; /**< \b 0x6C: ADC SFRRDDATA Register */ + __IO uint32_t sfrstatus; /**< \b 0x70: ADC SFRSTATUS Register */ } mxc_adc_regs_t; /* Register offsets for module ADC */ @@ -89,199 +111,454 @@ typedef struct { * @brief ADC Peripheral Register Offsets from the ADC Base Peripheral Address. * @{ */ -#define MXC_R_ADC_CTRL ((uint32_t)0x00000000UL) /**< Offset from ADC Base Address: 0x0000 */ -#define MXC_R_ADC_STATUS ((uint32_t)0x00000004UL) /**< Offset from ADC Base Address: 0x0004 */ -#define MXC_R_ADC_DATA ((uint32_t)0x00000008UL) /**< Offset from ADC Base Address: 0x0008 */ -#define MXC_R_ADC_INTR ((uint32_t)0x0000000CUL) /**< Offset from ADC Base Address: 0x000C */ -#define MXC_R_ADC_LIMIT ((uint32_t)0x00000010UL) /**< Offset from ADC Base Address: 0x0010 */ -#define MXC_R_ADC_DECCNT ((uint32_t)0x00000020UL) /**< Offset from ADC Base Address: 0x0020 */ +#define MXC_R_ADC_CTRL0 ((uint32_t)0x00000000UL) /**< Offset from ADC Base Address: 0x0000 */ +#define MXC_R_ADC_CTRL1 ((uint32_t)0x00000004UL) /**< Offset from ADC Base Address: 0x0004 */ +#define MXC_R_ADC_CLKCTRL ((uint32_t)0x00000008UL) /**< Offset from ADC Base Address: 0x0008 */ +#define MXC_R_ADC_SAMPCLKCTRL ((uint32_t)0x0000000CUL) /**< Offset from ADC Base Address: 0x000C */ +#define MXC_R_ADC_CHSEL0 ((uint32_t)0x00000010UL) /**< Offset from ADC Base Address: 0x0010 */ +#define MXC_R_ADC_CHSEL1 ((uint32_t)0x00000014UL) /**< Offset from ADC Base Address: 0x0014 */ +#define MXC_R_ADC_CHSEL2 ((uint32_t)0x00000018UL) /**< Offset from ADC Base Address: 0x0018 */ +#define MXC_R_ADC_CHSEL3 ((uint32_t)0x0000001CUL) /**< Offset from ADC Base Address: 0x001C */ +#define MXC_R_ADC_RESTART ((uint32_t)0x00000030UL) /**< Offset from ADC Base Address: 0x0030 */ +#define MXC_R_ADC_DATAFMT ((uint32_t)0x0000003CUL) /**< Offset from ADC Base Address: 0x003C */ +#define MXC_R_ADC_FIFODMACTRL ((uint32_t)0x00000040UL) /**< Offset from ADC Base Address: 0x0040 */ +#define MXC_R_ADC_DATA ((uint32_t)0x00000044UL) /**< Offset from ADC Base Address: 0x0044 */ +#define MXC_R_ADC_STATUS ((uint32_t)0x00000048UL) /**< Offset from ADC Base Address: 0x0048 */ +#define MXC_R_ADC_CHSTATUS ((uint32_t)0x0000004CUL) /**< Offset from ADC Base Address: 0x004C */ +#define MXC_R_ADC_INTEN ((uint32_t)0x00000050UL) /**< Offset from ADC Base Address: 0x0050 */ +#define MXC_R_ADC_INTFL ((uint32_t)0x00000054UL) /**< Offset from ADC Base Address: 0x0054 */ +#define MXC_R_ADC_SFRADDROFFSET ((uint32_t)0x00000060UL) /**< Offset from ADC Base Address: 0x0060 */ +#define MXC_R_ADC_SFRADDR ((uint32_t)0x00000064UL) /**< Offset from ADC Base Address: 0x0064 */ +#define MXC_R_ADC_SFRWRDATA ((uint32_t)0x00000068UL) /**< Offset from ADC Base Address: 0x0068 */ +#define MXC_R_ADC_SFRRDDATA ((uint32_t)0x0000006CUL) /**< Offset from ADC Base Address: 0x006C */ +#define MXC_R_ADC_SFRSTATUS ((uint32_t)0x00000070UL) /**< Offset from ADC Base Address: 0x0070 */ /**@} end of group adc_registers */ /** * @ingroup adc_registers - * @defgroup ADC_CTRL ADC_CTRL - * @brief ADC Control + * @defgroup ADC_CTRL0 ADC_CTRL0 + * @brief Control Register 0. * @{ */ -#define MXC_F_ADC_CTRL_START_POS 0 /**< CTRL_START Position */ -#define MXC_F_ADC_CTRL_START ((uint32_t)(0x1UL << MXC_F_ADC_CTRL_START_POS)) /**< CTRL_START Mask */ - -#define MXC_F_ADC_CTRL_PWR_POS 1 /**< CTRL_PWR Position */ -#define MXC_F_ADC_CTRL_PWR ((uint32_t)(0x1UL << MXC_F_ADC_CTRL_PWR_POS)) /**< CTRL_PWR Mask */ - -#define MXC_F_ADC_CTRL_REBUF_PWR_POS 3 /**< CTRL_REBUF_PWR Position */ -#define MXC_F_ADC_CTRL_REBUF_PWR ((uint32_t)(0x1UL << MXC_F_ADC_CTRL_REBUF_PWR_POS)) /**< CTRL_REBUF_PWR Mask */ - -#define MXC_F_ADC_CTRL_CHGPUMP_PWR_POS 4 /**< CTRL_CHGPUMP_PWR Position */ -#define MXC_F_ADC_CTRL_CHGPUMP_PWR ((uint32_t)(0x1UL << MXC_F_ADC_CTRL_CHGPUMP_PWR_POS)) /**< CTRL_CHGPUMP_PWR Mask */ - -#define MXC_F_ADC_CTRL_REF_SCALE_POS 8 /**< CTRL_REF_SCALE Position */ -#define MXC_F_ADC_CTRL_REF_SCALE ((uint32_t)(0x1UL << MXC_F_ADC_CTRL_REF_SCALE_POS)) /**< CTRL_REF_SCALE Mask */ - -#define MXC_F_ADC_CTRL_SCALE_POS 9 /**< CTRL_SCALE Position */ -#define MXC_F_ADC_CTRL_SCALE ((uint32_t)(0x1UL << MXC_F_ADC_CTRL_SCALE_POS)) /**< CTRL_SCALE Mask */ - -#define MXC_F_ADC_CTRL_CLK_EN_POS 11 /**< CTRL_CLK_EN Position */ -#define MXC_F_ADC_CTRL_CLK_EN ((uint32_t)(0x1UL << MXC_F_ADC_CTRL_CLK_EN_POS)) /**< CTRL_CLK_EN Mask */ - -#define MXC_F_ADC_CTRL_CH_SEL_POS 12 /**< CTRL_CH_SEL Position */ -#define MXC_F_ADC_CTRL_CH_SEL ((uint32_t)(0x1FUL << MXC_F_ADC_CTRL_CH_SEL_POS)) /**< CTRL_CH_SEL Mask */ -#define MXC_V_ADC_CTRL_CH_SEL_AIN0 ((uint32_t)0x0UL) /**< CTRL_CH_SEL_AIN0 Value */ -#define MXC_S_ADC_CTRL_CH_SEL_AIN0 (MXC_V_ADC_CTRL_CH_SEL_AIN0 << MXC_F_ADC_CTRL_CH_SEL_POS) /**< CTRL_CH_SEL_AIN0 Setting */ -#define MXC_V_ADC_CTRL_CH_SEL_AIN1 ((uint32_t)0x1UL) /**< CTRL_CH_SEL_AIN1 Value */ -#define MXC_S_ADC_CTRL_CH_SEL_AIN1 (MXC_V_ADC_CTRL_CH_SEL_AIN1 << MXC_F_ADC_CTRL_CH_SEL_POS) /**< CTRL_CH_SEL_AIN1 Setting */ -#define MXC_V_ADC_CTRL_CH_SEL_AIN2 ((uint32_t)0x2UL) /**< CTRL_CH_SEL_AIN2 Value */ -#define MXC_S_ADC_CTRL_CH_SEL_AIN2 (MXC_V_ADC_CTRL_CH_SEL_AIN2 << MXC_F_ADC_CTRL_CH_SEL_POS) /**< CTRL_CH_SEL_AIN2 Setting */ -#define MXC_V_ADC_CTRL_CH_SEL_AIN3 ((uint32_t)0x3UL) /**< CTRL_CH_SEL_AIN3 Value */ -#define MXC_S_ADC_CTRL_CH_SEL_AIN3 (MXC_V_ADC_CTRL_CH_SEL_AIN3 << MXC_F_ADC_CTRL_CH_SEL_POS) /**< CTRL_CH_SEL_AIN3 Setting */ -#define MXC_V_ADC_CTRL_CH_SEL_AIN4 ((uint32_t)0x4UL) /**< CTRL_CH_SEL_AIN4 Value */ -#define MXC_S_ADC_CTRL_CH_SEL_AIN4 (MXC_V_ADC_CTRL_CH_SEL_AIN4 << MXC_F_ADC_CTRL_CH_SEL_POS) /**< CTRL_CH_SEL_AIN4 Setting */ -#define MXC_V_ADC_CTRL_CH_SEL_AIN5 ((uint32_t)0x5UL) /**< CTRL_CH_SEL_AIN5 Value */ -#define MXC_S_ADC_CTRL_CH_SEL_AIN5 (MXC_V_ADC_CTRL_CH_SEL_AIN5 << MXC_F_ADC_CTRL_CH_SEL_POS) /**< CTRL_CH_SEL_AIN5 Setting */ -#define MXC_V_ADC_CTRL_CH_SEL_AIN6 ((uint32_t)0x6UL) /**< CTRL_CH_SEL_AIN6 Value */ -#define MXC_S_ADC_CTRL_CH_SEL_AIN6 (MXC_V_ADC_CTRL_CH_SEL_AIN6 << MXC_F_ADC_CTRL_CH_SEL_POS) /**< CTRL_CH_SEL_AIN6 Setting */ -#define MXC_V_ADC_CTRL_CH_SEL_AIN7 ((uint32_t)0x7UL) /**< CTRL_CH_SEL_AIN7 Value */ -#define MXC_S_ADC_CTRL_CH_SEL_AIN7 (MXC_V_ADC_CTRL_CH_SEL_AIN7 << MXC_F_ADC_CTRL_CH_SEL_POS) /**< CTRL_CH_SEL_AIN7 Setting */ -#define MXC_V_ADC_CTRL_CH_SEL_VCOREA ((uint32_t)0x8UL) /**< CTRL_CH_SEL_VCOREA Value */ -#define MXC_S_ADC_CTRL_CH_SEL_VCOREA (MXC_V_ADC_CTRL_CH_SEL_VCOREA << MXC_F_ADC_CTRL_CH_SEL_POS) /**< CTRL_CH_SEL_VCOREA Setting */ -#define MXC_V_ADC_CTRL_CH_SEL_VCOREB ((uint32_t)0x9UL) /**< CTRL_CH_SEL_VCOREB Value */ -#define MXC_S_ADC_CTRL_CH_SEL_VCOREB (MXC_V_ADC_CTRL_CH_SEL_VCOREB << MXC_F_ADC_CTRL_CH_SEL_POS) /**< CTRL_CH_SEL_VCOREB Setting */ -#define MXC_V_ADC_CTRL_CH_SEL_VRXOUT ((uint32_t)0xAUL) /**< CTRL_CH_SEL_VRXOUT Value */ -#define MXC_S_ADC_CTRL_CH_SEL_VRXOUT (MXC_V_ADC_CTRL_CH_SEL_VRXOUT << MXC_F_ADC_CTRL_CH_SEL_POS) /**< CTRL_CH_SEL_VRXOUT Setting */ -#define MXC_V_ADC_CTRL_CH_SEL_VTXOUT ((uint32_t)0xBUL) /**< CTRL_CH_SEL_VTXOUT Value */ -#define MXC_S_ADC_CTRL_CH_SEL_VTXOUT (MXC_V_ADC_CTRL_CH_SEL_VTXOUT << MXC_F_ADC_CTRL_CH_SEL_POS) /**< CTRL_CH_SEL_VTXOUT Setting */ -#define MXC_V_ADC_CTRL_CH_SEL_VDDA ((uint32_t)0xCUL) /**< CTRL_CH_SEL_VDDA Value */ -#define MXC_S_ADC_CTRL_CH_SEL_VDDA (MXC_V_ADC_CTRL_CH_SEL_VDDA << MXC_F_ADC_CTRL_CH_SEL_POS) /**< CTRL_CH_SEL_VDDA Setting */ -#define MXC_V_ADC_CTRL_CH_SEL_VDDB ((uint32_t)0xDUL) /**< CTRL_CH_SEL_VDDB Value */ -#define MXC_S_ADC_CTRL_CH_SEL_VDDB (MXC_V_ADC_CTRL_CH_SEL_VDDB << MXC_F_ADC_CTRL_CH_SEL_POS) /**< CTRL_CH_SEL_VDDB Setting */ -#define MXC_V_ADC_CTRL_CH_SEL_VDDIO ((uint32_t)0xEUL) /**< CTRL_CH_SEL_VDDIO Value */ -#define MXC_S_ADC_CTRL_CH_SEL_VDDIO (MXC_V_ADC_CTRL_CH_SEL_VDDIO << MXC_F_ADC_CTRL_CH_SEL_POS) /**< CTRL_CH_SEL_VDDIO Setting */ -#define MXC_V_ADC_CTRL_CH_SEL_VDDIOH ((uint32_t)0xFUL) /**< CTRL_CH_SEL_VDDIOH Value */ -#define MXC_S_ADC_CTRL_CH_SEL_VDDIOH (MXC_V_ADC_CTRL_CH_SEL_VDDIOH << MXC_F_ADC_CTRL_CH_SEL_POS) /**< CTRL_CH_SEL_VDDIOH Setting */ -#define MXC_V_ADC_CTRL_CH_SEL_VREGI ((uint32_t)0x10UL) /**< CTRL_CH_SEL_VREGI Value */ -#define MXC_S_ADC_CTRL_CH_SEL_VREGI (MXC_V_ADC_CTRL_CH_SEL_VREGI << MXC_F_ADC_CTRL_CH_SEL_POS) /**< CTRL_CH_SEL_VREGI Setting */ - -#define MXC_F_ADC_CTRL_DIVSEL_POS 17 /**< CTRL_DIVSEL Position */ -#define MXC_F_ADC_CTRL_DIVSEL ((uint32_t)(0x3UL << MXC_F_ADC_CTRL_DIVSEL_POS)) /**< CTRL_DIVSEL Mask */ -#define MXC_V_ADC_CTRL_DIVSEL_DIV1 ((uint32_t)0x0UL) /**< CTRL_DIVSEL_DIV1 Value */ -#define MXC_S_ADC_CTRL_DIVSEL_DIV1 (MXC_V_ADC_CTRL_DIVSEL_DIV1 << MXC_F_ADC_CTRL_DIVSEL_POS) /**< CTRL_DIVSEL_DIV1 Setting */ -#define MXC_V_ADC_CTRL_DIVSEL_DIV2 ((uint32_t)0x1UL) /**< CTRL_DIVSEL_DIV2 Value */ -#define MXC_S_ADC_CTRL_DIVSEL_DIV2 (MXC_V_ADC_CTRL_DIVSEL_DIV2 << MXC_F_ADC_CTRL_DIVSEL_POS) /**< CTRL_DIVSEL_DIV2 Setting */ -#define MXC_V_ADC_CTRL_DIVSEL_DIV3 ((uint32_t)0x2UL) /**< CTRL_DIVSEL_DIV3 Value */ -#define MXC_S_ADC_CTRL_DIVSEL_DIV3 (MXC_V_ADC_CTRL_DIVSEL_DIV3 << MXC_F_ADC_CTRL_DIVSEL_POS) /**< CTRL_DIVSEL_DIV3 Setting */ -#define MXC_V_ADC_CTRL_DIVSEL_DIV4 ((uint32_t)0x3UL) /**< CTRL_DIVSEL_DIV4 Value */ -#define MXC_S_ADC_CTRL_DIVSEL_DIV4 (MXC_V_ADC_CTRL_DIVSEL_DIV4 << MXC_F_ADC_CTRL_DIVSEL_POS) /**< CTRL_DIVSEL_DIV4 Setting */ - -#define MXC_F_ADC_CTRL_DATA_ALIGN_POS 20 /**< CTRL_DATA_ALIGN Position */ -#define MXC_F_ADC_CTRL_DATA_ALIGN ((uint32_t)(0x1UL << MXC_F_ADC_CTRL_DATA_ALIGN_POS)) /**< CTRL_DATA_ALIGN Mask */ - -/**@} end of group ADC_CTRL_Register */ +#define MXC_F_ADC_CTRL0_ADC_EN_POS 0 /**< CTRL0_ADC_EN Position */ +#define MXC_F_ADC_CTRL0_ADC_EN ((uint32_t)(0x1UL << MXC_F_ADC_CTRL0_ADC_EN_POS)) /**< CTRL0_ADC_EN Mask */ + +#define MXC_F_ADC_CTRL0_BIAS_EN_POS 1 /**< CTRL0_BIAS_EN Position */ +#define MXC_F_ADC_CTRL0_BIAS_EN ((uint32_t)(0x1UL << MXC_F_ADC_CTRL0_BIAS_EN_POS)) /**< CTRL0_BIAS_EN Mask */ + +#define MXC_F_ADC_CTRL0_SKIP_CAL_POS 2 /**< CTRL0_SKIP_CAL Position */ +#define MXC_F_ADC_CTRL0_SKIP_CAL ((uint32_t)(0x1UL << MXC_F_ADC_CTRL0_SKIP_CAL_POS)) /**< CTRL0_SKIP_CAL Mask */ + +#define MXC_F_ADC_CTRL0_CHOP_FORCE_POS 3 /**< CTRL0_CHOP_FORCE Position */ +#define MXC_F_ADC_CTRL0_CHOP_FORCE ((uint32_t)(0x1UL << MXC_F_ADC_CTRL0_CHOP_FORCE_POS)) /**< CTRL0_CHOP_FORCE Mask */ + +#define MXC_F_ADC_CTRL0_RESETB_POS 4 /**< CTRL0_RESETB Position */ +#define MXC_F_ADC_CTRL0_RESETB ((uint32_t)(0x1UL << MXC_F_ADC_CTRL0_RESETB_POS)) /**< CTRL0_RESETB Mask */ + +/**@} end of group ADC_CTRL0_Register */ /** * @ingroup adc_registers - * @defgroup ADC_STATUS ADC_STATUS - * @brief ADC Status + * @defgroup ADC_CTRL1 ADC_CTRL1 + * @brief Control Register 1. * @{ */ -#define MXC_F_ADC_STATUS_ACTIVE_POS 0 /**< STATUS_ACTIVE Position */ -#define MXC_F_ADC_STATUS_ACTIVE ((uint32_t)(0x1UL << MXC_F_ADC_STATUS_ACTIVE_POS)) /**< STATUS_ACTIVE Mask */ +#define MXC_F_ADC_CTRL1_START_POS 0 /**< CTRL1_START Position */ +#define MXC_F_ADC_CTRL1_START ((uint32_t)(0x1UL << MXC_F_ADC_CTRL1_START_POS)) /**< CTRL1_START Mask */ -#define MXC_F_ADC_STATUS_AFE_PWR_UP_ACTIVE_POS 2 /**< STATUS_AFE_PWR_UP_ACTIVE Position */ -#define MXC_F_ADC_STATUS_AFE_PWR_UP_ACTIVE ((uint32_t)(0x1UL << MXC_F_ADC_STATUS_AFE_PWR_UP_ACTIVE_POS)) /**< STATUS_AFE_PWR_UP_ACTIVE Mask */ +#define MXC_F_ADC_CTRL1_TRIG_MODE_POS 1 /**< CTRL1_TRIG_MODE Position */ +#define MXC_F_ADC_CTRL1_TRIG_MODE ((uint32_t)(0x1UL << MXC_F_ADC_CTRL1_TRIG_MODE_POS)) /**< CTRL1_TRIG_MODE Mask */ -#define MXC_F_ADC_STATUS_OVERFLOW_POS 3 /**< STATUS_OVERFLOW Position */ -#define MXC_F_ADC_STATUS_OVERFLOW ((uint32_t)(0x1UL << MXC_F_ADC_STATUS_OVERFLOW_POS)) /**< STATUS_OVERFLOW Mask */ +#define MXC_F_ADC_CTRL1_CNV_MODE_POS 2 /**< CTRL1_CNV_MODE Position */ +#define MXC_F_ADC_CTRL1_CNV_MODE ((uint32_t)(0x1UL << MXC_F_ADC_CTRL1_CNV_MODE_POS)) /**< CTRL1_CNV_MODE Mask */ -/**@} end of group ADC_STATUS_Register */ +#define MXC_F_ADC_CTRL1_SAMP_CK_OFF_POS 3 /**< CTRL1_SAMP_CK_OFF Position */ +#define MXC_F_ADC_CTRL1_SAMP_CK_OFF ((uint32_t)(0x1UL << MXC_F_ADC_CTRL1_SAMP_CK_OFF_POS)) /**< CTRL1_SAMP_CK_OFF Mask */ + +#define MXC_F_ADC_CTRL1_TRIG_SEL_POS 4 /**< CTRL1_TRIG_SEL Position */ +#define MXC_F_ADC_CTRL1_TRIG_SEL ((uint32_t)(0x7UL << MXC_F_ADC_CTRL1_TRIG_SEL_POS)) /**< CTRL1_TRIG_SEL Mask */ + +#define MXC_F_ADC_CTRL1_TS_SEL_POS 7 /**< CTRL1_TS_SEL Position */ +#define MXC_F_ADC_CTRL1_TS_SEL ((uint32_t)(0x1UL << MXC_F_ADC_CTRL1_TS_SEL_POS)) /**< CTRL1_TS_SEL Mask */ + +#define MXC_F_ADC_CTRL1_AVG_POS 8 /**< CTRL1_AVG Position */ +#define MXC_F_ADC_CTRL1_AVG ((uint32_t)(0x7UL << MXC_F_ADC_CTRL1_AVG_POS)) /**< CTRL1_AVG Mask */ +#define MXC_V_ADC_CTRL1_AVG_AVG1 ((uint32_t)0x0UL) /**< CTRL1_AVG_AVG1 Value */ +#define MXC_S_ADC_CTRL1_AVG_AVG1 (MXC_V_ADC_CTRL1_AVG_AVG1 << MXC_F_ADC_CTRL1_AVG_POS) /**< CTRL1_AVG_AVG1 Setting */ +#define MXC_V_ADC_CTRL1_AVG_AVG2 ((uint32_t)0x1UL) /**< CTRL1_AVG_AVG2 Value */ +#define MXC_S_ADC_CTRL1_AVG_AVG2 (MXC_V_ADC_CTRL1_AVG_AVG2 << MXC_F_ADC_CTRL1_AVG_POS) /**< CTRL1_AVG_AVG2 Setting */ +#define MXC_V_ADC_CTRL1_AVG_AVG4 ((uint32_t)0x2UL) /**< CTRL1_AVG_AVG4 Value */ +#define MXC_S_ADC_CTRL1_AVG_AVG4 (MXC_V_ADC_CTRL1_AVG_AVG4 << MXC_F_ADC_CTRL1_AVG_POS) /**< CTRL1_AVG_AVG4 Setting */ +#define MXC_V_ADC_CTRL1_AVG_AVG8 ((uint32_t)0x3UL) /**< CTRL1_AVG_AVG8 Value */ +#define MXC_S_ADC_CTRL1_AVG_AVG8 (MXC_V_ADC_CTRL1_AVG_AVG8 << MXC_F_ADC_CTRL1_AVG_POS) /**< CTRL1_AVG_AVG8 Setting */ +#define MXC_V_ADC_CTRL1_AVG_AVG16 ((uint32_t)0x4UL) /**< CTRL1_AVG_AVG16 Value */ +#define MXC_S_ADC_CTRL1_AVG_AVG16 (MXC_V_ADC_CTRL1_AVG_AVG16 << MXC_F_ADC_CTRL1_AVG_POS) /**< CTRL1_AVG_AVG16 Setting */ +#define MXC_V_ADC_CTRL1_AVG_AVG32 ((uint32_t)0x5UL) /**< CTRL1_AVG_AVG32 Value */ +#define MXC_S_ADC_CTRL1_AVG_AVG32 (MXC_V_ADC_CTRL1_AVG_AVG32 << MXC_F_ADC_CTRL1_AVG_POS) /**< CTRL1_AVG_AVG32 Setting */ + +#define MXC_F_ADC_CTRL1_NUM_SLOTS_POS 16 /**< CTRL1_NUM_SLOTS Position */ +#define MXC_F_ADC_CTRL1_NUM_SLOTS ((uint32_t)(0x1FUL << MXC_F_ADC_CTRL1_NUM_SLOTS_POS)) /**< CTRL1_NUM_SLOTS Mask */ + +/**@} end of group ADC_CTRL1_Register */ + +/** + * @ingroup adc_registers + * @defgroup ADC_CLKCTRL ADC_CLKCTRL + * @brief Clock Control Register. + * @{ + */ +#define MXC_F_ADC_CLKCTRL_CLKSEL_POS 0 /**< CLKCTRL_CLKSEL Position */ +#define MXC_F_ADC_CLKCTRL_CLKSEL ((uint32_t)(0x3UL << MXC_F_ADC_CLKCTRL_CLKSEL_POS)) /**< CLKCTRL_CLKSEL Mask */ +#define MXC_V_ADC_CLKCTRL_CLKSEL_HCLK ((uint32_t)0x0UL) /**< CLKCTRL_CLKSEL_HCLK Value */ +#define MXC_S_ADC_CLKCTRL_CLKSEL_HCLK (MXC_V_ADC_CLKCTRL_CLKSEL_HCLK << MXC_F_ADC_CLKCTRL_CLKSEL_POS) /**< CLKCTRL_CLKSEL_HCLK Setting */ +#define MXC_V_ADC_CLKCTRL_CLKSEL_CLK_ADC0 ((uint32_t)0x1UL) /**< CLKCTRL_CLKSEL_CLK_ADC0 Value */ +#define MXC_S_ADC_CLKCTRL_CLKSEL_CLK_ADC0 (MXC_V_ADC_CLKCTRL_CLKSEL_CLK_ADC0 << MXC_F_ADC_CLKCTRL_CLKSEL_POS) /**< CLKCTRL_CLKSEL_CLK_ADC0 Setting */ +#define MXC_V_ADC_CLKCTRL_CLKSEL_CLK_ADC1 ((uint32_t)0x2UL) /**< CLKCTRL_CLKSEL_CLK_ADC1 Value */ +#define MXC_S_ADC_CLKCTRL_CLKSEL_CLK_ADC1 (MXC_V_ADC_CLKCTRL_CLKSEL_CLK_ADC1 << MXC_F_ADC_CLKCTRL_CLKSEL_POS) /**< CLKCTRL_CLKSEL_CLK_ADC1 Setting */ +#define MXC_V_ADC_CLKCTRL_CLKSEL_CLK_ADC2 ((uint32_t)0x3UL) /**< CLKCTRL_CLKSEL_CLK_ADC2 Value */ +#define MXC_S_ADC_CLKCTRL_CLKSEL_CLK_ADC2 (MXC_V_ADC_CLKCTRL_CLKSEL_CLK_ADC2 << MXC_F_ADC_CLKCTRL_CLKSEL_POS) /**< CLKCTRL_CLKSEL_CLK_ADC2 Setting */ + +#define MXC_F_ADC_CLKCTRL_CLKDIV_POS 4 /**< CLKCTRL_CLKDIV Position */ +#define MXC_F_ADC_CLKCTRL_CLKDIV ((uint32_t)(0x7UL << MXC_F_ADC_CLKCTRL_CLKDIV_POS)) /**< CLKCTRL_CLKDIV Mask */ +#define MXC_V_ADC_CLKCTRL_CLKDIV_DIV2 ((uint32_t)0x0UL) /**< CLKCTRL_CLKDIV_DIV2 Value */ +#define MXC_S_ADC_CLKCTRL_CLKDIV_DIV2 (MXC_V_ADC_CLKCTRL_CLKDIV_DIV2 << MXC_F_ADC_CLKCTRL_CLKDIV_POS) /**< CLKCTRL_CLKDIV_DIV2 Setting */ +#define MXC_V_ADC_CLKCTRL_CLKDIV_DIV4 ((uint32_t)0x1UL) /**< CLKCTRL_CLKDIV_DIV4 Value */ +#define MXC_S_ADC_CLKCTRL_CLKDIV_DIV4 (MXC_V_ADC_CLKCTRL_CLKDIV_DIV4 << MXC_F_ADC_CLKCTRL_CLKDIV_POS) /**< CLKCTRL_CLKDIV_DIV4 Setting */ +#define MXC_V_ADC_CLKCTRL_CLKDIV_DIV8 ((uint32_t)0x2UL) /**< CLKCTRL_CLKDIV_DIV8 Value */ +#define MXC_S_ADC_CLKCTRL_CLKDIV_DIV8 (MXC_V_ADC_CLKCTRL_CLKDIV_DIV8 << MXC_F_ADC_CLKCTRL_CLKDIV_POS) /**< CLKCTRL_CLKDIV_DIV8 Setting */ +#define MXC_V_ADC_CLKCTRL_CLKDIV_DIV16 ((uint32_t)0x3UL) /**< CLKCTRL_CLKDIV_DIV16 Value */ +#define MXC_S_ADC_CLKCTRL_CLKDIV_DIV16 (MXC_V_ADC_CLKCTRL_CLKDIV_DIV16 << MXC_F_ADC_CLKCTRL_CLKDIV_POS) /**< CLKCTRL_CLKDIV_DIV16 Setting */ +#define MXC_V_ADC_CLKCTRL_CLKDIV_DIV1 ((uint32_t)0x4UL) /**< CLKCTRL_CLKDIV_DIV1 Value */ +#define MXC_S_ADC_CLKCTRL_CLKDIV_DIV1 (MXC_V_ADC_CLKCTRL_CLKDIV_DIV1 << MXC_F_ADC_CLKCTRL_CLKDIV_POS) /**< CLKCTRL_CLKDIV_DIV1 Setting */ + +/**@} end of group ADC_CLKCTRL_Register */ + +/** + * @ingroup adc_registers + * @defgroup ADC_SAMPCLKCTRL ADC_SAMPCLKCTRL + * @brief Sample Clock Control Register. + * @{ + */ +#define MXC_F_ADC_SAMPCLKCTRL_TRACK_CNT_POS 0 /**< SAMPCLKCTRL_TRACK_CNT Position */ +#define MXC_F_ADC_SAMPCLKCTRL_TRACK_CNT ((uint32_t)(0xFFUL << MXC_F_ADC_SAMPCLKCTRL_TRACK_CNT_POS)) /**< SAMPCLKCTRL_TRACK_CNT Mask */ + +#define MXC_F_ADC_SAMPCLKCTRL_IDLE_CNT_POS 16 /**< SAMPCLKCTRL_IDLE_CNT Position */ +#define MXC_F_ADC_SAMPCLKCTRL_IDLE_CNT ((uint32_t)(0xFFFFUL << MXC_F_ADC_SAMPCLKCTRL_IDLE_CNT_POS)) /**< SAMPCLKCTRL_IDLE_CNT Mask */ + +/**@} end of group ADC_SAMPCLKCTRL_Register */ + +/** + * @ingroup adc_registers + * @defgroup ADC_CHSEL0 ADC_CHSEL0 + * @brief Channel Select Register 0. + * @{ + */ +#define MXC_F_ADC_CHSEL0_SLOT0_ID_POS 0 /**< CHSEL0_SLOT0_ID Position */ +#define MXC_F_ADC_CHSEL0_SLOT0_ID ((uint32_t)(0x1FUL << MXC_F_ADC_CHSEL0_SLOT0_ID_POS)) /**< CHSEL0_SLOT0_ID Mask */ + +#define MXC_F_ADC_CHSEL0_SLOT1_ID_POS 8 /**< CHSEL0_SLOT1_ID Position */ +#define MXC_F_ADC_CHSEL0_SLOT1_ID ((uint32_t)(0x1FUL << MXC_F_ADC_CHSEL0_SLOT1_ID_POS)) /**< CHSEL0_SLOT1_ID Mask */ + +#define MXC_F_ADC_CHSEL0_SLOT2_ID_POS 16 /**< CHSEL0_SLOT2_ID Position */ +#define MXC_F_ADC_CHSEL0_SLOT2_ID ((uint32_t)(0x1FUL << MXC_F_ADC_CHSEL0_SLOT2_ID_POS)) /**< CHSEL0_SLOT2_ID Mask */ + +#define MXC_F_ADC_CHSEL0_SLOT3_ID_POS 24 /**< CHSEL0_SLOT3_ID Position */ +#define MXC_F_ADC_CHSEL0_SLOT3_ID ((uint32_t)(0x1FUL << MXC_F_ADC_CHSEL0_SLOT3_ID_POS)) /**< CHSEL0_SLOT3_ID Mask */ + +/**@} end of group ADC_CHSEL0_Register */ + +/** + * @ingroup adc_registers + * @defgroup ADC_CHSEL1 ADC_CHSEL1 + * @brief Channel Select Register 1. + * @{ + */ +#define MXC_F_ADC_CHSEL1_SLOT4_ID_POS 0 /**< CHSEL1_SLOT4_ID Position */ +#define MXC_F_ADC_CHSEL1_SLOT4_ID ((uint32_t)(0x1FUL << MXC_F_ADC_CHSEL1_SLOT4_ID_POS)) /**< CHSEL1_SLOT4_ID Mask */ + +#define MXC_F_ADC_CHSEL1_SLOT5_ID_POS 8 /**< CHSEL1_SLOT5_ID Position */ +#define MXC_F_ADC_CHSEL1_SLOT5_ID ((uint32_t)(0x1FUL << MXC_F_ADC_CHSEL1_SLOT5_ID_POS)) /**< CHSEL1_SLOT5_ID Mask */ + +#define MXC_F_ADC_CHSEL1_SLOT6_ID_POS 16 /**< CHSEL1_SLOT6_ID Position */ +#define MXC_F_ADC_CHSEL1_SLOT6_ID ((uint32_t)(0x1FUL << MXC_F_ADC_CHSEL1_SLOT6_ID_POS)) /**< CHSEL1_SLOT6_ID Mask */ + +#define MXC_F_ADC_CHSEL1_SLOT7_ID_POS 24 /**< CHSEL1_SLOT7_ID Position */ +#define MXC_F_ADC_CHSEL1_SLOT7_ID ((uint32_t)(0x1FUL << MXC_F_ADC_CHSEL1_SLOT7_ID_POS)) /**< CHSEL1_SLOT7_ID Mask */ + +/**@} end of group ADC_CHSEL1_Register */ + +/** + * @ingroup adc_registers + * @defgroup ADC_CHSEL2 ADC_CHSEL2 + * @brief Channel Select Register 2. + * @{ + */ +#define MXC_F_ADC_CHSEL2_SLOT8_ID_POS 0 /**< CHSEL2_SLOT8_ID Position */ +#define MXC_F_ADC_CHSEL2_SLOT8_ID ((uint32_t)(0x1FUL << MXC_F_ADC_CHSEL2_SLOT8_ID_POS)) /**< CHSEL2_SLOT8_ID Mask */ + +#define MXC_F_ADC_CHSEL2_SLOT9_ID_POS 8 /**< CHSEL2_SLOT9_ID Position */ +#define MXC_F_ADC_CHSEL2_SLOT9_ID ((uint32_t)(0x1FUL << MXC_F_ADC_CHSEL2_SLOT9_ID_POS)) /**< CHSEL2_SLOT9_ID Mask */ + +#define MXC_F_ADC_CHSEL2_SLOT10_ID_POS 16 /**< CHSEL2_SLOT10_ID Position */ +#define MXC_F_ADC_CHSEL2_SLOT10_ID ((uint32_t)(0x1FUL << MXC_F_ADC_CHSEL2_SLOT10_ID_POS)) /**< CHSEL2_SLOT10_ID Mask */ + +#define MXC_F_ADC_CHSEL2_SLOT11_ID_POS 24 /**< CHSEL2_SLOT11_ID Position */ +#define MXC_F_ADC_CHSEL2_SLOT11_ID ((uint32_t)(0x1FUL << MXC_F_ADC_CHSEL2_SLOT11_ID_POS)) /**< CHSEL2_SLOT11_ID Mask */ + +/**@} end of group ADC_CHSEL2_Register */ + +/** + * @ingroup adc_registers + * @defgroup ADC_CHSEL3 ADC_CHSEL3 + * @brief Channel Select Register 3. + * @{ + */ +#define MXC_F_ADC_CHSEL3_SLOT12_ID_POS 0 /**< CHSEL3_SLOT12_ID Position */ +#define MXC_F_ADC_CHSEL3_SLOT12_ID ((uint32_t)(0x1FUL << MXC_F_ADC_CHSEL3_SLOT12_ID_POS)) /**< CHSEL3_SLOT12_ID Mask */ + +#define MXC_F_ADC_CHSEL3_SLOT13_ID_POS 8 /**< CHSEL3_SLOT13_ID Position */ +#define MXC_F_ADC_CHSEL3_SLOT13_ID ((uint32_t)(0x1FUL << MXC_F_ADC_CHSEL3_SLOT13_ID_POS)) /**< CHSEL3_SLOT13_ID Mask */ + +#define MXC_F_ADC_CHSEL3_SLOT14_ID_POS 16 /**< CHSEL3_SLOT14_ID Position */ +#define MXC_F_ADC_CHSEL3_SLOT14_ID ((uint32_t)(0x1FUL << MXC_F_ADC_CHSEL3_SLOT14_ID_POS)) /**< CHSEL3_SLOT14_ID Mask */ + +#define MXC_F_ADC_CHSEL3_SLOT15_ID_POS 24 /**< CHSEL3_SLOT15_ID Position */ +#define MXC_F_ADC_CHSEL3_SLOT15_ID ((uint32_t)(0x1FUL << MXC_F_ADC_CHSEL3_SLOT15_ID_POS)) /**< CHSEL3_SLOT15_ID Mask */ + +/**@} end of group ADC_CHSEL3_Register */ + +/** + * @ingroup adc_registers + * @defgroup ADC_RESTART ADC_RESTART + * @brief Restart Count Control Register + * @{ + */ +#define MXC_F_ADC_RESTART_CNT_POS 0 /**< RESTART_CNT Position */ +#define MXC_F_ADC_RESTART_CNT ((uint32_t)(0xFFFFUL << MXC_F_ADC_RESTART_CNT_POS)) /**< RESTART_CNT Mask */ + +/**@} end of group ADC_RESTART_Register */ + +/** + * @ingroup adc_registers + * @defgroup ADC_DATAFMT ADC_DATAFMT + * @brief Channel Data Format Register + * @{ + */ +#define MXC_F_ADC_DATAFMT_MODE_POS 0 /**< DATAFMT_MODE Position */ +#define MXC_F_ADC_DATAFMT_MODE ((uint32_t)(0xFFFFFFFFUL << MXC_F_ADC_DATAFMT_MODE_POS)) /**< DATAFMT_MODE Mask */ + +/**@} end of group ADC_DATAFMT_Register */ + +/** + * @ingroup adc_registers + * @defgroup ADC_FIFODMACTRL ADC_FIFODMACTRL + * @brief FIFO and DMA control + * @{ + */ +#define MXC_F_ADC_FIFODMACTRL_DMA_EN_POS 0 /**< FIFODMACTRL_DMA_EN Position */ +#define MXC_F_ADC_FIFODMACTRL_DMA_EN ((uint32_t)(0x1UL << MXC_F_ADC_FIFODMACTRL_DMA_EN_POS)) /**< FIFODMACTRL_DMA_EN Mask */ + +#define MXC_F_ADC_FIFODMACTRL_FLUSH_POS 1 /**< FIFODMACTRL_FLUSH Position */ +#define MXC_F_ADC_FIFODMACTRL_FLUSH ((uint32_t)(0x1UL << MXC_F_ADC_FIFODMACTRL_FLUSH_POS)) /**< FIFODMACTRL_FLUSH Mask */ + +#define MXC_F_ADC_FIFODMACTRL_DATA_FORMAT_POS 2 /**< FIFODMACTRL_DATA_FORMAT Position */ +#define MXC_F_ADC_FIFODMACTRL_DATA_FORMAT ((uint32_t)(0x3UL << MXC_F_ADC_FIFODMACTRL_DATA_FORMAT_POS)) /**< FIFODMACTRL_DATA_FORMAT Mask */ +#define MXC_V_ADC_FIFODMACTRL_DATA_FORMAT_DATA_STATUS ((uint32_t)0x0UL) /**< FIFODMACTRL_DATA_FORMAT_DATA_STATUS Value */ +#define MXC_S_ADC_FIFODMACTRL_DATA_FORMAT_DATA_STATUS (MXC_V_ADC_FIFODMACTRL_DATA_FORMAT_DATA_STATUS << MXC_F_ADC_FIFODMACTRL_DATA_FORMAT_POS) /**< FIFODMACTRL_DATA_FORMAT_DATA_STATUS Setting */ +#define MXC_V_ADC_FIFODMACTRL_DATA_FORMAT_DATA_ONLY ((uint32_t)0x1UL) /**< FIFODMACTRL_DATA_FORMAT_DATA_ONLY Value */ +#define MXC_S_ADC_FIFODMACTRL_DATA_FORMAT_DATA_ONLY (MXC_V_ADC_FIFODMACTRL_DATA_FORMAT_DATA_ONLY << MXC_F_ADC_FIFODMACTRL_DATA_FORMAT_POS) /**< FIFODMACTRL_DATA_FORMAT_DATA_ONLY Setting */ +#define MXC_V_ADC_FIFODMACTRL_DATA_FORMAT_RAW_DATA_ONLY ((uint32_t)0x2UL) /**< FIFODMACTRL_DATA_FORMAT_RAW_DATA_ONLY Value */ +#define MXC_S_ADC_FIFODMACTRL_DATA_FORMAT_RAW_DATA_ONLY (MXC_V_ADC_FIFODMACTRL_DATA_FORMAT_RAW_DATA_ONLY << MXC_F_ADC_FIFODMACTRL_DATA_FORMAT_POS) /**< FIFODMACTRL_DATA_FORMAT_RAW_DATA_ONLY Setting */ + +#define MXC_F_ADC_FIFODMACTRL_THRESH_POS 8 /**< FIFODMACTRL_THRESH Position */ +#define MXC_F_ADC_FIFODMACTRL_THRESH ((uint32_t)(0xFFUL << MXC_F_ADC_FIFODMACTRL_THRESH_POS)) /**< FIFODMACTRL_THRESH Mask */ + +/**@} end of group ADC_FIFODMACTRL_Register */ /** * @ingroup adc_registers * @defgroup ADC_DATA ADC_DATA - * @brief ADC Output Data + * @brief Data Register (FIFO). * @{ */ #define MXC_F_ADC_DATA_DATA_POS 0 /**< DATA_DATA Position */ #define MXC_F_ADC_DATA_DATA ((uint32_t)(0xFFFFUL << MXC_F_ADC_DATA_DATA_POS)) /**< DATA_DATA Mask */ +#define MXC_F_ADC_DATA_CHAN_POS 16 /**< DATA_CHAN Position */ +#define MXC_F_ADC_DATA_CHAN ((uint32_t)(0x1FUL << MXC_F_ADC_DATA_CHAN_POS)) /**< DATA_CHAN Mask */ + +#define MXC_F_ADC_DATA_INVALID_POS 24 /**< DATA_INVALID Position */ +#define MXC_F_ADC_DATA_INVALID ((uint32_t)(0x1UL << MXC_F_ADC_DATA_INVALID_POS)) /**< DATA_INVALID Mask */ + +#define MXC_F_ADC_DATA_CLIPPED_POS 31 /**< DATA_CLIPPED Position */ +#define MXC_F_ADC_DATA_CLIPPED ((uint32_t)(0x1UL << MXC_F_ADC_DATA_CLIPPED_POS)) /**< DATA_CLIPPED Mask */ + /**@} end of group ADC_DATA_Register */ /** * @ingroup adc_registers - * @defgroup ADC_INTR ADC_INTR - * @brief ADC Interrupt Control Register + * @defgroup ADC_STATUS ADC_STATUS + * @brief Status Register * @{ */ -#define MXC_F_ADC_INTR_DONE_IE_POS 0 /**< INTR_DONE_IE Position */ -#define MXC_F_ADC_INTR_DONE_IE ((uint32_t)(0x1UL << MXC_F_ADC_INTR_DONE_IE_POS)) /**< INTR_DONE_IE Mask */ +#define MXC_F_ADC_STATUS_READY_POS 0 /**< STATUS_READY Position */ +#define MXC_F_ADC_STATUS_READY ((uint32_t)(0x1UL << MXC_F_ADC_STATUS_READY_POS)) /**< STATUS_READY Mask */ -#define MXC_F_ADC_INTR_REF_READY_IE_POS 1 /**< INTR_REF_READY_IE Position */ -#define MXC_F_ADC_INTR_REF_READY_IE ((uint32_t)(0x1UL << MXC_F_ADC_INTR_REF_READY_IE_POS)) /**< INTR_REF_READY_IE Mask */ +#define MXC_F_ADC_STATUS_EMPTY_POS 1 /**< STATUS_EMPTY Position */ +#define MXC_F_ADC_STATUS_EMPTY ((uint32_t)(0x1UL << MXC_F_ADC_STATUS_EMPTY_POS)) /**< STATUS_EMPTY Mask */ + +#define MXC_F_ADC_STATUS_FULL_POS 2 /**< STATUS_FULL Position */ +#define MXC_F_ADC_STATUS_FULL ((uint32_t)(0x1UL << MXC_F_ADC_STATUS_FULL_POS)) /**< STATUS_FULL Mask */ + +#define MXC_F_ADC_STATUS_FIFO_LEVEL_POS 8 /**< STATUS_FIFO_LEVEL Position */ +#define MXC_F_ADC_STATUS_FIFO_LEVEL ((uint32_t)(0xFFUL << MXC_F_ADC_STATUS_FIFO_LEVEL_POS)) /**< STATUS_FIFO_LEVEL Mask */ + +/**@} end of group ADC_STATUS_Register */ -#define MXC_F_ADC_INTR_HI_LIMIT_IE_POS 2 /**< INTR_HI_LIMIT_IE Position */ -#define MXC_F_ADC_INTR_HI_LIMIT_IE ((uint32_t)(0x1UL << MXC_F_ADC_INTR_HI_LIMIT_IE_POS)) /**< INTR_HI_LIMIT_IE Mask */ +/** + * @ingroup adc_registers + * @defgroup ADC_CHSTATUS ADC_CHSTATUS + * @brief Channel Status + * @{ + */ +#define MXC_F_ADC_CHSTATUS_CLIPPED_POS 0 /**< CHSTATUS_CLIPPED Position */ +#define MXC_F_ADC_CHSTATUS_CLIPPED ((uint32_t)(0xFFFFFFFFUL << MXC_F_ADC_CHSTATUS_CLIPPED_POS)) /**< CHSTATUS_CLIPPED Mask */ -#define MXC_F_ADC_INTR_LO_LIMIT_IE_POS 3 /**< INTR_LO_LIMIT_IE Position */ -#define MXC_F_ADC_INTR_LO_LIMIT_IE ((uint32_t)(0x1UL << MXC_F_ADC_INTR_LO_LIMIT_IE_POS)) /**< INTR_LO_LIMIT_IE Mask */ +/**@} end of group ADC_CHSTATUS_Register */ -#define MXC_F_ADC_INTR_OVERFLOW_IE_POS 4 /**< INTR_OVERFLOW_IE Position */ -#define MXC_F_ADC_INTR_OVERFLOW_IE ((uint32_t)(0x1UL << MXC_F_ADC_INTR_OVERFLOW_IE_POS)) /**< INTR_OVERFLOW_IE Mask */ +/** + * @ingroup adc_registers + * @defgroup ADC_INTEN ADC_INTEN + * @brief Interrupt Enable Register. + * @{ + */ +#define MXC_F_ADC_INTEN_READY_POS 0 /**< INTEN_READY Position */ +#define MXC_F_ADC_INTEN_READY ((uint32_t)(0x1UL << MXC_F_ADC_INTEN_READY_POS)) /**< INTEN_READY Mask */ -#define MXC_F_ADC_INTR_DONE_IF_POS 16 /**< INTR_DONE_IF Position */ -#define MXC_F_ADC_INTR_DONE_IF ((uint32_t)(0x1UL << MXC_F_ADC_INTR_DONE_IF_POS)) /**< INTR_DONE_IF Mask */ +#define MXC_F_ADC_INTEN_ABORT_POS 2 /**< INTEN_ABORT Position */ +#define MXC_F_ADC_INTEN_ABORT ((uint32_t)(0x1UL << MXC_F_ADC_INTEN_ABORT_POS)) /**< INTEN_ABORT Mask */ -#define MXC_F_ADC_INTR_REF_READY_IF_POS 17 /**< INTR_REF_READY_IF Position */ -#define MXC_F_ADC_INTR_REF_READY_IF ((uint32_t)(0x1UL << MXC_F_ADC_INTR_REF_READY_IF_POS)) /**< INTR_REF_READY_IF Mask */ +#define MXC_F_ADC_INTEN_START_DET_POS 3 /**< INTEN_START_DET Position */ +#define MXC_F_ADC_INTEN_START_DET ((uint32_t)(0x1UL << MXC_F_ADC_INTEN_START_DET_POS)) /**< INTEN_START_DET Mask */ -#define MXC_F_ADC_INTR_HI_LIMIT_IF_POS 18 /**< INTR_HI_LIMIT_IF Position */ -#define MXC_F_ADC_INTR_HI_LIMIT_IF ((uint32_t)(0x1UL << MXC_F_ADC_INTR_HI_LIMIT_IF_POS)) /**< INTR_HI_LIMIT_IF Mask */ +#define MXC_F_ADC_INTEN_SEQ_STARTED_POS 4 /**< INTEN_SEQ_STARTED Position */ +#define MXC_F_ADC_INTEN_SEQ_STARTED ((uint32_t)(0x1UL << MXC_F_ADC_INTEN_SEQ_STARTED_POS)) /**< INTEN_SEQ_STARTED Mask */ -#define MXC_F_ADC_INTR_LO_LIMIT_IF_POS 19 /**< INTR_LO_LIMIT_IF Position */ -#define MXC_F_ADC_INTR_LO_LIMIT_IF ((uint32_t)(0x1UL << MXC_F_ADC_INTR_LO_LIMIT_IF_POS)) /**< INTR_LO_LIMIT_IF Mask */ +#define MXC_F_ADC_INTEN_SEQ_DONE_POS 5 /**< INTEN_SEQ_DONE Position */ +#define MXC_F_ADC_INTEN_SEQ_DONE ((uint32_t)(0x1UL << MXC_F_ADC_INTEN_SEQ_DONE_POS)) /**< INTEN_SEQ_DONE Mask */ -#define MXC_F_ADC_INTR_OVERFLOW_IF_POS 20 /**< INTR_OVERFLOW_IF Position */ -#define MXC_F_ADC_INTR_OVERFLOW_IF ((uint32_t)(0x1UL << MXC_F_ADC_INTR_OVERFLOW_IF_POS)) /**< INTR_OVERFLOW_IF Mask */ +#define MXC_F_ADC_INTEN_CONV_DONE_POS 6 /**< INTEN_CONV_DONE Position */ +#define MXC_F_ADC_INTEN_CONV_DONE ((uint32_t)(0x1UL << MXC_F_ADC_INTEN_CONV_DONE_POS)) /**< INTEN_CONV_DONE Mask */ -#define MXC_F_ADC_INTR_PENDING_POS 22 /**< INTR_PENDING Position */ -#define MXC_F_ADC_INTR_PENDING ((uint32_t)(0x1UL << MXC_F_ADC_INTR_PENDING_POS)) /**< INTR_PENDING Mask */ +#define MXC_F_ADC_INTEN_CLIPPED_POS 7 /**< INTEN_CLIPPED Position */ +#define MXC_F_ADC_INTEN_CLIPPED ((uint32_t)(0x1UL << MXC_F_ADC_INTEN_CLIPPED_POS)) /**< INTEN_CLIPPED Mask */ -/**@} end of group ADC_INTR_Register */ +#define MXC_F_ADC_INTEN_FIFO_LVL_POS 8 /**< INTEN_FIFO_LVL Position */ +#define MXC_F_ADC_INTEN_FIFO_LVL ((uint32_t)(0x1UL << MXC_F_ADC_INTEN_FIFO_LVL_POS)) /**< INTEN_FIFO_LVL Mask */ + +#define MXC_F_ADC_INTEN_FIFO_UFL_POS 9 /**< INTEN_FIFO_UFL Position */ +#define MXC_F_ADC_INTEN_FIFO_UFL ((uint32_t)(0x1UL << MXC_F_ADC_INTEN_FIFO_UFL_POS)) /**< INTEN_FIFO_UFL Mask */ + +#define MXC_F_ADC_INTEN_FIFO_OFL_POS 10 /**< INTEN_FIFO_OFL Position */ +#define MXC_F_ADC_INTEN_FIFO_OFL ((uint32_t)(0x1UL << MXC_F_ADC_INTEN_FIFO_OFL_POS)) /**< INTEN_FIFO_OFL Mask */ + +/**@} end of group ADC_INTEN_Register */ + +/** + * @ingroup adc_registers + * @defgroup ADC_INTFL ADC_INTFL + * @brief Interrupt Flags Register. + * @{ + */ +#define MXC_F_ADC_INTFL_READY_POS 0 /**< INTFL_READY Position */ +#define MXC_F_ADC_INTFL_READY ((uint32_t)(0x1UL << MXC_F_ADC_INTFL_READY_POS)) /**< INTFL_READY Mask */ + +#define MXC_F_ADC_INTFL_ABORT_POS 2 /**< INTFL_ABORT Position */ +#define MXC_F_ADC_INTFL_ABORT ((uint32_t)(0x1UL << MXC_F_ADC_INTFL_ABORT_POS)) /**< INTFL_ABORT Mask */ + +#define MXC_F_ADC_INTFL_START_DET_POS 3 /**< INTFL_START_DET Position */ +#define MXC_F_ADC_INTFL_START_DET ((uint32_t)(0x1UL << MXC_F_ADC_INTFL_START_DET_POS)) /**< INTFL_START_DET Mask */ + +#define MXC_F_ADC_INTFL_SEQ_STARTED_POS 4 /**< INTFL_SEQ_STARTED Position */ +#define MXC_F_ADC_INTFL_SEQ_STARTED ((uint32_t)(0x1UL << MXC_F_ADC_INTFL_SEQ_STARTED_POS)) /**< INTFL_SEQ_STARTED Mask */ + +#define MXC_F_ADC_INTFL_SEQ_DONE_POS 5 /**< INTFL_SEQ_DONE Position */ +#define MXC_F_ADC_INTFL_SEQ_DONE ((uint32_t)(0x1UL << MXC_F_ADC_INTFL_SEQ_DONE_POS)) /**< INTFL_SEQ_DONE Mask */ + +#define MXC_F_ADC_INTFL_CONV_DONE_POS 6 /**< INTFL_CONV_DONE Position */ +#define MXC_F_ADC_INTFL_CONV_DONE ((uint32_t)(0x1UL << MXC_F_ADC_INTFL_CONV_DONE_POS)) /**< INTFL_CONV_DONE Mask */ + +#define MXC_F_ADC_INTFL_CLIPPED_POS 7 /**< INTFL_CLIPPED Position */ +#define MXC_F_ADC_INTFL_CLIPPED ((uint32_t)(0x1UL << MXC_F_ADC_INTFL_CLIPPED_POS)) /**< INTFL_CLIPPED Mask */ + +#define MXC_F_ADC_INTFL_FIFO_LVL_POS 8 /**< INTFL_FIFO_LVL Position */ +#define MXC_F_ADC_INTFL_FIFO_LVL ((uint32_t)(0x1UL << MXC_F_ADC_INTFL_FIFO_LVL_POS)) /**< INTFL_FIFO_LVL Mask */ + +#define MXC_F_ADC_INTFL_FIFO_UFL_POS 9 /**< INTFL_FIFO_UFL Position */ +#define MXC_F_ADC_INTFL_FIFO_UFL ((uint32_t)(0x1UL << MXC_F_ADC_INTFL_FIFO_UFL_POS)) /**< INTFL_FIFO_UFL Mask */ + +#define MXC_F_ADC_INTFL_FIFO_OFL_POS 10 /**< INTFL_FIFO_OFL Position */ +#define MXC_F_ADC_INTFL_FIFO_OFL ((uint32_t)(0x1UL << MXC_F_ADC_INTFL_FIFO_OFL_POS)) /**< INTFL_FIFO_OFL Mask */ + +/**@} end of group ADC_INTFL_Register */ + +/** + * @ingroup adc_registers + * @defgroup ADC_SFRADDROFFSET ADC_SFRADDROFFSET + * @brief SFR Address Offset Register + * @{ + */ +#define MXC_F_ADC_SFRADDROFFSET_OFFSET_POS 0 /**< SFRADDROFFSET_OFFSET Position */ +#define MXC_F_ADC_SFRADDROFFSET_OFFSET ((uint32_t)(0xFFUL << MXC_F_ADC_SFRADDROFFSET_OFFSET_POS)) /**< SFRADDROFFSET_OFFSET Mask */ + +/**@} end of group ADC_SFRADDROFFSET_Register */ /** * @ingroup adc_registers - * @defgroup ADC_LIMIT ADC_LIMIT - * @brief ADC Limit + * @defgroup ADC_SFRADDR ADC_SFRADDR + * @brief SFR Address Register * @{ */ -#define MXC_F_ADC_LIMIT_CH_LO_LIMIT_POS 0 /**< LIMIT_CH_LO_LIMIT Position */ -#define MXC_F_ADC_LIMIT_CH_LO_LIMIT ((uint32_t)(0x3FFUL << MXC_F_ADC_LIMIT_CH_LO_LIMIT_POS)) /**< LIMIT_CH_LO_LIMIT Mask */ +#define MXC_F_ADC_SFRADDR_ADDR_POS 0 /**< SFRADDR_ADDR Position */ +#define MXC_F_ADC_SFRADDR_ADDR ((uint32_t)(0xFFUL << MXC_F_ADC_SFRADDR_ADDR_POS)) /**< SFRADDR_ADDR Mask */ -#define MXC_F_ADC_LIMIT_CH_HI_LIMIT_POS 12 /**< LIMIT_CH_HI_LIMIT Position */ -#define MXC_F_ADC_LIMIT_CH_HI_LIMIT ((uint32_t)(0x3FFUL << MXC_F_ADC_LIMIT_CH_HI_LIMIT_POS)) /**< LIMIT_CH_HI_LIMIT Mask */ +/**@} end of group ADC_SFRADDR_Register */ -#define MXC_F_ADC_LIMIT_CH_SEL_POS 24 /**< LIMIT_CH_SEL Position */ -#define MXC_F_ADC_LIMIT_CH_SEL ((uint32_t)(0xFUL << MXC_F_ADC_LIMIT_CH_SEL_POS)) /**< LIMIT_CH_SEL Mask */ +/** + * @ingroup adc_registers + * @defgroup ADC_SFRWRDATA ADC_SFRWRDATA + * @brief SFR Write Data Register + * @{ + */ +#define MXC_F_ADC_SFRWRDATA_DATA_POS 0 /**< SFRWRDATA_DATA Position */ +#define MXC_F_ADC_SFRWRDATA_DATA ((uint32_t)(0xFFUL << MXC_F_ADC_SFRWRDATA_DATA_POS)) /**< SFRWRDATA_DATA Mask */ -#define MXC_F_ADC_LIMIT_CH_LO_LIMIT_EN_POS 28 /**< LIMIT_CH_LO_LIMIT_EN Position */ -#define MXC_F_ADC_LIMIT_CH_LO_LIMIT_EN ((uint32_t)(0x1UL << MXC_F_ADC_LIMIT_CH_LO_LIMIT_EN_POS)) /**< LIMIT_CH_LO_LIMIT_EN Mask */ +/**@} end of group ADC_SFRWRDATA_Register */ -#define MXC_F_ADC_LIMIT_CH_HI_LIMIT_EN_POS 29 /**< LIMIT_CH_HI_LIMIT_EN Position */ -#define MXC_F_ADC_LIMIT_CH_HI_LIMIT_EN ((uint32_t)(0x1UL << MXC_F_ADC_LIMIT_CH_HI_LIMIT_EN_POS)) /**< LIMIT_CH_HI_LIMIT_EN Mask */ +/** + * @ingroup adc_registers + * @defgroup ADC_SFRRDDATA ADC_SFRRDDATA + * @brief SFR Read Data Register + * @{ + */ +#define MXC_F_ADC_SFRRDDATA_DATA_POS 0 /**< SFRRDDATA_DATA Position */ +#define MXC_F_ADC_SFRRDDATA_DATA ((uint32_t)(0xFFUL << MXC_F_ADC_SFRRDDATA_DATA_POS)) /**< SFRRDDATA_DATA Mask */ -/**@} end of group ADC_LIMIT_Register */ +/**@} end of group ADC_SFRRDDATA_Register */ /** * @ingroup adc_registers - * @defgroup ADC_DECCNT ADC_DECCNT - * @brief ADC Decimation Count. + * @defgroup ADC_SFRSTATUS ADC_SFRSTATUS + * @brief SFR Status Register * @{ */ -#define MXC_F_ADC_DECCNT_DELAY_POS 0 /**< DECCNT_DELAY Position */ -#define MXC_F_ADC_DECCNT_DELAY ((uint32_t)(0xFFFFFFFFUL << MXC_F_ADC_DECCNT_DELAY_POS)) /**< DECCNT_DELAY Mask */ +#define MXC_F_ADC_SFRSTATUS_NACK_POS 0 /**< SFRSTATUS_NACK Position */ +#define MXC_F_ADC_SFRSTATUS_NACK ((uint32_t)(0x1UL << MXC_F_ADC_SFRSTATUS_NACK_POS)) /**< SFRSTATUS_NACK Mask */ -/**@} end of group ADC_DECCNT_Register */ +/**@} end of group ADC_SFRSTATUS_Register */ #ifdef __cplusplus } #endif -#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_ADC_REGS_H_ +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32672_INCLUDE_ADC_REGS_H_ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32572/Include/aes_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32572/Include/aes_regs.h new file mode 100644 index 00000000000..24d747ef58c --- /dev/null +++ b/Libraries/CMSIS/Device/Maxim/MAX32572/Include/aes_regs.h @@ -0,0 +1,224 @@ +/** + * @file aes_regs.h + * @brief Registers, Bit Masks and Bit Positions for the AES Peripheral Module. + * @note This file is @generated. + * @ingroup aes_registers + */ + +/****************************************************************************** + * + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32672_INCLUDE_AES_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32672_INCLUDE_AES_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup aes + * @defgroup aes_registers AES_Registers + * @brief Registers, Bit Masks and Bit Positions for the AES Peripheral Module. + * @details AES Keys. + */ + +/** + * @ingroup aes_registers + * Structure type to access the AES Registers. + */ +typedef struct { + __IO uint32_t ctrl; /**< \b 0x0000: AES CTRL Register */ + __IO uint32_t status; /**< \b 0x0004: AES STATUS Register */ + __IO uint32_t intfl; /**< \b 0x0008: AES INTFL Register */ + __IO uint32_t inten; /**< \b 0x000C: AES INTEN Register */ + __IO uint32_t fifo; /**< \b 0x0010: AES FIFO Register */ +} mxc_aes_regs_t; + +/* Register offsets for module AES */ +/** + * @ingroup aes_registers + * @defgroup AES_Register_Offsets Register Offsets + * @brief AES Peripheral Register Offsets from the AES Base Peripheral Address. + * @{ + */ +#define MXC_R_AES_CTRL ((uint32_t)0x00000000UL) /**< Offset from AES Base Address: 0x0000 */ +#define MXC_R_AES_STATUS ((uint32_t)0x00000004UL) /**< Offset from AES Base Address: 0x0004 */ +#define MXC_R_AES_INTFL ((uint32_t)0x00000008UL) /**< Offset from AES Base Address: 0x0008 */ +#define MXC_R_AES_INTEN ((uint32_t)0x0000000CUL) /**< Offset from AES Base Address: 0x000C */ +#define MXC_R_AES_FIFO ((uint32_t)0x00000010UL) /**< Offset from AES Base Address: 0x0010 */ +/**@} end of group aes_registers */ + +/** + * @ingroup aes_registers + * @defgroup AES_CTRL AES_CTRL + * @brief AES Control Register + * @{ + */ +#define MXC_F_AES_CTRL_EN_POS 0 /**< CTRL_EN Position */ +#define MXC_F_AES_CTRL_EN ((uint32_t)(0x1UL << MXC_F_AES_CTRL_EN_POS)) /**< CTRL_EN Mask */ + +#define MXC_F_AES_CTRL_DMA_RX_EN_POS 1 /**< CTRL_DMA_RX_EN Position */ +#define MXC_F_AES_CTRL_DMA_RX_EN ((uint32_t)(0x1UL << MXC_F_AES_CTRL_DMA_RX_EN_POS)) /**< CTRL_DMA_RX_EN Mask */ + +#define MXC_F_AES_CTRL_DMA_TX_EN_POS 2 /**< CTRL_DMA_TX_EN Position */ +#define MXC_F_AES_CTRL_DMA_TX_EN ((uint32_t)(0x1UL << MXC_F_AES_CTRL_DMA_TX_EN_POS)) /**< CTRL_DMA_TX_EN Mask */ + +#define MXC_F_AES_CTRL_START_POS 3 /**< CTRL_START Position */ +#define MXC_F_AES_CTRL_START ((uint32_t)(0x1UL << MXC_F_AES_CTRL_START_POS)) /**< CTRL_START Mask */ + +#define MXC_F_AES_CTRL_INPUT_FLUSH_POS 4 /**< CTRL_INPUT_FLUSH Position */ +#define MXC_F_AES_CTRL_INPUT_FLUSH ((uint32_t)(0x1UL << MXC_F_AES_CTRL_INPUT_FLUSH_POS)) /**< CTRL_INPUT_FLUSH Mask */ + +#define MXC_F_AES_CTRL_OUTPUT_FLUSH_POS 5 /**< CTRL_OUTPUT_FLUSH Position */ +#define MXC_F_AES_CTRL_OUTPUT_FLUSH ((uint32_t)(0x1UL << MXC_F_AES_CTRL_OUTPUT_FLUSH_POS)) /**< CTRL_OUTPUT_FLUSH Mask */ + +#define MXC_F_AES_CTRL_KEY_SIZE_POS 6 /**< CTRL_KEY_SIZE Position */ +#define MXC_F_AES_CTRL_KEY_SIZE ((uint32_t)(0x3UL << MXC_F_AES_CTRL_KEY_SIZE_POS)) /**< CTRL_KEY_SIZE Mask */ +#define MXC_V_AES_CTRL_KEY_SIZE_AES128 ((uint32_t)0x0UL) /**< CTRL_KEY_SIZE_AES128 Value */ +#define MXC_S_AES_CTRL_KEY_SIZE_AES128 (MXC_V_AES_CTRL_KEY_SIZE_AES128 << MXC_F_AES_CTRL_KEY_SIZE_POS) /**< CTRL_KEY_SIZE_AES128 Setting */ +#define MXC_V_AES_CTRL_KEY_SIZE_AES192 ((uint32_t)0x1UL) /**< CTRL_KEY_SIZE_AES192 Value */ +#define MXC_S_AES_CTRL_KEY_SIZE_AES192 (MXC_V_AES_CTRL_KEY_SIZE_AES192 << MXC_F_AES_CTRL_KEY_SIZE_POS) /**< CTRL_KEY_SIZE_AES192 Setting */ +#define MXC_V_AES_CTRL_KEY_SIZE_AES256 ((uint32_t)0x2UL) /**< CTRL_KEY_SIZE_AES256 Value */ +#define MXC_S_AES_CTRL_KEY_SIZE_AES256 (MXC_V_AES_CTRL_KEY_SIZE_AES256 << MXC_F_AES_CTRL_KEY_SIZE_POS) /**< CTRL_KEY_SIZE_AES256 Setting */ + +#define MXC_F_AES_CTRL_TYPE_POS 8 /**< CTRL_TYPE Position */ +#define MXC_F_AES_CTRL_TYPE ((uint32_t)(0x3UL << MXC_F_AES_CTRL_TYPE_POS)) /**< CTRL_TYPE Mask */ + +/**@} end of group AES_CTRL_Register */ + +/** + * @ingroup aes_registers + * @defgroup AES_STATUS AES_STATUS + * @brief AES Status Register + * @{ + */ +#define MXC_F_AES_STATUS_BUSY_POS 0 /**< STATUS_BUSY Position */ +#define MXC_F_AES_STATUS_BUSY ((uint32_t)(0x1UL << MXC_F_AES_STATUS_BUSY_POS)) /**< STATUS_BUSY Mask */ + +#define MXC_F_AES_STATUS_INPUT_EM_POS 1 /**< STATUS_INPUT_EM Position */ +#define MXC_F_AES_STATUS_INPUT_EM ((uint32_t)(0x1UL << MXC_F_AES_STATUS_INPUT_EM_POS)) /**< STATUS_INPUT_EM Mask */ + +#define MXC_F_AES_STATUS_INPUT_FULL_POS 2 /**< STATUS_INPUT_FULL Position */ +#define MXC_F_AES_STATUS_INPUT_FULL ((uint32_t)(0x1UL << MXC_F_AES_STATUS_INPUT_FULL_POS)) /**< STATUS_INPUT_FULL Mask */ + +#define MXC_F_AES_STATUS_OUTPUT_EM_POS 3 /**< STATUS_OUTPUT_EM Position */ +#define MXC_F_AES_STATUS_OUTPUT_EM ((uint32_t)(0x1UL << MXC_F_AES_STATUS_OUTPUT_EM_POS)) /**< STATUS_OUTPUT_EM Mask */ + +#define MXC_F_AES_STATUS_OUTPUT_FULL_POS 4 /**< STATUS_OUTPUT_FULL Position */ +#define MXC_F_AES_STATUS_OUTPUT_FULL ((uint32_t)(0x1UL << MXC_F_AES_STATUS_OUTPUT_FULL_POS)) /**< STATUS_OUTPUT_FULL Mask */ + +/**@} end of group AES_STATUS_Register */ + +/** + * @ingroup aes_registers + * @defgroup AES_INTFL AES_INTFL + * @brief AES Interrupt Flag Register + * @{ + */ +#define MXC_F_AES_INTFL_DONE_POS 0 /**< INTFL_DONE Position */ +#define MXC_F_AES_INTFL_DONE ((uint32_t)(0x1UL << MXC_F_AES_INTFL_DONE_POS)) /**< INTFL_DONE Mask */ + +#define MXC_F_AES_INTFL_KEY_CHANGE_POS 1 /**< INTFL_KEY_CHANGE Position */ +#define MXC_F_AES_INTFL_KEY_CHANGE ((uint32_t)(0x1UL << MXC_F_AES_INTFL_KEY_CHANGE_POS)) /**< INTFL_KEY_CHANGE Mask */ + +#define MXC_F_AES_INTFL_KEY_ZERO_POS 2 /**< INTFL_KEY_ZERO Position */ +#define MXC_F_AES_INTFL_KEY_ZERO ((uint32_t)(0x1UL << MXC_F_AES_INTFL_KEY_ZERO_POS)) /**< INTFL_KEY_ZERO Mask */ + +#define MXC_F_AES_INTFL_OV_POS 3 /**< INTFL_OV Position */ +#define MXC_F_AES_INTFL_OV ((uint32_t)(0x1UL << MXC_F_AES_INTFL_OV_POS)) /**< INTFL_OV Mask */ + +#define MXC_F_AES_INTFL_KEY_ONE_POS 4 /**< INTFL_KEY_ONE Position */ +#define MXC_F_AES_INTFL_KEY_ONE ((uint32_t)(0x1UL << MXC_F_AES_INTFL_KEY_ONE_POS)) /**< INTFL_KEY_ONE Mask */ + +/**@} end of group AES_INTFL_Register */ + +/** + * @ingroup aes_registers + * @defgroup AES_INTEN AES_INTEN + * @brief AES Interrupt Enable Register + * @{ + */ +#define MXC_F_AES_INTEN_DONE_POS 0 /**< INTEN_DONE Position */ +#define MXC_F_AES_INTEN_DONE ((uint32_t)(0x1UL << MXC_F_AES_INTEN_DONE_POS)) /**< INTEN_DONE Mask */ + +#define MXC_F_AES_INTEN_KEY_CHANGE_POS 1 /**< INTEN_KEY_CHANGE Position */ +#define MXC_F_AES_INTEN_KEY_CHANGE ((uint32_t)(0x1UL << MXC_F_AES_INTEN_KEY_CHANGE_POS)) /**< INTEN_KEY_CHANGE Mask */ + +#define MXC_F_AES_INTEN_KEY_ZERO_POS 2 /**< INTEN_KEY_ZERO Position */ +#define MXC_F_AES_INTEN_KEY_ZERO ((uint32_t)(0x1UL << MXC_F_AES_INTEN_KEY_ZERO_POS)) /**< INTEN_KEY_ZERO Mask */ + +#define MXC_F_AES_INTEN_OV_POS 3 /**< INTEN_OV Position */ +#define MXC_F_AES_INTEN_OV ((uint32_t)(0x1UL << MXC_F_AES_INTEN_OV_POS)) /**< INTEN_OV Mask */ + +#define MXC_F_AES_INTEN_KEY_ONE_POS 4 /**< INTEN_KEY_ONE Position */ +#define MXC_F_AES_INTEN_KEY_ONE ((uint32_t)(0x1UL << MXC_F_AES_INTEN_KEY_ONE_POS)) /**< INTEN_KEY_ONE Mask */ + +/**@} end of group AES_INTEN_Register */ + +/** + * @ingroup aes_registers + * @defgroup AES_FIFO AES_FIFO + * @brief AES Data Register + * @{ + */ +#define MXC_F_AES_FIFO_DATA_POS 0 /**< FIFO_DATA Position */ +#define MXC_F_AES_FIFO_DATA ((uint32_t)(0x1UL << MXC_F_AES_FIFO_DATA_POS)) /**< FIFO_DATA Mask */ + +/**@} end of group AES_FIFO_Register */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32672_INCLUDE_AES_REGS_H_ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32572/Include/aeskeys_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32572/Include/aeskeys_regs.h index 5d71357c203..95894a7344f 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32572/Include/aeskeys_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32572/Include/aeskeys_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32572/Include/ctb_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32572/Include/ctb_regs.h index ac9be96e873..7c3346c0ac3 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32572/Include/ctb_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32572/Include/ctb_regs.h @@ -25,8 +25,8 @@ * ******************************************************************************/ -#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_CTB_REGS_H_ -#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_CTB_REGS_H_ +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32672_INCLUDE_CTB_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32672_INCLUDE_CTB_REGS_H_ /* **** Includes **** */ #include @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile @@ -81,12 +85,12 @@ typedef struct { __IO uint32_t dma_src; /**< \b 0x10: CTB DMA_SRC Register */ __IO uint32_t dma_dest; /**< \b 0x14: CTB DMA_DEST Register */ __IO uint32_t dma_cnt; /**< \b 0x18: CTB DMA_CNT Register */ - __IO uint32_t maa_ctrl; /**< \b 0x1C: CTB MAA_CTRL Register */ + __R uint32_t rsv_0x1c; __O uint32_t din[4]; /**< \b 0x20: CTB DIN Register */ __I uint32_t dout[4]; /**< \b 0x30: CTB DOUT Register */ __IO uint32_t crc_poly; /**< \b 0x40: CTB CRC_POLY Register */ __IO uint32_t crc_val; /**< \b 0x44: CTB CRC_VAL Register */ - __IO uint32_t crc_prng; /**< \b 0x48: CTB CRC_PRNG Register */ + __R uint32_t rsv_0x48; __IO uint32_t ham_ecc; /**< \b 0x4C: CTB HAM_ECC Register */ __IO uint32_t cipher_init[4]; /**< \b 0x50: CTB CIPHER_INIT Register */ __O uint32_t cipher_key[8]; /**< \b 0x60: CTB CIPHER_KEY Register */ @@ -95,23 +99,21 @@ typedef struct { __IO uint32_t aad_length[2]; /**< \b 0xD0: CTB AAD_LENGTH Register */ __IO uint32_t pld_length[2]; /**< \b 0xD8: CTB PLD_LENGTH Register */ __IO uint32_t tagmic[4]; /**< \b 0xE0: CTB TAGMIC Register */ - __IO uint32_t maa_maws; /**< \b 0xF0: CTB MAA_MAWS Register */ - __R uint32_t rsv_0xf4_0x6ff[387]; - __IO uint32_t sca_ctrl0; /**< \b 0x700: CTB SCA_CTRL0 Register */ - __IO uint32_t sca_ctrl1; /**< \b 0x704: CTB SCA_CTRL1 Register */ - __IO uint32_t sca_stat; /**< \b 0x708: CTB SCA_STAT Register */ - __IO uint32_t sca_ppx_addr; /**< \b 0x70C: CTB SCA_PPX_ADDR Register */ - __IO uint32_t sca_ppy_addr; /**< \b 0x710: CTB SCA_PPY_ADDR Register */ - __IO uint32_t sca_ppz_addr; /**< \b 0x714: CTB SCA_PPZ_ADDR Register */ - __IO uint32_t sca_pqx_addr; /**< \b 0x718: CTB SCA_PQX_ADDR Register */ - __IO uint32_t sca_pqy_addr; /**< \b 0x71C: CTB SCA_PQY_ADDR Register */ - __IO uint32_t sca_pqz_addr; /**< \b 0x720: CTB SCA_PQZ_ADDR Register */ - __IO uint32_t sca_rdsa_addr; /**< \b 0x724: CTB SCA_RDSA_ADDR Register */ - __IO uint32_t sca_res_addr; /**< \b 0x728: CTB SCA_RES_ADDR Register */ - __IO uint32_t sca_op_buff_addr; /**< \b 0x72C: CTB SCA_OP_BUFF_ADDR Register */ - __IO uint32_t sca_moddata; /**< \b 0x730: CTB SCA_MODDATA Register */ - __IO uint32_t sca_nrng; /**< \b 0x734: CTB SCA_NRNG Register */ - __IO uint32_t sca_wash; /**< \b 0x738: CTB SCA_WASH Register */ + __R uint32_t rsv_0xf0_0xff[4]; + __IO uint32_t sca_ctrl0; /**< \b 0x100: CTB SCA_CTRL0 Register */ + __IO uint32_t sca_ctrl1; /**< \b 0x104: CTB SCA_CTRL1 Register */ + __IO uint32_t sca_stat; /**< \b 0x108: CTB SCA_STAT Register */ + __IO uint32_t sca_ppx_addr; /**< \b 0x10C: CTB SCA_PPX_ADDR Register */ + __IO uint32_t sca_ppy_addr; /**< \b 0x110: CTB SCA_PPY_ADDR Register */ + __IO uint32_t sca_ppz_addr; /**< \b 0x114: CTB SCA_PPZ_ADDR Register */ + __IO uint32_t sca_pqx_addr; /**< \b 0x118: CTB SCA_PQX_ADDR Register */ + __IO uint32_t sca_pqy_addr; /**< \b 0x11C: CTB SCA_PQY_ADDR Register */ + __IO uint32_t sca_pqz_addr; /**< \b 0x120: CTB SCA_PQZ_ADDR Register */ + __IO uint32_t sca_rdsa_addr; /**< \b 0x124: CTB SCA_RDSA_ADDR Register */ + __IO uint32_t sca_res_addr; /**< \b 0x128: CTB SCA_RES_ADDR Register */ + __IO uint32_t sca_op_buff_addr; /**< \b 0x12C: CTB SCA_OP_BUFF_ADDR Register */ + __IO uint32_t sca_moddata; /**< \b 0x130: CTB SCA_MODDATA Register */ + __IO uint32_t sca_nrng; /**< \b 0x134: CTB SCA_NRNG Register */ } mxc_ctb_regs_t; /* Register offsets for module CTB */ @@ -128,12 +130,10 @@ typedef struct { #define MXC_R_CTB_DMA_SRC ((uint32_t)0x00000010UL) /**< Offset from CTB Base Address: 0x0010 */ #define MXC_R_CTB_DMA_DEST ((uint32_t)0x00000014UL) /**< Offset from CTB Base Address: 0x0014 */ #define MXC_R_CTB_DMA_CNT ((uint32_t)0x00000018UL) /**< Offset from CTB Base Address: 0x0018 */ -#define MXC_R_CTB_MAA_CTRL ((uint32_t)0x0000001CUL) /**< Offset from CTB Base Address: 0x001C */ #define MXC_R_CTB_DIN ((uint32_t)0x00000020UL) /**< Offset from CTB Base Address: 0x0020 */ #define MXC_R_CTB_DOUT ((uint32_t)0x00000030UL) /**< Offset from CTB Base Address: 0x0030 */ #define MXC_R_CTB_CRC_POLY ((uint32_t)0x00000040UL) /**< Offset from CTB Base Address: 0x0040 */ #define MXC_R_CTB_CRC_VAL ((uint32_t)0x00000044UL) /**< Offset from CTB Base Address: 0x0044 */ -#define MXC_R_CTB_CRC_PRNG ((uint32_t)0x00000048UL) /**< Offset from CTB Base Address: 0x0048 */ #define MXC_R_CTB_HAM_ECC ((uint32_t)0x0000004CUL) /**< Offset from CTB Base Address: 0x004C */ #define MXC_R_CTB_CIPHER_INIT ((uint32_t)0x00000050UL) /**< Offset from CTB Base Address: 0x0050 */ #define MXC_R_CTB_CIPHER_KEY ((uint32_t)0x00000060UL) /**< Offset from CTB Base Address: 0x0060 */ @@ -142,22 +142,20 @@ typedef struct { #define MXC_R_CTB_AAD_LENGTH ((uint32_t)0x000000D0UL) /**< Offset from CTB Base Address: 0x00D0 */ #define MXC_R_CTB_PLD_LENGTH ((uint32_t)0x000000D8UL) /**< Offset from CTB Base Address: 0x00D8 */ #define MXC_R_CTB_TAGMIC ((uint32_t)0x000000E0UL) /**< Offset from CTB Base Address: 0x00E0 */ -#define MXC_R_CTB_MAA_MAWS ((uint32_t)0x000000F0UL) /**< Offset from CTB Base Address: 0x00F0 */ -#define MXC_R_CTB_SCA_CTRL0 ((uint32_t)0x00000700UL) /**< Offset from CTB Base Address: 0x0700 */ -#define MXC_R_CTB_SCA_CTRL1 ((uint32_t)0x00000704UL) /**< Offset from CTB Base Address: 0x0704 */ -#define MXC_R_CTB_SCA_STAT ((uint32_t)0x00000708UL) /**< Offset from CTB Base Address: 0x0708 */ -#define MXC_R_CTB_SCA_PPX_ADDR ((uint32_t)0x0000070CUL) /**< Offset from CTB Base Address: 0x070C */ -#define MXC_R_CTB_SCA_PPY_ADDR ((uint32_t)0x00000710UL) /**< Offset from CTB Base Address: 0x0710 */ -#define MXC_R_CTB_SCA_PPZ_ADDR ((uint32_t)0x00000714UL) /**< Offset from CTB Base Address: 0x0714 */ -#define MXC_R_CTB_SCA_PQX_ADDR ((uint32_t)0x00000718UL) /**< Offset from CTB Base Address: 0x0718 */ -#define MXC_R_CTB_SCA_PQY_ADDR ((uint32_t)0x0000071CUL) /**< Offset from CTB Base Address: 0x071C */ -#define MXC_R_CTB_SCA_PQZ_ADDR ((uint32_t)0x00000720UL) /**< Offset from CTB Base Address: 0x0720 */ -#define MXC_R_CTB_SCA_RDSA_ADDR ((uint32_t)0x00000724UL) /**< Offset from CTB Base Address: 0x0724 */ -#define MXC_R_CTB_SCA_RES_ADDR ((uint32_t)0x00000728UL) /**< Offset from CTB Base Address: 0x0728 */ -#define MXC_R_CTB_SCA_OP_BUFF_ADDR ((uint32_t)0x0000072CUL) /**< Offset from CTB Base Address: 0x072C */ -#define MXC_R_CTB_SCA_MODDATA ((uint32_t)0x00000730UL) /**< Offset from CTB Base Address: 0x0730 */ -#define MXC_R_CTB_SCA_NRNG ((uint32_t)0x00000734UL) /**< Offset from CTB Base Address: 0x0734 */ -#define MXC_R_CTB_SCA_WASH ((uint32_t)0x00000738UL) /**< Offset from CTB Base Address: 0x0738 */ +#define MXC_R_CTB_SCA_CTRL0 ((uint32_t)0x00000100UL) /**< Offset from CTB Base Address: 0x0100 */ +#define MXC_R_CTB_SCA_CTRL1 ((uint32_t)0x00000104UL) /**< Offset from CTB Base Address: 0x0104 */ +#define MXC_R_CTB_SCA_STAT ((uint32_t)0x00000108UL) /**< Offset from CTB Base Address: 0x0108 */ +#define MXC_R_CTB_SCA_PPX_ADDR ((uint32_t)0x0000010CUL) /**< Offset from CTB Base Address: 0x010C */ +#define MXC_R_CTB_SCA_PPY_ADDR ((uint32_t)0x00000110UL) /**< Offset from CTB Base Address: 0x0110 */ +#define MXC_R_CTB_SCA_PPZ_ADDR ((uint32_t)0x00000114UL) /**< Offset from CTB Base Address: 0x0114 */ +#define MXC_R_CTB_SCA_PQX_ADDR ((uint32_t)0x00000118UL) /**< Offset from CTB Base Address: 0x0118 */ +#define MXC_R_CTB_SCA_PQY_ADDR ((uint32_t)0x0000011CUL) /**< Offset from CTB Base Address: 0x011C */ +#define MXC_R_CTB_SCA_PQZ_ADDR ((uint32_t)0x00000120UL) /**< Offset from CTB Base Address: 0x0120 */ +#define MXC_R_CTB_SCA_RDSA_ADDR ((uint32_t)0x00000124UL) /**< Offset from CTB Base Address: 0x0124 */ +#define MXC_R_CTB_SCA_RES_ADDR ((uint32_t)0x00000128UL) /**< Offset from CTB Base Address: 0x0128 */ +#define MXC_R_CTB_SCA_OP_BUFF_ADDR ((uint32_t)0x0000012CUL) /**< Offset from CTB Base Address: 0x012C */ +#define MXC_R_CTB_SCA_MODDATA ((uint32_t)0x00000130UL) /**< Offset from CTB Base Address: 0x0130 */ +#define MXC_R_CTB_SCA_NRNG ((uint32_t)0x00000134UL) /**< Offset from CTB Base Address: 0x0134 */ /**@} end of group ctb_registers */ /** @@ -443,17 +441,6 @@ typedef struct { /**@} end of group CTB_CRC_VAL_Register */ -/** - * @ingroup ctb_registers - * @defgroup CTB_CRC_PRNG CTB_CRC_PRNG - * @brief CRC PRNG Register. - * @{ - */ -#define MXC_F_CTB_CRC_PRNG_PRNG_POS 0 /**< CRC_PRNG_PRNG Position */ -#define MXC_F_CTB_CRC_PRNG_PRNG ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_CRC_PRNG_PRNG_POS)) /**< CRC_PRNG_PRNG Mask */ - -/**@} end of group CTB_CRC_PRNG_Register */ - /** * @ingroup ctb_registers * @defgroup CTB_HAM_ECC CTB_HAM_ECC @@ -551,17 +538,6 @@ typedef struct { /**@} end of group CTB_TAGMIC_Register */ -/** - * @ingroup ctb_registers - * @defgroup CTB_MAA_MAWS CTB_MAA_MAWS - * @brief MAA Word Size Register. - * @{ - */ -#define MXC_F_CTB_MAA_MAWS_SIZE_POS 0 /**< MAA_MAWS_SIZE Position */ -#define MXC_F_CTB_MAA_MAWS_SIZE ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_MAA_MAWS_SIZE_POS)) /**< MAA_MAWS_SIZE Mask */ - -/**@} end of group CTB_MAA_MAWS_Register */ - /** * @ingroup ctb_registers * @defgroup CTB_SCA_CTRL0 CTB_SCA_CTRL0 @@ -577,9 +553,6 @@ typedef struct { #define MXC_F_CTB_SCA_CTRL0_ABORT_POS 2 /**< SCA_CTRL0_ABORT Position */ #define MXC_F_CTB_SCA_CTRL0_ABORT ((uint32_t)(0x1UL << MXC_F_CTB_SCA_CTRL0_ABORT_POS)) /**< SCA_CTRL0_ABORT Mask */ -#define MXC_F_CTB_SCA_CTRL0_AFFJAC_POS 3 /**< SCA_CTRL0_AFFJAC Position */ -#define MXC_F_CTB_SCA_CTRL0_AFFJAC ((uint32_t)(0x1UL << MXC_F_CTB_SCA_CTRL0_AFFJAC_POS)) /**< SCA_CTRL0_AFFJAC Mask */ - #define MXC_F_CTB_SCA_CTRL0_ERMEM_POS 4 /**< SCA_CTRL0_ERMEM Position */ #define MXC_F_CTB_SCA_CTRL0_ERMEM ((uint32_t)(0x1UL << MXC_F_CTB_SCA_CTRL0_ERMEM_POS)) /**< SCA_CTRL0_ERMEM Mask */ @@ -603,7 +576,7 @@ typedef struct { /** * @ingroup ctb_registers * @defgroup CTB_SCA_CTRL1 CTB_SCA_CTRL1 - * @brief SCA Advanced Control Register. + * @brief SCA Control 1 Register. * @{ */ #define MXC_F_CTB_SCA_CTRL1_MAN_POS 0 /**< SCA_CTRL1_MAN Position */ @@ -615,18 +588,12 @@ typedef struct { #define MXC_F_CTB_SCA_CTRL1_PLUSONE_POS 2 /**< SCA_CTRL1_PLUSONE Position */ #define MXC_F_CTB_SCA_CTRL1_PLUSONE ((uint32_t)(0x1UL << MXC_F_CTB_SCA_CTRL1_PLUSONE_POS)) /**< SCA_CTRL1_PLUSONE Mask */ -#define MXC_F_CTB_SCA_CTRL1_RESSELECT_POS 3 /**< SCA_CTRL1_RESSELECT Position */ -#define MXC_F_CTB_SCA_CTRL1_RESSELECT ((uint32_t)(0x3UL << MXC_F_CTB_SCA_CTRL1_RESSELECT_POS)) /**< SCA_CTRL1_RESSELECT Mask */ - #define MXC_F_CTB_SCA_CTRL1_NRNG_POS 5 /**< SCA_CTRL1_NRNG Position */ #define MXC_F_CTB_SCA_CTRL1_NRNG ((uint32_t)(0x1UL << MXC_F_CTB_SCA_CTRL1_NRNG_POS)) /**< SCA_CTRL1_NRNG Mask */ #define MXC_F_CTB_SCA_CTRL1_CARRYPOS_POS 8 /**< SCA_CTRL1_CARRYPOS Position */ #define MXC_F_CTB_SCA_CTRL1_CARRYPOS ((uint32_t)(0x3FFUL << MXC_F_CTB_SCA_CTRL1_CARRYPOS_POS)) /**< SCA_CTRL1_CARRYPOS Mask */ -#define MXC_F_CTB_SCA_CTRL1_CM_EN_POS 20 /**< SCA_CTRL1_CM_EN Position */ -#define MXC_F_CTB_SCA_CTRL1_CM_EN ((uint32_t)(0xFFFUL << MXC_F_CTB_SCA_CTRL1_CM_EN_POS)) /**< SCA_CTRL1_CM_EN Mask */ - /**@} end of group CTB_SCA_CTRL1_Register */ /** @@ -780,30 +747,8 @@ typedef struct { /**@} end of group CTB_SCA_MODDATA_Register */ -/** - * @ingroup ctb_registers - * @defgroup CTB_SCA_NRNG CTB_SCA_NRNG - * @brief SCA NIST RNG Address Register. - * @{ - */ -#define MXC_F_CTB_SCA_NRNG_ADDR_POS 0 /**< SCA_NRNG_ADDR Position */ -#define MXC_F_CTB_SCA_NRNG_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_SCA_NRNG_ADDR_POS)) /**< SCA_NRNG_ADDR Mask */ - -/**@} end of group CTB_SCA_NRNG_Register */ - -/** - * @ingroup ctb_registers - * @defgroup CTB_SCA_WASH CTB_SCA_WASH - * @brief SCA Wash Register. - * @{ - */ -#define MXC_F_CTB_SCA_WASH_ADDR_POS 0 /**< SCA_WASH_ADDR Position */ -#define MXC_F_CTB_SCA_WASH_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_SCA_WASH_ADDR_POS)) /**< SCA_WASH_ADDR Mask */ - -/**@} end of group CTB_SCA_WASH_Register */ - #ifdef __cplusplus } #endif -#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_CTB_REGS_H_ +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32672_INCLUDE_CTB_REGS_H_ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32572/Include/dma_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32572/Include/dma_regs.h index 47a089a6977..887a405f73e 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32572/Include/dma_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32572/Include/dma_regs.h @@ -25,8 +25,8 @@ * ******************************************************************************/ -#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_DMA_REGS_H_ -#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_DMA_REGS_H_ +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32672_INCLUDE_DMA_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32672_INCLUDE_DMA_REGS_H_ /* **** Includes **** */ #include @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile @@ -88,7 +92,7 @@ typedef struct { __IO uint32_t inten; /**< \b 0x000: DMA INTEN Register */ __I uint32_t intfl; /**< \b 0x004: DMA INTFL Register */ __R uint32_t rsv_0x8_0xff[62]; - __IO mxc_dma_ch_regs_t ch[16]; /**< \b 0x100: DMA CH Register */ + __IO mxc_dma_ch_regs_t ch[12]; /**< \b 0x100: DMA CH Register */ } mxc_dma_regs_t; /* Register offsets for module DMA */ @@ -114,7 +118,7 @@ typedef struct { /** * @ingroup dma_registers * @defgroup DMA_INTEN DMA_INTEN - * @brief DMA Interrupt Enable Register. + * @brief DMA Control Register. * @{ */ #define MXC_F_DMA_INTEN_CH0_POS 0 /**< INTEN_CH0 Position */ @@ -141,36 +145,12 @@ typedef struct { #define MXC_F_DMA_INTEN_CH7_POS 7 /**< INTEN_CH7 Position */ #define MXC_F_DMA_INTEN_CH7 ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH7_POS)) /**< INTEN_CH7 Mask */ -#define MXC_F_DMA_INTEN_CH8_POS 8 /**< INTEN_CH8 Position */ -#define MXC_F_DMA_INTEN_CH8 ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH8_POS)) /**< INTEN_CH8 Mask */ - -#define MXC_F_DMA_INTEN_CH9_POS 9 /**< INTEN_CH9 Position */ -#define MXC_F_DMA_INTEN_CH9 ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH9_POS)) /**< INTEN_CH9 Mask */ - -#define MXC_F_DMA_INTEN_CH10_POS 10 /**< INTEN_CH10 Position */ -#define MXC_F_DMA_INTEN_CH10 ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH10_POS)) /**< INTEN_CH10 Mask */ - -#define MXC_F_DMA_INTEN_CH11_POS 11 /**< INTEN_CH11 Position */ -#define MXC_F_DMA_INTEN_CH11 ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH11_POS)) /**< INTEN_CH11 Mask */ - -#define MXC_F_DMA_INTEN_CH12_POS 12 /**< INTEN_CH12 Position */ -#define MXC_F_DMA_INTEN_CH12 ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH12_POS)) /**< INTEN_CH12 Mask */ - -#define MXC_F_DMA_INTEN_CH13_POS 13 /**< INTEN_CH13 Position */ -#define MXC_F_DMA_INTEN_CH13 ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH13_POS)) /**< INTEN_CH13 Mask */ - -#define MXC_F_DMA_INTEN_CH14_POS 14 /**< INTEN_CH14 Position */ -#define MXC_F_DMA_INTEN_CH14 ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH14_POS)) /**< INTEN_CH14 Mask */ - -#define MXC_F_DMA_INTEN_CH15_POS 15 /**< INTEN_CH15 Position */ -#define MXC_F_DMA_INTEN_CH15 ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH15_POS)) /**< INTEN_CH15 Mask */ - /**@} end of group DMA_INTEN_Register */ /** * @ingroup dma_registers * @defgroup DMA_INTFL DMA_INTFL - * @brief DMA Interrupt Flag Register. + * @brief DMA Interrupt Register. * @{ */ #define MXC_F_DMA_INTFL_CH0_POS 0 /**< INTFL_CH0 Position */ @@ -197,30 +177,6 @@ typedef struct { #define MXC_F_DMA_INTFL_CH7_POS 7 /**< INTFL_CH7 Position */ #define MXC_F_DMA_INTFL_CH7 ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH7_POS)) /**< INTFL_CH7 Mask */ -#define MXC_F_DMA_INTFL_CH8_POS 8 /**< INTFL_CH8 Position */ -#define MXC_F_DMA_INTFL_CH8 ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH8_POS)) /**< INTFL_CH8 Mask */ - -#define MXC_F_DMA_INTFL_CH9_POS 9 /**< INTFL_CH9 Position */ -#define MXC_F_DMA_INTFL_CH9 ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH9_POS)) /**< INTFL_CH9 Mask */ - -#define MXC_F_DMA_INTFL_CH10_POS 10 /**< INTFL_CH10 Position */ -#define MXC_F_DMA_INTFL_CH10 ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH10_POS)) /**< INTFL_CH10 Mask */ - -#define MXC_F_DMA_INTFL_CH11_POS 11 /**< INTFL_CH11 Position */ -#define MXC_F_DMA_INTFL_CH11 ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH11_POS)) /**< INTFL_CH11 Mask */ - -#define MXC_F_DMA_INTFL_CH12_POS 12 /**< INTFL_CH12 Position */ -#define MXC_F_DMA_INTFL_CH12 ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH12_POS)) /**< INTFL_CH12 Mask */ - -#define MXC_F_DMA_INTFL_CH13_POS 13 /**< INTFL_CH13 Position */ -#define MXC_F_DMA_INTFL_CH13 ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH13_POS)) /**< INTFL_CH13 Mask */ - -#define MXC_F_DMA_INTFL_CH14_POS 14 /**< INTFL_CH14 Position */ -#define MXC_F_DMA_INTFL_CH14 ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH14_POS)) /**< INTFL_CH14 Mask */ - -#define MXC_F_DMA_INTFL_CH15_POS 15 /**< INTFL_CH15 Position */ -#define MXC_F_DMA_INTFL_CH15 ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH15_POS)) /**< INTFL_CH15 Mask */ - /**@} end of group DMA_INTFL_Register */ /** @@ -254,90 +210,58 @@ typedef struct { #define MXC_S_DMA_CTRL_REQUEST_SPI0RX (MXC_V_DMA_CTRL_REQUEST_SPI0RX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI0RX Setting */ #define MXC_V_DMA_CTRL_REQUEST_SPI1RX ((uint32_t)0x2UL) /**< CTRL_REQUEST_SPI1RX Value */ #define MXC_S_DMA_CTRL_REQUEST_SPI1RX (MXC_V_DMA_CTRL_REQUEST_SPI1RX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI1RX Setting */ +#define MXC_V_DMA_CTRL_REQUEST_SPI2RX ((uint32_t)0x3UL) /**< CTRL_REQUEST_SPI2RX Value */ +#define MXC_S_DMA_CTRL_REQUEST_SPI2RX (MXC_V_DMA_CTRL_REQUEST_SPI2RX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI2RX Setting */ #define MXC_V_DMA_CTRL_REQUEST_UART0RX ((uint32_t)0x4UL) /**< CTRL_REQUEST_UART0RX Value */ #define MXC_S_DMA_CTRL_REQUEST_UART0RX (MXC_V_DMA_CTRL_REQUEST_UART0RX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UART0RX Setting */ #define MXC_V_DMA_CTRL_REQUEST_UART1RX ((uint32_t)0x5UL) /**< CTRL_REQUEST_UART1RX Value */ #define MXC_S_DMA_CTRL_REQUEST_UART1RX (MXC_V_DMA_CTRL_REQUEST_UART1RX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UART1RX Setting */ -#define MXC_V_DMA_CTRL_REQUEST_SC0RX ((uint32_t)0x6UL) /**< CTRL_REQUEST_SC0RX Value */ -#define MXC_S_DMA_CTRL_REQUEST_SC0RX (MXC_V_DMA_CTRL_REQUEST_SC0RX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SC0RX Setting */ #define MXC_V_DMA_CTRL_REQUEST_I2C0RX ((uint32_t)0x7UL) /**< CTRL_REQUEST_I2C0RX Value */ #define MXC_S_DMA_CTRL_REQUEST_I2C0RX (MXC_V_DMA_CTRL_REQUEST_I2C0RX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I2C0RX Setting */ #define MXC_V_DMA_CTRL_REQUEST_I2C1RX ((uint32_t)0x8UL) /**< CTRL_REQUEST_I2C1RX Value */ #define MXC_S_DMA_CTRL_REQUEST_I2C1RX (MXC_V_DMA_CTRL_REQUEST_I2C1RX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I2C1RX Setting */ #define MXC_V_DMA_CTRL_REQUEST_ADC ((uint32_t)0x9UL) /**< CTRL_REQUEST_ADC Value */ #define MXC_S_DMA_CTRL_REQUEST_ADC (MXC_V_DMA_CTRL_REQUEST_ADC << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_ADC Setting */ -#define MXC_V_DMA_CTRL_REQUEST_MSRADC ((uint32_t)0xBUL) /**< CTRL_REQUEST_MSRADC Value */ -#define MXC_S_DMA_CTRL_REQUEST_MSRADC (MXC_V_DMA_CTRL_REQUEST_MSRADC << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_MSRADC Setting */ +#define MXC_V_DMA_CTRL_REQUEST_I2C2RX ((uint32_t)0xAUL) /**< CTRL_REQUEST_I2C2RX Value */ +#define MXC_S_DMA_CTRL_REQUEST_I2C2RX (MXC_V_DMA_CTRL_REQUEST_I2C2RX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I2C2RX Setting */ #define MXC_V_DMA_CTRL_REQUEST_UART2RX ((uint32_t)0xEUL) /**< CTRL_REQUEST_UART2RX Value */ #define MXC_S_DMA_CTRL_REQUEST_UART2RX (MXC_V_DMA_CTRL_REQUEST_UART2RX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UART2RX Setting */ #define MXC_V_DMA_CTRL_REQUEST_SPI3RX ((uint32_t)0xFUL) /**< CTRL_REQUEST_SPI3RX Value */ #define MXC_S_DMA_CTRL_REQUEST_SPI3RX (MXC_V_DMA_CTRL_REQUEST_SPI3RX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI3RX Setting */ -#define MXC_V_DMA_CTRL_REQUEST_USBRXEP1 ((uint32_t)0x11UL) /**< CTRL_REQUEST_USBRXEP1 Value */ -#define MXC_S_DMA_CTRL_REQUEST_USBRXEP1 (MXC_V_DMA_CTRL_REQUEST_USBRXEP1 << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBRXEP1 Setting */ -#define MXC_V_DMA_CTRL_REQUEST_USBRXEP2 ((uint32_t)0x12UL) /**< CTRL_REQUEST_USBRXEP2 Value */ -#define MXC_S_DMA_CTRL_REQUEST_USBRXEP2 (MXC_V_DMA_CTRL_REQUEST_USBRXEP2 << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBRXEP2 Setting */ -#define MXC_V_DMA_CTRL_REQUEST_USBRXEP3 ((uint32_t)0x13UL) /**< CTRL_REQUEST_USBRXEP3 Value */ -#define MXC_S_DMA_CTRL_REQUEST_USBRXEP3 (MXC_V_DMA_CTRL_REQUEST_USBRXEP3 << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBRXEP3 Setting */ -#define MXC_V_DMA_CTRL_REQUEST_USBRXEP4 ((uint32_t)0x14UL) /**< CTRL_REQUEST_USBRXEP4 Value */ -#define MXC_S_DMA_CTRL_REQUEST_USBRXEP4 (MXC_V_DMA_CTRL_REQUEST_USBRXEP4 << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBRXEP4 Setting */ -#define MXC_V_DMA_CTRL_REQUEST_USBRXEP5 ((uint32_t)0x15UL) /**< CTRL_REQUEST_USBRXEP5 Value */ -#define MXC_S_DMA_CTRL_REQUEST_USBRXEP5 (MXC_V_DMA_CTRL_REQUEST_USBRXEP5 << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBRXEP5 Setting */ -#define MXC_V_DMA_CTRL_REQUEST_USBRXEP6 ((uint32_t)0x16UL) /**< CTRL_REQUEST_USBRXEP6 Value */ -#define MXC_S_DMA_CTRL_REQUEST_USBRXEP6 (MXC_V_DMA_CTRL_REQUEST_USBRXEP6 << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBRXEP6 Setting */ -#define MXC_V_DMA_CTRL_REQUEST_USBRXEP7 ((uint32_t)0x17UL) /**< CTRL_REQUEST_USBRXEP7 Value */ -#define MXC_S_DMA_CTRL_REQUEST_USBRXEP7 (MXC_V_DMA_CTRL_REQUEST_USBRXEP7 << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBRXEP7 Setting */ -#define MXC_V_DMA_CTRL_REQUEST_USBRXEP8 ((uint32_t)0x18UL) /**< CTRL_REQUEST_USBRXEP8 Value */ -#define MXC_S_DMA_CTRL_REQUEST_USBRXEP8 (MXC_V_DMA_CTRL_REQUEST_USBRXEP8 << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBRXEP8 Setting */ -#define MXC_V_DMA_CTRL_REQUEST_USBRXEP9 ((uint32_t)0x19UL) /**< CTRL_REQUEST_USBRXEP9 Value */ -#define MXC_S_DMA_CTRL_REQUEST_USBRXEP9 (MXC_V_DMA_CTRL_REQUEST_USBRXEP9 << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBRXEP9 Setting */ -#define MXC_V_DMA_CTRL_REQUEST_USBRXEP10 ((uint32_t)0x1AUL) /**< CTRL_REQUEST_USBRXEP10 Value */ -#define MXC_S_DMA_CTRL_REQUEST_USBRXEP10 (MXC_V_DMA_CTRL_REQUEST_USBRXEP10 << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBRXEP10 Setting */ -#define MXC_V_DMA_CTRL_REQUEST_USBRXEP11 ((uint32_t)0x1BUL) /**< CTRL_REQUEST_USBRXEP11 Value */ -#define MXC_S_DMA_CTRL_REQUEST_USBRXEP11 (MXC_V_DMA_CTRL_REQUEST_USBRXEP11 << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBRXEP11 Setting */ +#define MXC_V_DMA_CTRL_REQUEST_AESRX ((uint32_t)0x10UL) /**< CTRL_REQUEST_AESRX Value */ +#define MXC_S_DMA_CTRL_REQUEST_AESRX (MXC_V_DMA_CTRL_REQUEST_AESRX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_AESRX Setting */ #define MXC_V_DMA_CTRL_REQUEST_UART3RX ((uint32_t)0x1CUL) /**< CTRL_REQUEST_UART3RX Value */ #define MXC_S_DMA_CTRL_REQUEST_UART3RX (MXC_V_DMA_CTRL_REQUEST_UART3RX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UART3RX Setting */ +#define MXC_V_DMA_CTRL_REQUEST_I2SRX ((uint32_t)0x1EUL) /**< CTRL_REQUEST_I2SRX Value */ +#define MXC_S_DMA_CTRL_REQUEST_I2SRX (MXC_V_DMA_CTRL_REQUEST_I2SRX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I2SRX Setting */ #define MXC_V_DMA_CTRL_REQUEST_SPI0TX ((uint32_t)0x21UL) /**< CTRL_REQUEST_SPI0TX Value */ #define MXC_S_DMA_CTRL_REQUEST_SPI0TX (MXC_V_DMA_CTRL_REQUEST_SPI0TX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI0TX Setting */ #define MXC_V_DMA_CTRL_REQUEST_SPI1TX ((uint32_t)0x22UL) /**< CTRL_REQUEST_SPI1TX Value */ #define MXC_S_DMA_CTRL_REQUEST_SPI1TX (MXC_V_DMA_CTRL_REQUEST_SPI1TX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI1TX Setting */ +#define MXC_V_DMA_CTRL_REQUEST_SPI2TX ((uint32_t)0x23UL) /**< CTRL_REQUEST_SPI2TX Value */ +#define MXC_S_DMA_CTRL_REQUEST_SPI2TX (MXC_V_DMA_CTRL_REQUEST_SPI2TX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI2TX Setting */ #define MXC_V_DMA_CTRL_REQUEST_UART0TX ((uint32_t)0x24UL) /**< CTRL_REQUEST_UART0TX Value */ #define MXC_S_DMA_CTRL_REQUEST_UART0TX (MXC_V_DMA_CTRL_REQUEST_UART0TX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UART0TX Setting */ #define MXC_V_DMA_CTRL_REQUEST_UART1TX ((uint32_t)0x25UL) /**< CTRL_REQUEST_UART1TX Value */ #define MXC_S_DMA_CTRL_REQUEST_UART1TX (MXC_V_DMA_CTRL_REQUEST_UART1TX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UART1TX Setting */ -#define MXC_V_DMA_CTRL_REQUEST_SC0TX ((uint32_t)0x26UL) /**< CTRL_REQUEST_SC0TX Value */ -#define MXC_S_DMA_CTRL_REQUEST_SC0TX (MXC_V_DMA_CTRL_REQUEST_SC0TX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SC0TX Setting */ #define MXC_V_DMA_CTRL_REQUEST_I2C0TX ((uint32_t)0x27UL) /**< CTRL_REQUEST_I2C0TX Value */ #define MXC_S_DMA_CTRL_REQUEST_I2C0TX (MXC_V_DMA_CTRL_REQUEST_I2C0TX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I2C0TX Setting */ #define MXC_V_DMA_CTRL_REQUEST_I2C1TX ((uint32_t)0x28UL) /**< CTRL_REQUEST_I2C1TX Value */ #define MXC_S_DMA_CTRL_REQUEST_I2C1TX (MXC_V_DMA_CTRL_REQUEST_I2C1TX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I2C1TX Setting */ +#define MXC_V_DMA_CTRL_REQUEST_I2C2TX ((uint32_t)0x2AUL) /**< CTRL_REQUEST_I2C2TX Value */ +#define MXC_S_DMA_CTRL_REQUEST_I2C2TX (MXC_V_DMA_CTRL_REQUEST_I2C2TX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I2C2TX Setting */ +#define MXC_V_DMA_CTRL_REQUEST_CRCTX ((uint32_t)0x2CUL) /**< CTRL_REQUEST_CRCTX Value */ +#define MXC_S_DMA_CTRL_REQUEST_CRCTX (MXC_V_DMA_CTRL_REQUEST_CRCTX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_CRCTX Setting */ #define MXC_V_DMA_CTRL_REQUEST_UART2TX ((uint32_t)0x2EUL) /**< CTRL_REQUEST_UART2TX Value */ #define MXC_S_DMA_CTRL_REQUEST_UART2TX (MXC_V_DMA_CTRL_REQUEST_UART2TX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UART2TX Setting */ #define MXC_V_DMA_CTRL_REQUEST_SPI3TX ((uint32_t)0x2FUL) /**< CTRL_REQUEST_SPI3TX Value */ #define MXC_S_DMA_CTRL_REQUEST_SPI3TX (MXC_V_DMA_CTRL_REQUEST_SPI3TX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI3TX Setting */ -#define MXC_V_DMA_CTRL_REQUEST_USBTXEP1 ((uint32_t)0x31UL) /**< CTRL_REQUEST_USBTXEP1 Value */ -#define MXC_S_DMA_CTRL_REQUEST_USBTXEP1 (MXC_V_DMA_CTRL_REQUEST_USBTXEP1 << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBTXEP1 Setting */ -#define MXC_V_DMA_CTRL_REQUEST_USBTXEP2 ((uint32_t)0x32UL) /**< CTRL_REQUEST_USBTXEP2 Value */ -#define MXC_S_DMA_CTRL_REQUEST_USBTXEP2 (MXC_V_DMA_CTRL_REQUEST_USBTXEP2 << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBTXEP2 Setting */ -#define MXC_V_DMA_CTRL_REQUEST_USBTXEP3 ((uint32_t)0x33UL) /**< CTRL_REQUEST_USBTXEP3 Value */ -#define MXC_S_DMA_CTRL_REQUEST_USBTXEP3 (MXC_V_DMA_CTRL_REQUEST_USBTXEP3 << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBTXEP3 Setting */ -#define MXC_V_DMA_CTRL_REQUEST_USBTXEP4 ((uint32_t)0x34UL) /**< CTRL_REQUEST_USBTXEP4 Value */ -#define MXC_S_DMA_CTRL_REQUEST_USBTXEP4 (MXC_V_DMA_CTRL_REQUEST_USBTXEP4 << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBTXEP4 Setting */ -#define MXC_V_DMA_CTRL_REQUEST_USBTXEP5 ((uint32_t)0x35UL) /**< CTRL_REQUEST_USBTXEP5 Value */ -#define MXC_S_DMA_CTRL_REQUEST_USBTXEP5 (MXC_V_DMA_CTRL_REQUEST_USBTXEP5 << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBTXEP5 Setting */ -#define MXC_V_DMA_CTRL_REQUEST_USBTXEP6 ((uint32_t)0x36UL) /**< CTRL_REQUEST_USBTXEP6 Value */ -#define MXC_S_DMA_CTRL_REQUEST_USBTXEP6 (MXC_V_DMA_CTRL_REQUEST_USBTXEP6 << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBTXEP6 Setting */ -#define MXC_V_DMA_CTRL_REQUEST_USBTXEP7 ((uint32_t)0x37UL) /**< CTRL_REQUEST_USBTXEP7 Value */ -#define MXC_S_DMA_CTRL_REQUEST_USBTXEP7 (MXC_V_DMA_CTRL_REQUEST_USBTXEP7 << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBTXEP7 Setting */ -#define MXC_V_DMA_CTRL_REQUEST_USBTXEP8 ((uint32_t)0x38UL) /**< CTRL_REQUEST_USBTXEP8 Value */ -#define MXC_S_DMA_CTRL_REQUEST_USBTXEP8 (MXC_V_DMA_CTRL_REQUEST_USBTXEP8 << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBTXEP8 Setting */ -#define MXC_V_DMA_CTRL_REQUEST_USBTXEP9 ((uint32_t)0x39UL) /**< CTRL_REQUEST_USBTXEP9 Value */ -#define MXC_S_DMA_CTRL_REQUEST_USBTXEP9 (MXC_V_DMA_CTRL_REQUEST_USBTXEP9 << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBTXEP9 Setting */ -#define MXC_V_DMA_CTRL_REQUEST_USBTXEP10 ((uint32_t)0x3AUL) /**< CTRL_REQUEST_USBTXEP10 Value */ -#define MXC_S_DMA_CTRL_REQUEST_USBTXEP10 (MXC_V_DMA_CTRL_REQUEST_USBTXEP10 << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBTXEP10 Setting */ -#define MXC_V_DMA_CTRL_REQUEST_USBTXEP11 ((uint32_t)0x3BUL) /**< CTRL_REQUEST_USBTXEP11 Value */ -#define MXC_S_DMA_CTRL_REQUEST_USBTXEP11 (MXC_V_DMA_CTRL_REQUEST_USBTXEP11 << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBTXEP11 Setting */ +#define MXC_V_DMA_CTRL_REQUEST_AESTX ((uint32_t)0x30UL) /**< CTRL_REQUEST_AESTX Value */ +#define MXC_S_DMA_CTRL_REQUEST_AESTX (MXC_V_DMA_CTRL_REQUEST_AESTX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_AESTX Setting */ #define MXC_V_DMA_CTRL_REQUEST_UART3TX ((uint32_t)0x3CUL) /**< CTRL_REQUEST_UART3TX Value */ #define MXC_S_DMA_CTRL_REQUEST_UART3TX (MXC_V_DMA_CTRL_REQUEST_UART3TX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UART3TX Setting */ +#define MXC_V_DMA_CTRL_REQUEST_I2STX ((uint32_t)0x3EUL) /**< CTRL_REQUEST_I2STX Value */ +#define MXC_S_DMA_CTRL_REQUEST_I2STX (MXC_V_DMA_CTRL_REQUEST_I2STX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I2STX Setting */ #define MXC_F_DMA_CTRL_TO_WAIT_POS 10 /**< CTRL_TO_WAIT Position */ #define MXC_F_DMA_CTRL_TO_WAIT ((uint32_t)(0x1UL << MXC_F_DMA_CTRL_TO_WAIT_POS)) /**< CTRL_TO_WAIT Mask */ @@ -519,4 +443,4 @@ typedef struct { } #endif -#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_DMA_REGS_H_ +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32672_INCLUDE_DMA_REGS_H_ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32572/Include/fcr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32572/Include/fcr_regs.h index 024b8655a91..a724871e65a 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32572/Include/fcr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32572/Include/fcr_regs.h @@ -25,8 +25,8 @@ * ******************************************************************************/ -#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_FCR_REGS_H_ -#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_FCR_REGS_H_ +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32672_INCLUDE_FCR_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32672_INCLUDE_FCR_REGS_H_ /* **** Includes **** */ #include @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile @@ -75,14 +79,14 @@ extern "C" { */ typedef struct { __IO uint32_t fctrl0; /**< \b 0x00: FCR FCTRL0 Register */ - __IO uint32_t fctrl1; /**< \b 0x04: FCR FCTRL1 Register */ - __R uint32_t rsv_0x8; - __IO uint32_t fctrl3; /**< \b 0x0C: FCR FCTRL3 Register */ - __IO uint32_t urvbootaddr; /**< \b 0x10: FCR URVBOOTADDR Register */ - __IO uint32_t urvctrl; /**< \b 0x14: FCR URVCTRL Register */ - __R uint32_t rsv_0x18; - __IO uint32_t gp; /**< \b 0x1C: FCR GP Register */ - __IO uint32_t trimctrl; /**< \b 0x20: FCR TRIMCTRL Register */ + __IO uint32_t autocal0; /**< \b 0x04: FCR AUTOCAL0 Register */ + __IO uint32_t autocal1; /**< \b 0x08: FCR AUTOCAL1 Register */ + __IO uint32_t autocal2; /**< \b 0x0C: FCR AUTOCAL2 Register */ + __I uint32_t ts0; /**< \b 0x10: FCR TS0 Register */ + __I uint32_t ts1; /**< \b 0x14: FCR TS1 Register */ + __IO uint32_t adcreftrim0; /**< \b 0x18: FCR ADCREFTRIM0 Register */ + __IO uint32_t adcreftrim1; /**< \b 0x1C: FCR ADCREFTRIM1 Register */ + __IO uint32_t adcreftrim2; /**< \b 0x20: FCR ADCREFTRIM2 Register */ __IO uint32_t erfoks; /**< \b 0x24: FCR ERFOKS Register */ } mxc_fcr_regs_t; @@ -94,12 +98,14 @@ typedef struct { * @{ */ #define MXC_R_FCR_FCTRL0 ((uint32_t)0x00000000UL) /**< Offset from FCR Base Address: 0x0000 */ -#define MXC_R_FCR_FCTRL1 ((uint32_t)0x00000004UL) /**< Offset from FCR Base Address: 0x0004 */ -#define MXC_R_FCR_FCTRL3 ((uint32_t)0x0000000CUL) /**< Offset from FCR Base Address: 0x000C */ -#define MXC_R_FCR_URVBOOTADDR ((uint32_t)0x00000010UL) /**< Offset from FCR Base Address: 0x0010 */ -#define MXC_R_FCR_URVCTRL ((uint32_t)0x00000014UL) /**< Offset from FCR Base Address: 0x0014 */ -#define MXC_R_FCR_GP ((uint32_t)0x0000001CUL) /**< Offset from FCR Base Address: 0x001C */ -#define MXC_R_FCR_TRIMCTRL ((uint32_t)0x00000020UL) /**< Offset from FCR Base Address: 0x0020 */ +#define MXC_R_FCR_AUTOCAL0 ((uint32_t)0x00000004UL) /**< Offset from FCR Base Address: 0x0004 */ +#define MXC_R_FCR_AUTOCAL1 ((uint32_t)0x00000008UL) /**< Offset from FCR Base Address: 0x0008 */ +#define MXC_R_FCR_AUTOCAL2 ((uint32_t)0x0000000CUL) /**< Offset from FCR Base Address: 0x000C */ +#define MXC_R_FCR_TS0 ((uint32_t)0x00000010UL) /**< Offset from FCR Base Address: 0x0010 */ +#define MXC_R_FCR_TS1 ((uint32_t)0x00000014UL) /**< Offset from FCR Base Address: 0x0014 */ +#define MXC_R_FCR_ADCREFTRIM0 ((uint32_t)0x00000018UL) /**< Offset from FCR Base Address: 0x0018 */ +#define MXC_R_FCR_ADCREFTRIM1 ((uint32_t)0x0000001CUL) /**< Offset from FCR Base Address: 0x001C */ +#define MXC_R_FCR_ADCREFTRIM2 ((uint32_t)0x00000020UL) /**< Offset from FCR Base Address: 0x0020 */ #define MXC_R_FCR_ERFOKS ((uint32_t)0x00000024UL) /**< Offset from FCR Base Address: 0x0024 */ /**@} end of group fcr_registers */ @@ -109,135 +115,178 @@ typedef struct { * @brief Register 0. * @{ */ -#define MXC_F_FCR_FCTRL0_USBCLKSEL_POS 16 /**< FCTRL0_USBCLKSEL Position */ -#define MXC_F_FCR_FCTRL0_USBCLKSEL ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_USBCLKSEL_POS)) /**< FCTRL0_USBCLKSEL Mask */ +#define MXC_F_FCR_FCTRL0_ERFO_RANGE_SEL_POS 0 /**< FCTRL0_ERFO_RANGE_SEL Position */ +#define MXC_F_FCR_FCTRL0_ERFO_RANGE_SEL ((uint32_t)(0x7UL << MXC_F_FCR_FCTRL0_ERFO_RANGE_SEL_POS)) /**< FCTRL0_ERFO_RANGE_SEL Mask */ + +#define MXC_F_FCR_FCTRL0_KEYWIPE_SYS_POS 8 /**< FCTRL0_KEYWIPE_SYS Position */ +#define MXC_F_FCR_FCTRL0_KEYWIPE_SYS ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_KEYWIPE_SYS_POS)) /**< FCTRL0_KEYWIPE_SYS Mask */ + +#define MXC_F_FCR_FCTRL0_I2C0_SDA_FILTER_EN_POS 20 /**< FCTRL0_I2C0_SDA_FILTER_EN Position */ +#define MXC_F_FCR_FCTRL0_I2C0_SDA_FILTER_EN ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C0_SDA_FILTER_EN_POS)) /**< FCTRL0_I2C0_SDA_FILTER_EN Mask */ -#define MXC_F_FCR_FCTRL0_I2C0DGEN0_POS 20 /**< FCTRL0_I2C0DGEN0 Position */ -#define MXC_F_FCR_FCTRL0_I2C0DGEN0 ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C0DGEN0_POS)) /**< FCTRL0_I2C0DGEN0 Mask */ +#define MXC_F_FCR_FCTRL0_I2C0_SCL_FILTER_EN_POS 21 /**< FCTRL0_I2C0_SCL_FILTER_EN Position */ +#define MXC_F_FCR_FCTRL0_I2C0_SCL_FILTER_EN ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C0_SCL_FILTER_EN_POS)) /**< FCTRL0_I2C0_SCL_FILTER_EN Mask */ -#define MXC_F_FCR_FCTRL0_I2C0DGEN1_POS 21 /**< FCTRL0_I2C0DGEN1 Position */ -#define MXC_F_FCR_FCTRL0_I2C0DGEN1 ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C0DGEN1_POS)) /**< FCTRL0_I2C0DGEN1 Mask */ +#define MXC_F_FCR_FCTRL0_I2C1_SDA_FILTER_EN_POS 22 /**< FCTRL0_I2C1_SDA_FILTER_EN Position */ +#define MXC_F_FCR_FCTRL0_I2C1_SDA_FILTER_EN ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C1_SDA_FILTER_EN_POS)) /**< FCTRL0_I2C1_SDA_FILTER_EN Mask */ -#define MXC_F_FCR_FCTRL0_I2C1DGEN0_POS 22 /**< FCTRL0_I2C1DGEN0 Position */ -#define MXC_F_FCR_FCTRL0_I2C1DGEN0 ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C1DGEN0_POS)) /**< FCTRL0_I2C1DGEN0 Mask */ +#define MXC_F_FCR_FCTRL0_I2C1_SCL_FILTER_EN_POS 23 /**< FCTRL0_I2C1_SCL_FILTER_EN Position */ +#define MXC_F_FCR_FCTRL0_I2C1_SCL_FILTER_EN ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C1_SCL_FILTER_EN_POS)) /**< FCTRL0_I2C1_SCL_FILTER_EN Mask */ -#define MXC_F_FCR_FCTRL0_I2C1DGEN1_POS 23 /**< FCTRL0_I2C1DGEN1 Position */ -#define MXC_F_FCR_FCTRL0_I2C1DGEN1 ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C1DGEN1_POS)) /**< FCTRL0_I2C1DGEN1 Mask */ +#define MXC_F_FCR_FCTRL0_I2C2_SDA_FILTER_EN_POS 24 /**< FCTRL0_I2C2_SDA_FILTER_EN Position */ +#define MXC_F_FCR_FCTRL0_I2C2_SDA_FILTER_EN ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C2_SDA_FILTER_EN_POS)) /**< FCTRL0_I2C2_SDA_FILTER_EN Mask */ + +#define MXC_F_FCR_FCTRL0_I2C2_SCL_FILTER_EN_POS 25 /**< FCTRL0_I2C2_SCL_FILTER_EN Position */ +#define MXC_F_FCR_FCTRL0_I2C2_SCL_FILTER_EN ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C2_SCL_FILTER_EN_POS)) /**< FCTRL0_I2C2_SCL_FILTER_EN Mask */ /**@} end of group FCR_FCTRL0_Register */ /** * @ingroup fcr_registers - * @defgroup FCR_FCTRL1 FCR_FCTRL1 + * @defgroup FCR_AUTOCAL0 FCR_AUTOCAL0 * @brief Register 1. * @{ */ -#define MXC_F_FCR_FCTRL1_AC_EN_POS 0 /**< FCTRL1_AC_EN Position */ -#define MXC_F_FCR_FCTRL1_AC_EN ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL1_AC_EN_POS)) /**< FCTRL1_AC_EN Mask */ +#define MXC_F_FCR_AUTOCAL0_SEL_POS 0 /**< AUTOCAL0_SEL Position */ +#define MXC_F_FCR_AUTOCAL0_SEL ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL0_SEL_POS)) /**< AUTOCAL0_SEL Mask */ -#define MXC_F_FCR_FCTRL1_AC_RUN_POS 1 /**< FCTRL1_AC_RUN Position */ -#define MXC_F_FCR_FCTRL1_AC_RUN ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL1_AC_RUN_POS)) /**< FCTRL1_AC_RUN Mask */ +#define MXC_F_FCR_AUTOCAL0_EN_POS 1 /**< AUTOCAL0_EN Position */ +#define MXC_F_FCR_AUTOCAL0_EN ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL0_EN_POS)) /**< AUTOCAL0_EN Mask */ -#define MXC_F_FCR_FCTRL1_LOAD_POS 2 /**< FCTRL1_LOAD Position */ -#define MXC_F_FCR_FCTRL1_LOAD ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL1_LOAD_POS)) /**< FCTRL1_LOAD Mask */ +#define MXC_F_FCR_AUTOCAL0_LOAD_POS 2 /**< AUTOCAL0_LOAD Position */ +#define MXC_F_FCR_AUTOCAL0_LOAD ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL0_LOAD_POS)) /**< AUTOCAL0_LOAD Mask */ -#define MXC_F_FCR_FCTRL1_INV_GAIN_POS 3 /**< FCTRL1_INV_GAIN Position */ -#define MXC_F_FCR_FCTRL1_INV_GAIN ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL1_INV_GAIN_POS)) /**< FCTRL1_INV_GAIN Mask */ +#define MXC_F_FCR_AUTOCAL0_INVERT_POS 3 /**< AUTOCAL0_INVERT Position */ +#define MXC_F_FCR_AUTOCAL0_INVERT ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL0_INVERT_POS)) /**< AUTOCAL0_INVERT Mask */ -#define MXC_F_FCR_FCTRL1_ATOMIC_POS 4 /**< FCTRL1_ATOMIC Position */ -#define MXC_F_FCR_FCTRL1_ATOMIC ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL1_ATOMIC_POS)) /**< FCTRL1_ATOMIC Mask */ +#define MXC_F_FCR_AUTOCAL0_ATOMIC_POS 4 /**< AUTOCAL0_ATOMIC Position */ +#define MXC_F_FCR_AUTOCAL0_ATOMIC ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL0_ATOMIC_POS)) /**< AUTOCAL0_ATOMIC Mask */ -#define MXC_F_FCR_FCTRL1_MU_POS 8 /**< FCTRL1_MU Position */ -#define MXC_F_FCR_FCTRL1_MU ((uint32_t)(0xFFFUL << MXC_F_FCR_FCTRL1_MU_POS)) /**< FCTRL1_MU Mask */ +#define MXC_F_FCR_AUTOCAL0_GAIN_POS 8 /**< AUTOCAL0_GAIN Position */ +#define MXC_F_FCR_AUTOCAL0_GAIN ((uint32_t)(0xFFFUL << MXC_F_FCR_AUTOCAL0_GAIN_POS)) /**< AUTOCAL0_GAIN Mask */ -#define MXC_F_FCR_FCTRL1_AC_TRIM_POS 23 /**< FCTRL1_AC_TRIM Position */ -#define MXC_F_FCR_FCTRL1_AC_TRIM ((uint32_t)(0x1FFUL << MXC_F_FCR_FCTRL1_AC_TRIM_POS)) /**< FCTRL1_AC_TRIM Mask */ +#define MXC_F_FCR_AUTOCAL0_TRIM_POS 23 /**< AUTOCAL0_TRIM Position */ +#define MXC_F_FCR_AUTOCAL0_TRIM ((uint32_t)(0x1FFUL << MXC_F_FCR_AUTOCAL0_TRIM_POS)) /**< AUTOCAL0_TRIM Mask */ -/**@} end of group FCR_FCTRL1_Register */ +/**@} end of group FCR_AUTOCAL0_Register */ /** * @ingroup fcr_registers - * @defgroup FCR_FCTRL3 FCR_FCTRL3 + * @defgroup FCR_AUTOCAL1 FCR_AUTOCAL1 + * @brief Register 2. + * @{ + */ +#define MXC_F_FCR_AUTOCAL1_INITIAL_POS 0 /**< AUTOCAL1_INITIAL Position */ +#define MXC_F_FCR_AUTOCAL1_INITIAL ((uint32_t)(0x1FFUL << MXC_F_FCR_AUTOCAL1_INITIAL_POS)) /**< AUTOCAL1_INITIAL Mask */ + +/**@} end of group FCR_AUTOCAL1_Register */ + +/** + * @ingroup fcr_registers + * @defgroup FCR_AUTOCAL2 FCR_AUTOCAL2 * @brief Register 3. * @{ */ -#define MXC_F_FCR_FCTRL3_DONECNT_POS 0 /**< FCTRL3_DONECNT Position */ -#define MXC_F_FCR_FCTRL3_DONECNT ((uint32_t)(0xFFUL << MXC_F_FCR_FCTRL3_DONECNT_POS)) /**< FCTRL3_DONECNT Mask */ +#define MXC_F_FCR_AUTOCAL2_RUNTIME_POS 0 /**< AUTOCAL2_RUNTIME Position */ +#define MXC_F_FCR_AUTOCAL2_RUNTIME ((uint32_t)(0xFFUL << MXC_F_FCR_AUTOCAL2_RUNTIME_POS)) /**< AUTOCAL2_RUNTIME Mask */ + +#define MXC_F_FCR_AUTOCAL2_DIV_POS 8 /**< AUTOCAL2_DIV Position */ +#define MXC_F_FCR_AUTOCAL2_DIV ((uint32_t)(0x1FFFUL << MXC_F_FCR_AUTOCAL2_DIV_POS)) /**< AUTOCAL2_DIV Mask */ -/**@} end of group FCR_FCTRL3_Register */ +/**@} end of group FCR_AUTOCAL2_Register */ /** * @ingroup fcr_registers - * @defgroup FCR_URVBOOTADDR FCR_URVBOOTADDR + * @defgroup FCR_TS0 FCR_TS0 * @brief Register 4. * @{ */ -#define MXC_F_FCR_URVBOOTADDR_BOOTADDR_POS 0 /**< URVBOOTADDR_BOOTADDR Position */ -#define MXC_F_FCR_URVBOOTADDR_BOOTADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_FCR_URVBOOTADDR_BOOTADDR_POS)) /**< URVBOOTADDR_BOOTADDR Mask */ +#define MXC_F_FCR_TS0_GAIN_POS 0 /**< TS0_GAIN Position */ +#define MXC_F_FCR_TS0_GAIN ((uint32_t)(0xFFFUL << MXC_F_FCR_TS0_GAIN_POS)) /**< TS0_GAIN Mask */ -/**@} end of group FCR_URVBOOTADDR_Register */ +/**@} end of group FCR_TS0_Register */ /** * @ingroup fcr_registers - * @defgroup FCR_URVCTRL FCR_URVCTRL + * @defgroup FCR_TS1 FCR_TS1 * @brief Register 5. * @{ */ -#define MXC_F_FCR_URVCTRL_SLEEP_REQ_POS 0 /**< URVCTRL_SLEEP_REQ Position */ -#define MXC_F_FCR_URVCTRL_SLEEP_REQ ((uint32_t)(0x1UL << MXC_F_FCR_URVCTRL_SLEEP_REQ_POS)) /**< URVCTRL_SLEEP_REQ Mask */ +#define MXC_F_FCR_TS1_OFFSET_POS 0 /**< TS1_OFFSET Position */ +#define MXC_F_FCR_TS1_OFFSET ((uint32_t)(0xFFFFFFFFUL << MXC_F_FCR_TS1_OFFSET_POS)) /**< TS1_OFFSET Mask */ -#define MXC_F_FCR_URVCTRL_SLEEP_ACK_POS 1 /**< URVCTRL_SLEEP_ACK Position */ -#define MXC_F_FCR_URVCTRL_SLEEP_ACK ((uint32_t)(0x1UL << MXC_F_FCR_URVCTRL_SLEEP_ACK_POS)) /**< URVCTRL_SLEEP_ACK Mask */ +/**@} end of group FCR_TS1_Register */ -/**@} end of group FCR_URVCTRL_Register */ +/** + * @ingroup fcr_registers + * @defgroup FCR_ADCREFTRIM0 FCR_ADCREFTRIM0 + * @brief ADC Reference Trim 0 + * @{ + */ +#define MXC_F_FCR_ADCREFTRIM0_VREFP_POS 0 /**< ADCREFTRIM0_VREFP Position */ +#define MXC_F_FCR_ADCREFTRIM0_VREFP ((uint32_t)(0x7FUL << MXC_F_FCR_ADCREFTRIM0_VREFP_POS)) /**< ADCREFTRIM0_VREFP Mask */ + +#define MXC_F_FCR_ADCREFTRIM0_VREFM_POS 8 /**< ADCREFTRIM0_VREFM Position */ +#define MXC_F_FCR_ADCREFTRIM0_VREFM ((uint32_t)(0x7FUL << MXC_F_FCR_ADCREFTRIM0_VREFM_POS)) /**< ADCREFTRIM0_VREFM Mask */ + +#define MXC_F_FCR_ADCREFTRIM0_VCM_POS 16 /**< ADCREFTRIM0_VCM Position */ +#define MXC_F_FCR_ADCREFTRIM0_VCM ((uint32_t)(0x3UL << MXC_F_FCR_ADCREFTRIM0_VCM_POS)) /**< ADCREFTRIM0_VCM Mask */ + +#define MXC_F_FCR_ADCREFTRIM0_VX2_TUNE_POS 24 /**< ADCREFTRIM0_VX2_TUNE Position */ +#define MXC_F_FCR_ADCREFTRIM0_VX2_TUNE ((uint32_t)(0x3FUL << MXC_F_FCR_ADCREFTRIM0_VX2_TUNE_POS)) /**< ADCREFTRIM0_VX2_TUNE Mask */ + +/**@} end of group FCR_ADCREFTRIM0_Register */ /** * @ingroup fcr_registers - * @defgroup FCR_GP FCR_GP - * @brief General Purpose Register. + * @defgroup FCR_ADCREFTRIM1 FCR_ADCREFTRIM1 + * @brief ADC Reference Trim 1 * @{ */ -#define MXC_F_FCR_GP_GP_POS 0 /**< GP_GP Position */ -#define MXC_F_FCR_GP_GP ((uint32_t)(0xFFFFFFFFUL << MXC_F_FCR_GP_GP_POS)) /**< GP_GP Mask */ +#define MXC_F_FCR_ADCREFTRIM1_VREFP_POS 0 /**< ADCREFTRIM1_VREFP Position */ +#define MXC_F_FCR_ADCREFTRIM1_VREFP ((uint32_t)(0x7FUL << MXC_F_FCR_ADCREFTRIM1_VREFP_POS)) /**< ADCREFTRIM1_VREFP Mask */ + +#define MXC_F_FCR_ADCREFTRIM1_VREFM_POS 8 /**< ADCREFTRIM1_VREFM Position */ +#define MXC_F_FCR_ADCREFTRIM1_VREFM ((uint32_t)(0x7FUL << MXC_F_FCR_ADCREFTRIM1_VREFM_POS)) /**< ADCREFTRIM1_VREFM Mask */ + +#define MXC_F_FCR_ADCREFTRIM1_VCM_POS 16 /**< ADCREFTRIM1_VCM Position */ +#define MXC_F_FCR_ADCREFTRIM1_VCM ((uint32_t)(0x3UL << MXC_F_FCR_ADCREFTRIM1_VCM_POS)) /**< ADCREFTRIM1_VCM Mask */ -/**@} end of group FCR_GP_Register */ +#define MXC_F_FCR_ADCREFTRIM1_VX2_TUNE_POS 24 /**< ADCREFTRIM1_VX2_TUNE Position */ +#define MXC_F_FCR_ADCREFTRIM1_VX2_TUNE ((uint32_t)(0x3FUL << MXC_F_FCR_ADCREFTRIM1_VX2_TUNE_POS)) /**< ADCREFTRIM1_VX2_TUNE Mask */ + +/**@} end of group FCR_ADCREFTRIM1_Register */ /** * @ingroup fcr_registers - * @defgroup FCR_TRIMCTRL FCR_TRIMCTRL - * @brief MSR ADC Trim Register. + * @defgroup FCR_ADCREFTRIM2 FCR_ADCREFTRIM2 + * @brief ADC Reference Trim 2 * @{ */ -#define MXC_F_FCR_TRIMCTRL_MSR_R1_POS 0 /**< TRIMCTRL_MSR_R1 Position */ -#define MXC_F_FCR_TRIMCTRL_MSR_R1 ((uint32_t)(0x3UL << MXC_F_FCR_TRIMCTRL_MSR_R1_POS)) /**< TRIMCTRL_MSR_R1 Mask */ -#define MXC_V_FCR_TRIMCTRL_MSR_R1_0K ((uint32_t)0x0UL) /**< TRIMCTRL_MSR_R1_0K Value */ -#define MXC_S_FCR_TRIMCTRL_MSR_R1_0K (MXC_V_FCR_TRIMCTRL_MSR_R1_0K << MXC_F_FCR_TRIMCTRL_MSR_R1_POS) /**< TRIMCTRL_MSR_R1_0K Setting */ -#define MXC_V_FCR_TRIMCTRL_MSR_R1_1P2K ((uint32_t)0x1UL) /**< TRIMCTRL_MSR_R1_1P2K Value */ -#define MXC_S_FCR_TRIMCTRL_MSR_R1_1P2K (MXC_V_FCR_TRIMCTRL_MSR_R1_1P2K << MXC_F_FCR_TRIMCTRL_MSR_R1_POS) /**< TRIMCTRL_MSR_R1_1P2K Setting */ -#define MXC_V_FCR_TRIMCTRL_MSR_R1_2P4K ((uint32_t)0x2UL) /**< TRIMCTRL_MSR_R1_2P4K Value */ -#define MXC_S_FCR_TRIMCTRL_MSR_R1_2P4K (MXC_V_FCR_TRIMCTRL_MSR_R1_2P4K << MXC_F_FCR_TRIMCTRL_MSR_R1_POS) /**< TRIMCTRL_MSR_R1_2P4K Setting */ -#define MXC_V_FCR_TRIMCTRL_MSR_R1_4P8K ((uint32_t)0x3UL) /**< TRIMCTRL_MSR_R1_4P8K Value */ -#define MXC_S_FCR_TRIMCTRL_MSR_R1_4P8K (MXC_V_FCR_TRIMCTRL_MSR_R1_4P8K << MXC_F_FCR_TRIMCTRL_MSR_R1_POS) /**< TRIMCTRL_MSR_R1_4P8K Setting */ - -#define MXC_F_FCR_TRIMCTRL_MSR_R2_POS 2 /**< TRIMCTRL_MSR_R2 Position */ -#define MXC_F_FCR_TRIMCTRL_MSR_R2 ((uint32_t)(0x7UL << MXC_F_FCR_TRIMCTRL_MSR_R2_POS)) /**< TRIMCTRL_MSR_R2 Mask */ -#define MXC_V_FCR_TRIMCTRL_MSR_R2_OPEN ((uint32_t)0x0UL) /**< TRIMCTRL_MSR_R2_OPEN Value */ -#define MXC_S_FCR_TRIMCTRL_MSR_R2_OPEN (MXC_V_FCR_TRIMCTRL_MSR_R2_OPEN << MXC_F_FCR_TRIMCTRL_MSR_R2_POS) /**< TRIMCTRL_MSR_R2_OPEN Setting */ -#define MXC_V_FCR_TRIMCTRL_MSR_R2_3K ((uint32_t)0x4UL) /**< TRIMCTRL_MSR_R2_3K Value */ -#define MXC_S_FCR_TRIMCTRL_MSR_R2_3K (MXC_V_FCR_TRIMCTRL_MSR_R2_3K << MXC_F_FCR_TRIMCTRL_MSR_R2_POS) /**< TRIMCTRL_MSR_R2_3K Setting */ -#define MXC_V_FCR_TRIMCTRL_MSR_R2_6K ((uint32_t)0x5UL) /**< TRIMCTRL_MSR_R2_6K Value */ -#define MXC_S_FCR_TRIMCTRL_MSR_R2_6K (MXC_V_FCR_TRIMCTRL_MSR_R2_6K << MXC_F_FCR_TRIMCTRL_MSR_R2_POS) /**< TRIMCTRL_MSR_R2_6K Setting */ -#define MXC_V_FCR_TRIMCTRL_MSR_R2_12K ((uint32_t)0x6UL) /**< TRIMCTRL_MSR_R2_12K Value */ -#define MXC_S_FCR_TRIMCTRL_MSR_R2_12K (MXC_V_FCR_TRIMCTRL_MSR_R2_12K << MXC_F_FCR_TRIMCTRL_MSR_R2_POS) /**< TRIMCTRL_MSR_R2_12K Setting */ -#define MXC_V_FCR_TRIMCTRL_MSR_R2_24K ((uint32_t)0x7UL) /**< TRIMCTRL_MSR_R2_24K Value */ -#define MXC_S_FCR_TRIMCTRL_MSR_R2_24K (MXC_V_FCR_TRIMCTRL_MSR_R2_24K << MXC_F_FCR_TRIMCTRL_MSR_R2_POS) /**< TRIMCTRL_MSR_R2_24K Setting */ - -/**@} end of group FCR_TRIMCTRL_Register */ +#define MXC_F_FCR_ADCREFTRIM2_IDRV_1P25_POS 0 /**< ADCREFTRIM2_IDRV_1P25 Position */ +#define MXC_F_FCR_ADCREFTRIM2_IDRV_1P25 ((uint32_t)(0xFUL << MXC_F_FCR_ADCREFTRIM2_IDRV_1P25_POS)) /**< ADCREFTRIM2_IDRV_1P25 Mask */ + +#define MXC_F_FCR_ADCREFTRIM2_IBOOST_1P25_POS 4 /**< ADCREFTRIM2_IBOOST_1P25 Position */ +#define MXC_F_FCR_ADCREFTRIM2_IBOOST_1P25 ((uint32_t)(0x1UL << MXC_F_FCR_ADCREFTRIM2_IBOOST_1P25_POS)) /**< ADCREFTRIM2_IBOOST_1P25 Mask */ + +#define MXC_F_FCR_ADCREFTRIM2_IDRV_2P048_POS 8 /**< ADCREFTRIM2_IDRV_2P048 Position */ +#define MXC_F_FCR_ADCREFTRIM2_IDRV_2P048 ((uint32_t)(0xFUL << MXC_F_FCR_ADCREFTRIM2_IDRV_2P048_POS)) /**< ADCREFTRIM2_IDRV_2P048 Mask */ + +#define MXC_F_FCR_ADCREFTRIM2_IBOOST_2P048_POS 12 /**< ADCREFTRIM2_IBOOST_2P048 Position */ +#define MXC_F_FCR_ADCREFTRIM2_IBOOST_2P048 ((uint32_t)(0x1UL << MXC_F_FCR_ADCREFTRIM2_IBOOST_2P048_POS)) /**< ADCREFTRIM2_IBOOST_2P048 Mask */ + +#define MXC_F_FCR_ADCREFTRIM2_VCM_POS 16 /**< ADCREFTRIM2_VCM Position */ +#define MXC_F_FCR_ADCREFTRIM2_VCM ((uint32_t)(0x3UL << MXC_F_FCR_ADCREFTRIM2_VCM_POS)) /**< ADCREFTRIM2_VCM Mask */ + +#define MXC_F_FCR_ADCREFTRIM2_VX2_TUNE_POS 24 /**< ADCREFTRIM2_VX2_TUNE Position */ +#define MXC_F_FCR_ADCREFTRIM2_VX2_TUNE ((uint32_t)(0x3FUL << MXC_F_FCR_ADCREFTRIM2_VX2_TUNE_POS)) /**< ADCREFTRIM2_VX2_TUNE Mask */ + +/**@} end of group FCR_ADCREFTRIM2_Register */ /** * @ingroup fcr_registers * @defgroup FCR_ERFOKS FCR_ERFOKS - * @brief ERFO Kick Start Register. + * @brief External Radio Frequency Oscillator Kick Start Control Register. * @{ */ #define MXC_F_FCR_ERFOKS_CTRL_POS 0 /**< ERFOKS_CTRL Position */ @@ -249,4 +298,4 @@ typedef struct { } #endif -#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_FCR_REGS_H_ +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32672_INCLUDE_FCR_REGS_H_ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32572/Include/flc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32572/Include/flc_regs.h new file mode 100644 index 00000000000..b7f4d4bedb0 --- /dev/null +++ b/Libraries/CMSIS/Device/Maxim/MAX32572/Include/flc_regs.h @@ -0,0 +1,290 @@ +/** + * @file flc_regs.h + * @brief Registers, Bit Masks and Bit Positions for the FLC Peripheral Module. + * @note This file is @generated. + * @ingroup flc_registers + */ + +/****************************************************************************** + * + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32672_INCLUDE_FLC_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32672_INCLUDE_FLC_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup flc + * @defgroup flc_registers FLC_Registers + * @brief Registers, Bit Masks and Bit Positions for the FLC Peripheral Module. + * @details Flash Memory Control. + */ + +/** + * @ingroup flc_registers + * Structure type to access the FLC Registers. + */ +typedef struct { + __IO uint32_t addr; /**< \b 0x00: FLC ADDR Register */ + __IO uint32_t clkdiv; /**< \b 0x04: FLC CLKDIV Register */ + __IO uint32_t ctrl; /**< \b 0x08: FLC CTRL Register */ + __R uint32_t rsv_0xc_0x23[6]; + __IO uint32_t intr; /**< \b 0x024: FLC INTR Register */ + __R uint32_t rsv_0x28; + __IO uint32_t eccdata; /**< \b 0x2C: FLC ECCDATA Register */ + __IO uint32_t data[4]; /**< \b 0x30: FLC DATA Register */ + __O uint32_t actrl; /**< \b 0x40: FLC ACTRL Register */ + __R uint32_t rsv_0x44_0x7f[15]; + __IO uint32_t welr0; /**< \b 0x80: FLC WELR0 Register */ + __R uint32_t rsv_0x84; + __IO uint32_t welr1; /**< \b 0x88: FLC WELR1 Register */ + __R uint32_t rsv_0x8c; + __IO uint32_t rlr0; /**< \b 0x90: FLC RLR0 Register */ + __R uint32_t rsv_0x94; + __IO uint32_t rlr1; /**< \b 0x98: FLC RLR1 Register */ +} mxc_flc_regs_t; + +/* Register offsets for module FLC */ +/** + * @ingroup flc_registers + * @defgroup FLC_Register_Offsets Register Offsets + * @brief FLC Peripheral Register Offsets from the FLC Base Peripheral Address. + * @{ + */ +#define MXC_R_FLC_ADDR ((uint32_t)0x00000000UL) /**< Offset from FLC Base Address: 0x0000 */ +#define MXC_R_FLC_CLKDIV ((uint32_t)0x00000004UL) /**< Offset from FLC Base Address: 0x0004 */ +#define MXC_R_FLC_CTRL ((uint32_t)0x00000008UL) /**< Offset from FLC Base Address: 0x0008 */ +#define MXC_R_FLC_INTR ((uint32_t)0x00000024UL) /**< Offset from FLC Base Address: 0x0024 */ +#define MXC_R_FLC_ECCDATA ((uint32_t)0x0000002CUL) /**< Offset from FLC Base Address: 0x002C */ +#define MXC_R_FLC_DATA ((uint32_t)0x00000030UL) /**< Offset from FLC Base Address: 0x0030 */ +#define MXC_R_FLC_ACTRL ((uint32_t)0x00000040UL) /**< Offset from FLC Base Address: 0x0040 */ +#define MXC_R_FLC_WELR0 ((uint32_t)0x00000080UL) /**< Offset from FLC Base Address: 0x0080 */ +#define MXC_R_FLC_WELR1 ((uint32_t)0x00000088UL) /**< Offset from FLC Base Address: 0x0088 */ +#define MXC_R_FLC_RLR0 ((uint32_t)0x00000090UL) /**< Offset from FLC Base Address: 0x0090 */ +#define MXC_R_FLC_RLR1 ((uint32_t)0x00000098UL) /**< Offset from FLC Base Address: 0x0098 */ +/**@} end of group flc_registers */ + +/** + * @ingroup flc_registers + * @defgroup FLC_ADDR FLC_ADDR + * @brief Flash Write Address. + * @{ + */ +#define MXC_F_FLC_ADDR_ADDR_POS 0 /**< ADDR_ADDR Position */ +#define MXC_F_FLC_ADDR_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_ADDR_ADDR_POS)) /**< ADDR_ADDR Mask */ + +/**@} end of group FLC_ADDR_Register */ + +/** + * @ingroup flc_registers + * @defgroup FLC_CLKDIV FLC_CLKDIV + * @brief Flash Clock Divide. The clock (PLL0) is divided by this value to generate a 1 + * MHz clock for Flash controller. + * @{ + */ +#define MXC_F_FLC_CLKDIV_CLKDIV_POS 0 /**< CLKDIV_CLKDIV Position */ +#define MXC_F_FLC_CLKDIV_CLKDIV ((uint32_t)(0xFFUL << MXC_F_FLC_CLKDIV_CLKDIV_POS)) /**< CLKDIV_CLKDIV Mask */ + +/**@} end of group FLC_CLKDIV_Register */ + +/** + * @ingroup flc_registers + * @defgroup FLC_CTRL FLC_CTRL + * @brief Flash Control Register. + * @{ + */ +#define MXC_F_FLC_CTRL_WR_POS 0 /**< CTRL_WR Position */ +#define MXC_F_FLC_CTRL_WR ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_WR_POS)) /**< CTRL_WR Mask */ + +#define MXC_F_FLC_CTRL_ME_POS 1 /**< CTRL_ME Position */ +#define MXC_F_FLC_CTRL_ME ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_ME_POS)) /**< CTRL_ME Mask */ + +#define MXC_F_FLC_CTRL_PGE_POS 2 /**< CTRL_PGE Position */ +#define MXC_F_FLC_CTRL_PGE ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_PGE_POS)) /**< CTRL_PGE Mask */ + +#define MXC_F_FLC_CTRL_ERASE_CODE_POS 8 /**< CTRL_ERASE_CODE Position */ +#define MXC_F_FLC_CTRL_ERASE_CODE ((uint32_t)(0xFFUL << MXC_F_FLC_CTRL_ERASE_CODE_POS)) /**< CTRL_ERASE_CODE Mask */ +#define MXC_V_FLC_CTRL_ERASE_CODE_NOP ((uint32_t)0x0UL) /**< CTRL_ERASE_CODE_NOP Value */ +#define MXC_S_FLC_CTRL_ERASE_CODE_NOP (MXC_V_FLC_CTRL_ERASE_CODE_NOP << MXC_F_FLC_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_NOP Setting */ +#define MXC_V_FLC_CTRL_ERASE_CODE_ERASEPAGE ((uint32_t)0x55UL) /**< CTRL_ERASE_CODE_ERASEPAGE Value */ +#define MXC_S_FLC_CTRL_ERASE_CODE_ERASEPAGE (MXC_V_FLC_CTRL_ERASE_CODE_ERASEPAGE << MXC_F_FLC_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_ERASEPAGE Setting */ +#define MXC_V_FLC_CTRL_ERASE_CODE_ERASEALL ((uint32_t)0xAAUL) /**< CTRL_ERASE_CODE_ERASEALL Value */ +#define MXC_S_FLC_CTRL_ERASE_CODE_ERASEALL (MXC_V_FLC_CTRL_ERASE_CODE_ERASEALL << MXC_F_FLC_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_ERASEALL Setting */ + +#define MXC_F_FLC_CTRL_PEND_POS 24 /**< CTRL_PEND Position */ +#define MXC_F_FLC_CTRL_PEND ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_PEND_POS)) /**< CTRL_PEND Mask */ + +#define MXC_F_FLC_CTRL_LVE_POS 25 /**< CTRL_LVE Position */ +#define MXC_F_FLC_CTRL_LVE ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_LVE_POS)) /**< CTRL_LVE Mask */ + +#define MXC_F_FLC_CTRL_UNLOCK_POS 28 /**< CTRL_UNLOCK Position */ +#define MXC_F_FLC_CTRL_UNLOCK ((uint32_t)(0xFUL << MXC_F_FLC_CTRL_UNLOCK_POS)) /**< CTRL_UNLOCK Mask */ +#define MXC_V_FLC_CTRL_UNLOCK_UNLOCKED ((uint32_t)0x2UL) /**< CTRL_UNLOCK_UNLOCKED Value */ +#define MXC_S_FLC_CTRL_UNLOCK_UNLOCKED (MXC_V_FLC_CTRL_UNLOCK_UNLOCKED << MXC_F_FLC_CTRL_UNLOCK_POS) /**< CTRL_UNLOCK_UNLOCKED Setting */ +#define MXC_V_FLC_CTRL_UNLOCK_LOCKED ((uint32_t)0x3UL) /**< CTRL_UNLOCK_LOCKED Value */ +#define MXC_S_FLC_CTRL_UNLOCK_LOCKED (MXC_V_FLC_CTRL_UNLOCK_LOCKED << MXC_F_FLC_CTRL_UNLOCK_POS) /**< CTRL_UNLOCK_LOCKED Setting */ + +/**@} end of group FLC_CTRL_Register */ + +/** + * @ingroup flc_registers + * @defgroup FLC_INTR FLC_INTR + * @brief Flash Interrupt Register. + * @{ + */ +#define MXC_F_FLC_INTR_DONE_POS 0 /**< INTR_DONE Position */ +#define MXC_F_FLC_INTR_DONE ((uint32_t)(0x1UL << MXC_F_FLC_INTR_DONE_POS)) /**< INTR_DONE Mask */ + +#define MXC_F_FLC_INTR_AF_POS 1 /**< INTR_AF Position */ +#define MXC_F_FLC_INTR_AF ((uint32_t)(0x1UL << MXC_F_FLC_INTR_AF_POS)) /**< INTR_AF Mask */ + +#define MXC_F_FLC_INTR_DONEIE_POS 8 /**< INTR_DONEIE Position */ +#define MXC_F_FLC_INTR_DONEIE ((uint32_t)(0x1UL << MXC_F_FLC_INTR_DONEIE_POS)) /**< INTR_DONEIE Mask */ + +#define MXC_F_FLC_INTR_AFIE_POS 9 /**< INTR_AFIE Position */ +#define MXC_F_FLC_INTR_AFIE ((uint32_t)(0x1UL << MXC_F_FLC_INTR_AFIE_POS)) /**< INTR_AFIE Mask */ + +/**@} end of group FLC_INTR_Register */ + +/** + * @ingroup flc_registers + * @defgroup FLC_ECCDATA FLC_ECCDATA + * @brief ECC Data Register. + * @{ + */ +#define MXC_F_FLC_ECCDATA_EVEN_POS 0 /**< ECCDATA_EVEN Position */ +#define MXC_F_FLC_ECCDATA_EVEN ((uint32_t)(0x1FFUL << MXC_F_FLC_ECCDATA_EVEN_POS)) /**< ECCDATA_EVEN Mask */ + +#define MXC_F_FLC_ECCDATA_ODD_POS 16 /**< ECCDATA_ODD Position */ +#define MXC_F_FLC_ECCDATA_ODD ((uint32_t)(0x1FFUL << MXC_F_FLC_ECCDATA_ODD_POS)) /**< ECCDATA_ODD Mask */ + +/**@} end of group FLC_ECCDATA_Register */ + +/** + * @ingroup flc_registers + * @defgroup FLC_DATA FLC_DATA + * @brief Flash Write Data. + * @{ + */ +#define MXC_F_FLC_DATA_DATA_POS 0 /**< DATA_DATA Position */ +#define MXC_F_FLC_DATA_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_DATA_DATA_POS)) /**< DATA_DATA Mask */ + +/**@} end of group FLC_DATA_Register */ + +/** + * @ingroup flc_registers + * @defgroup FLC_ACTRL FLC_ACTRL + * @brief Access Control Register. Writing the ACTRL register with the following values in + * the order shown, allows read and write access to the system and user Information + * block: pflc-actrl = 0x3a7f5ca3; pflc-actrl = 0xa1e34f20; pflc-actrl + * = 0x9608b2c1. When unlocked, a write of any word will disable access to system + * and user information block. Readback of this register is always zero. + * @{ + */ +#define MXC_F_FLC_ACTRL_ACTRL_POS 0 /**< ACTRL_ACTRL Position */ +#define MXC_F_FLC_ACTRL_ACTRL ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_ACTRL_ACTRL_POS)) /**< ACTRL_ACTRL Mask */ + +/**@} end of group FLC_ACTRL_Register */ + +/** + * @ingroup flc_registers + * @defgroup FLC_WELR0 FLC_WELR0 + * @brief WELR0 + * @{ + */ +#define MXC_F_FLC_WELR0_WELR0_POS 0 /**< WELR0_WELR0 Position */ +#define MXC_F_FLC_WELR0_WELR0 ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_WELR0_WELR0_POS)) /**< WELR0_WELR0 Mask */ + +/**@} end of group FLC_WELR0_Register */ + +/** + * @ingroup flc_registers + * @defgroup FLC_WELR1 FLC_WELR1 + * @brief WELR1 + * @{ + */ +#define MXC_F_FLC_WELR1_WELR1_POS 0 /**< WELR1_WELR1 Position */ +#define MXC_F_FLC_WELR1_WELR1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_WELR1_WELR1_POS)) /**< WELR1_WELR1 Mask */ + +/**@} end of group FLC_WELR1_Register */ + +/** + * @ingroup flc_registers + * @defgroup FLC_RLR0 FLC_RLR0 + * @brief RLR0 + * @{ + */ +#define MXC_F_FLC_RLR0_RLR0_POS 0 /**< RLR0_RLR0 Position */ +#define MXC_F_FLC_RLR0_RLR0 ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_RLR0_RLR0_POS)) /**< RLR0_RLR0 Mask */ + +/**@} end of group FLC_RLR0_Register */ + +/** + * @ingroup flc_registers + * @defgroup FLC_RLR1 FLC_RLR1 + * @brief RLR1 + * @{ + */ +#define MXC_F_FLC_RLR1_RLR1_POS 0 /**< RLR1_RLR1 Position */ +#define MXC_F_FLC_RLR1_RLR1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_RLR1_RLR1_POS)) /**< RLR1_RLR1 Mask */ + +/**@} end of group FLC_RLR1_Register */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32672_INCLUDE_FLC_REGS_H_ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32572/Include/gcr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32572/Include/gcr_regs.h index eb87d0ffdd9..3fb4495a4a5 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32572/Include/gcr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32572/Include/gcr_regs.h @@ -25,8 +25,8 @@ * ******************************************************************************/ -#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_GCR_REGS_H_ -#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_GCR_REGS_H_ +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32672_INCLUDE_GCR_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32672_INCLUDE_GCR_REGS_H_ /* **** Includes **** */ #include @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile @@ -84,16 +88,18 @@ typedef struct { __IO uint32_t pclkdis0; /**< \b 0x24: GCR PCLKDIS0 Register */ __IO uint32_t memctrl; /**< \b 0x28: GCR MEMCTRL Register */ __IO uint32_t memz; /**< \b 0x2C: GCR MEMZ Register */ - __R uint32_t rsv_0x30; - __IO uint32_t scclkctrl; /**< \b 0x34: GCR SCCLKCTRL Register */ - __R uint32_t rsv_0x38_0x3f[2]; + __R uint32_t rsv_0x30_0x3f[4]; __IO uint32_t sysst; /**< \b 0x40: GCR SYSST Register */ __IO uint32_t rst1; /**< \b 0x44: GCR RST1 Register */ __IO uint32_t pclkdis1; /**< \b 0x48: GCR PCLKDIS1 Register */ __IO uint32_t eventen; /**< \b 0x4C: GCR EVENTEN Register */ __I uint32_t revision; /**< \b 0x50: GCR REVISION Register */ __IO uint32_t sysie; /**< \b 0x54: GCR SYSIE Register */ - __IO uint32_t ipocnt; /**< \b 0x58: GCR IPOCNT Register */ + __R uint32_t rsv_0x58_0x63[3]; + __IO uint32_t eccerr; /**< \b 0x64: GCR ECCERR Register */ + __IO uint32_t eccced; /**< \b 0x68: GCR ECCCED Register */ + __IO uint32_t eccie; /**< \b 0x6C: GCR ECCIE Register */ + __IO uint32_t eccaddr; /**< \b 0x70: GCR ECCADDR Register */ } mxc_gcr_regs_t; /* Register offsets for module GCR */ @@ -111,14 +117,16 @@ typedef struct { #define MXC_R_GCR_PCLKDIS0 ((uint32_t)0x00000024UL) /**< Offset from GCR Base Address: 0x0024 */ #define MXC_R_GCR_MEMCTRL ((uint32_t)0x00000028UL) /**< Offset from GCR Base Address: 0x0028 */ #define MXC_R_GCR_MEMZ ((uint32_t)0x0000002CUL) /**< Offset from GCR Base Address: 0x002C */ -#define MXC_R_GCR_SCCLKCTRL ((uint32_t)0x00000034UL) /**< Offset from GCR Base Address: 0x0034 */ #define MXC_R_GCR_SYSST ((uint32_t)0x00000040UL) /**< Offset from GCR Base Address: 0x0040 */ #define MXC_R_GCR_RST1 ((uint32_t)0x00000044UL) /**< Offset from GCR Base Address: 0x0044 */ #define MXC_R_GCR_PCLKDIS1 ((uint32_t)0x00000048UL) /**< Offset from GCR Base Address: 0x0048 */ #define MXC_R_GCR_EVENTEN ((uint32_t)0x0000004CUL) /**< Offset from GCR Base Address: 0x004C */ #define MXC_R_GCR_REVISION ((uint32_t)0x00000050UL) /**< Offset from GCR Base Address: 0x0050 */ #define MXC_R_GCR_SYSIE ((uint32_t)0x00000054UL) /**< Offset from GCR Base Address: 0x0054 */ -#define MXC_R_GCR_IPOCNT ((uint32_t)0x00000058UL) /**< Offset from GCR Base Address: 0x0058 */ +#define MXC_R_GCR_ECCERR ((uint32_t)0x00000064UL) /**< Offset from GCR Base Address: 0x0064 */ +#define MXC_R_GCR_ECCCED ((uint32_t)0x00000068UL) /**< Offset from GCR Base Address: 0x0068 */ +#define MXC_R_GCR_ECCIE ((uint32_t)0x0000006CUL) /**< Offset from GCR Base Address: 0x006C */ +#define MXC_R_GCR_ECCADDR ((uint32_t)0x00000070UL) /**< Offset from GCR Base Address: 0x0070 */ /**@} end of group gcr_registers */ /** @@ -127,9 +135,6 @@ typedef struct { * @brief System Control. * @{ */ -#define MXC_F_GCR_SYSCTRL_BSTAPEN_POS 0 /**< SYSCTRL_BSTAPEN Position */ -#define MXC_F_GCR_SYSCTRL_BSTAPEN ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_BSTAPEN_POS)) /**< SYSCTRL_BSTAPEN Mask */ - #define MXC_F_GCR_SYSCTRL_SBUSARB_POS 1 /**< SYSCTRL_SBUSARB Position */ #define MXC_F_GCR_SYSCTRL_SBUSARB ((uint32_t)(0x3UL << MXC_F_GCR_SYSCTRL_SBUSARB_POS)) /**< SYSCTRL_SBUSARB Mask */ #define MXC_V_GCR_SYSCTRL_SBUSARB_FIX ((uint32_t)0x0UL) /**< SYSCTRL_SBUSARB_FIX Value */ @@ -137,26 +142,23 @@ typedef struct { #define MXC_V_GCR_SYSCTRL_SBUSARB_ROUND ((uint32_t)0x1UL) /**< SYSCTRL_SBUSARB_ROUND Value */ #define MXC_S_GCR_SYSCTRL_SBUSARB_ROUND (MXC_V_GCR_SYSCTRL_SBUSARB_ROUND << MXC_F_GCR_SYSCTRL_SBUSARB_POS) /**< SYSCTRL_SBUSARB_ROUND Setting */ +#define MXC_F_GCR_SYSCTRL_FLASH_PAGE_FLIP_POS 4 /**< SYSCTRL_FLASH_PAGE_FLIP Position */ +#define MXC_F_GCR_SYSCTRL_FLASH_PAGE_FLIP ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_FLASH_PAGE_FLIP_POS)) /**< SYSCTRL_FLASH_PAGE_FLIP Mask */ + #define MXC_F_GCR_SYSCTRL_FPU_DIS_POS 5 /**< SYSCTRL_FPU_DIS Position */ #define MXC_F_GCR_SYSCTRL_FPU_DIS ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_FPU_DIS_POS)) /**< SYSCTRL_FPU_DIS Mask */ -#define MXC_F_GCR_SYSCTRL_SFCC_FLUSH_POS 6 /**< SYSCTRL_SFCC_FLUSH Position */ -#define MXC_F_GCR_SYSCTRL_SFCC_FLUSH ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_SFCC_FLUSH_POS)) /**< SYSCTRL_SFCC_FLUSH Mask */ +#define MXC_F_GCR_SYSCTRL_ICC0_FLUSH_POS 6 /**< SYSCTRL_ICC0_FLUSH Position */ +#define MXC_F_GCR_SYSCTRL_ICC0_FLUSH ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_ICC0_FLUSH_POS)) /**< SYSCTRL_ICC0_FLUSH Mask */ -#define MXC_F_GCR_SYSCTRL_CHKRES1_POS 11 /**< SYSCTRL_CHKRES1 Position */ -#define MXC_F_GCR_SYSCTRL_CHKRES1 ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_CHKRES1_POS)) /**< SYSCTRL_CHKRES1 Mask */ - -#define MXC_F_GCR_SYSCTRL_CCHK1_POS 12 /**< SYSCTRL_CCHK1 Position */ -#define MXC_F_GCR_SYSCTRL_CCHK1 ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_CCHK1_POS)) /**< SYSCTRL_CCHK1 Mask */ - -#define MXC_F_GCR_SYSCTRL_CCHK0_POS 13 /**< SYSCTRL_CCHK0 Position */ -#define MXC_F_GCR_SYSCTRL_CCHK0 ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_CCHK0_POS)) /**< SYSCTRL_CCHK0 Mask */ +#define MXC_F_GCR_SYSCTRL_CCHK_POS 13 /**< SYSCTRL_CCHK Position */ +#define MXC_F_GCR_SYSCTRL_CCHK ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_CCHK_POS)) /**< SYSCTRL_CCHK Mask */ #define MXC_F_GCR_SYSCTRL_SWD_DIS_POS 14 /**< SYSCTRL_SWD_DIS Position */ #define MXC_F_GCR_SYSCTRL_SWD_DIS ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_SWD_DIS_POS)) /**< SYSCTRL_SWD_DIS Mask */ -#define MXC_F_GCR_SYSCTRL_CHKRES0_POS 15 /**< SYSCTRL_CHKRES0 Position */ -#define MXC_F_GCR_SYSCTRL_CHKRES0 ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_CHKRES0_POS)) /**< SYSCTRL_CHKRES0 Mask */ +#define MXC_F_GCR_SYSCTRL_CHKRES_POS 15 /**< SYSCTRL_CHKRES Position */ +#define MXC_F_GCR_SYSCTRL_CHKRES ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_CHKRES_POS)) /**< SYSCTRL_CHKRES Mask */ /**@} end of group GCR_SYSCTRL_Register */ @@ -190,12 +192,6 @@ typedef struct { #define MXC_F_GCR_RST0_TMR3_POS 8 /**< RST0_TMR3 Position */ #define MXC_F_GCR_RST0_TMR3 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TMR3_POS)) /**< RST0_TMR3 Mask */ -#define MXC_F_GCR_RST0_TMR4_POS 9 /**< RST0_TMR4 Position */ -#define MXC_F_GCR_RST0_TMR4 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TMR4_POS)) /**< RST0_TMR4 Mask */ - -#define MXC_F_GCR_RST0_TMR5_POS 10 /**< RST0_TMR5 Position */ -#define MXC_F_GCR_RST0_TMR5 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TMR5_POS)) /**< RST0_TMR5 Mask */ - #define MXC_F_GCR_RST0_UART0_POS 11 /**< RST0_UART0 Position */ #define MXC_F_GCR_RST0_UART0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_UART0_POS)) /**< RST0_UART0 Mask */ @@ -208,14 +204,14 @@ typedef struct { #define MXC_F_GCR_RST0_SPI1_POS 14 /**< RST0_SPI1 Position */ #define MXC_F_GCR_RST0_SPI1 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SPI1_POS)) /**< RST0_SPI1 Mask */ +#define MXC_F_GCR_RST0_SPI2_POS 15 /**< RST0_SPI2 Position */ +#define MXC_F_GCR_RST0_SPI2 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SPI2_POS)) /**< RST0_SPI2 Mask */ + #define MXC_F_GCR_RST0_I2C0_POS 16 /**< RST0_I2C0 Position */ #define MXC_F_GCR_RST0_I2C0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_I2C0_POS)) /**< RST0_I2C0 Mask */ -#define MXC_F_GCR_RST0_CRYPTO_POS 18 /**< RST0_CRYPTO Position */ -#define MXC_F_GCR_RST0_CRYPTO ((uint32_t)(0x1UL << MXC_F_GCR_RST0_CRYPTO_POS)) /**< RST0_CRYPTO Mask */ - -#define MXC_F_GCR_RST0_USB_POS 23 /**< RST0_USB Position */ -#define MXC_F_GCR_RST0_USB ((uint32_t)(0x1UL << MXC_F_GCR_RST0_USB_POS)) /**< RST0_USB Mask */ +#define MXC_F_GCR_RST0_CTB_POS 18 /**< RST0_CTB Position */ +#define MXC_F_GCR_RST0_CTB ((uint32_t)(0x1UL << MXC_F_GCR_RST0_CTB_POS)) /**< RST0_CTB Mask */ #define MXC_F_GCR_RST0_TRNG_POS 24 /**< RST0_TRNG Position */ #define MXC_F_GCR_RST0_TRNG ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TRNG_POS)) /**< RST0_TRNG Mask */ @@ -243,17 +239,6 @@ typedef struct { * @brief Clock Control. * @{ */ -#define MXC_F_GCR_CLKCTRL_PCLK_DIV_POS 3 /**< CLKCTRL_PCLK_DIV Position */ -#define MXC_F_GCR_CLKCTRL_PCLK_DIV ((uint32_t)(0x7UL << MXC_F_GCR_CLKCTRL_PCLK_DIV_POS)) /**< CLKCTRL_PCLK_DIV Mask */ -#define MXC_V_GCR_CLKCTRL_PCLK_DIV_DIV1 ((uint32_t)0x0UL) /**< CLKCTRL_PCLK_DIV_DIV1 Value */ -#define MXC_S_GCR_CLKCTRL_PCLK_DIV_DIV1 (MXC_V_GCR_CLKCTRL_PCLK_DIV_DIV1 << MXC_F_GCR_CLKCTRL_PCLK_DIV_POS) /**< CLKCTRL_PCLK_DIV_DIV1 Setting */ -#define MXC_V_GCR_CLKCTRL_PCLK_DIV_DIV2 ((uint32_t)0x1UL) /**< CLKCTRL_PCLK_DIV_DIV2 Value */ -#define MXC_S_GCR_CLKCTRL_PCLK_DIV_DIV2 (MXC_V_GCR_CLKCTRL_PCLK_DIV_DIV2 << MXC_F_GCR_CLKCTRL_PCLK_DIV_POS) /**< CLKCTRL_PCLK_DIV_DIV2 Setting */ -#define MXC_V_GCR_CLKCTRL_PCLK_DIV_DIV4 ((uint32_t)0x2UL) /**< CLKCTRL_PCLK_DIV_DIV4 Value */ -#define MXC_S_GCR_CLKCTRL_PCLK_DIV_DIV4 (MXC_V_GCR_CLKCTRL_PCLK_DIV_DIV4 << MXC_F_GCR_CLKCTRL_PCLK_DIV_POS) /**< CLKCTRL_PCLK_DIV_DIV4 Setting */ -#define MXC_V_GCR_CLKCTRL_PCLK_DIV_DIV8 ((uint32_t)0x3UL) /**< CLKCTRL_PCLK_DIV_DIV8 Value */ -#define MXC_S_GCR_CLKCTRL_PCLK_DIV_DIV8 (MXC_V_GCR_CLKCTRL_PCLK_DIV_DIV8 << MXC_F_GCR_CLKCTRL_PCLK_DIV_POS) /**< CLKCTRL_PCLK_DIV_DIV8 Setting */ - #define MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS 6 /**< CLKCTRL_SYSCLK_DIV Position */ #define MXC_F_GCR_CLKCTRL_SYSCLK_DIV ((uint32_t)(0x7UL << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS)) /**< CLKCTRL_SYSCLK_DIV Mask */ #define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV1 ((uint32_t)0x0UL) /**< CLKCTRL_SYSCLK_DIV_DIV1 Value */ @@ -275,8 +260,6 @@ typedef struct { #define MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS 9 /**< CLKCTRL_SYSCLK_SEL Position */ #define MXC_F_GCR_CLKCTRL_SYSCLK_SEL ((uint32_t)(0x7UL << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS)) /**< CLKCTRL_SYSCLK_SEL Mask */ -#define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ISO ((uint32_t)0x0UL) /**< CLKCTRL_SYSCLK_SEL_ISO Value */ -#define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_ISO (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ISO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) /**< CLKCTRL_SYSCLK_SEL_ISO Setting */ #define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERFO ((uint32_t)0x2UL) /**< CLKCTRL_SYSCLK_SEL_ERFO Value */ #define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_ERFO (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERFO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) /**< CLKCTRL_SYSCLK_SEL_ERFO Setting */ #define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_INRO ((uint32_t)0x3UL) /**< CLKCTRL_SYSCLK_SEL_INRO Value */ @@ -287,9 +270,8 @@ typedef struct { #define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_IBRO (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IBRO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) /**< CLKCTRL_SYSCLK_SEL_IBRO Setting */ #define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERTCO ((uint32_t)0x6UL) /**< CLKCTRL_SYSCLK_SEL_ERTCO Value */ #define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_ERTCO (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERTCO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) /**< CLKCTRL_SYSCLK_SEL_ERTCO Setting */ - -#define MXC_F_GCR_CLKCTRL_CRYPTOCLK_DIV_POS 12 /**< CLKCTRL_CRYPTOCLK_DIV Position */ -#define MXC_F_GCR_CLKCTRL_CRYPTOCLK_DIV ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_CRYPTOCLK_DIV_POS)) /**< CLKCTRL_CRYPTOCLK_DIV Mask */ +#define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK ((uint32_t)0x7UL) /**< CLKCTRL_SYSCLK_SEL_EXTCLK Value */ +#define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) /**< CLKCTRL_SYSCLK_SEL_EXTCLK Setting */ #define MXC_F_GCR_CLKCTRL_SYSCLK_RDY_POS 13 /**< CLKCTRL_SYSCLK_RDY Position */ #define MXC_F_GCR_CLKCTRL_SYSCLK_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_SYSCLK_RDY_POS)) /**< CLKCTRL_SYSCLK_RDY Mask */ @@ -308,9 +290,6 @@ typedef struct { #define MXC_F_GCR_CLKCTRL_ERFO_EN_POS 16 /**< CLKCTRL_ERFO_EN Position */ #define MXC_F_GCR_CLKCTRL_ERFO_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_ERFO_EN_POS)) /**< CLKCTRL_ERFO_EN Mask */ -#define MXC_F_GCR_CLKCTRL_ISO_EN_POS 18 /**< CLKCTRL_ISO_EN Position */ -#define MXC_F_GCR_CLKCTRL_ISO_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_ISO_EN_POS)) /**< CLKCTRL_ISO_EN Mask */ - #define MXC_F_GCR_CLKCTRL_IPO_EN_POS 19 /**< CLKCTRL_IPO_EN Position */ #define MXC_F_GCR_CLKCTRL_IPO_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_IPO_EN_POS)) /**< CLKCTRL_IPO_EN Mask */ @@ -326,9 +305,6 @@ typedef struct { #define MXC_F_GCR_CLKCTRL_ERTCO_RDY_POS 25 /**< CLKCTRL_ERTCO_RDY Position */ #define MXC_F_GCR_CLKCTRL_ERTCO_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_ERTCO_RDY_POS)) /**< CLKCTRL_ERTCO_RDY Mask */ -#define MXC_F_GCR_CLKCTRL_ISO_RDY_POS 26 /**< CLKCTRL_ISO_RDY Position */ -#define MXC_F_GCR_CLKCTRL_ISO_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_ISO_RDY_POS)) /**< CLKCTRL_ISO_RDY Mask */ - #define MXC_F_GCR_CLKCTRL_IPO_RDY_POS 27 /**< CLKCTRL_IPO_RDY Position */ #define MXC_F_GCR_CLKCTRL_IPO_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_IPO_RDY_POS)) /**< CLKCTRL_IPO_RDY Mask */ @@ -338,6 +314,9 @@ typedef struct { #define MXC_F_GCR_CLKCTRL_INRO_RDY_POS 29 /**< CLKCTRL_INRO_RDY Position */ #define MXC_F_GCR_CLKCTRL_INRO_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_INRO_RDY_POS)) /**< CLKCTRL_INRO_RDY Mask */ +#define MXC_F_GCR_CLKCTRL_EXTCLK_RDY_POS 31 /**< CLKCTRL_EXTCLK_RDY Position */ +#define MXC_F_GCR_CLKCTRL_EXTCLK_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_EXTCLK_RDY_POS)) /**< CLKCTRL_EXTCLK_RDY Mask */ + /**@} end of group GCR_CLKCTRL_Register */ /** @@ -350,10 +329,6 @@ typedef struct { #define MXC_F_GCR_PM_MODE ((uint32_t)(0x7UL << MXC_F_GCR_PM_MODE_POS)) /**< PM_MODE Mask */ #define MXC_V_GCR_PM_MODE_ACTIVE ((uint32_t)0x0UL) /**< PM_MODE_ACTIVE Value */ #define MXC_S_GCR_PM_MODE_ACTIVE (MXC_V_GCR_PM_MODE_ACTIVE << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_ACTIVE Setting */ -#define MXC_V_GCR_PM_MODE_SLEEP ((uint32_t)0x1UL) /**< PM_MODE_SLEEP Value */ -#define MXC_S_GCR_PM_MODE_SLEEP (MXC_V_GCR_PM_MODE_SLEEP << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_SLEEP Setting */ -#define MXC_V_GCR_PM_MODE_DEEPSLEEP ((uint32_t)0x2UL) /**< PM_MODE_DEEPSLEEP Value */ -#define MXC_S_GCR_PM_MODE_DEEPSLEEP (MXC_V_GCR_PM_MODE_DEEPSLEEP << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_DEEPSLEEP Setting */ #define MXC_V_GCR_PM_MODE_SHUTDOWN ((uint32_t)0x3UL) /**< PM_MODE_SHUTDOWN Value */ #define MXC_S_GCR_PM_MODE_SHUTDOWN (MXC_V_GCR_PM_MODE_SHUTDOWN << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_SHUTDOWN Setting */ #define MXC_V_GCR_PM_MODE_BACKUP ((uint32_t)0x4UL) /**< PM_MODE_BACKUP Value */ @@ -365,15 +340,21 @@ typedef struct { #define MXC_F_GCR_PM_RTC_WE_POS 5 /**< PM_RTC_WE Position */ #define MXC_F_GCR_PM_RTC_WE ((uint32_t)(0x1UL << MXC_F_GCR_PM_RTC_WE_POS)) /**< PM_RTC_WE Mask */ -#define MXC_F_GCR_PM_USB_WE_POS 6 /**< PM_USB_WE Position */ -#define MXC_F_GCR_PM_USB_WE ((uint32_t)(0x1UL << MXC_F_GCR_PM_USB_WE_POS)) /**< PM_USB_WE Mask */ +#define MXC_F_GCR_PM_LPTMR0_WE_POS 6 /**< PM_LPTMR0_WE Position */ +#define MXC_F_GCR_PM_LPTMR0_WE ((uint32_t)(0x1UL << MXC_F_GCR_PM_LPTMR0_WE_POS)) /**< PM_LPTMR0_WE Mask */ + +#define MXC_F_GCR_PM_LPTMR1_WE_POS 7 /**< PM_LPTMR1_WE Position */ +#define MXC_F_GCR_PM_LPTMR1_WE ((uint32_t)(0x1UL << MXC_F_GCR_PM_LPTMR1_WE_POS)) /**< PM_LPTMR1_WE Mask */ + +#define MXC_F_GCR_PM_LPUART0_WE_POS 8 /**< PM_LPUART0_WE Position */ +#define MXC_F_GCR_PM_LPUART0_WE ((uint32_t)(0x1UL << MXC_F_GCR_PM_LPUART0_WE_POS)) /**< PM_LPUART0_WE Mask */ + +#define MXC_F_GCR_PM_AINCOMP_WE_POS 9 /**< PM_AINCOMP_WE Position */ +#define MXC_F_GCR_PM_AINCOMP_WE ((uint32_t)(0x1UL << MXC_F_GCR_PM_AINCOMP_WE_POS)) /**< PM_AINCOMP_WE Mask */ #define MXC_F_GCR_PM_ERFO_PD_POS 12 /**< PM_ERFO_PD Position */ #define MXC_F_GCR_PM_ERFO_PD ((uint32_t)(0x1UL << MXC_F_GCR_PM_ERFO_PD_POS)) /**< PM_ERFO_PD Mask */ -#define MXC_F_GCR_PM_ISO_PD_POS 15 /**< PM_ISO_PD Position */ -#define MXC_F_GCR_PM_ISO_PD ((uint32_t)(0x1UL << MXC_F_GCR_PM_ISO_PD_POS)) /**< PM_ISO_PD Mask */ - #define MXC_F_GCR_PM_IPO_PD_POS 16 /**< PM_IPO_PD Position */ #define MXC_F_GCR_PM_IPO_PD ((uint32_t)(0x1UL << MXC_F_GCR_PM_IPO_PD_POS)) /**< PM_IPO_PD Mask */ @@ -391,22 +372,30 @@ typedef struct { * @brief Peripheral Clock Divider. * @{ */ -#define MXC_F_GCR_PCLKDIV_SKBDFRQ_POS 0 /**< PCLKDIV_SKBDFRQ Position */ -#define MXC_F_GCR_PCLKDIV_SKBDFRQ ((uint32_t)(0x7UL << MXC_F_GCR_PCLKDIV_SKBDFRQ_POS)) /**< PCLKDIV_SKBDFRQ Mask */ - -#define MXC_F_GCR_PCLKDIV_ADCFRQ_POS 10 /**< PCLKDIV_ADCFRQ Position */ -#define MXC_F_GCR_PCLKDIV_ADCFRQ ((uint32_t)(0xFUL << MXC_F_GCR_PCLKDIV_ADCFRQ_POS)) /**< PCLKDIV_ADCFRQ Mask */ - -#define MXC_F_GCR_PCLKDIV_AONCLKDIV_POS 14 /**< PCLKDIV_AONCLKDIV Position */ -#define MXC_F_GCR_PCLKDIV_AONCLKDIV ((uint32_t)(0x3UL << MXC_F_GCR_PCLKDIV_AONCLKDIV_POS)) /**< PCLKDIV_AONCLKDIV Mask */ -#define MXC_V_GCR_PCLKDIV_AONCLKDIV_DIV4 ((uint32_t)0x0UL) /**< PCLKDIV_AONCLKDIV_DIV4 Value */ -#define MXC_S_GCR_PCLKDIV_AONCLKDIV_DIV4 (MXC_V_GCR_PCLKDIV_AONCLKDIV_DIV4 << MXC_F_GCR_PCLKDIV_AONCLKDIV_POS) /**< PCLKDIV_AONCLKDIV_DIV4 Setting */ -#define MXC_V_GCR_PCLKDIV_AONCLKDIV_DIV8 ((uint32_t)0x1UL) /**< PCLKDIV_AONCLKDIV_DIV8 Value */ -#define MXC_S_GCR_PCLKDIV_AONCLKDIV_DIV8 (MXC_V_GCR_PCLKDIV_AONCLKDIV_DIV8 << MXC_F_GCR_PCLKDIV_AONCLKDIV_POS) /**< PCLKDIV_AONCLKDIV_DIV8 Setting */ -#define MXC_V_GCR_PCLKDIV_AONCLKDIV_DIV16 ((uint32_t)0x2UL) /**< PCLKDIV_AONCLKDIV_DIV16 Value */ -#define MXC_S_GCR_PCLKDIV_AONCLKDIV_DIV16 (MXC_V_GCR_PCLKDIV_AONCLKDIV_DIV16 << MXC_F_GCR_PCLKDIV_AONCLKDIV_POS) /**< PCLKDIV_AONCLKDIV_DIV16 Setting */ -#define MXC_V_GCR_PCLKDIV_AONCLKDIV_DIV32 ((uint32_t)0x3UL) /**< PCLKDIV_AONCLKDIV_DIV32 Value */ -#define MXC_S_GCR_PCLKDIV_AONCLKDIV_DIV32 (MXC_V_GCR_PCLKDIV_AONCLKDIV_DIV32 << MXC_F_GCR_PCLKDIV_AONCLKDIV_POS) /**< PCLKDIV_AONCLKDIV_DIV32 Setting */ +#define MXC_F_GCR_PCLKDIV_AON_CLKDIV_POS 0 /**< PCLKDIV_AON_CLKDIV Position */ +#define MXC_F_GCR_PCLKDIV_AON_CLKDIV ((uint32_t)(0x7UL << MXC_F_GCR_PCLKDIV_AON_CLKDIV_POS)) /**< PCLKDIV_AON_CLKDIV Mask */ +#define MXC_V_GCR_PCLKDIV_AON_CLKDIV_DIV4 ((uint32_t)0x0UL) /**< PCLKDIV_AON_CLKDIV_DIV4 Value */ +#define MXC_S_GCR_PCLKDIV_AON_CLKDIV_DIV4 (MXC_V_GCR_PCLKDIV_AON_CLKDIV_DIV4 << MXC_F_GCR_PCLKDIV_AON_CLKDIV_POS) /**< PCLKDIV_AON_CLKDIV_DIV4 Setting */ +#define MXC_V_GCR_PCLKDIV_AON_CLKDIV_DIV8 ((uint32_t)0x1UL) /**< PCLKDIV_AON_CLKDIV_DIV8 Value */ +#define MXC_S_GCR_PCLKDIV_AON_CLKDIV_DIV8 (MXC_V_GCR_PCLKDIV_AON_CLKDIV_DIV8 << MXC_F_GCR_PCLKDIV_AON_CLKDIV_POS) /**< PCLKDIV_AON_CLKDIV_DIV8 Setting */ +#define MXC_V_GCR_PCLKDIV_AON_CLKDIV_DIV16 ((uint32_t)0x2UL) /**< PCLKDIV_AON_CLKDIV_DIV16 Value */ +#define MXC_S_GCR_PCLKDIV_AON_CLKDIV_DIV16 (MXC_V_GCR_PCLKDIV_AON_CLKDIV_DIV16 << MXC_F_GCR_PCLKDIV_AON_CLKDIV_POS) /**< PCLKDIV_AON_CLKDIV_DIV16 Setting */ +#define MXC_V_GCR_PCLKDIV_AON_CLKDIV_DIV32 ((uint32_t)0x3UL) /**< PCLKDIV_AON_CLKDIV_DIV32 Value */ +#define MXC_S_GCR_PCLKDIV_AON_CLKDIV_DIV32 (MXC_V_GCR_PCLKDIV_AON_CLKDIV_DIV32 << MXC_F_GCR_PCLKDIV_AON_CLKDIV_POS) /**< PCLKDIV_AON_CLKDIV_DIV32 Setting */ + +#define MXC_F_GCR_PCLKDIV_DIV_CLK_OUT_CTRL_POS 14 /**< PCLKDIV_DIV_CLK_OUT_CTRL Position */ +#define MXC_F_GCR_PCLKDIV_DIV_CLK_OUT_CTRL ((uint32_t)(0x3UL << MXC_F_GCR_PCLKDIV_DIV_CLK_OUT_CTRL_POS)) /**< PCLKDIV_DIV_CLK_OUT_CTRL Mask */ +#define MXC_V_GCR_PCLKDIV_DIV_CLK_OUT_CTRL_OFF ((uint32_t)0x0UL) /**< PCLKDIV_DIV_CLK_OUT_CTRL_OFF Value */ +#define MXC_S_GCR_PCLKDIV_DIV_CLK_OUT_CTRL_OFF (MXC_V_GCR_PCLKDIV_DIV_CLK_OUT_CTRL_OFF << MXC_F_GCR_PCLKDIV_DIV_CLK_OUT_CTRL_POS) /**< PCLKDIV_DIV_CLK_OUT_CTRL_OFF Setting */ +#define MXC_V_GCR_PCLKDIV_DIV_CLK_OUT_CTRL_DIV2 ((uint32_t)0x1UL) /**< PCLKDIV_DIV_CLK_OUT_CTRL_DIV2 Value */ +#define MXC_S_GCR_PCLKDIV_DIV_CLK_OUT_CTRL_DIV2 (MXC_V_GCR_PCLKDIV_DIV_CLK_OUT_CTRL_DIV2 << MXC_F_GCR_PCLKDIV_DIV_CLK_OUT_CTRL_POS) /**< PCLKDIV_DIV_CLK_OUT_CTRL_DIV2 Setting */ +#define MXC_V_GCR_PCLKDIV_DIV_CLK_OUT_CTRL_DIV4 ((uint32_t)0x2UL) /**< PCLKDIV_DIV_CLK_OUT_CTRL_DIV4 Value */ +#define MXC_S_GCR_PCLKDIV_DIV_CLK_OUT_CTRL_DIV4 (MXC_V_GCR_PCLKDIV_DIV_CLK_OUT_CTRL_DIV4 << MXC_F_GCR_PCLKDIV_DIV_CLK_OUT_CTRL_POS) /**< PCLKDIV_DIV_CLK_OUT_CTRL_DIV4 Setting */ +#define MXC_V_GCR_PCLKDIV_DIV_CLK_OUT_CTRL_DIV8 ((uint32_t)0x3UL) /**< PCLKDIV_DIV_CLK_OUT_CTRL_DIV8 Value */ +#define MXC_S_GCR_PCLKDIV_DIV_CLK_OUT_CTRL_DIV8 (MXC_V_GCR_PCLKDIV_DIV_CLK_OUT_CTRL_DIV8 << MXC_F_GCR_PCLKDIV_DIV_CLK_OUT_CTRL_POS) /**< PCLKDIV_DIV_CLK_OUT_CTRL_DIV8 Setting */ + +#define MXC_F_GCR_PCLKDIV_DIV_CLK_OUT_EN_POS 16 /**< PCLKDIV_DIV_CLK_OUT_EN Position */ +#define MXC_F_GCR_PCLKDIV_DIV_CLK_OUT_EN ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIV_DIV_CLK_OUT_EN_POS)) /**< PCLKDIV_DIV_CLK_OUT_EN Mask */ /**@} end of group GCR_PCLKDIV_Register */ @@ -422,9 +411,6 @@ typedef struct { #define MXC_F_GCR_PCLKDIS0_GPIO1_POS 1 /**< PCLKDIS0_GPIO1 Position */ #define MXC_F_GCR_PCLKDIS0_GPIO1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_GPIO1_POS)) /**< PCLKDIS0_GPIO1 Mask */ -#define MXC_F_GCR_PCLKDIS0_USB_POS 3 /**< PCLKDIS0_USB Position */ -#define MXC_F_GCR_PCLKDIS0_USB ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_USB_POS)) /**< PCLKDIS0_USB Mask */ - #define MXC_F_GCR_PCLKDIS0_DMA_POS 5 /**< PCLKDIS0_DMA Position */ #define MXC_F_GCR_PCLKDIS0_DMA ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_DMA_POS)) /**< PCLKDIS0_DMA Mask */ @@ -434,6 +420,9 @@ typedef struct { #define MXC_F_GCR_PCLKDIS0_SPI1_POS 7 /**< PCLKDIS0_SPI1 Position */ #define MXC_F_GCR_PCLKDIS0_SPI1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_SPI1_POS)) /**< PCLKDIS0_SPI1 Mask */ +#define MXC_F_GCR_PCLKDIS0_SPI2_POS 8 /**< PCLKDIS0_SPI2 Position */ +#define MXC_F_GCR_PCLKDIS0_SPI2 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_SPI2_POS)) /**< PCLKDIS0_SPI2 Mask */ + #define MXC_F_GCR_PCLKDIS0_UART0_POS 9 /**< PCLKDIS0_UART0 Position */ #define MXC_F_GCR_PCLKDIS0_UART0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_UART0_POS)) /**< PCLKDIS0_UART0 Mask */ @@ -443,8 +432,8 @@ typedef struct { #define MXC_F_GCR_PCLKDIS0_I2C0_POS 13 /**< PCLKDIS0_I2C0 Position */ #define MXC_F_GCR_PCLKDIS0_I2C0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_I2C0_POS)) /**< PCLKDIS0_I2C0 Mask */ -#define MXC_F_GCR_PCLKDIS0_CRYPTO_POS 14 /**< PCLKDIS0_CRYPTO Position */ -#define MXC_F_GCR_PCLKDIS0_CRYPTO ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_CRYPTO_POS)) /**< PCLKDIS0_CRYPTO Mask */ +#define MXC_F_GCR_PCLKDIS0_CTB_POS 14 /**< PCLKDIS0_CTB Position */ +#define MXC_F_GCR_PCLKDIS0_CTB ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_CTB_POS)) /**< PCLKDIS0_CTB Mask */ #define MXC_F_GCR_PCLKDIS0_TMR0_POS 15 /**< PCLKDIS0_TMR0 Position */ #define MXC_F_GCR_PCLKDIS0_TMR0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_TMR0_POS)) /**< PCLKDIS0_TMR0 Mask */ @@ -458,36 +447,12 @@ typedef struct { #define MXC_F_GCR_PCLKDIS0_TMR3_POS 18 /**< PCLKDIS0_TMR3 Position */ #define MXC_F_GCR_PCLKDIS0_TMR3 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_TMR3_POS)) /**< PCLKDIS0_TMR3 Mask */ -#define MXC_F_GCR_PCLKDIS0_TMR4_POS 19 /**< PCLKDIS0_TMR4 Position */ -#define MXC_F_GCR_PCLKDIS0_TMR4 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_TMR4_POS)) /**< PCLKDIS0_TMR4 Mask */ - -#define MXC_F_GCR_PCLKDIS0_TMR5_POS 20 /**< PCLKDIS0_TMR5 Position */ -#define MXC_F_GCR_PCLKDIS0_TMR5 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_TMR5_POS)) /**< PCLKDIS0_TMR5 Mask */ - -#define MXC_F_GCR_PCLKDIS0_SKBD_POS 22 /**< PCLKDIS0_SKBD Position */ -#define MXC_F_GCR_PCLKDIS0_SKBD ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_SKBD_POS)) /**< PCLKDIS0_SKBD Mask */ - #define MXC_F_GCR_PCLKDIS0_ADC_POS 23 /**< PCLKDIS0_ADC Position */ #define MXC_F_GCR_PCLKDIS0_ADC ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_ADC_POS)) /**< PCLKDIS0_ADC Mask */ -#define MXC_F_GCR_PCLKDIS0_HTMR0_POS 26 /**< PCLKDIS0_HTMR0 Position */ -#define MXC_F_GCR_PCLKDIS0_HTMR0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_HTMR0_POS)) /**< PCLKDIS0_HTMR0 Mask */ - -#define MXC_F_GCR_PCLKDIS0_HTMR1_POS 27 /**< PCLKDIS0_HTMR1 Position */ -#define MXC_F_GCR_PCLKDIS0_HTMR1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_HTMR1_POS)) /**< PCLKDIS0_HTMR1 Mask */ - #define MXC_F_GCR_PCLKDIS0_I2C1_POS 28 /**< PCLKDIS0_I2C1 Position */ #define MXC_F_GCR_PCLKDIS0_I2C1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_I2C1_POS)) /**< PCLKDIS0_I2C1 Mask */ -#define MXC_F_GCR_PCLKDIS0_PT_POS 29 /**< PCLKDIS0_PT Position */ -#define MXC_F_GCR_PCLKDIS0_PT ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_PT_POS)) /**< PCLKDIS0_PT Mask */ - -#define MXC_F_GCR_PCLKDIS0_SPIXIP_POS 30 /**< PCLKDIS0_SPIXIP Position */ -#define MXC_F_GCR_PCLKDIS0_SPIXIP ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_SPIXIP_POS)) /**< PCLKDIS0_SPIXIP Mask */ - -#define MXC_F_GCR_PCLKDIS0_SPIXIPC_POS 31 /**< PCLKDIS0_SPIXIPC Position */ -#define MXC_F_GCR_PCLKDIS0_SPIXIPC ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_SPIXIPC_POS)) /**< PCLKDIS0_SPIXIPC Mask */ - /**@} end of group GCR_PCLKDIS0_Register */ /** @@ -499,56 +464,26 @@ typedef struct { #define MXC_F_GCR_MEMCTRL_FWS_POS 0 /**< MEMCTRL_FWS Position */ #define MXC_F_GCR_MEMCTRL_FWS ((uint32_t)(0x7UL << MXC_F_GCR_MEMCTRL_FWS_POS)) /**< MEMCTRL_FWS Mask */ -#define MXC_F_GCR_MEMCTRL_RAM4_WS_POS 4 /**< MEMCTRL_RAM4_WS Position */ -#define MXC_F_GCR_MEMCTRL_RAM4_WS ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_RAM4_WS_POS)) /**< MEMCTRL_RAM4_WS Mask */ - -#define MXC_F_GCR_MEMCTRL_RAM5_WS_POS 5 /**< MEMCTRL_RAM5_WS Position */ -#define MXC_F_GCR_MEMCTRL_RAM5_WS ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_RAM5_WS_POS)) /**< MEMCTRL_RAM5_WS Mask */ +#define MXC_F_GCR_MEMCTRL_RAMWS_EN_POS 4 /**< MEMCTRL_RAMWS_EN Position */ +#define MXC_F_GCR_MEMCTRL_RAMWS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_RAMWS_EN_POS)) /**< MEMCTRL_RAMWS_EN Mask */ -#define MXC_F_GCR_MEMCTRL_RAM6_WS_POS 6 /**< MEMCTRL_RAM6_WS Position */ -#define MXC_F_GCR_MEMCTRL_RAM6_WS ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_RAM6_WS_POS)) /**< MEMCTRL_RAM6_WS Mask */ - -#define MXC_F_GCR_MEMCTRL_ROM1_WS_POS 7 /**< MEMCTRL_ROM1_WS Position */ -#define MXC_F_GCR_MEMCTRL_ROM1_WS ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_ROM1_WS_POS)) /**< MEMCTRL_ROM1_WS Mask */ - -#define MXC_F_GCR_MEMCTRL_RAM0LS_EN_POS 16 /**< MEMCTRL_RAM0LS_EN Position */ +#define MXC_F_GCR_MEMCTRL_RAM0LS_EN_POS 8 /**< MEMCTRL_RAM0LS_EN Position */ #define MXC_F_GCR_MEMCTRL_RAM0LS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_RAM0LS_EN_POS)) /**< MEMCTRL_RAM0LS_EN Mask */ -#define MXC_F_GCR_MEMCTRL_RAM1LS_EN_POS 17 /**< MEMCTRL_RAM1LS_EN Position */ +#define MXC_F_GCR_MEMCTRL_RAM1LS_EN_POS 9 /**< MEMCTRL_RAM1LS_EN Position */ #define MXC_F_GCR_MEMCTRL_RAM1LS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_RAM1LS_EN_POS)) /**< MEMCTRL_RAM1LS_EN Mask */ -#define MXC_F_GCR_MEMCTRL_RAM2LS_EN_POS 18 /**< MEMCTRL_RAM2LS_EN Position */ +#define MXC_F_GCR_MEMCTRL_RAM2LS_EN_POS 10 /**< MEMCTRL_RAM2LS_EN Position */ #define MXC_F_GCR_MEMCTRL_RAM2LS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_RAM2LS_EN_POS)) /**< MEMCTRL_RAM2LS_EN Mask */ -#define MXC_F_GCR_MEMCTRL_RAM3LS_EN_POS 19 /**< MEMCTRL_RAM3LS_EN Position */ +#define MXC_F_GCR_MEMCTRL_RAM3LS_EN_POS 11 /**< MEMCTRL_RAM3LS_EN Position */ #define MXC_F_GCR_MEMCTRL_RAM3LS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_RAM3LS_EN_POS)) /**< MEMCTRL_RAM3LS_EN Mask */ -#define MXC_F_GCR_MEMCTRL_RAM4LS_EN_POS 20 /**< MEMCTRL_RAM4LS_EN Position */ -#define MXC_F_GCR_MEMCTRL_RAM4LS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_RAM4LS_EN_POS)) /**< MEMCTRL_RAM4LS_EN Mask */ - -#define MXC_F_GCR_MEMCTRL_RAM5LS_EN_POS 21 /**< MEMCTRL_RAM5LS_EN Position */ -#define MXC_F_GCR_MEMCTRL_RAM5LS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_RAM5LS_EN_POS)) /**< MEMCTRL_RAM5LS_EN Mask */ - -#define MXC_F_GCR_MEMCTRL_RAM6LS_EN_POS 22 /**< MEMCTRL_RAM6LS_EN Position */ -#define MXC_F_GCR_MEMCTRL_RAM6LS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_RAM6LS_EN_POS)) /**< MEMCTRL_RAM6LS_EN Mask */ - -#define MXC_F_GCR_MEMCTRL_ICCXIPLS_EN_POS 25 /**< MEMCTRL_ICCXIPLS_EN Position */ -#define MXC_F_GCR_MEMCTRL_ICCXIPLS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_ICCXIPLS_EN_POS)) /**< MEMCTRL_ICCXIPLS_EN Mask */ - -#define MXC_F_GCR_MEMCTRL_CRYPTOLS_EN_POS 27 /**< MEMCTRL_CRYPTOLS_EN Position */ -#define MXC_F_GCR_MEMCTRL_CRYPTOLS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_CRYPTOLS_EN_POS)) /**< MEMCTRL_CRYPTOLS_EN Mask */ - -#define MXC_F_GCR_MEMCTRL_USBLS_EN_POS 28 /**< MEMCTRL_USBLS_EN Position */ -#define MXC_F_GCR_MEMCTRL_USBLS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_USBLS_EN_POS)) /**< MEMCTRL_USBLS_EN Mask */ - -#define MXC_F_GCR_MEMCTRL_ROM0LS_EN_POS 29 /**< MEMCTRL_ROM0LS_EN Position */ -#define MXC_F_GCR_MEMCTRL_ROM0LS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_ROM0LS_EN_POS)) /**< MEMCTRL_ROM0LS_EN Mask */ - -#define MXC_F_GCR_MEMCTRL_ROM1LS_EN_POS 30 /**< MEMCTRL_ROM1LS_EN Position */ -#define MXC_F_GCR_MEMCTRL_ROM1LS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_ROM1LS_EN_POS)) /**< MEMCTRL_ROM1LS_EN Mask */ +#define MXC_F_GCR_MEMCTRL_ICC0LS_EN_POS 12 /**< MEMCTRL_ICC0LS_EN Position */ +#define MXC_F_GCR_MEMCTRL_ICC0LS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_ICC0LS_EN_POS)) /**< MEMCTRL_ICC0LS_EN Mask */ -#define MXC_F_GCR_MEMCTRL_MAALS_EN_POS 31 /**< MEMCTRL_MAALS_EN Position */ -#define MXC_F_GCR_MEMCTRL_MAALS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_MAALS_EN_POS)) /**< MEMCTRL_MAALS_EN Mask */ +#define MXC_F_GCR_MEMCTRL_ROMLS_EN_POS 13 /**< MEMCTRL_ROMLS_EN Position */ +#define MXC_F_GCR_MEMCTRL_ROMLS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_ROMLS_EN_POS)) /**< MEMCTRL_ROMLS_EN Mask */ /**@} end of group GCR_MEMCTRL_Register */ @@ -567,43 +502,14 @@ typedef struct { #define MXC_F_GCR_MEMZ_RAM2_POS 2 /**< MEMZ_RAM2 Position */ #define MXC_F_GCR_MEMZ_RAM2 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAM2_POS)) /**< MEMZ_RAM2 Mask */ -#define MXC_F_GCR_MEMZ_RAM3_POS 3 /**< MEMZ_RAM3 Position */ -#define MXC_F_GCR_MEMZ_RAM3 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAM3_POS)) /**< MEMZ_RAM3 Mask */ +#define MXC_F_GCR_MEMZ_RAMCB_POS 3 /**< MEMZ_RAMCB Position */ +#define MXC_F_GCR_MEMZ_RAMCB ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAMCB_POS)) /**< MEMZ_RAMCB Mask */ -#define MXC_F_GCR_MEMZ_RAM4_POS 4 /**< MEMZ_RAM4 Position */ -#define MXC_F_GCR_MEMZ_RAM4 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAM4_POS)) /**< MEMZ_RAM4 Mask */ - -#define MXC_F_GCR_MEMZ_RAM5_POS 5 /**< MEMZ_RAM5 Position */ -#define MXC_F_GCR_MEMZ_RAM5 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAM5_POS)) /**< MEMZ_RAM5 Mask */ - -#define MXC_F_GCR_MEMZ_RAM6_POS 6 /**< MEMZ_RAM6 Position */ -#define MXC_F_GCR_MEMZ_RAM6 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAM6_POS)) /**< MEMZ_RAM6 Mask */ - -#define MXC_F_GCR_MEMZ_ICCXIP_POS 9 /**< MEMZ_ICCXIP Position */ -#define MXC_F_GCR_MEMZ_ICCXIP ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_ICCXIP_POS)) /**< MEMZ_ICCXIP Mask */ - -#define MXC_F_GCR_MEMZ_CRYPTO_POS 12 /**< MEMZ_CRYPTO Position */ -#define MXC_F_GCR_MEMZ_CRYPTO ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_CRYPTO_POS)) /**< MEMZ_CRYPTO Mask */ - -#define MXC_F_GCR_MEMZ_USBFIFO_POS 13 /**< MEMZ_USBFIFO Position */ -#define MXC_F_GCR_MEMZ_USBFIFO ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_USBFIFO_POS)) /**< MEMZ_USBFIFO Mask */ +#define MXC_F_GCR_MEMZ_ICC0_POS 4 /**< MEMZ_ICC0 Position */ +#define MXC_F_GCR_MEMZ_ICC0 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_ICC0_POS)) /**< MEMZ_ICC0 Mask */ /**@} end of group GCR_MEMZ_Register */ -/** - * @ingroup gcr_registers - * @defgroup GCR_SCCLKCTRL GCR_SCCLKCTRL - * @brief Smart Card Clock Control. - * @{ - */ -#define MXC_F_GCR_SCCLKCTRL_SC0CLK_DIV_POS 0 /**< SCCLKCTRL_SC0CLK_DIV Position */ -#define MXC_F_GCR_SCCLKCTRL_SC0CLK_DIV ((uint32_t)(0x3FUL << MXC_F_GCR_SCCLKCTRL_SC0CLK_DIV_POS)) /**< SCCLKCTRL_SC0CLK_DIV Mask */ - -#define MXC_F_GCR_SCCLKCTRL_SC1CLK_DIV_POS 8 /**< SCCLKCTRL_SC1CLK_DIV Position */ -#define MXC_F_GCR_SCCLKCTRL_SC1CLK_DIV ((uint32_t)(0x3FUL << MXC_F_GCR_SCCLKCTRL_SC1CLK_DIV_POS)) /**< SCCLKCTRL_SC1CLK_DIV Mask */ - -/**@} end of group GCR_SCCLKCTRL_Register */ - /** * @ingroup gcr_registers * @defgroup GCR_SYSST GCR_SYSST @@ -613,12 +519,6 @@ typedef struct { #define MXC_F_GCR_SYSST_ICELOCK_POS 0 /**< SYSST_ICELOCK Position */ #define MXC_F_GCR_SYSST_ICELOCK ((uint32_t)(0x1UL << MXC_F_GCR_SYSST_ICELOCK_POS)) /**< SYSST_ICELOCK Mask */ -#define MXC_F_GCR_SYSST_CODEINTERR_POS 1 /**< SYSST_CODEINTERR Position */ -#define MXC_F_GCR_SYSST_CODEINTERR ((uint32_t)(0x1UL << MXC_F_GCR_SYSST_CODEINTERR_POS)) /**< SYSST_CODEINTERR Mask */ - -#define MXC_F_GCR_SYSST_SCMEMF_POS 5 /**< SYSST_SCMEMF Position */ -#define MXC_F_GCR_SYSST_SCMEMF ((uint32_t)(0x1UL << MXC_F_GCR_SYSST_SCMEMF_POS)) /**< SYSST_SCMEMF Mask */ - /**@} end of group GCR_SYSST_Register */ /** @@ -630,50 +530,23 @@ typedef struct { #define MXC_F_GCR_RST1_I2C1_POS 0 /**< RST1_I2C1 Position */ #define MXC_F_GCR_RST1_I2C1 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_I2C1_POS)) /**< RST1_I2C1 Mask */ -#define MXC_F_GCR_RST1_PT_POS 1 /**< RST1_PT Position */ -#define MXC_F_GCR_RST1_PT ((uint32_t)(0x1UL << MXC_F_GCR_RST1_PT_POS)) /**< RST1_PT Mask */ - -#define MXC_F_GCR_RST1_SPIXIP_POS 3 /**< RST1_SPIXIP Position */ -#define MXC_F_GCR_RST1_SPIXIP ((uint32_t)(0x1UL << MXC_F_GCR_RST1_SPIXIP_POS)) /**< RST1_SPIXIP Mask */ - -#define MXC_F_GCR_RST1_SPIXIPM_POS 4 /**< RST1_SPIXIPM Position */ -#define MXC_F_GCR_RST1_SPIXIPM ((uint32_t)(0x1UL << MXC_F_GCR_RST1_SPIXIPM_POS)) /**< RST1_SPIXIPM Mask */ - #define MXC_F_GCR_RST1_WDT1_POS 8 /**< RST1_WDT1 Position */ #define MXC_F_GCR_RST1_WDT1 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_WDT1_POS)) /**< RST1_WDT1 Mask */ -#define MXC_F_GCR_RST1_SPI3_POS 9 /**< RST1_SPI3 Position */ -#define MXC_F_GCR_RST1_SPI3 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_SPI3_POS)) /**< RST1_SPI3 Mask */ +#define MXC_F_GCR_RST1_AES_POS 10 /**< RST1_AES Position */ +#define MXC_F_GCR_RST1_AES ((uint32_t)(0x1UL << MXC_F_GCR_RST1_AES_POS)) /**< RST1_AES Mask */ #define MXC_F_GCR_RST1_AC_POS 14 /**< RST1_AC Position */ #define MXC_F_GCR_RST1_AC ((uint32_t)(0x1UL << MXC_F_GCR_RST1_AC_POS)) /**< RST1_AC Mask */ -#define MXC_F_GCR_RST1_SEMA_POS 16 /**< RST1_SEMA Position */ -#define MXC_F_GCR_RST1_SEMA ((uint32_t)(0x1UL << MXC_F_GCR_RST1_SEMA_POS)) /**< RST1_SEMA Mask */ - -#define MXC_F_GCR_RST1_UART3_POS 18 /**< RST1_UART3 Position */ -#define MXC_F_GCR_RST1_UART3 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_UART3_POS)) /**< RST1_UART3 Mask */ - -#define MXC_F_GCR_RST1_SKBD_POS 21 /**< RST1_SKBD Position */ -#define MXC_F_GCR_RST1_SKBD ((uint32_t)(0x1UL << MXC_F_GCR_RST1_SKBD_POS)) /**< RST1_SKBD Mask */ - -#define MXC_F_GCR_RST1_MSRADC_POS 22 /**< RST1_MSRADC Position */ -#define MXC_F_GCR_RST1_MSRADC ((uint32_t)(0x1UL << MXC_F_GCR_RST1_MSRADC_POS)) /**< RST1_MSRADC Mask */ +#define MXC_F_GCR_RST1_I2C2_POS 17 /**< RST1_I2C2 Position */ +#define MXC_F_GCR_RST1_I2C2 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_I2C2_POS)) /**< RST1_I2C2 Mask */ -#define MXC_F_GCR_RST1_SC0_POS 23 /**< RST1_SC0 Position */ -#define MXC_F_GCR_RST1_SC0 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_SC0_POS)) /**< RST1_SC0 Mask */ +#define MXC_F_GCR_RST1_I2S_POS 23 /**< RST1_I2S Position */ +#define MXC_F_GCR_RST1_I2S ((uint32_t)(0x1UL << MXC_F_GCR_RST1_I2S_POS)) /**< RST1_I2S Mask */ -#define MXC_F_GCR_RST1_SC1_POS 24 /**< RST1_SC1 Position */ -#define MXC_F_GCR_RST1_SC1 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_SC1_POS)) /**< RST1_SC1 Mask */ - -#define MXC_F_GCR_RST1_HTMR0_POS 28 /**< RST1_HTMR0 Position */ -#define MXC_F_GCR_RST1_HTMR0 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_HTMR0_POS)) /**< RST1_HTMR0 Mask */ - -#define MXC_F_GCR_RST1_HTMR1_POS 29 /**< RST1_HTMR1 Position */ -#define MXC_F_GCR_RST1_HTMR1 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_HTMR1_POS)) /**< RST1_HTMR1 Mask */ - -#define MXC_F_GCR_RST1_CPU1_POS 31 /**< RST1_CPU1 Position */ -#define MXC_F_GCR_RST1_CPU1 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_CPU1_POS)) /**< RST1_CPU1 Mask */ +#define MXC_F_GCR_RST1_QDEC_POS 25 /**< RST1_QDEC Position */ +#define MXC_F_GCR_RST1_QDEC ((uint32_t)(0x1UL << MXC_F_GCR_RST1_QDEC_POS)) /**< RST1_QDEC Mask */ /**@} end of group GCR_RST1_Register */ @@ -689,35 +562,26 @@ typedef struct { #define MXC_F_GCR_PCLKDIS1_TRNG_POS 2 /**< PCLKDIS1_TRNG Position */ #define MXC_F_GCR_PCLKDIS1_TRNG ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_TRNG_POS)) /**< PCLKDIS1_TRNG Mask */ -#define MXC_F_GCR_PCLKDIS1_OTP_POS 3 /**< PCLKDIS1_OTP Position */ -#define MXC_F_GCR_PCLKDIS1_OTP ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_OTP_POS)) /**< PCLKDIS1_OTP Mask */ - #define MXC_F_GCR_PCLKDIS1_WDT0_POS 4 /**< PCLKDIS1_WDT0 Position */ #define MXC_F_GCR_PCLKDIS1_WDT0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_WDT0_POS)) /**< PCLKDIS1_WDT0 Mask */ #define MXC_F_GCR_PCLKDIS1_WDT1_POS 5 /**< PCLKDIS1_WDT1 Position */ #define MXC_F_GCR_PCLKDIS1_WDT1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_WDT1_POS)) /**< PCLKDIS1_WDT1 Mask */ -#define MXC_F_GCR_PCLKDIS1_SEMA_POS 9 /**< PCLKDIS1_SEMA Position */ -#define MXC_F_GCR_PCLKDIS1_SEMA ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_SEMA_POS)) /**< PCLKDIS1_SEMA Mask */ - -#define MXC_F_GCR_PCLKDIS1_SPI3_POS 14 /**< PCLKDIS1_SPI3 Position */ -#define MXC_F_GCR_PCLKDIS1_SPI3 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_SPI3_POS)) /**< PCLKDIS1_SPI3 Mask */ - -#define MXC_F_GCR_PCLKDIS1_UART3_POS 22 /**< PCLKDIS1_UART3 Position */ -#define MXC_F_GCR_PCLKDIS1_UART3 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_UART3_POS)) /**< PCLKDIS1_UART3 Mask */ +#define MXC_F_GCR_PCLKDIS1_ICC0_POS 11 /**< PCLKDIS1_ICC0 Position */ +#define MXC_F_GCR_PCLKDIS1_ICC0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_ICC0_POS)) /**< PCLKDIS1_ICC0 Mask */ -#define MXC_F_GCR_PCLKDIS1_MSRADC_POS 25 /**< PCLKDIS1_MSRADC Position */ -#define MXC_F_GCR_PCLKDIS1_MSRADC ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_MSRADC_POS)) /**< PCLKDIS1_MSRADC Mask */ +#define MXC_F_GCR_PCLKDIS1_AES_POS 15 /**< PCLKDIS1_AES Position */ +#define MXC_F_GCR_PCLKDIS1_AES ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_AES_POS)) /**< PCLKDIS1_AES Mask */ -#define MXC_F_GCR_PCLKDIS1_SC0_POS 26 /**< PCLKDIS1_SC0 Position */ -#define MXC_F_GCR_PCLKDIS1_SC0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_SC0_POS)) /**< PCLKDIS1_SC0 Mask */ +#define MXC_F_GCR_PCLKDIS1_I2C2_POS 21 /**< PCLKDIS1_I2C2 Position */ +#define MXC_F_GCR_PCLKDIS1_I2C2 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_I2C2_POS)) /**< PCLKDIS1_I2C2 Mask */ -#define MXC_F_GCR_PCLKDIS1_SC1_POS 27 /**< PCLKDIS1_SC1 Position */ -#define MXC_F_GCR_PCLKDIS1_SC1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_SC1_POS)) /**< PCLKDIS1_SC1 Mask */ +#define MXC_F_GCR_PCLKDIS1_I2S_POS 23 /**< PCLKDIS1_I2S Position */ +#define MXC_F_GCR_PCLKDIS1_I2S ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_I2S_POS)) /**< PCLKDIS1_I2S Mask */ -#define MXC_F_GCR_PCLKDIS1_CPU1_POS 31 /**< PCLKDIS1_CPU1 Position */ -#define MXC_F_GCR_PCLKDIS1_CPU1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_CPU1_POS)) /**< PCLKDIS1_CPU1 Mask */ +#define MXC_F_GCR_PCLKDIS1_QDEC_POS 25 /**< PCLKDIS1_QDEC Position */ +#define MXC_F_GCR_PCLKDIS1_QDEC ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_QDEC_POS)) /**< PCLKDIS1_QDEC Mask */ /**@} end of group GCR_PCLKDIS1_Register */ @@ -758,27 +622,114 @@ typedef struct { #define MXC_F_GCR_SYSIE_ICEUNLOCK_POS 0 /**< SYSIE_ICEUNLOCK Position */ #define MXC_F_GCR_SYSIE_ICEUNLOCK ((uint32_t)(0x1UL << MXC_F_GCR_SYSIE_ICEUNLOCK_POS)) /**< SYSIE_ICEUNLOCK Mask */ -#define MXC_F_GCR_SYSIE_CIE_POS 1 /**< SYSIE_CIE Position */ -#define MXC_F_GCR_SYSIE_CIE ((uint32_t)(0x1UL << MXC_F_GCR_SYSIE_CIE_POS)) /**< SYSIE_CIE Mask */ +/**@} end of group GCR_SYSIE_Register */ -#define MXC_F_GCR_SYSIE_SCMF_POS 5 /**< SYSIE_SCMF Position */ -#define MXC_F_GCR_SYSIE_SCMF ((uint32_t)(0x1UL << MXC_F_GCR_SYSIE_SCMF_POS)) /**< SYSIE_SCMF Mask */ +/** + * @ingroup gcr_registers + * @defgroup GCR_ECCERR GCR_ECCERR + * @brief ECC Error Register + * @{ + */ +#define MXC_F_GCR_ECCERR_RAM0_1_POS 0 /**< ECCERR_RAM0_1 Position */ +#define MXC_F_GCR_ECCERR_RAM0_1 ((uint32_t)(0x1UL << MXC_F_GCR_ECCERR_RAM0_1_POS)) /**< ECCERR_RAM0_1 Mask */ -/**@} end of group GCR_SYSIE_Register */ +#define MXC_F_GCR_ECCERR_RAM2_POS 1 /**< ECCERR_RAM2 Position */ +#define MXC_F_GCR_ECCERR_RAM2 ((uint32_t)(0x1UL << MXC_F_GCR_ECCERR_RAM2_POS)) /**< ECCERR_RAM2 Mask */ + +#define MXC_F_GCR_ECCERR_RAM3_POS 2 /**< ECCERR_RAM3 Position */ +#define MXC_F_GCR_ECCERR_RAM3 ((uint32_t)(0x1UL << MXC_F_GCR_ECCERR_RAM3_POS)) /**< ECCERR_RAM3 Mask */ + +#define MXC_F_GCR_ECCERR_ICC0_POS 3 /**< ECCERR_ICC0 Position */ +#define MXC_F_GCR_ECCERR_ICC0 ((uint32_t)(0x1UL << MXC_F_GCR_ECCERR_ICC0_POS)) /**< ECCERR_ICC0 Mask */ + +#define MXC_F_GCR_ECCERR_FLASH0_POS 4 /**< ECCERR_FLASH0 Position */ +#define MXC_F_GCR_ECCERR_FLASH0 ((uint32_t)(0x1UL << MXC_F_GCR_ECCERR_FLASH0_POS)) /**< ECCERR_FLASH0 Mask */ + +#define MXC_F_GCR_ECCERR_FLASH1_POS 5 /**< ECCERR_FLASH1 Position */ +#define MXC_F_GCR_ECCERR_FLASH1 ((uint32_t)(0x1UL << MXC_F_GCR_ECCERR_FLASH1_POS)) /**< ECCERR_FLASH1 Mask */ + +/**@} end of group GCR_ECCERR_Register */ /** * @ingroup gcr_registers - * @defgroup GCR_IPOCNT GCR_IPOCNT - * @brief IPO Warmup Count Register. + * @defgroup GCR_ECCCED GCR_ECCCED + * @brief ECC Correctable Error Detect Register * @{ */ -#define MXC_F_GCR_IPOCNT_WMUPCNT_POS 0 /**< IPOCNT_WMUPCNT Position */ -#define MXC_F_GCR_IPOCNT_WMUPCNT ((uint32_t)(0x3FFUL << MXC_F_GCR_IPOCNT_WMUPCNT_POS)) /**< IPOCNT_WMUPCNT Mask */ +#define MXC_F_GCR_ECCCED_RAM0_1_POS 0 /**< ECCCED_RAM0_1 Position */ +#define MXC_F_GCR_ECCCED_RAM0_1 ((uint32_t)(0x1UL << MXC_F_GCR_ECCCED_RAM0_1_POS)) /**< ECCCED_RAM0_1 Mask */ + +#define MXC_F_GCR_ECCCED_RAM2_POS 1 /**< ECCCED_RAM2 Position */ +#define MXC_F_GCR_ECCCED_RAM2 ((uint32_t)(0x1UL << MXC_F_GCR_ECCCED_RAM2_POS)) /**< ECCCED_RAM2 Mask */ + +#define MXC_F_GCR_ECCCED_RAM3_POS 2 /**< ECCCED_RAM3 Position */ +#define MXC_F_GCR_ECCCED_RAM3 ((uint32_t)(0x1UL << MXC_F_GCR_ECCCED_RAM3_POS)) /**< ECCCED_RAM3 Mask */ + +#define MXC_F_GCR_ECCCED_ICC0_POS 3 /**< ECCCED_ICC0 Position */ +#define MXC_F_GCR_ECCCED_ICC0 ((uint32_t)(0x1UL << MXC_F_GCR_ECCCED_ICC0_POS)) /**< ECCCED_ICC0 Mask */ + +#define MXC_F_GCR_ECCCED_FLASH0_POS 4 /**< ECCCED_FLASH0 Position */ +#define MXC_F_GCR_ECCCED_FLASH0 ((uint32_t)(0x1UL << MXC_F_GCR_ECCCED_FLASH0_POS)) /**< ECCCED_FLASH0 Mask */ + +#define MXC_F_GCR_ECCCED_FLASH1_POS 5 /**< ECCCED_FLASH1 Position */ +#define MXC_F_GCR_ECCCED_FLASH1 ((uint32_t)(0x1UL << MXC_F_GCR_ECCCED_FLASH1_POS)) /**< ECCCED_FLASH1 Mask */ + +/**@} end of group GCR_ECCCED_Register */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_ECCIE GCR_ECCIE + * @brief ECC IRQ Enable Register + * @{ + */ +#define MXC_F_GCR_ECCIE_RAM0_1_POS 0 /**< ECCIE_RAM0_1 Position */ +#define MXC_F_GCR_ECCIE_RAM0_1 ((uint32_t)(0x1UL << MXC_F_GCR_ECCIE_RAM0_1_POS)) /**< ECCIE_RAM0_1 Mask */ + +#define MXC_F_GCR_ECCIE_RAM2_POS 1 /**< ECCIE_RAM2 Position */ +#define MXC_F_GCR_ECCIE_RAM2 ((uint32_t)(0x1UL << MXC_F_GCR_ECCIE_RAM2_POS)) /**< ECCIE_RAM2 Mask */ + +#define MXC_F_GCR_ECCIE_RAM3_POS 2 /**< ECCIE_RAM3 Position */ +#define MXC_F_GCR_ECCIE_RAM3 ((uint32_t)(0x1UL << MXC_F_GCR_ECCIE_RAM3_POS)) /**< ECCIE_RAM3 Mask */ + +#define MXC_F_GCR_ECCIE_ICC0_POS 3 /**< ECCIE_ICC0 Position */ +#define MXC_F_GCR_ECCIE_ICC0 ((uint32_t)(0x1UL << MXC_F_GCR_ECCIE_ICC0_POS)) /**< ECCIE_ICC0 Mask */ + +#define MXC_F_GCR_ECCIE_FLASH0_POS 4 /**< ECCIE_FLASH0 Position */ +#define MXC_F_GCR_ECCIE_FLASH0 ((uint32_t)(0x1UL << MXC_F_GCR_ECCIE_FLASH0_POS)) /**< ECCIE_FLASH0 Mask */ + +#define MXC_F_GCR_ECCIE_FLASH1_POS 5 /**< ECCIE_FLASH1 Position */ +#define MXC_F_GCR_ECCIE_FLASH1 ((uint32_t)(0x1UL << MXC_F_GCR_ECCIE_FLASH1_POS)) /**< ECCIE_FLASH1 Mask */ + +/**@} end of group GCR_ECCIE_Register */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_ECCADDR GCR_ECCADDR + * @brief ECC Error Address Register + * @{ + */ +#define MXC_F_GCR_ECCADDR_DATARAMADDR_POS 0 /**< ECCADDR_DATARAMADDR Position */ +#define MXC_F_GCR_ECCADDR_DATARAMADDR ((uint32_t)(0x3FFFUL << MXC_F_GCR_ECCADDR_DATARAMADDR_POS)) /**< ECCADDR_DATARAMADDR Mask */ + +#define MXC_F_GCR_ECCADDR_DATARAMBANK_POS 14 /**< ECCADDR_DATARAMBANK Position */ +#define MXC_F_GCR_ECCADDR_DATARAMBANK ((uint32_t)(0x1UL << MXC_F_GCR_ECCADDR_DATARAMBANK_POS)) /**< ECCADDR_DATARAMBANK Mask */ + +#define MXC_F_GCR_ECCADDR_DATARAMERR_POS 15 /**< ECCADDR_DATARAMERR Position */ +#define MXC_F_GCR_ECCADDR_DATARAMERR ((uint32_t)(0x1UL << MXC_F_GCR_ECCADDR_DATARAMERR_POS)) /**< ECCADDR_DATARAMERR Mask */ + +#define MXC_F_GCR_ECCADDR_TAGRAMADDR_POS 16 /**< ECCADDR_TAGRAMADDR Position */ +#define MXC_F_GCR_ECCADDR_TAGRAMADDR ((uint32_t)(0x3FFFUL << MXC_F_GCR_ECCADDR_TAGRAMADDR_POS)) /**< ECCADDR_TAGRAMADDR Mask */ + +#define MXC_F_GCR_ECCADDR_TAGRAMBANK_POS 30 /**< ECCADDR_TAGRAMBANK Position */ +#define MXC_F_GCR_ECCADDR_TAGRAMBANK ((uint32_t)(0x1UL << MXC_F_GCR_ECCADDR_TAGRAMBANK_POS)) /**< ECCADDR_TAGRAMBANK Mask */ + +#define MXC_F_GCR_ECCADDR_TAGRAMERR_POS 31 /**< ECCADDR_TAGRAMERR Position */ +#define MXC_F_GCR_ECCADDR_TAGRAMERR ((uint32_t)(0x1UL << MXC_F_GCR_ECCADDR_TAGRAMERR_POS)) /**< ECCADDR_TAGRAMERR Mask */ -/**@} end of group GCR_IPOCNT_Register */ +/**@} end of group GCR_ECCADDR_Register */ #ifdef __cplusplus } #endif -#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_GCR_REGS_H_ +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32672_INCLUDE_GCR_REGS_H_ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32572/Include/gpio_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32572/Include/gpio_regs.h index 433cf8d5c00..8512980e956 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32572/Include/gpio_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32572/Include/gpio_regs.h @@ -25,8 +25,8 @@ * ******************************************************************************/ -#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_GPIO_REGS_H_ -#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_GPIO_REGS_H_ +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32672_INCLUDE_GPIO_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32672_INCLUDE_GPIO_REGS_H_ /* **** Includes **** */ #include @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile @@ -111,7 +115,7 @@ typedef struct { __IO uint32_t srsel; /**< \b 0xAC: GPIO SRSEL Register */ __IO uint32_t ds0; /**< \b 0xB0: GPIO DS0 Register */ __IO uint32_t ds1; /**< \b 0xB4: GPIO DS1 Register */ - __IO uint32_t pssel; /**< \b 0xB8: GPIO PSSEL Register */ + __IO uint32_t ps; /**< \b 0xB8: GPIO PS Register */ __R uint32_t rsv_0xbc; __IO uint32_t vssel; /**< \b 0xC0: GPIO VSSEL Register */ } mxc_gpio_regs_t; @@ -157,7 +161,7 @@ typedef struct { #define MXC_R_GPIO_SRSEL ((uint32_t)0x000000ACUL) /**< Offset from GPIO Base Address: 0x00AC */ #define MXC_R_GPIO_DS0 ((uint32_t)0x000000B0UL) /**< Offset from GPIO Base Address: 0x00B0 */ #define MXC_R_GPIO_DS1 ((uint32_t)0x000000B4UL) /**< Offset from GPIO Base Address: 0x00B4 */ -#define MXC_R_GPIO_PSSEL ((uint32_t)0x000000B8UL) /**< Offset from GPIO Base Address: 0x00B8 */ +#define MXC_R_GPIO_PS ((uint32_t)0x000000B8UL) /**< Offset from GPIO Base Address: 0x00B8 */ #define MXC_R_GPIO_VSSEL ((uint32_t)0x000000C0UL) /**< Offset from GPIO Base Address: 0x00C0 */ /**@} end of group gpio_registers */ @@ -168,12 +172,12 @@ typedef struct { * GPIO pin on the associated port. * @{ */ -#define MXC_F_GPIO_EN0_ALL_POS 0 /**< EN0_ALL Position */ -#define MXC_F_GPIO_EN0_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN0_ALL_POS)) /**< EN0_ALL Mask */ -#define MXC_V_GPIO_EN0_ALL_ALTERNATE ((uint32_t)0x0UL) /**< EN0_ALL_ALTERNATE Value */ -#define MXC_S_GPIO_EN0_ALL_ALTERNATE (MXC_V_GPIO_EN0_ALL_ALTERNATE << MXC_F_GPIO_EN0_ALL_POS) /**< EN0_ALL_ALTERNATE Setting */ -#define MXC_V_GPIO_EN0_ALL_GPIO ((uint32_t)0x1UL) /**< EN0_ALL_GPIO Value */ -#define MXC_S_GPIO_EN0_ALL_GPIO (MXC_V_GPIO_EN0_ALL_GPIO << MXC_F_GPIO_EN0_ALL_POS) /**< EN0_ALL_GPIO Setting */ +#define MXC_F_GPIO_EN0_GPIO_EN_POS 0 /**< EN0_GPIO_EN Position */ +#define MXC_F_GPIO_EN0_GPIO_EN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN0_GPIO_EN_POS)) /**< EN0_GPIO_EN Mask */ +#define MXC_V_GPIO_EN0_GPIO_EN_ALTERNATE ((uint32_t)0x0UL) /**< EN0_GPIO_EN_ALTERNATE Value */ +#define MXC_S_GPIO_EN0_GPIO_EN_ALTERNATE (MXC_V_GPIO_EN0_GPIO_EN_ALTERNATE << MXC_F_GPIO_EN0_GPIO_EN_POS) /**< EN0_GPIO_EN_ALTERNATE Setting */ +#define MXC_V_GPIO_EN0_GPIO_EN_GPIO ((uint32_t)0x1UL) /**< EN0_GPIO_EN_GPIO Value */ +#define MXC_S_GPIO_EN0_GPIO_EN_GPIO (MXC_V_GPIO_EN0_GPIO_EN_GPIO << MXC_F_GPIO_EN0_GPIO_EN_POS) /**< EN0_GPIO_EN_GPIO Setting */ /**@} end of group GPIO_EN0_Register */ @@ -210,12 +214,12 @@ typedef struct { * GPIO pin in the associated port. * @{ */ -#define MXC_F_GPIO_OUTEN_ALL_POS 0 /**< OUTEN_ALL Position */ -#define MXC_F_GPIO_OUTEN_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUTEN_ALL_POS)) /**< OUTEN_ALL Mask */ -#define MXC_V_GPIO_OUTEN_ALL_DIS ((uint32_t)0x0UL) /**< OUTEN_ALL_DIS Value */ -#define MXC_S_GPIO_OUTEN_ALL_DIS (MXC_V_GPIO_OUTEN_ALL_DIS << MXC_F_GPIO_OUTEN_ALL_POS) /**< OUTEN_ALL_DIS Setting */ -#define MXC_V_GPIO_OUTEN_ALL_EN ((uint32_t)0x1UL) /**< OUTEN_ALL_EN Value */ -#define MXC_S_GPIO_OUTEN_ALL_EN (MXC_V_GPIO_OUTEN_ALL_EN << MXC_F_GPIO_OUTEN_ALL_POS) /**< OUTEN_ALL_EN Setting */ +#define MXC_F_GPIO_OUTEN_EN_POS 0 /**< OUTEN_EN Position */ +#define MXC_F_GPIO_OUTEN_EN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUTEN_EN_POS)) /**< OUTEN_EN Mask */ +#define MXC_V_GPIO_OUTEN_EN_DIS ((uint32_t)0x0UL) /**< OUTEN_EN_DIS Value */ +#define MXC_S_GPIO_OUTEN_EN_DIS (MXC_V_GPIO_OUTEN_EN_DIS << MXC_F_GPIO_OUTEN_EN_POS) /**< OUTEN_EN_DIS Setting */ +#define MXC_V_GPIO_OUTEN_EN_EN ((uint32_t)0x1UL) /**< OUTEN_EN_EN Value */ +#define MXC_S_GPIO_OUTEN_EN_EN (MXC_V_GPIO_OUTEN_EN_EN << MXC_F_GPIO_OUTEN_EN_POS) /**< OUTEN_EN_EN Setting */ /**@} end of group GPIO_OUTEN_Register */ @@ -253,12 +257,12 @@ typedef struct { * GPIO_OUT_SET and GPIO_OUT_CLR registers. * @{ */ -#define MXC_F_GPIO_OUT_ALL_POS 0 /**< OUT_ALL Position */ -#define MXC_F_GPIO_OUT_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_ALL_POS)) /**< OUT_ALL Mask */ -#define MXC_V_GPIO_OUT_ALL_LOW ((uint32_t)0x0UL) /**< OUT_ALL_LOW Value */ -#define MXC_S_GPIO_OUT_ALL_LOW (MXC_V_GPIO_OUT_ALL_LOW << MXC_F_GPIO_OUT_ALL_POS) /**< OUT_ALL_LOW Setting */ -#define MXC_V_GPIO_OUT_ALL_HIGH ((uint32_t)0x1UL) /**< OUT_ALL_HIGH Value */ -#define MXC_S_GPIO_OUT_ALL_HIGH (MXC_V_GPIO_OUT_ALL_HIGH << MXC_F_GPIO_OUT_ALL_POS) /**< OUT_ALL_HIGH Setting */ +#define MXC_F_GPIO_OUT_GPIO_OUT_POS 0 /**< OUT_GPIO_OUT Position */ +#define MXC_F_GPIO_OUT_GPIO_OUT ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_GPIO_OUT_POS)) /**< OUT_GPIO_OUT Mask */ +#define MXC_V_GPIO_OUT_GPIO_OUT_LOW ((uint32_t)0x0UL) /**< OUT_GPIO_OUT_LOW Value */ +#define MXC_S_GPIO_OUT_GPIO_OUT_LOW (MXC_V_GPIO_OUT_GPIO_OUT_LOW << MXC_F_GPIO_OUT_GPIO_OUT_POS) /**< OUT_GPIO_OUT_LOW Setting */ +#define MXC_V_GPIO_OUT_GPIO_OUT_HIGH ((uint32_t)0x1UL) /**< OUT_GPIO_OUT_HIGH Value */ +#define MXC_S_GPIO_OUT_GPIO_OUT_HIGH (MXC_V_GPIO_OUT_GPIO_OUT_HIGH << MXC_F_GPIO_OUT_GPIO_OUT_POS) /**< OUT_GPIO_OUT_HIGH Setting */ /**@} end of group GPIO_OUT_Register */ @@ -270,12 +274,12 @@ typedef struct { * register. * @{ */ -#define MXC_F_GPIO_OUT_SET_ALL_POS 0 /**< OUT_SET_ALL Position */ -#define MXC_F_GPIO_OUT_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_SET_ALL_POS)) /**< OUT_SET_ALL Mask */ -#define MXC_V_GPIO_OUT_SET_ALL_NO ((uint32_t)0x0UL) /**< OUT_SET_ALL_NO Value */ -#define MXC_S_GPIO_OUT_SET_ALL_NO (MXC_V_GPIO_OUT_SET_ALL_NO << MXC_F_GPIO_OUT_SET_ALL_POS) /**< OUT_SET_ALL_NO Setting */ -#define MXC_V_GPIO_OUT_SET_ALL_SET ((uint32_t)0x1UL) /**< OUT_SET_ALL_SET Value */ -#define MXC_S_GPIO_OUT_SET_ALL_SET (MXC_V_GPIO_OUT_SET_ALL_SET << MXC_F_GPIO_OUT_SET_ALL_POS) /**< OUT_SET_ALL_SET Setting */ +#define MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS 0 /**< OUT_SET_GPIO_OUT_SET Position */ +#define MXC_F_GPIO_OUT_SET_GPIO_OUT_SET ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS)) /**< OUT_SET_GPIO_OUT_SET Mask */ +#define MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_NO ((uint32_t)0x0UL) /**< OUT_SET_GPIO_OUT_SET_NO Value */ +#define MXC_S_GPIO_OUT_SET_GPIO_OUT_SET_NO (MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_NO << MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS) /**< OUT_SET_GPIO_OUT_SET_NO Setting */ +#define MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_SET ((uint32_t)0x1UL) /**< OUT_SET_GPIO_OUT_SET_SET Value */ +#define MXC_S_GPIO_OUT_SET_GPIO_OUT_SET_SET (MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_SET << MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS) /**< OUT_SET_GPIO_OUT_SET_SET Setting */ /**@} end of group GPIO_OUT_SET_Register */ @@ -287,8 +291,8 @@ typedef struct { * that register. * @{ */ -#define MXC_F_GPIO_OUT_CLR_ALL_POS 0 /**< OUT_CLR_ALL Position */ -#define MXC_F_GPIO_OUT_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_CLR_ALL_POS)) /**< OUT_CLR_ALL Mask */ +#define MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR_POS 0 /**< OUT_CLR_GPIO_OUT_CLR Position */ +#define MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR_POS)) /**< OUT_CLR_GPIO_OUT_CLR Mask */ /**@} end of group GPIO_OUT_CLR_Register */ @@ -299,8 +303,8 @@ typedef struct { * GPIO pins on this port. * @{ */ -#define MXC_F_GPIO_IN_ALL_POS 0 /**< IN_ALL Position */ -#define MXC_F_GPIO_IN_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_IN_ALL_POS)) /**< IN_ALL Mask */ +#define MXC_F_GPIO_IN_GPIO_IN_POS 0 /**< IN_GPIO_IN Position */ +#define MXC_F_GPIO_IN_GPIO_IN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_IN_GPIO_IN_POS)) /**< IN_GPIO_IN Mask */ /**@} end of group GPIO_IN_Register */ @@ -311,12 +315,12 @@ typedef struct { * mode setting for the associated GPIO pin on this port. * @{ */ -#define MXC_F_GPIO_INTMODE_ALL_POS 0 /**< INTMODE_ALL Position */ -#define MXC_F_GPIO_INTMODE_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INTMODE_ALL_POS)) /**< INTMODE_ALL Mask */ -#define MXC_V_GPIO_INTMODE_ALL_LEVEL ((uint32_t)0x0UL) /**< INTMODE_ALL_LEVEL Value */ -#define MXC_S_GPIO_INTMODE_ALL_LEVEL (MXC_V_GPIO_INTMODE_ALL_LEVEL << MXC_F_GPIO_INTMODE_ALL_POS) /**< INTMODE_ALL_LEVEL Setting */ -#define MXC_V_GPIO_INTMODE_ALL_EDGE ((uint32_t)0x1UL) /**< INTMODE_ALL_EDGE Value */ -#define MXC_S_GPIO_INTMODE_ALL_EDGE (MXC_V_GPIO_INTMODE_ALL_EDGE << MXC_F_GPIO_INTMODE_ALL_POS) /**< INTMODE_ALL_EDGE Setting */ +#define MXC_F_GPIO_INTMODE_GPIO_INTMODE_POS 0 /**< INTMODE_GPIO_INTMODE Position */ +#define MXC_F_GPIO_INTMODE_GPIO_INTMODE ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INTMODE_GPIO_INTMODE_POS)) /**< INTMODE_GPIO_INTMODE Mask */ +#define MXC_V_GPIO_INTMODE_GPIO_INTMODE_LEVEL ((uint32_t)0x0UL) /**< INTMODE_GPIO_INTMODE_LEVEL Value */ +#define MXC_S_GPIO_INTMODE_GPIO_INTMODE_LEVEL (MXC_V_GPIO_INTMODE_GPIO_INTMODE_LEVEL << MXC_F_GPIO_INTMODE_GPIO_INTMODE_POS) /**< INTMODE_GPIO_INTMODE_LEVEL Setting */ +#define MXC_V_GPIO_INTMODE_GPIO_INTMODE_EDGE ((uint32_t)0x1UL) /**< INTMODE_GPIO_INTMODE_EDGE Value */ +#define MXC_S_GPIO_INTMODE_GPIO_INTMODE_EDGE (MXC_V_GPIO_INTMODE_GPIO_INTMODE_EDGE << MXC_F_GPIO_INTMODE_GPIO_INTMODE_POS) /**< INTMODE_GPIO_INTMODE_EDGE Setting */ /**@} end of group GPIO_INTMODE_Register */ @@ -327,12 +331,12 @@ typedef struct { * interrupt polarity setting for one GPIO pin in the associated port. * @{ */ -#define MXC_F_GPIO_INTPOL_ALL_POS 0 /**< INTPOL_ALL Position */ -#define MXC_F_GPIO_INTPOL_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INTPOL_ALL_POS)) /**< INTPOL_ALL Mask */ -#define MXC_V_GPIO_INTPOL_ALL_FALLING ((uint32_t)0x0UL) /**< INTPOL_ALL_FALLING Value */ -#define MXC_S_GPIO_INTPOL_ALL_FALLING (MXC_V_GPIO_INTPOL_ALL_FALLING << MXC_F_GPIO_INTPOL_ALL_POS) /**< INTPOL_ALL_FALLING Setting */ -#define MXC_V_GPIO_INTPOL_ALL_RISING ((uint32_t)0x1UL) /**< INTPOL_ALL_RISING Value */ -#define MXC_S_GPIO_INTPOL_ALL_RISING (MXC_V_GPIO_INTPOL_ALL_RISING << MXC_F_GPIO_INTPOL_ALL_POS) /**< INTPOL_ALL_RISING Setting */ +#define MXC_F_GPIO_INTPOL_GPIO_INTPOL_POS 0 /**< INTPOL_GPIO_INTPOL Position */ +#define MXC_F_GPIO_INTPOL_GPIO_INTPOL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INTPOL_GPIO_INTPOL_POS)) /**< INTPOL_GPIO_INTPOL Mask */ +#define MXC_V_GPIO_INTPOL_GPIO_INTPOL_FALLING ((uint32_t)0x0UL) /**< INTPOL_GPIO_INTPOL_FALLING Value */ +#define MXC_S_GPIO_INTPOL_GPIO_INTPOL_FALLING (MXC_V_GPIO_INTPOL_GPIO_INTPOL_FALLING << MXC_F_GPIO_INTPOL_GPIO_INTPOL_POS) /**< INTPOL_GPIO_INTPOL_FALLING Setting */ +#define MXC_V_GPIO_INTPOL_GPIO_INTPOL_RISING ((uint32_t)0x1UL) /**< INTPOL_GPIO_INTPOL_RISING Value */ +#define MXC_S_GPIO_INTPOL_GPIO_INTPOL_RISING (MXC_V_GPIO_INTPOL_GPIO_INTPOL_RISING << MXC_F_GPIO_INTPOL_GPIO_INTPOL_POS) /**< INTPOL_GPIO_INTPOL_RISING Setting */ /**@} end of group GPIO_INTPOL_Register */ @@ -343,12 +347,12 @@ typedef struct { * interrupt enable for the associated pin on the GPIO port. * @{ */ -#define MXC_F_GPIO_INTEN_ALL_POS 0 /**< INTEN_ALL Position */ -#define MXC_F_GPIO_INTEN_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INTEN_ALL_POS)) /**< INTEN_ALL Mask */ -#define MXC_V_GPIO_INTEN_ALL_DIS ((uint32_t)0x0UL) /**< INTEN_ALL_DIS Value */ -#define MXC_S_GPIO_INTEN_ALL_DIS (MXC_V_GPIO_INTEN_ALL_DIS << MXC_F_GPIO_INTEN_ALL_POS) /**< INTEN_ALL_DIS Setting */ -#define MXC_V_GPIO_INTEN_ALL_EN ((uint32_t)0x1UL) /**< INTEN_ALL_EN Value */ -#define MXC_S_GPIO_INTEN_ALL_EN (MXC_V_GPIO_INTEN_ALL_EN << MXC_F_GPIO_INTEN_ALL_POS) /**< INTEN_ALL_EN Setting */ +#define MXC_F_GPIO_INTEN_GPIO_INTEN_POS 0 /**< INTEN_GPIO_INTEN Position */ +#define MXC_F_GPIO_INTEN_GPIO_INTEN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INTEN_GPIO_INTEN_POS)) /**< INTEN_GPIO_INTEN Mask */ +#define MXC_V_GPIO_INTEN_GPIO_INTEN_DIS ((uint32_t)0x0UL) /**< INTEN_GPIO_INTEN_DIS Value */ +#define MXC_S_GPIO_INTEN_GPIO_INTEN_DIS (MXC_V_GPIO_INTEN_GPIO_INTEN_DIS << MXC_F_GPIO_INTEN_GPIO_INTEN_POS) /**< INTEN_GPIO_INTEN_DIS Setting */ +#define MXC_V_GPIO_INTEN_GPIO_INTEN_EN ((uint32_t)0x1UL) /**< INTEN_GPIO_INTEN_EN Value */ +#define MXC_S_GPIO_INTEN_GPIO_INTEN_EN (MXC_V_GPIO_INTEN_GPIO_INTEN_EN << MXC_F_GPIO_INTEN_GPIO_INTEN_POS) /**< INTEN_GPIO_INTEN_EN Setting */ /**@} end of group GPIO_INTEN_Register */ @@ -360,12 +364,12 @@ typedef struct { * in that register. * @{ */ -#define MXC_F_GPIO_INTEN_SET_ALL_POS 0 /**< INTEN_SET_ALL Position */ -#define MXC_F_GPIO_INTEN_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INTEN_SET_ALL_POS)) /**< INTEN_SET_ALL Mask */ -#define MXC_V_GPIO_INTEN_SET_ALL_NO ((uint32_t)0x0UL) /**< INTEN_SET_ALL_NO Value */ -#define MXC_S_GPIO_INTEN_SET_ALL_NO (MXC_V_GPIO_INTEN_SET_ALL_NO << MXC_F_GPIO_INTEN_SET_ALL_POS) /**< INTEN_SET_ALL_NO Setting */ -#define MXC_V_GPIO_INTEN_SET_ALL_SET ((uint32_t)0x1UL) /**< INTEN_SET_ALL_SET Value */ -#define MXC_S_GPIO_INTEN_SET_ALL_SET (MXC_V_GPIO_INTEN_SET_ALL_SET << MXC_F_GPIO_INTEN_SET_ALL_POS) /**< INTEN_SET_ALL_SET Setting */ +#define MXC_F_GPIO_INTEN_SET_GPIO_INTEN_SET_POS 0 /**< INTEN_SET_GPIO_INTEN_SET Position */ +#define MXC_F_GPIO_INTEN_SET_GPIO_INTEN_SET ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INTEN_SET_GPIO_INTEN_SET_POS)) /**< INTEN_SET_GPIO_INTEN_SET Mask */ +#define MXC_V_GPIO_INTEN_SET_GPIO_INTEN_SET_NO ((uint32_t)0x0UL) /**< INTEN_SET_GPIO_INTEN_SET_NO Value */ +#define MXC_S_GPIO_INTEN_SET_GPIO_INTEN_SET_NO (MXC_V_GPIO_INTEN_SET_GPIO_INTEN_SET_NO << MXC_F_GPIO_INTEN_SET_GPIO_INTEN_SET_POS) /**< INTEN_SET_GPIO_INTEN_SET_NO Setting */ +#define MXC_V_GPIO_INTEN_SET_GPIO_INTEN_SET_SET ((uint32_t)0x1UL) /**< INTEN_SET_GPIO_INTEN_SET_SET Value */ +#define MXC_S_GPIO_INTEN_SET_GPIO_INTEN_SET_SET (MXC_V_GPIO_INTEN_SET_GPIO_INTEN_SET_SET << MXC_F_GPIO_INTEN_SET_GPIO_INTEN_SET_POS) /**< INTEN_SET_GPIO_INTEN_SET_SET Setting */ /**@} end of group GPIO_INTEN_SET_Register */ @@ -377,12 +381,12 @@ typedef struct { * other bits in that register. * @{ */ -#define MXC_F_GPIO_INTEN_CLR_ALL_POS 0 /**< INTEN_CLR_ALL Position */ -#define MXC_F_GPIO_INTEN_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INTEN_CLR_ALL_POS)) /**< INTEN_CLR_ALL Mask */ -#define MXC_V_GPIO_INTEN_CLR_ALL_NO ((uint32_t)0x0UL) /**< INTEN_CLR_ALL_NO Value */ -#define MXC_S_GPIO_INTEN_CLR_ALL_NO (MXC_V_GPIO_INTEN_CLR_ALL_NO << MXC_F_GPIO_INTEN_CLR_ALL_POS) /**< INTEN_CLR_ALL_NO Setting */ -#define MXC_V_GPIO_INTEN_CLR_ALL_CLEAR ((uint32_t)0x1UL) /**< INTEN_CLR_ALL_CLEAR Value */ -#define MXC_S_GPIO_INTEN_CLR_ALL_CLEAR (MXC_V_GPIO_INTEN_CLR_ALL_CLEAR << MXC_F_GPIO_INTEN_CLR_ALL_POS) /**< INTEN_CLR_ALL_CLEAR Setting */ +#define MXC_F_GPIO_INTEN_CLR_GPIO_INTEN_CLR_POS 0 /**< INTEN_CLR_GPIO_INTEN_CLR Position */ +#define MXC_F_GPIO_INTEN_CLR_GPIO_INTEN_CLR ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INTEN_CLR_GPIO_INTEN_CLR_POS)) /**< INTEN_CLR_GPIO_INTEN_CLR Mask */ +#define MXC_V_GPIO_INTEN_CLR_GPIO_INTEN_CLR_NO ((uint32_t)0x0UL) /**< INTEN_CLR_GPIO_INTEN_CLR_NO Value */ +#define MXC_S_GPIO_INTEN_CLR_GPIO_INTEN_CLR_NO (MXC_V_GPIO_INTEN_CLR_GPIO_INTEN_CLR_NO << MXC_F_GPIO_INTEN_CLR_GPIO_INTEN_CLR_POS) /**< INTEN_CLR_GPIO_INTEN_CLR_NO Setting */ +#define MXC_V_GPIO_INTEN_CLR_GPIO_INTEN_CLR_CLEAR ((uint32_t)0x1UL) /**< INTEN_CLR_GPIO_INTEN_CLR_CLEAR Value */ +#define MXC_S_GPIO_INTEN_CLR_GPIO_INTEN_CLR_CLEAR (MXC_V_GPIO_INTEN_CLR_GPIO_INTEN_CLR_CLEAR << MXC_F_GPIO_INTEN_CLR_GPIO_INTEN_CLR_POS) /**< INTEN_CLR_GPIO_INTEN_CLR_CLEAR Setting */ /**@} end of group GPIO_INTEN_CLR_Register */ @@ -393,12 +397,12 @@ typedef struct { * interrupt status for the associated GPIO pin in this port. * @{ */ -#define MXC_F_GPIO_INTFL_ALL_POS 0 /**< INTFL_ALL Position */ -#define MXC_F_GPIO_INTFL_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INTFL_ALL_POS)) /**< INTFL_ALL Mask */ -#define MXC_V_GPIO_INTFL_ALL_NO ((uint32_t)0x0UL) /**< INTFL_ALL_NO Value */ -#define MXC_S_GPIO_INTFL_ALL_NO (MXC_V_GPIO_INTFL_ALL_NO << MXC_F_GPIO_INTFL_ALL_POS) /**< INTFL_ALL_NO Setting */ -#define MXC_V_GPIO_INTFL_ALL_PENDING ((uint32_t)0x1UL) /**< INTFL_ALL_PENDING Value */ -#define MXC_S_GPIO_INTFL_ALL_PENDING (MXC_V_GPIO_INTFL_ALL_PENDING << MXC_F_GPIO_INTFL_ALL_POS) /**< INTFL_ALL_PENDING Setting */ +#define MXC_F_GPIO_INTFL_GPIO_INTFL_POS 0 /**< INTFL_GPIO_INTFL Position */ +#define MXC_F_GPIO_INTFL_GPIO_INTFL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INTFL_GPIO_INTFL_POS)) /**< INTFL_GPIO_INTFL Mask */ +#define MXC_V_GPIO_INTFL_GPIO_INTFL_NO ((uint32_t)0x0UL) /**< INTFL_GPIO_INTFL_NO Value */ +#define MXC_S_GPIO_INTFL_GPIO_INTFL_NO (MXC_V_GPIO_INTFL_GPIO_INTFL_NO << MXC_F_GPIO_INTFL_GPIO_INTFL_POS) /**< INTFL_GPIO_INTFL_NO Setting */ +#define MXC_V_GPIO_INTFL_GPIO_INTFL_PENDING ((uint32_t)0x1UL) /**< INTFL_GPIO_INTFL_PENDING Value */ +#define MXC_S_GPIO_INTFL_GPIO_INTFL_PENDING (MXC_V_GPIO_INTFL_GPIO_INTFL_PENDING << MXC_F_GPIO_INTFL_GPIO_INTFL_POS) /**< INTFL_GPIO_INTFL_PENDING Setting */ /**@} end of group GPIO_INTFL_Register */ @@ -422,12 +426,12 @@ typedef struct { * enable for the associated GPIO pin in this port. * @{ */ -#define MXC_F_GPIO_WKEN_ALL_POS 0 /**< WKEN_ALL Position */ -#define MXC_F_GPIO_WKEN_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_WKEN_ALL_POS)) /**< WKEN_ALL Mask */ -#define MXC_V_GPIO_WKEN_ALL_DIS ((uint32_t)0x0UL) /**< WKEN_ALL_DIS Value */ -#define MXC_S_GPIO_WKEN_ALL_DIS (MXC_V_GPIO_WKEN_ALL_DIS << MXC_F_GPIO_WKEN_ALL_POS) /**< WKEN_ALL_DIS Setting */ -#define MXC_V_GPIO_WKEN_ALL_EN ((uint32_t)0x1UL) /**< WKEN_ALL_EN Value */ -#define MXC_S_GPIO_WKEN_ALL_EN (MXC_V_GPIO_WKEN_ALL_EN << MXC_F_GPIO_WKEN_ALL_POS) /**< WKEN_ALL_EN Setting */ +#define MXC_F_GPIO_WKEN_GPIO_WKEN_POS 0 /**< WKEN_GPIO_WKEN Position */ +#define MXC_F_GPIO_WKEN_GPIO_WKEN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_WKEN_GPIO_WKEN_POS)) /**< WKEN_GPIO_WKEN Mask */ +#define MXC_V_GPIO_WKEN_GPIO_WKEN_DIS ((uint32_t)0x0UL) /**< WKEN_GPIO_WKEN_DIS Value */ +#define MXC_S_GPIO_WKEN_GPIO_WKEN_DIS (MXC_V_GPIO_WKEN_GPIO_WKEN_DIS << MXC_F_GPIO_WKEN_GPIO_WKEN_POS) /**< WKEN_GPIO_WKEN_DIS Setting */ +#define MXC_V_GPIO_WKEN_GPIO_WKEN_EN ((uint32_t)0x1UL) /**< WKEN_GPIO_WKEN_EN Value */ +#define MXC_S_GPIO_WKEN_GPIO_WKEN_EN (MXC_V_GPIO_WKEN_GPIO_WKEN_EN << MXC_F_GPIO_WKEN_GPIO_WKEN_POS) /**< WKEN_GPIO_WKEN_EN Setting */ /**@} end of group GPIO_WKEN_Register */ @@ -464,48 +468,48 @@ typedef struct { * edge mode for the associated GPIO pin in this port. * @{ */ -#define MXC_F_GPIO_DUALEDGE_ALL_POS 0 /**< DUALEDGE_ALL Position */ -#define MXC_F_GPIO_DUALEDGE_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_DUALEDGE_ALL_POS)) /**< DUALEDGE_ALL Mask */ -#define MXC_V_GPIO_DUALEDGE_ALL_NO ((uint32_t)0x0UL) /**< DUALEDGE_ALL_NO Value */ -#define MXC_S_GPIO_DUALEDGE_ALL_NO (MXC_V_GPIO_DUALEDGE_ALL_NO << MXC_F_GPIO_DUALEDGE_ALL_POS) /**< DUALEDGE_ALL_NO Setting */ -#define MXC_V_GPIO_DUALEDGE_ALL_EN ((uint32_t)0x1UL) /**< DUALEDGE_ALL_EN Value */ -#define MXC_S_GPIO_DUALEDGE_ALL_EN (MXC_V_GPIO_DUALEDGE_ALL_EN << MXC_F_GPIO_DUALEDGE_ALL_POS) /**< DUALEDGE_ALL_EN Setting */ +#define MXC_F_GPIO_DUALEDGE_GPIO_DUALEDGE_POS 0 /**< DUALEDGE_GPIO_DUALEDGE Position */ +#define MXC_F_GPIO_DUALEDGE_GPIO_DUALEDGE ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_DUALEDGE_GPIO_DUALEDGE_POS)) /**< DUALEDGE_GPIO_DUALEDGE Mask */ +#define MXC_V_GPIO_DUALEDGE_GPIO_DUALEDGE_NO ((uint32_t)0x0UL) /**< DUALEDGE_GPIO_DUALEDGE_NO Value */ +#define MXC_S_GPIO_DUALEDGE_GPIO_DUALEDGE_NO (MXC_V_GPIO_DUALEDGE_GPIO_DUALEDGE_NO << MXC_F_GPIO_DUALEDGE_GPIO_DUALEDGE_POS) /**< DUALEDGE_GPIO_DUALEDGE_NO Setting */ +#define MXC_V_GPIO_DUALEDGE_GPIO_DUALEDGE_EN ((uint32_t)0x1UL) /**< DUALEDGE_GPIO_DUALEDGE_EN Value */ +#define MXC_S_GPIO_DUALEDGE_GPIO_DUALEDGE_EN (MXC_V_GPIO_DUALEDGE_GPIO_DUALEDGE_EN << MXC_F_GPIO_DUALEDGE_GPIO_DUALEDGE_POS) /**< DUALEDGE_GPIO_DUALEDGE_EN Setting */ /**@} end of group GPIO_DUALEDGE_Register */ /** * @ingroup gpio_registers * @defgroup GPIO_PADCTRL0 GPIO_PADCTRL0 - * @brief GPIO Input Mode Config 0. Each bit in this register enables the weak pull-up for + * @brief GPIO Input Mode Config 1. Each bit in this register enables the weak pull-up for * the associated GPIO pin in this port. * @{ */ -#define MXC_F_GPIO_PADCTRL0_ALL_POS 0 /**< PADCTRL0_ALL Position */ -#define MXC_F_GPIO_PADCTRL0_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_PADCTRL0_ALL_POS)) /**< PADCTRL0_ALL Mask */ -#define MXC_V_GPIO_PADCTRL0_ALL_IMPEDANCE ((uint32_t)0x0UL) /**< PADCTRL0_ALL_IMPEDANCE Value */ -#define MXC_S_GPIO_PADCTRL0_ALL_IMPEDANCE (MXC_V_GPIO_PADCTRL0_ALL_IMPEDANCE << MXC_F_GPIO_PADCTRL0_ALL_POS) /**< PADCTRL0_ALL_IMPEDANCE Setting */ -#define MXC_V_GPIO_PADCTRL0_ALL_PU ((uint32_t)0x1UL) /**< PADCTRL0_ALL_PU Value */ -#define MXC_S_GPIO_PADCTRL0_ALL_PU (MXC_V_GPIO_PADCTRL0_ALL_PU << MXC_F_GPIO_PADCTRL0_ALL_POS) /**< PADCTRL0_ALL_PU Setting */ -#define MXC_V_GPIO_PADCTRL0_ALL_PD ((uint32_t)0x2UL) /**< PADCTRL0_ALL_PD Value */ -#define MXC_S_GPIO_PADCTRL0_ALL_PD (MXC_V_GPIO_PADCTRL0_ALL_PD << MXC_F_GPIO_PADCTRL0_ALL_POS) /**< PADCTRL0_ALL_PD Setting */ +#define MXC_F_GPIO_PADCTRL0_GPIO_PADCTRL0_POS 0 /**< PADCTRL0_GPIO_PADCTRL0 Position */ +#define MXC_F_GPIO_PADCTRL0_GPIO_PADCTRL0 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_PADCTRL0_GPIO_PADCTRL0_POS)) /**< PADCTRL0_GPIO_PADCTRL0 Mask */ +#define MXC_V_GPIO_PADCTRL0_GPIO_PADCTRL0_IMPEDANCE ((uint32_t)0x0UL) /**< PADCTRL0_GPIO_PADCTRL0_IMPEDANCE Value */ +#define MXC_S_GPIO_PADCTRL0_GPIO_PADCTRL0_IMPEDANCE (MXC_V_GPIO_PADCTRL0_GPIO_PADCTRL0_IMPEDANCE << MXC_F_GPIO_PADCTRL0_GPIO_PADCTRL0_POS) /**< PADCTRL0_GPIO_PADCTRL0_IMPEDANCE Setting */ +#define MXC_V_GPIO_PADCTRL0_GPIO_PADCTRL0_PU ((uint32_t)0x1UL) /**< PADCTRL0_GPIO_PADCTRL0_PU Value */ +#define MXC_S_GPIO_PADCTRL0_GPIO_PADCTRL0_PU (MXC_V_GPIO_PADCTRL0_GPIO_PADCTRL0_PU << MXC_F_GPIO_PADCTRL0_GPIO_PADCTRL0_POS) /**< PADCTRL0_GPIO_PADCTRL0_PU Setting */ +#define MXC_V_GPIO_PADCTRL0_GPIO_PADCTRL0_PD ((uint32_t)0x2UL) /**< PADCTRL0_GPIO_PADCTRL0_PD Value */ +#define MXC_S_GPIO_PADCTRL0_GPIO_PADCTRL0_PD (MXC_V_GPIO_PADCTRL0_GPIO_PADCTRL0_PD << MXC_F_GPIO_PADCTRL0_GPIO_PADCTRL0_POS) /**< PADCTRL0_GPIO_PADCTRL0_PD Setting */ /**@} end of group GPIO_PADCTRL0_Register */ /** * @ingroup gpio_registers * @defgroup GPIO_PADCTRL1 GPIO_PADCTRL1 - * @brief GPIO Input Mode Config 1. Each bit in this register enables the weak pull-up for + * @brief GPIO Input Mode Config 2. Each bit in this register enables the weak pull-up for * the associated GPIO pin in this port. * @{ */ -#define MXC_F_GPIO_PADCTRL1_ALL_POS 0 /**< PADCTRL1_ALL Position */ -#define MXC_F_GPIO_PADCTRL1_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_PADCTRL1_ALL_POS)) /**< PADCTRL1_ALL Mask */ -#define MXC_V_GPIO_PADCTRL1_ALL_IMPEDANCE ((uint32_t)0x0UL) /**< PADCTRL1_ALL_IMPEDANCE Value */ -#define MXC_S_GPIO_PADCTRL1_ALL_IMPEDANCE (MXC_V_GPIO_PADCTRL1_ALL_IMPEDANCE << MXC_F_GPIO_PADCTRL1_ALL_POS) /**< PADCTRL1_ALL_IMPEDANCE Setting */ -#define MXC_V_GPIO_PADCTRL1_ALL_PU ((uint32_t)0x1UL) /**< PADCTRL1_ALL_PU Value */ -#define MXC_S_GPIO_PADCTRL1_ALL_PU (MXC_V_GPIO_PADCTRL1_ALL_PU << MXC_F_GPIO_PADCTRL1_ALL_POS) /**< PADCTRL1_ALL_PU Setting */ -#define MXC_V_GPIO_PADCTRL1_ALL_PD ((uint32_t)0x2UL) /**< PADCTRL1_ALL_PD Value */ -#define MXC_S_GPIO_PADCTRL1_ALL_PD (MXC_V_GPIO_PADCTRL1_ALL_PD << MXC_F_GPIO_PADCTRL1_ALL_POS) /**< PADCTRL1_ALL_PD Setting */ +#define MXC_F_GPIO_PADCTRL1_GPIO_PADCTRL1_POS 0 /**< PADCTRL1_GPIO_PADCTRL1 Position */ +#define MXC_F_GPIO_PADCTRL1_GPIO_PADCTRL1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_PADCTRL1_GPIO_PADCTRL1_POS)) /**< PADCTRL1_GPIO_PADCTRL1 Mask */ +#define MXC_V_GPIO_PADCTRL1_GPIO_PADCTRL1_IMPEDANCE ((uint32_t)0x0UL) /**< PADCTRL1_GPIO_PADCTRL1_IMPEDANCE Value */ +#define MXC_S_GPIO_PADCTRL1_GPIO_PADCTRL1_IMPEDANCE (MXC_V_GPIO_PADCTRL1_GPIO_PADCTRL1_IMPEDANCE << MXC_F_GPIO_PADCTRL1_GPIO_PADCTRL1_POS) /**< PADCTRL1_GPIO_PADCTRL1_IMPEDANCE Setting */ +#define MXC_V_GPIO_PADCTRL1_GPIO_PADCTRL1_PU ((uint32_t)0x1UL) /**< PADCTRL1_GPIO_PADCTRL1_PU Value */ +#define MXC_S_GPIO_PADCTRL1_GPIO_PADCTRL1_PU (MXC_V_GPIO_PADCTRL1_GPIO_PADCTRL1_PU << MXC_F_GPIO_PADCTRL1_GPIO_PADCTRL1_POS) /**< PADCTRL1_GPIO_PADCTRL1_PU Setting */ +#define MXC_V_GPIO_PADCTRL1_GPIO_PADCTRL1_PD ((uint32_t)0x2UL) /**< PADCTRL1_GPIO_PADCTRL1_PD Value */ +#define MXC_S_GPIO_PADCTRL1_GPIO_PADCTRL1_PD (MXC_V_GPIO_PADCTRL1_GPIO_PADCTRL1_PD << MXC_F_GPIO_PADCTRL1_GPIO_PADCTRL1_POS) /**< PADCTRL1_GPIO_PADCTRL1_PD Setting */ /**@} end of group GPIO_PADCTRL1_Register */ @@ -516,12 +520,12 @@ typedef struct { * between primary/secondary functions for the associated GPIO pin in this port. * @{ */ -#define MXC_F_GPIO_EN1_ALL_POS 0 /**< EN1_ALL Position */ -#define MXC_F_GPIO_EN1_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN1_ALL_POS)) /**< EN1_ALL Mask */ -#define MXC_V_GPIO_EN1_ALL_PRIMARY ((uint32_t)0x0UL) /**< EN1_ALL_PRIMARY Value */ -#define MXC_S_GPIO_EN1_ALL_PRIMARY (MXC_V_GPIO_EN1_ALL_PRIMARY << MXC_F_GPIO_EN1_ALL_POS) /**< EN1_ALL_PRIMARY Setting */ -#define MXC_V_GPIO_EN1_ALL_SECONDARY ((uint32_t)0x1UL) /**< EN1_ALL_SECONDARY Value */ -#define MXC_S_GPIO_EN1_ALL_SECONDARY (MXC_V_GPIO_EN1_ALL_SECONDARY << MXC_F_GPIO_EN1_ALL_POS) /**< EN1_ALL_SECONDARY Setting */ +#define MXC_F_GPIO_EN1_GPIO_EN1_POS 0 /**< EN1_GPIO_EN1 Position */ +#define MXC_F_GPIO_EN1_GPIO_EN1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN1_GPIO_EN1_POS)) /**< EN1_GPIO_EN1 Mask */ +#define MXC_V_GPIO_EN1_GPIO_EN1_PRIMARY ((uint32_t)0x0UL) /**< EN1_GPIO_EN1_PRIMARY Value */ +#define MXC_S_GPIO_EN1_GPIO_EN1_PRIMARY (MXC_V_GPIO_EN1_GPIO_EN1_PRIMARY << MXC_F_GPIO_EN1_GPIO_EN1_POS) /**< EN1_GPIO_EN1_PRIMARY Setting */ +#define MXC_V_GPIO_EN1_GPIO_EN1_SECONDARY ((uint32_t)0x1UL) /**< EN1_GPIO_EN1_SECONDARY Value */ +#define MXC_S_GPIO_EN1_GPIO_EN1_SECONDARY (MXC_V_GPIO_EN1_GPIO_EN1_SECONDARY << MXC_F_GPIO_EN1_GPIO_EN1_POS) /**< EN1_GPIO_EN1_SECONDARY Setting */ /**@} end of group GPIO_EN1_Register */ @@ -558,12 +562,12 @@ typedef struct { * between primary/secondary functions for the associated GPIO pin in this port. * @{ */ -#define MXC_F_GPIO_EN2_ALL_POS 0 /**< EN2_ALL Position */ -#define MXC_F_GPIO_EN2_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN2_ALL_POS)) /**< EN2_ALL Mask */ -#define MXC_V_GPIO_EN2_ALL_PRIMARY ((uint32_t)0x0UL) /**< EN2_ALL_PRIMARY Value */ -#define MXC_S_GPIO_EN2_ALL_PRIMARY (MXC_V_GPIO_EN2_ALL_PRIMARY << MXC_F_GPIO_EN2_ALL_POS) /**< EN2_ALL_PRIMARY Setting */ -#define MXC_V_GPIO_EN2_ALL_SECONDARY ((uint32_t)0x1UL) /**< EN2_ALL_SECONDARY Value */ -#define MXC_S_GPIO_EN2_ALL_SECONDARY (MXC_V_GPIO_EN2_ALL_SECONDARY << MXC_F_GPIO_EN2_ALL_POS) /**< EN2_ALL_SECONDARY Setting */ +#define MXC_F_GPIO_EN2_GPIO_EN2_POS 0 /**< EN2_GPIO_EN2 Position */ +#define MXC_F_GPIO_EN2_GPIO_EN2 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN2_GPIO_EN2_POS)) /**< EN2_GPIO_EN2 Mask */ +#define MXC_V_GPIO_EN2_GPIO_EN2_PRIMARY ((uint32_t)0x0UL) /**< EN2_GPIO_EN2_PRIMARY Value */ +#define MXC_S_GPIO_EN2_GPIO_EN2_PRIMARY (MXC_V_GPIO_EN2_GPIO_EN2_PRIMARY << MXC_F_GPIO_EN2_GPIO_EN2_POS) /**< EN2_GPIO_EN2_PRIMARY Setting */ +#define MXC_V_GPIO_EN2_GPIO_EN2_SECONDARY ((uint32_t)0x1UL) /**< EN2_GPIO_EN2_SECONDARY Value */ +#define MXC_S_GPIO_EN2_GPIO_EN2_SECONDARY (MXC_V_GPIO_EN2_GPIO_EN2_SECONDARY << MXC_F_GPIO_EN2_GPIO_EN2_POS) /**< EN2_GPIO_EN2_SECONDARY Setting */ /**@} end of group GPIO_EN2_Register */ @@ -599,8 +603,8 @@ typedef struct { * @brief GPIO Input Hysteresis Enable. * @{ */ -#define MXC_F_GPIO_HYSEN_ALL_POS 0 /**< HYSEN_ALL Position */ -#define MXC_F_GPIO_HYSEN_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_HYSEN_ALL_POS)) /**< HYSEN_ALL Mask */ +#define MXC_F_GPIO_HYSEN_GPIO_HYSEN_POS 0 /**< HYSEN_GPIO_HYSEN Position */ +#define MXC_F_GPIO_HYSEN_GPIO_HYSEN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_HYSEN_GPIO_HYSEN_POS)) /**< HYSEN_GPIO_HYSEN Mask */ /**@} end of group GPIO_HYSEN_Register */ @@ -610,29 +614,29 @@ typedef struct { * @brief GPIO Slew Rate Enable Register. * @{ */ -#define MXC_F_GPIO_SRSEL_ALL_POS 0 /**< SRSEL_ALL Position */ -#define MXC_F_GPIO_SRSEL_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_SRSEL_ALL_POS)) /**< SRSEL_ALL Mask */ -#define MXC_V_GPIO_SRSEL_ALL_FAST ((uint32_t)0x0UL) /**< SRSEL_ALL_FAST Value */ -#define MXC_S_GPIO_SRSEL_ALL_FAST (MXC_V_GPIO_SRSEL_ALL_FAST << MXC_F_GPIO_SRSEL_ALL_POS) /**< SRSEL_ALL_FAST Setting */ -#define MXC_V_GPIO_SRSEL_ALL_SLOW ((uint32_t)0x1UL) /**< SRSEL_ALL_SLOW Value */ -#define MXC_S_GPIO_SRSEL_ALL_SLOW (MXC_V_GPIO_SRSEL_ALL_SLOW << MXC_F_GPIO_SRSEL_ALL_POS) /**< SRSEL_ALL_SLOW Setting */ +#define MXC_F_GPIO_SRSEL_GPIO_SRSEL_POS 0 /**< SRSEL_GPIO_SRSEL Position */ +#define MXC_F_GPIO_SRSEL_GPIO_SRSEL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_SRSEL_GPIO_SRSEL_POS)) /**< SRSEL_GPIO_SRSEL Mask */ +#define MXC_V_GPIO_SRSEL_GPIO_SRSEL_FAST ((uint32_t)0x0UL) /**< SRSEL_GPIO_SRSEL_FAST Value */ +#define MXC_S_GPIO_SRSEL_GPIO_SRSEL_FAST (MXC_V_GPIO_SRSEL_GPIO_SRSEL_FAST << MXC_F_GPIO_SRSEL_GPIO_SRSEL_POS) /**< SRSEL_GPIO_SRSEL_FAST Setting */ +#define MXC_V_GPIO_SRSEL_GPIO_SRSEL_SLOW ((uint32_t)0x1UL) /**< SRSEL_GPIO_SRSEL_SLOW Value */ +#define MXC_S_GPIO_SRSEL_GPIO_SRSEL_SLOW (MXC_V_GPIO_SRSEL_GPIO_SRSEL_SLOW << MXC_F_GPIO_SRSEL_GPIO_SRSEL_POS) /**< SRSEL_GPIO_SRSEL_SLOW Setting */ /**@} end of group GPIO_SRSEL_Register */ /** * @ingroup gpio_registers * @defgroup GPIO_DS0 GPIO_DS0 - * @brief GPIO Drive Strength 0 Register. Each bit in this register selects the drive + * @brief GPIO Drive Strength Register. Each bit in this register selects the drive * strength for the associated GPIO pin in this port. Refer to the Datasheet for * sink/source current of GPIO pins in each mode. * @{ */ -#define MXC_F_GPIO_DS0_ALL_POS 0 /**< DS0_ALL Position */ -#define MXC_F_GPIO_DS0_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_DS0_ALL_POS)) /**< DS0_ALL Mask */ -#define MXC_V_GPIO_DS0_ALL_LD ((uint32_t)0x0UL) /**< DS0_ALL_LD Value */ -#define MXC_S_GPIO_DS0_ALL_LD (MXC_V_GPIO_DS0_ALL_LD << MXC_F_GPIO_DS0_ALL_POS) /**< DS0_ALL_LD Setting */ -#define MXC_V_GPIO_DS0_ALL_HD ((uint32_t)0x1UL) /**< DS0_ALL_HD Value */ -#define MXC_S_GPIO_DS0_ALL_HD (MXC_V_GPIO_DS0_ALL_HD << MXC_F_GPIO_DS0_ALL_POS) /**< DS0_ALL_HD Setting */ +#define MXC_F_GPIO_DS0_GPIO_DS0_POS 0 /**< DS0_GPIO_DS0 Position */ +#define MXC_F_GPIO_DS0_GPIO_DS0 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_DS0_GPIO_DS0_POS)) /**< DS0_GPIO_DS0 Mask */ +#define MXC_V_GPIO_DS0_GPIO_DS0_LD ((uint32_t)0x0UL) /**< DS0_GPIO_DS0_LD Value */ +#define MXC_S_GPIO_DS0_GPIO_DS0_LD (MXC_V_GPIO_DS0_GPIO_DS0_LD << MXC_F_GPIO_DS0_GPIO_DS0_POS) /**< DS0_GPIO_DS0_LD Setting */ +#define MXC_V_GPIO_DS0_GPIO_DS0_HD ((uint32_t)0x1UL) /**< DS0_GPIO_DS0_HD Value */ +#define MXC_S_GPIO_DS0_GPIO_DS0_HD (MXC_V_GPIO_DS0_GPIO_DS0_HD << MXC_F_GPIO_DS0_GPIO_DS0_POS) /**< DS0_GPIO_DS0_HD Setting */ /**@} end of group GPIO_DS0_Register */ @@ -644,21 +648,21 @@ typedef struct { * sink/source current of GPIO pins in each mode. * @{ */ -#define MXC_F_GPIO_DS1_ALL_POS 0 /**< DS1_ALL Position */ -#define MXC_F_GPIO_DS1_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_DS1_ALL_POS)) /**< DS1_ALL Mask */ +#define MXC_F_GPIO_DS1_GPIO_DS1_POS 0 /**< DS1_GPIO_DS1 Position */ +#define MXC_F_GPIO_DS1_GPIO_DS1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_DS1_GPIO_DS1_POS)) /**< DS1_GPIO_DS1 Mask */ /**@} end of group GPIO_DS1_Register */ /** * @ingroup gpio_registers - * @defgroup GPIO_PSSEL GPIO_PSSEL + * @defgroup GPIO_PS GPIO_PS * @brief GPIO Pull Select Mode. * @{ */ -#define MXC_F_GPIO_PSSEL_ALL_POS 0 /**< PSSEL_ALL Position */ -#define MXC_F_GPIO_PSSEL_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_PSSEL_ALL_POS)) /**< PSSEL_ALL Mask */ +#define MXC_F_GPIO_PS_ALL_POS 0 /**< PS_ALL Position */ +#define MXC_F_GPIO_PS_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_PS_ALL_POS)) /**< PS_ALL Mask */ -/**@} end of group GPIO_PSSEL_Register */ +/**@} end of group GPIO_PS_Register */ /** * @ingroup gpio_registers @@ -675,4 +679,4 @@ typedef struct { } #endif -#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_GPIO_REGS_H_ +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32672_INCLUDE_GPIO_REGS_H_ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32572/Include/htmr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32572/Include/htmr_regs.h index fdf782d0b73..9754df8998b 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32572/Include/htmr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32572/Include/htmr_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32572/Include/i2c_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32572/Include/i2c_regs.h index af14c8567f3..86ca9ce0e58 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32572/Include/i2c_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32572/Include/i2c_regs.h @@ -25,8 +25,8 @@ * ******************************************************************************/ -#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_I2C_REGS_H_ -#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_I2C_REGS_H_ +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32672_INCLUDE_I2C_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32672_INCLUDE_I2C_REGS_H_ /* **** Includes **** */ #include @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile @@ -169,8 +173,8 @@ typedef struct { #define MXC_F_I2C_CTRL_SDA_POS 9 /**< CTRL_SDA Position */ #define MXC_F_I2C_CTRL_SDA ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SDA_POS)) /**< CTRL_SDA Mask */ -#define MXC_F_I2C_CTRL_BB_EN_POS 10 /**< CTRL_BB_EN Position */ -#define MXC_F_I2C_CTRL_BB_EN ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_BB_EN_POS)) /**< CTRL_BB_EN Mask */ +#define MXC_F_I2C_CTRL_BB_MODE_POS 10 /**< CTRL_BB_MODE Position */ +#define MXC_F_I2C_CTRL_BB_MODE ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_BB_MODE_POS)) /**< CTRL_BB_MODE Mask */ #define MXC_F_I2C_CTRL_READ_POS 11 /**< CTRL_READ Position */ #define MXC_F_I2C_CTRL_READ ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_READ_POS)) /**< CTRL_READ Mask */ @@ -448,8 +452,8 @@ typedef struct { #define MXC_F_I2C_TXCTRL0_FLUSH_POS 7 /**< TXCTRL0_FLUSH Position */ #define MXC_F_I2C_TXCTRL0_FLUSH ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_FLUSH_POS)) /**< TXCTRL0_FLUSH Mask */ -#define MXC_F_I2C_TXCTRL0_THD_VAL_POS 8 /**< TXCTRL0_THD_VAL Position */ -#define MXC_F_I2C_TXCTRL0_THD_VAL ((uint32_t)(0xFUL << MXC_F_I2C_TXCTRL0_THD_VAL_POS)) /**< TXCTRL0_THD_VAL Mask */ +#define MXC_F_I2C_TXCTRL0_THD_LVL_POS 8 /**< TXCTRL0_THD_LVL Position */ +#define MXC_F_I2C_TXCTRL0_THD_LVL ((uint32_t)(0xFUL << MXC_F_I2C_TXCTRL0_THD_LVL_POS)) /**< TXCTRL0_THD_LVL Mask */ /**@} end of group I2C_TXCTRL0_Register */ @@ -462,9 +466,6 @@ typedef struct { #define MXC_F_I2C_TXCTRL1_PRELOAD_RDY_POS 0 /**< TXCTRL1_PRELOAD_RDY Position */ #define MXC_F_I2C_TXCTRL1_PRELOAD_RDY ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL1_PRELOAD_RDY_POS)) /**< TXCTRL1_PRELOAD_RDY Mask */ -#define MXC_F_I2C_TXCTRL1_LAST_POS 1 /**< TXCTRL1_LAST Position */ -#define MXC_F_I2C_TXCTRL1_LAST ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL1_LAST_POS)) /**< TXCTRL1_LAST Mask */ - #define MXC_F_I2C_TXCTRL1_LVL_POS 8 /**< TXCTRL1_LVL Position */ #define MXC_F_I2C_TXCTRL1_LVL ((uint32_t)(0xFUL << MXC_F_I2C_TXCTRL1_LVL_POS)) /**< TXCTRL1_LVL Mask */ @@ -499,12 +500,6 @@ typedef struct { #define MXC_F_I2C_MSTCTRL_EX_ADDR_EN_POS 7 /**< MSTCTRL_EX_ADDR_EN Position */ #define MXC_F_I2C_MSTCTRL_EX_ADDR_EN ((uint32_t)(0x1UL << MXC_F_I2C_MSTCTRL_EX_ADDR_EN_POS)) /**< MSTCTRL_EX_ADDR_EN Mask */ -#define MXC_F_I2C_MSTCTRL_CODE_POS 8 /**< MSTCTRL_CODE Position */ -#define MXC_F_I2C_MSTCTRL_CODE ((uint32_t)(0x7UL << MXC_F_I2C_MSTCTRL_CODE_POS)) /**< MSTCTRL_CODE Mask */ - -#define MXC_F_I2C_MSTCTRL_IGN_ACK_POS 12 /**< MSTCTRL_IGN_ACK Position */ -#define MXC_F_I2C_MSTCTRL_IGN_ACK ((uint32_t)(0x1UL << MXC_F_I2C_MSTCTRL_IGN_ACK_POS)) /**< MSTCTRL_IGN_ACK Mask */ - /**@} end of group I2C_MSTCTRL_Register */ /** @@ -589,4 +584,4 @@ typedef struct { } #endif -#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_I2C_REGS_H_ +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32672_INCLUDE_I2C_REGS_H_ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32572/Include/i2s_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32572/Include/i2s_regs.h new file mode 100644 index 00000000000..7ee0408bd63 --- /dev/null +++ b/Libraries/CMSIS/Device/Maxim/MAX32572/Include/i2s_regs.h @@ -0,0 +1,294 @@ +/** + * @file i2s_regs.h + * @brief Registers, Bit Masks and Bit Positions for the I2S Peripheral Module. + * @note This file is @generated. + * @ingroup i2s_registers + */ + +/****************************************************************************** + * + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32672_INCLUDE_I2S_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32672_INCLUDE_I2S_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup i2s + * @defgroup i2s_registers I2S_Registers + * @brief Registers, Bit Masks and Bit Positions for the I2S Peripheral Module. + * @details Inter-IC Sound Interface. + */ + +/** + * @ingroup i2s_registers + * Structure type to access the I2S Registers. + */ +typedef struct { + __IO uint32_t ctrl0ch0; /**< \b 0x00: I2S CTRL0CH0 Register */ + __R uint32_t rsv_0x4_0xf[3]; + __IO uint32_t ctrl1ch0; /**< \b 0x10: I2S CTRL1CH0 Register */ + __R uint32_t rsv_0x14_0x1f[3]; + __IO uint32_t filtch0; /**< \b 0x20: I2S FILTCH0 Register */ + __R uint32_t rsv_0x24_0x2f[3]; + __IO uint32_t dmach0; /**< \b 0x30: I2S DMACH0 Register */ + __R uint32_t rsv_0x34_0x3f[3]; + __IO uint32_t fifoch0; /**< \b 0x40: I2S FIFOCH0 Register */ + __R uint32_t rsv_0x44_0x4f[3]; + __IO uint32_t intfl; /**< \b 0x50: I2S INTFL Register */ + __IO uint32_t inten; /**< \b 0x54: I2S INTEN Register */ + __IO uint32_t extsetup; /**< \b 0x58: I2S EXTSETUP Register */ + __IO uint32_t wken; /**< \b 0x5C: I2S WKEN Register */ + __IO uint32_t wkfl; /**< \b 0x60: I2S WKFL Register */ +} mxc_i2s_regs_t; + +/* Register offsets for module I2S */ +/** + * @ingroup i2s_registers + * @defgroup I2S_Register_Offsets Register Offsets + * @brief I2S Peripheral Register Offsets from the I2S Base Peripheral Address. + * @{ + */ +#define MXC_R_I2S_CTRL0CH0 ((uint32_t)0x00000000UL) /**< Offset from I2S Base Address: 0x0000 */ +#define MXC_R_I2S_CTRL1CH0 ((uint32_t)0x00000010UL) /**< Offset from I2S Base Address: 0x0010 */ +#define MXC_R_I2S_FILTCH0 ((uint32_t)0x00000020UL) /**< Offset from I2S Base Address: 0x0020 */ +#define MXC_R_I2S_DMACH0 ((uint32_t)0x00000030UL) /**< Offset from I2S Base Address: 0x0030 */ +#define MXC_R_I2S_FIFOCH0 ((uint32_t)0x00000040UL) /**< Offset from I2S Base Address: 0x0040 */ +#define MXC_R_I2S_INTFL ((uint32_t)0x00000050UL) /**< Offset from I2S Base Address: 0x0050 */ +#define MXC_R_I2S_INTEN ((uint32_t)0x00000054UL) /**< Offset from I2S Base Address: 0x0054 */ +#define MXC_R_I2S_EXTSETUP ((uint32_t)0x00000058UL) /**< Offset from I2S Base Address: 0x0058 */ +#define MXC_R_I2S_WKEN ((uint32_t)0x0000005CUL) /**< Offset from I2S Base Address: 0x005C */ +#define MXC_R_I2S_WKFL ((uint32_t)0x00000060UL) /**< Offset from I2S Base Address: 0x0060 */ +/**@} end of group i2s_registers */ + +/** + * @ingroup i2s_registers + * @defgroup I2S_CTRL0CH0 I2S_CTRL0CH0 + * @brief Global mode channel. + * @{ + */ +#define MXC_F_I2S_CTRL0CH0_LSB_FIRST_POS 1 /**< CTRL0CH0_LSB_FIRST Position */ +#define MXC_F_I2S_CTRL0CH0_LSB_FIRST ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_LSB_FIRST_POS)) /**< CTRL0CH0_LSB_FIRST Mask */ + +#define MXC_F_I2S_CTRL0CH0_PDM_FILT_POS 2 /**< CTRL0CH0_PDM_FILT Position */ +#define MXC_F_I2S_CTRL0CH0_PDM_FILT ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_PDM_FILT_POS)) /**< CTRL0CH0_PDM_FILT Mask */ + +#define MXC_F_I2S_CTRL0CH0_PDM_EN_POS 3 /**< CTRL0CH0_PDM_EN Position */ +#define MXC_F_I2S_CTRL0CH0_PDM_EN ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_PDM_EN_POS)) /**< CTRL0CH0_PDM_EN Mask */ + +#define MXC_F_I2S_CTRL0CH0_USEDDR_POS 4 /**< CTRL0CH0_USEDDR Position */ +#define MXC_F_I2S_CTRL0CH0_USEDDR ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_USEDDR_POS)) /**< CTRL0CH0_USEDDR Mask */ + +#define MXC_F_I2S_CTRL0CH0_PDM_INV_POS 5 /**< CTRL0CH0_PDM_INV Position */ +#define MXC_F_I2S_CTRL0CH0_PDM_INV ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_PDM_INV_POS)) /**< CTRL0CH0_PDM_INV Mask */ + +#define MXC_F_I2S_CTRL0CH0_CH_MODE_POS 6 /**< CTRL0CH0_CH_MODE Position */ +#define MXC_F_I2S_CTRL0CH0_CH_MODE ((uint32_t)(0x3UL << MXC_F_I2S_CTRL0CH0_CH_MODE_POS)) /**< CTRL0CH0_CH_MODE Mask */ + +#define MXC_F_I2S_CTRL0CH0_WS_POL_POS 8 /**< CTRL0CH0_WS_POL Position */ +#define MXC_F_I2S_CTRL0CH0_WS_POL ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_WS_POL_POS)) /**< CTRL0CH0_WS_POL Mask */ + +#define MXC_F_I2S_CTRL0CH0_MSB_LOC_POS 9 /**< CTRL0CH0_MSB_LOC Position */ +#define MXC_F_I2S_CTRL0CH0_MSB_LOC ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_MSB_LOC_POS)) /**< CTRL0CH0_MSB_LOC Mask */ + +#define MXC_F_I2S_CTRL0CH0_ALIGN_POS 10 /**< CTRL0CH0_ALIGN Position */ +#define MXC_F_I2S_CTRL0CH0_ALIGN ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_ALIGN_POS)) /**< CTRL0CH0_ALIGN Mask */ + +#define MXC_F_I2S_CTRL0CH0_EXT_SEL_POS 11 /**< CTRL0CH0_EXT_SEL Position */ +#define MXC_F_I2S_CTRL0CH0_EXT_SEL ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_EXT_SEL_POS)) /**< CTRL0CH0_EXT_SEL Mask */ + +#define MXC_F_I2S_CTRL0CH0_STEREO_POS 12 /**< CTRL0CH0_STEREO Position */ +#define MXC_F_I2S_CTRL0CH0_STEREO ((uint32_t)(0x3UL << MXC_F_I2S_CTRL0CH0_STEREO_POS)) /**< CTRL0CH0_STEREO Mask */ + +#define MXC_F_I2S_CTRL0CH0_WSIZE_POS 14 /**< CTRL0CH0_WSIZE Position */ +#define MXC_F_I2S_CTRL0CH0_WSIZE ((uint32_t)(0x3UL << MXC_F_I2S_CTRL0CH0_WSIZE_POS)) /**< CTRL0CH0_WSIZE Mask */ + +#define MXC_F_I2S_CTRL0CH0_TX_EN_POS 16 /**< CTRL0CH0_TX_EN Position */ +#define MXC_F_I2S_CTRL0CH0_TX_EN ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_TX_EN_POS)) /**< CTRL0CH0_TX_EN Mask */ + +#define MXC_F_I2S_CTRL0CH0_RX_EN_POS 17 /**< CTRL0CH0_RX_EN Position */ +#define MXC_F_I2S_CTRL0CH0_RX_EN ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_RX_EN_POS)) /**< CTRL0CH0_RX_EN Mask */ + +#define MXC_F_I2S_CTRL0CH0_FLUSH_POS 18 /**< CTRL0CH0_FLUSH Position */ +#define MXC_F_I2S_CTRL0CH0_FLUSH ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_FLUSH_POS)) /**< CTRL0CH0_FLUSH Mask */ + +#define MXC_F_I2S_CTRL0CH0_RST_POS 19 /**< CTRL0CH0_RST Position */ +#define MXC_F_I2S_CTRL0CH0_RST ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_RST_POS)) /**< CTRL0CH0_RST Mask */ + +#define MXC_F_I2S_CTRL0CH0_FIFO_LSB_POS 20 /**< CTRL0CH0_FIFO_LSB Position */ +#define MXC_F_I2S_CTRL0CH0_FIFO_LSB ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_FIFO_LSB_POS)) /**< CTRL0CH0_FIFO_LSB Mask */ + +#define MXC_F_I2S_CTRL0CH0_RX_THD_VAL_POS 24 /**< CTRL0CH0_RX_THD_VAL Position */ +#define MXC_F_I2S_CTRL0CH0_RX_THD_VAL ((uint32_t)(0xFFUL << MXC_F_I2S_CTRL0CH0_RX_THD_VAL_POS)) /**< CTRL0CH0_RX_THD_VAL Mask */ + +/**@} end of group I2S_CTRL0CH0_Register */ + +/** + * @ingroup i2s_registers + * @defgroup I2S_CTRL1CH0 I2S_CTRL1CH0 + * @brief Local channel Setup. + * @{ + */ +#define MXC_F_I2S_CTRL1CH0_BITS_WORD_POS 0 /**< CTRL1CH0_BITS_WORD Position */ +#define MXC_F_I2S_CTRL1CH0_BITS_WORD ((uint32_t)(0x1FUL << MXC_F_I2S_CTRL1CH0_BITS_WORD_POS)) /**< CTRL1CH0_BITS_WORD Mask */ + +#define MXC_F_I2S_CTRL1CH0_EN_POS 8 /**< CTRL1CH0_EN Position */ +#define MXC_F_I2S_CTRL1CH0_EN ((uint32_t)(0x1UL << MXC_F_I2S_CTRL1CH0_EN_POS)) /**< CTRL1CH0_EN Mask */ + +#define MXC_F_I2S_CTRL1CH0_SMP_SIZE_POS 9 /**< CTRL1CH0_SMP_SIZE Position */ +#define MXC_F_I2S_CTRL1CH0_SMP_SIZE ((uint32_t)(0x1FUL << MXC_F_I2S_CTRL1CH0_SMP_SIZE_POS)) /**< CTRL1CH0_SMP_SIZE Mask */ + +#define MXC_F_I2S_CTRL1CH0_ADJUST_POS 15 /**< CTRL1CH0_ADJUST Position */ +#define MXC_F_I2S_CTRL1CH0_ADJUST ((uint32_t)(0x1UL << MXC_F_I2S_CTRL1CH0_ADJUST_POS)) /**< CTRL1CH0_ADJUST Mask */ + +#define MXC_F_I2S_CTRL1CH0_CLKDIV_POS 16 /**< CTRL1CH0_CLKDIV Position */ +#define MXC_F_I2S_CTRL1CH0_CLKDIV ((uint32_t)(0xFFFFUL << MXC_F_I2S_CTRL1CH0_CLKDIV_POS)) /**< CTRL1CH0_CLKDIV Mask */ + +/**@} end of group I2S_CTRL1CH0_Register */ + +/** + * @ingroup i2s_registers + * @defgroup I2S_DMACH0 I2S_DMACH0 + * @brief DMA Control. + * @{ + */ +#define MXC_F_I2S_DMACH0_DMA_TX_THD_VAL_POS 0 /**< DMACH0_DMA_TX_THD_VAL Position */ +#define MXC_F_I2S_DMACH0_DMA_TX_THD_VAL ((uint32_t)(0x7FUL << MXC_F_I2S_DMACH0_DMA_TX_THD_VAL_POS)) /**< DMACH0_DMA_TX_THD_VAL Mask */ + +#define MXC_F_I2S_DMACH0_DMA_TX_EN_POS 7 /**< DMACH0_DMA_TX_EN Position */ +#define MXC_F_I2S_DMACH0_DMA_TX_EN ((uint32_t)(0x1UL << MXC_F_I2S_DMACH0_DMA_TX_EN_POS)) /**< DMACH0_DMA_TX_EN Mask */ + +#define MXC_F_I2S_DMACH0_DMA_RX_THD_VAL_POS 8 /**< DMACH0_DMA_RX_THD_VAL Position */ +#define MXC_F_I2S_DMACH0_DMA_RX_THD_VAL ((uint32_t)(0x7FUL << MXC_F_I2S_DMACH0_DMA_RX_THD_VAL_POS)) /**< DMACH0_DMA_RX_THD_VAL Mask */ + +#define MXC_F_I2S_DMACH0_DMA_RX_EN_POS 15 /**< DMACH0_DMA_RX_EN Position */ +#define MXC_F_I2S_DMACH0_DMA_RX_EN ((uint32_t)(0x1UL << MXC_F_I2S_DMACH0_DMA_RX_EN_POS)) /**< DMACH0_DMA_RX_EN Mask */ + +#define MXC_F_I2S_DMACH0_TX_LVL_POS 16 /**< DMACH0_TX_LVL Position */ +#define MXC_F_I2S_DMACH0_TX_LVL ((uint32_t)(0xFFUL << MXC_F_I2S_DMACH0_TX_LVL_POS)) /**< DMACH0_TX_LVL Mask */ + +#define MXC_F_I2S_DMACH0_RX_LVL_POS 24 /**< DMACH0_RX_LVL Position */ +#define MXC_F_I2S_DMACH0_RX_LVL ((uint32_t)(0xFFUL << MXC_F_I2S_DMACH0_RX_LVL_POS)) /**< DMACH0_RX_LVL Mask */ + +/**@} end of group I2S_DMACH0_Register */ + +/** + * @ingroup i2s_registers + * @defgroup I2S_FIFOCH0 I2S_FIFOCH0 + * @brief I2S Fifo. + * @{ + */ +#define MXC_F_I2S_FIFOCH0_DATA_POS 0 /**< FIFOCH0_DATA Position */ +#define MXC_F_I2S_FIFOCH0_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_I2S_FIFOCH0_DATA_POS)) /**< FIFOCH0_DATA Mask */ + +/**@} end of group I2S_FIFOCH0_Register */ + +/** + * @ingroup i2s_registers + * @defgroup I2S_INTFL I2S_INTFL + * @brief ISR Status. + * @{ + */ +#define MXC_F_I2S_INTFL_RX_OV_CH0_POS 0 /**< INTFL_RX_OV_CH0 Position */ +#define MXC_F_I2S_INTFL_RX_OV_CH0 ((uint32_t)(0x1UL << MXC_F_I2S_INTFL_RX_OV_CH0_POS)) /**< INTFL_RX_OV_CH0 Mask */ + +#define MXC_F_I2S_INTFL_RX_THD_CH0_POS 1 /**< INTFL_RX_THD_CH0 Position */ +#define MXC_F_I2S_INTFL_RX_THD_CH0 ((uint32_t)(0x1UL << MXC_F_I2S_INTFL_RX_THD_CH0_POS)) /**< INTFL_RX_THD_CH0 Mask */ + +#define MXC_F_I2S_INTFL_TX_OB_CH0_POS 2 /**< INTFL_TX_OB_CH0 Position */ +#define MXC_F_I2S_INTFL_TX_OB_CH0 ((uint32_t)(0x1UL << MXC_F_I2S_INTFL_TX_OB_CH0_POS)) /**< INTFL_TX_OB_CH0 Mask */ + +#define MXC_F_I2S_INTFL_TX_HE_CH0_POS 3 /**< INTFL_TX_HE_CH0 Position */ +#define MXC_F_I2S_INTFL_TX_HE_CH0 ((uint32_t)(0x1UL << MXC_F_I2S_INTFL_TX_HE_CH0_POS)) /**< INTFL_TX_HE_CH0 Mask */ + +/**@} end of group I2S_INTFL_Register */ + +/** + * @ingroup i2s_registers + * @defgroup I2S_INTEN I2S_INTEN + * @brief Interrupt Enable. + * @{ + */ +#define MXC_F_I2S_INTEN_RX_OV_CH0_POS 0 /**< INTEN_RX_OV_CH0 Position */ +#define MXC_F_I2S_INTEN_RX_OV_CH0 ((uint32_t)(0x1UL << MXC_F_I2S_INTEN_RX_OV_CH0_POS)) /**< INTEN_RX_OV_CH0 Mask */ + +#define MXC_F_I2S_INTEN_RX_THD_CH0_POS 1 /**< INTEN_RX_THD_CH0 Position */ +#define MXC_F_I2S_INTEN_RX_THD_CH0 ((uint32_t)(0x1UL << MXC_F_I2S_INTEN_RX_THD_CH0_POS)) /**< INTEN_RX_THD_CH0 Mask */ + +#define MXC_F_I2S_INTEN_TX_OB_CH0_POS 2 /**< INTEN_TX_OB_CH0 Position */ +#define MXC_F_I2S_INTEN_TX_OB_CH0 ((uint32_t)(0x1UL << MXC_F_I2S_INTEN_TX_OB_CH0_POS)) /**< INTEN_TX_OB_CH0 Mask */ + +#define MXC_F_I2S_INTEN_TX_HE_CH0_POS 3 /**< INTEN_TX_HE_CH0 Position */ +#define MXC_F_I2S_INTEN_TX_HE_CH0 ((uint32_t)(0x1UL << MXC_F_I2S_INTEN_TX_HE_CH0_POS)) /**< INTEN_TX_HE_CH0 Mask */ + +/**@} end of group I2S_INTEN_Register */ + +/** + * @ingroup i2s_registers + * @defgroup I2S_EXTSETUP I2S_EXTSETUP + * @brief Ext Control. + * @{ + */ +#define MXC_F_I2S_EXTSETUP_EXT_BITS_WORD_POS 0 /**< EXTSETUP_EXT_BITS_WORD Position */ +#define MXC_F_I2S_EXTSETUP_EXT_BITS_WORD ((uint32_t)(0x1FUL << MXC_F_I2S_EXTSETUP_EXT_BITS_WORD_POS)) /**< EXTSETUP_EXT_BITS_WORD Mask */ + +/**@} end of group I2S_EXTSETUP_Register */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32672_INCLUDE_I2S_REGS_H_ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32572/Include/icc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32572/Include/icc_regs.h new file mode 100644 index 00000000000..11394e51e7a --- /dev/null +++ b/Libraries/CMSIS/Device/Maxim/MAX32572/Include/icc_regs.h @@ -0,0 +1,162 @@ +/** + * @file icc_regs.h + * @brief Registers, Bit Masks and Bit Positions for the ICC Peripheral Module. + * @note This file is @generated. + * @ingroup icc_registers + */ + +/****************************************************************************** + * + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32672_INCLUDE_ICC_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32672_INCLUDE_ICC_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup icc + * @defgroup icc_registers ICC_Registers + * @brief Registers, Bit Masks and Bit Positions for the ICC Peripheral Module. + * @details Instruction Cache Controller Registers + */ + +/** + * @ingroup icc_registers + * Structure type to access the ICC Registers. + */ +typedef struct { + __I uint32_t info; /**< \b 0x0000: ICC INFO Register */ + __I uint32_t sz; /**< \b 0x0004: ICC SZ Register */ + __R uint32_t rsv_0x8_0xff[62]; + __IO uint32_t ctrl; /**< \b 0x0100: ICC CTRL Register */ + __R uint32_t rsv_0x104_0x6ff[383]; + __IO uint32_t invalidate; /**< \b 0x0700: ICC INVALIDATE Register */ +} mxc_icc_regs_t; + +/* Register offsets for module ICC */ +/** + * @ingroup icc_registers + * @defgroup ICC_Register_Offsets Register Offsets + * @brief ICC Peripheral Register Offsets from the ICC Base Peripheral Address. + * @{ + */ +#define MXC_R_ICC_INFO ((uint32_t)0x00000000UL) /**< Offset from ICC Base Address: 0x0000 */ +#define MXC_R_ICC_SZ ((uint32_t)0x00000004UL) /**< Offset from ICC Base Address: 0x0004 */ +#define MXC_R_ICC_CTRL ((uint32_t)0x00000100UL) /**< Offset from ICC Base Address: 0x0100 */ +#define MXC_R_ICC_INVALIDATE ((uint32_t)0x00000700UL) /**< Offset from ICC Base Address: 0x0700 */ +/**@} end of group icc_registers */ + +/** + * @ingroup icc_registers + * @defgroup ICC_INFO ICC_INFO + * @brief Cache ID Register. + * @{ + */ +#define MXC_F_ICC_INFO_RELNUM_POS 0 /**< INFO_RELNUM Position */ +#define MXC_F_ICC_INFO_RELNUM ((uint32_t)(0x3FUL << MXC_F_ICC_INFO_RELNUM_POS)) /**< INFO_RELNUM Mask */ + +#define MXC_F_ICC_INFO_PARTNUM_POS 6 /**< INFO_PARTNUM Position */ +#define MXC_F_ICC_INFO_PARTNUM ((uint32_t)(0xFUL << MXC_F_ICC_INFO_PARTNUM_POS)) /**< INFO_PARTNUM Mask */ + +#define MXC_F_ICC_INFO_ID_POS 10 /**< INFO_ID Position */ +#define MXC_F_ICC_INFO_ID ((uint32_t)(0x3FUL << MXC_F_ICC_INFO_ID_POS)) /**< INFO_ID Mask */ + +/**@} end of group ICC_INFO_Register */ + +/** + * @ingroup icc_registers + * @defgroup ICC_SZ ICC_SZ + * @brief Memory Configuration Register. + * @{ + */ +#define MXC_F_ICC_SZ_CCH_POS 0 /**< SZ_CCH Position */ +#define MXC_F_ICC_SZ_CCH ((uint32_t)(0xFFFFUL << MXC_F_ICC_SZ_CCH_POS)) /**< SZ_CCH Mask */ + +#define MXC_F_ICC_SZ_MEM_POS 16 /**< SZ_MEM Position */ +#define MXC_F_ICC_SZ_MEM ((uint32_t)(0xFFFFUL << MXC_F_ICC_SZ_MEM_POS)) /**< SZ_MEM Mask */ + +/**@} end of group ICC_SZ_Register */ + +/** + * @ingroup icc_registers + * @defgroup ICC_CTRL ICC_CTRL + * @brief Cache Control and Status Register. + * @{ + */ +#define MXC_F_ICC_CTRL_EN_POS 0 /**< CTRL_EN Position */ +#define MXC_F_ICC_CTRL_EN ((uint32_t)(0x1UL << MXC_F_ICC_CTRL_EN_POS)) /**< CTRL_EN Mask */ + +#define MXC_F_ICC_CTRL_RDY_POS 16 /**< CTRL_RDY Position */ +#define MXC_F_ICC_CTRL_RDY ((uint32_t)(0x1UL << MXC_F_ICC_CTRL_RDY_POS)) /**< CTRL_RDY Mask */ + +/**@} end of group ICC_CTRL_Register */ + +/** + * @ingroup icc_registers + * @defgroup ICC_INVALIDATE ICC_INVALIDATE + * @brief Invalidate All Registers. + * @{ + */ +#define MXC_F_ICC_INVALIDATE_INVALID_POS 0 /**< INVALIDATE_INVALID Position */ +#define MXC_F_ICC_INVALIDATE_INVALID ((uint32_t)(0xFFFFFFFFUL << MXC_F_ICC_INVALIDATE_INVALID_POS)) /**< INVALIDATE_INVALID Mask */ + +/**@} end of group ICC_INVALIDATE_Register */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32672_INCLUDE_ICC_REGS_H_ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32572/Include/max32672.svd b/Libraries/CMSIS/Device/Maxim/MAX32572/Include/max32672.svd new file mode 100644 index 00000000000..98e5cbfeace --- /dev/null +++ b/Libraries/CMSIS/Device/Maxim/MAX32572/Include/max32672.svd @@ -0,0 +1,13165 @@ + + + Maxim-Integrated + Maxim + max32672 + ARMCM4 + 1.0 + MAX32672 High-Reliability, Tiny, Ultra-Low-Power AEM Cortex-M4F Microcontroller with 12-bit 1MSPS ADC. + + CM4 + r2p1 + little + true + true + 3 + false + + 8 + 32 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + ADC + Inter-Integrated Circuit. + ADC + 0x40034000 + 32 + + 0x00 + 0x1000 + registers + + + ADC + ADC IRQ + 20 + + + + CTRL0 + Control Register 0. + 0x00 + + + ADC_EN + ADC Enable. + [0:0] + read-write + + + dis + Disable ADC. + 0 + + + en + enable ADC. + 1 + + + + + BIAS_EN + Bias Enable. + [1:1] + read-write + + + dis + Disable Bias. + 0 + + + en + Enable Bias. + 1 + + + + + SKIP_CAL + Skip Calibration Enable. + [2:2] + read-write + + + no_skip + Do not skip calibration. + 0 + + + skip + Skip calibration. + 1 + + + + + CHOP_FORCE + Chop Force Control. + [3:3] + read-write + + + dis + Do not force chop mode. + 0 + + + en + Force chop Mode. + 1 + + + + + RESETB + Reset ADC. + [4:4] + read-write + + + reset + reset ADC. + 0 + + + activate + activate ADC. + 1 + + + + + + + CTRL1 + Control Register 1. + 0x04 + + + START + Start conversion control. + [0:0] + read-write + + + stop + Stop conversions. + 0 + + + start + Start conversions. + 1 + + + + + TRIG_MODE + Trigger mode control. + [1:1] + read-write + + + software + software trigger mode. + 0 + + + hardware + hardware trigger mode. + 1 + + + + + CNV_MODE + Conversion mode control. + [2:2] + read-write + + + atomic + Do one conversion sequence. + 0 + + + continuous + Do continuous conversion sequences. + 1 + + + + + SAMP_CK_OFF + Sample clock off control. + [3:3] + read-write + + + always + Sample clock always generated. + 0 + + + cnv_only + Sample clock generated only when converting. + 1 + + + + + TRIG_SEL + Hardware trigger source select. + [6:4] + read-write + + + TS_SEL + Temp sensor select. + [7:7] + read-write + + + dis + Temp sensor is not one of the slots in the sequence. + 0 + + + en + Temp sensor is one of the slots in the sequence. + 1 + + + + + AVG + Number of samples to average for each output data code. + [10:8] + read-write + + + avg1 + 1 Sample per output code. + 0 + + + avg2 + 2 Samples per output code. + 1 + + + avg4 + 4 Samples per output code. + 2 + + + avg8 + 8 Samples per output code. + 3 + + + avg16 + 16 Samples per output code. + 4 + + + avg32 + 32 Samples per output code. + 5 + + + + + NUM_SLOTS + Number of slots enabled for the conversion sequence + [20:16] + read-write + + + + + CLKCTRL + Clock Control Register. + 0x08 + + + CLKSEL + Clock source select. + [1:0] + read-write + + + HCLK + Select HCLK. + 0 + + + CLK_ADC0 + Select CLK_ADC0. + 1 + + + CLK_ADC1 + Select CLK_ADC1. + 2 + + + CLK_ADC2 + Select CLK_ADC2. + 3 + + + + + CLKDIV + Clock divider control. + [6:4] + read-write + + + DIV2 + Divide by 2. + 0 + + + DIV4 + Divide by 4. + 1 + + + DIV8 + Divide by 8. + 2 + + + DIV16 + Divide by 16. + 3 + + + DIV1 + Divide by 1. + 4 + + + + + + + SAMPCLKCTRL + Sample Clock Control Register. + 0x0C + read-write + + + TRACK_CNT + Number of cycles for SAMPLE_CLK high time. + [7:0] + read-write + + + IDLE_CNT + Number of cycles for SAMPLE_CLK low time. + [31:16] + read-write + + + + + CHSEL0 + Channel Select Register 0. + 0x10 + + + slot0_id + channel assignment for slot 0. + [4:0] + read-write + + + slot1_id + channel assignment for slot 1. + [12:8] + read-write + + + slot2_id + channel assignment for slot 2. + [20:16] + read-write + + + slot3_id + channel assignment for slot 3. + [28:24] + read-write + + + + + CHSEL1 + Channel Select Register 1. + 0x14 + + + slot4_id + channel assignment for slot 4. + [4:0] + read-write + + + slot5_id + channel assignment for slot 5. + [12:8] + read-write + + + slot6_id + channel assignment for slot 6. + [20:16] + read-write + + + slot7_id + channel assignment for slot 7. + [28:24] + read-write + + + + + CHSEL2 + Channel Select Register 2. + 0x18 + + + slot8_id + channel assignment for slot 8. + [4:0] + read-write + + + slot9_id + channel assignment for slot 9. + [12:8] + read-write + + + slot10_id + channel assignment for slot 10. + [20:16] + read-write + + + slot11_id + channel assignment for slot 11. + [28:24] + read-write + + + + + CHSEL3 + Channel Select Register 3. + 0x1C + + + slot12_id + channel assignment for slot 12. + [4:0] + read-write + + + slot13_id + channel assignment for slot 13. + [12:8] + read-write + + + slot14_id + channel assignment for slot 14. + [20:16] + read-write + + + slot15_id + channel assignment for slot 15. + [28:24] + read-write + + + + + RESTART + Restart Count Control Register + 0x30 + + + CNT + Number of sample periods to skip before restarting a continuous mode sequence + [15:0] + read-write + + + + + DATAFMT + Channel Data Format Register + 0x3C + + + MODE + Data format control + [31:0] + read-write + + + + + FIFODMACTRL + FIFO and DMA control + 0x40 + + + DMA_EN + DMA Enable. + [0:0] + read-write + + + dis + Disable DMA. + 0 + + + en + Enable DMA. + 1 + + + + + FLUSH + FIFO Flush. + [1:1] + read-write + + + normal + Normal FIFO operation. + 0 + + + flush + Flush FIFO. + 1 + + + + + DATA_FORMAT + DATA format control. + [3:2] + read-write + + + data_status + Data and Status in FIFO. + 0 + + + data_only + Only Data in FIFO. + 1 + + + raw_data_only + Only Raw Data in FIFO. + 2 + + + + + THRESH + FIFO Threshold. These bits define the FIFO interrupt threshold. + [15:8] + read-write + + + + + DATA + Data Register (FIFO). + 0x44 + + + DATA + Conversion data. + [15:0] + read-only + + + CHAN + Channel for the data. + [20:16] + read-only + + + INVALID + Invalid status for the data. + [24:24] + read-only + + + CLIPPED + Clipped status for the data. + [31:31] + read-only + + + + + STATUS + Status Register + 0x48 + + + READY + Indication that the ADC is in ON power state + [0:0] + read-only + + + EMPTY + FIFO Empty + [1:1] + read-only + + + FULL + FIFO full + [2:2] + read-only + + + FIFO_LEVEL + Number of entries in FIFO available to read + [15:8] + read-only + + + + + CHSTATUS + Channel Status + 0x4C + + + CLIPPED + + [31:0] + read-write + + + + + INTEN + Interrupt Enable Register. + 0x50 + + + READY + ADC is ready. + [0:0] + read-write + + + ABORT + Conversion start is aborted. + [2:2] + read-write + + + START_DET + Conversion start is detected. + [3:3] + read-write + + + SEQ_STARTED + [4:4] + read-write + + + SEQ_DONE + [5:5] + read-write + + + CONV_DONE + [6:6] + read-write + + + CLIPPED + [7:7] + read-write + + + FIFO_LVL + [8:8] + read-write + + + FIFO_UFL + [9:9] + read-write + + + FIFO_OFL + [10:10] + read-write + + + + + INTFL + Interrupt Flags Register. + 0x54 + + + READY + ADC is ready. + [0:0] + read-write + oneToClear + + + ABORT + Conversion start is aborted. + [2:2] + read-write + oneToClear + + + START_DET + Conversion start is detected. + [3:3] + read-write + oneToClear + + + SEQ_STARTED + [4:4] + read-write + oneToClear + + + SEQ_DONE + [5:5] + read-write + oneToClear + + + CONV_DONE + [6:6] + read-write + oneToClear + + + CLIPPED + [7:7] + read-write + oneToClear + + + FIFO_LVL + [8:8] + read-write + oneToClear + + + FIFO_UFL + [9:9] + read-write + oneToClear + + + FIFO_OFL + [10:10] + read-write + oneToClear + + + + + SFRADDROFFSET + SFR Address Offset Register + 0x60 + + + OFFSET + Address Offset for SAR Digital + [7:0] + read-write + + + + + SFRADDR + SFR Address Register + 0x64 + + + ADDR + Address to SAR Digital + [7:0] + read-write + + + + + SFRWRDATA + SFR Write Data Register + 0x68 + + + DATA + DATA to SAR Digital + [7:0] + read-write + + + + + SFRRDDATA + SFR Read Data Register + 0x6C + + + DATA + DATA from SAR Digital + [7:0] + read-only + + + + + SFRSTATUS + SFR Status Register + 0x70 + + + NACK + NACK status for SAR Digital SFR communication + [0:0] + read-only + + + + + + + + AES + AES Keys. + 0x40207400 + + 0x00 + 0x400 + registers + + + + CTRL + AES Control Register + 0x0000 + 32 + + + EN + AES Enable + [0:0] + read-write + + + DMA_RX_EN + DMA Request To Read Data Output FIFO + [1:1] + read-write + + + DMA_TX_EN + DMA Request To Write Data Input FIFO + [2:2] + read-write + + + START + Start AES Calculation + [3:3] + read-write + + + INPUT_FLUSH + Flush the data input FIFO + [4:4] + read-write + + + OUTPUT_FLUSH + Flush the data output FIFO + [5:5] + read-write + + + KEY_SIZE + Encryption Key Size + [7:6] + read-write + + + AES128 + 128 Bits. + 0 + + + AES192 + 192 Bits. + 1 + + + AES256 + 256 Bits. + 2 + + + + + TYPE + Encryption Type Selection + [9:8] + read-write + + + + + STATUS + AES Status Register + 0x0004 + + + BUSY + AES Busy Status + [0:0] + read-write + + + INPUT_EM + Data input FIFO empty status + [1:1] + read-write + + + INPUT_FULL + Data input FIFO full status + [2:2] + read-write + + + OUTPUT_EM + Data output FIFO empty status + [3:3] + read-write + + + OUTPUT_FULL + Data output FIFO full status + [4:4] + read-write + + + + + INTFL + AES Interrupt Flag Register + 0x0008 + + + DONE + AES Done Interrupt + [0:0] + read-write + + + KEY_CHANGE + External AES Key Changed Interrupt + [1:1] + read-write + + + KEY_ZERO + External AES Key Zero Interrupt + [2:2] + read-write + + + OV + Data Output FIFO Overrun Interrupt + [3:3] + read-write + + + KEY_ONE + KEY_ONE + [4:4] + read-write + + + + + INTEN + AES Interrupt Enable Register + 0x000C + + + DONE + AES Done Interrupt Enable + [0:0] + read-write + + + KEY_CHANGE + External AES Key Changed Interrupt Enable + [1:1] + read-write + + + KEY_ZERO + External AES Key Zero Interrupt Enable + [2:2] + read-write + + + OV + Data Output FIFO Overrun Interrupt Enable + [3:3] + read-write + + + KEY_ONE + KEY_ONE + [4:4] + read-write + + + + + FIFO + AES Data Register + 0x0010 + + + DATA + AES FIFO + [0:0] + read-write + + + + + + + + SYS_AESKEYS + System AES Key Registers. + 0x40205000 + + 0x00 + 0x400 + registers + + + + KEY0 + AES Key 0. + 0x00 + 32 + + + KEY1 + AES Key 1. + 0x04 + 32 + + + KEY2 + AES Key 2. + 0x08 + 32 + + + KEY3 + AES Key 3. + 0x0C + 32 + + + KEY4 + AES Key 4. + 0x10 + 32 + + + KEY5 + AES Key 5. + 0x14 + 32 + + + KEY6 + AES Key 6. + 0x18 + 32 + + + KEY7 + AES Key 7. + 0x1C + 32 + + + + + + USR_AESKEYS + User AES Key Registers. + 0x40005000 + + 0x00 + 0x400 + registers + + + + SRAM_KEY + AES SRAM KEY + 0x00 + 32 + + + CODE_KEY + AES CODE Key + 0x20 + + + DATA_KEY + AES DATA KEY + 0x40 + + + + + + CTB + The Cryptographic Toolbox is a combination of cryptographic engines and a secure cryptographic accelerator (SCA) used to provide advanced cryptographic security. + 0x40001000 + + 0x00 + 0x1000 + registers + + + Crypto_Engine + Crypto Engine interrupt. + 27 + + + + CTRL + Crypto Control Register. + 0x00 + 0xC0000000 + + + RST + Reset. This bit is used to reset the crypto accelerator. All crypto internal states and related registers are reset to their default reset values. Control register such as CRYPTO_CTRL, CIPHER_CTRL, HASH_CTRL, CRC_CTRL, MAA_CTRL (with the exception of the STC bit), HASH_MSG_SZ_[3:0] and MAA_MAWS will retain their values. This bit will automatically clear itself after one cycle. + 0 + 1 + + reset_write + write + + reset + Starts reset operation. + 1 + + + + reset_read + read + + reset_done + Reset complete. + 0 + + + busy + Reset in progress. + 1 + + + + + INTR + Interrupt Enable. Generates an interrupt when done or error set. + 1 + 1 + + + dis + Disable + 0 + + + en + Enable + 1 + + + + + SRC + Source Select. This bit selects the hash function and CRC generator input source. + 2 + 1 + + + inputFIFO + Input FIFO + 0 + + + outputFIFO + Output FIFO + 1 + + + + + BSO + Byte Swap Output. Note. No byte swap will occur if there is not a full word. + 4 + 1 + + + BSI + Byte Swap Input. Note. No byte swap will occur if there is not a full word. + 5 + 1 + + + WAIT_EN + Wait Pin Enable. This can be used to hold off the crypto DMA until an external memory is ready. This is useful for transferring pages from NAND flash which may take several microseconds to become ready. + 6 + 1 + + + WAIT_POL + Wait Pin Polarity. When the wait pin is enabled, this bit selects its active state. + 7 + 1 + + + activeLo + Active Low. + 0 + + + activeHi + Active High. + 1 + + + + + WRSRC + Write FIFO Source Select. This field determines where data written to the write FIFO comes from. When data is written to the write FIFO, it is always written out the DMA. To decrypt or encrypt data, the write FIFO source should be set to the cipher output. To implement memcpy() or memset() functions, or to fill memory with random data, the write FIFO source should be set to the read FIFO. When calculating a HASH or CMAC, the write FIFO should be disabled. + 8 + 2 + + + none + None. + 0 + + + cipherOutput + Cipher Output. + 1 + + + readFIFO + Read FIFO. + 2 + + + + + RDSRC + Read FIFO Source Select. This field selects the source of the read FIFO. Typically, it is set to use the DMA. To implement a memset() function, the read FIFO DMA should be disabled. To fill memory with random data or to hash random numbers, the read FIFO source should be set to the random number generator. + 10 + 2 + + + dmaDisabled + DMA Disable. + 0 + + + dmaOrApb + DMA Or APB. + 1 + + + rng + RNG. + 2 + + + + + FLAG_MODE + Done Flag Mode. This bit configures the access behavior of the individual CRYPTO_CTRL Done flags (CRYPTO_CTRL[27:24]). This bit is cleared only on reset to limit upkeep, i.e. once set, it will remain set until a reset occurs. + 14 + 1 + + + unres_wr + Unrestricted write (0 or 1) of CRYPTO_CTRL[27:24] flags. + 0 + + + res_wr + Access to CRYPTO_CTRL[27:24] are write 1 to clear/write 0 no effect. + 1 + + + + + DMADNEMSK + DMA Done Flag Mask. This bit masks the DMA_DONE flag from being used to generate the CRYPTO_CTRL.DONE flag, and this disables a DMA_DONE condition from generating and interrupt. The DMA_DONE flag itself is unaffected and still may be monitored. This allows more optimal interrupt-driven crypto operations using DMA. + 15 + 1 + + + not_used + DMA_DONE not used in setting CRYPTO_CTRL.DONE bit. + 0 + + + used + DMA_DONE used in setting CRYPTO_CTRL.DONE bit. + 1 + + + + + DMA_DONE + DMA Done. DMA write/read operation is complete. This bit must be cleared before starting a DMA operation. + 24 + 1 + + + notDone + Not Done. + 0 + + + done + Done. + 1 + + + + + GLS_DONE + Galois Done. FIFO is full and CRC or Hamming Code Generator is enabled. This bit must be cleared before starting a CRC operation Note that DMA_DONE must be polled instead of this bit to determine the end of DMA operation during the utilization of Hamming Code Generator. + 25 + 1 + + + HSH_DONE + Hash Done. SHA operation is complete. This bit must be cleared before starting a HASH operation. + 26 + 1 + + + CPH_DONE + Cipher Done. Either AES or DES encryption/decryption operation is complete. This bit must be cleared before starting a cipher operation. + 27 + 1 + + + ERR + AHB Bus Error. This bit is set when the DMA encounters a bus error during a read or write operation. Once this bit is set, the DMA will stop. This bit can only be cleared by resetting the crypto block. + 29 + 1 + read-only + + + noError + No Error. + 0 + + + error + Error. + 1 + + + + + RDY + Ready. Crypto block ready for more data. + 30 + 1 + read-only + + + busy + Busy. + 0 + + + ready + Ready. + 1 + + + + + DONE + Done. One or more cryptographic calculations complete (logical OR of done flags). + 31 + 1 + read-only + + + + + CIPHER_CTRL + Cipher Control Register. + 0x04 + + + ENC + Encrypt. Select encryption or decryption of input data. + 0 + 1 + + + encrypt + Encrypt. + 0 + + + decrypt + Decrypt. + 1 + + + + + KEY + Load Key from crypto DMA. This bit is automatically cleared by hardware after the DMA has completed loading the key. When the DMA operation is done, it sets the appropriate crypto DMA Done flag. + 1 + 1 + + + complete + No operation/complete. + 0 + + + start + Start operation. + 1 + + + + + SRC + Source of Random key. + 2 + 2 + + + cipherKey + User cipher key (0x4000_1060). + 0 + + + regFile + Key from battery-backed register file (0x4000_5000 to 0x4000_501F). + 2 + + + qspiKey_regFile + Key from battery-backed register file (0x4000_5020 to 0x4000_502F). + 3 + + + + + CIPHER + Cipher Operation Select. Symmetric Block Cipher algorithm selection or memory operation. + 4 + 3 + + + dis + Disabled. + 0 + + + aes128 + AES 128. + 1 + + + aes192 + AES 192. + 2 + + + aes256 + AES 256. + 3 + + + des + DES. + 4 + + + tdes + Triple DES. + 5 + + + + + MODE + Mode Select. Mode of operation for block cipher or memory operation. DES/TDES cannot be used in CFB, OFB or CTR modes. + 8 + 3 + + + ECB + ECB Mode. + 0 + + + CBC + CBC Mode. + 1 + + + CFB + CFB (AES only). + 2 + + + OFB + OFB (AES only). + 3 + + + CTR + CTR (AES only). + 4 + + + + + HVC + H Vector Computation. + 11 + 1 + read-only + + + DTYPE + GCM/CCM data type. + 12 + 1 + read-only + + + CCMM + CCM M Parameter. + 13 + 3 + read-only + + + CCML + CCM L Parameter. + 16 + 3 + read-only + + + + + HASH_CTRL + HASH Control Register. + 0x08 + + + INIT + Initialize. Initializes hash registers with standard constants. + 0 + 1 + + + nop + No operation/complete. + 0 + + + start + Start operation. + 1 + + + + + XOR + XOR data with IV from cipher block. Useful when calculating HMAC to XOR the input pad and output pad. + 1 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + HASH + Hash function selection. + 2 + 3 + + + dis + Disabled. + 0 + + + sha1 + SHA-1. + 1 + + + sha224 + SHA 224. + 2 + + + sha256 + SHA 256. + 3 + + + sha384 + SHA 384. + 4 + + + sha512 + SHA 512. + 5 + + + + + LAST + Last Message Bit. This bit shall be set along with the HASH_MSG_SZ register prior to hashing the last 512 or 1024-bit block of the message data. It will allow automatic preprocessing of the last message padding, which includes the trailing bit 1, followed by the respective number of zero bits for the last block size and finally the message length represented in bytes. The bit will be automatically cleared at the same time the HASH DONE is set, designating the completion of the last message hash. + 5 + 1 + + + noEffect + No Effect. + 0 + + + lastMsgData + Last Message Data. + 1 + + + + + + + CRC_CTRL + CRC Control Register. + 0x0C + + + CRC + Cyclic Redundancy Check Enable. The CRC cannot be enabled if the PRNG is enabled. + 0 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + MSB + MSB select. This bit selects the order of calculating CRC on data. + 1 + 1 + + + lsbFirst + LSB First. + 0 + + + msbFirst + MSB First. + 1 + + + + + PRNG + Pseudo Random Number Generator Enable. If entropy is disabled, this outputs one byte of pseudo random data per clock cycle. If entropy is enabled, data is output at a rate of one bit per clock cycle. + 2 + 1 + + + ENT + Entropy Enable. If the PRNG is enabled, this mixes the high frequency ring oscillator with the LFSR. If the PRNG is disabled, the raw entropy data is output at a rate of 1 bit per clock. This makes it possible to characterize the quality of the entropy source. + 3 + 1 + + + HAM + Hamming Code Enable. Enable hamming code calculation. + 4 + 1 + + + HRST + Hamming Reset. Reset Hamming code ECC generator for next block. + 5 + 1 + write-only + + write + + reset + Starts reset operation. + 1 + + + + + + + DMA_SRC + Crypto DMA Source Address. + 0x10 + + + ADDR + DMA Source Address. + 0 + 32 + + + + + DMA_DEST + Crypto DMA Destination Address. + 0x14 + + + ADDR + DMA Destination Address. + 0 + 32 + + + + + DMA_CNT + Crypto DMA Byte Count. + 0x18 + + + ADDR + DMA Byte Address. + 0 + 32 + + + + + 4 + 4 + DIN[%s] + Crypto Data Input. Data input can be written to this register instead of using the DMA. This register writes to the FIFO. This register occupies four successive words to allow the use of multi-store instructions. Words can be written to any location, they will be placed in the FIFO in the order they are written. The endian swap input control bit affects this register. + 0x20 + write-only + + + DATA + Crypto Data Input. Input can be written to this register instead of using DMA. + 0 + 32 + + + + + 4 + 4 + DOUT[%s] + Crypto Data Output. Resulting data from cipher calculation. Data is placed in the lower words of these four registers depending on the algorithm. For block cipher modes, this register holds the result of most recent encryption or decryption operation. These registers are affected by the endian swap bits. + 0x30 + read-only + + + DATA + Crypto Data Output. Resulting data from cipher calculation. Data is placed in the lower words of these four registers depending on algorithm. + 0 + 32 + + + + + CRC_POLY + CRC Polynomial. The polynomial to be used for Galois Field calculations (CRC or LFSR) should be written to this register. This register is affected by the MSB control bit. + 0x40 + 0xEDB88320 + + + POLY + CRC Polynomial. The polynomial to be used for Galois Field calculations (CRC or LFSR) should be written to this register. This register is affected by the MSB control bit. + 0 + 32 + + + + + CRC_VAL + CRC Value. This is the state for the Galois Field. This register holds the result of a CRC calculation or the current state of the LFSR. This register is affected by the MSB control bit. + 0x44 + 0xFFFFFFFF + + + VAL + CRC Value. This is the state for the Galois Field. This register holds the result of a CRC calculation or the current state of LFSR. This register is affected by the MSB control bit. + 0 + 32 + + + + + HAM_ECC + Hamming ECC Register. + 0x4C + + + ECC + Hamming ECC Value. These bits are the even parity of their corresponding bit groups. + 0 + 16 + + + PAR + Parity. This is the parity of the entire array. + 16 + 1 + + + even + Even. + 0 + + + odd + Odd. + 1 + + + + + + + 4 + 4 + CIPHER_INIT[%s] + Initial Vector. For block cipher operations that use CBC, CFB, OFB, or CNTR modes, this register holds the initial value. This register is updated with each encryption or decryption operation. This register is affected by the endian swap bits. + 0x50 + + + IVEC + Initial Vector. For block cipher operations that use CBC, CFB, OFB, or CNTR modes, this register holds the initial value. This register is updated with each encryption or decryption operation. This register is affected by the endian swap bits. + 0 + 32 + + + + + 8 + 4 + CIPHER_KEY[%s] + Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter key lengths. This register is affected by the endian swap input control bits. + 0x60 + write-only + + + KEY + Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter kye lengths. This register is affected by the endian swap input control bits. + 0 + 32 + + + + + 16 + 4 + HASH_DIGEST[%s] + This register holds the calculated hash value. This register is affected by the endian swap bits. + 0x80 + + + HASH + This register holds the calculated hash value. This register is affected by the endian swap bits. + 0 + 32 + + + + + 4 + 4 + HASH_MSG_SZ[%s] + Message Size. This register holds the lowest 32-bit of message size in bytes. + 0xC0 + + + MSGSZ + Message Size. This register holds the lowest 32-bit of message size in bytes. + 0 + 32 + + + + + 2 + 4 + AAD_LENGTH[%s] + AAD Length Registers. + 0xD0 + 0x0 + + + LENGTH + AAD length in bytes for AES GCM and CCM operations. + 0 + 32 + + + + + 2 + 4 + PLD_LENGTH[%s] + PLD Length Registers. + 0xD8 + 0x0 + + + LENGTH + PLD length in bytes for AES GCM and CCM operations. + 0 + 32 + + + + + 4 + 4 + TAGMIC[%s] + TAG/MIC Registers. + 0xE0 + + + LENGTH + TAG/MIC output for AES GCM and CCM operations. + 0 + 32 + + + + + SCA_CTRL0 + SCA Control 0 Register. + 0x100 + + + STC + Start Calculation. + 0 + 1 + + + SCAIE + SCA Interrupt Enable. + 1 + 1 + + + disable + Disable + 0 + + + enable + Enable + 1 + + + + + ABORT + Abort Operation. + 2 + 1 + + + ERMEM + Erase Cryptographic Memory. + 4 + 1 + + + MANPARAM + ECC Parameter Source. + 5 + 1 + + + HWKEY + Hardware Key Select. + 6 + 1 + + + OPCODE + SCA Opcode. + 8 + 5 + + + MODADDR + MODULO Address Offset. + 16 + 5 + + + ECCSIZE + ECC Size. + 24 + 2 + + + + + SCA_CTRL1 + SCA Control 1 Register. + 0x104 + + + MAN + SCA Mode. + 0 + 1 + + + auto + Auto Mode + 0 + + + manual + Manual Mode + 1 + + + + + AUTOCARRY + Automatically propagate the carry for the next operation. + 1 + 1 + + + PLUSONE + Enable Carry propagation for the next operation. + 2 + 1 + + + NRNG + NRNG. + 5 + 1 + + + CARRYPOS + To set Carry location. + 8 + 10 + + + + + SCA_STAT + SCA Status Register. + 0x108 + + + BUSY + SCA Busy. + 0 + 1 + + + SCAIF + SCA Interrupt Flag. + 1 + 1 + + + PVF1 + Point 1 Verification Failed. + 2 + 1 + + + PVF2 + Point 2 Verification Failed. + 3 + 1 + + + FSMERR + FSM Transition Error. + 4 + 1 + + + COMPERR + EC Computation Error. + 5 + 1 + + + MEMERR + SCA Memory Access Error. + 6 + 1 + + + CARRY + Carry on ongoing operation. + 8 + 1 + + + GTE2I2 + Modulo 2x Result. + 9 + 1 + + + ALUNEG1 + ALU 2 SubSign of the subtraction result for ALU_2. + 10 + 1 + + + ALUNEG2 + ALU 2 SubSign of the subtraction result for ALU_2. + 11 + 1 + + + + + SCA_PPX_ADDR + PPX Coordinate Data Pointer Register. + 0x10C + 0x0 + + + ADDR + Point P Coordinate Data Pointer. + 0 + 32 + + + + + SCA_PPY_ADDR + PPY Coordinate Data Pointer Register. + 0x110 + 0x0 + + + ADDR + Point P Coordinate Data Pointer. + 0 + 32 + + + + + SCA_PPZ_ADDR + PPZ Coordinate Data Pointer Register. + 0x114 + 0x0 + + + ADDR + Point P Coordinate Data Pointer. + 0 + 32 + + + + + SCA_PQX_ADDR + PQX Coordinate Data Pointer Register. + 0x118 + 0x0 + + + ADDR + Point Q Coordinate Data Pointer. + 0 + 32 + + + + + SCA_PQY_ADDR + PQY Coordinate Data Pointer Register. + 0x11C + 0x0 + + + ADDR + Point Q Coordinate Data Pointer. + 0 + 32 + + + + + SCA_PQZ_ADDR + PQZ Coordinate Data Pointer Register. + 0x120 + 0x0 + + + ADDR + Point Q Coordinate Data Pointer. + 0 + 32 + + + + + SCA_RDSA_ADDR + SCA RDSA Address Register. + 0x124 + 0x0 + + + ADDR + The starting address of the R portion for R, S ECDSA signature. + 0 + 32 + + + + + SCA_RES_ADDR + SCA Result Address Register. + 0x128 + 0x0 + + + ADDR + Starting address of result storage. + 0 + 32 + + + + + SCA_OP_BUFF_ADDR + SCA Operation Buffer Address Register. + 0x12C + 0x0 + + + ADDR + Starting address of operation buffer. + 0 + 32 + + + + + SCA_MODDATA + SCA Modulo Data Input Register. + 0x130 + 0x0 + + + DATA + Used to load the SCA modulo for modular operations. + 0 + 32 + + + + + SCA_NRNG + Starting address for NRNG stored in SRAM. + 0x134 + 0x0 + + + + + + DMA + DMA Controller Fully programmable, chaining capable DMA channels. + 0x40028000 + 32 + + 0x00 + 0x1000 + registers + + + DMA0 + 28 + + + DMA1 + 29 + + + DMA2 + 30 + + + DMA3 + 31 + + + DMA4 + 68 + + + DMA5 + 69 + + + DMA6 + 70 + + + DMA7 + 71 + + + DMA8 + 72 + + + DMA9 + 73 + + + DMA10 + 74 + + + DMA11 + 75 + + + + INTEN + DMA Control Register. + 0x000 + + + CH0 + Channel 0 Interrupt Enable. + 0 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + CH1 + Channel 1 Interrupt Enable. + 1 + 1 + + + CH2 + Channel 2 Interrupt Enable. + 2 + 1 + + + CH3 + Channel 3 Interrupt Enable. + 3 + 1 + + + CH4 + Channel 4 Interrupt Enable. + 4 + 1 + + + CH5 + Channel 5 Interrupt Enable. + 5 + 1 + + + CH6 + Channel 6 Interrupt Enable. + 6 + 1 + + + CH7 + Channel 7 Interrupt Enable. + 7 + 1 + + + + + INTFL + DMA Interrupt Register. + 0x004 + read-only + + + CH0 + Channel Interrupt. To clear an interrupt, all active interrupt bits of the DMA_ST must be cleared. The interrupt bits are set only if their corresponding interrupt enable bits are set in DMA_CN. + 0 + 1 + + + inactive + No interrupt is pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + CH1 + 1 + 1 + + + CH2 + 2 + 1 + + + CH3 + 3 + 1 + + + CH4 + 4 + 1 + + + CH5 + 5 + 1 + + + CH6 + 6 + 1 + + + CH7 + 7 + 1 + + + + + 12 + 0x20 + CH[%s] + DMA Channel registers. + dma_ch + 0x100 + read-write + + CTRL + DMA Channel Control Register. + 0x000 + + + EN + Channel Enable. This bit is automatically cleared when DMA_ST.CH_ST changes from 1 to 0. + 0 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + RLDEN + Reload Enable. Setting this bit to 1 enables DMA_SRC, DMA_DST and DMA_CNT to be reloaded with their corresponding reload registers upon count-to-zero. This bit is also writeable in the Count Reload Register. Refer to the description on Buffer Chaining for use of this bit. If buffer chaining is not used this bit must be written with a 0. This bit should be set after the reload registers have been programmed. + 1 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + PRI + DMA Priority. + 2 + 2 + + + high + Highest Priority. + 0 + + + medHigh + Medium High Priority. + 1 + + + medLow + Medium Low Priority. + 2 + + + low + Lowest Priority. + 3 + + + + + REQUEST + Request Select. Select DMA request line for this channel. If memory-to-memory is selected, the channel operates as if the request is always active. + 4 + 6 + + + MEMTOMEM + Memory To Memory + 0x00 + + + SPI0RX + SPI0 RX + 0x01 + + + SPI1RX + SPI1 RX + 0x02 + + + SPI2RX + SPI2 RX + 0x03 + + + UART0RX + UART0 RX + 0x04 + + + UART1RX + UART1 RX + 0x05 + + + I2C0RX + I2C0 RX + 0x07 + + + I2C1RX + I2C1 RX + 0x08 + + + ADC + ADC + 0x09 + + + I2C2RX + I2C2 RX + 0x0A + + + UART2RX + UART2 RX + 0x0E + + + SPI3RX + SPI3 RX + 0x0F + + + AESRX + AES RX + 0x10 + + + UART3RX + UART3 RX + 0x1C + + + I2SRX + I2S RX + 0x1E + + + SPI0TX + SPI0 TX + 0x21 + + + SPI1TX + SPI1 TX + 0x22 + + + SPI2TX + SPI2 TX + 0x23 + + + UART0TX + UART0 TX + 0x24 + + + UART1TX + UART1 TX + 0x25 + + + I2C0TX + I2C0 TX + 0x27 + + + I2C1TX + I2C1 TX + 0x28 + + + I2C2TX + I2C2 TX + 0x2A + + + CRCTX + CRC TX + 0x2C + + + UART2TX + UART2 TX + 0x2E + + + SPI3TX + SPI3 TX + 0x2F + + + AESTX + AES TX + 0x30 + + + UART3TX + UART3 TX + 0x3C + + + I2STX + I2S TX + 0x3E + + + + + TO_WAIT + Request Wait Enable. When enabled, delay timer start until DMA request transitions from active to inactive. + 10 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + TO_PER + Timeout Period Select. + 11 + 3 + + + to4 + Timeout of 3 to 4 prescale clocks. + 0 + + + to8 + Timeout of 7 to 8 prescale clocks. + 1 + + + to16 + Timeout of 15 to 16 prescale clocks. + 2 + + + to32 + Timeout of 31 to 32 prescale clocks. + 3 + + + to64 + Timeout of 63 to 64 prescale clocks. + 4 + + + to128 + Timeout of 127 to 128 prescale clocks. + 5 + + + to256 + Timeout of 255 to 256 prescale clocks. + 6 + + + to512 + Timeout of 511 to 512 prescale clocks. + 7 + + + + + TO_CLKDIV + Pre-Scale Select. Selects the Pre-Scale divider for timer clock input. + 14 + 2 + + + dis + Disable timer. + 0 + + + div256 + hclk / 256. + 1 + + + div64k + hclk / 64k. + 2 + + + div16M + hclk / 16M. + 3 + + + + + SRCWD + Source Width. In most cases, this will be the data width of each AHB transactions. However, the width will be reduced in the cases where DMA_CNT indicates a smaller value. + 16 + 2 + + + byte + Byte. + 0 + + + halfWord + Halfword. + 1 + + + word + Word. + 2 + + + + + SRCINC + Source Increment Enable. This bit enables DMA_SRC increment upon every AHB transaction. This bit is forced to 0 for DMA receive from peripherals. + 18 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + DSTWD + Destination Width. Indicates the width of the each AHB transactions to the destination peripheral or memory. (The actual width may be less than this if there are insufficient bytes in the DMA FIFO for the full width). + 20 + 2 + + + byte + Byte. + 0 + + + halfWord + Halfword. + 1 + + + word + Word. + 2 + + + + + DSTINC + Destination Increment Enable. This bit enables DMA_DST increment upon every AHB transaction. This bit is forced to 0 for DMA transmit to peripherals. + 22 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + BURST_SIZE + Burst Size. The number of bytes to be transferred into and out of the DMA FIFO in a single burst. Burst size equals 1 + value stored in this field. + 24 + 5 + + + DIS_IE + Channel Disable Interrupt Enable. When enabled, the IPEND will be set to 1 whenever CH_ST changes from 1 to 0. + 30 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + CTZ_IE + Count-to-zero Interrupts Enable. When enabled, the IPEND will be set to 1 whenever a count-to-zero event occurs. + 31 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + + + STATUS + DMA Channel Status Register. + 0x004 + + + STATUS + Channel Status. This bit is used to indicate to the programmer when it is safe to change the configuration, address, and count registers for the channel. Whenever this bit is cleared by hardware, the DMA_CFG.CHEN bit is also cleared (if not cleared already). + 0 + 1 + read-only + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + IPEND + Channel Interrupt. + 1 + 1 + read-only + + + inactive + No interrupt is pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + CTZ_IF + Count-to-Zero (CTZ) Interrupt Flag + 2 + 1 + oneToClear + + + RLD_IF + Reload Event Interrupt Flag. + 3 + 1 + oneToClear + + + BUS_ERR + Bus Error. Indicates that an AHB abort was received and the channel has been disabled. + 4 + 1 + oneToClear + + + TO_IF + Time-Out Event Interrupt Flag. + 6 + 1 + oneToClear + + + + + SRC + Source Device Address. If SRCINC=1, the counter bits are incremented by 1,2, or 4, depending on the data width of each AHB cycle. For peripheral transfers, some or all of the actual address bits are fixed. If SRCINC=0, this register remains constant. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with the contents of DMA_SRC_RLD. + 0x008 + + + ADDR + 0 + 32 + + + + + DST + Destination Device Address. For peripheral transfers, some or all of the actual address bits are fixed. If DSTINC=1, this register is incremented on every AHB write out of the DMA FIFO. They are incremented by 1, 2, or 4, depending on the data width of each AHB cycle. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with DMA_DST_RLD. + 0x00C + + + ADDR + 0 + 32 + + + + + CNT + DMA Counter. The user loads this register with the number of bytes to transfer. This counter decreases on every AHB cycle into the DMA FIFO. The decrement will be 1, 2, or 4 depending on the data width of each AHB cycle. When the counter reaches 0, a count-to-zero condition is triggered. + 0x010 + + + CNT + DMA Counter. + 0 + 24 + + + + + SRCRLD + Source Address Reload Value. The value of this register is loaded into DMA0_SRC upon a count-to-zero condition. + 0x014 + + + ADDR + Source Address Reload Value. + 0 + 31 + + + + + DSTRLD + Destination Address Reload Value. The value of this register is loaded into DMA0_DST upon a count-to-zero condition. + 0x018 + + + ADDR + Destination Address Reload Value. + 0 + 31 + + + + + CNTRLD + DMA Channel Count Reload Register. + 0x01C + + + CNT + Count Reload Value. The value of this register is loaded into DMA0_CNT upon a count-to-zero condition. + 0 + 24 + + + EN + Reload Enable. This bit should be set after the address reload registers have been programmed. This bit is automatically cleared to 0 when reload occurs. + 31 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + + + + + + + FCR + Function Control Register. + 0x40000800 + + 0x00 + 0x400 + registers + + + + FCTRL0 + Register 0. + 0x00 + read-write + + + ERFO_RANGE_SEL + 14MHz-32MHz ERFO Frequency Range Select. + 0 + 3 + + + KEYWIPE_SYS + KEYWIPE_SYS. + 8 + 1 + + + I2C0_SDA_FILTER_EN + I2C0 SDA Glitch Filter Enable. + 20 + 1 + + + dis + Filter disabled. + 0 + + + en + Filter enabled. + 1 + + + + + I2C0_SCL_FILTER_EN + I2C0 SCL Glitch Filter Enable. + 21 + 1 + + + I2C1_SDA_FILTER_EN + I2C1 SDA Glitch Filter Enable. + 22 + 1 + + + I2C1_SCL_FILTER_EN + I2C1 SCL Glitch Filter Enable. + 23 + 1 + + + I2C2_SDA_FILTER_EN + I2C2 SDA Glitch Filter Enable. + 24 + 1 + + + I2C2_SCL_FILTER_EN + I2C2 SCL Glitch Filter Enable. + 25 + 1 + + + + + AUTOCAL0 + Register 1. + 0x04 + read-write + + + SEL + Auto-calibration Enable. + 0 + 1 + + + dis + Disabled. + 0 + + + en + Enabled. + 1 + + + + + EN + Autocalibration Run. + 1 + 1 + + + not + Not Running. + 0 + + + run + Running. + 1 + + + + + LOAD + Load Trim. + 2 + 1 + + + INVERT + Invert Gain. + 3 + 1 + + + not + do Not invert trim step. + 0 + + + invert + Invert trim step. + 1 + + + + + ATOMIC + Atomic mode. + 4 + 1 + + + not + Not Running. + 0 + + + run + Running. + 1 + + + + + GAIN + MU value. + 8 + 12 + + + TRIM + 150MHz HFIO Auto Calibration Trim + 23 + 9 + + + + + AUTOCAL1 + Register 2. + 0x08 + read-write + + + INITIAL + 100MHz IPO Trim Automatic Calibration Initial Trim. + 0 + 9 + + + + + AUTOCAL2 + Register 3. + 0x0C + read-write + + + RUNTIME + 100MHz IPO Trim Automatic Calibration Run Time. + 0 + 8 + + + DIV + 100MHz IPO Trim Automatic Calibration Divide Factor. + 8 + 13 + + + + + TS0 + Register 4. + 0x10 + read-only + + + GAIN + Unsigned gain for temp sensor normalization + 0 + 12 + + + + + TS1 + Register 5. + 0x14 + read-only + + + OFFSET + Signed offset for temp sensor correction + 0 + 32 + + + + + ADCREFTRIM0 + ADC Reference Trim 0 + 0x18 + read-write + + + VREFP + Trimming code for VREFP output of reference buffer + 0 + 7 + + + VREFM + Trimming code for VREFM output of reference buffer + 8 + 7 + + + VCM + Trimming code for VCM output of reference buffer + 16 + 2 + + + VX2_TUNE + Controls tuning capacitor in fine DAC (offset binary) + 24 + 6 + + + + + ADCREFTRIM1 + ADC Reference Trim 1 + 0x1C + read-write + + + VREFP + Trimming code for VREFP output of reference buffer + 0 + 7 + + + VREFM + Trimming code for VREFM output of reference buffer + 8 + 7 + + + VCM + Trimming code for VCM output of reference buffer + 16 + 2 + + + VX2_TUNE + Controls tuning capacitor in fine DAC (offset binary) + 24 + 6 + + + + + ADCREFTRIM2 + ADC Reference Trim 2 + 0x20 + read-write + + + IDRV_1P25 + Trimming code for reference buffer drive strength. 1.25V + 0 + 4 + + + IBOOST_1P25 + Trimming value for extra drive current in reference buffer outputs. 2.048V + 4 + 1 + + + IDRV_2P048 + Trimming code for reference buffer drive strength. 2.048V + 8 + 4 + + + IBOOST_2P048 + Trimming value for extra drive current in reference buffer outputs. 2.048V + 12 + 1 + + + VCM + Trimming code for VCM output of reference buffer + 16 + 2 + + + VX2_TUNE + Controls tuning capacitor in fine DAC (offset binary) + 24 + 6 + + + + + ERFOKS + External Radio Frequency Oscillator Kick Start Control Register. + 0x24 + read-write + + + CTRL + Kickstart Control for ERFO. + 0 + 16 + + + + + + + + FLC + Flash Memory Control. + FLSH_ + 0x40029000 + + 0x00 + 0x400 + registers + + + Flash_Controller + Flash Controller interrupt. + 23 + + + + ADDR + Flash Write Address. + 0x00 + + + ADDR + Address for next operation. + 0 + 32 + + + + + CLKDIV + Flash Clock Divide. The clock (PLL0) is divided by this value to generate a 1 MHz clock for Flash controller. + 0x04 + 0x00000064 + + + CLKDIV + Flash Clock Divide. The clock is divided by this value to generate a 1MHz clock for flash controller. + 0 + 8 + + + + + CTRL + Flash Control Register. + 0x08 + + + WR + Write. This bit is automatically cleared after the operation. + 0 + 1 + + + complete + No operation/complete. + 0 + + + start + Start operation. + 1 + + + + + ME + Mass Erase. This bit is automatically cleared after the operation. + 1 + 1 + + + PGE + Page Erase. This bit is automatically cleared after the operation. + 2 + 1 + + + ERASE_CODE + Erase Code. The ERASE_CODE must be set up property before erase operation can be initiated. These bits are automatically cleared after the operation is complete. + 8 + 8 + + + nop + No operation. + 0 + + + erasePage + Enable Page Erase. + 0x55 + + + eraseAll + Enable Mass Erase. The debug port must be enabled. + 0xAA + + + + + PEND + Flash Pending. When Flash operation is in progress (busy), Flash reads and writes will fail. When PEND is set, write to all Flash registers, with exception of the Flash interrupt register, are ignored. + 24 + 1 + read-only + + + idle + Idle. + 0 + + + busy + Busy. + 1 + + + + + LVE + Low Voltage enable. + 25 + 1 + + + UNLOCK + Flash Unlock. The correct unlock code must be written to these four bits before any Flash write or erase operation is allowed. + 28 + 4 + + + unlocked + Flash Unlocked. + 2 + + + locked + Flash Locked. + 3 + + + + + + + INTR + Flash Interrupt Register. + 0x024 + + + DONE + Flash Done Interrupt. This bit is set to 1 upon Flash write or erase completion. + 0 + 1 + + + inactive + No interrupt is pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + AF + Flash Access Fail. This bit is set when an attempt is made to write the flash while the flash is busy or the flash is locked. This bit can only be set to 1 by hardware. + 1 + 1 + + + noError + No Failure. + 0 + + + error + Failure occurs. + 1 + + + + + DONEIE + Flash Done Interrupt Enable. + 8 + 1 + + + disable + Disable. + 0 + + + enable + Enable. + 1 + + + + + AFIE + 9 + 1 + + + + + ECCDATA + ECC Data Register. + 0x2C + + + EVEN + Error Correction Code Odd Data. + 0 + 9 + + + ODD + Error Correction Code Even Data. + 16 + 9 + + + + + 4 + 4 + DATA[%s] + Flash Write Data. + 0x30 + + + DATA + Data next operation. + 0 + 32 + + + + + ACTRL + Access Control Register. Writing the ACTRL register with the following values in the order shown, allows read and write access to the system and user Information block: + pflc-actrl = 0x3a7f5ca3; + pflc-actrl = 0xa1e34f20; + pflc-actrl = 0x9608b2c1. When unlocked, a write of any word will disable access to system and user information block. Readback of this register is always zero. + 0x40 + write-only + + + ACTRL + Access control. + 0 + 32 + + + + + WELR0 + WELR0 + 0x80 + + + WELR0 + Access control. + 0 + 32 + + + + + WELR1 + WELR1 + 0x88 + + + WELR1 + Access control. + 0 + 32 + + + + + RLR0 + RLR0 + 0x90 + + + RLR0 + Access control. + 0 + 32 + + + + + RLR1 + RLR1 + 0x98 + + + RLR1 + Access control. + 0 + 32 + + + + + + + + FLC1 + Flash Memory Control. 1 + 0x40029400 + + FLC1 + FLC1 IRQ + 87 + + + + + GCR + Global Control Registers. + 0x40000000 + + 0 + 0x400 + registers + + + + SYSCTRL + System Control. + 0x00 + 0xFFFFFFFE + + + SBUSARB + System bus abritration scheme. These bits are used to select between Fixed-burst abritration and Round-Robin scheme. The Round-Robin scheme is selected by default. These bits are reset by the system reset. + 1 + 2 + + + Fix + Fixed Burst abritration. + 0 + + + Round + Round-robin scheme. + 1 + + + + + FLASH_PAGE_FLIP + . + 4 + 1 + + + dis + Physical layout matches logical layout. + 0 + + + en + Bottom half mapped to logical top half and vice versa. + 1 + + + + + FPU_DIS + Cortex M4 Floating Point Disable This bit is used to disable the floating-point unit of the Cortex-M4 + 5 + 1 + + + en + FPU Enabled. + 0 + + + dis + FPU Disabled. + 1 + + + + + ICC0_FLUSH + Internal Cache Controller Flush. This bit is used to flush the code caches and the instruction buffer of the Cortex-M4. + 6 + 1 + + + normal + Normal Code Cache Operation + 0 + + + flush + Code Caches and CPU instruction buffer are flushed + 1 + + + + + CCHK + Compute ROM Checksum. This bit is self-cleared when calculation is completed. Once set, software clearing this bit is ignored and the bit will remain set until the operation is completed. + 13 + 1 + + + complete + No operation/complete. + 0 + + + start + Start operation. + 1 + + + + + SWD_DIS + Serial Wire Debug Disable. This bit is used to disable the serial wire debug interface This bit is only writeable if (FMV lock word is not programmed) or if (ICE lock word is not programmed and the ROM_DONE bit is not set) + + 14 + 1 + + + en + SWD Enabled. + 0 + + + dis + SWD Disabled. + 1 + + + + + CHKRES + ROM Checksum Result. This bit is only valid when CHKRD=1. + 15 + 1 + + + pass + ROM Checksum Correct. + 0 + + + fail + ROM Checksum Fail. + 1 + + + + + + + RST0 + Reset. + 0x04 + + + DMA + DMA Reset. + 0 + 1 + + reset + read-write + + reset_done + Reset complete. + 0 + + + busy + Starts Reset or indicates reset in progress. + 1 + + + + + WDT0 + Watchdog Timer Reset. + 1 + 1 + + + GPIO0 + GPIO0 Reset. Setting this bit to 1 resets GPIO0 pins to their default states. + 2 + 1 + + + GPIO1 + GPIO1 Reset. Setting this bit to 1 resets GPIO1 pins to their default states. + 3 + 1 + + + TMR0 + Timer0 Reset. Setting this bit to 1 resets Timer 0 blocks. + 5 + 1 + + + TMR1 + Timer1 Reset. Setting this bit to 1 resets Timer 1 blocks. + 6 + 1 + + + TMR2 + Timer2 Reset. Setting this bit to 1 resets Timer 2 blocks. + 7 + 1 + + + TMR3 + Timer3 Reset. Setting this bit to 1 resets Timer 3 blocks. + 8 + 1 + + + UART0 + UART0 Reset. Setting this bit to 1 resets all UART 0 blocks. + 11 + 1 + + + UART1 + UART1 Reset. Setting this bit to 1 resets all UART 1 blocks. + 12 + 1 + + + SPI0 + SPI0 Reset. Setting this bit to 1 resets all SPI 0 blocks. + 13 + 1 + + + SPI1 + SPI1 Reset. Setting this bit to 1 resets all SPI 1 blocks. + 14 + 1 + + + SPI2 + SPI2 Reset. Setting this bit to 1 resets all SPI 1 blocks. + 15 + 1 + + + I2C0 + I2C0 Reset. + 16 + 1 + + + CTB + Crypto Toolbox Reset. + 18 + 1 + + + TRNG + TRNG Reset. + 24 + 1 + + + ADC + ADC Reset. + 26 + 1 + + + UART2 + UART2 Reset. Setting this bit to 1 resets all UART 2 blocks. + 28 + 1 + + + SOFT + Soft Reset. Setting this bit to 1 resets everything except the CPU and the watchdog timer. + 29 + 1 + + + PERIPH + Peripheral Reset. Setting this bit to 1 resets all peripherals. The CPU core, the watchdog timer, and all GPIO pins are unaffected by this reset. + 30 + 1 + + + SYS + System Reset. Setting this bit to 1 resets the CPU core and all peripherals, including the watchdog timer. + 31 + 1 + + + + + CLKCTRL + Clock Control. + 0x08 + 0x00000008 + + + SYSCLK_DIV + Prescaler Select. This 3 bit field sets the system operating frequency by controlling the prescaler that divides the output of the PLL0. + 6 + 3 + + + div1 + Divide by 1. + 0 + + + div2 + Divide by 2. + 1 + + + div4 + Divide by 4. + 2 + + + div8 + Divide by 8. + 3 + + + div16 + Divide by 16. + 4 + + + div32 + Divide by 32. + 5 + + + div64 + Divide by 64. + 6 + + + div128 + Divide by 128. + 7 + + + + + SYSCLK_SEL + Clock Source Select. This 3 bit field selects the source for the system clock. + 9 + 3 + + + ERFO + 32MHz Crystal is used for the system clock. + 2 + + + INRO + 80kHz LIRC is used for the system clock. + 3 + + + IPO + The internal 96 MHz oscillator is used for the system clock. + 4 + + + IBRO + The internal 8 MHz oscillator is used for the system clock. + 5 + + + ERTCO + 32kHz is used for the system clock. + 6 + + + EXTCLK + External clock on gpio0 28 (AF4). + 7 + + + + + SYSCLK_RDY + Clock Ready. This read only bit reflects whether the currently selected system clock source is running. + 13 + 1 + read-only + + + busy + Switchover to the new clock source (as selected by CLKSEL) has not yet occurred. + 0 + + + ready + System clock running from CLKSEL clock source. + 1 + + + + + IPO_DIV + Divides the HIRC96M clock before the system clock prescaler, will affect HIRC96M Autocalibration. + 14 + 2 + + + div1 + divide clock by 1 + 0 + + + div2 + divide clock by 2 + 1 + + + div4 + divide clock by 4 + 2 + + + div8 + divide clock by 8 + 3 + + + + + ERFO_EN + 32MHz Crystal Oscillator Enable. + 16 + 1 + + + dis + Is Disabled. + 0 + + + en + Is Enabled. + 1 + + + + + IPO_EN + 96MHz High Frequency Internal Reference Clock Enable. + 19 + 1 + + + IBRO_EN + 8MHz High Frequency Internal Reference Clock Enable. + 20 + 1 + + + IBRO_VS + 8MHz High Frequency Internal Reference Clock Voltage Select. This register bit is used to select the power supply to the HIRC8M. + 21 + 1 + + + 1V + Dedicated 1v regulated supply. + 0 + + + Vcor + VCore Supply + 1 + + + + + ERFO_RDY + 32MHz Crystal Oscillator Ready + 24 + 1 + read-only + + + busy + Is not Ready. + 0 + + + ready + Is Ready. + 1 + + + + + ERTCO_RDY + 32kHz Crystal Oscillator Ready + 25 + 1 + read-only + + + busy + Is not Ready. + 0 + + + ready + Is Ready. + 1 + + + + + IPO_RDY + 96MHz HIRC Ready. + 27 + 1 + + + IBRO_RDY + 8MHz HIRC Ready. + 28 + 1 + + + INRO_RDY + 8kHz Low Frequency Reference Clock Ready. + 29 + 1 + + + EXTCLK_RDY + External Clock (GPIO0[11] AF2) + 31 + 1 + + + + + PM + Power Management. + 0x0C + + + MODE + Operating Mode. This three bit field selects the current operating mode for the device. Note that code execution only occurs during ACTIVE mode. + 0 + 3 + + + active + Active Mode. + 0 + + + shutdown + Shutdown Mode. + 3 + + + backup + Backup Mode. + 4 + + + + + GPIO_WE + GPIO Wake Up Enable. This bit enables all GPIO pins as potential wakeup sources. Any GPIO configured for wakeup is capable of causing an exit from IDLE or STANDBY modes when this bit is set. + 4 + 1 + + + dis + Wake Up Disable. + 0 + + + en + Wake Up Enable. + 1 + + + + + RTC_WE + RTC Alarm Wake Up Enable. This bit enables RTC alarm as wakeup source. If enabled, the desired RTC alarm must be configured via the RTC control registers. + 5 + 1 + + + LPTMR0_WE + TIMER4 Wake Up Enable. This bit enables TIMER4 as wakeup source. + 6 + 1 + + + LPTMR1_WE + TIMER5 Wake Up Enable. This bit enables TIMER5 as wakeup source. + 7 + 1 + + + LPUART0_WE + LPUART3 Wake Up Enable. This bit enables LPUART3 as wakeup source. + 8 + 1 + + + AINCOMP_WE + AINCOMP Wake Up Enable. This bit enables AINCOMP as wakeup source. + 9 + 1 + + + ERFO_PD + 32MHz power down. This bit selects 32MHz Crystal power state in DEEPSLEEP mode. + 12 + 1 + + + active + Mode is Active. + 0 + + + deepsleep + Powered down in DEEPSLEEP. + 1 + + + + + IPO_PD + 96MHz power down. This bit selects 96MHz HIRC power state in DEEPSLEEP mode. + 16 + 1 + + + IBRO_PD + 8MHz power down. This bit selects 8MHz HIRC power state in DEEPSLEEP mode. + 17 + 1 + + + ERFO_BP + 32MHz Oscillator Bypass + 20 + 1 + + + dis + Bypass Disabled. + 0 + + + en + Bypass Enabled. + 1 + + + + + + + PCLKDIV + Peripheral Clock Divider. + 0x18 + 0x00000001 + + + AON_CLKDIV + Always-ON (AON) domain Clock Divider. These bits define the AON domain clock divider + 0 + 3 + + + div4 + 0 + + + div8 + 1 + + + div16 + 2 + + + div32 + 3 + + + + + DIV_CLK_OUT_CTRL + DIV_CLK_OUT Control + 14 + 2 + + + off + HART clock off. + 0 + + + div2 + HART clock HIRC8M Div 2. + 1 + + + div4 + HART clock XO32M Div 4. + 2 + + + div8 + HART clock XO32M Div 8. + 3 + + + + + DIV_CLK_OUT_EN + DIV_CLK_OUT Enable + 16 + 1 + + + dis + HART clock Disable. + 0 + + + en + HART clock Enable. + 1 + + + + + + + PCLKDIS0 + Peripheral Clock Disable. + 0x24 + + + GPIO0 + GPIO0 Disable. + 0 + 1 + + + en + enable it. + 0 + + + dis + disable it. + 1 + + + + + GPIO1 + GPIO1 Disable. + 1 + 1 + + + DMA + DMA Disable. + 5 + 1 + + + SPI0 + SPI 0 Disable. + 6 + 1 + + + SPI1 + SPI 1 Disable. + 7 + 1 + + + SPI2 + SPI 2 Disable. + 8 + 1 + + + UART0 + UART 0 Disable. + 9 + 1 + + + UART1 + UART 1 Disable. + 10 + 1 + + + I2C0 + I2C 0 Disable. + 13 + 1 + + + CTB + Crypto Disable. + 14 + 1 + + + TMR0 + Timer 0 Disable. + 15 + 1 + + + TMR1 + Timer 1 Disable. + 16 + 1 + + + TMR2 + Timer 2 Disable. + 17 + 1 + + + TMR3 + Timer 3 Disable. + 18 + 1 + + + ADC + ADC Clock Disable. + 23 + 1 + + + I2C1 + I2C 1 Disable. + 28 + 1 + + + + + MEMCTRL + Memory Clock Control Register. + 0x28 + + + FWS + Flash Wait State. These bits define the number of wait-state cycles per Flash data read access. Minimum wait state is 2. + 0 + 3 + + + RAMWS_EN + System RAM Wait State enable + 4 + 1 + + + no + no SRAM wait state. + 0 + + + en + SRAM wait state enabled. + 1 + + + + + RAM0LS_EN + System RAM 0 Light Sleep Mode. + 8 + 1 + + + active + RAM is active. + 0 + + + light_sleep + RAM is in Light Sleep mode. + 1 + + + + + RAM1LS_EN + System RAM 1 Light Sleep Mode. + 9 + 1 + + + RAM2LS_EN + System RAM 2 Light Sleep Mode. + 10 + 1 + + + RAM3LS_EN + System RAM 3 Light Sleep Mode. + 11 + 1 + + + ICC0LS_EN + ICache RAM Light Sleep Mode. + 12 + 1 + + + ROMLS_EN + ROM Light Sleep Mode. + 13 + 1 + + + + + MEMZ + Memory Zeroize Control. + 0x2C + + + RAM0 + System RAM 0 Block. + 0 + 1 + + + nop + No operation/complete. + 0 + + + start + Start operation. + 1 + + + + + RAM1 + System RAM 1 zeroization. + 1 + 1 + + + RAM2 + System RAM 2 zeroization. + 2 + 1 + + + RAMCB + System RAM check bit zeroization. + 3 + 1 + + + ICC0 + Instruction Cache. + 4 + 1 + + + + + SYSST + System Status Register. + 0x40 + + + ICELOCK + ARM ICE Lock Status. + 0 + 1 + + + unlocked + ICE is unlocked. + 0 + + + locked + ICE is locked. + 1 + + + + + + + RST1 + Reset 1. + 0x44 + + + I2C1 + I2C1 Reset. + 0 + 1 + + + reset + Reset. + 1 + + + reset_done + Reset complete. + 0 + + + + + WDT1 + WDT1 Reset. + 8 + 1 + + + AES + WDT1 Reset. + 10 + 1 + + + AC + AC Reset. + 14 + 1 + + + I2C2 + I2C2 Reset. + 17 + 1 + + + I2S + I2S Reset. + 23 + 1 + + + QDEC + QDEC Reset. + 25 + 1 + + + + + PCLKDIS1 + Peripheral Clock Disable. + 0x48 + + + UART2 + UART2 Disable. + 1 + 1 + + + en + Enable. + 0 + + + dis + Disable. + 1 + + + + + TRNG + TRNG Disable. + 2 + 1 + + + WDT0 + WDT0 Disable. + 4 + 1 + + + WDT1 + WDT1 Disable. + 5 + 1 + + + ICC0 + ICACHE Disable. + 11 + 1 + + + AES + AES Clock Disable. + 15 + 1 + + + I2C2 + I2C2 Disable. + 21 + 1 + + + I2S + I2S Clock Disable. + 23 + 1 + + + QDEC + Quadrature Decoder Interface Clock Disable. + 25 + 1 + + + + + EVENTEN + Event Enable Register. + 0x4C + + + DMA + Enable DMA event. When this bit is set, a DMA event will cause an RXEV event to wake the CPU from WFE sleep mode. + 0 + 1 + + + dis + Event Disable. + 0 + + + en + Event Enable. + 1 + + + + + RX + Enable RXEV pin event. When this bit is set, a logic high of GPIO0[20] (AF1) will cause an RXEV event to wake the CPU from WFE sleep mode. + 1 + 1 + + + dis + Event Disable. + 0 + + + en + Event Enable. + 1 + + + + + TX + Enable TXEV pin event. When this bit is set, TXEV event from the CPU is output to GPIO[21] (AF1). + 2 + 1 + + + dis + Event Disable. + 0 + + + en + Event Enable. + 1 + + + + + + + REVISION + Revision Register. + 0x50 + read-only + + + REVISION + Manufacturer Chip Revision. + 0 + 16 + + + + + SYSIE + System Status Interrupt Enable Register. + 0x54 + + + ICEUNLOCK + ARM ICE Unlock Interrupt Enable. + 0 + 1 + + + dis + disabled. + 0 + + + en + enabled. + 1 + + + + + + + ECCERR + ECC Error Register + 0x64 + + + RAM0_1 + ECC System RAM0 and RAM1 Error Flag. Write 1 to clear. + 0 + 1 + + + RAM2 + ECC System RAM2 Error Flag. Write 1 to clear. + 1 + 1 + + + RAM3 + ECC System RAM3 Error Flag. Write 1 to clear. + 2 + 1 + + + ICC0 + ECC Icache Error Flag. Write 1 to clear. + 3 + 1 + + + FLASH0 + ECC Flash0 Error Flag. Write 1 to clear. + 4 + 1 + + + FLASH1 + ECC Flash1 Error Flag. Write 1 to clear. + 5 + 1 + + + + + ECCCED + ECC Correctable Error Detect Register + 0x68 + + + RAM0_1 + ECC System RAM0 and RAM1 Error Flag. Write 1 to clear. + 0 + 1 + + + RAM2 + ECC System RAM2 Error Flag. Write 1 to clear. + 1 + 1 + + + RAM3 + ECC System RAM3 Error Flag. Write 1 to clear. + 2 + 1 + + + ICC0 + ECC Icache Error Flag. Write 1 to clear. + 3 + 1 + + + FLASH0 + ECC Flash0 Error Flag. Write 1 to clear. + 4 + 1 + + + FLASH1 + ECC Flash1 Error Flag. Write 1 to clear. + 5 + 1 + + + + + ECCIE + ECC IRQ Enable Register + 0x6C + + + RAM0_1 + ECC System RAM0 and RAM1 Error interrupt enable. + 0 + 1 + + + dis + interrupt disabled. + 0 + + + en + interrupt enabled. + 1 + + + + + RAM2 + ECC System RAM2 Error interrupt enable. + 1 + 1 + + + RAM3 + ECC System RAM3 Error interrupt enable. + 2 + 1 + + + ICC0 + ECC Icache Error interrupt enable. + 3 + 1 + + + FLASH0 + ECC Flash0 Error interrupt enable. + 4 + 1 + + + FLASH1 + ECC Flash1 Error interrupt enable. + 5 + 1 + + + + + ECCADDR + ECC Error Address Register + 0x70 + + + DATARAMADDR + ECC Error Address/TAG RAM Error Address. + 0 + 14 + + + DATARAMBANK + ECC Error Address/DATA RAM Error Bank. + 14 + 1 + + + DATARAMERR + ECC Error Address/DATA RAM Error Address. + 15 + 1 + + + TAGRAMADDR + ECC Error Address/TAG RAM Error Address. + 16 + 14 + + + TAGRAMBANK + ECC Error Address/TAG RAM Error Bank. + 30 + 1 + + + TAGRAMERR + ECC Error Address/TAG RAM Error. + 31 + 1 + + + + + + + + GPIO0 + Individual I/O for each GPIO + GPIO + 0x40008000 + + 0x00 + 0x1000 + registers + + + GPIO0 + GPIO0 interrupt. + 24 + + + + EN0 + GPIO Function Enable Register. Each bit controls the GPIO_EN setting for one GPIO pin on the associated port. + 0x00 + + + GPIO_EN + Mask of all of the pins on the port. + 0 + 32 + + + ALTERNATE + Alternate function enabled. + 0 + + + GPIO + GPIO function is enabled. + 1 + + + + + + + EN0_SET + GPIO Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN to 1, without affecting other bits in that register. + 0x04 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + EN0_CLR + GPIO Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN to 0, without affecting other bits in that register. + 0x08 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + OUTEN + GPIO Output Enable Register. Each bit controls the GPIO_OUT_EN setting for one GPIO pin in the associated port. + 0x0C + + + EN + Mask of all of the pins on the port. + 0 + 32 + + + dis + GPIO Output Disable + 0 + + + en + GPIO Output Enable + 1 + + + + + + + OUTEN_SET + GPIO Output Enable Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT_EN to 1, without affecting other bits in that register. + 0x10 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + OUTEN_CLR + GPIO Output Enable Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT_EN to 0, without affecting other bits in that register. + 0x14 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + OUT + GPIO Output Register. Each bit controls the GPIO_OUT setting for one pin in the associated port. This register can be written either directly, or by using the GPIO_OUT_SET and GPIO_OUT_CLR registers. + 0x18 + + + GPIO_OUT + Mask of all of the pins on the port. + 0 + 32 + + + low + Drive Logic 0 (low) on GPIO output. + 0 + + + high + Drive logic 1 (high) on GPIO output. + 1 + + + + + + + OUT_SET + GPIO Output Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT to 1, without affecting other bits in that register. + 0x1C + write-only + + + GPIO_OUT_SET + Mask of all of the pins on the port. + 0 + 32 + + + no + No Effect. + 0 + + + set + Set GPIO_OUT bit in this position to '1' + 1 + + + + + + + OUT_CLR + GPIO Output Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT to 0, without affecting other bits in that register. + 0x20 + write-only + + + GPIO_OUT_CLR + Mask of all of the pins on the port. + 0 + 32 + + + + + IN + GPIO Input Register. Read-only register to read from the logic states of the GPIO pins on this port. + 0x24 + read-only + + + GPIO_IN + Mask of all of the pins on the port. + 0 + 32 + + + + + INTMODE + GPIO Interrupt Mode Register. Each bit in this register controls the interrupt mode setting for the associated GPIO pin on this port. + 0x28 + + + GPIO_INTMODE + Mask of all of the pins on the port. + 0 + 32 + + + level + Interrupts for this pin are level triggered. + 0 + + + edge + Interrupts for this pin are edge triggered. + 1 + + + + + + + INTPOL + GPIO Interrupt Polarity Register. Each bit in this register controls the interrupt polarity setting for one GPIO pin in the associated port. + 0x2C + + + GPIO_INTPOL + Mask of all of the pins on the port. + 0 + 32 + + + falling + Interrupts are latched on a falling edge or low level condition for this pin. + 0 + + + rising + Interrupts are latched on a rising edge or high condition for this pin. + 1 + + + + + + + INEN + GPIO Input Enable + 0x30 + + + INTEN + GPIO Interrupt Enable Register. Each bit in this register controls the GPIO interrupt enable for the associated pin on the GPIO port. + 0x34 + + + GPIO_INTEN + Mask of all of the pins on the port. + 0 + 32 + + + dis + Interrupts are disabled for this GPIO pin. + 0 + + + en + Interrupts are enabled for this GPIO pin. + 1 + + + + + + + INTEN_SET + GPIO Interrupt Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_INT_EN to 1, without affecting other bits in that register. + 0x38 + + + GPIO_INTEN_SET + Mask of all of the pins on the port. + 0 + 32 + + + no + No effect. + 0 + + + set + Set GPIO_INT_EN bit in this position to '1' + 1 + + + + + + + INTEN_CLR + GPIO Interrupt Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_EN to 0, without affecting other bits in that register. + 0x3C + + + GPIO_INTEN_CLR + Mask of all of the pins on the port. + 0 + 32 + + + no + No Effect. + 0 + + + clear + Clear GPIO_INT_EN bit in this position to '0' + 1 + + + + + + + INTFL + GPIO Interrupt Status Register. Each bit in this register contains the pending interrupt status for the associated GPIO pin in this port. + 0x40 + read-only + + + GPIO_INTFL + Mask of all of the pins on the port. + 0 + 32 + + + no + No Interrupt is pending on this GPIO pin. + 0 + + + pending + An Interrupt is pending on this GPIO pin. + 1 + + + + + + + INTFL_CLR + GPIO Status Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_STAT to 0, without affecting other bits in that register. + 0x48 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + WKEN + GPIO Wake Enable Register. Each bit in this register controls the PMU wakeup enable for the associated GPIO pin in this port. + 0x4C + + + GPIO_WKEN + Mask of all of the pins on the port. + 0 + 32 + + + dis + PMU wakeup for this GPIO is disabled. + 0 + + + en + PMU wakeup for this GPIO is enabled. + 1 + + + + + + + WKEN_SET + GPIO Wake Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_WAKE_EN to 1, without affecting other bits in that register. + 0x50 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + WKEN_CLR + GPIO Wake Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_WAKE_EN to 0, without affecting other bits in that register. + 0x54 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + DUALEDGE + GPIO Interrupt Dual Edge Mode Register. Each bit in this register selects dual edge mode for the associated GPIO pin in this port. + 0x5C + + + GPIO_DUALEDGE + Mask of all of the pins on the port. + 0 + 32 + + + no + No Effect. + 0 + + + en + Dual Edge mode is enabled. If edge-triggered interrupts are enabled on this GPIO pin, then both rising and falling edges will trigger interrupts regardless of the GPIO_INT_POL setting. + 1 + + + + + + + PADCTRL0 + GPIO Input Mode Config 1. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port. + 0x60 + + + GPIO_PADCTRL0 + The two bits in GPIO_PAD_CFG1 and GPIO_PAD_CFG2 for each GPIO pin work together to determine the pad mode when the GPIO is set to input mode. + 0 + 32 + + + impedance + High Impedance. + 0 + + + pu + Weak pull-up mode. + 1 + + + pd + weak pull-down mode. + 2 + + + + + + + PADCTRL1 + GPIO Input Mode Config 2. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port. + 0x64 + + + GPIO_PADCTRL1 + The two bits in GPIO_PAD_CFG1 and GPIO_PAD_CFG2 for each GPIO pin work together to determine the pad mode when the GPIO is set to input mode. + 0 + 32 + + + impedance + High Impedance. + 0 + + + pu + Weak pull-up mode. + 1 + + + pd + weak pull-down mode. + 2 + + + + + + + EN1 + GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port. + 0x68 + + + GPIO_EN1 + Mask of all of the pins on the port. + 0 + 32 + + + primary + Primary function selected. + 0 + + + secondary + Secondary function selected. + 1 + + + + + + + EN1_SET + GPIO Alternate Function Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN1 to 1, without affecting other bits in that register. + 0x6C + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + EN1_CLR + GPIO Alternate Function Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN1 to 0, without affecting other bits in that register. + 0x70 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + EN2 + GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port. + 0x74 + + + GPIO_EN2 + Mask of all of the pins on the port. + 0 + 32 + + + primary + Primary function selected. + 0 + + + secondary + Secondary function selected. + 1 + + + + + + + EN2_SET + GPIO Alternate Function 2 Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN2 to 1, without affecting other bits in that register. + 0x78 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + EN2_CLR + GPIO Wake Alternate Function Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN2 to 0, without affecting other bits in that register. + 0x7C + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + HYSEN + GPIO Input Hysteresis Enable. + 0xA8 + + + GPIO_HYSEN + Mask of all of the pins on the port. + 0 + 32 + + + + + SRSEL + GPIO Slew Rate Enable Register. + 0xAC + + + GPIO_SRSEL + Mask of all of the pins on the port. + 0 + 32 + + + FAST + Fast Slew Rate selected. + 0 + + + SLOW + Slow Slew Rate selected. + 1 + + + + + + + DS0 + GPIO Drive Strength Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode. + 0xB0 + + + GPIO_DS0 + Mask of all of the pins on the port. + 0 + 32 + + + ld + GPIO port pin is in low-drive mode. + 0 + + + hd + GPIO port pin is in high-drive mode. + 1 + + + + + + + DS1 + GPIO Drive Strength 1 Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode. + 0xB4 + + + GPIO_DS1 + Mask of all of the pins on the port. + 0 + 32 + + + + + PS + GPIO Pull Select Mode. + 0xB8 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + VSSEL + GPIO Voltage Select. + 0xC0 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + + + + GPIO1 + Individual I/O for each GPIO 1 + 0x40009000 + + GPIO1 + GPIO1 IRQ + 25 + + + + + I2C0 + Inter-Integrated Circuit. + I2C + 0x4001D000 + 32 + + 0x00 + 0x1000 + registers + + + I2C0 + I2C0 IRQ + 13 + + + + CTRL + Control Register0. + 0x00 + + + EN + I2C Enable. + [0:0] + read-write + + + dis + Disable I2C. + 0 + + + en + enable I2C. + 1 + + + + + MST_MODE + Master Mode Enable. + [1:1] + read-write + + + slave_mode + Slave Mode. + 0 + + + master_mode + Master Mode. + 1 + + + + + GC_ADDR_EN + General Call Address Enable. + [2:2] + read-write + + + dis + Ignore Gneral Call Address. + 0 + + + en + Acknowledge general call address. + 1 + + + + + IRXM_EN + Interactive Receive Mode. + [3:3] + read-write + + + dis + Disable Interactive Receive Mode. + 0 + + + en + Enable Interactive Receive Mode. + 1 + + + + + IRXM_ACK + Data Acknowledge. This bit defines the acknowledge bit returned by the I2C receiver while IRXM = 1 HW forces ACK to 0 when IRXM = 0. + [4:4] + read-write + + + ack + return ACK (pulling SDA LOW). + 0 + + + nack + return NACK (leaving SDA HIGH). + 1 + + + + + SCL_OUT + SCL Output. This bits control SCL output when SWOE =1. + [6:6] + read-write + + + drive_scl_low + Drive SCL low. + 0 + + + release_scl + Release SCL. + 1 + + + + + SDA_OUT + SDA Output. This bits control SDA output when SWOE = 1. + [7:7] + read-write + + + drive_sda_low + Drive SDA low. + 0 + + + release_sda + Release SDA. + 1 + + + + + SCL + SCL status. This bit reflects the logic gate of SCL signal. + [8:8] + read-only + + + SDA + SDA status. THis bit reflects the logic gate of SDA signal. + [9:9] + read-only + + + BB_MODE + Software Output Enable. + [10:10] + read-write + + + outputs_disable + I2C Outputs SCLO and SDAO disabled. + 0 + + + outputs_enable + I2C Outputs SCLO and SDAO enabled. + 1 + + + + + READ + Read. This bit reflects the R/W bit of an address match (AMI = 1) or general call match (GCI = 1). This bit is valid 3 cycles after the relevant interrupt bit is set. + [11:11] + read-only + + + write + Write. + 0 + + + read + Read. + 1 + + + + + CLKSTR_DIS + This bit will disable slave clock stretching when set. + [12:12] + read-write + + + en + Slave clock stretching enabled. + 0 + + + dis + Slave clock stretching disabled. + 1 + + + + + ONE_MST_MODE + SCL Push-Pull Mode. This bit controls whether SCL is operated in a the I2C standard open-drain mode, or in a non-standard push-pull mode where the Hi-Z output isreplaced with Drive-1. The non-standard mode should only be used when operating as a master and communicating with slaves that are guaranteed to never drive SCL low. + [13:13] + read-write + + + dis + Standard open-drain operation: + drive low for 0, Hi-Z for 1 + 0 + + + en + Non-standard push-pull operation: + drive low for 0, drive high for 1 + 1 + + + + + HS_EN + High speed mode enable + [15:15] + read-write + + + + + STATUS + Status Register. + 0x04 + + + BUSY + Bus Status. + [0:0] + read-only + + + idle + I2C Bus Idle. + 0 + + + busy + I2C Bus Busy. + 1 + + + + + RX_EM + RX empty. + [1:1] + read-only + + + not_empty + Not Empty. + 0 + + + empty + Empty. + 1 + + + + + RX_FULL + RX Full. + [2:2] + read-only + + + not_full + Not Full. + 0 + + + full + Full. + 1 + + + + + TX_EM + TX Empty. + [3:3] + + + not_empty + Not Empty. + 0 + + + empty + Empty. + 1 + + + + + TX_FULL + TX Full. + [4:4] + + + not_empty + Not Empty. + 0 + + + empty + Empty. + 1 + + + + + MST_BUSY + Clock Mode. + [5:5] + read-only + + + not_actively_driving_scl_clock + Device not actively driving SCL clock cycles. + 0 + + + actively_driving_scl_clock + Device operating as master and actively driving SCL clock cycles. + 1 + + + + + + + INTFL0 + Interrupt Status Register. + 0x08 + + + DONE + Transfer Done Interrupt. + [0:0] + + INT_FL0_Done + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + IRXM + Interactive Receive Interrupt. + [1:1] + + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + GC_ADDR_MATCH + Slave General Call Address Match Interrupt. + [2:2] + + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + ADDR_MATCH + Slave Address Match Interrupt. + [3:3] + + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + RX_THD + Receive Threshold Interrupt. This bit is automaticcaly cleared when RX_FIFO is below the threshold level. + [4:4] + + + inactive + No interrupt is pending. + 0 + + + pending + An interrupt is pending. RX_FIFO equal or more bytes than the threshold. + 1 + + + + + TX_THD + Transmit Threshold Interrupt. This bit is automaticcaly cleared when TX_FIFO is above the threshold level. + [5:5] + + + inactive + No interrupt is pending. + 0 + + + pending + An interrupt is pending. TX_FIFO has equal or less bytes than the threshold. + 1 + + + + + STOP + STOP Interrupt. + [6:6] + + + inactive + No interrupt is pending. + 0 + + + pending + An interrupt is pending. TX_FIFO has equal or less bytes than the threshold. + 1 + + + + + ADDR_ACK + Address Acknowledge Interrupt. + [7:7] + + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + ARB_ERR + Arbritation error Interrupt. + [8:8] + + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + TO_ERR + timeout Error Interrupt. + [9:9] + + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + ADDR_NACK_ERR + Address NACK Error Interrupt. + [10:10] + + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + DATA_ERR + Data NACK Error Interrupt. + [11:11] + + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + DNR_ERR + Do Not Respond Error Interrupt. + [12:12] + + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + START_ERR + Start Error Interrupt. + [13:13] + + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + STOP_ERR + Stop Error Interrupt. + [14:14] + + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + TX_LOCKOUT + Transmit Lock Out Interrupt. + [15:15] + + + MAMI + Multiple Address Match Interrupt + [21:16] + + + RD_ADDR_MATCH + Slave Read Address Match Interrupt + [22:22] + + + WR_ADDR_MATCH + Slave Write Address Match Interrupt + [23:23] + + + + + INTEN0 + Interrupt Enable Register. + 0x0C + read-write + + + DONE + Transfer Done Interrupt Enable. + [0:0] + read-write + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled when DONE = 1. + 1 + + + + + IRXM + Description not available. + [1:1] + read-write + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled when RX_MODE = 1. + 1 + + + + + GC_ADDR_MATCH + Slave mode general call address match received input enable. + [2:2] + read-write + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled when GEN_CTRL_ADDR = 1. + 1 + + + + + ADDR_MATCH + Slave mode incoming address match interrupt. + [3:3] + read-write + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled when ADDR_MATCH = 1. + 1 + + + + + RX_THD + RX FIFO Above Treshold Level Interrupt Enable. + [4:4] + read-write + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled. + 1 + + + + + TX_THD + TX FIFO Below Treshold Level Interrupt Enable. + [5:5] + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled. + 1 + + + + + STOP + Stop Interrupt Enable + [6:6] + read-write + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled when STOP = 1. + 1 + + + + + ADDR_ACK + Received Address ACK from Slave Interrupt. + [7:7] + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled. + 1 + + + + + ARB_ERR + Master Mode Arbitration Lost Interrupt. + [8:8] + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled. + 1 + + + + + TO_ERR + Timeout Error Interrupt Enable. + [9:9] + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled. + 1 + + + + + ADDR_NACK_ERR + Master Mode Address NACK Received Interrupt. + [10:10] + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled. + 1 + + + + + DATA_ERR + Master Mode Data NACK Received Interrupt. + [11:11] + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled. + 1 + + + + + DNR_ERR + Slave Mode Do Not Respond Interrupt. + [12:12] + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled. + 1 + + + + + START_ERR + Out of Sequence START condition detected interrupt. + [13:13] + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled. + 1 + + + + + STOP_ERR + Out of Sequence STOP condition detected interrupt. + [14:14] + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled. + 1 + + + + + TX_LOCKOUT + TX FIFO Locked Out Interrupt. + [15:15] + + + MAMI + Multiple Address Match Interrupt + [21:16] + + + RD_ADDR_MATCH + Slave Read Address Match Interrupt + [22:22] + + + WR_ADDR_MATCH + Slave Write Address Match Interrupt + [23:23] + + + + + INTFL1 + Interrupt Status Register 1. + 0x10 + + + RX_OV + Receiver Overflow Interrupt. When operating as a slave receiver, this bit is set when you reach the first data bit and the RX FIFO and shift register are both full. + [0:0] + + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + TX_UN + Transmit Underflow Interrupt. When operating as a slave transmitter, this bit is set when you reach the first data bit and the TX FIFO is empty and the master is still asking for more data (i.e the master hasn't sent a NACK yet). + [1:1] + + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + START + START Condition Status Flag. + [2:2] + + + + + INTEN1 + Interrupt Staus Register 1. + 0x14 + read-write + + + RX_OV + Receiver Overflow Interrupt Enable. + [0:0] + + + dis + No Interrupt is Pending. + 0 + + + en + An interrupt is pending. + 1 + + + + + TX_UN + Transmit Underflow Interrupt Enable. + [1:1] + + + dis + No Interrupt is Pending. + 0 + + + en + An interrupt is pending. + 1 + + + + + START + START Condition Interrupt Enable. + [2:2] + + + + + FIFOLEN + FIFO Configuration Register. + 0x18 + + + RX_DEPTH + Receive FIFO Length. + [7:0] + read-only + + + TX_DEPTH + Transmit FIFO Length. + [15:8] + read-only + + + + + RXCTRL0 + Receive Control Register 0. + 0x1C + + + DNR + Do Not Respond. + [0:0] + + + respond + Always respond to address match. + 0 + + + not_respond_rx_fifo_empty + Do not respond to address match when RX_FIFO is not empty. + 1 + + + + + FLUSH + Receive FIFO Flush. This bit is automatically cleared to 0 after the operation. Setting this bit to 1 will affect RX_FIFO status. + [7:7] + + + not_flushed + FIFO not flushed. + 0 + + + flush + Flush RX_FIFO. + 1 + + + + + THD_LVL + Receive FIFO Threshold. These bits define the RX_FIFO interrupt threshold. + [11:8] + + + + + RXCTRL1 + Receive Control Register 1. + 0x20 + + + CNT + Receive Count Bits. These bits define the number of bytes to be received in a transaction, except for the case RXCNT = 0. RXCNT = 0 means 256 bytes to be received in a transaction. + [7:0] + + + LVL + Receive FIFO Count. These bits reflect the number of byte in the RX_FIFO. These bits are flushed when I2CEN = 0. + [11:8] + read-only + + + + + TXCTRL0 + Transmit Control Register 0. + 0x24 + + + PRELOAD_MODE + Transmit FIFO Preaload Mode. Setting this bit will allow for high speed application to preload the transmit FIFO prior to Slave Address Match. + [0:0] + + + TX_READY_MODE + Transmit FIFO Ready Manual Mode. + [1:1] + + + en + HW control of I2CTXRDY enabled. + 0 + + + dis + HW control of I2CTXRDY disabled. + 1 + + + + + GC_ADDR_FLUSH_DIS + TX FIFO General Call Address Match Auto Flush Disable. + [2:2] + + + en + Enabled. + 0 + + + dis + Disabled. + 1 + + + + + WR_ADDR_FLUSH_DIS + TX FIFO Slave Address Match Write Auto Flush Disable. + [3:3] + + + en + Enabled. + 0 + + + dis + Disabled. + 1 + + + + + RD_ADDR_FLUSH_DIS + TX FIFO Slave Address Match Read Auto Flush Disable. + [4:4] + + + en + Enabled. + 0 + + + dis + Disabled. + 1 + + + + + NACK_FLUSH_DIS + TX FIFO received NACK Auto Flush Disable. + [5:5] + + + en + Enabled. + 0 + + + dis + Disabled. + 1 + + + + + FLUSH + Transmit FIFO Flush. This bit is automatically cleared to 0 after the operation. + [7:7] + + + not_flushed + FIFO not flushed. + 0 + + + flush + Flush TX_FIFO. + 1 + + + + + THD_LVL + Transmit FIFO Threshold. These bits define the TX_FIFO interrupt threshold. + [11:8] + + + + + TXCTRL1 + Transmit Control Register 1. + 0x28 + + + PRELOAD_RDY + Transmit FIFO Preload Ready. + [0:0] + + + LVL + Transmit FIFO Count. These bits reflect the number of bytes in the TX_FIFO. + [11:8] + read-only + + + + + FIFO + Data Register. + 0x2C + + + DATA + Data is read from or written to this location. Transmit and receive FIFO are separate but both are addressed at this location. + 0 + 8 + + + + + MSTCTRL + Master Control Register. + 0x30 + + + START + Setting this bit to 1 will start a master transfer. + [0:0] + + + RESTART + Setting this bit to 1 will generate a repeated START. + [1:1] + + + STOP + Setting this bit to 1 will generate a STOP condition. + [2:2] + + + EX_ADDR_EN + Slave Extend Address Select. + [7:7] + + + 7_bits_address + 7-bit address. + 0 + + + 10_bits_address + 10-bit address. + 1 + + + + + + + CLKLO + Clock Low Register. + 0x34 + + + LO + Clock low. In master mode, these bits define the SCL low period. In slave mode, these bits define the time SCL will be held low after data is outputted. + [8:0] + + + + + CLKHI + Clock high Register. + 0x38 + + + HI + Clock High. In master mode, these bits define the SCL high period. + [8:0] + + + + + HSCLK + Clock high Register. + 0x3C + + + LO + Clock Low. This field sets the Hs-Mode clock low count. In Slave mode, this is the time SCL is held low after data is output on SDA. + [7:0] + + + HI + Clock High. This field sets the Hs-Mode clock high count. In Slave mode, this is the time SCL is held high after data is output on SDA + [15:8] + + + + + TIMEOUT + Timeout Register + 0x40 + + + SCL_TO_VAL + Timeout + [15:0] + + + + + DMA + DMA Register. + 0x48 + + + TX_EN + TX channel enable. + [0:0] + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + RX_EN + RX channel enable. + [1:1] + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + + + 4 + 4 + SLAVE_MULTI[%s] + Slave Address Register. + SLAVE0 + 0x4C + 32 + read-write + + + ADDR + Slave Address. + [9:0] + + + DIS + Slave Disable. + [10:10] + + + EXT_ADDR_EN + Extended Address Select. + [15:15] + + + 7_bits_address + 7-bit address. + 0 + + + 10_bits_address + 10-bit address. + 1 + + + + + + + SLAVE0 + Slave Address Register. + 0x4C + + + SLAVE1 + Slave Address Register. + 0x50 + + + SLAVE2 + Slave Address Register. + 0x54 + + + SLAVE3 + Slave Address Register. + 0x58 + + + + + + I2C1 + Inter-Integrated Circuit. 1 + 0x4001E000 + + I2C1 + I2C1 IRQ + 36 + + + + + I2C2 + Inter-Integrated Circuit. 2 + 0x4001F000 + + I2C2 + I2C2 IRQ + 62 + + + + + I2S + Inter-IC Sound Interface. + I2S + 0x40060000 + 32 + + 0x00 + 0x1000 + registers + + + I2S + I2S IRQ + 99 + + + + CTRL0CH0 + Global mode channel. + 0x00 + + + LSB_FIRST + LSB Transmit Receive First. + [1:1] + read-write + + + PDM_FILT + PDM Filter. + [2:2] + read-write + + + PDM_EN + PDM Enable. + [3:3] + read-write + + + USEDDR + DDR. + [4:4] + read-write + + + PDM_INV + Invert PDM. + [5:5] + read-write + + + CH_MODE + SCK Select. + [7:6] + read-write + + + WS_POL + WS polarity select. + [8:8] + read-write + + + MSB_LOC + MSB location. + [9:9] + read-only + + + ALIGN + Align to MSB or LSB. + [10:10] + read-only + + + EXT_SEL + External SCK/WS selection. + [11:11] + read-write + + + STEREO + Stereo mode of I2S. + [13:12] + read-only + + + WSIZE + Data size when write to FIFO. + [15:14] + read-write + + + TX_EN + TX channel enable. + [16:16] + read-write + + + RX_EN + RX channel enable. + [17:17] + read-write + + + FLUSH + Flushes the TX/RX FIFO buffer. + [18:18] + read-write + + + RST + Write 1 to reset channel. + [19:19] + read-write + + + FIFO_LSB + Bit Field Control. + [20:20] + read-write + + + RX_THD_VAL + depth of receive FIFO for threshold interrupt generation. + [31:24] + read-write + + + + + CTRL1CH0 + Local channel Setup. + 0x10 + + + BITS_WORD + I2S word length. + [4:0] + read-write + + + EN + I2S clock enable. + [8:8] + read-write + + + SMP_SIZE + I2S sample size length. + [13:9] + read-write + + + ADJUST + LSB/MSB Justify. + [15:15] + read-write + + + CLKDIV + I2S clock frequency divisor. + [31:16] + read-write + + + + + FILTCH0 + Filter. + 0x20 + + + DMACH0 + DMA Control. + 0x30 + + + DMA_TX_THD_VAL + TX FIFO Level DMA Trigger. + [6:0] + read-write + + + DMA_TX_EN + TX DMA channel enable. + [7:7] + read-write + + + DMA_RX_THD_VAL + RX FIFO Level DMA Trigger. + [14:8] + read-write + + + DMA_RX_EN + RX DMA channel enable. + [15:15] + read-write + + + TX_LVL + Number of data word in the TX FIFO. + [23:16] + read-write + + + RX_LVL + Number of data word in the RX FIFO. + [31:24] + read-write + + + + + FIFOCH0 + I2S Fifo. + 0x40 + + + DATA + Load/unload location for TX and RX FIFO buffers. + [31:0] + read-write + + + + + INTFL + ISR Status. + 0x50 + + + RX_OV_CH0 + Status for RX FIFO Overrun interrupt. + [0:0] + read-write + + + RX_THD_CH0 + Status for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field. + [1:1] + read-write + + + TX_OB_CH0 + Status for interrupt when TX FIFO has only one byte remaining. + [2:2] + read-write + + + TX_HE_CH0 + Status for interrupt when TX FIFO is half empty. + [3:3] + read-write + + + + + INTEN + Interrupt Enable. + 0x54 + + + RX_OV_CH0 + Enable for RX FIFO Overrun interrupt. + [0:0] + read-write + + + RX_THD_CH0 + Enable for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field. + [1:1] + read-write + + + TX_OB_CH0 + Enable for interrupt when TX FIFO has only one byte remaining. + [2:2] + read-write + + + TX_HE_CH0 + Enable for interrupt when TX FIFO is half empty. + [3:3] + read-write + + + + + EXTSETUP + Ext Control. + 0x58 + + + EXT_BITS_WORD + Word Length for ch_mode. + [4:0] + read-write + + + + + WKEN + Wakeup Enable. + 0x5C + + + WKFL + Wakeup Flags. + 0x60 + + + + + + ICC0 + Instruction Cache Controller Registers + 0x4002A000 + + 0x00 + 0x800 + registers + + + + INFO + Cache ID Register. + 0x0000 + read-only + + + RELNUM + Release Number. Identifies the RTL release version. + 0 + 6 + + + PARTNUM + Part Number. This field reflects the value of C_ID_PART_NUMBER configuration parameter. + 6 + 4 + + + ID + Cache ID. This field reflects the value of the C_ID_CACHEID configuration parameter. + 10 + 6 + + + + + SZ + Memory Configuration Register. + 0x0004 + read-only + 0x00080008 + + + CCH + Cache Size. Indicates total size in Kbytes of cache. + 0 + 16 + + + MEM + Main Memory Size. Indicates the total size, in units of 128 Kbytes, of code memory accessible to the cache controller. + 16 + 16 + + + + + CTRL + Cache Control and Status Register. + 0x0100 + + + EN + Cache Enable. Controls whether the cache is bypassed or is in use. Changing the state of this bit will cause the instruction cache to be flushed and its contents invalidated. + 0 + 1 + + + dis + Cache Bypassed. Instruction data is stored in the line fill buffer but is not written to main cache memory array. + 0 + + + en + Cache Enabled. + 1 + + + + + RDY + Cache Ready flag. Cleared by hardware when at any time the cache as a whole is invalidated (including a system reset). When this bit is 0, the cache is effectively in bypass mode (instruction fetches will come from main memory or from the line fill buffer). Set by hardware when the invalidate operation is complete and the cache is ready. + 16 + 1 + read-only + + + notReady + Not Ready. + 0 + + + ready + Ready. + 1 + + + + + + + INVALIDATE + Invalidate All Registers. + 0x0700 + read-write + + + INVALID + Invalidate. + 0 + 32 + + + + + + + + MCR + Misc Control. + 0x40106C00 + + 0x00 + 0x400 + registers + + + + RST + Low Power Reset Control Register + 0x04 + + + LPTMR0 + Low Power Timer0 Reset. + 0 + 1 + + reset + read-write + + reset_done + Reset complete. + 0 + + + busy + Starts Reset or indicates reset in progress. + 1 + + + + + LPTMR1 + Low Power Timer1 Reset. + 1 + 1 + + + LPUART0 + Low Power UART0 Reset. + 2 + 1 + + + RTC + RTC Reset. + 3 + 1 + + + + + CLKCTRL + Clock Control. + 0x08 + + + ERTCO_PD + 32KHz Crystal Oscillator Power Down. + 16 + 1 + + + ERTCO_EN + 32KHz Crystal Oscillator Enable. + 17 + 1 + + + dis + Is Disabled. + 0 + + + en + Is Enabled. + 1 + + + + + + + AINCOMP + AIN Comparator. + 0x0C + + + PD + AIN Comparator Power Down control. + 0 + 2 + + + HYST + AIN Comparator Hysteresis control. + 2 + 2 + + + NSEL_COMP0 + Negative input select for AIN Comparator 0. + 16 + 4 + + + PSEL_COMP0 + Positive input select for AIN Comparator 0 + 20 + 4 + + + NSEL_COMP1 + Negative input select for AIN Comparator 1 + 24 + 4 + + + PSEL_COMP1 + Positive input select for AIN Comparator 1 + 28 + 4 + + + + + LPPIOCTRL + Low Power Peripheral IO Control Register. + 0x10 + + + LPTMR0_I + Enable control for LPTMR0 input. + 0 + 1 + + + LPTMR0_O + Enable control for LPTMR0 output. + 1 + 1 + + + LPTMR1_I + Enable control for LPTMR1 input. + 2 + 1 + + + LPTMR1_O + Enable control for LPTMR1 output. + 3 + 1 + + + LPUART0_RX + Enable control for LPUART0 RX. + 4 + 1 + + + LPUART0_TX + Enable control for LPUART0 TX. + 5 + 1 + + + LPUART0_CTS + Enable control for LPUART0 CTS. + 6 + 1 + + + LPUART0_RTS + Enable control for LPUART0 RTS. + 7 + 1 + + + + + PCLKDIS + Low Power Peripheral Clock Disable. + 0x24 + + + LPTMR0 + Low Power Timer0 Clock Disable. + 0 + 1 + + + en + enable it. + 0 + + + dis + disable it. + 1 + + + + + LPTMR1 + Low Power Timer1 Clock Disable. + 1 + 1 + + + LPUART0 + Low Power UART0 Clock Disable. + 2 + 1 + + + + + AESKEY + AES Key Pointer and Status. + 0x34 + + + PTR + AESKEY Pointer and Status. + 0 + 16 + + + + + ADC_CFG0 + ADC Cfig Register0. + 0x38 + + + LP_5K_DIS + Disable 5K divider option in low power modes + 0 + 1 + + + en + Enable. + 0 + + + dis + Disable. + 1 + + + + + LP_50K_DIS + Disable 50K divider option in low power modes + 1 + 1 + + + EN + Enable. + 0 + + + DIS + Disable. + 1 + + + + + EXT_REF + External Reference + 2 + 1 + + + REF_SEL + Reference Select + 3 + 1 + + + + + ADC_CFG1 + ADC Config Register1. + 0x3C + + + CH0_PU_DYN + ADC PU Dynamic Control for CH0 + 0 + 1 + + + dis + divider select always used. + 0 + + + en + divider select only used when channel is selected. + 1 + + + + + CH1_PU_DYN + ADC PU Dynamic Control for CH1 + 1 + 1 + + + CH2_PU_DYN + ADC PU Dynamic Control for CH2 + 2 + 1 + + + CH3_PU_DYN + ADC PU Dynamic Control for CH3 + 3 + 1 + + + CH4_PU_DYN + ADC PU Dynamic Control for CH4 + 4 + 1 + + + CH5_PU_DYN + ADC PU Dynamic Control for CH5 + 5 + 1 + + + CH6_PU_DYN + ADC PU Dynamic Control for CH6 + 6 + 1 + + + CH7_PU_DYN + ADC PU Dynamic Control for CH7 + 7 + 1 + + + CH8_PU_DYN + ADC PU Dynamic Control for CH8 + 8 + 1 + + + CH9_PU_DYN + ADC PU Dynamic Control for CH9 + 9 + 1 + + + CH10_PU_DYN + ADC PU Dynamic Control for CH10 + 10 + 1 + + + CH11_PU_DYN + ADC PU Dynamic Control for CH11 + 11 + 1 + + + CH12_PU_DYN + ADC PU Dynamic Control for CH12 + 12 + 1 + + + + + ADC_CFG2 + ADC Config Register2. + 0x40 + + + CH0 + Divider Select for channel 0 + 0 + 2 + + + div1 + Pass through, no divider. + 0 + + + div2_5k + Divide by 2, 5Kohm. + 1 + + + div2_50k + Divide by 2, 50Kohm. + 2 + + + + + CH1 + Divider Select for channel 1 + 2 + 2 + + + CH2 + Divider Select for channel 2 + 4 + 2 + + + CH3 + Divider Select for channel 3 + 6 + 2 + + + CH4 + Divider Select for channel 4 + 8 + 2 + + + CH5 + Divider Select for channel 5 + 10 + 2 + + + CH6 + Divider Select for channel 6 + 12 + 2 + + + CH7 + Divider Select for channel 7 + 14 + 2 + + + CH8 + Divider Select for channel 8 + 16 + 2 + + + CH9 + Divider Select for channel 9 + 18 + 2 + + + CH10 + Divider Select for channel 10 + 20 + 2 + + + CH11 + Divider Select for channel 11 + 22 + 2 + + + CH12 + Divider Select for channel 12 + 24 + 2 + + + + + ADC_CFG3 + ADC Config Register3. + 0x44 + + + VREFM + VREFM + 0 + 7 + + + VREFP + VREFP + 8 + 7 + + + IDRV + IDRV + 16 + 4 + + + VCM + VCM + 20 + 2 + + + ATB + ATB + 22 + 2 + + + D_IBOOST + D_IBOOST + 24 + 1 + + + + + + + + PWRSEQ + Power Sequencer / Low Power Control Register. + 0x40106800 + + 0x00 + 0x400 + registers + + + + LPCN + Low Power Control Register. + 0x00 + + + RAM0RET_EN + System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. + 0 + 1 + read-write + + + dis + Disable Ram Retention. + 0 + + + en + Enable System RAM 0 retention. + 1 + + + + + RAM1RET_EN + System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. + 1 + 1 + read-write + + + dis + Disable Ram Retention. + 0 + + + en + Enable System RAM 1 retention. + 1 + + + + + RAM2RET_EN + System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. + 2 + 1 + read-write + + + dis + Disable Ram Retention. + 0 + + + en + Enable System RAM 2 retention. + 1 + + + + + RAM3RET_EN + System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. + 3 + 1 + read-write + + + dis + Disable Ram Retention. + 0 + + + en + Enable System RAM 3 retention. + 1 + + + + + OVR + Operating Voltage Range + 4 + 2 + read-write + + + 0_9V + 0.9V 12MHz + 0 + + + 1_0V + 1.0V 48MHz + 1 + + + 1_1V + 1.1V 96MHz + 2 + + + + + VCORE_DET_BYPASS + Block Auto-Detect + 6 + 1 + read-write + + + en + enable + 0 + + + dis + disable + 1 + + + + + FVDDEN + Flash VDD Enable, force the flash VDD to remain enabled during LP modes. + 7 + 1 + read-write + + + dis + enable + 0 + + + en + disable + 1 + + + + + RETREG_EN + Retention Regulator Enable. This bit controls the retention regulator in BACKUP mode. + 8 + 1 + read-write + + + dis + Disabled. + 0 + + + en + Enabled. + 1 + + + + + STORAGE_EN + STORAGE Mode ENable. This bit allows low-power background mode operations, while the CPU is in DeepSleep. + 9 + 1 + read-write + + + dis + Disabled. + 0 + + + en + Enabled. + 1 + + + + + FASTWK_EN + Fast Wake-Up Mode. This bit enables fast wake-up from DeepSleep mode. (5uS typical). + 10 + 1 + read-write + + + dis + Disabled. + 0 + + + en + Enabled. + 1 + + + + + BG_DIS + Bandgap OFF. This controls the System Bandgap in DeepSleep mode. + 11 + 1 + read-write + + + on + Bandgap is always ON. + 0 + + + off + Bandgap is OFF in DeepSleep mode (default). + 1 + + + + + VCOREPOR_DIS + VDDC (Vcore) Power on reset Monitor Disable.This bit controls the Power-On Reset monitor on VDDC supply in DeepSleep and BACKUP mode. + 12 + 1 + read-write + + + en + Enable + 0 + + + dis + Disabled. + 1 + + + + + LDO_DIS + Disable Main LDO + 16 + 1 + read-write + + + en + Enable + 0 + + + dis + Disabled. + 1 + + + + + VCORE_EXT + Use external VCORE for 1V supply + 17 + 1 + read-write + + + dis + disable + 0 + + + en + use Vcore for retention. + 1 + + + + + VCOREMON_DIS + VDDC (Vcore) Monitor Disable. This bit controls the power monitor on the VCore supply in all operating modes. + 20 + 1 + read-write + + + en + Enable + 0 + + + dis + Disabled. + 1 + + + + + VDDAMON_DIS + VDDA Monitor Disable. This bit controls the power monitor of the Analog Supply in all operating modes. + 22 + 1 + read-write + + + en + Enable if Bandgap is ON (default) + 0 + + + dis + Disabled. + 1 + + + + + PORVDDMON_DIS + VDDIO Power-On Reset Monitor Disable. This bit controls the Power-On Reset monitor on VDDIO supply in all operating mods. + 25 + 1 + read-write + + + dis + Disabled. + 0 + + + en + Enabled. + 1 + + + + + VBBMON_DIS + VBB Monitor Disable. This bit controls the power monitor of the Analog Supply in all operating modes. + 27 + 1 + read-write + + + en + Enable if Bandgap is ON (default) + 0 + + + dis + Disabled. + 1 + + + + + INRO_EN + INRO remains on in all power modes if this bit is set otherwise it is controled by the LP controller + 28 + 1 + read-write + + + ERTCO_EN + XRTCO remains on in all power modes if this bit is set otherwise it is controled by the LP controller + 29 + 1 + read-write + + + TM_LPMODE + TBD + 30 + 1 + read-write + + + TM_PWRSEQ + TBD + 31 + 1 + read-write + + + + + LPWKST0 + Low Power I/O Wakeup Status Register 0. This register indicates the low power wakeup status for GPIO0. + 0x04 + + + ST + Wakeup IRQ flags (write ones to clear). One or more of these bits will be set when the corresponding dedicated GPIO pin (s) transition (s) from low to high or high to low. If GPIO wakeup source is selected, using PM.GPIOWKEN register, and the corresponding bit is also selected in LPWKEN register, an interrupt will be gnerated to wake up the CPU from a low power mode. + 0 + 31 + read-write + oneToClear + + + + + LPWKEN0 + Low Power I/O Wakeup Enable Register 0. This register enables low power wakeup functionality for GPIO0. + 0x08 + + + EN + Enable wakeup. These bits allow wakeup from the corresponding GPIO pin (s) on transition (s) from low to high or high to low when PM.GPIOWKEN is set. Wakeup status is indicated in PPWKST register. + 0 + 31 + read-write + + + + + LPWKST1 + Low Power I/O Wakeup Status Register 1. This register indicates the low power wakeup status for GPIO1. + 0x0C + + + LPWKEN1 + Low Power I/O Wakeup Enable Register 1. This register enables low power wakeup functionality for GPIO1. + 0x10 + + + LPPWKST + Low Power Peripheral Wakeup Status Register. + 0x30 + + + LPTMR0 + LPTM0 Wakeup Flag. + 0 + 1 + read-write + oneToClear + + + LPTMR1 + LPTMR1 Wakeup Flag. + 1 + 1 + read-write + oneToClear + + + LPUART0 + LPUART0 Wakeup Flag. + 2 + 1 + read-write + oneToClear + + + AINCOMP0 + AINCOMP0 Wakeup Flag. + 3 + 1 + read-write + oneToClear + + + AINCOMP1 + AINCOMP1 Wakeup Flag. + 4 + 1 + read-write + oneToClear + + + AINCOMP0_OUT + AINCOMP0 Status. + 5 + 1 + read-only + + + AINCOMP1_OUT + AINCOMP1 Status. + 6 + 1 + read-only + + + BACKUP + BBMODE Wakeup Flag. + 16 + 1 + read-write + oneToClear + + + + + LPPWKEN + Low Power Peripheral Wakeup Enable Register. + 0x34 + + + LPTMR0 + TIMER4 Wakeup Enable. This bit allows wakeup from the TIMER4. + 0 + 1 + read-write + + + LPTMR1 + TIMER5 Wakeup Enable. This bit allows wakeup from the TIMER5. + 1 + 1 + read-write + + + LPUART0 + LPUART Wakeup Enable. This bit allows wakeup from the LPUART. + 2 + 1 + read-write + + + AINCOMP0 + AINCOMP0 Wakeup Enable. This bit allows wakeup from the AINCOMP0. + 3 + 1 + read-write + + + AINCOMP1 + AINCOMP1 Wakeup Enable. This bit allows wakeup from the AINCOMP1. + 4 + 1 + read-write + + + + + LPMEMSD + Low Power Memory Shutdown Control. + 0x40 + + + RAM0 + System RAM block 0 Shut Down. + 0 + 1 + read-write + + + normal + Normal Operating Mode. + 0 + + + shutdown + Shutdown Mode. + 1 + + + + + RAM1 + System RAM block 1 Shut Down. + 1 + 1 + read-write + + + normal + Normal Operating Mode. + 0 + + + shutdown + Shutdown Mode. + 1 + + + + + RAM2 + System RAM block 2 Shut Down. + 2 + 1 + read-write + + + normal + Normal Operating Mode. + 0 + + + shutdown + Shutdown Mode. + 1 + + + + + RAM3 + System RAM block 3 Shut Down. + 3 + 1 + read-write + + + normal + Normal Operating Mode. + 0 + + + shutdown + Shutdown Mode. + 1 + + + + + + + GPR0 + General Purpose Register 0. + 0x48 + + + GPR1 + General Purpose Register 1. + 0x4C + + + + + + QDEC + Quadrature Encoder Interface + 0x40063000 + + 0x00 + 0x1000 + registers + + + + CTRL + Control Register. + 0x0000 + + + en + 0 + 1 + read-write + + enum + + disable + 0x0 + + + enable + 0x1 + + + + + mode + 1 + 2 + read-write + + enum + + x1mode + 0 + + + x2mode + 1 + + + x4mode + 2 + + + + + swap + 3 + 1 + read-write + + + filter + 4 + 2 + read-write + + enum + + 1_sample + 0 + + + 2_samples + 1 + + + 3_samples + 2 + + + 4_samples + 3 + + + + + rst_index + 6 + 1 + read-write + + + rst_maxcnt + 7 + 1 + read-write + + + sticky + 8 + 1 + read-write + + + psc + 16 + 3 + read-write + + enum + + div1 + 0 + + + div2 + 1 + + + div4 + 2 + + + div8 + 3 + + + div16 + 4 + + + div32 + 5 + + + div64 + 6 + + + div128 + 7 + + + + + + + INTFL + Interrupt Flag Register. + 0x0004 + + + index + 0 + 1 + read-write + oneToClear + + + qerr + 1 + 1 + read-write + oneToClear + + + compare + 2 + 1 + read-write + oneToClear + + + maxcnt + 3 + 1 + read-write + oneToClear + + + capture + 4 + 1 + read-write + oneToClear + + + dir + 5 + 1 + read-write + oneToClear + + + move + 6 + 1 + read-write + oneToClear + + + + + INTEN + Interrupt Enable Register. + 0x0008 + + + index + 0 + 1 + read-write + + + qerr + 1 + 1 + read-write + + + compare + 2 + 1 + read-write + + + maxcnt + 3 + 1 + read-write + + + capture + 4 + 1 + read-write + + + dir + 5 + 1 + read-write + + + move + 6 + 1 + read-write + + + + + MAXCNT + Maximum Count Register. + 0x000C + + + maxcnt + 0 + 32 + read-write + + + + + INITIAL + Initial Count Register. + 0x0010 + + + initial + 0 + 32 + read-write + + + + + COMPARE + Compare Register. + 0x0014 + + + compare + 0 + 32 + read-write + + + + + INDEX + Index Register. count captured when QEI fired + 0x0018 + read-only + + + index + 0 + 32 + read-only + + + + + CAPTURE + Capture Register. counter captured when QES fired + 0x001C + read-only + + + capture + 0 + 32 + read-only + + + + + STATUS + Status Register. + 0x0020 + read-only + + + dir + 0 + 1 + read-only + + + + + POSITION + Count Register. raw counter value + 0x0024 + + + position + 0 + 32 + read-only + + + + + CAPDLY + delay CAPTURE + 0x0028 + + + capdly + 0 + 32 + read-write + + + + + + + + RTC + Real Time Clock and Alarm. + 0x40106000 + + 0x00 + 0x400 + registers + + + RTC + RTC interrupt. + 3 + + + + SEC + RTC Second Counter. This register contains the 32-bit second counter. + 0x00 + 0x00000000 + + + SEC + Seconds Counter. + 0 + 32 + + + + + SSEC + RTC Sub-second Counter. This counter increments at 256Hz. RTC_SEC is incremented when this register rolls over from 0xFF to 0x00. + 0x04 + 0x00000000 + + + SSEC + Sub-Seconds Counter (12-bit). + 0 + 12 + + + + + TODA + Time-of-day Alarm. + 0x08 + 0x00000000 + + + TOD_ALARM + Time-of-day Alarm. + 0 + 20 + + + + + SSECA + RTC sub-second alarm. This register contains the reload value for the sub-second alarm. + 0x0C + 0x00000000 + + + SSEC_ALARM + This register contains the reload value for the sub-second alarm. + 0 + 32 + + + + + CTRL + RTC Control Register. + 0x10 + 0x00000008 + 0xFFFFFF38 + + + EN + Real Time Clock Enable. This bit enables the Real Time Clock. This bit can only be written when WE=1 and BUSY =0. Change to this bit is effective only after BUSY is cleared from 1 to 0. + 0 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + TOD_ALARM_IE + Alarm Time-of-Day Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0. + 1 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + SSEC_ALARM_IE + Alarm Sub-second Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0. + 2 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + BUSY + RTC Busy. This bit is set to 1 by hardware when changes to RTC registers required a synchronized version of the register to be in place. This bit is automatically cleared by hardware. + 3 + 1 + read-only + + + idle + Idle. + 0 + + + busy + Busy. + 1 + + + + + RDY + RTC Ready. This bit is set to 1 by hardware when the RTC count registers update. It can be cleared to 0 by software at any time. It will also be cleared to 0 by hardware just prior to an update of the RTC count register. + 4 + 1 + + + busy + Register has not updated. + 0 + + + ready + Ready. + 1 + + + + + RDY_IE + RTC Ready Interrupt Enable. + 5 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + TOD_ALARM + Time-of-Day Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor. + 6 + 1 + read-only + + + inactive + Not active + 0 + + + Pending + Active + 1 + + + + + SSEC_ALARM + Sub-second Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor. + 7 + 1 + read-only + + + inactive + Not active + 0 + + + Pending + Active + 1 + + + + + SQW_EN + Square Wave Output Enable. + 8 + 1 + + + inactive + Not active + 0 + + + Pending + Active + 1 + + + + + SQW_SEL + Frequency Output Selection. When SQE=1, these bits specify the output frequency on the SQW pin. + 9 + 2 + + + freq1Hz + 1 Hz (Compensated). + 0 + + + freq512Hz + 512 Hz (Compensated). + 1 + + + freq4KHz + 4 KHz. + 2 + + + clkDiv8 + RTC Input Clock / 8. + 3 + + + + + RD_EN + Asynchronous Counter Read Enable. + 14 + 1 + + + WR_EN + Write Enable. This register bit serves as a protection mechanism against unintentional writes to critical RTC bits. + 15 + 1 + + + inactive + Not active + 0 + + + Pending + Active + 1 + + + + + + + TRIM + RTC Trim Register. + 0x14 + 0x00000000 + + + TRIM + RTC Trim. This register contains the 2's complement value that specifies the trim resolution. Each increment or decrement of the bit adds or subtracts 1ppm at each 4KHz clock value, with a maximum correction of +/- 127ppm. + 0 + 8 + + + VRTC_TMR + VBAT Timer Value. When RTC is running off of VBAT, this field is incremented every 32 seconds. + 8 + 24 + + + + + OSCCTRL + RTC Oscillator Control Register. + 0x18 + 0x00000000 + + + FILTER_EN + Enables analog deglitch filter. + 0 + 1 + + + IBIAS_SEL + If IBIAS_EN is 1, selects 4x,2x mode. + 1 + 1 + + + HYST_EN + Enables high current hysteresis buffer. + 2 + 1 + + + IBIAS_EN + Enables higher 4x,2x current modes. + 3 + 1 + + + BYPASS + RTC Crystal Bypass + 4 + 1 + + + SQW_32K + RTC 32kHz Square Wave Output + 5 + 1 + + + + + + + + SIR + System Initialization Registers. + 0x40000400 + read-only + + 0x00 + 0x400 + registers + + + + STATUS + System Initialization Status Register. + 0x00 + read-only + + + CFG_VALID + Configuration Valid Flag. + 0 + 1 + read-only + + + CFG_ERR + Configuration Error Flag. + 1 + 1 + read-only + + + USER_CFG_ERR + User Configuration Error Flag. + 2 + 1 + read-only + + + + + ADDR + Read-only field set by the SIB block if a CRC error occurs during the read of the OTP memory. Contains the failing address in OTP memory (when CRCERR equals 1). + 0x04 + read-only + + + ADDR + 0 + 32 + + + + + FSTAT + Function Status Register. + 0x100 + read-only + + + FPU + FPU Function. + 0 + 1 + + + TRNG + TRNG Function. + 14 + 1 + + + DS_ACK + DeepSleep Acknowledge. + 15 + 1 + + + + + SFSTAT + Security Function Status Register. + 0x104 + read-only + + + SECFUNC0 + Secure Function 0 Status. + 0 + 1 + + + + + + + + SPI0 + SPI peripheral. + 0x40046000 + + 0x00 + 0x1000 + registers + + + SPI0 + 16 + + + + FIFO32 + Register for reading and writing the FIFO. + 0x00 + 32 + read-write + + + DATA + Read to pull from RX FIFO, write to put into TX FIFO. + 0 + 32 + + + + + 2 + 2 + FIFO16[%s] + Register for reading and writing the FIFO. + 0x00 + 16 + read-write + + + DATA + Read to pull from RX FIFO, write to put into TX FIFO. + 0 + 16 + + + + + 4 + 1 + FIFO8[%s] + Register for reading and writing the FIFO. + 0x00 + 8 + read-write + + + DATA + Read to pull from RX FIFO, write to put into TX FIFO. + 0 + 8 + + + + + CTRL0 + Register for controlling SPI peripheral. + 0x04 + read-write + + + EN + SPI Enable. + 0 + 1 + + + dis + SPI is disabled. + 0 + + + en + SPI is enabled. + 1 + + + + + MST_MODE + Master Mode Enable. + 1 + 1 + + + dis + SPI is Slave mode. + 0 + + + en + SPI is Master mode. + 1 + + + + + SS_IO + Slave Select 0, IO direction, to support Multi-Master mode,Slave Select 0 can be input in Master mode. This bit has no effect in slave mode. + 4 + 1 + + + output + Slave select 0 is output. + 0 + + + input + Slave Select 0 is input, only valid if MMEN=1. + 1 + + + + + START + Start Transmit. + 5 + 1 + + + start + Master Initiates a transaction, this bit is self clearing when transactions are done. If a transaction cimpletes, and the TX FIFO is empty, the Master halts, if a transaction completes, and the TX FIFO is not empty, the Master initiates another transaction. + 1 + + + + + SS_CTRL + Start Select Control. Used in Master mode to control the behavior of the Slave Select signal at the end of a transaction. + 8 + 1 + + + DEASSERT + SPI De-asserts Slave Select at the end of a transaction. + 0 + + + ASSERT + SPI leaves Slave Select asserted at the end of a transaction. + 1 + + + + + SS_ACTIVE + Slave Select, when in Master mode selects which Slave devices are selected. More than one Slave device can be selected. + 16 + 4 + + + SS0 + SS0 is selected. + 0x1 + + + SS1 + SS1 is selected. + 0x2 + + + SS2 + SS2 is selected. + 0x4 + + + SS3 + SS3 is selected. + 0x8 + + + + + + + CTRL1 + Register for controlling SPI peripheral. + 0x08 + read-write + + + TX_NUM_CHAR + Nubmer of Characters to transmit. + 0 + 16 + + + RX_NUM_CHAR + Nubmer of Characters to receive. + 16 + 16 + + + + + CTRL2 + Register for controlling SPI peripheral. + 0x0C + read-write + + + CLKPHA + Clock Phase. + 0 + 1 + + + Rising_Edge + Data Sampled on clock rising edge. Use when in SPI Mode 0 and Mode 2 + 0 + + + Falling_Edge + Data Sampled on clock falling edge. Use when in SPI Mode 1 and Mode 3 + 1 + + + + + CLKPOL + Clock Polarity. + 1 + 1 + + + Normal + Normal Clock. Use when in SPI Mode 0 and Mode 1 + 0 + + + Inverted + Inverted Clock. Use when in SPI Mode 2 and Mode 3 + 1 + + + + + SCLK_FB_INV + SCLK_FB_INV. + 4 + 1 + + + NUMBITS + Number of Bits per character. + 8 + 4 + + + 0 + 16 bits per character. + 0 + + + + + DATA_WIDTH + SPI Data width. + 12 + 2 + + + Mono + 1 data pin. + 0 + + + Dual + 2 data pins. + 1 + + + Quad + 4 data pins. + 2 + + + + + THREE_WIRE + Three Wire mode. MOSI/MISO pin (s) shared. Only Mono mode suports Four-Wire. + 15 + 1 + + + dis + Use four wire mode (Mono only). + 0 + + + en + Use three wire mode. + 1 + + + + + SS_POL + Slave Select Polarity, each Slave Select can have unique polarity. + 16 + 8 + + + SS0_high + SS0 active high. + 0x1 + + + SS1_high + SS1 active high. + 0x2 + + + SS2_high + SS2 active high. + 0x4 + + + SS3_high + SS3 active high. + 0x8 + + + + + + + SSTIME + Register for controlling SPI peripheral/Slave Select Timing. + 0x10 + read-write + + + PRE + Slave Select Pre delay 1. + 0 + 8 + + + 256 + 256 system clocks between SS active and first serial clock edge. + 0 + + + + + POST + Slave Select Post delay 2. + 8 + 8 + + + 256 + 256 system clocks between last serial clock edge and SS inactive. + 0 + + + + + INACT + Slave Select Inactive delay. + 16 + 8 + + + 256 + 256 system clocks between transactions. + 0 + + + + + + + CLKCTRL + Register for controlling SPI clock rate. + 0x14 + read-write + + + LO + Low duty cycle control. In timer mode, reload[7:0]. + 0 + 8 + + + Dis + Duty cycle control of serial clock generation is disabled. + 0 + + + + + HI + High duty cycle control. In timer mode, reload[15:8]. + 8 + 8 + + + Dis + Duty cycle control of serial clock generation is disabled. + 0 + + + + + CLKDIV + System Clock scale factor. Scales the AMBA clock by 2^SCALE before generating serial clock. + 16 + 4 + + + + + DMA + Register for controlling DMA. + 0x1C + read-write + + + TX_THD_VAL + Transmit FIFO level that will trigger a DMA request, also level for threshold status. When TX FIFO has fewer than this many bytes, the associated events and conditions are triggered. + 0 + 5 + + + TX_FIFO_EN + Transmit FIFO enabled for SPI transactions. + 6 + 1 + + + dis + Transmit FIFO is not enabled. + 0 + + + en + Transmit FIFO is enabled. + 1 + + + + + TX_FLUSH + Clear TX FIFO, clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side. + 7 + 1 + + + CLEAR + Clear the Transmit FIFO, clears any pending TX FIFO status. + 1 + + + + + TX_LVL + Count of entries in TX FIFO. + 8 + 6 + read-only + + + DMA_TX_EN + TX DMA Enable. + 15 + 1 + + + DIS + TX DMA requests are disabled, andy pending DMA requests are cleared. + 0 + + + en + TX DMA requests are enabled. + 1 + + + + + RX_THD_VAL + Receive FIFO level that will trigger a DMA request, also level for threshold status. When RX FIFO has more than this many bytes, the associated events and conditions are triggered. + 16 + 5 + + + RX_FIFO_EN + Receive FIFO enabled for SPI transactions. + 22 + 1 + + + DIS + Receive FIFO is not enabled. + 0 + + + en + Receive FIFO is enabled. + 1 + + + + + RX_FLUSH + Clear RX FIFO, clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side. + 23 + 1 + + + CLEAR + Clear the Receive FIFO, clears any pending RX FIFO status. + 1 + + + + + RX_LVL + Count of entries in RX FIFO. + 24 + 6 + read-only + + + DMA_RX_EN + RX DMA Enable. + 31 + 1 + + + dis + RX DMA requests are disabled, any pending DMA requests are cleared. + 0 + + + en + RX DMA requests are enabled. + 1 + + + + + + + INTFL + Register for reading and clearing interrupt flags. All bits are write 1 to clear. + 0x20 + read-write + + + TX_THD + TX FIFO Threshold Crossed. + 0 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + TX_EM + TX FIFO Empty. + 1 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + RX_THD + RX FIFO Threshold Crossed. + 2 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + RX_FULL + RX FIFO FULL. + 3 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + SSA + Slave Select Asserted. + 4 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + SSD + Slave Select Deasserted. + 5 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + FAULT + Multi-Master Mode Fault. + 8 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + ABORT + Slave Abort Detected. + 9 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + MST_DONE + Master Done, set when SPI Master has completed any transactions. + 11 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + TX_OV + Transmit FIFO Overrun, set when the AMBA side attempts to write data to a full transmit FIFO. + 12 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + TX_UN + Transmit FIFO Underrun, set when the SPI side attempts to read data from an empty transmit FIFO. + 13 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + RX_OV + Receive FIFO Overrun, set when the SPI side attempts to write to a full receive FIFO. + 14 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + RX_UN + Receive FIFO Underrun, set when the AMBA side attempts to read data from an empty receive FIFO. + 15 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + + + INTEN + Register for enabling interrupts. + 0x24 + read-write + + + TX_THD + TX FIFO Threshold interrupt enable. + 0 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + TX_EM + TX FIFO Empty interrupt enable. + 1 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + RX_THD + RX FIFO Threshold Crossed interrupt enable. + 2 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + RX_FULL + RX FIFO FULL interrupt enable. + 3 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + SSA + Slave Select Asserted interrupt enable. + 4 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + SSD + Slave Select Deasserted interrupt enable. + 5 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + FAULT + Multi-Master Mode Fault interrupt enable. + 8 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + ABORT + Slave Abort Detected interrupt enable. + 9 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + MST_DONE + Master Done interrupt enable. + 11 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + TX_OV + Transmit FIFO Overrun interrupt enable. + 12 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + TX_UN + Transmit FIFO Underrun interrupt enable. + 13 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + RX_OV + Receive FIFO Overrun interrupt enable. + 14 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + RX_UN + Receive FIFO Underrun interrupt enable. + 15 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + + + WKFL + Register for wake up flags. All bits in this register are write 1 to clear. + 0x28 + read-write + + + TX_THD + Wake on TX FIFO Threshold Crossed. + 0 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + TX_EM + Wake on TX FIFO Empty. + 1 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + RX_THD + Wake on RX FIFO Threshold Crossed. + 2 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + RX_FULL + Wake on RX FIFO Full. + 3 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + + + WKEN + Register for wake up enable. + 0x2C + read-write + + + TX_THD + Wake on TX FIFO Threshold Crossed Enable. + 0 + 1 + + + dis + Wakeup source disabled. + 0 + + + en + Wakeup source enabled. + 1 + + + + + TX_EM + Wake on TX FIFO Empty Enable. + 1 + 1 + + + dis + Wakeup source disabled. + 0 + + + en + Wakeup source enabled. + 1 + + + + + RX_THD + Wake on RX FIFO Threshold Crossed Enable. + 2 + 1 + + + dis + Wakeup source disabled. + 0 + + + en + Wakeup source enabled. + 1 + + + + + RX_FULL + Wake on RX FIFO Full Enable. + 3 + 1 + + + dis + Wakeup source disabled. + 0 + + + en + Wakeup source enabled. + 1 + + + + + + + STAT + SPI Status register. + 0x30 + read-only + + + BUSY + SPI active status. In Master mode, set when transaction starts, cleared when last bit of last character is acted upon and Slave Select de-assertion would occur. In Slave mode, set when Slave Select is asserted, cleared when Slave Select is de-asserted. Not used in Timer mode. + 0 + 1 + + + not + SPI not active. + 0 + + + active + SPI active. + 1 + + + + + + + + + + SPI1 + SPI peripheral. 1 + 0x40047000 + + SPI1 + SPI1 IRQ + 17 + + + + + SPI2 + SPI peripheral. 2 + 0x40048000 + + SPI2 + SPI2 IRQ + 18 + + + + + TMR + Low-Power Configurable Timer + 0x40010000 + + 0x00 + 0x1000 + registers + + + TMR + 5 + + + + CNT + Timer Counter Register. + 0x00 + read-write + + + COUNT + The current count value for the timer. This field increments as the timer counts. + 0 + 32 + + + + + CMP + Timer Compare Register. + 0x04 + read-write + + + COMPARE + The value in this register is used as the compare value for the timer's count value. The compare field meaning is determined by the specific mode of the timer. + 0 + 32 + + + + + PWM + Timer PWM Register. + 0x08 + read-write + + + PWM + Timer PWM Match: + In PWM Mode, this field sets the count value for the first transition period of the PWM cycle. At the end of the cycle where CNT equals PWM, the PWM output transitions to the second period of the PWM cycle. The second PWM period count is stored in the CMP register. The value set for PWM must me less than the value set in CMP for PWM mode operation. Timer Capture Value: + In Capture, Compare, and Capture/Compare modes, this field is used to store the CNT value when a Capture, Compare, or Capture/Compare event occurs. + 0 + 32 + + + + + INTFL + Timer Interrupt Status Register. + 0x0C + read-write + + + IRQ_A + Interrupt Flag for Timer A. + 0 + 1 + + + WRDONE_A + Write Done Flag for Timer A indicating the write is complete from APB to CLK_TMR domain. + 8 + 1 + + + WR_DIS_A + Write Disable to CNT/PWM for Timer A in the non-cascaded dual timer configuration. + 9 + 1 + + + IRQ_B + Interrupt Flag for Timer B. + 16 + 1 + + + WRDONE_B + Write Done Flag for Timer B indicating the write is complete from APB to CLK_TMR domain. + 24 + 1 + + + WR_DIS_B + Write Disable to CNT/PWM for Timer B in the non-cascaded dual timer configuration. + 25 + 1 + + + + + CTRL0 + Timer Control Register. + 0x10 + read-write + + + MODE_A + Mode Select for Timer A + 0 + 4 + + + ONE_SHOT + One-Shot Mode + 0 + + + CONTINUOUS + Continuous Mode + 1 + + + COUNTER + Counter Mode + 2 + + + PWM + PWM Mode + 3 + + + CAPTURE + Capture Mode + 4 + + + COMPARE + Compare Mode + 5 + + + GATED + Gated Mode + 6 + + + CAPCOMP + Capture/Compare Mode + 7 + + + DUAL_EDGE + Dual Edge Capture Mode + 8 + + + IGATED + Inactive Gated Mode + 12 + + + + + CLKDIV_A + Clock Divider Select for Timer A + 4 + 4 + + + DIV_BY_1 + Prescaler Divide-By-1 + 0 + + + DIV_BY_2 + Prescaler Divide-By-2 + 1 + + + DIV_BY_4 + Prescaler Divide-By-4 + 2 + + + DIV_BY_8 + Prescaler Divide-By-8 + 3 + + + DIV_BY_16 + Prescaler Divide-By-16 + 4 + + + DIV_BY_32 + Prescaler Divide-By-32 + 5 + + + DIV_BY_64 + Prescaler Divide-By-64 + 6 + + + DIV_BY_128 + Prescaler Divide-By-128 + 7 + + + DIV_BY_256 + Prescaler Divide-By-256 + 8 + + + DIV_BY_512 + Prescaler Divide-By-512 + 9 + + + DIV_BY_1024 + Prescaler Divide-By-1024 + 10 + + + DIV_BY_2048 + Prescaler Divide-By-2048 + 11 + + + DIV_BY_4096 + TBD + 12 + + + + + POL_A + Timer Polarity for Timer A + 8 + 1 + + + PWMSYNC_A + PWM Synchronization Mode for Timer A + 9 + 1 + + + NOLHPOL_A + PWM Phase A (Non-Overlapping High) Polarity for Timer A + 10 + 1 + + + NOLLPOL_A + PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer A + 11 + 1 + + + PWMCKBD_A + PWM Phase A-Prime Output Disable for Timer A + 12 + 1 + + + RST_A + Resets all flip flops in the CLK_TMR domain for Timer A. Self-clears. + 13 + 1 + + + CLKEN_A + Write 1 to Enable CLK_TMR for Timer A + 14 + 1 + + + EN_A + Enable for Timer A + 15 + 1 + + + MODE_B + Mode Select for Timer B + 16 + 4 + + + ONE_SHOT + One-Shot Mode + 0 + + + CONTINUOUS + Continuous Mode + 1 + + + COUNTER + Counter Mode + 2 + + + PWM + PWM Mode + 3 + + + CAPTURE + Capture Mode + 4 + + + COMPARE + Compare Mode + 5 + + + GATED + Gated Mode + 6 + + + CAPCOMP + Capture/Compare Mode + 7 + + + DUAL_EDGE + Dual Edge Capture Mode + 8 + + + IGATED + Inactive Gated Mode + 14 + + + + + CLKDIV_B + Clock Divider Select for Timer B + 20 + 4 + + + DIV_BY_1 + Prescaler Divide-By-1 + 0 + + + DIV_BY_2 + Prescaler Divide-By-2 + 1 + + + DIV_BY_4 + Prescaler Divide-By-4 + 2 + + + DIV_BY_8 + Prescaler Divide-By-8 + 3 + + + DIV_BY_16 + Prescaler Divide-By-16 + 4 + + + DIV_BY_32 + Prescaler Divide-By-32 + 5 + + + DIV_BY_64 + Prescaler Divide-By-64 + 6 + + + DIV_BY_128 + Prescaler Divide-By-128 + 7 + + + DIV_BY_256 + Prescaler Divide-By-256 + 8 + + + DIV_BY_512 + Prescaler Divide-By-512 + 9 + + + DIV_BY_1024 + Prescaler Divide-By-1024 + 10 + + + DIV_BY_2048 + Prescaler Divide-By-2048 + 11 + + + DIV_BY_4096 + TBD + 12 + + + + + POL_B + Timer Polarity for Timer B + 24 + 1 + + + PWMSYNC_B + PWM Synchronization Mode for Timer B + 25 + 1 + + + NOLHPOL_B + PWM Phase A (Non-Overlapping High) Polarity for Timer B + 26 + 1 + + + NOLLPOL_B + PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer B + 27 + 1 + + + PWMCKBD_B + PWM Phase A-Prime Output Disable for Timer B + 28 + 1 + + + RST_B + Resets all flip flops in the CLK_TMR domain for Timer B. Self-clears. + 29 + 1 + + + CLKEN_B + Write 1 to Enable CLK_TMR for Timer B + 30 + 1 + + + EN_B + Enable for Timer B + 31 + 1 + + + + + NOLCMP + Timer Non-Overlapping Compare Register. + 0x14 + read-write + + + LO_A + Non-Overlapping Low Compare value for Timer A controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime. + 0 + 8 + + + HI_A + Non-Overlapping High Compare value for Timer A controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A. + 8 + 8 + + + LO_B + Non-Overlapping Low Compare value for Timer B controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime. + 16 + 8 + + + HI_B + Non-Overlapping High Compare value for Timer B controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A. + 24 + 8 + + + + + CTRL1 + Timer Configuration Register. + 0x18 + read-write + + + CLKSEL_A + Timer Clock Select for Timer A + 0 + 2 + + + CLKEN_A + Timer A Enable Status + 2 + 1 + + + CLKRDY_A + CLK_TMR Ready Flag for Timer A + 3 + 1 + + + EVENT_SEL_A + Event Select for Timer A + 4 + 3 + + + NEGTRIG_A + Negative Edge Trigger for Event for Timer A + 7 + 1 + + + IE_A + Interrupt Enable for Timer A + 8 + 1 + + + CAPEVENT_SEL_A + Capture Event Select for Timer A + 9 + 2 + + + SW_CAPEVENT_A + Software Capture Event for Timer A + 11 + 1 + + + WE_A + Wake-Up Enable for Timer A + 12 + 1 + + + OUTEN_A + OUT_OE_O Enable for Modes 0, 1,and 5 for Timer A + 13 + 1 + + + OUTBEN_A + PWM_CKB_EN_O Enable for Modes other than Mode 3 for Timer A + 14 + 1 + + + CLKSEL_B + Timer Clock Select for Timer B + 16 + 2 + + + CLKEN_B + Timer B Enable Status + 18 + 1 + + + CLKRDY_B + CLK_TMR Ready Flag for Timer B + 19 + 1 + + + EVENT_SEL_B + Event Select for Timer B + 20 + 3 + + + NEGTRIG_B + Negative Edge Trigger for Event for Timer B + 23 + 1 + + + IE_B + Interrupt Enable for Timer B + 24 + 1 + + + CAPEVENT_SEL_B + Capture Event Select for Timer B + 25 + 2 + + + SW_CAPEVENT_B + Software Capture Event for Timer B + 27 + 1 + + + WE_B + Wake-Up Enable for Timer B + 28 + 1 + + + CASCADE + Cascade two 16-bit timers into one 32-bit timer. Only available when C_TMR16=0 adn C_DUALTMR16=1. + 31 + 1 + + + + + WKFL + Timer Wakeup Status Register. + 0x1C + read-write + + + A + Wake-Up Flag for Timer A + 0 + 1 + + + B + Wake-Up Flag for Timer B + 16 + 1 + + + + + + + + TMR1 + Low-Power Configurable Timer 1 + 0x40011000 + + TMR1 + TMR1 IRQ + 6 + + + + + TMR2 + Low-Power Configurable Timer 2 + 0x40012000 + + TMR2 + TMR2 IRQ + 7 + + + + + TMR3 + Low-Power Configurable Timer 3 + 0x40013000 + + TMR3 + TMR3 IRQ + 8 + + + + + TMR4 + Low-Power Configurable Timer 4 + 0x40114000 + + TMR4 + TMR4 IRQ + 9 + + + + + TMR5 + Low-Power Configurable Timer 5 + 0x40115000 + + TMR5 + TMR5 IRQ + 10 + + + + + TRIMSIR + Trim System Initilazation Registers + 0x40105400 + + 0x00 + 0x400 + registers + + + + BB_SIR2 + System Init. Configuration Register 2. + 0x08 + read-write + + + TRIM_IBRO_RBIAS + HIRC8M Trim + 0 + 6 + + + RAM0_1ECCEN + RAM 0 and RAM 1 ECC Enable + 8 + 1 + + + dis + ECC Disabled. + 0 + + + en + ECC Enabled. + 1 + + + + + RAM2ECCEN + RAM 2 ECC Enable + 9 + 1 + + + RAM3ECCEN + RAM 3 ECC Enable + 10 + 1 + + + ICC0ECCEN + ICC 0 ECC Enable + 11 + 1 + + + FL0ECCEN + Flash 0 ECC Enable + 12 + 1 + + + FL1ECCEN + Flash 1 ECC Enable + 13 + 1 + + + TRIM_IBRO + HIRC8M Trim + 16 + 16 + + + + + BB_SIR3 + System Init. Configuration Register 3. + 0x0C + read-write + + + BB_SIR6 + System Init. Configuration Register 6. + 0x18 + read-only + + + RTCX1TRIM + RTCX1 Trim + 4 + 5 + + + RTCX2TRIM + RTCX2 Trim + 9 + 5 + + + + + + + + TRNG + Random Number Generator. + 0x4004D000 + + 0x00 + 0x1000 + registers + + + TRNG + TRNG interrupt. + 4 + + + + CTRL + TRNG Control Register. + 0x00 + 0x00000003 + + + ODHT + Start On-Demand health test. + 0 + 1 + + + RND_IE + To enable IRQ generation when a new 32-bit Random number is ready. + 1 + 1 + + + disable + Disable + 0 + + + enable + Enable + 1 + + + + + HEALTH_EN + Enable IRQ generation when a health test fails. + 2 + 1 + + + AESKG_USR + AES Key Generate. When enabled, the key for securing NVSRAM is generated and transferred to the secure key register automatically without user visibility or intervention. This bit is cleared by hardware once the key has been transferred to the secure key register. + 3 + 1 + + + AESKG_SYS + AESKG_SYS. + 4 + 1 + + + KEYWIPE + To wipe the Battery Backed key. + 15 + 1 + + + + + STATUS + Data. The content of this register is valid only when RNG_IS = 1. When TRNG is disabled, read returns 0x0000 0000. + 0x04 + + + RDY + 32-bit random data is ready to read from TRNG_DATA register. Reading TRNG_DATA when RND_RDY=0 will return all 0's. IRQ is generated when RND_RDY=1 if TRNG_CN.RND_IRQ_EN=1. + 0 + 1 + + + Busy + TRNG Busy + 0 + + + Ready + 32 bit random data is ready + 1 + + + + + ODHT + On-Demand health test status. + 1 + 1 + + + HT + Health test status. + 2 + 1 + + + SRCFAIL + Entropy source has failed. + 3 + 1 + + + AESKGD + AESKGD. + 4 + 1 + + + LD_CNT + LD_CNT. + 24 + 8 + + + + + DATA + Data. The content of this register is valid only when RNG_IS = 1. When TRNG is disabled, read returns 0x0000 0000. + 0x08 + read-only + + + DATA + Data. The content of this register is valid only when RNG_IS =1. When TNRG is disabled, read returns 0x0000 0000. + 0 + 32 + + + + + + + + UART + UART Low Power Registers + 0x40042000 + + 0x00 + 0x1000 + registers + + + + CTRL + Control register + 0x0000 + + + RX_THD_VAL + This field specifies the depth of receive FIFO for interrupt generation (value 0 and > 16 are ignored) + 0 + 4 + + + PAR_EN + Parity Enable + 4 + 1 + + + PAR_EO + when PAREN=1 selects odd or even parity odd is 1 even is 0 + 5 + 1 + + + PAR_MD + Selects parity based on 1s or 0s count (when PAREN=1) + 6 + 1 + + + CTS_DIS + CTS Sampling Disable + 7 + 1 + + + TX_FLUSH + Flushes the TX FIFO buffer. This bit is automatically cleared by hardware when flush is completed. + 8 + 1 + + + RX_FLUSH + Flushes the RX FIFO buffer. This bit is automatically cleared by hardware when flush is completed. + 9 + 1 + + + CHAR_SIZE + Selects UART character size + 10 + 2 + + + 5bits + 5 bits + 0 + + + 6bits + 6 bits + 1 + + + 7bits + 7 bits + 2 + + + 8bits + 8 bits + 3 + + + + + STOPBITS + Selects the number of stop bits that will be generated + 12 + 1 + + + HFC_EN + Enables/disables hardware flow control + 13 + 1 + + + RTSDC + Hardware Flow Control RTS Mode + 14 + 1 + + + BCLKEN + Baud clock enable + 15 + 1 + + + BCLKSRC + To select the UART clock source for the UART engine (except APB registers). Secondary clock (used for baud rate generator) can be asynchronous from APB clock. + 16 + 2 + + + Peripheral_Clock + apb clock + 0 + + + CLK1 + Clock 1 + 1 + + + CLK2 + Clock 2 + 2 + + + CLK3 + Clock 3 + 3 + + + + + DPFE_EN + Data/Parity bit frame error detection enable + 18 + 1 + + + BCLKRDY + Baud clock Ready read only bit + 19 + 1 + + + UCAGM + UART Clock Auto Gating mode + 20 + 1 + + + FDM + Fractional Division Mode + 21 + 1 + + + DESM + RX Dual Edge Sampling Mode + 22 + 1 + + + + + STATUS + Status register + 0x0004 + read-only + + + TX_BUSY + Read-only flag indicating the UART transmit status + 0 + 1 + + + RX_BUSY + Read-only flag indicating the UART receiver status + 1 + 1 + + + RX_EM + Read-only flag indicating the RX FIFO state + 4 + 1 + + + RX_FULL + Read-only flag indicating the RX FIFO state + 5 + 1 + + + TX_EM + Read-only flag indicating the TX FIFO state + 6 + 1 + + + TX_FULL + Read-only flag indicating the TX FIFO state + 7 + 1 + + + RX_LVL + Indicates the number of bytes currently in the RX FIFO (0-RX FIFO_ELTS) + 8 + 4 + + + TX_LVL + Indicates the number of bytes currently in the TX FIFO (0-TX FIFO_ELTS) + 12 + 4 + + + + + INT_EN + Interrupt Enable control register + 0x0008 + + + RX_FERR + Enable Interrupt For RX Frame Error + 0 + 1 + + + RX_PAR + Enable Interrupt For RX Parity Error + 1 + 1 + + + CTS_EV + Enable Interrupt For CTS signal change Error + 2 + 1 + + + RX_OV + Enable Interrupt For RX FIFO Overrun Error + 3 + 1 + + + RX_THD + Enable Interrupt For RX FIFO reaches the number of bytes configured by RXTHD + 4 + 1 + + + TX_OB + Enable Interrupt For TX FIFO has one byte remaining + 5 + 1 + + + TX_HE + Enable Interrupt For TX FIFO has half empty + 6 + 1 + + + + + INT_FL + Interrupt status flags Control register + 0x000C + + + RX_FERR + Flag for RX Frame Error Interrupt. + 0 + 1 + + + RX_PAR + Flag for RX Parity Error interrupt + 1 + 1 + + + CTS_EV + Flag for CTS signal change interrupt (hardware flow control disabled) + 2 + 1 + + + RX_OV + Flag for RX FIFO Overrun interrupt + 3 + 1 + + + RX_THD + Flag for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field + 4 + 1 + + + TX_OB + Flag for interrupt when TX FIFO has one byte remaining + 5 + 1 + + + TX_HE + Flag for interrupt when TX FIFO is half empty + 6 + 1 + + + + + CLKDIV + Clock Divider register + 0x0010 + + + CLKDIV + Baud rate divisor value + 0 + 20 + + + + + OSR + Over Sampling Rate register + 0x0014 + + + OSR + OSR + 0 + 3 + + + + + TXPEEK + TX FIFO Output Peek register + 0x0018 + + + DATA + Read TX FIFO next data. Reading from this field does not affect the contents of TX FIFO. Note that the parity bit is available from this field. + 0 + 8 + + + + + PNR + Pin register + 0x001C + + + CTS + Current sampled value of CTS IO + 0 + 1 + read-only + + + RTS + This bit controls the value to apply on the RTS IO. If set to 1, the RTS IO is set to high level. If set to 0, the RTS IO is set to low level. + 1 + 1 + + + + + FIFO + FIFO Read/Write register + 0x0020 + + + DATA + Load/unload location for TX and RX FIFO buffers. + 0 + 8 + + + RX_PAR + Parity error flag for next byte to be read from FIFO. + 8 + 1 + + + + + DMA + DMA Configuration register + 0x0030 + + + TX_THD_VAL + TX FIFO Level DMA Trigger If the TX FIFO level is less than this value, then the TX FIFO DMA interface will send a signal to system DMA to notify that TX FIFO is ready to receive data from memory. + 0 + 4 + + + TX_EN + TX DMA channel enable + 4 + 1 + + + RX_THD_VAL + Rx FIFO Level DMA Trigger If the RX FIFO level is greater than this value, then the RX FIFO DMA interface will send a signal to the system DMA to notify that RX FIFO has characters to transfer to memory. + 5 + 4 + + + RX_EN + RX DMA channel enable + 9 + 1 + + + + + WKEN + Wake up enable Control register + 0x0034 + + + RX_NE + Wake-Up Enable for RX FIFO Not Empty + 0 + 1 + + + RX_FULL + Wake-Up Enable for RX FIFO Full + 1 + 1 + + + RX_THD + Wake-Up Enable for RX FIFO Threshold Met + 2 + 1 + + + + + WKFL + Wake up Flags register + 0x0038 + + + RX_NE + Wake-Up Flag for RX FIFO Not Empty + 0 + 1 + + + RX_FULL + Wake-Up Flag for RX FIFO Full + 1 + 1 + + + RX_THD + Wake-Up Flag for RX FIFO Threshold Met + 2 + 1 + + + + + + + + UART1 + UART Low Power Registers 1 + 0x40043000 + + + + UART2 + UART Low Power Registers 2 + 0x40044000 + + + + UART3 + UART Low Power Registers 3 + 0x40145000 + + + + WDT + Windowed Watchdog Timer + 0x40003000 + + 0x00 + 0x0400 + registers + + + WWDT + 1 + + + + CTRL + Watchdog Timer Control Register. + 0x00 + read-write + + + INT_LATE_VAL + Windowed Watchdog Interrupt Upper Limit. Sets the number of WDTCLK cycles until a windowed watchdog timer interrupt is generated (if enabled) if the CPU does not write the windowed watchdog reset sequence to the WWDT_RST register before the watchdog timer has counted this time period since the last timer reset. + 0 + 4 + + + wdt2pow31 + 2**31 clock cycles. + 0 + + + wdt2pow30 + 2**30 clock cycles. + 1 + + + wdt2pow29 + 2**29 clock cycles. + 2 + + + wdt2pow28 + 2**28 clock cycles. + 3 + + + wdt2pow27 + 2^27 clock cycles. + 4 + + + wdt2pow26 + 2**26 clock cycles. + 5 + + + wdt2pow25 + 2**25 clock cycles. + 6 + + + wdt2pow24 + 2**24 clock cycles. + 7 + + + wdt2pow23 + 2**23 clock cycles. + 8 + + + wdt2pow22 + 2**22 clock cycles. + 9 + + + wdt2pow21 + 2**21 clock cycles. + 10 + + + wdt2pow20 + 2**20 clock cycles. + 11 + + + wdt2pow19 + 2**19 clock cycles. + 12 + + + wdt2pow18 + 2**18 clock cycles. + 13 + + + wdt2pow17 + 2**17 clock cycles. + 14 + + + wdt2pow16 + 2**16 clock cycles. + 15 + + + + + RST_LATE_VAL + Windowed Watchdog Reset Upper Limit. Sets the number of WDTCLK cycles until a system reset occurs (if enabled) if the CPU does not write the watchdog reset sequence to the WDT_RST register before the watchdog timer has counted this time period since the last timer reset. + 4 + 4 + + + wdt2pow31 + 2**31 clock cycles. + 0 + + + wdt2pow30 + 2**30 clock cycles. + 1 + + + wdt2pow29 + 2**29 clock cycles. + 2 + + + wdt2pow28 + 2**28 clock cycles. + 3 + + + wdt2pow27 + 2^27 clock cycles. + 4 + + + wdt2pow26 + 2**26 clock cycles. + 5 + + + wdt2pow25 + 2**25 clock cycles. + 6 + + + wdt2pow24 + 2**24 clock cycles. + 7 + + + wdt2pow23 + 2**23 clock cycles. + 8 + + + wdt2pow22 + 2**22 clock cycles. + 9 + + + wdt2pow21 + 2**21 clock cycles. + 10 + + + wdt2pow20 + 2**20 clock cycles. + 11 + + + wdt2pow19 + 2**19 clock cycles. + 12 + + + wdt2pow18 + 2**18 clock cycles. + 13 + + + wdt2pow17 + 2**17 clock cycles. + 14 + + + wdt2pow16 + 2**16 clock cycles. + 15 + + + + + EN + Windowed Watchdog Timer Enable. + 8 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + INT_LATE + Windowed Watchdog Timer Interrupt Flag Too Late. + 9 + 1 + + read-write + + inactive + No interrupt is pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + WDT_INT_EN + Windowed Watchdog Timer Interrupt Enable. + 10 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + WDT_RST_EN + Windowed Watchdog Timer Reset Enable. + 11 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + INT_EARLY + Windowed Watchdog Timer Interrupt Flag Too Soon. + 12 + 1 + + read-write + + inactive + No interrupt is pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + INT_EARLY_VAL + Windowed Watchdog Interrupt Lower Limit. Sets the number of WDTCLK cycles that establishes the lower boundary of the watchdog window. A windowed watchdog timer interrupt is generated (if enabled) if the CPU writes the windowed watchdog reset sequence to the WWDT_RST register before the watchdog timer has counted this time period since the last timer reset. + 16 + 4 + + + wdt2pow31 + 2**31 clock cycles. + 0 + + + wdt2pow30 + 2**30 clock cycles. + 1 + + + wdt2pow29 + 2**29 clock cycles. + 2 + + + wdt2pow28 + 2**28 clock cycles. + 3 + + + wdt2pow27 + 2^27 clock cycles. + 4 + + + wdt2pow26 + 2**26 clock cycles. + 5 + + + wdt2pow25 + 2**25 clock cycles. + 6 + + + wdt2pow24 + 2**24 clock cycles. + 7 + + + wdt2pow23 + 2**23 clock cycles. + 8 + + + wdt2pow22 + 2**22 clock cycles. + 9 + + + wdt2pow21 + 2**21 clock cycles. + 10 + + + wdt2pow20 + 2**20 clock cycles. + 11 + + + wdt2pow19 + 2**19 clock cycles. + 12 + + + wdt2pow18 + 2**18 clock cycles. + 13 + + + wdt2pow17 + 2**17 clock cycles. + 14 + + + wdt2pow16 + 2**16 clock cycles. + 15 + + + + + RST_EARLY_VAL + Windowed Watchdog Reset Lower Limit. Sets the number of WDTCLK cycles that establishes the lower boundary of the watchdog window. A system reset occurs (if enabled) if the CPU writes the windowed watchdog reset sequence to the WWDT_RST register before the watchdog timer has counted this time period since the last timer reset. + 20 + 4 + + + wdt2pow31 + 2**31 clock cycles. + 0 + + + wdt2pow30 + 2**30 clock cycles. + 1 + + + wdt2pow29 + 2**29 clock cycles. + 2 + + + wdt2pow28 + 2**28 clock cycles. + 3 + + + wdt2pow27 + 2^27 clock cycles. + 4 + + + wdt2pow26 + 2**26 clock cycles. + 5 + + + wdt2pow25 + 2**25 clock cycles. + 6 + + + wdt2pow24 + 2**24 clock cycles. + 7 + + + wdt2pow23 + 2**23 clock cycles. + 8 + + + wdt2pow22 + 2**22 clock cycles. + 9 + + + wdt2pow21 + 2**21 clock cycles. + 10 + + + wdt2pow20 + 2**20 clock cycles. + 11 + + + wdt2pow19 + 2**19 clock cycles. + 12 + + + wdt2pow18 + 2**18 clock cycles. + 13 + + + wdt2pow17 + 2**17 clock cycles. + 14 + + + wdt2pow16 + 2**16 clock cycles. + 15 + + + + + CLKRDY_IE + Switch Ready Interrupt Enable. Fires an interrupt when it is safe to swithc the clock. + 27 + 1 + + + CLKRDY + Clock Status. + 28 + 1 + + + WIN_EN + Enables the Windowed Watchdog Function. + 29 + 1 + + + dis + Windowed Mode Disabled (i.e. Compatibility Mode). + 0 + + + en + Windowed Mode Enabled. + 1 + + + + + RST_EARLY + Windowed Watchdog Timer Reset Flag Too Soon. + 30 + 1 + + read-write + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + RST_LATE + Windowed Watchdog Timer Reset Flag Too Late. + 31 + 1 + + read-write + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + + + RST + Windowed Watchdog Timer Reset Register. + 0x04 + write-only + + + RESET + Writing the watchdog counter 'reset sequence' to this register resets the watchdog counter. If the watchdog count exceeds INT_PERIOD_UPPER_LIMIT then a watchdog interrupt will occur, if enabled. If the watchdog count exceeds RST_PERIOD_UPPER_LIMIT then a watchdog reset will occur, if enabled. + 0 + 8 + + + seq0 + The first value to be written to reset the WDT. + 0x000000A5 + + + seq1 + The second value to be written to reset the WDT. + 0x0000005A + + + + + + + CLKSEL + Windowed Watchdog Timer Clock Select Register. + 0x08 + read-write + + + SOURCE + WWDT Clock Selection Register. + 0 + 3 + + + + + CNT + Windowed Watchdog Timer Count Register. + 0x0C + read-only + + + COUNT + Current Value of the Windowed Watchdog Timer Counter. + 0 + 32 + + + + + + + + WDT1 + Windowed Watchdog Timer 1 + 0x40003400 + + WDT1 + WDT1 IRQ + 57 + + + + + diff --git a/Libraries/CMSIS/Device/Maxim/MAX32572/Include/mcr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32572/Include/mcr_regs.h index 74d81eabe9e..443fbd4d40a 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32572/Include/mcr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32572/Include/mcr_regs.h @@ -25,8 +25,8 @@ * ******************************************************************************/ -#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_MCR_REGS_H_ -#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_MCR_REGS_H_ +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32672_INCLUDE_MCR_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32672_INCLUDE_MCR_REGS_H_ /* **** Includes **** */ #include @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile @@ -74,16 +78,19 @@ extern "C" { * Structure type to access the MCR Registers. */ typedef struct { - __R uint32_t rsv_0x0_0x7[2]; - __IO uint32_t pdown; /**< \b 0x08: MCR PDOWN Register */ - __R uint32_t rsv_0xc; - __IO uint32_t ctrl; /**< \b 0x10: MCR CTRL Register */ - __IO uint32_t clkctrl; /**< \b 0x14: MCR CLKCTRL Register */ - __IO uint32_t rst; /**< \b 0x18: MCR RST Register */ - __IO uint32_t rtctrim; /**< \b 0x1C: MCR RTCTRIM Register */ - __R uint32_t rsv_0x20_0x5f[16]; - __IO uint32_t ldoctrl; /**< \b 0x60: MCR LDOCTRL Register */ - __IO uint32_t pwrmonst; /**< \b 0x64: MCR PWRMONST Register */ + __R uint32_t rsv_0x0; + __IO uint32_t rst; /**< \b 0x04: MCR RST Register */ + __IO uint32_t clkctrl; /**< \b 0x08: MCR CLKCTRL Register */ + __IO uint32_t aincomp; /**< \b 0x0C: MCR AINCOMP Register */ + __IO uint32_t lppioctrl; /**< \b 0x10: MCR LPPIOCTRL Register */ + __R uint32_t rsv_0x14_0x23[4]; + __IO uint32_t pclkdis; /**< \b 0x24: MCR PCLKDIS Register */ + __R uint32_t rsv_0x28_0x33[3]; + __IO uint32_t aeskey; /**< \b 0x34: MCR AESKEY Register */ + __IO uint32_t adc_cfg0; /**< \b 0x38: MCR ADC_CFG0 Register */ + __IO uint32_t adc_cfg1; /**< \b 0x3C: MCR ADC_CFG1 Register */ + __IO uint32_t adc_cfg2; /**< \b 0x40: MCR ADC_CFG2 Register */ + __IO uint32_t adc_cfg3; /**< \b 0x44: MCR ADC_CFG3 Register */ } mxc_mcr_regs_t; /* Register offsets for module MCR */ @@ -93,160 +100,286 @@ typedef struct { * @brief MCR Peripheral Register Offsets from the MCR Base Peripheral Address. * @{ */ -#define MXC_R_MCR_PDOWN ((uint32_t)0x00000008UL) /**< Offset from MCR Base Address: 0x0008 */ -#define MXC_R_MCR_CTRL ((uint32_t)0x00000010UL) /**< Offset from MCR Base Address: 0x0010 */ -#define MXC_R_MCR_CLKCTRL ((uint32_t)0x00000014UL) /**< Offset from MCR Base Address: 0x0014 */ -#define MXC_R_MCR_RST ((uint32_t)0x00000018UL) /**< Offset from MCR Base Address: 0x0018 */ -#define MXC_R_MCR_RTCTRIM ((uint32_t)0x0000001CUL) /**< Offset from MCR Base Address: 0x001C */ -#define MXC_R_MCR_LDOCTRL ((uint32_t)0x00000060UL) /**< Offset from MCR Base Address: 0x0060 */ -#define MXC_R_MCR_PWRMONST ((uint32_t)0x00000064UL) /**< Offset from MCR Base Address: 0x0064 */ +#define MXC_R_MCR_RST ((uint32_t)0x00000004UL) /**< Offset from MCR Base Address: 0x0004 */ +#define MXC_R_MCR_CLKCTRL ((uint32_t)0x00000008UL) /**< Offset from MCR Base Address: 0x0008 */ +#define MXC_R_MCR_AINCOMP ((uint32_t)0x0000000CUL) /**< Offset from MCR Base Address: 0x000C */ +#define MXC_R_MCR_LPPIOCTRL ((uint32_t)0x00000010UL) /**< Offset from MCR Base Address: 0x0010 */ +#define MXC_R_MCR_PCLKDIS ((uint32_t)0x00000024UL) /**< Offset from MCR Base Address: 0x0024 */ +#define MXC_R_MCR_AESKEY ((uint32_t)0x00000034UL) /**< Offset from MCR Base Address: 0x0034 */ +#define MXC_R_MCR_ADC_CFG0 ((uint32_t)0x00000038UL) /**< Offset from MCR Base Address: 0x0038 */ +#define MXC_R_MCR_ADC_CFG1 ((uint32_t)0x0000003CUL) /**< Offset from MCR Base Address: 0x003C */ +#define MXC_R_MCR_ADC_CFG2 ((uint32_t)0x00000040UL) /**< Offset from MCR Base Address: 0x0040 */ +#define MXC_R_MCR_ADC_CFG3 ((uint32_t)0x00000044UL) /**< Offset from MCR Base Address: 0x0044 */ /**@} end of group mcr_registers */ /** * @ingroup mcr_registers - * @defgroup MCR_PDOWN MCR_PDOWN - * @brief PDOWN Drive Strength + * @defgroup MCR_RST MCR_RST + * @brief Low Power Reset Control Register * @{ */ -#define MXC_F_MCR_PDOWN_PDOWNDS_POS 0 /**< PDOWN_PDOWNDS Position */ -#define MXC_F_MCR_PDOWN_PDOWNDS ((uint32_t)(0x3UL << MXC_F_MCR_PDOWN_PDOWNDS_POS)) /**< PDOWN_PDOWNDS Mask */ +#define MXC_F_MCR_RST_LPTMR0_POS 0 /**< RST_LPTMR0 Position */ +#define MXC_F_MCR_RST_LPTMR0 ((uint32_t)(0x1UL << MXC_F_MCR_RST_LPTMR0_POS)) /**< RST_LPTMR0 Mask */ -#define MXC_F_MCR_PDOWN_PDOWNVS_POS 2 /**< PDOWN_PDOWNVS Position */ -#define MXC_F_MCR_PDOWN_PDOWNVS ((uint32_t)(0x1UL << MXC_F_MCR_PDOWN_PDOWNVS_POS)) /**< PDOWN_PDOWNVS Mask */ +#define MXC_F_MCR_RST_LPTMR1_POS 1 /**< RST_LPTMR1 Position */ +#define MXC_F_MCR_RST_LPTMR1 ((uint32_t)(0x1UL << MXC_F_MCR_RST_LPTMR1_POS)) /**< RST_LPTMR1 Mask */ -/**@} end of group MCR_PDOWN_Register */ +#define MXC_F_MCR_RST_LPUART0_POS 2 /**< RST_LPUART0 Position */ +#define MXC_F_MCR_RST_LPUART0 ((uint32_t)(0x1UL << MXC_F_MCR_RST_LPUART0_POS)) /**< RST_LPUART0 Mask */ + +#define MXC_F_MCR_RST_RTC_POS 3 /**< RST_RTC Position */ +#define MXC_F_MCR_RST_RTC ((uint32_t)(0x1UL << MXC_F_MCR_RST_RTC_POS)) /**< RST_RTC Mask */ + +/**@} end of group MCR_RST_Register */ /** * @ingroup mcr_registers - * @defgroup MCR_CTRL MCR_CTRL - * @brief Misc Power State Control Register + * @defgroup MCR_CLKCTRL MCR_CLKCTRL + * @brief Clock Control. * @{ */ -#define MXC_F_MCR_CTRL_VDDCSW_POS 1 /**< CTRL_VDDCSW Position */ -#define MXC_F_MCR_CTRL_VDDCSW ((uint32_t)(0x3UL << MXC_F_MCR_CTRL_VDDCSW_POS)) /**< CTRL_VDDCSW Mask */ +#define MXC_F_MCR_CLKCTRL_ERTCO_PD_POS 16 /**< CLKCTRL_ERTCO_PD Position */ +#define MXC_F_MCR_CLKCTRL_ERTCO_PD ((uint32_t)(0x1UL << MXC_F_MCR_CLKCTRL_ERTCO_PD_POS)) /**< CLKCTRL_ERTCO_PD Mask */ -#define MXC_F_MCR_CTRL_USBSWEN_N_POS 3 /**< CTRL_USBSWEN_N Position */ -#define MXC_F_MCR_CTRL_USBSWEN_N ((uint32_t)(0x1UL << MXC_F_MCR_CTRL_USBSWEN_N_POS)) /**< CTRL_USBSWEN_N Mask */ +#define MXC_F_MCR_CLKCTRL_ERTCO_EN_POS 17 /**< CLKCTRL_ERTCO_EN Position */ +#define MXC_F_MCR_CLKCTRL_ERTCO_EN ((uint32_t)(0x1UL << MXC_F_MCR_CLKCTRL_ERTCO_EN_POS)) /**< CLKCTRL_ERTCO_EN Mask */ -#define MXC_F_MCR_CTRL_P1M_POS 9 /**< CTRL_P1M Position */ -#define MXC_F_MCR_CTRL_P1M ((uint32_t)(0x1UL << MXC_F_MCR_CTRL_P1M_POS)) /**< CTRL_P1M Mask */ +/**@} end of group MCR_CLKCTRL_Register */ -#define MXC_F_MCR_CTRL_RSTN_VOLTAGE_SEL_POS 10 /**< CTRL_RSTN_VOLTAGE_SEL Position */ -#define MXC_F_MCR_CTRL_RSTN_VOLTAGE_SEL ((uint32_t)(0x1UL << MXC_F_MCR_CTRL_RSTN_VOLTAGE_SEL_POS)) /**< CTRL_RSTN_VOLTAGE_SEL Mask */ +/** + * @ingroup mcr_registers + * @defgroup MCR_AINCOMP MCR_AINCOMP + * @brief AIN Comparator. + * @{ + */ +#define MXC_F_MCR_AINCOMP_PD_POS 0 /**< AINCOMP_PD Position */ +#define MXC_F_MCR_AINCOMP_PD ((uint32_t)(0x3UL << MXC_F_MCR_AINCOMP_PD_POS)) /**< AINCOMP_PD Mask */ -/**@} end of group MCR_CTRL_Register */ +#define MXC_F_MCR_AINCOMP_HYST_POS 2 /**< AINCOMP_HYST Position */ +#define MXC_F_MCR_AINCOMP_HYST ((uint32_t)(0x3UL << MXC_F_MCR_AINCOMP_HYST_POS)) /**< AINCOMP_HYST Mask */ + +#define MXC_F_MCR_AINCOMP_NSEL_COMP0_POS 16 /**< AINCOMP_NSEL_COMP0 Position */ +#define MXC_F_MCR_AINCOMP_NSEL_COMP0 ((uint32_t)(0xFUL << MXC_F_MCR_AINCOMP_NSEL_COMP0_POS)) /**< AINCOMP_NSEL_COMP0 Mask */ + +#define MXC_F_MCR_AINCOMP_PSEL_COMP0_POS 20 /**< AINCOMP_PSEL_COMP0 Position */ +#define MXC_F_MCR_AINCOMP_PSEL_COMP0 ((uint32_t)(0xFUL << MXC_F_MCR_AINCOMP_PSEL_COMP0_POS)) /**< AINCOMP_PSEL_COMP0 Mask */ + +#define MXC_F_MCR_AINCOMP_NSEL_COMP1_POS 24 /**< AINCOMP_NSEL_COMP1 Position */ +#define MXC_F_MCR_AINCOMP_NSEL_COMP1 ((uint32_t)(0xFUL << MXC_F_MCR_AINCOMP_NSEL_COMP1_POS)) /**< AINCOMP_NSEL_COMP1 Mask */ + +#define MXC_F_MCR_AINCOMP_PSEL_COMP1_POS 28 /**< AINCOMP_PSEL_COMP1 Position */ +#define MXC_F_MCR_AINCOMP_PSEL_COMP1 ((uint32_t)(0xFUL << MXC_F_MCR_AINCOMP_PSEL_COMP1_POS)) /**< AINCOMP_PSEL_COMP1 Mask */ + +/**@} end of group MCR_AINCOMP_Register */ /** * @ingroup mcr_registers - * @defgroup MCR_CLKCTRL MCR_CLKCTRL - * @brief Clock Control Register. + * @defgroup MCR_LPPIOCTRL MCR_LPPIOCTRL + * @brief Low Power Peripheral IO Control Register. * @{ */ -#define MXC_F_MCR_CLKCTRL_ERTCO_PD_POS 16 /**< CLKCTRL_ERTCO_PD Position */ -#define MXC_F_MCR_CLKCTRL_ERTCO_PD ((uint32_t)(0x1UL << MXC_F_MCR_CLKCTRL_ERTCO_PD_POS)) /**< CLKCTRL_ERTCO_PD Mask */ +#define MXC_F_MCR_LPPIOCTRL_LPTMR0_I_POS 0 /**< LPPIOCTRL_LPTMR0_I Position */ +#define MXC_F_MCR_LPPIOCTRL_LPTMR0_I ((uint32_t)(0x1UL << MXC_F_MCR_LPPIOCTRL_LPTMR0_I_POS)) /**< LPPIOCTRL_LPTMR0_I Mask */ -#define MXC_F_MCR_CLKCTRL_ERTCO_EN_POS 17 /**< CLKCTRL_ERTCO_EN Position */ -#define MXC_F_MCR_CLKCTRL_ERTCO_EN ((uint32_t)(0x1UL << MXC_F_MCR_CLKCTRL_ERTCO_EN_POS)) /**< CLKCTRL_ERTCO_EN Mask */ +#define MXC_F_MCR_LPPIOCTRL_LPTMR0_O_POS 1 /**< LPPIOCTRL_LPTMR0_O Position */ +#define MXC_F_MCR_LPPIOCTRL_LPTMR0_O ((uint32_t)(0x1UL << MXC_F_MCR_LPPIOCTRL_LPTMR0_O_POS)) /**< LPPIOCTRL_LPTMR0_O Mask */ -/**@} end of group MCR_CLKCTRL_Register */ +#define MXC_F_MCR_LPPIOCTRL_LPTMR1_I_POS 2 /**< LPPIOCTRL_LPTMR1_I Position */ +#define MXC_F_MCR_LPPIOCTRL_LPTMR1_I ((uint32_t)(0x1UL << MXC_F_MCR_LPPIOCTRL_LPTMR1_I_POS)) /**< LPPIOCTRL_LPTMR1_I Mask */ + +#define MXC_F_MCR_LPPIOCTRL_LPTMR1_O_POS 3 /**< LPPIOCTRL_LPTMR1_O Position */ +#define MXC_F_MCR_LPPIOCTRL_LPTMR1_O ((uint32_t)(0x1UL << MXC_F_MCR_LPPIOCTRL_LPTMR1_O_POS)) /**< LPPIOCTRL_LPTMR1_O Mask */ + +#define MXC_F_MCR_LPPIOCTRL_LPUART0_RX_POS 4 /**< LPPIOCTRL_LPUART0_RX Position */ +#define MXC_F_MCR_LPPIOCTRL_LPUART0_RX ((uint32_t)(0x1UL << MXC_F_MCR_LPPIOCTRL_LPUART0_RX_POS)) /**< LPPIOCTRL_LPUART0_RX Mask */ + +#define MXC_F_MCR_LPPIOCTRL_LPUART0_TX_POS 5 /**< LPPIOCTRL_LPUART0_TX Position */ +#define MXC_F_MCR_LPPIOCTRL_LPUART0_TX ((uint32_t)(0x1UL << MXC_F_MCR_LPPIOCTRL_LPUART0_TX_POS)) /**< LPPIOCTRL_LPUART0_TX Mask */ + +#define MXC_F_MCR_LPPIOCTRL_LPUART0_CTS_POS 6 /**< LPPIOCTRL_LPUART0_CTS Position */ +#define MXC_F_MCR_LPPIOCTRL_LPUART0_CTS ((uint32_t)(0x1UL << MXC_F_MCR_LPPIOCTRL_LPUART0_CTS_POS)) /**< LPPIOCTRL_LPUART0_CTS Mask */ + +#define MXC_F_MCR_LPPIOCTRL_LPUART0_RTS_POS 7 /**< LPPIOCTRL_LPUART0_RTS Position */ +#define MXC_F_MCR_LPPIOCTRL_LPUART0_RTS ((uint32_t)(0x1UL << MXC_F_MCR_LPPIOCTRL_LPUART0_RTS_POS)) /**< LPPIOCTRL_LPUART0_RTS Mask */ + +/**@} end of group MCR_LPPIOCTRL_Register */ /** * @ingroup mcr_registers - * @defgroup MCR_RST MCR_RST - * @brief Reset Register. + * @defgroup MCR_PCLKDIS MCR_PCLKDIS + * @brief Low Power Peripheral Clock Disable. * @{ */ -#define MXC_F_MCR_RST_RTC_POS 0 /**< RST_RTC Position */ -#define MXC_F_MCR_RST_RTC ((uint32_t)(0x1UL << MXC_F_MCR_RST_RTC_POS)) /**< RST_RTC Mask */ +#define MXC_F_MCR_PCLKDIS_LPTMR0_POS 0 /**< PCLKDIS_LPTMR0 Position */ +#define MXC_F_MCR_PCLKDIS_LPTMR0 ((uint32_t)(0x1UL << MXC_F_MCR_PCLKDIS_LPTMR0_POS)) /**< PCLKDIS_LPTMR0 Mask */ -/**@} end of group MCR_RST_Register */ +#define MXC_F_MCR_PCLKDIS_LPTMR1_POS 1 /**< PCLKDIS_LPTMR1 Position */ +#define MXC_F_MCR_PCLKDIS_LPTMR1 ((uint32_t)(0x1UL << MXC_F_MCR_PCLKDIS_LPTMR1_POS)) /**< PCLKDIS_LPTMR1 Mask */ + +#define MXC_F_MCR_PCLKDIS_LPUART0_POS 2 /**< PCLKDIS_LPUART0 Position */ +#define MXC_F_MCR_PCLKDIS_LPUART0 ((uint32_t)(0x1UL << MXC_F_MCR_PCLKDIS_LPUART0_POS)) /**< PCLKDIS_LPUART0 Mask */ + +/**@} end of group MCR_PCLKDIS_Register */ /** * @ingroup mcr_registers - * @defgroup MCR_RTCTRIM MCR_RTCTRIM - * @brief RTC Trim Register. + * @defgroup MCR_AESKEY MCR_AESKEY + * @brief AES Key Pointer and Status. * @{ */ -#define MXC_F_MCR_RTCTRIM_TRIM_X1_POS 0 /**< RTCTRIM_TRIM_X1 Position */ -#define MXC_F_MCR_RTCTRIM_TRIM_X1 ((uint32_t)(0x1FUL << MXC_F_MCR_RTCTRIM_TRIM_X1_POS)) /**< RTCTRIM_TRIM_X1 Mask */ +#define MXC_F_MCR_AESKEY_PTR_POS 0 /**< AESKEY_PTR Position */ +#define MXC_F_MCR_AESKEY_PTR ((uint32_t)(0xFFFFUL << MXC_F_MCR_AESKEY_PTR_POS)) /**< AESKEY_PTR Mask */ -#define MXC_F_MCR_RTCTRIM_TRIM_X2_POS 8 /**< RTCTRIM_TRIM_X2 Position */ -#define MXC_F_MCR_RTCTRIM_TRIM_X2 ((uint32_t)(0x1FUL << MXC_F_MCR_RTCTRIM_TRIM_X2_POS)) /**< RTCTRIM_TRIM_X2 Mask */ +/**@} end of group MCR_AESKEY_Register */ -/**@} end of group MCR_RTCTRIM_Register */ +/** + * @ingroup mcr_registers + * @defgroup MCR_ADC_CFG0 MCR_ADC_CFG0 + * @brief ADC Cfig Register0. + * @{ + */ +#define MXC_F_MCR_ADC_CFG0_LP_5K_DIS_POS 0 /**< ADC_CFG0_LP_5K_DIS Position */ +#define MXC_F_MCR_ADC_CFG0_LP_5K_DIS ((uint32_t)(0x1UL << MXC_F_MCR_ADC_CFG0_LP_5K_DIS_POS)) /**< ADC_CFG0_LP_5K_DIS Mask */ + +#define MXC_F_MCR_ADC_CFG0_LP_50K_DIS_POS 1 /**< ADC_CFG0_LP_50K_DIS Position */ +#define MXC_F_MCR_ADC_CFG0_LP_50K_DIS ((uint32_t)(0x1UL << MXC_F_MCR_ADC_CFG0_LP_50K_DIS_POS)) /**< ADC_CFG0_LP_50K_DIS Mask */ + +#define MXC_F_MCR_ADC_CFG0_EXT_REF_POS 2 /**< ADC_CFG0_EXT_REF Position */ +#define MXC_F_MCR_ADC_CFG0_EXT_REF ((uint32_t)(0x1UL << MXC_F_MCR_ADC_CFG0_EXT_REF_POS)) /**< ADC_CFG0_EXT_REF Mask */ + +#define MXC_F_MCR_ADC_CFG0_REF_SEL_POS 3 /**< ADC_CFG0_REF_SEL Position */ +#define MXC_F_MCR_ADC_CFG0_REF_SEL ((uint32_t)(0x1UL << MXC_F_MCR_ADC_CFG0_REF_SEL_POS)) /**< ADC_CFG0_REF_SEL Mask */ + +/**@} end of group MCR_ADC_CFG0_Register */ /** * @ingroup mcr_registers - * @defgroup MCR_LDOCTRL MCR_LDOCTRL - * @brief LDO Control Register. + * @defgroup MCR_ADC_CFG1 MCR_ADC_CFG1 + * @brief ADC Config Register1. * @{ */ -#define MXC_F_MCR_LDOCTRL_0P9V_EN_POS 0 /**< LDOCTRL_0P9V_EN Position */ -#define MXC_F_MCR_LDOCTRL_0P9V_EN ((uint32_t)(0x1UL << MXC_F_MCR_LDOCTRL_0P9V_EN_POS)) /**< LDOCTRL_0P9V_EN Mask */ +#define MXC_F_MCR_ADC_CFG1_CH0_PU_DYN_POS 0 /**< ADC_CFG1_CH0_PU_DYN Position */ +#define MXC_F_MCR_ADC_CFG1_CH0_PU_DYN ((uint32_t)(0x1UL << MXC_F_MCR_ADC_CFG1_CH0_PU_DYN_POS)) /**< ADC_CFG1_CH0_PU_DYN Mask */ + +#define MXC_F_MCR_ADC_CFG1_CH1_PU_DYN_POS 1 /**< ADC_CFG1_CH1_PU_DYN Position */ +#define MXC_F_MCR_ADC_CFG1_CH1_PU_DYN ((uint32_t)(0x1UL << MXC_F_MCR_ADC_CFG1_CH1_PU_DYN_POS)) /**< ADC_CFG1_CH1_PU_DYN Mask */ + +#define MXC_F_MCR_ADC_CFG1_CH2_PU_DYN_POS 2 /**< ADC_CFG1_CH2_PU_DYN Position */ +#define MXC_F_MCR_ADC_CFG1_CH2_PU_DYN ((uint32_t)(0x1UL << MXC_F_MCR_ADC_CFG1_CH2_PU_DYN_POS)) /**< ADC_CFG1_CH2_PU_DYN Mask */ + +#define MXC_F_MCR_ADC_CFG1_CH3_PU_DYN_POS 3 /**< ADC_CFG1_CH3_PU_DYN Position */ +#define MXC_F_MCR_ADC_CFG1_CH3_PU_DYN ((uint32_t)(0x1UL << MXC_F_MCR_ADC_CFG1_CH3_PU_DYN_POS)) /**< ADC_CFG1_CH3_PU_DYN Mask */ -/**@} end of group MCR_LDOCTRL_Register */ +#define MXC_F_MCR_ADC_CFG1_CH4_PU_DYN_POS 4 /**< ADC_CFG1_CH4_PU_DYN Position */ +#define MXC_F_MCR_ADC_CFG1_CH4_PU_DYN ((uint32_t)(0x1UL << MXC_F_MCR_ADC_CFG1_CH4_PU_DYN_POS)) /**< ADC_CFG1_CH4_PU_DYN Mask */ + +#define MXC_F_MCR_ADC_CFG1_CH5_PU_DYN_POS 5 /**< ADC_CFG1_CH5_PU_DYN Position */ +#define MXC_F_MCR_ADC_CFG1_CH5_PU_DYN ((uint32_t)(0x1UL << MXC_F_MCR_ADC_CFG1_CH5_PU_DYN_POS)) /**< ADC_CFG1_CH5_PU_DYN Mask */ + +#define MXC_F_MCR_ADC_CFG1_CH6_PU_DYN_POS 6 /**< ADC_CFG1_CH6_PU_DYN Position */ +#define MXC_F_MCR_ADC_CFG1_CH6_PU_DYN ((uint32_t)(0x1UL << MXC_F_MCR_ADC_CFG1_CH6_PU_DYN_POS)) /**< ADC_CFG1_CH6_PU_DYN Mask */ + +#define MXC_F_MCR_ADC_CFG1_CH7_PU_DYN_POS 7 /**< ADC_CFG1_CH7_PU_DYN Position */ +#define MXC_F_MCR_ADC_CFG1_CH7_PU_DYN ((uint32_t)(0x1UL << MXC_F_MCR_ADC_CFG1_CH7_PU_DYN_POS)) /**< ADC_CFG1_CH7_PU_DYN Mask */ + +#define MXC_F_MCR_ADC_CFG1_CH8_PU_DYN_POS 8 /**< ADC_CFG1_CH8_PU_DYN Position */ +#define MXC_F_MCR_ADC_CFG1_CH8_PU_DYN ((uint32_t)(0x1UL << MXC_F_MCR_ADC_CFG1_CH8_PU_DYN_POS)) /**< ADC_CFG1_CH8_PU_DYN Mask */ + +#define MXC_F_MCR_ADC_CFG1_CH9_PU_DYN_POS 9 /**< ADC_CFG1_CH9_PU_DYN Position */ +#define MXC_F_MCR_ADC_CFG1_CH9_PU_DYN ((uint32_t)(0x1UL << MXC_F_MCR_ADC_CFG1_CH9_PU_DYN_POS)) /**< ADC_CFG1_CH9_PU_DYN Mask */ + +#define MXC_F_MCR_ADC_CFG1_CH10_PU_DYN_POS 10 /**< ADC_CFG1_CH10_PU_DYN Position */ +#define MXC_F_MCR_ADC_CFG1_CH10_PU_DYN ((uint32_t)(0x1UL << MXC_F_MCR_ADC_CFG1_CH10_PU_DYN_POS)) /**< ADC_CFG1_CH10_PU_DYN Mask */ + +#define MXC_F_MCR_ADC_CFG1_CH11_PU_DYN_POS 11 /**< ADC_CFG1_CH11_PU_DYN Position */ +#define MXC_F_MCR_ADC_CFG1_CH11_PU_DYN ((uint32_t)(0x1UL << MXC_F_MCR_ADC_CFG1_CH11_PU_DYN_POS)) /**< ADC_CFG1_CH11_PU_DYN Mask */ + +#define MXC_F_MCR_ADC_CFG1_CH12_PU_DYN_POS 12 /**< ADC_CFG1_CH12_PU_DYN Position */ +#define MXC_F_MCR_ADC_CFG1_CH12_PU_DYN ((uint32_t)(0x1UL << MXC_F_MCR_ADC_CFG1_CH12_PU_DYN_POS)) /**< ADC_CFG1_CH12_PU_DYN Mask */ + +/**@} end of group MCR_ADC_CFG1_Register */ /** * @ingroup mcr_registers - * @defgroup MCR_PWRMONST MCR_PWRMONST - * @brief Power Monitor Statuses Register. + * @defgroup MCR_ADC_CFG2 MCR_ADC_CFG2 + * @brief ADC Config Register2. * @{ */ -#define MXC_F_MCR_PWRMONST_PORZ_VLOSS_POS 0 /**< PWRMONST_PORZ_VLOSS Position */ -#define MXC_F_MCR_PWRMONST_PORZ_VLOSS ((uint32_t)(0x1UL << MXC_F_MCR_PWRMONST_PORZ_VLOSS_POS)) /**< PWRMONST_PORZ_VLOSS Mask */ +#define MXC_F_MCR_ADC_CFG2_CH0_POS 0 /**< ADC_CFG2_CH0 Position */ +#define MXC_F_MCR_ADC_CFG2_CH0 ((uint32_t)(0x3UL << MXC_F_MCR_ADC_CFG2_CH0_POS)) /**< ADC_CFG2_CH0 Mask */ +#define MXC_V_MCR_ADC_CFG2_CH0_DIV1 ((uint32_t)0x0UL) /**< ADC_CFG2_CH0_DIV1 Value */ +#define MXC_S_MCR_ADC_CFG2_CH0_DIV1 (MXC_V_MCR_ADC_CFG2_CH0_DIV1 << MXC_F_MCR_ADC_CFG2_CH0_POS) /**< ADC_CFG2_CH0_DIV1 Setting */ +#define MXC_V_MCR_ADC_CFG2_CH0_DIV2_5K ((uint32_t)0x1UL) /**< ADC_CFG2_CH0_DIV2_5K Value */ +#define MXC_S_MCR_ADC_CFG2_CH0_DIV2_5K (MXC_V_MCR_ADC_CFG2_CH0_DIV2_5K << MXC_F_MCR_ADC_CFG2_CH0_POS) /**< ADC_CFG2_CH0_DIV2_5K Setting */ +#define MXC_V_MCR_ADC_CFG2_CH0_DIV2_50K ((uint32_t)0x2UL) /**< ADC_CFG2_CH0_DIV2_50K Value */ +#define MXC_S_MCR_ADC_CFG2_CH0_DIV2_50K (MXC_V_MCR_ADC_CFG2_CH0_DIV2_50K << MXC_F_MCR_ADC_CFG2_CH0_POS) /**< ADC_CFG2_CH0_DIV2_50K Setting */ + +#define MXC_F_MCR_ADC_CFG2_CH1_POS 2 /**< ADC_CFG2_CH1 Position */ +#define MXC_F_MCR_ADC_CFG2_CH1 ((uint32_t)(0x3UL << MXC_F_MCR_ADC_CFG2_CH1_POS)) /**< ADC_CFG2_CH1 Mask */ + +#define MXC_F_MCR_ADC_CFG2_CH2_POS 4 /**< ADC_CFG2_CH2 Position */ +#define MXC_F_MCR_ADC_CFG2_CH2 ((uint32_t)(0x3UL << MXC_F_MCR_ADC_CFG2_CH2_POS)) /**< ADC_CFG2_CH2 Mask */ + +#define MXC_F_MCR_ADC_CFG2_CH3_POS 6 /**< ADC_CFG2_CH3 Position */ +#define MXC_F_MCR_ADC_CFG2_CH3 ((uint32_t)(0x3UL << MXC_F_MCR_ADC_CFG2_CH3_POS)) /**< ADC_CFG2_CH3 Mask */ -#define MXC_F_MCR_PWRMONST_PORZ_VBAT_POS 1 /**< PWRMONST_PORZ_VBAT Position */ -#define MXC_F_MCR_PWRMONST_PORZ_VBAT ((uint32_t)(0x1UL << MXC_F_MCR_PWRMONST_PORZ_VBAT_POS)) /**< PWRMONST_PORZ_VBAT Mask */ +#define MXC_F_MCR_ADC_CFG2_CH4_POS 8 /**< ADC_CFG2_CH4 Position */ +#define MXC_F_MCR_ADC_CFG2_CH4 ((uint32_t)(0x3UL << MXC_F_MCR_ADC_CFG2_CH4_POS)) /**< ADC_CFG2_CH4 Mask */ -#define MXC_F_MCR_PWRMONST_PORZ_VRTC_POS 2 /**< PWRMONST_PORZ_VRTC Position */ -#define MXC_F_MCR_PWRMONST_PORZ_VRTC ((uint32_t)(0x1UL << MXC_F_MCR_PWRMONST_PORZ_VRTC_POS)) /**< PWRMONST_PORZ_VRTC Mask */ +#define MXC_F_MCR_ADC_CFG2_CH5_POS 10 /**< ADC_CFG2_CH5 Position */ +#define MXC_F_MCR_ADC_CFG2_CH5 ((uint32_t)(0x3UL << MXC_F_MCR_ADC_CFG2_CH5_POS)) /**< ADC_CFG2_CH5 Mask */ -#define MXC_F_MCR_PWRMONST_PORZ_VDDC_POS 5 /**< PWRMONST_PORZ_VDDC Position */ -#define MXC_F_MCR_PWRMONST_PORZ_VDDC ((uint32_t)(0x1UL << MXC_F_MCR_PWRMONST_PORZ_VDDC_POS)) /**< PWRMONST_PORZ_VDDC Mask */ +#define MXC_F_MCR_ADC_CFG2_CH6_POS 12 /**< ADC_CFG2_CH6 Position */ +#define MXC_F_MCR_ADC_CFG2_CH6 ((uint32_t)(0x3UL << MXC_F_MCR_ADC_CFG2_CH6_POS)) /**< ADC_CFG2_CH6 Mask */ -#define MXC_F_MCR_PWRMONST_PORZ_VDDA_POS 6 /**< PWRMONST_PORZ_VDDA Position */ -#define MXC_F_MCR_PWRMONST_PORZ_VDDA ((uint32_t)(0x1UL << MXC_F_MCR_PWRMONST_PORZ_VDDA_POS)) /**< PWRMONST_PORZ_VDDA Mask */ +#define MXC_F_MCR_ADC_CFG2_CH7_POS 14 /**< ADC_CFG2_CH7 Position */ +#define MXC_F_MCR_ADC_CFG2_CH7 ((uint32_t)(0x3UL << MXC_F_MCR_ADC_CFG2_CH7_POS)) /**< ADC_CFG2_CH7 Mask */ -#define MXC_F_MCR_PWRMONST_PORZ_VDDB_POS 7 /**< PWRMONST_PORZ_VDDB Position */ -#define MXC_F_MCR_PWRMONST_PORZ_VDDB ((uint32_t)(0x1UL << MXC_F_MCR_PWRMONST_PORZ_VDDB_POS)) /**< PWRMONST_PORZ_VDDB Mask */ +#define MXC_F_MCR_ADC_CFG2_CH8_POS 16 /**< ADC_CFG2_CH8 Position */ +#define MXC_F_MCR_ADC_CFG2_CH8 ((uint32_t)(0x3UL << MXC_F_MCR_ADC_CFG2_CH8_POS)) /**< ADC_CFG2_CH8 Mask */ -#define MXC_F_MCR_PWRMONST_RSTZ_VDDC_POS 9 /**< PWRMONST_RSTZ_VDDC Position */ -#define MXC_F_MCR_PWRMONST_RSTZ_VDDC ((uint32_t)(0x1UL << MXC_F_MCR_PWRMONST_RSTZ_VDDC_POS)) /**< PWRMONST_RSTZ_VDDC Mask */ +#define MXC_F_MCR_ADC_CFG2_CH9_POS 18 /**< ADC_CFG2_CH9 Position */ +#define MXC_F_MCR_ADC_CFG2_CH9 ((uint32_t)(0x3UL << MXC_F_MCR_ADC_CFG2_CH9_POS)) /**< ADC_CFG2_CH9 Mask */ -#define MXC_F_MCR_PWRMONST_RSTZ_VDDA_POS 10 /**< PWRMONST_RSTZ_VDDA Position */ -#define MXC_F_MCR_PWRMONST_RSTZ_VDDA ((uint32_t)(0x1UL << MXC_F_MCR_PWRMONST_RSTZ_VDDA_POS)) /**< PWRMONST_RSTZ_VDDA Mask */ +#define MXC_F_MCR_ADC_CFG2_CH10_POS 20 /**< ADC_CFG2_CH10 Position */ +#define MXC_F_MCR_ADC_CFG2_CH10 ((uint32_t)(0x3UL << MXC_F_MCR_ADC_CFG2_CH10_POS)) /**< ADC_CFG2_CH10 Mask */ -#define MXC_F_MCR_PWRMONST_RSTZ_VDDB_POS 11 /**< PWRMONST_RSTZ_VDDB Position */ -#define MXC_F_MCR_PWRMONST_RSTZ_VDDB ((uint32_t)(0x1UL << MXC_F_MCR_PWRMONST_RSTZ_VDDB_POS)) /**< PWRMONST_RSTZ_VDDB Mask */ +#define MXC_F_MCR_ADC_CFG2_CH11_POS 22 /**< ADC_CFG2_CH11 Position */ +#define MXC_F_MCR_ADC_CFG2_CH11 ((uint32_t)(0x3UL << MXC_F_MCR_ADC_CFG2_CH11_POS)) /**< ADC_CFG2_CH11 Mask */ -#define MXC_F_MCR_PWRMONST_RSTZ_VDDIO_POS 12 /**< PWRMONST_RSTZ_VDDIO Position */ -#define MXC_F_MCR_PWRMONST_RSTZ_VDDIO ((uint32_t)(0x1UL << MXC_F_MCR_PWRMONST_RSTZ_VDDIO_POS)) /**< PWRMONST_RSTZ_VDDIO Mask */ +#define MXC_F_MCR_ADC_CFG2_CH12_POS 24 /**< ADC_CFG2_CH12 Position */ +#define MXC_F_MCR_ADC_CFG2_CH12 ((uint32_t)(0x3UL << MXC_F_MCR_ADC_CFG2_CH12_POS)) /**< ADC_CFG2_CH12 Mask */ -#define MXC_F_MCR_PWRMONST_RSTZ_VDDIOH_POS 13 /**< PWRMONST_RSTZ_VDDIOH Position */ -#define MXC_F_MCR_PWRMONST_RSTZ_VDDIOH ((uint32_t)(0x1UL << MXC_F_MCR_PWRMONST_RSTZ_VDDIOH_POS)) /**< PWRMONST_RSTZ_VDDIOH Mask */ +/**@} end of group MCR_ADC_CFG2_Register */ -#define MXC_F_MCR_PWRMONST_RSTZ_VRTC_POS 14 /**< PWRMONST_RSTZ_VRTC Position */ -#define MXC_F_MCR_PWRMONST_RSTZ_VRTC ((uint32_t)(0x1UL << MXC_F_MCR_PWRMONST_RSTZ_VRTC_POS)) /**< PWRMONST_RSTZ_VRTC Mask */ +/** + * @ingroup mcr_registers + * @defgroup MCR_ADC_CFG3 MCR_ADC_CFG3 + * @brief ADC Config Register3. + * @{ + */ +#define MXC_F_MCR_ADC_CFG3_VREFM_POS 0 /**< ADC_CFG3_VREFM Position */ +#define MXC_F_MCR_ADC_CFG3_VREFM ((uint32_t)(0x7FUL << MXC_F_MCR_ADC_CFG3_VREFM_POS)) /**< ADC_CFG3_VREFM Mask */ -#define MXC_F_MCR_PWRMONST_RSTZ_LDO_0P9V_POS 16 /**< PWRMONST_RSTZ_LDO_0P9V Position */ -#define MXC_F_MCR_PWRMONST_RSTZ_LDO_0P9V ((uint32_t)(0x1UL << MXC_F_MCR_PWRMONST_RSTZ_LDO_0P9V_POS)) /**< PWRMONST_RSTZ_LDO_0P9V Mask */ +#define MXC_F_MCR_ADC_CFG3_VREFP_POS 8 /**< ADC_CFG3_VREFP Position */ +#define MXC_F_MCR_ADC_CFG3_VREFP ((uint32_t)(0x7FUL << MXC_F_MCR_ADC_CFG3_VREFP_POS)) /**< ADC_CFG3_VREFP Mask */ -#define MXC_F_MCR_PWRMONST_RSTZ_VDDCA_POS 17 /**< PWRMONST_RSTZ_VDDCA Position */ -#define MXC_F_MCR_PWRMONST_RSTZ_VDDCA ((uint32_t)(0x1UL << MXC_F_MCR_PWRMONST_RSTZ_VDDCA_POS)) /**< PWRMONST_RSTZ_VDDCA Mask */ +#define MXC_F_MCR_ADC_CFG3_IDRV_POS 16 /**< ADC_CFG3_IDRV Position */ +#define MXC_F_MCR_ADC_CFG3_IDRV ((uint32_t)(0xFUL << MXC_F_MCR_ADC_CFG3_IDRV_POS)) /**< ADC_CFG3_IDRV Mask */ -#define MXC_F_MCR_PWRMONST_RSTZ_VCOREHV_POS 18 /**< PWRMONST_RSTZ_VCOREHV Position */ -#define MXC_F_MCR_PWRMONST_RSTZ_VCOREHV ((uint32_t)(0x1UL << MXC_F_MCR_PWRMONST_RSTZ_VCOREHV_POS)) /**< PWRMONST_RSTZ_VCOREHV Mask */ +#define MXC_F_MCR_ADC_CFG3_VCM_POS 20 /**< ADC_CFG3_VCM Position */ +#define MXC_F_MCR_ADC_CFG3_VCM ((uint32_t)(0x3UL << MXC_F_MCR_ADC_CFG3_VCM_POS)) /**< ADC_CFG3_VCM Mask */ -#define MXC_F_MCR_PWRMONST_RSTZ_VDDIOHV_POS 19 /**< PWRMONST_RSTZ_VDDIOHV Position */ -#define MXC_F_MCR_PWRMONST_RSTZ_VDDIOHV ((uint32_t)(0x1UL << MXC_F_MCR_PWRMONST_RSTZ_VDDIOHV_POS)) /**< PWRMONST_RSTZ_VDDIOHV Mask */ +#define MXC_F_MCR_ADC_CFG3_ATB_POS 22 /**< ADC_CFG3_ATB Position */ +#define MXC_F_MCR_ADC_CFG3_ATB ((uint32_t)(0x3UL << MXC_F_MCR_ADC_CFG3_ATB_POS)) /**< ADC_CFG3_ATB Mask */ -#define MXC_F_MCR_PWRMONST_RSTZ_VDDIOHHV_POS 20 /**< PWRMONST_RSTZ_VDDIOHHV Position */ -#define MXC_F_MCR_PWRMONST_RSTZ_VDDIOHHV ((uint32_t)(0x1UL << MXC_F_MCR_PWRMONST_RSTZ_VDDIOHHV_POS)) /**< PWRMONST_RSTZ_VDDIOHHV Mask */ +#define MXC_F_MCR_ADC_CFG3_D_IBOOST_POS 24 /**< ADC_CFG3_D_IBOOST Position */ +#define MXC_F_MCR_ADC_CFG3_D_IBOOST ((uint32_t)(0x1UL << MXC_F_MCR_ADC_CFG3_D_IBOOST_POS)) /**< ADC_CFG3_D_IBOOST Mask */ -/**@} end of group MCR_PWRMONST_Register */ +/**@} end of group MCR_ADC_CFG3_Register */ #ifdef __cplusplus } #endif -#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_MCR_REGS_H_ +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32672_INCLUDE_MCR_REGS_H_ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32572/Include/msradc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32572/Include/msradc_regs.h index 3233c2eff37..6059ff094a9 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32572/Include/msradc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32572/Include/msradc_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32572/Include/otp_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32572/Include/otp_regs.h index d52785030be..81981bdf4e2 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32572/Include/otp_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32572/Include/otp_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32572/Include/pt_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32572/Include/pt_regs.h index a6c7cc59447..21e56a42b54 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32572/Include/pt_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32572/Include/pt_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32572/Include/ptg_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32572/Include/ptg_regs.h index 1408bdde806..cc3171b7307 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32572/Include/ptg_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32572/Include/ptg_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32572/Include/pwrseq_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32572/Include/pwrseq_regs.h index c14923bfb1c..63406b1dd78 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32572/Include/pwrseq_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32572/Include/pwrseq_regs.h @@ -25,8 +25,8 @@ * ******************************************************************************/ -#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_PWRSEQ_REGS_H_ -#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_PWRSEQ_REGS_H_ +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32672_INCLUDE_PWRSEQ_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32672_INCLUDE_PWRSEQ_REGS_H_ /* **** Includes **** */ #include @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile @@ -74,23 +78,19 @@ extern "C" { * Structure type to access the PWRSEQ Registers. */ typedef struct { - __IO uint32_t lpctrl; /**< \b 0x00: PWRSEQ LPCTRL Register */ - __IO uint32_t lpwkfl0; /**< \b 0x04: PWRSEQ LPWKFL0 Register */ + __IO uint32_t lpcn; /**< \b 0x00: PWRSEQ LPCN Register */ + __IO uint32_t lpwkst0; /**< \b 0x04: PWRSEQ LPWKST0 Register */ __IO uint32_t lpwken0; /**< \b 0x08: PWRSEQ LPWKEN0 Register */ - __IO uint32_t lpwkfl1; /**< \b 0x0C: PWRSEQ LPWKFL1 Register */ + __IO uint32_t lpwkst1; /**< \b 0x0C: PWRSEQ LPWKST1 Register */ __IO uint32_t lpwken1; /**< \b 0x10: PWRSEQ LPWKEN1 Register */ - __IO uint32_t lpwkfl2; /**< \b 0x14: PWRSEQ LPWKFL2 Register */ - __IO uint32_t lpwken2; /**< \b 0x18: PWRSEQ LPWKEN2 Register */ - __IO uint32_t lpwkfl3; /**< \b 0x1C: PWRSEQ LPWKFL3 Register */ - __IO uint32_t lpwken3; /**< \b 0x20: PWRSEQ LPWKEN3 Register */ - __R uint32_t rsv_0x24_0x2f[3]; - __IO uint32_t lppwkfl; /**< \b 0x30: PWRSEQ LPPWKFL Register */ + __R uint32_t rsv_0x14_0x2f[7]; + __IO uint32_t lppwkst; /**< \b 0x30: PWRSEQ LPPWKST Register */ __IO uint32_t lppwken; /**< \b 0x34: PWRSEQ LPPWKEN Register */ __R uint32_t rsv_0x38_0x3f[2]; __IO uint32_t lpmemsd; /**< \b 0x40: PWRSEQ LPMEMSD Register */ - __IO uint32_t lpvddpd; /**< \b 0x44: PWRSEQ LPVDDPD Register */ - __IO uint32_t gp0; /**< \b 0x48: PWRSEQ GP0 Register */ - __IO uint32_t gp1; /**< \b 0x4C: PWRSEQ GP1 Register */ + __R uint32_t rsv_0x44; + __IO uint32_t gpr0; /**< \b 0x48: PWRSEQ GPR0 Register */ + __IO uint32_t gpr1; /**< \b 0x4C: PWRSEQ GPR1 Register */ } mxc_pwrseq_regs_t; /* Register offsets for module PWRSEQ */ @@ -100,92 +100,109 @@ typedef struct { * @brief PWRSEQ Peripheral Register Offsets from the PWRSEQ Base Peripheral Address. * @{ */ -#define MXC_R_PWRSEQ_LPCTRL ((uint32_t)0x00000000UL) /**< Offset from PWRSEQ Base Address: 0x0000 */ -#define MXC_R_PWRSEQ_LPWKFL0 ((uint32_t)0x00000004UL) /**< Offset from PWRSEQ Base Address: 0x0004 */ +#define MXC_R_PWRSEQ_LPCN ((uint32_t)0x00000000UL) /**< Offset from PWRSEQ Base Address: 0x0000 */ +#define MXC_R_PWRSEQ_LPWKST0 ((uint32_t)0x00000004UL) /**< Offset from PWRSEQ Base Address: 0x0004 */ #define MXC_R_PWRSEQ_LPWKEN0 ((uint32_t)0x00000008UL) /**< Offset from PWRSEQ Base Address: 0x0008 */ -#define MXC_R_PWRSEQ_LPWKFL1 ((uint32_t)0x0000000CUL) /**< Offset from PWRSEQ Base Address: 0x000C */ +#define MXC_R_PWRSEQ_LPWKST1 ((uint32_t)0x0000000CUL) /**< Offset from PWRSEQ Base Address: 0x000C */ #define MXC_R_PWRSEQ_LPWKEN1 ((uint32_t)0x00000010UL) /**< Offset from PWRSEQ Base Address: 0x0010 */ -#define MXC_R_PWRSEQ_LPWKFL2 ((uint32_t)0x00000014UL) /**< Offset from PWRSEQ Base Address: 0x0014 */ -#define MXC_R_PWRSEQ_LPWKEN2 ((uint32_t)0x00000018UL) /**< Offset from PWRSEQ Base Address: 0x0018 */ -#define MXC_R_PWRSEQ_LPWKFL3 ((uint32_t)0x0000001CUL) /**< Offset from PWRSEQ Base Address: 0x001C */ -#define MXC_R_PWRSEQ_LPWKEN3 ((uint32_t)0x00000020UL) /**< Offset from PWRSEQ Base Address: 0x0020 */ -#define MXC_R_PWRSEQ_LPPWKFL ((uint32_t)0x00000030UL) /**< Offset from PWRSEQ Base Address: 0x0030 */ +#define MXC_R_PWRSEQ_LPPWKST ((uint32_t)0x00000030UL) /**< Offset from PWRSEQ Base Address: 0x0030 */ #define MXC_R_PWRSEQ_LPPWKEN ((uint32_t)0x00000034UL) /**< Offset from PWRSEQ Base Address: 0x0034 */ #define MXC_R_PWRSEQ_LPMEMSD ((uint32_t)0x00000040UL) /**< Offset from PWRSEQ Base Address: 0x0040 */ -#define MXC_R_PWRSEQ_LPVDDPD ((uint32_t)0x00000044UL) /**< Offset from PWRSEQ Base Address: 0x0044 */ -#define MXC_R_PWRSEQ_GP0 ((uint32_t)0x00000048UL) /**< Offset from PWRSEQ Base Address: 0x0048 */ -#define MXC_R_PWRSEQ_GP1 ((uint32_t)0x0000004CUL) /**< Offset from PWRSEQ Base Address: 0x004C */ +#define MXC_R_PWRSEQ_GPR0 ((uint32_t)0x00000048UL) /**< Offset from PWRSEQ Base Address: 0x0048 */ +#define MXC_R_PWRSEQ_GPR1 ((uint32_t)0x0000004CUL) /**< Offset from PWRSEQ Base Address: 0x004C */ /**@} end of group pwrseq_registers */ /** * @ingroup pwrseq_registers - * @defgroup PWRSEQ_LPCTRL PWRSEQ_LPCTRL + * @defgroup PWRSEQ_LPCN PWRSEQ_LPCN * @brief Low Power Control Register. * @{ */ -#define MXC_F_PWRSEQ_LPCTRL_RAMRET_EN_POS 0 /**< LPCTRL_RAMRET_EN Position */ -#define MXC_F_PWRSEQ_LPCTRL_RAMRET_EN ((uint32_t)(0xFUL << MXC_F_PWRSEQ_LPCTRL_RAMRET_EN_POS)) /**< LPCTRL_RAMRET_EN Mask */ +#define MXC_F_PWRSEQ_LPCN_RAM0RET_EN_POS 0 /**< LPCN_RAM0RET_EN Position */ +#define MXC_F_PWRSEQ_LPCN_RAM0RET_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_RAM0RET_EN_POS)) /**< LPCN_RAM0RET_EN Mask */ + +#define MXC_F_PWRSEQ_LPCN_RAM1RET_EN_POS 1 /**< LPCN_RAM1RET_EN Position */ +#define MXC_F_PWRSEQ_LPCN_RAM1RET_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_RAM1RET_EN_POS)) /**< LPCN_RAM1RET_EN Mask */ + +#define MXC_F_PWRSEQ_LPCN_RAM2RET_EN_POS 2 /**< LPCN_RAM2RET_EN Position */ +#define MXC_F_PWRSEQ_LPCN_RAM2RET_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_RAM2RET_EN_POS)) /**< LPCN_RAM2RET_EN Mask */ + +#define MXC_F_PWRSEQ_LPCN_RAM3RET_EN_POS 3 /**< LPCN_RAM3RET_EN Position */ +#define MXC_F_PWRSEQ_LPCN_RAM3RET_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_RAM3RET_EN_POS)) /**< LPCN_RAM3RET_EN Mask */ + +#define MXC_F_PWRSEQ_LPCN_OVR_POS 4 /**< LPCN_OVR Position */ +#define MXC_F_PWRSEQ_LPCN_OVR ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPCN_OVR_POS)) /**< LPCN_OVR Mask */ +#define MXC_V_PWRSEQ_LPCN_OVR_0_9V ((uint32_t)0x0UL) /**< LPCN_OVR_0_9V Value */ +#define MXC_S_PWRSEQ_LPCN_OVR_0_9V (MXC_V_PWRSEQ_LPCN_OVR_0_9V << MXC_F_PWRSEQ_LPCN_OVR_POS) /**< LPCN_OVR_0_9V Setting */ +#define MXC_V_PWRSEQ_LPCN_OVR_1_0V ((uint32_t)0x1UL) /**< LPCN_OVR_1_0V Value */ +#define MXC_S_PWRSEQ_LPCN_OVR_1_0V (MXC_V_PWRSEQ_LPCN_OVR_1_0V << MXC_F_PWRSEQ_LPCN_OVR_POS) /**< LPCN_OVR_1_0V Setting */ +#define MXC_V_PWRSEQ_LPCN_OVR_1_1V ((uint32_t)0x2UL) /**< LPCN_OVR_1_1V Value */ +#define MXC_S_PWRSEQ_LPCN_OVR_1_1V (MXC_V_PWRSEQ_LPCN_OVR_1_1V << MXC_F_PWRSEQ_LPCN_OVR_POS) /**< LPCN_OVR_1_1V Setting */ -#define MXC_F_PWRSEQ_LPCTRL_OVR_POS 4 /**< LPCTRL_OVR Position */ -#define MXC_F_PWRSEQ_LPCTRL_OVR ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPCTRL_OVR_POS)) /**< LPCTRL_OVR Mask */ -#define MXC_V_PWRSEQ_LPCTRL_OVR_1_1V ((uint32_t)0x2UL) /**< LPCTRL_OVR_1_1V Value */ -#define MXC_S_PWRSEQ_LPCTRL_OVR_1_1V (MXC_V_PWRSEQ_LPCTRL_OVR_1_1V << MXC_F_PWRSEQ_LPCTRL_OVR_POS) /**< LPCTRL_OVR_1_1V Setting */ +#define MXC_F_PWRSEQ_LPCN_VCORE_DET_BYPASS_POS 6 /**< LPCN_VCORE_DET_BYPASS Position */ +#define MXC_F_PWRSEQ_LPCN_VCORE_DET_BYPASS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VCORE_DET_BYPASS_POS)) /**< LPCN_VCORE_DET_BYPASS Mask */ -#define MXC_F_PWRSEQ_LPCTRL_RETREG_EN_POS 8 /**< LPCTRL_RETREG_EN Position */ -#define MXC_F_PWRSEQ_LPCTRL_RETREG_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCTRL_RETREG_EN_POS)) /**< LPCTRL_RETREG_EN Mask */ +#define MXC_F_PWRSEQ_LPCN_FVDDEN_POS 7 /**< LPCN_FVDDEN Position */ +#define MXC_F_PWRSEQ_LPCN_FVDDEN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_FVDDEN_POS)) /**< LPCN_FVDDEN Mask */ -#define MXC_F_PWRSEQ_LPCTRL_FASTWK_EN_POS 10 /**< LPCTRL_FASTWK_EN Position */ -#define MXC_F_PWRSEQ_LPCTRL_FASTWK_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCTRL_FASTWK_EN_POS)) /**< LPCTRL_FASTWK_EN Mask */ +#define MXC_F_PWRSEQ_LPCN_RETREG_EN_POS 8 /**< LPCN_RETREG_EN Position */ +#define MXC_F_PWRSEQ_LPCN_RETREG_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_RETREG_EN_POS)) /**< LPCN_RETREG_EN Mask */ -#define MXC_F_PWRSEQ_LPCTRL_BGOFF_POS 11 /**< LPCTRL_BGOFF Position */ -#define MXC_F_PWRSEQ_LPCTRL_BGOFF ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCTRL_BGOFF_POS)) /**< LPCTRL_BGOFF Mask */ +#define MXC_F_PWRSEQ_LPCN_STORAGE_EN_POS 9 /**< LPCN_STORAGE_EN Position */ +#define MXC_F_PWRSEQ_LPCN_STORAGE_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_STORAGE_EN_POS)) /**< LPCN_STORAGE_EN Mask */ -#define MXC_F_PWRSEQ_LPCTRL_VCOREPOR_DIS_POS 12 /**< LPCTRL_VCOREPOR_DIS Position */ -#define MXC_F_PWRSEQ_LPCTRL_VCOREPOR_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCTRL_VCOREPOR_DIS_POS)) /**< LPCTRL_VCOREPOR_DIS Mask */ +#define MXC_F_PWRSEQ_LPCN_FASTWK_EN_POS 10 /**< LPCN_FASTWK_EN Position */ +#define MXC_F_PWRSEQ_LPCN_FASTWK_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_FASTWK_EN_POS)) /**< LPCN_FASTWK_EN Mask */ -#define MXC_F_PWRSEQ_LPCTRL_VDDIOHHVMON_DIS_POS 17 /**< LPCTRL_VDDIOHHVMON_DIS Position */ -#define MXC_F_PWRSEQ_LPCTRL_VDDIOHHVMON_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCTRL_VDDIOHHVMON_DIS_POS)) /**< LPCTRL_VDDIOHHVMON_DIS Mask */ +#define MXC_F_PWRSEQ_LPCN_BG_DIS_POS 11 /**< LPCN_BG_DIS Position */ +#define MXC_F_PWRSEQ_LPCN_BG_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_BG_DIS_POS)) /**< LPCN_BG_DIS Mask */ -#define MXC_F_PWRSEQ_LPCTRL_VDDIOHVMON_DIS_POS 18 /**< LPCTRL_VDDIOHVMON_DIS Position */ -#define MXC_F_PWRSEQ_LPCTRL_VDDIOHVMON_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCTRL_VDDIOHVMON_DIS_POS)) /**< LPCTRL_VDDIOHVMON_DIS Mask */ +#define MXC_F_PWRSEQ_LPCN_VCOREPOR_DIS_POS 12 /**< LPCN_VCOREPOR_DIS Position */ +#define MXC_F_PWRSEQ_LPCN_VCOREPOR_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VCOREPOR_DIS_POS)) /**< LPCN_VCOREPOR_DIS Mask */ -#define MXC_F_PWRSEQ_LPCTRL_VCOREHVMON_DIS_POS 19 /**< LPCTRL_VCOREHVMON_DIS Position */ -#define MXC_F_PWRSEQ_LPCTRL_VCOREHVMON_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCTRL_VCOREHVMON_DIS_POS)) /**< LPCTRL_VCOREHVMON_DIS Mask */ +#define MXC_F_PWRSEQ_LPCN_LDO_DIS_POS 16 /**< LPCN_LDO_DIS Position */ +#define MXC_F_PWRSEQ_LPCN_LDO_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_LDO_DIS_POS)) /**< LPCN_LDO_DIS Mask */ -#define MXC_F_PWRSEQ_LPCTRL_VCOREMON_DIS_POS 20 /**< LPCTRL_VCOREMON_DIS Position */ -#define MXC_F_PWRSEQ_LPCTRL_VCOREMON_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCTRL_VCOREMON_DIS_POS)) /**< LPCTRL_VCOREMON_DIS Mask */ +#define MXC_F_PWRSEQ_LPCN_VCORE_EXT_POS 17 /**< LPCN_VCORE_EXT Position */ +#define MXC_F_PWRSEQ_LPCN_VCORE_EXT ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VCORE_EXT_POS)) /**< LPCN_VCORE_EXT Mask */ -#define MXC_F_PWRSEQ_LPCTRL_VRTCMON_DIS_POS 21 /**< LPCTRL_VRTCMON_DIS Position */ -#define MXC_F_PWRSEQ_LPCTRL_VRTCMON_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCTRL_VRTCMON_DIS_POS)) /**< LPCTRL_VRTCMON_DIS Mask */ +#define MXC_F_PWRSEQ_LPCN_VCOREMON_DIS_POS 20 /**< LPCN_VCOREMON_DIS Position */ +#define MXC_F_PWRSEQ_LPCN_VCOREMON_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VCOREMON_DIS_POS)) /**< LPCN_VCOREMON_DIS Mask */ -#define MXC_F_PWRSEQ_LPCTRL_VDDAMON_DIS_POS 22 /**< LPCTRL_VDDAMON_DIS Position */ -#define MXC_F_PWRSEQ_LPCTRL_VDDAMON_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCTRL_VDDAMON_DIS_POS)) /**< LPCTRL_VDDAMON_DIS Mask */ +#define MXC_F_PWRSEQ_LPCN_VDDAMON_DIS_POS 22 /**< LPCN_VDDAMON_DIS Position */ +#define MXC_F_PWRSEQ_LPCN_VDDAMON_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VDDAMON_DIS_POS)) /**< LPCN_VDDAMON_DIS Mask */ -#define MXC_F_PWRSEQ_LPCTRL_VDDIOMON_DIS_POS 23 /**< LPCTRL_VDDIOMON_DIS Position */ -#define MXC_F_PWRSEQ_LPCTRL_VDDIOMON_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCTRL_VDDIOMON_DIS_POS)) /**< LPCTRL_VDDIOMON_DIS Mask */ +#define MXC_F_PWRSEQ_LPCN_PORVDDMON_DIS_POS 25 /**< LPCN_PORVDDMON_DIS Position */ +#define MXC_F_PWRSEQ_LPCN_PORVDDMON_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_PORVDDMON_DIS_POS)) /**< LPCN_PORVDDMON_DIS Mask */ -#define MXC_F_PWRSEQ_LPCTRL_VDDIOHMON_DIS_POS 24 /**< LPCTRL_VDDIOHMON_DIS Position */ -#define MXC_F_PWRSEQ_LPCTRL_VDDIOHMON_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCTRL_VDDIOHMON_DIS_POS)) /**< LPCTRL_VDDIOHMON_DIS Mask */ +#define MXC_F_PWRSEQ_LPCN_VBBMON_DIS_POS 27 /**< LPCN_VBBMON_DIS Position */ +#define MXC_F_PWRSEQ_LPCN_VBBMON_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VBBMON_DIS_POS)) /**< LPCN_VBBMON_DIS Mask */ -#define MXC_F_PWRSEQ_LPCTRL_VDDBMON_DIS_POS 27 /**< LPCTRL_VDDBMON_DIS Position */ -#define MXC_F_PWRSEQ_LPCTRL_VDDBMON_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCTRL_VDDBMON_DIS_POS)) /**< LPCTRL_VDDBMON_DIS Mask */ +#define MXC_F_PWRSEQ_LPCN_INRO_EN_POS 28 /**< LPCN_INRO_EN Position */ +#define MXC_F_PWRSEQ_LPCN_INRO_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_INRO_EN_POS)) /**< LPCN_INRO_EN Mask */ -#define MXC_F_PWRSEQ_LPCTRL_DEEPSLEEP_PDOUT_DIS_POS 30 /**< LPCTRL_DEEPSLEEP_PDOUT_DIS Position */ -#define MXC_F_PWRSEQ_LPCTRL_DEEPSLEEP_PDOUT_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCTRL_DEEPSLEEP_PDOUT_DIS_POS)) /**< LPCTRL_DEEPSLEEP_PDOUT_DIS Mask */ +#define MXC_F_PWRSEQ_LPCN_ERTCO_EN_POS 29 /**< LPCN_ERTCO_EN Position */ +#define MXC_F_PWRSEQ_LPCN_ERTCO_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_ERTCO_EN_POS)) /**< LPCN_ERTCO_EN Mask */ -/**@} end of group PWRSEQ_LPCTRL_Register */ +#define MXC_F_PWRSEQ_LPCN_TM_LPMODE_POS 30 /**< LPCN_TM_LPMODE Position */ +#define MXC_F_PWRSEQ_LPCN_TM_LPMODE ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_TM_LPMODE_POS)) /**< LPCN_TM_LPMODE Mask */ + +#define MXC_F_PWRSEQ_LPCN_TM_PWRSEQ_POS 31 /**< LPCN_TM_PWRSEQ Position */ +#define MXC_F_PWRSEQ_LPCN_TM_PWRSEQ ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_TM_PWRSEQ_POS)) /**< LPCN_TM_PWRSEQ Mask */ + +/**@} end of group PWRSEQ_LPCN_Register */ /** * @ingroup pwrseq_registers - * @defgroup PWRSEQ_LPWKFL0 PWRSEQ_LPWKFL0 + * @defgroup PWRSEQ_LPWKST0 PWRSEQ_LPWKST0 * @brief Low Power I/O Wakeup Status Register 0. This register indicates the low power * wakeup status for GPIO0. * @{ */ -#define MXC_F_PWRSEQ_LPWKFL0_WAKEST_POS 0 /**< LPWKFL0_WAKEST Position */ -#define MXC_F_PWRSEQ_LPWKFL0_WAKEST ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPWKFL0_WAKEST_POS)) /**< LPWKFL0_WAKEST Mask */ +#define MXC_F_PWRSEQ_LPWKST0_ST_POS 0 /**< LPWKST0_ST Position */ +#define MXC_F_PWRSEQ_LPWKST0_ST ((uint32_t)(0x7FFFFFFFUL << MXC_F_PWRSEQ_LPWKST0_ST_POS)) /**< LPWKST0_ST Mask */ -/**@} end of group PWRSEQ_LPWKFL0_Register */ +/**@} end of group PWRSEQ_LPWKST0_Register */ /** * @ingroup pwrseq_registers @@ -194,36 +211,42 @@ typedef struct { * functionality for GPIO0. * @{ */ -#define MXC_F_PWRSEQ_LPWKEN0_WAKEEN_POS 0 /**< LPWKEN0_WAKEEN Position */ -#define MXC_F_PWRSEQ_LPWKEN0_WAKEEN ((uint32_t)(0x7FFFFFFFUL << MXC_F_PWRSEQ_LPWKEN0_WAKEEN_POS)) /**< LPWKEN0_WAKEEN Mask */ +#define MXC_F_PWRSEQ_LPWKEN0_EN_POS 0 /**< LPWKEN0_EN Position */ +#define MXC_F_PWRSEQ_LPWKEN0_EN ((uint32_t)(0x7FFFFFFFUL << MXC_F_PWRSEQ_LPWKEN0_EN_POS)) /**< LPWKEN0_EN Mask */ /**@} end of group PWRSEQ_LPWKEN0_Register */ /** * @ingroup pwrseq_registers - * @defgroup PWRSEQ_LPPWKFL PWRSEQ_LPPWKFL + * @defgroup PWRSEQ_LPPWKST PWRSEQ_LPPWKST * @brief Low Power Peripheral Wakeup Status Register. * @{ */ -#define MXC_F_PWRSEQ_LPPWKFL_USBLS_POS 0 /**< LPPWKFL_USBLS Position */ -#define MXC_F_PWRSEQ_LPPWKFL_USBLS ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPPWKFL_USBLS_POS)) /**< LPPWKFL_USBLS Mask */ +#define MXC_F_PWRSEQ_LPPWKST_LPTMR0_POS 0 /**< LPPWKST_LPTMR0 Position */ +#define MXC_F_PWRSEQ_LPPWKST_LPTMR0 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKST_LPTMR0_POS)) /**< LPPWKST_LPTMR0 Mask */ + +#define MXC_F_PWRSEQ_LPPWKST_LPTMR1_POS 1 /**< LPPWKST_LPTMR1 Position */ +#define MXC_F_PWRSEQ_LPPWKST_LPTMR1 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKST_LPTMR1_POS)) /**< LPPWKST_LPTMR1 Mask */ -#define MXC_F_PWRSEQ_LPPWKFL_USBVBUS_POS 2 /**< LPPWKFL_USBVBUS Position */ -#define MXC_F_PWRSEQ_LPPWKFL_USBVBUS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKFL_USBVBUS_POS)) /**< LPPWKFL_USBVBUS Mask */ +#define MXC_F_PWRSEQ_LPPWKST_LPUART0_POS 2 /**< LPPWKST_LPUART0 Position */ +#define MXC_F_PWRSEQ_LPPWKST_LPUART0 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKST_LPUART0_POS)) /**< LPPWKST_LPUART0 Mask */ -#define MXC_F_PWRSEQ_LPPWKFL_CPU1_POS 3 /**< LPPWKFL_CPU1 Position */ -#define MXC_F_PWRSEQ_LPPWKFL_CPU1 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKFL_CPU1_POS)) /**< LPPWKFL_CPU1 Mask */ +#define MXC_F_PWRSEQ_LPPWKST_AINCOMP0_POS 3 /**< LPPWKST_AINCOMP0 Position */ +#define MXC_F_PWRSEQ_LPPWKST_AINCOMP0 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKST_AINCOMP0_POS)) /**< LPPWKST_AINCOMP0 Mask */ -#define MXC_F_PWRSEQ_LPPWKFL_BACKUP_POS 16 /**< LPPWKFL_BACKUP Position */ -#define MXC_F_PWRSEQ_LPPWKFL_BACKUP ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKFL_BACKUP_POS)) /**< LPPWKFL_BACKUP Mask */ +#define MXC_F_PWRSEQ_LPPWKST_AINCOMP1_POS 4 /**< LPPWKST_AINCOMP1 Position */ +#define MXC_F_PWRSEQ_LPPWKST_AINCOMP1 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKST_AINCOMP1_POS)) /**< LPPWKST_AINCOMP1 Mask */ -#define MXC_F_PWRSEQ_LPPWKFL_RESET_POS 17 /**< LPPWKFL_RESET Position */ -#define MXC_F_PWRSEQ_LPPWKFL_RESET ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKFL_RESET_POS)) /**< LPPWKFL_RESET Mask */ +#define MXC_F_PWRSEQ_LPPWKST_AINCOMP0_OUT_POS 5 /**< LPPWKST_AINCOMP0_OUT Position */ +#define MXC_F_PWRSEQ_LPPWKST_AINCOMP0_OUT ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKST_AINCOMP0_OUT_POS)) /**< LPPWKST_AINCOMP0_OUT Mask */ -#define MXC_F_PWRSEQ_LPPWKFL_DRS_EVT_POS 19 /**< LPPWKFL_DRS_EVT Position */ -#define MXC_F_PWRSEQ_LPPWKFL_DRS_EVT ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKFL_DRS_EVT_POS)) /**< LPPWKFL_DRS_EVT Mask */ +#define MXC_F_PWRSEQ_LPPWKST_AINCOMP1_OUT_POS 6 /**< LPPWKST_AINCOMP1_OUT Position */ +#define MXC_F_PWRSEQ_LPPWKST_AINCOMP1_OUT ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKST_AINCOMP1_OUT_POS)) /**< LPPWKST_AINCOMP1_OUT Mask */ -/**@} end of group PWRSEQ_LPPWKFL_Register */ +#define MXC_F_PWRSEQ_LPPWKST_BACKUP_POS 16 /**< LPPWKST_BACKUP Position */ +#define MXC_F_PWRSEQ_LPPWKST_BACKUP ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKST_BACKUP_POS)) /**< LPPWKST_BACKUP Mask */ + +/**@} end of group PWRSEQ_LPPWKST_Register */ /** * @ingroup pwrseq_registers @@ -231,14 +254,20 @@ typedef struct { * @brief Low Power Peripheral Wakeup Enable Register. * @{ */ -#define MXC_F_PWRSEQ_LPPWKEN_USBLS_POS 0 /**< LPPWKEN_USBLS Position */ -#define MXC_F_PWRSEQ_LPPWKEN_USBLS ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPPWKEN_USBLS_POS)) /**< LPPWKEN_USBLS Mask */ +#define MXC_F_PWRSEQ_LPPWKEN_LPTMR0_POS 0 /**< LPPWKEN_LPTMR0 Position */ +#define MXC_F_PWRSEQ_LPPWKEN_LPTMR0 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKEN_LPTMR0_POS)) /**< LPPWKEN_LPTMR0 Mask */ + +#define MXC_F_PWRSEQ_LPPWKEN_LPTMR1_POS 1 /**< LPPWKEN_LPTMR1 Position */ +#define MXC_F_PWRSEQ_LPPWKEN_LPTMR1 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKEN_LPTMR1_POS)) /**< LPPWKEN_LPTMR1 Mask */ -#define MXC_F_PWRSEQ_LPPWKEN_USBVBUS_POS 2 /**< LPPWKEN_USBVBUS Position */ -#define MXC_F_PWRSEQ_LPPWKEN_USBVBUS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKEN_USBVBUS_POS)) /**< LPPWKEN_USBVBUS Mask */ +#define MXC_F_PWRSEQ_LPPWKEN_LPUART0_POS 2 /**< LPPWKEN_LPUART0 Position */ +#define MXC_F_PWRSEQ_LPPWKEN_LPUART0 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKEN_LPUART0_POS)) /**< LPPWKEN_LPUART0 Mask */ -#define MXC_F_PWRSEQ_LPPWKEN_CPU1_POS 3 /**< LPPWKEN_CPU1 Position */ -#define MXC_F_PWRSEQ_LPPWKEN_CPU1 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKEN_CPU1_POS)) /**< LPPWKEN_CPU1 Mask */ +#define MXC_F_PWRSEQ_LPPWKEN_AINCOMP0_POS 3 /**< LPPWKEN_AINCOMP0 Position */ +#define MXC_F_PWRSEQ_LPPWKEN_AINCOMP0 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKEN_AINCOMP0_POS)) /**< LPPWKEN_AINCOMP0 Mask */ + +#define MXC_F_PWRSEQ_LPPWKEN_AINCOMP1_POS 4 /**< LPPWKEN_AINCOMP1 Position */ +#define MXC_F_PWRSEQ_LPPWKEN_AINCOMP1 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKEN_AINCOMP1_POS)) /**< LPPWKEN_AINCOMP1 Mask */ /**@} end of group PWRSEQ_LPPWKEN_Register */ @@ -260,37 +289,10 @@ typedef struct { #define MXC_F_PWRSEQ_LPMEMSD_RAM3_POS 3 /**< LPMEMSD_RAM3 Position */ #define MXC_F_PWRSEQ_LPMEMSD_RAM3 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_RAM3_POS)) /**< LPMEMSD_RAM3 Mask */ -#define MXC_F_PWRSEQ_LPMEMSD_RAM4_POS 4 /**< LPMEMSD_RAM4 Position */ -#define MXC_F_PWRSEQ_LPMEMSD_RAM4 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_RAM4_POS)) /**< LPMEMSD_RAM4 Mask */ - -#define MXC_F_PWRSEQ_LPMEMSD_RAM5_POS 5 /**< LPMEMSD_RAM5 Position */ -#define MXC_F_PWRSEQ_LPMEMSD_RAM5 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_RAM5_POS)) /**< LPMEMSD_RAM5 Mask */ - -#define MXC_F_PWRSEQ_LPMEMSD_RAM6_POS 6 /**< LPMEMSD_RAM6 Position */ -#define MXC_F_PWRSEQ_LPMEMSD_RAM6 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_RAM6_POS)) /**< LPMEMSD_RAM6 Mask */ - -#define MXC_F_PWRSEQ_LPMEMSD_ICCXIP_POS 8 /**< LPMEMSD_ICCXIP Position */ -#define MXC_F_PWRSEQ_LPMEMSD_ICCXIP ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_ICCXIP_POS)) /**< LPMEMSD_ICCXIP Mask */ - -#define MXC_F_PWRSEQ_LPMEMSD_CRYPTO_POS 10 /**< LPMEMSD_CRYPTO Position */ -#define MXC_F_PWRSEQ_LPMEMSD_CRYPTO ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_CRYPTO_POS)) /**< LPMEMSD_CRYPTO Mask */ - -#define MXC_F_PWRSEQ_LPMEMSD_USBFIFO_POS 11 /**< LPMEMSD_USBFIFO Position */ -#define MXC_F_PWRSEQ_LPMEMSD_USBFIFO ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_USBFIFO_POS)) /**< LPMEMSD_USBFIFO Mask */ - -#define MXC_F_PWRSEQ_LPMEMSD_ROM0_POS 12 /**< LPMEMSD_ROM0 Position */ -#define MXC_F_PWRSEQ_LPMEMSD_ROM0 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_ROM0_POS)) /**< LPMEMSD_ROM0 Mask */ - -#define MXC_F_PWRSEQ_LPMEMSD_MEUMEM_POS 13 /**< LPMEMSD_MEUMEM Position */ -#define MXC_F_PWRSEQ_LPMEMSD_MEUMEM ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_MEUMEM_POS)) /**< LPMEMSD_MEUMEM Mask */ - -#define MXC_F_PWRSEQ_LPMEMSD_ROM1_POS 15 /**< LPMEMSD_ROM1 Position */ -#define MXC_F_PWRSEQ_LPMEMSD_ROM1 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_ROM1_POS)) /**< LPMEMSD_ROM1 Mask */ - /**@} end of group PWRSEQ_LPMEMSD_Register */ #ifdef __cplusplus } #endif -#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_PWRSEQ_REGS_H_ +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32672_INCLUDE_PWRSEQ_REGS_H_ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32572/Include/qdec_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32572/Include/qdec_regs.h new file mode 100644 index 00000000000..cf3a0e23021 --- /dev/null +++ b/Libraries/CMSIS/Device/Maxim/MAX32572/Include/qdec_regs.h @@ -0,0 +1,326 @@ +/** + * @file qdec_regs.h + * @brief Registers, Bit Masks and Bit Positions for the QDEC Peripheral Module. + * @note This file is @generated. + * @ingroup qdec_registers + */ + +/****************************************************************************** + * + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32672_INCLUDE_QDEC_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32672_INCLUDE_QDEC_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup qdec + * @defgroup qdec_registers QDEC_Registers + * @brief Registers, Bit Masks and Bit Positions for the QDEC Peripheral Module. + * @details Quadrature Encoder Interface + */ + +/** + * @ingroup qdec_registers + * Structure type to access the QDEC Registers. + */ +typedef struct { + __IO uint32_t ctrl; /**< \b 0x0000: QDEC CTRL Register */ + __IO uint32_t intfl; /**< \b 0x0004: QDEC INTFL Register */ + __IO uint32_t inten; /**< \b 0x0008: QDEC INTEN Register */ + __IO uint32_t maxcnt; /**< \b 0x000C: QDEC MAXCNT Register */ + __IO uint32_t initial; /**< \b 0x0010: QDEC INITIAL Register */ + __IO uint32_t compare; /**< \b 0x0014: QDEC COMPARE Register */ + __I uint32_t index; /**< \b 0x0018: QDEC INDEX Register */ + __I uint32_t capture; /**< \b 0x001C: QDEC CAPTURE Register */ + __I uint32_t status; /**< \b 0x0020: QDEC STATUS Register */ + __IO uint32_t position; /**< \b 0x0024: QDEC POSITION Register */ + __IO uint32_t capdly; /**< \b 0x0028: QDEC CAPDLY Register */ +} mxc_qdec_regs_t; + +/* Register offsets for module QDEC */ +/** + * @ingroup qdec_registers + * @defgroup QDEC_Register_Offsets Register Offsets + * @brief QDEC Peripheral Register Offsets from the QDEC Base Peripheral Address. + * @{ + */ +#define MXC_R_QDEC_CTRL ((uint32_t)0x00000000UL) /**< Offset from QDEC Base Address: 0x0000 */ +#define MXC_R_QDEC_INTFL ((uint32_t)0x00000004UL) /**< Offset from QDEC Base Address: 0x0004 */ +#define MXC_R_QDEC_INTEN ((uint32_t)0x00000008UL) /**< Offset from QDEC Base Address: 0x0008 */ +#define MXC_R_QDEC_MAXCNT ((uint32_t)0x0000000CUL) /**< Offset from QDEC Base Address: 0x000C */ +#define MXC_R_QDEC_INITIAL ((uint32_t)0x00000010UL) /**< Offset from QDEC Base Address: 0x0010 */ +#define MXC_R_QDEC_COMPARE ((uint32_t)0x00000014UL) /**< Offset from QDEC Base Address: 0x0014 */ +#define MXC_R_QDEC_INDEX ((uint32_t)0x00000018UL) /**< Offset from QDEC Base Address: 0x0018 */ +#define MXC_R_QDEC_CAPTURE ((uint32_t)0x0000001CUL) /**< Offset from QDEC Base Address: 0x001C */ +#define MXC_R_QDEC_STATUS ((uint32_t)0x00000020UL) /**< Offset from QDEC Base Address: 0x0020 */ +#define MXC_R_QDEC_POSITION ((uint32_t)0x00000024UL) /**< Offset from QDEC Base Address: 0x0024 */ +#define MXC_R_QDEC_CAPDLY ((uint32_t)0x00000028UL) /**< Offset from QDEC Base Address: 0x0028 */ +/**@} end of group qdec_registers */ + +/** + * @ingroup qdec_registers + * @defgroup QDEC_CTRL QDEC_CTRL + * @brief Control Register. + * @{ + */ +#define MXC_F_QDEC_CTRL_EN_POS 0 /**< CTRL_EN Position */ +#define MXC_F_QDEC_CTRL_EN ((uint32_t)(0x1UL << MXC_F_QDEC_CTRL_EN_POS)) /**< CTRL_EN Mask */ + +#define MXC_F_QDEC_CTRL_MODE_POS 1 /**< CTRL_MODE Position */ +#define MXC_F_QDEC_CTRL_MODE ((uint32_t)(0x3UL << MXC_F_QDEC_CTRL_MODE_POS)) /**< CTRL_MODE Mask */ +#define MXC_V_QDEC_CTRL_MODE_X1MODE ((uint32_t)0x0UL) /**< CTRL_MODE_X1MODE Value */ +#define MXC_S_QDEC_CTRL_MODE_X1MODE (MXC_V_QDEC_CTRL_MODE_X1MODE << MXC_F_QDEC_CTRL_MODE_POS) /**< CTRL_MODE_X1MODE Setting */ +#define MXC_V_QDEC_CTRL_MODE_X2MODE ((uint32_t)0x1UL) /**< CTRL_MODE_X2MODE Value */ +#define MXC_S_QDEC_CTRL_MODE_X2MODE (MXC_V_QDEC_CTRL_MODE_X2MODE << MXC_F_QDEC_CTRL_MODE_POS) /**< CTRL_MODE_X2MODE Setting */ +#define MXC_V_QDEC_CTRL_MODE_X4MODE ((uint32_t)0x2UL) /**< CTRL_MODE_X4MODE Value */ +#define MXC_S_QDEC_CTRL_MODE_X4MODE (MXC_V_QDEC_CTRL_MODE_X4MODE << MXC_F_QDEC_CTRL_MODE_POS) /**< CTRL_MODE_X4MODE Setting */ + +#define MXC_F_QDEC_CTRL_SWAP_POS 3 /**< CTRL_SWAP Position */ +#define MXC_F_QDEC_CTRL_SWAP ((uint32_t)(0x1UL << MXC_F_QDEC_CTRL_SWAP_POS)) /**< CTRL_SWAP Mask */ + +#define MXC_F_QDEC_CTRL_FILTER_POS 4 /**< CTRL_FILTER Position */ +#define MXC_F_QDEC_CTRL_FILTER ((uint32_t)(0x3UL << MXC_F_QDEC_CTRL_FILTER_POS)) /**< CTRL_FILTER Mask */ +#define MXC_V_QDEC_CTRL_FILTER_1_SAMPLE ((uint32_t)0x0UL) /**< CTRL_FILTER_1_SAMPLE Value */ +#define MXC_S_QDEC_CTRL_FILTER_1_SAMPLE (MXC_V_QDEC_CTRL_FILTER_1_SAMPLE << MXC_F_QDEC_CTRL_FILTER_POS) /**< CTRL_FILTER_1_SAMPLE Setting */ +#define MXC_V_QDEC_CTRL_FILTER_2_SAMPLES ((uint32_t)0x1UL) /**< CTRL_FILTER_2_SAMPLES Value */ +#define MXC_S_QDEC_CTRL_FILTER_2_SAMPLES (MXC_V_QDEC_CTRL_FILTER_2_SAMPLES << MXC_F_QDEC_CTRL_FILTER_POS) /**< CTRL_FILTER_2_SAMPLES Setting */ +#define MXC_V_QDEC_CTRL_FILTER_3_SAMPLES ((uint32_t)0x2UL) /**< CTRL_FILTER_3_SAMPLES Value */ +#define MXC_S_QDEC_CTRL_FILTER_3_SAMPLES (MXC_V_QDEC_CTRL_FILTER_3_SAMPLES << MXC_F_QDEC_CTRL_FILTER_POS) /**< CTRL_FILTER_3_SAMPLES Setting */ +#define MXC_V_QDEC_CTRL_FILTER_4_SAMPLES ((uint32_t)0x3UL) /**< CTRL_FILTER_4_SAMPLES Value */ +#define MXC_S_QDEC_CTRL_FILTER_4_SAMPLES (MXC_V_QDEC_CTRL_FILTER_4_SAMPLES << MXC_F_QDEC_CTRL_FILTER_POS) /**< CTRL_FILTER_4_SAMPLES Setting */ + +#define MXC_F_QDEC_CTRL_RST_INDEX_POS 6 /**< CTRL_RST_INDEX Position */ +#define MXC_F_QDEC_CTRL_RST_INDEX ((uint32_t)(0x1UL << MXC_F_QDEC_CTRL_RST_INDEX_POS)) /**< CTRL_RST_INDEX Mask */ + +#define MXC_F_QDEC_CTRL_RST_MAXCNT_POS 7 /**< CTRL_RST_MAXCNT Position */ +#define MXC_F_QDEC_CTRL_RST_MAXCNT ((uint32_t)(0x1UL << MXC_F_QDEC_CTRL_RST_MAXCNT_POS)) /**< CTRL_RST_MAXCNT Mask */ + +#define MXC_F_QDEC_CTRL_STICKY_POS 8 /**< CTRL_STICKY Position */ +#define MXC_F_QDEC_CTRL_STICKY ((uint32_t)(0x1UL << MXC_F_QDEC_CTRL_STICKY_POS)) /**< CTRL_STICKY Mask */ + +#define MXC_F_QDEC_CTRL_PSC_POS 16 /**< CTRL_PSC Position */ +#define MXC_F_QDEC_CTRL_PSC ((uint32_t)(0x7UL << MXC_F_QDEC_CTRL_PSC_POS)) /**< CTRL_PSC Mask */ +#define MXC_V_QDEC_CTRL_PSC_DIV1 ((uint32_t)0x0UL) /**< CTRL_PSC_DIV1 Value */ +#define MXC_S_QDEC_CTRL_PSC_DIV1 (MXC_V_QDEC_CTRL_PSC_DIV1 << MXC_F_QDEC_CTRL_PSC_POS) /**< CTRL_PSC_DIV1 Setting */ +#define MXC_V_QDEC_CTRL_PSC_DIV2 ((uint32_t)0x1UL) /**< CTRL_PSC_DIV2 Value */ +#define MXC_S_QDEC_CTRL_PSC_DIV2 (MXC_V_QDEC_CTRL_PSC_DIV2 << MXC_F_QDEC_CTRL_PSC_POS) /**< CTRL_PSC_DIV2 Setting */ +#define MXC_V_QDEC_CTRL_PSC_DIV4 ((uint32_t)0x2UL) /**< CTRL_PSC_DIV4 Value */ +#define MXC_S_QDEC_CTRL_PSC_DIV4 (MXC_V_QDEC_CTRL_PSC_DIV4 << MXC_F_QDEC_CTRL_PSC_POS) /**< CTRL_PSC_DIV4 Setting */ +#define MXC_V_QDEC_CTRL_PSC_DIV8 ((uint32_t)0x3UL) /**< CTRL_PSC_DIV8 Value */ +#define MXC_S_QDEC_CTRL_PSC_DIV8 (MXC_V_QDEC_CTRL_PSC_DIV8 << MXC_F_QDEC_CTRL_PSC_POS) /**< CTRL_PSC_DIV8 Setting */ +#define MXC_V_QDEC_CTRL_PSC_DIV16 ((uint32_t)0x4UL) /**< CTRL_PSC_DIV16 Value */ +#define MXC_S_QDEC_CTRL_PSC_DIV16 (MXC_V_QDEC_CTRL_PSC_DIV16 << MXC_F_QDEC_CTRL_PSC_POS) /**< CTRL_PSC_DIV16 Setting */ +#define MXC_V_QDEC_CTRL_PSC_DIV32 ((uint32_t)0x5UL) /**< CTRL_PSC_DIV32 Value */ +#define MXC_S_QDEC_CTRL_PSC_DIV32 (MXC_V_QDEC_CTRL_PSC_DIV32 << MXC_F_QDEC_CTRL_PSC_POS) /**< CTRL_PSC_DIV32 Setting */ +#define MXC_V_QDEC_CTRL_PSC_DIV64 ((uint32_t)0x6UL) /**< CTRL_PSC_DIV64 Value */ +#define MXC_S_QDEC_CTRL_PSC_DIV64 (MXC_V_QDEC_CTRL_PSC_DIV64 << MXC_F_QDEC_CTRL_PSC_POS) /**< CTRL_PSC_DIV64 Setting */ +#define MXC_V_QDEC_CTRL_PSC_DIV128 ((uint32_t)0x7UL) /**< CTRL_PSC_DIV128 Value */ +#define MXC_S_QDEC_CTRL_PSC_DIV128 (MXC_V_QDEC_CTRL_PSC_DIV128 << MXC_F_QDEC_CTRL_PSC_POS) /**< CTRL_PSC_DIV128 Setting */ + +/**@} end of group QDEC_CTRL_Register */ + +/** + * @ingroup qdec_registers + * @defgroup QDEC_INTFL QDEC_INTFL + * @brief Interrupt Flag Register. + * @{ + */ +#define MXC_F_QDEC_INTFL_INDEX_POS 0 /**< INTFL_INDEX Position */ +#define MXC_F_QDEC_INTFL_INDEX ((uint32_t)(0x1UL << MXC_F_QDEC_INTFL_INDEX_POS)) /**< INTFL_INDEX Mask */ + +#define MXC_F_QDEC_INTFL_QERR_POS 1 /**< INTFL_QERR Position */ +#define MXC_F_QDEC_INTFL_QERR ((uint32_t)(0x1UL << MXC_F_QDEC_INTFL_QERR_POS)) /**< INTFL_QERR Mask */ + +#define MXC_F_QDEC_INTFL_COMPARE_POS 2 /**< INTFL_COMPARE Position */ +#define MXC_F_QDEC_INTFL_COMPARE ((uint32_t)(0x1UL << MXC_F_QDEC_INTFL_COMPARE_POS)) /**< INTFL_COMPARE Mask */ + +#define MXC_F_QDEC_INTFL_MAXCNT_POS 3 /**< INTFL_MAXCNT Position */ +#define MXC_F_QDEC_INTFL_MAXCNT ((uint32_t)(0x1UL << MXC_F_QDEC_INTFL_MAXCNT_POS)) /**< INTFL_MAXCNT Mask */ + +#define MXC_F_QDEC_INTFL_CAPTURE_POS 4 /**< INTFL_CAPTURE Position */ +#define MXC_F_QDEC_INTFL_CAPTURE ((uint32_t)(0x1UL << MXC_F_QDEC_INTFL_CAPTURE_POS)) /**< INTFL_CAPTURE Mask */ + +#define MXC_F_QDEC_INTFL_DIR_POS 5 /**< INTFL_DIR Position */ +#define MXC_F_QDEC_INTFL_DIR ((uint32_t)(0x1UL << MXC_F_QDEC_INTFL_DIR_POS)) /**< INTFL_DIR Mask */ + +#define MXC_F_QDEC_INTFL_MOVE_POS 6 /**< INTFL_MOVE Position */ +#define MXC_F_QDEC_INTFL_MOVE ((uint32_t)(0x1UL << MXC_F_QDEC_INTFL_MOVE_POS)) /**< INTFL_MOVE Mask */ + +/**@} end of group QDEC_INTFL_Register */ + +/** + * @ingroup qdec_registers + * @defgroup QDEC_INTEN QDEC_INTEN + * @brief Interrupt Enable Register. + * @{ + */ +#define MXC_F_QDEC_INTEN_INDEX_POS 0 /**< INTEN_INDEX Position */ +#define MXC_F_QDEC_INTEN_INDEX ((uint32_t)(0x1UL << MXC_F_QDEC_INTEN_INDEX_POS)) /**< INTEN_INDEX Mask */ + +#define MXC_F_QDEC_INTEN_QERR_POS 1 /**< INTEN_QERR Position */ +#define MXC_F_QDEC_INTEN_QERR ((uint32_t)(0x1UL << MXC_F_QDEC_INTEN_QERR_POS)) /**< INTEN_QERR Mask */ + +#define MXC_F_QDEC_INTEN_COMPARE_POS 2 /**< INTEN_COMPARE Position */ +#define MXC_F_QDEC_INTEN_COMPARE ((uint32_t)(0x1UL << MXC_F_QDEC_INTEN_COMPARE_POS)) /**< INTEN_COMPARE Mask */ + +#define MXC_F_QDEC_INTEN_MAXCNT_POS 3 /**< INTEN_MAXCNT Position */ +#define MXC_F_QDEC_INTEN_MAXCNT ((uint32_t)(0x1UL << MXC_F_QDEC_INTEN_MAXCNT_POS)) /**< INTEN_MAXCNT Mask */ + +#define MXC_F_QDEC_INTEN_CAPTURE_POS 4 /**< INTEN_CAPTURE Position */ +#define MXC_F_QDEC_INTEN_CAPTURE ((uint32_t)(0x1UL << MXC_F_QDEC_INTEN_CAPTURE_POS)) /**< INTEN_CAPTURE Mask */ + +#define MXC_F_QDEC_INTEN_DIR_POS 5 /**< INTEN_DIR Position */ +#define MXC_F_QDEC_INTEN_DIR ((uint32_t)(0x1UL << MXC_F_QDEC_INTEN_DIR_POS)) /**< INTEN_DIR Mask */ + +#define MXC_F_QDEC_INTEN_MOVE_POS 6 /**< INTEN_MOVE Position */ +#define MXC_F_QDEC_INTEN_MOVE ((uint32_t)(0x1UL << MXC_F_QDEC_INTEN_MOVE_POS)) /**< INTEN_MOVE Mask */ + +/**@} end of group QDEC_INTEN_Register */ + +/** + * @ingroup qdec_registers + * @defgroup QDEC_MAXCNT QDEC_MAXCNT + * @brief Maximum Count Register. + * @{ + */ +#define MXC_F_QDEC_MAXCNT_MAXCNT_POS 0 /**< MAXCNT_MAXCNT Position */ +#define MXC_F_QDEC_MAXCNT_MAXCNT ((uint32_t)(0xFFFFFFFFUL << MXC_F_QDEC_MAXCNT_MAXCNT_POS)) /**< MAXCNT_MAXCNT Mask */ + +/**@} end of group QDEC_MAXCNT_Register */ + +/** + * @ingroup qdec_registers + * @defgroup QDEC_INITIAL QDEC_INITIAL + * @brief Initial Count Register. + * @{ + */ +#define MXC_F_QDEC_INITIAL_INITIAL_POS 0 /**< INITIAL_INITIAL Position */ +#define MXC_F_QDEC_INITIAL_INITIAL ((uint32_t)(0xFFFFFFFFUL << MXC_F_QDEC_INITIAL_INITIAL_POS)) /**< INITIAL_INITIAL Mask */ + +/**@} end of group QDEC_INITIAL_Register */ + +/** + * @ingroup qdec_registers + * @defgroup QDEC_COMPARE QDEC_COMPARE + * @brief Compare Register. + * @{ + */ +#define MXC_F_QDEC_COMPARE_COMPARE_POS 0 /**< COMPARE_COMPARE Position */ +#define MXC_F_QDEC_COMPARE_COMPARE ((uint32_t)(0xFFFFFFFFUL << MXC_F_QDEC_COMPARE_COMPARE_POS)) /**< COMPARE_COMPARE Mask */ + +/**@} end of group QDEC_COMPARE_Register */ + +/** + * @ingroup qdec_registers + * @defgroup QDEC_INDEX QDEC_INDEX + * @brief Index Register. count captured when QEI fired + * @{ + */ +#define MXC_F_QDEC_INDEX_INDEX_POS 0 /**< INDEX_INDEX Position */ +#define MXC_F_QDEC_INDEX_INDEX ((uint32_t)(0xFFFFFFFFUL << MXC_F_QDEC_INDEX_INDEX_POS)) /**< INDEX_INDEX Mask */ + +/**@} end of group QDEC_INDEX_Register */ + +/** + * @ingroup qdec_registers + * @defgroup QDEC_CAPTURE QDEC_CAPTURE + * @brief Capture Register. counter captured when QES fired + * @{ + */ +#define MXC_F_QDEC_CAPTURE_CAPTURE_POS 0 /**< CAPTURE_CAPTURE Position */ +#define MXC_F_QDEC_CAPTURE_CAPTURE ((uint32_t)(0xFFFFFFFFUL << MXC_F_QDEC_CAPTURE_CAPTURE_POS)) /**< CAPTURE_CAPTURE Mask */ + +/**@} end of group QDEC_CAPTURE_Register */ + +/** + * @ingroup qdec_registers + * @defgroup QDEC_STATUS QDEC_STATUS + * @brief Status Register. + * @{ + */ +#define MXC_F_QDEC_STATUS_DIR_POS 0 /**< STATUS_DIR Position */ +#define MXC_F_QDEC_STATUS_DIR ((uint32_t)(0x1UL << MXC_F_QDEC_STATUS_DIR_POS)) /**< STATUS_DIR Mask */ + +/**@} end of group QDEC_STATUS_Register */ + +/** + * @ingroup qdec_registers + * @defgroup QDEC_POSITION QDEC_POSITION + * @brief Count Register. raw counter value + * @{ + */ +#define MXC_F_QDEC_POSITION_POSITION_POS 0 /**< POSITION_POSITION Position */ +#define MXC_F_QDEC_POSITION_POSITION ((uint32_t)(0xFFFFFFFFUL << MXC_F_QDEC_POSITION_POSITION_POS)) /**< POSITION_POSITION Mask */ + +/**@} end of group QDEC_POSITION_Register */ + +/** + * @ingroup qdec_registers + * @defgroup QDEC_CAPDLY QDEC_CAPDLY + * @brief delay CAPTURE + * @{ + */ +#define MXC_F_QDEC_CAPDLY_CAPDLY_POS 0 /**< CAPDLY_CAPDLY Position */ +#define MXC_F_QDEC_CAPDLY_CAPDLY ((uint32_t)(0xFFFFFFFFUL << MXC_F_QDEC_CAPDLY_CAPDLY_POS)) /**< CAPDLY_CAPDLY Mask */ + +/**@} end of group QDEC_CAPDLY_Register */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32672_INCLUDE_QDEC_REGS_H_ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32572/Include/rtc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32572/Include/rtc_regs.h index 7293fa2df2b..74a6aa80245 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32572/Include/rtc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32572/Include/rtc_regs.h @@ -25,8 +25,8 @@ * ******************************************************************************/ -#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_RTC_REGS_H_ -#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_RTC_REGS_H_ +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32672_INCLUDE_RTC_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32672_INCLUDE_RTC_REGS_H_ /* **** Includes **** */ #include @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile @@ -169,11 +173,11 @@ typedef struct { #define MXC_F_RTC_CTRL_RDY_IE_POS 5 /**< CTRL_RDY_IE Position */ #define MXC_F_RTC_CTRL_RDY_IE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_RDY_IE_POS)) /**< CTRL_RDY_IE Mask */ -#define MXC_F_RTC_CTRL_TOD_ALARM_IF_POS 6 /**< CTRL_TOD_ALARM_IF Position */ -#define MXC_F_RTC_CTRL_TOD_ALARM_IF ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_TOD_ALARM_IF_POS)) /**< CTRL_TOD_ALARM_IF Mask */ +#define MXC_F_RTC_CTRL_TOD_ALARM_POS 6 /**< CTRL_TOD_ALARM Position */ +#define MXC_F_RTC_CTRL_TOD_ALARM ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_TOD_ALARM_POS)) /**< CTRL_TOD_ALARM Mask */ -#define MXC_F_RTC_CTRL_SSEC_ALARM_IF_POS 7 /**< CTRL_SSEC_ALARM_IF Position */ -#define MXC_F_RTC_CTRL_SSEC_ALARM_IF ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_SSEC_ALARM_IF_POS)) /**< CTRL_SSEC_ALARM_IF Mask */ +#define MXC_F_RTC_CTRL_SSEC_ALARM_POS 7 /**< CTRL_SSEC_ALARM Position */ +#define MXC_F_RTC_CTRL_SSEC_ALARM ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_SSEC_ALARM_POS)) /**< CTRL_SSEC_ALARM Mask */ #define MXC_F_RTC_CTRL_SQW_EN_POS 8 /**< CTRL_SQW_EN Position */ #define MXC_F_RTC_CTRL_SQW_EN ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_SQW_EN_POS)) /**< CTRL_SQW_EN Mask */ @@ -206,8 +210,8 @@ typedef struct { #define MXC_F_RTC_TRIM_TRIM_POS 0 /**< TRIM_TRIM Position */ #define MXC_F_RTC_TRIM_TRIM ((uint32_t)(0xFFUL << MXC_F_RTC_TRIM_TRIM_POS)) /**< TRIM_TRIM Mask */ -#define MXC_F_RTC_TRIM_VBAT_TMR_POS 8 /**< TRIM_VBAT_TMR Position */ -#define MXC_F_RTC_TRIM_VBAT_TMR ((uint32_t)(0xFFFFFFUL << MXC_F_RTC_TRIM_VBAT_TMR_POS)) /**< TRIM_VBAT_TMR Mask */ +#define MXC_F_RTC_TRIM_VRTC_TMR_POS 8 /**< TRIM_VRTC_TMR Position */ +#define MXC_F_RTC_TRIM_VRTC_TMR ((uint32_t)(0xFFFFFFUL << MXC_F_RTC_TRIM_VRTC_TMR_POS)) /**< TRIM_VRTC_TMR Mask */ /**@} end of group RTC_TRIM_Register */ @@ -241,4 +245,4 @@ typedef struct { } #endif -#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_RTC_REGS_H_ +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32672_INCLUDE_RTC_REGS_H_ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32572/Include/scn_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32572/Include/scn_regs.h index 9b3e29a86dc..cb8aa9a692f 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32572/Include/scn_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32572/Include/scn_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32572/Include/sema_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32572/Include/sema_regs.h index da08de5acc6..1919923be7f 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32572/Include/sema_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32572/Include/sema_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32572/Include/sfcc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32572/Include/sfcc_regs.h index 2a19e25fc43..55ceb492803 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32572/Include/sfcc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32572/Include/sfcc_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32572/Include/sir_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32572/Include/sir_regs.h index b09a85e2b95..8b1b3d57419 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32572/Include/sir_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32572/Include/sir_regs.h @@ -25,8 +25,8 @@ * ******************************************************************************/ -#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_SIR_REGS_H_ -#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_SIR_REGS_H_ +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32672_INCLUDE_SIR_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32672_INCLUDE_SIR_REGS_H_ /* **** Includes **** */ #include @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile @@ -74,8 +78,8 @@ extern "C" { * Structure type to access the SIR Registers. */ typedef struct { - __I uint32_t sistat; /**< \b 0x00: SIR SISTAT Register */ - __I uint32_t siaddr; /**< \b 0x04: SIR SIADDR Register */ + __I uint32_t status; /**< \b 0x00: SIR STATUS Register */ + __I uint32_t addr; /**< \b 0x04: SIR ADDR Register */ __R uint32_t rsv_0x8_0xff[62]; __I uint32_t fstat; /**< \b 0x100: SIR FSTAT Register */ __I uint32_t sfstat; /**< \b 0x104: SIR SFSTAT Register */ @@ -88,91 +92,67 @@ typedef struct { * @brief SIR Peripheral Register Offsets from the SIR Base Peripheral Address. * @{ */ -#define MXC_R_SIR_SISTAT ((uint32_t)0x00000000UL) /**< Offset from SIR Base Address: 0x0000 */ -#define MXC_R_SIR_SIADDR ((uint32_t)0x00000004UL) /**< Offset from SIR Base Address: 0x0004 */ +#define MXC_R_SIR_STATUS ((uint32_t)0x00000000UL) /**< Offset from SIR Base Address: 0x0000 */ +#define MXC_R_SIR_ADDR ((uint32_t)0x00000004UL) /**< Offset from SIR Base Address: 0x0004 */ #define MXC_R_SIR_FSTAT ((uint32_t)0x00000100UL) /**< Offset from SIR Base Address: 0x0100 */ #define MXC_R_SIR_SFSTAT ((uint32_t)0x00000104UL) /**< Offset from SIR Base Address: 0x0104 */ /**@} end of group sir_registers */ /** * @ingroup sir_registers - * @defgroup SIR_SISTAT SIR_SISTAT + * @defgroup SIR_STATUS SIR_STATUS * @brief System Initialization Status Register. * @{ */ -#define MXC_F_SIR_SISTAT_MAGIC_POS 0 /**< SISTAT_MAGIC Position */ -#define MXC_F_SIR_SISTAT_MAGIC ((uint32_t)(0x1UL << MXC_F_SIR_SISTAT_MAGIC_POS)) /**< SISTAT_MAGIC Mask */ +#define MXC_F_SIR_STATUS_CFG_VALID_POS 0 /**< STATUS_CFG_VALID Position */ +#define MXC_F_SIR_STATUS_CFG_VALID ((uint32_t)(0x1UL << MXC_F_SIR_STATUS_CFG_VALID_POS)) /**< STATUS_CFG_VALID Mask */ + +#define MXC_F_SIR_STATUS_CFG_ERR_POS 1 /**< STATUS_CFG_ERR Position */ +#define MXC_F_SIR_STATUS_CFG_ERR ((uint32_t)(0x1UL << MXC_F_SIR_STATUS_CFG_ERR_POS)) /**< STATUS_CFG_ERR Mask */ -#define MXC_F_SIR_SISTAT_CRCERR_POS 1 /**< SISTAT_CRCERR Position */ -#define MXC_F_SIR_SISTAT_CRCERR ((uint32_t)(0x1UL << MXC_F_SIR_SISTAT_CRCERR_POS)) /**< SISTAT_CRCERR Mask */ +#define MXC_F_SIR_STATUS_USER_CFG_ERR_POS 2 /**< STATUS_USER_CFG_ERR Position */ +#define MXC_F_SIR_STATUS_USER_CFG_ERR ((uint32_t)(0x1UL << MXC_F_SIR_STATUS_USER_CFG_ERR_POS)) /**< STATUS_USER_CFG_ERR Mask */ -/**@} end of group SIR_SISTAT_Register */ +/**@} end of group SIR_STATUS_Register */ /** * @ingroup sir_registers - * @defgroup SIR_SIADDR SIR_SIADDR + * @defgroup SIR_ADDR SIR_ADDR * @brief Read-only field set by the SIB block if a CRC error occurs during the read of * the OTP memory. Contains the failing address in OTP memory (when CRCERR equals * 1). * @{ */ -#define MXC_F_SIR_SIADDR_ERRADDR_POS 0 /**< SIADDR_ERRADDR Position */ -#define MXC_F_SIR_SIADDR_ERRADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_SIR_SIADDR_ERRADDR_POS)) /**< SIADDR_ERRADDR Mask */ +#define MXC_F_SIR_ADDR_ADDR_POS 0 /**< ADDR_ADDR Position */ +#define MXC_F_SIR_ADDR_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_SIR_ADDR_ADDR_POS)) /**< ADDR_ADDR Mask */ -/**@} end of group SIR_SIADDR_Register */ +/**@} end of group SIR_ADDR_Register */ /** * @ingroup sir_registers * @defgroup SIR_FSTAT SIR_FSTAT - * @brief funcstat register. + * @brief Function Status Register. * @{ */ #define MXC_F_SIR_FSTAT_FPU_POS 0 /**< FSTAT_FPU Position */ #define MXC_F_SIR_FSTAT_FPU ((uint32_t)(0x1UL << MXC_F_SIR_FSTAT_FPU_POS)) /**< FSTAT_FPU Mask */ -#define MXC_F_SIR_FSTAT_USB_POS 1 /**< FSTAT_USB Position */ -#define MXC_F_SIR_FSTAT_USB ((uint32_t)(0x1UL << MXC_F_SIR_FSTAT_USB_POS)) /**< FSTAT_USB Mask */ - -#define MXC_F_SIR_FSTAT_ADC_POS 2 /**< FSTAT_ADC Position */ -#define MXC_F_SIR_FSTAT_ADC ((uint32_t)(0x1UL << MXC_F_SIR_FSTAT_ADC_POS)) /**< FSTAT_ADC Mask */ - -#define MXC_F_SIR_FSTAT_SPIXIP_POS 3 /**< FSTAT_SPIXIP Position */ -#define MXC_F_SIR_FSTAT_SPIXIP ((uint32_t)(0x1UL << MXC_F_SIR_FSTAT_SPIXIP_POS)) /**< FSTAT_SPIXIP Mask */ - -#define MXC_F_SIR_FSTAT_ADC9_POS 9 /**< FSTAT_ADC9 Position */ -#define MXC_F_SIR_FSTAT_ADC9 ((uint32_t)(0x1UL << MXC_F_SIR_FSTAT_ADC9_POS)) /**< FSTAT_ADC9 Mask */ +#define MXC_F_SIR_FSTAT_TRNG_POS 14 /**< FSTAT_TRNG Position */ +#define MXC_F_SIR_FSTAT_TRNG ((uint32_t)(0x1UL << MXC_F_SIR_FSTAT_TRNG_POS)) /**< FSTAT_TRNG Mask */ -#define MXC_F_SIR_FSTAT_SC_POS 10 /**< FSTAT_SC Position */ -#define MXC_F_SIR_FSTAT_SC ((uint32_t)(0x1UL << MXC_F_SIR_FSTAT_SC_POS)) /**< FSTAT_SC Mask */ - -#define MXC_F_SIR_FSTAT_NMI_POS 12 /**< FSTAT_NMI Position */ -#define MXC_F_SIR_FSTAT_NMI ((uint32_t)(0x1UL << MXC_F_SIR_FSTAT_NMI_POS)) /**< FSTAT_NMI Mask */ +#define MXC_F_SIR_FSTAT_DS_ACK_POS 15 /**< FSTAT_DS_ACK Position */ +#define MXC_F_SIR_FSTAT_DS_ACK ((uint32_t)(0x1UL << MXC_F_SIR_FSTAT_DS_ACK_POS)) /**< FSTAT_DS_ACK Mask */ /**@} end of group SIR_FSTAT_Register */ /** * @ingroup sir_registers * @defgroup SIR_SFSTAT SIR_SFSTAT - * @brief Security Function + * @brief Security Function Status Register. * @{ */ -#define MXC_F_SIR_SFSTAT_SECBOOT_POS 0 /**< SFSTAT_SECBOOT Position */ -#define MXC_F_SIR_SFSTAT_SECBOOT ((uint32_t)(0x1UL << MXC_F_SIR_SFSTAT_SECBOOT_POS)) /**< SFSTAT_SECBOOT Mask */ - -#define MXC_F_SIR_SFSTAT_SERLOAD_POS 1 /**< SFSTAT_SERLOAD Position */ -#define MXC_F_SIR_SFSTAT_SERLOAD ((uint32_t)(0x1UL << MXC_F_SIR_SFSTAT_SERLOAD_POS)) /**< SFSTAT_SERLOAD Mask */ - -#define MXC_F_SIR_SFSTAT_TRNG_POS 2 /**< SFSTAT_TRNG Position */ -#define MXC_F_SIR_SFSTAT_TRNG ((uint32_t)(0x1UL << MXC_F_SIR_SFSTAT_TRNG_POS)) /**< SFSTAT_TRNG Mask */ - -#define MXC_F_SIR_SFSTAT_AES_POS 3 /**< SFSTAT_AES Position */ -#define MXC_F_SIR_SFSTAT_AES ((uint32_t)(0x1UL << MXC_F_SIR_SFSTAT_AES_POS)) /**< SFSTAT_AES Mask */ - -#define MXC_F_SIR_SFSTAT_SHA_POS 4 /**< SFSTAT_SHA Position */ -#define MXC_F_SIR_SFSTAT_SHA ((uint32_t)(0x1UL << MXC_F_SIR_SFSTAT_SHA_POS)) /**< SFSTAT_SHA Mask */ - -#define MXC_F_SIR_SFSTAT_SECMODE_POS 7 /**< SFSTAT_SECMODE Position */ -#define MXC_F_SIR_SFSTAT_SECMODE ((uint32_t)(0x1UL << MXC_F_SIR_SFSTAT_SECMODE_POS)) /**< SFSTAT_SECMODE Mask */ +#define MXC_F_SIR_SFSTAT_SECFUNC0_POS 0 /**< SFSTAT_SECFUNC0 Position */ +#define MXC_F_SIR_SFSTAT_SECFUNC0 ((uint32_t)(0x1UL << MXC_F_SIR_SFSTAT_SECFUNC0_POS)) /**< SFSTAT_SECFUNC0 Mask */ /**@} end of group SIR_SFSTAT_Register */ @@ -180,4 +160,4 @@ typedef struct { } #endif -#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_SIR_REGS_H_ +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32672_INCLUDE_SIR_REGS_H_ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32572/Include/skbd_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32572/Include/skbd_regs.h index bf13ea7d4d4..5bb65075410 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32572/Include/skbd_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32572/Include/skbd_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32572/Include/smon_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32572/Include/smon_regs.h index 4594f20904c..043977c1eee 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32572/Include/smon_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32572/Include/smon_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32572/Include/spi_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32572/Include/spi_regs.h index d582b47845a..2b11e5223ca 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32572/Include/spi_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32572/Include/spi_regs.h @@ -25,8 +25,8 @@ * ******************************************************************************/ -#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_SPI_REGS_H_ -#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_SPI_REGS_H_ +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32672_INCLUDE_SPI_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32672_INCLUDE_SPI_REGS_H_ /* **** Includes **** */ #include @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile @@ -90,7 +94,7 @@ typedef struct { __IO uint32_t inten; /**< \b 0x24: SPI INTEN Register */ __IO uint32_t wkfl; /**< \b 0x28: SPI WKFL Register */ __IO uint32_t wken; /**< \b 0x2C: SPI WKEN Register */ - __I uint32_t status; /**< \b 0x30: SPI STATUS Register */ + __I uint32_t stat; /**< \b 0x30: SPI STAT Register */ } mxc_spi_regs_t; /* Register offsets for module SPI */ @@ -113,7 +117,7 @@ typedef struct { #define MXC_R_SPI_INTEN ((uint32_t)0x00000024UL) /**< Offset from SPI Base Address: 0x0024 */ #define MXC_R_SPI_WKFL ((uint32_t)0x00000028UL) /**< Offset from SPI Base Address: 0x0028 */ #define MXC_R_SPI_WKEN ((uint32_t)0x0000002CUL) /**< Offset from SPI Base Address: 0x002C */ -#define MXC_R_SPI_STATUS ((uint32_t)0x00000030UL) /**< Offset from SPI Base Address: 0x0030 */ +#define MXC_R_SPI_STAT ((uint32_t)0x00000030UL) /**< Offset from SPI Base Address: 0x0030 */ /**@} end of group spi_registers */ /** @@ -214,38 +218,8 @@ typedef struct { #define MXC_F_SPI_CTRL2_NUMBITS_POS 8 /**< CTRL2_NUMBITS Position */ #define MXC_F_SPI_CTRL2_NUMBITS ((uint32_t)(0xFUL << MXC_F_SPI_CTRL2_NUMBITS_POS)) /**< CTRL2_NUMBITS Mask */ -#define MXC_V_SPI_CTRL2_NUMBITS_16 ((uint32_t)0x0UL) /**< CTRL2_NUMBITS_16 Value */ -#define MXC_S_SPI_CTRL2_NUMBITS_16 (MXC_V_SPI_CTRL2_NUMBITS_16 << MXC_F_SPI_CTRL2_NUMBITS_POS) /**< CTRL2_NUMBITS_16 Setting */ -#define MXC_V_SPI_CTRL2_NUMBITS_1 ((uint32_t)0x1UL) /**< CTRL2_NUMBITS_1 Value */ -#define MXC_S_SPI_CTRL2_NUMBITS_1 (MXC_V_SPI_CTRL2_NUMBITS_1 << MXC_F_SPI_CTRL2_NUMBITS_POS) /**< CTRL2_NUMBITS_1 Setting */ -#define MXC_V_SPI_CTRL2_NUMBITS_2 ((uint32_t)0x2UL) /**< CTRL2_NUMBITS_2 Value */ -#define MXC_S_SPI_CTRL2_NUMBITS_2 (MXC_V_SPI_CTRL2_NUMBITS_2 << MXC_F_SPI_CTRL2_NUMBITS_POS) /**< CTRL2_NUMBITS_2 Setting */ -#define MXC_V_SPI_CTRL2_NUMBITS_3 ((uint32_t)0x3UL) /**< CTRL2_NUMBITS_3 Value */ -#define MXC_S_SPI_CTRL2_NUMBITS_3 (MXC_V_SPI_CTRL2_NUMBITS_3 << MXC_F_SPI_CTRL2_NUMBITS_POS) /**< CTRL2_NUMBITS_3 Setting */ -#define MXC_V_SPI_CTRL2_NUMBITS_4 ((uint32_t)0x4UL) /**< CTRL2_NUMBITS_4 Value */ -#define MXC_S_SPI_CTRL2_NUMBITS_4 (MXC_V_SPI_CTRL2_NUMBITS_4 << MXC_F_SPI_CTRL2_NUMBITS_POS) /**< CTRL2_NUMBITS_4 Setting */ -#define MXC_V_SPI_CTRL2_NUMBITS_5 ((uint32_t)0x5UL) /**< CTRL2_NUMBITS_5 Value */ -#define MXC_S_SPI_CTRL2_NUMBITS_5 (MXC_V_SPI_CTRL2_NUMBITS_5 << MXC_F_SPI_CTRL2_NUMBITS_POS) /**< CTRL2_NUMBITS_5 Setting */ -#define MXC_V_SPI_CTRL2_NUMBITS_6 ((uint32_t)0x6UL) /**< CTRL2_NUMBITS_6 Value */ -#define MXC_S_SPI_CTRL2_NUMBITS_6 (MXC_V_SPI_CTRL2_NUMBITS_6 << MXC_F_SPI_CTRL2_NUMBITS_POS) /**< CTRL2_NUMBITS_6 Setting */ -#define MXC_V_SPI_CTRL2_NUMBITS_7 ((uint32_t)0x7UL) /**< CTRL2_NUMBITS_7 Value */ -#define MXC_S_SPI_CTRL2_NUMBITS_7 (MXC_V_SPI_CTRL2_NUMBITS_7 << MXC_F_SPI_CTRL2_NUMBITS_POS) /**< CTRL2_NUMBITS_7 Setting */ -#define MXC_V_SPI_CTRL2_NUMBITS_8 ((uint32_t)0x8UL) /**< CTRL2_NUMBITS_8 Value */ -#define MXC_S_SPI_CTRL2_NUMBITS_8 (MXC_V_SPI_CTRL2_NUMBITS_8 << MXC_F_SPI_CTRL2_NUMBITS_POS) /**< CTRL2_NUMBITS_8 Setting */ -#define MXC_V_SPI_CTRL2_NUMBITS_9 ((uint32_t)0x9UL) /**< CTRL2_NUMBITS_9 Value */ -#define MXC_S_SPI_CTRL2_NUMBITS_9 (MXC_V_SPI_CTRL2_NUMBITS_9 << MXC_F_SPI_CTRL2_NUMBITS_POS) /**< CTRL2_NUMBITS_9 Setting */ -#define MXC_V_SPI_CTRL2_NUMBITS_10 ((uint32_t)0xAUL) /**< CTRL2_NUMBITS_10 Value */ -#define MXC_S_SPI_CTRL2_NUMBITS_10 (MXC_V_SPI_CTRL2_NUMBITS_10 << MXC_F_SPI_CTRL2_NUMBITS_POS) /**< CTRL2_NUMBITS_10 Setting */ -#define MXC_V_SPI_CTRL2_NUMBITS_11 ((uint32_t)0xBUL) /**< CTRL2_NUMBITS_11 Value */ -#define MXC_S_SPI_CTRL2_NUMBITS_11 (MXC_V_SPI_CTRL2_NUMBITS_11 << MXC_F_SPI_CTRL2_NUMBITS_POS) /**< CTRL2_NUMBITS_11 Setting */ -#define MXC_V_SPI_CTRL2_NUMBITS_12 ((uint32_t)0xCUL) /**< CTRL2_NUMBITS_12 Value */ -#define MXC_S_SPI_CTRL2_NUMBITS_12 (MXC_V_SPI_CTRL2_NUMBITS_12 << MXC_F_SPI_CTRL2_NUMBITS_POS) /**< CTRL2_NUMBITS_12 Setting */ -#define MXC_V_SPI_CTRL2_NUMBITS_13 ((uint32_t)0xDUL) /**< CTRL2_NUMBITS_13 Value */ -#define MXC_S_SPI_CTRL2_NUMBITS_13 (MXC_V_SPI_CTRL2_NUMBITS_13 << MXC_F_SPI_CTRL2_NUMBITS_POS) /**< CTRL2_NUMBITS_13 Setting */ -#define MXC_V_SPI_CTRL2_NUMBITS_14 ((uint32_t)0xEUL) /**< CTRL2_NUMBITS_14 Value */ -#define MXC_S_SPI_CTRL2_NUMBITS_14 (MXC_V_SPI_CTRL2_NUMBITS_14 << MXC_F_SPI_CTRL2_NUMBITS_POS) /**< CTRL2_NUMBITS_14 Setting */ -#define MXC_V_SPI_CTRL2_NUMBITS_15 ((uint32_t)0xFUL) /**< CTRL2_NUMBITS_15 Value */ -#define MXC_S_SPI_CTRL2_NUMBITS_15 (MXC_V_SPI_CTRL2_NUMBITS_15 << MXC_F_SPI_CTRL2_NUMBITS_POS) /**< CTRL2_NUMBITS_15 Setting */ +#define MXC_V_SPI_CTRL2_NUMBITS_0 ((uint32_t)0x0UL) /**< CTRL2_NUMBITS_0 Value */ +#define MXC_S_SPI_CTRL2_NUMBITS_0 (MXC_V_SPI_CTRL2_NUMBITS_0 << MXC_F_SPI_CTRL2_NUMBITS_POS) /**< CTRL2_NUMBITS_0 Setting */ #define MXC_F_SPI_CTRL2_DATA_WIDTH_POS 12 /**< CTRL2_DATA_WIDTH Position */ #define MXC_F_SPI_CTRL2_DATA_WIDTH ((uint32_t)(0x3UL << MXC_F_SPI_CTRL2_DATA_WIDTH_POS)) /**< CTRL2_DATA_WIDTH Mask */ @@ -259,16 +233,16 @@ typedef struct { #define MXC_F_SPI_CTRL2_THREE_WIRE_POS 15 /**< CTRL2_THREE_WIRE Position */ #define MXC_F_SPI_CTRL2_THREE_WIRE ((uint32_t)(0x1UL << MXC_F_SPI_CTRL2_THREE_WIRE_POS)) /**< CTRL2_THREE_WIRE Mask */ -#define MXC_F_SPI_CTRL2_SSPOL_POS 16 /**< CTRL2_SSPOL Position */ -#define MXC_F_SPI_CTRL2_SSPOL ((uint32_t)(0xFUL << MXC_F_SPI_CTRL2_SSPOL_POS)) /**< CTRL2_SSPOL Mask */ -#define MXC_V_SPI_CTRL2_SSPOL_SS0_HIGH ((uint32_t)0x1UL) /**< CTRL2_SSPOL_SS0_HIGH Value */ -#define MXC_S_SPI_CTRL2_SSPOL_SS0_HIGH (MXC_V_SPI_CTRL2_SSPOL_SS0_HIGH << MXC_F_SPI_CTRL2_SSPOL_POS) /**< CTRL2_SSPOL_SS0_HIGH Setting */ -#define MXC_V_SPI_CTRL2_SSPOL_SS1_HIGH ((uint32_t)0x2UL) /**< CTRL2_SSPOL_SS1_HIGH Value */ -#define MXC_S_SPI_CTRL2_SSPOL_SS1_HIGH (MXC_V_SPI_CTRL2_SSPOL_SS1_HIGH << MXC_F_SPI_CTRL2_SSPOL_POS) /**< CTRL2_SSPOL_SS1_HIGH Setting */ -#define MXC_V_SPI_CTRL2_SSPOL_SS2_HIGH ((uint32_t)0x4UL) /**< CTRL2_SSPOL_SS2_HIGH Value */ -#define MXC_S_SPI_CTRL2_SSPOL_SS2_HIGH (MXC_V_SPI_CTRL2_SSPOL_SS2_HIGH << MXC_F_SPI_CTRL2_SSPOL_POS) /**< CTRL2_SSPOL_SS2_HIGH Setting */ -#define MXC_V_SPI_CTRL2_SSPOL_SS3_HIGH ((uint32_t)0x8UL) /**< CTRL2_SSPOL_SS3_HIGH Value */ -#define MXC_S_SPI_CTRL2_SSPOL_SS3_HIGH (MXC_V_SPI_CTRL2_SSPOL_SS3_HIGH << MXC_F_SPI_CTRL2_SSPOL_POS) /**< CTRL2_SSPOL_SS3_HIGH Setting */ +#define MXC_F_SPI_CTRL2_SS_POL_POS 16 /**< CTRL2_SS_POL Position */ +#define MXC_F_SPI_CTRL2_SS_POL ((uint32_t)(0xFFUL << MXC_F_SPI_CTRL2_SS_POL_POS)) /**< CTRL2_SS_POL Mask */ +#define MXC_V_SPI_CTRL2_SS_POL_SS0_HIGH ((uint32_t)0x1UL) /**< CTRL2_SS_POL_SS0_HIGH Value */ +#define MXC_S_SPI_CTRL2_SS_POL_SS0_HIGH (MXC_V_SPI_CTRL2_SS_POL_SS0_HIGH << MXC_F_SPI_CTRL2_SS_POL_POS) /**< CTRL2_SS_POL_SS0_HIGH Setting */ +#define MXC_V_SPI_CTRL2_SS_POL_SS1_HIGH ((uint32_t)0x2UL) /**< CTRL2_SS_POL_SS1_HIGH Value */ +#define MXC_S_SPI_CTRL2_SS_POL_SS1_HIGH (MXC_V_SPI_CTRL2_SS_POL_SS1_HIGH << MXC_F_SPI_CTRL2_SS_POL_POS) /**< CTRL2_SS_POL_SS1_HIGH Setting */ +#define MXC_V_SPI_CTRL2_SS_POL_SS2_HIGH ((uint32_t)0x4UL) /**< CTRL2_SS_POL_SS2_HIGH Value */ +#define MXC_S_SPI_CTRL2_SS_POL_SS2_HIGH (MXC_V_SPI_CTRL2_SS_POL_SS2_HIGH << MXC_F_SPI_CTRL2_SS_POL_POS) /**< CTRL2_SS_POL_SS2_HIGH Setting */ +#define MXC_V_SPI_CTRL2_SS_POL_SS3_HIGH ((uint32_t)0x8UL) /**< CTRL2_SS_POL_SS3_HIGH Value */ +#define MXC_S_SPI_CTRL2_SS_POL_SS3_HIGH (MXC_V_SPI_CTRL2_SS_POL_SS3_HIGH << MXC_F_SPI_CTRL2_SS_POL_POS) /**< CTRL2_SS_POL_SS3_HIGH Setting */ /**@} end of group SPI_CTRL2_Register */ @@ -334,8 +308,8 @@ typedef struct { #define MXC_F_SPI_DMA_TX_LVL_POS 8 /**< DMA_TX_LVL Position */ #define MXC_F_SPI_DMA_TX_LVL ((uint32_t)(0x3FUL << MXC_F_SPI_DMA_TX_LVL_POS)) /**< DMA_TX_LVL Mask */ -#define MXC_F_SPI_DMA_TX_EN_POS 15 /**< DMA_TX_EN Position */ -#define MXC_F_SPI_DMA_TX_EN ((uint32_t)(0x1UL << MXC_F_SPI_DMA_TX_EN_POS)) /**< DMA_TX_EN Mask */ +#define MXC_F_SPI_DMA_DMA_TX_EN_POS 15 /**< DMA_DMA_TX_EN Position */ +#define MXC_F_SPI_DMA_DMA_TX_EN ((uint32_t)(0x1UL << MXC_F_SPI_DMA_DMA_TX_EN_POS)) /**< DMA_DMA_TX_EN Mask */ #define MXC_F_SPI_DMA_RX_THD_VAL_POS 16 /**< DMA_RX_THD_VAL Position */ #define MXC_F_SPI_DMA_RX_THD_VAL ((uint32_t)(0x1FUL << MXC_F_SPI_DMA_RX_THD_VAL_POS)) /**< DMA_RX_THD_VAL Mask */ @@ -349,8 +323,8 @@ typedef struct { #define MXC_F_SPI_DMA_RX_LVL_POS 24 /**< DMA_RX_LVL Position */ #define MXC_F_SPI_DMA_RX_LVL ((uint32_t)(0x3FUL << MXC_F_SPI_DMA_RX_LVL_POS)) /**< DMA_RX_LVL Mask */ -#define MXC_F_SPI_DMA_RX_EN_POS 31 /**< DMA_RX_EN Position */ -#define MXC_F_SPI_DMA_RX_EN ((uint32_t)(0x1UL << MXC_F_SPI_DMA_RX_EN_POS)) /**< DMA_RX_EN Mask */ +#define MXC_F_SPI_DMA_DMA_RX_EN_POS 31 /**< DMA_DMA_RX_EN Position */ +#define MXC_F_SPI_DMA_DMA_RX_EN ((uint32_t)(0x1UL << MXC_F_SPI_DMA_DMA_RX_EN_POS)) /**< DMA_DMA_RX_EN Mask */ /**@} end of group SPI_DMA_Register */ @@ -491,17 +465,17 @@ typedef struct { /** * @ingroup spi_registers - * @defgroup SPI_STATUS SPI_STATUS + * @defgroup SPI_STAT SPI_STAT * @brief SPI Status register. * @{ */ -#define MXC_F_SPI_STATUS_BUSY_POS 0 /**< STATUS_BUSY Position */ -#define MXC_F_SPI_STATUS_BUSY ((uint32_t)(0x1UL << MXC_F_SPI_STATUS_BUSY_POS)) /**< STATUS_BUSY Mask */ +#define MXC_F_SPI_STAT_BUSY_POS 0 /**< STAT_BUSY Position */ +#define MXC_F_SPI_STAT_BUSY ((uint32_t)(0x1UL << MXC_F_SPI_STAT_BUSY_POS)) /**< STAT_BUSY Mask */ -/**@} end of group SPI_STATUS_Register */ +/**@} end of group SPI_STAT_Register */ #ifdef __cplusplus } #endif -#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_SPI_REGS_H_ +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32672_INCLUDE_SPI_REGS_H_ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32572/Include/spixfc_fifo_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32572/Include/spixfc_fifo_regs.h index 12de3bdcbf8..6f1c0160054 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32572/Include/spixfc_fifo_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32572/Include/spixfc_fifo_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32572/Include/spixfc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32572/Include/spixfc_regs.h index 774e2ee551a..a8d385695d7 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32572/Include/spixfc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32572/Include/spixfc_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32572/Include/spixfm_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32572/Include/spixfm_regs.h index 89115ec20dd..466724d8171 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32572/Include/spixfm_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32572/Include/spixfm_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32572/Include/sys_aeskeys_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32572/Include/sys_aeskeys_regs.h new file mode 100644 index 00000000000..30a311515da --- /dev/null +++ b/Libraries/CMSIS/Device/Maxim/MAX32572/Include/sys_aeskeys_regs.h @@ -0,0 +1,113 @@ +/** + * @file sys_aeskeys_regs.h + * @brief Registers, Bit Masks and Bit Positions for the SYS_AESKEYS Peripheral Module. + * @note This file is @generated. + * @ingroup sys_aeskeys_registers + */ + +/****************************************************************************** + * + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32672_INCLUDE_SYS_AESKEYS_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32672_INCLUDE_SYS_AESKEYS_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup sys_aeskeys + * @ingroup aes + * @defgroup sys_aeskeys_registers SYS_AESKEYS_Registers + * @brief Registers, Bit Masks and Bit Positions for the SYS_AESKEYS Peripheral Module. + * @details System AES Key Registers. + */ + +/** + * @ingroup sys_aeskeys_registers + * Structure type to access the SYS_AESKEYS Registers. + */ +typedef struct { + __IO uint32_t key0; /**< \b 0x00: SYS_AESKEYS KEY0 Register */ + __IO uint32_t key1; /**< \b 0x04: SYS_AESKEYS KEY1 Register */ + __IO uint32_t key2; /**< \b 0x08: SYS_AESKEYS KEY2 Register */ + __IO uint32_t key3; /**< \b 0x0C: SYS_AESKEYS KEY3 Register */ + __IO uint32_t key4; /**< \b 0x10: SYS_AESKEYS KEY4 Register */ + __IO uint32_t key5; /**< \b 0x14: SYS_AESKEYS KEY5 Register */ + __IO uint32_t key6; /**< \b 0x18: SYS_AESKEYS KEY6 Register */ + __IO uint32_t key7; /**< \b 0x1C: SYS_AESKEYS KEY7 Register */ +} mxc_sys_aeskeys_regs_t; + +/* Register offsets for module SYS_AESKEYS */ +/** + * @ingroup sys_aeskeys_registers + * @defgroup SYS_AESKEYS_Register_Offsets Register Offsets + * @brief SYS_AESKEYS Peripheral Register Offsets from the SYS_AESKEYS Base Peripheral Address. + * @{ + */ +#define MXC_R_SYS_AESKEYS_KEY0 ((uint32_t)0x00000000UL) /**< Offset from SYS_AESKEYS Base Address: 0x0000 */ +#define MXC_R_SYS_AESKEYS_KEY1 ((uint32_t)0x00000004UL) /**< Offset from SYS_AESKEYS Base Address: 0x0004 */ +#define MXC_R_SYS_AESKEYS_KEY2 ((uint32_t)0x00000008UL) /**< Offset from SYS_AESKEYS Base Address: 0x0008 */ +#define MXC_R_SYS_AESKEYS_KEY3 ((uint32_t)0x0000000CUL) /**< Offset from SYS_AESKEYS Base Address: 0x000C */ +#define MXC_R_SYS_AESKEYS_KEY4 ((uint32_t)0x00000010UL) /**< Offset from SYS_AESKEYS Base Address: 0x0010 */ +#define MXC_R_SYS_AESKEYS_KEY5 ((uint32_t)0x00000014UL) /**< Offset from SYS_AESKEYS Base Address: 0x0014 */ +#define MXC_R_SYS_AESKEYS_KEY6 ((uint32_t)0x00000018UL) /**< Offset from SYS_AESKEYS Base Address: 0x0018 */ +#define MXC_R_SYS_AESKEYS_KEY7 ((uint32_t)0x0000001CUL) /**< Offset from SYS_AESKEYS Base Address: 0x001C */ +/**@} end of group sys_aeskeys_registers */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32672_INCLUDE_SYS_AESKEYS_REGS_H_ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32572/Include/tmr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32572/Include/tmr_regs.h index 601436eeb9b..5bb43b39acf 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32572/Include/tmr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32572/Include/tmr_regs.h @@ -25,8 +25,8 @@ * ******************************************************************************/ -#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_TMR_REGS_H_ -#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_TMR_REGS_H_ +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32672_INCLUDE_TMR_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32672_INCLUDE_TMR_REGS_H_ /* **** Includes **** */ #include @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile @@ -66,7 +70,7 @@ extern "C" { * @ingroup tmr * @defgroup tmr_registers TMR_Registers * @brief Registers, Bit Masks and Bit Positions for the TMR Peripheral Module. - * @details 32-bit reloadable timer that can be used for timing and event counting. + * @details Low-Power Configurable Timer */ /** @@ -78,8 +82,10 @@ typedef struct { __IO uint32_t cmp; /**< \b 0x04: TMR CMP Register */ __IO uint32_t pwm; /**< \b 0x08: TMR PWM Register */ __IO uint32_t intfl; /**< \b 0x0C: TMR INTFL Register */ - __IO uint32_t ctrl; /**< \b 0x10: TMR CTRL Register */ + __IO uint32_t ctrl0; /**< \b 0x10: TMR CTRL0 Register */ __IO uint32_t nolcmp; /**< \b 0x14: TMR NOLCMP Register */ + __IO uint32_t ctrl1; /**< \b 0x18: TMR CTRL1 Register */ + __IO uint32_t wkfl; /**< \b 0x1C: TMR WKFL Register */ } mxc_tmr_regs_t; /* Register offsets for module TMR */ @@ -93,14 +99,16 @@ typedef struct { #define MXC_R_TMR_CMP ((uint32_t)0x00000004UL) /**< Offset from TMR Base Address: 0x0004 */ #define MXC_R_TMR_PWM ((uint32_t)0x00000008UL) /**< Offset from TMR Base Address: 0x0008 */ #define MXC_R_TMR_INTFL ((uint32_t)0x0000000CUL) /**< Offset from TMR Base Address: 0x000C */ -#define MXC_R_TMR_CTRL ((uint32_t)0x00000010UL) /**< Offset from TMR Base Address: 0x0010 */ +#define MXC_R_TMR_CTRL0 ((uint32_t)0x00000010UL) /**< Offset from TMR Base Address: 0x0010 */ #define MXC_R_TMR_NOLCMP ((uint32_t)0x00000014UL) /**< Offset from TMR Base Address: 0x0014 */ +#define MXC_R_TMR_CTRL1 ((uint32_t)0x00000018UL) /**< Offset from TMR Base Address: 0x0018 */ +#define MXC_R_TMR_WKFL ((uint32_t)0x0000001CUL) /**< Offset from TMR Base Address: 0x001C */ /**@} end of group tmr_registers */ /** * @ingroup tmr_registers * @defgroup TMR_CNT TMR_CNT - * @brief Count. This register stores the current timer count. + * @brief Timer Counter Register. * @{ */ #define MXC_F_TMR_CNT_COUNT_POS 0 /**< CNT_COUNT Position */ @@ -111,8 +119,7 @@ typedef struct { /** * @ingroup tmr_registers * @defgroup TMR_CMP TMR_CMP - * @brief Compare. This register stores the compare value, which is used to set the - * maximum count value to initiate a reload of the timer to 0x0001. + * @brief Timer Compare Register. * @{ */ #define MXC_F_TMR_CMP_COMPARE_POS 0 /**< CMP_COMPARE Position */ @@ -123,8 +130,7 @@ typedef struct { /** * @ingroup tmr_registers * @defgroup TMR_PWM TMR_PWM - * @brief PWM. This register stores the value that is compared to the current timer - * count. + * @brief Timer PWM Register. * @{ */ #define MXC_F_TMR_PWM_PWM_POS 0 /**< PWM_PWM Position */ @@ -135,81 +141,188 @@ typedef struct { /** * @ingroup tmr_registers * @defgroup TMR_INTFL TMR_INTFL - * @brief Clear Interrupt. Writing a value (0 or 1) to a bit in this register clears the - * associated interrupt. + * @brief Timer Interrupt Status Register. * @{ */ -#define MXC_F_TMR_INTFL_IRQ_POS 0 /**< INTFL_IRQ Position */ -#define MXC_F_TMR_INTFL_IRQ ((uint32_t)(0x1UL << MXC_F_TMR_INTFL_IRQ_POS)) /**< INTFL_IRQ Mask */ +#define MXC_F_TMR_INTFL_IRQ_A_POS 0 /**< INTFL_IRQ_A Position */ +#define MXC_F_TMR_INTFL_IRQ_A ((uint32_t)(0x1UL << MXC_F_TMR_INTFL_IRQ_A_POS)) /**< INTFL_IRQ_A Mask */ + +#define MXC_F_TMR_INTFL_WRDONE_A_POS 8 /**< INTFL_WRDONE_A Position */ +#define MXC_F_TMR_INTFL_WRDONE_A ((uint32_t)(0x1UL << MXC_F_TMR_INTFL_WRDONE_A_POS)) /**< INTFL_WRDONE_A Mask */ + +#define MXC_F_TMR_INTFL_WR_DIS_A_POS 9 /**< INTFL_WR_DIS_A Position */ +#define MXC_F_TMR_INTFL_WR_DIS_A ((uint32_t)(0x1UL << MXC_F_TMR_INTFL_WR_DIS_A_POS)) /**< INTFL_WR_DIS_A Mask */ + +#define MXC_F_TMR_INTFL_IRQ_B_POS 16 /**< INTFL_IRQ_B Position */ +#define MXC_F_TMR_INTFL_IRQ_B ((uint32_t)(0x1UL << MXC_F_TMR_INTFL_IRQ_B_POS)) /**< INTFL_IRQ_B Mask */ + +#define MXC_F_TMR_INTFL_WRDONE_B_POS 24 /**< INTFL_WRDONE_B Position */ +#define MXC_F_TMR_INTFL_WRDONE_B ((uint32_t)(0x1UL << MXC_F_TMR_INTFL_WRDONE_B_POS)) /**< INTFL_WRDONE_B Mask */ + +#define MXC_F_TMR_INTFL_WR_DIS_B_POS 25 /**< INTFL_WR_DIS_B Position */ +#define MXC_F_TMR_INTFL_WR_DIS_B ((uint32_t)(0x1UL << MXC_F_TMR_INTFL_WR_DIS_B_POS)) /**< INTFL_WR_DIS_B Mask */ /**@} end of group TMR_INTFL_Register */ /** * @ingroup tmr_registers - * @defgroup TMR_CTRL TMR_CTRL + * @defgroup TMR_CTRL0 TMR_CTRL0 * @brief Timer Control Register. * @{ */ -#define MXC_F_TMR_CTRL_MODE_POS 0 /**< CTRL_MODE Position */ -#define MXC_F_TMR_CTRL_MODE ((uint32_t)(0x7UL << MXC_F_TMR_CTRL_MODE_POS)) /**< CTRL_MODE Mask */ -#define MXC_V_TMR_CTRL_MODE_ONESHOT ((uint32_t)0x0UL) /**< CTRL_MODE_ONESHOT Value */ -#define MXC_S_TMR_CTRL_MODE_ONESHOT (MXC_V_TMR_CTRL_MODE_ONESHOT << MXC_F_TMR_CTRL_MODE_POS) /**< CTRL_MODE_ONESHOT Setting */ -#define MXC_V_TMR_CTRL_MODE_CONTINUOUS ((uint32_t)0x1UL) /**< CTRL_MODE_CONTINUOUS Value */ -#define MXC_S_TMR_CTRL_MODE_CONTINUOUS (MXC_V_TMR_CTRL_MODE_CONTINUOUS << MXC_F_TMR_CTRL_MODE_POS) /**< CTRL_MODE_CONTINUOUS Setting */ -#define MXC_V_TMR_CTRL_MODE_COUNTER ((uint32_t)0x2UL) /**< CTRL_MODE_COUNTER Value */ -#define MXC_S_TMR_CTRL_MODE_COUNTER (MXC_V_TMR_CTRL_MODE_COUNTER << MXC_F_TMR_CTRL_MODE_POS) /**< CTRL_MODE_COUNTER Setting */ -#define MXC_V_TMR_CTRL_MODE_PWM ((uint32_t)0x3UL) /**< CTRL_MODE_PWM Value */ -#define MXC_S_TMR_CTRL_MODE_PWM (MXC_V_TMR_CTRL_MODE_PWM << MXC_F_TMR_CTRL_MODE_POS) /**< CTRL_MODE_PWM Setting */ -#define MXC_V_TMR_CTRL_MODE_CAPTURE ((uint32_t)0x4UL) /**< CTRL_MODE_CAPTURE Value */ -#define MXC_S_TMR_CTRL_MODE_CAPTURE (MXC_V_TMR_CTRL_MODE_CAPTURE << MXC_F_TMR_CTRL_MODE_POS) /**< CTRL_MODE_CAPTURE Setting */ -#define MXC_V_TMR_CTRL_MODE_COMPARE ((uint32_t)0x5UL) /**< CTRL_MODE_COMPARE Value */ -#define MXC_S_TMR_CTRL_MODE_COMPARE (MXC_V_TMR_CTRL_MODE_COMPARE << MXC_F_TMR_CTRL_MODE_POS) /**< CTRL_MODE_COMPARE Setting */ -#define MXC_V_TMR_CTRL_MODE_GATED ((uint32_t)0x6UL) /**< CTRL_MODE_GATED Value */ -#define MXC_S_TMR_CTRL_MODE_GATED (MXC_V_TMR_CTRL_MODE_GATED << MXC_F_TMR_CTRL_MODE_POS) /**< CTRL_MODE_GATED Setting */ -#define MXC_V_TMR_CTRL_MODE_CAPTURECOMPARE ((uint32_t)0x7UL) /**< CTRL_MODE_CAPTURECOMPARE Value */ -#define MXC_S_TMR_CTRL_MODE_CAPTURECOMPARE (MXC_V_TMR_CTRL_MODE_CAPTURECOMPARE << MXC_F_TMR_CTRL_MODE_POS) /**< CTRL_MODE_CAPTURECOMPARE Setting */ - -#define MXC_F_TMR_CTRL_CLKDIV_POS 3 /**< CTRL_CLKDIV Position */ -#define MXC_F_TMR_CTRL_CLKDIV ((uint32_t)(0x7UL << MXC_F_TMR_CTRL_CLKDIV_POS)) /**< CTRL_CLKDIV Mask */ -#define MXC_V_TMR_CTRL_CLKDIV_DIV1 ((uint32_t)0x0UL) /**< CTRL_CLKDIV_DIV1 Value */ -#define MXC_S_TMR_CTRL_CLKDIV_DIV1 (MXC_V_TMR_CTRL_CLKDIV_DIV1 << MXC_F_TMR_CTRL_CLKDIV_POS) /**< CTRL_CLKDIV_DIV1 Setting */ -#define MXC_V_TMR_CTRL_CLKDIV_DIV2 ((uint32_t)0x1UL) /**< CTRL_CLKDIV_DIV2 Value */ -#define MXC_S_TMR_CTRL_CLKDIV_DIV2 (MXC_V_TMR_CTRL_CLKDIV_DIV2 << MXC_F_TMR_CTRL_CLKDIV_POS) /**< CTRL_CLKDIV_DIV2 Setting */ -#define MXC_V_TMR_CTRL_CLKDIV_DIV4 ((uint32_t)0x2UL) /**< CTRL_CLKDIV_DIV4 Value */ -#define MXC_S_TMR_CTRL_CLKDIV_DIV4 (MXC_V_TMR_CTRL_CLKDIV_DIV4 << MXC_F_TMR_CTRL_CLKDIV_POS) /**< CTRL_CLKDIV_DIV4 Setting */ -#define MXC_V_TMR_CTRL_CLKDIV_DIV8 ((uint32_t)0x3UL) /**< CTRL_CLKDIV_DIV8 Value */ -#define MXC_S_TMR_CTRL_CLKDIV_DIV8 (MXC_V_TMR_CTRL_CLKDIV_DIV8 << MXC_F_TMR_CTRL_CLKDIV_POS) /**< CTRL_CLKDIV_DIV8 Setting */ -#define MXC_V_TMR_CTRL_CLKDIV_DIV16 ((uint32_t)0x4UL) /**< CTRL_CLKDIV_DIV16 Value */ -#define MXC_S_TMR_CTRL_CLKDIV_DIV16 (MXC_V_TMR_CTRL_CLKDIV_DIV16 << MXC_F_TMR_CTRL_CLKDIV_POS) /**< CTRL_CLKDIV_DIV16 Setting */ -#define MXC_V_TMR_CTRL_CLKDIV_DIV32 ((uint32_t)0x5UL) /**< CTRL_CLKDIV_DIV32 Value */ -#define MXC_S_TMR_CTRL_CLKDIV_DIV32 (MXC_V_TMR_CTRL_CLKDIV_DIV32 << MXC_F_TMR_CTRL_CLKDIV_POS) /**< CTRL_CLKDIV_DIV32 Setting */ -#define MXC_V_TMR_CTRL_CLKDIV_DIV64 ((uint32_t)0x6UL) /**< CTRL_CLKDIV_DIV64 Value */ -#define MXC_S_TMR_CTRL_CLKDIV_DIV64 (MXC_V_TMR_CTRL_CLKDIV_DIV64 << MXC_F_TMR_CTRL_CLKDIV_POS) /**< CTRL_CLKDIV_DIV64 Setting */ -#define MXC_V_TMR_CTRL_CLKDIV_DIV128 ((uint32_t)0x7UL) /**< CTRL_CLKDIV_DIV128 Value */ -#define MXC_S_TMR_CTRL_CLKDIV_DIV128 (MXC_V_TMR_CTRL_CLKDIV_DIV128 << MXC_F_TMR_CTRL_CLKDIV_POS) /**< CTRL_CLKDIV_DIV128 Setting */ - -#define MXC_F_TMR_CTRL_POL_POS 6 /**< CTRL_POL Position */ -#define MXC_F_TMR_CTRL_POL ((uint32_t)(0x1UL << MXC_F_TMR_CTRL_POL_POS)) /**< CTRL_POL Mask */ - -#define MXC_F_TMR_CTRL_EN_POS 7 /**< CTRL_EN Position */ -#define MXC_F_TMR_CTRL_EN ((uint32_t)(0x1UL << MXC_F_TMR_CTRL_EN_POS)) /**< CTRL_EN Mask */ - -#define MXC_F_TMR_CTRL_CLKDIV3_POS 8 /**< CTRL_CLKDIV3 Position */ -#define MXC_F_TMR_CTRL_CLKDIV3 ((uint32_t)(0x1UL << MXC_F_TMR_CTRL_CLKDIV3_POS)) /**< CTRL_CLKDIV3 Mask */ - -#define MXC_F_TMR_CTRL_PWMSYNC_POS 9 /**< CTRL_PWMSYNC Position */ -#define MXC_F_TMR_CTRL_PWMSYNC ((uint32_t)(0x1UL << MXC_F_TMR_CTRL_PWMSYNC_POS)) /**< CTRL_PWMSYNC Mask */ - -#define MXC_F_TMR_CTRL_NOLHPOL_POS 10 /**< CTRL_NOLHPOL Position */ -#define MXC_F_TMR_CTRL_NOLHPOL ((uint32_t)(0x1UL << MXC_F_TMR_CTRL_NOLHPOL_POS)) /**< CTRL_NOLHPOL Mask */ - -#define MXC_F_TMR_CTRL_NOLLPOL_POS 11 /**< CTRL_NOLLPOL Position */ -#define MXC_F_TMR_CTRL_NOLLPOL ((uint32_t)(0x1UL << MXC_F_TMR_CTRL_NOLLPOL_POS)) /**< CTRL_NOLLPOL Mask */ - -#define MXC_F_TMR_CTRL_PWMCKBD_POS 12 /**< CTRL_PWMCKBD Position */ -#define MXC_F_TMR_CTRL_PWMCKBD ((uint32_t)(0x1UL << MXC_F_TMR_CTRL_PWMCKBD_POS)) /**< CTRL_PWMCKBD Mask */ - -/**@} end of group TMR_CTRL_Register */ +#define MXC_F_TMR_CTRL0_MODE_A_POS 0 /**< CTRL0_MODE_A Position */ +#define MXC_F_TMR_CTRL0_MODE_A ((uint32_t)(0xFUL << MXC_F_TMR_CTRL0_MODE_A_POS)) /**< CTRL0_MODE_A Mask */ +#define MXC_V_TMR_CTRL0_MODE_A_ONE_SHOT ((uint32_t)0x0UL) /**< CTRL0_MODE_A_ONE_SHOT Value */ +#define MXC_S_TMR_CTRL0_MODE_A_ONE_SHOT (MXC_V_TMR_CTRL0_MODE_A_ONE_SHOT << MXC_F_TMR_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_ONE_SHOT Setting */ +#define MXC_V_TMR_CTRL0_MODE_A_CONTINUOUS ((uint32_t)0x1UL) /**< CTRL0_MODE_A_CONTINUOUS Value */ +#define MXC_S_TMR_CTRL0_MODE_A_CONTINUOUS (MXC_V_TMR_CTRL0_MODE_A_CONTINUOUS << MXC_F_TMR_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_CONTINUOUS Setting */ +#define MXC_V_TMR_CTRL0_MODE_A_COUNTER ((uint32_t)0x2UL) /**< CTRL0_MODE_A_COUNTER Value */ +#define MXC_S_TMR_CTRL0_MODE_A_COUNTER (MXC_V_TMR_CTRL0_MODE_A_COUNTER << MXC_F_TMR_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_COUNTER Setting */ +#define MXC_V_TMR_CTRL0_MODE_A_PWM ((uint32_t)0x3UL) /**< CTRL0_MODE_A_PWM Value */ +#define MXC_S_TMR_CTRL0_MODE_A_PWM (MXC_V_TMR_CTRL0_MODE_A_PWM << MXC_F_TMR_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_PWM Setting */ +#define MXC_V_TMR_CTRL0_MODE_A_CAPTURE ((uint32_t)0x4UL) /**< CTRL0_MODE_A_CAPTURE Value */ +#define MXC_S_TMR_CTRL0_MODE_A_CAPTURE (MXC_V_TMR_CTRL0_MODE_A_CAPTURE << MXC_F_TMR_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_CAPTURE Setting */ +#define MXC_V_TMR_CTRL0_MODE_A_COMPARE ((uint32_t)0x5UL) /**< CTRL0_MODE_A_COMPARE Value */ +#define MXC_S_TMR_CTRL0_MODE_A_COMPARE (MXC_V_TMR_CTRL0_MODE_A_COMPARE << MXC_F_TMR_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_COMPARE Setting */ +#define MXC_V_TMR_CTRL0_MODE_A_GATED ((uint32_t)0x6UL) /**< CTRL0_MODE_A_GATED Value */ +#define MXC_S_TMR_CTRL0_MODE_A_GATED (MXC_V_TMR_CTRL0_MODE_A_GATED << MXC_F_TMR_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_GATED Setting */ +#define MXC_V_TMR_CTRL0_MODE_A_CAPCOMP ((uint32_t)0x7UL) /**< CTRL0_MODE_A_CAPCOMP Value */ +#define MXC_S_TMR_CTRL0_MODE_A_CAPCOMP (MXC_V_TMR_CTRL0_MODE_A_CAPCOMP << MXC_F_TMR_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_CAPCOMP Setting */ +#define MXC_V_TMR_CTRL0_MODE_A_DUAL_EDGE ((uint32_t)0x8UL) /**< CTRL0_MODE_A_DUAL_EDGE Value */ +#define MXC_S_TMR_CTRL0_MODE_A_DUAL_EDGE (MXC_V_TMR_CTRL0_MODE_A_DUAL_EDGE << MXC_F_TMR_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_DUAL_EDGE Setting */ +#define MXC_V_TMR_CTRL0_MODE_A_IGATED ((uint32_t)0xCUL) /**< CTRL0_MODE_A_IGATED Value */ +#define MXC_S_TMR_CTRL0_MODE_A_IGATED (MXC_V_TMR_CTRL0_MODE_A_IGATED << MXC_F_TMR_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_IGATED Setting */ + +#define MXC_F_TMR_CTRL0_CLKDIV_A_POS 4 /**< CTRL0_CLKDIV_A Position */ +#define MXC_F_TMR_CTRL0_CLKDIV_A ((uint32_t)(0xFUL << MXC_F_TMR_CTRL0_CLKDIV_A_POS)) /**< CTRL0_CLKDIV_A Mask */ +#define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_1 ((uint32_t)0x0UL) /**< CTRL0_CLKDIV_A_DIV_BY_1 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_1 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_1 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_1 Setting */ +#define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_2 ((uint32_t)0x1UL) /**< CTRL0_CLKDIV_A_DIV_BY_2 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_2 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_2 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_2 Setting */ +#define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_4 ((uint32_t)0x2UL) /**< CTRL0_CLKDIV_A_DIV_BY_4 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_4 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_4 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_4 Setting */ +#define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_8 ((uint32_t)0x3UL) /**< CTRL0_CLKDIV_A_DIV_BY_8 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_8 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_8 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_8 Setting */ +#define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_16 ((uint32_t)0x4UL) /**< CTRL0_CLKDIV_A_DIV_BY_16 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_16 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_16 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_16 Setting */ +#define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_32 ((uint32_t)0x5UL) /**< CTRL0_CLKDIV_A_DIV_BY_32 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_32 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_32 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_32 Setting */ +#define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_64 ((uint32_t)0x6UL) /**< CTRL0_CLKDIV_A_DIV_BY_64 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_64 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_64 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_64 Setting */ +#define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_128 ((uint32_t)0x7UL) /**< CTRL0_CLKDIV_A_DIV_BY_128 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_128 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_128 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_128 Setting */ +#define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_256 ((uint32_t)0x8UL) /**< CTRL0_CLKDIV_A_DIV_BY_256 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_256 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_256 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_256 Setting */ +#define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_512 ((uint32_t)0x9UL) /**< CTRL0_CLKDIV_A_DIV_BY_512 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_512 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_512 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_512 Setting */ +#define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_1024 ((uint32_t)0xAUL) /**< CTRL0_CLKDIV_A_DIV_BY_1024 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_1024 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_1024 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_1024 Setting */ +#define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_2048 ((uint32_t)0xBUL) /**< CTRL0_CLKDIV_A_DIV_BY_2048 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_2048 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_2048 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_2048 Setting */ +#define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_4096 ((uint32_t)0xCUL) /**< CTRL0_CLKDIV_A_DIV_BY_4096 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_4096 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_4096 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_4096 Setting */ + +#define MXC_F_TMR_CTRL0_POL_A_POS 8 /**< CTRL0_POL_A Position */ +#define MXC_F_TMR_CTRL0_POL_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_POL_A_POS)) /**< CTRL0_POL_A Mask */ + +#define MXC_F_TMR_CTRL0_PWMSYNC_A_POS 9 /**< CTRL0_PWMSYNC_A Position */ +#define MXC_F_TMR_CTRL0_PWMSYNC_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_PWMSYNC_A_POS)) /**< CTRL0_PWMSYNC_A Mask */ + +#define MXC_F_TMR_CTRL0_NOLHPOL_A_POS 10 /**< CTRL0_NOLHPOL_A Position */ +#define MXC_F_TMR_CTRL0_NOLHPOL_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_NOLHPOL_A_POS)) /**< CTRL0_NOLHPOL_A Mask */ + +#define MXC_F_TMR_CTRL0_NOLLPOL_A_POS 11 /**< CTRL0_NOLLPOL_A Position */ +#define MXC_F_TMR_CTRL0_NOLLPOL_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_NOLLPOL_A_POS)) /**< CTRL0_NOLLPOL_A Mask */ + +#define MXC_F_TMR_CTRL0_PWMCKBD_A_POS 12 /**< CTRL0_PWMCKBD_A Position */ +#define MXC_F_TMR_CTRL0_PWMCKBD_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_PWMCKBD_A_POS)) /**< CTRL0_PWMCKBD_A Mask */ + +#define MXC_F_TMR_CTRL0_RST_A_POS 13 /**< CTRL0_RST_A Position */ +#define MXC_F_TMR_CTRL0_RST_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_RST_A_POS)) /**< CTRL0_RST_A Mask */ + +#define MXC_F_TMR_CTRL0_CLKEN_A_POS 14 /**< CTRL0_CLKEN_A Position */ +#define MXC_F_TMR_CTRL0_CLKEN_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_CLKEN_A_POS)) /**< CTRL0_CLKEN_A Mask */ + +#define MXC_F_TMR_CTRL0_EN_A_POS 15 /**< CTRL0_EN_A Position */ +#define MXC_F_TMR_CTRL0_EN_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_EN_A_POS)) /**< CTRL0_EN_A Mask */ + +#define MXC_F_TMR_CTRL0_MODE_B_POS 16 /**< CTRL0_MODE_B Position */ +#define MXC_F_TMR_CTRL0_MODE_B ((uint32_t)(0xFUL << MXC_F_TMR_CTRL0_MODE_B_POS)) /**< CTRL0_MODE_B Mask */ +#define MXC_V_TMR_CTRL0_MODE_B_ONE_SHOT ((uint32_t)0x0UL) /**< CTRL0_MODE_B_ONE_SHOT Value */ +#define MXC_S_TMR_CTRL0_MODE_B_ONE_SHOT (MXC_V_TMR_CTRL0_MODE_B_ONE_SHOT << MXC_F_TMR_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_ONE_SHOT Setting */ +#define MXC_V_TMR_CTRL0_MODE_B_CONTINUOUS ((uint32_t)0x1UL) /**< CTRL0_MODE_B_CONTINUOUS Value */ +#define MXC_S_TMR_CTRL0_MODE_B_CONTINUOUS (MXC_V_TMR_CTRL0_MODE_B_CONTINUOUS << MXC_F_TMR_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_CONTINUOUS Setting */ +#define MXC_V_TMR_CTRL0_MODE_B_COUNTER ((uint32_t)0x2UL) /**< CTRL0_MODE_B_COUNTER Value */ +#define MXC_S_TMR_CTRL0_MODE_B_COUNTER (MXC_V_TMR_CTRL0_MODE_B_COUNTER << MXC_F_TMR_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_COUNTER Setting */ +#define MXC_V_TMR_CTRL0_MODE_B_PWM ((uint32_t)0x3UL) /**< CTRL0_MODE_B_PWM Value */ +#define MXC_S_TMR_CTRL0_MODE_B_PWM (MXC_V_TMR_CTRL0_MODE_B_PWM << MXC_F_TMR_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_PWM Setting */ +#define MXC_V_TMR_CTRL0_MODE_B_CAPTURE ((uint32_t)0x4UL) /**< CTRL0_MODE_B_CAPTURE Value */ +#define MXC_S_TMR_CTRL0_MODE_B_CAPTURE (MXC_V_TMR_CTRL0_MODE_B_CAPTURE << MXC_F_TMR_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_CAPTURE Setting */ +#define MXC_V_TMR_CTRL0_MODE_B_COMPARE ((uint32_t)0x5UL) /**< CTRL0_MODE_B_COMPARE Value */ +#define MXC_S_TMR_CTRL0_MODE_B_COMPARE (MXC_V_TMR_CTRL0_MODE_B_COMPARE << MXC_F_TMR_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_COMPARE Setting */ +#define MXC_V_TMR_CTRL0_MODE_B_GATED ((uint32_t)0x6UL) /**< CTRL0_MODE_B_GATED Value */ +#define MXC_S_TMR_CTRL0_MODE_B_GATED (MXC_V_TMR_CTRL0_MODE_B_GATED << MXC_F_TMR_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_GATED Setting */ +#define MXC_V_TMR_CTRL0_MODE_B_CAPCOMP ((uint32_t)0x7UL) /**< CTRL0_MODE_B_CAPCOMP Value */ +#define MXC_S_TMR_CTRL0_MODE_B_CAPCOMP (MXC_V_TMR_CTRL0_MODE_B_CAPCOMP << MXC_F_TMR_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_CAPCOMP Setting */ +#define MXC_V_TMR_CTRL0_MODE_B_DUAL_EDGE ((uint32_t)0x8UL) /**< CTRL0_MODE_B_DUAL_EDGE Value */ +#define MXC_S_TMR_CTRL0_MODE_B_DUAL_EDGE (MXC_V_TMR_CTRL0_MODE_B_DUAL_EDGE << MXC_F_TMR_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_DUAL_EDGE Setting */ +#define MXC_V_TMR_CTRL0_MODE_B_IGATED ((uint32_t)0xEUL) /**< CTRL0_MODE_B_IGATED Value */ +#define MXC_S_TMR_CTRL0_MODE_B_IGATED (MXC_V_TMR_CTRL0_MODE_B_IGATED << MXC_F_TMR_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_IGATED Setting */ + +#define MXC_F_TMR_CTRL0_CLKDIV_B_POS 20 /**< CTRL0_CLKDIV_B Position */ +#define MXC_F_TMR_CTRL0_CLKDIV_B ((uint32_t)(0xFUL << MXC_F_TMR_CTRL0_CLKDIV_B_POS)) /**< CTRL0_CLKDIV_B Mask */ +#define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_1 ((uint32_t)0x0UL) /**< CTRL0_CLKDIV_B_DIV_BY_1 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_1 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_1 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_1 Setting */ +#define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_2 ((uint32_t)0x1UL) /**< CTRL0_CLKDIV_B_DIV_BY_2 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_2 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_2 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_2 Setting */ +#define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_4 ((uint32_t)0x2UL) /**< CTRL0_CLKDIV_B_DIV_BY_4 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_4 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_4 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_4 Setting */ +#define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_8 ((uint32_t)0x3UL) /**< CTRL0_CLKDIV_B_DIV_BY_8 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_8 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_8 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_8 Setting */ +#define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_16 ((uint32_t)0x4UL) /**< CTRL0_CLKDIV_B_DIV_BY_16 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_16 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_16 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_16 Setting */ +#define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_32 ((uint32_t)0x5UL) /**< CTRL0_CLKDIV_B_DIV_BY_32 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_32 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_32 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_32 Setting */ +#define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_64 ((uint32_t)0x6UL) /**< CTRL0_CLKDIV_B_DIV_BY_64 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_64 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_64 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_64 Setting */ +#define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_128 ((uint32_t)0x7UL) /**< CTRL0_CLKDIV_B_DIV_BY_128 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_128 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_128 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_128 Setting */ +#define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_256 ((uint32_t)0x8UL) /**< CTRL0_CLKDIV_B_DIV_BY_256 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_256 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_256 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_256 Setting */ +#define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_512 ((uint32_t)0x9UL) /**< CTRL0_CLKDIV_B_DIV_BY_512 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_512 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_512 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_512 Setting */ +#define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_1024 ((uint32_t)0xAUL) /**< CTRL0_CLKDIV_B_DIV_BY_1024 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_1024 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_1024 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_1024 Setting */ +#define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_2048 ((uint32_t)0xBUL) /**< CTRL0_CLKDIV_B_DIV_BY_2048 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_2048 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_2048 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_2048 Setting */ +#define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_4096 ((uint32_t)0xCUL) /**< CTRL0_CLKDIV_B_DIV_BY_4096 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_4096 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_4096 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_4096 Setting */ + +#define MXC_F_TMR_CTRL0_POL_B_POS 24 /**< CTRL0_POL_B Position */ +#define MXC_F_TMR_CTRL0_POL_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_POL_B_POS)) /**< CTRL0_POL_B Mask */ + +#define MXC_F_TMR_CTRL0_PWMSYNC_B_POS 25 /**< CTRL0_PWMSYNC_B Position */ +#define MXC_F_TMR_CTRL0_PWMSYNC_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_PWMSYNC_B_POS)) /**< CTRL0_PWMSYNC_B Mask */ + +#define MXC_F_TMR_CTRL0_NOLHPOL_B_POS 26 /**< CTRL0_NOLHPOL_B Position */ +#define MXC_F_TMR_CTRL0_NOLHPOL_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_NOLHPOL_B_POS)) /**< CTRL0_NOLHPOL_B Mask */ + +#define MXC_F_TMR_CTRL0_NOLLPOL_B_POS 27 /**< CTRL0_NOLLPOL_B Position */ +#define MXC_F_TMR_CTRL0_NOLLPOL_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_NOLLPOL_B_POS)) /**< CTRL0_NOLLPOL_B Mask */ + +#define MXC_F_TMR_CTRL0_PWMCKBD_B_POS 28 /**< CTRL0_PWMCKBD_B Position */ +#define MXC_F_TMR_CTRL0_PWMCKBD_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_PWMCKBD_B_POS)) /**< CTRL0_PWMCKBD_B Mask */ + +#define MXC_F_TMR_CTRL0_RST_B_POS 29 /**< CTRL0_RST_B Position */ +#define MXC_F_TMR_CTRL0_RST_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_RST_B_POS)) /**< CTRL0_RST_B Mask */ + +#define MXC_F_TMR_CTRL0_CLKEN_B_POS 30 /**< CTRL0_CLKEN_B Position */ +#define MXC_F_TMR_CTRL0_CLKEN_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_CLKEN_B_POS)) /**< CTRL0_CLKEN_B Mask */ + +#define MXC_F_TMR_CTRL0_EN_B_POS 31 /**< CTRL0_EN_B Position */ +#define MXC_F_TMR_CTRL0_EN_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_EN_B_POS)) /**< CTRL0_EN_B Mask */ + +/**@} end of group TMR_CTRL0_Register */ /** * @ingroup tmr_registers @@ -217,16 +330,107 @@ typedef struct { * @brief Timer Non-Overlapping Compare Register. * @{ */ -#define MXC_F_TMR_NOLCMP_LO_POS 0 /**< NOLCMP_LO Position */ -#define MXC_F_TMR_NOLCMP_LO ((uint32_t)(0xFFUL << MXC_F_TMR_NOLCMP_LO_POS)) /**< NOLCMP_LO Mask */ +#define MXC_F_TMR_NOLCMP_LO_A_POS 0 /**< NOLCMP_LO_A Position */ +#define MXC_F_TMR_NOLCMP_LO_A ((uint32_t)(0xFFUL << MXC_F_TMR_NOLCMP_LO_A_POS)) /**< NOLCMP_LO_A Mask */ + +#define MXC_F_TMR_NOLCMP_HI_A_POS 8 /**< NOLCMP_HI_A Position */ +#define MXC_F_TMR_NOLCMP_HI_A ((uint32_t)(0xFFUL << MXC_F_TMR_NOLCMP_HI_A_POS)) /**< NOLCMP_HI_A Mask */ + +#define MXC_F_TMR_NOLCMP_LO_B_POS 16 /**< NOLCMP_LO_B Position */ +#define MXC_F_TMR_NOLCMP_LO_B ((uint32_t)(0xFFUL << MXC_F_TMR_NOLCMP_LO_B_POS)) /**< NOLCMP_LO_B Mask */ -#define MXC_F_TMR_NOLCMP_HI_POS 8 /**< NOLCMP_HI Position */ -#define MXC_F_TMR_NOLCMP_HI ((uint32_t)(0xFFUL << MXC_F_TMR_NOLCMP_HI_POS)) /**< NOLCMP_HI Mask */ +#define MXC_F_TMR_NOLCMP_HI_B_POS 24 /**< NOLCMP_HI_B Position */ +#define MXC_F_TMR_NOLCMP_HI_B ((uint32_t)(0xFFUL << MXC_F_TMR_NOLCMP_HI_B_POS)) /**< NOLCMP_HI_B Mask */ /**@} end of group TMR_NOLCMP_Register */ +/** + * @ingroup tmr_registers + * @defgroup TMR_CTRL1 TMR_CTRL1 + * @brief Timer Configuration Register. + * @{ + */ +#define MXC_F_TMR_CTRL1_CLKSEL_A_POS 0 /**< CTRL1_CLKSEL_A Position */ +#define MXC_F_TMR_CTRL1_CLKSEL_A ((uint32_t)(0x3UL << MXC_F_TMR_CTRL1_CLKSEL_A_POS)) /**< CTRL1_CLKSEL_A Mask */ + +#define MXC_F_TMR_CTRL1_CLKEN_A_POS 2 /**< CTRL1_CLKEN_A Position */ +#define MXC_F_TMR_CTRL1_CLKEN_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_CLKEN_A_POS)) /**< CTRL1_CLKEN_A Mask */ + +#define MXC_F_TMR_CTRL1_CLKRDY_A_POS 3 /**< CTRL1_CLKRDY_A Position */ +#define MXC_F_TMR_CTRL1_CLKRDY_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_CLKRDY_A_POS)) /**< CTRL1_CLKRDY_A Mask */ + +#define MXC_F_TMR_CTRL1_EVENT_SEL_A_POS 4 /**< CTRL1_EVENT_SEL_A Position */ +#define MXC_F_TMR_CTRL1_EVENT_SEL_A ((uint32_t)(0x7UL << MXC_F_TMR_CTRL1_EVENT_SEL_A_POS)) /**< CTRL1_EVENT_SEL_A Mask */ + +#define MXC_F_TMR_CTRL1_NEGTRIG_A_POS 7 /**< CTRL1_NEGTRIG_A Position */ +#define MXC_F_TMR_CTRL1_NEGTRIG_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_NEGTRIG_A_POS)) /**< CTRL1_NEGTRIG_A Mask */ + +#define MXC_F_TMR_CTRL1_IE_A_POS 8 /**< CTRL1_IE_A Position */ +#define MXC_F_TMR_CTRL1_IE_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_IE_A_POS)) /**< CTRL1_IE_A Mask */ + +#define MXC_F_TMR_CTRL1_CAPEVENT_SEL_A_POS 9 /**< CTRL1_CAPEVENT_SEL_A Position */ +#define MXC_F_TMR_CTRL1_CAPEVENT_SEL_A ((uint32_t)(0x3UL << MXC_F_TMR_CTRL1_CAPEVENT_SEL_A_POS)) /**< CTRL1_CAPEVENT_SEL_A Mask */ + +#define MXC_F_TMR_CTRL1_SW_CAPEVENT_A_POS 11 /**< CTRL1_SW_CAPEVENT_A Position */ +#define MXC_F_TMR_CTRL1_SW_CAPEVENT_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_SW_CAPEVENT_A_POS)) /**< CTRL1_SW_CAPEVENT_A Mask */ + +#define MXC_F_TMR_CTRL1_WE_A_POS 12 /**< CTRL1_WE_A Position */ +#define MXC_F_TMR_CTRL1_WE_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_WE_A_POS)) /**< CTRL1_WE_A Mask */ + +#define MXC_F_TMR_CTRL1_OUTEN_A_POS 13 /**< CTRL1_OUTEN_A Position */ +#define MXC_F_TMR_CTRL1_OUTEN_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_OUTEN_A_POS)) /**< CTRL1_OUTEN_A Mask */ + +#define MXC_F_TMR_CTRL1_OUTBEN_A_POS 14 /**< CTRL1_OUTBEN_A Position */ +#define MXC_F_TMR_CTRL1_OUTBEN_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_OUTBEN_A_POS)) /**< CTRL1_OUTBEN_A Mask */ + +#define MXC_F_TMR_CTRL1_CLKSEL_B_POS 16 /**< CTRL1_CLKSEL_B Position */ +#define MXC_F_TMR_CTRL1_CLKSEL_B ((uint32_t)(0x3UL << MXC_F_TMR_CTRL1_CLKSEL_B_POS)) /**< CTRL1_CLKSEL_B Mask */ + +#define MXC_F_TMR_CTRL1_CLKEN_B_POS 18 /**< CTRL1_CLKEN_B Position */ +#define MXC_F_TMR_CTRL1_CLKEN_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_CLKEN_B_POS)) /**< CTRL1_CLKEN_B Mask */ + +#define MXC_F_TMR_CTRL1_CLKRDY_B_POS 19 /**< CTRL1_CLKRDY_B Position */ +#define MXC_F_TMR_CTRL1_CLKRDY_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_CLKRDY_B_POS)) /**< CTRL1_CLKRDY_B Mask */ + +#define MXC_F_TMR_CTRL1_EVENT_SEL_B_POS 20 /**< CTRL1_EVENT_SEL_B Position */ +#define MXC_F_TMR_CTRL1_EVENT_SEL_B ((uint32_t)(0x7UL << MXC_F_TMR_CTRL1_EVENT_SEL_B_POS)) /**< CTRL1_EVENT_SEL_B Mask */ + +#define MXC_F_TMR_CTRL1_NEGTRIG_B_POS 23 /**< CTRL1_NEGTRIG_B Position */ +#define MXC_F_TMR_CTRL1_NEGTRIG_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_NEGTRIG_B_POS)) /**< CTRL1_NEGTRIG_B Mask */ + +#define MXC_F_TMR_CTRL1_IE_B_POS 24 /**< CTRL1_IE_B Position */ +#define MXC_F_TMR_CTRL1_IE_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_IE_B_POS)) /**< CTRL1_IE_B Mask */ + +#define MXC_F_TMR_CTRL1_CAPEVENT_SEL_B_POS 25 /**< CTRL1_CAPEVENT_SEL_B Position */ +#define MXC_F_TMR_CTRL1_CAPEVENT_SEL_B ((uint32_t)(0x3UL << MXC_F_TMR_CTRL1_CAPEVENT_SEL_B_POS)) /**< CTRL1_CAPEVENT_SEL_B Mask */ + +#define MXC_F_TMR_CTRL1_SW_CAPEVENT_B_POS 27 /**< CTRL1_SW_CAPEVENT_B Position */ +#define MXC_F_TMR_CTRL1_SW_CAPEVENT_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_SW_CAPEVENT_B_POS)) /**< CTRL1_SW_CAPEVENT_B Mask */ + +#define MXC_F_TMR_CTRL1_WE_B_POS 28 /**< CTRL1_WE_B Position */ +#define MXC_F_TMR_CTRL1_WE_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_WE_B_POS)) /**< CTRL1_WE_B Mask */ + +#define MXC_F_TMR_CTRL1_CASCADE_POS 31 /**< CTRL1_CASCADE Position */ +#define MXC_F_TMR_CTRL1_CASCADE ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_CASCADE_POS)) /**< CTRL1_CASCADE Mask */ + +/**@} end of group TMR_CTRL1_Register */ + +/** + * @ingroup tmr_registers + * @defgroup TMR_WKFL TMR_WKFL + * @brief Timer Wakeup Status Register. + * @{ + */ +#define MXC_F_TMR_WKFL_A_POS 0 /**< WKFL_A Position */ +#define MXC_F_TMR_WKFL_A ((uint32_t)(0x1UL << MXC_F_TMR_WKFL_A_POS)) /**< WKFL_A Mask */ + +#define MXC_F_TMR_WKFL_B_POS 16 /**< WKFL_B Position */ +#define MXC_F_TMR_WKFL_B ((uint32_t)(0x1UL << MXC_F_TMR_WKFL_B_POS)) /**< WKFL_B Mask */ + +/**@} end of group TMR_WKFL_Register */ + #ifdef __cplusplus } #endif -#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_TMR_REGS_H_ +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32672_INCLUDE_TMR_REGS_H_ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32572/Include/trimsir_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32572/Include/trimsir_regs.h index 3823b69b3c5..8c9b5eb8fbc 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32572/Include/trimsir_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32572/Include/trimsir_regs.h @@ -25,8 +25,8 @@ * ******************************************************************************/ -#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_TRIMSIR_REGS_H_ -#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_TRIMSIR_REGS_H_ +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32672_INCLUDE_TRIMSIR_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32672_INCLUDE_TRIMSIR_REGS_H_ /* **** Includes **** */ #include @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile @@ -75,8 +79,10 @@ extern "C" { */ typedef struct { __R uint32_t rsv_0x0_0x7[2]; - __I uint32_t bbsir2; /**< \b 0x08: TRIMSIR BBSIR2 Register */ - __I uint32_t bbsir3; /**< \b 0x0C: TRIMSIR BBSIR3 Register */ + __IO uint32_t bb_sir2; /**< \b 0x08: TRIMSIR BB_SIR2 Register */ + __IO uint32_t bb_sir3; /**< \b 0x0C: TRIMSIR BB_SIR3 Register */ + __R uint32_t rsv_0x10_0x17[2]; + __I uint32_t bb_sir6; /**< \b 0x18: TRIMSIR BB_SIR6 Register */ } mxc_trimsir_regs_t; /* Register offsets for module TRIMSIR */ @@ -86,12 +92,59 @@ typedef struct { * @brief TRIMSIR Peripheral Register Offsets from the TRIMSIR Base Peripheral Address. * @{ */ -#define MXC_R_TRIMSIR_BBSIR2 ((uint32_t)0x00000008UL) /**< Offset from TRIMSIR Base Address: 0x0008 */ -#define MXC_R_TRIMSIR_BBSIR3 ((uint32_t)0x0000000CUL) /**< Offset from TRIMSIR Base Address: 0x000C */ +#define MXC_R_TRIMSIR_BB_SIR2 ((uint32_t)0x00000008UL) /**< Offset from TRIMSIR Base Address: 0x0008 */ +#define MXC_R_TRIMSIR_BB_SIR3 ((uint32_t)0x0000000CUL) /**< Offset from TRIMSIR Base Address: 0x000C */ +#define MXC_R_TRIMSIR_BB_SIR6 ((uint32_t)0x00000018UL) /**< Offset from TRIMSIR Base Address: 0x0018 */ /**@} end of group trimsir_registers */ +/** + * @ingroup trimsir_registers + * @defgroup TRIMSIR_BB_SIR2 TRIMSIR_BB_SIR2 + * @brief System Init. Configuration Register 2. + * @{ + */ +#define MXC_F_TRIMSIR_BB_SIR2_TRIM_IBRO_RBIAS_POS 0 /**< BB_SIR2_TRIM_IBRO_RBIAS Position */ +#define MXC_F_TRIMSIR_BB_SIR2_TRIM_IBRO_RBIAS ((uint32_t)(0x3FUL << MXC_F_TRIMSIR_BB_SIR2_TRIM_IBRO_RBIAS_POS)) /**< BB_SIR2_TRIM_IBRO_RBIAS Mask */ + +#define MXC_F_TRIMSIR_BB_SIR2_RAM0_1ECCEN_POS 8 /**< BB_SIR2_RAM0_1ECCEN Position */ +#define MXC_F_TRIMSIR_BB_SIR2_RAM0_1ECCEN ((uint32_t)(0x1UL << MXC_F_TRIMSIR_BB_SIR2_RAM0_1ECCEN_POS)) /**< BB_SIR2_RAM0_1ECCEN Mask */ + +#define MXC_F_TRIMSIR_BB_SIR2_RAM2ECCEN_POS 9 /**< BB_SIR2_RAM2ECCEN Position */ +#define MXC_F_TRIMSIR_BB_SIR2_RAM2ECCEN ((uint32_t)(0x1UL << MXC_F_TRIMSIR_BB_SIR2_RAM2ECCEN_POS)) /**< BB_SIR2_RAM2ECCEN Mask */ + +#define MXC_F_TRIMSIR_BB_SIR2_RAM3ECCEN_POS 10 /**< BB_SIR2_RAM3ECCEN Position */ +#define MXC_F_TRIMSIR_BB_SIR2_RAM3ECCEN ((uint32_t)(0x1UL << MXC_F_TRIMSIR_BB_SIR2_RAM3ECCEN_POS)) /**< BB_SIR2_RAM3ECCEN Mask */ + +#define MXC_F_TRIMSIR_BB_SIR2_ICC0ECCEN_POS 11 /**< BB_SIR2_ICC0ECCEN Position */ +#define MXC_F_TRIMSIR_BB_SIR2_ICC0ECCEN ((uint32_t)(0x1UL << MXC_F_TRIMSIR_BB_SIR2_ICC0ECCEN_POS)) /**< BB_SIR2_ICC0ECCEN Mask */ + +#define MXC_F_TRIMSIR_BB_SIR2_FL0ECCEN_POS 12 /**< BB_SIR2_FL0ECCEN Position */ +#define MXC_F_TRIMSIR_BB_SIR2_FL0ECCEN ((uint32_t)(0x1UL << MXC_F_TRIMSIR_BB_SIR2_FL0ECCEN_POS)) /**< BB_SIR2_FL0ECCEN Mask */ + +#define MXC_F_TRIMSIR_BB_SIR2_FL1ECCEN_POS 13 /**< BB_SIR2_FL1ECCEN Position */ +#define MXC_F_TRIMSIR_BB_SIR2_FL1ECCEN ((uint32_t)(0x1UL << MXC_F_TRIMSIR_BB_SIR2_FL1ECCEN_POS)) /**< BB_SIR2_FL1ECCEN Mask */ + +#define MXC_F_TRIMSIR_BB_SIR2_TRIM_IBRO_POS 16 /**< BB_SIR2_TRIM_IBRO Position */ +#define MXC_F_TRIMSIR_BB_SIR2_TRIM_IBRO ((uint32_t)(0xFFFFUL << MXC_F_TRIMSIR_BB_SIR2_TRIM_IBRO_POS)) /**< BB_SIR2_TRIM_IBRO Mask */ + +/**@} end of group TRIMSIR_BB_SIR2_Register */ + +/** + * @ingroup trimsir_registers + * @defgroup TRIMSIR_BB_SIR6 TRIMSIR_BB_SIR6 + * @brief System Init. Configuration Register 6. + * @{ + */ +#define MXC_F_TRIMSIR_BB_SIR6_RTCX1TRIM_POS 4 /**< BB_SIR6_RTCX1TRIM Position */ +#define MXC_F_TRIMSIR_BB_SIR6_RTCX1TRIM ((uint32_t)(0x1FUL << MXC_F_TRIMSIR_BB_SIR6_RTCX1TRIM_POS)) /**< BB_SIR6_RTCX1TRIM Mask */ + +#define MXC_F_TRIMSIR_BB_SIR6_RTCX2TRIM_POS 9 /**< BB_SIR6_RTCX2TRIM Position */ +#define MXC_F_TRIMSIR_BB_SIR6_RTCX2TRIM ((uint32_t)(0x1FUL << MXC_F_TRIMSIR_BB_SIR6_RTCX2TRIM_POS)) /**< BB_SIR6_RTCX2TRIM Mask */ + +/**@} end of group TRIMSIR_BB_SIR6_Register */ + #ifdef __cplusplus } #endif -#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_TRIMSIR_REGS_H_ +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32672_INCLUDE_TRIMSIR_REGS_H_ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32572/Include/trng_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32572/Include/trng_regs.h index 4d742caaa85..506873f0a75 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32572/Include/trng_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32572/Include/trng_regs.h @@ -25,8 +25,8 @@ * ******************************************************************************/ -#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_TRNG_REGS_H_ -#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_TRNG_REGS_H_ +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32672_INCLUDE_TRNG_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32672_INCLUDE_TRNG_REGS_H_ /* **** Includes **** */ #include @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile @@ -77,8 +81,6 @@ typedef struct { __IO uint32_t ctrl; /**< \b 0x00: TRNG CTRL Register */ __IO uint32_t status; /**< \b 0x04: TRNG STATUS Register */ __I uint32_t data; /**< \b 0x08: TRNG DATA Register */ - __R uint32_t rsv_0xc_0x37[11]; - __IO uint32_t data_nist; /**< \b 0x38: TRNG DATA_NIST Register */ } mxc_trng_regs_t; /* Register offsets for module TRNG */ @@ -91,7 +93,6 @@ typedef struct { #define MXC_R_TRNG_CTRL ((uint32_t)0x00000000UL) /**< Offset from TRNG Base Address: 0x0000 */ #define MXC_R_TRNG_STATUS ((uint32_t)0x00000004UL) /**< Offset from TRNG Base Address: 0x0004 */ #define MXC_R_TRNG_DATA ((uint32_t)0x00000008UL) /**< Offset from TRNG Base Address: 0x0008 */ -#define MXC_R_TRNG_DATA_NIST ((uint32_t)0x00000038UL) /**< Offset from TRNG Base Address: 0x0038 */ /**@} end of group trng_registers */ /** @@ -100,54 +101,24 @@ typedef struct { * @brief TRNG Control Register. * @{ */ -#define MXC_F_TRNG_CTRL_OD_HEALTH_POS 0 /**< CTRL_OD_HEALTH Position */ -#define MXC_F_TRNG_CTRL_OD_HEALTH ((uint32_t)(0x1UL << MXC_F_TRNG_CTRL_OD_HEALTH_POS)) /**< CTRL_OD_HEALTH Mask */ +#define MXC_F_TRNG_CTRL_ODHT_POS 0 /**< CTRL_ODHT Position */ +#define MXC_F_TRNG_CTRL_ODHT ((uint32_t)(0x1UL << MXC_F_TRNG_CTRL_ODHT_POS)) /**< CTRL_ODHT Mask */ #define MXC_F_TRNG_CTRL_RND_IE_POS 1 /**< CTRL_RND_IE Position */ #define MXC_F_TRNG_CTRL_RND_IE ((uint32_t)(0x1UL << MXC_F_TRNG_CTRL_RND_IE_POS)) /**< CTRL_RND_IE Mask */ -#define MXC_F_TRNG_CTRL_HEALTH_IE_POS 2 /**< CTRL_HEALTH_IE Position */ -#define MXC_F_TRNG_CTRL_HEALTH_IE ((uint32_t)(0x1UL << MXC_F_TRNG_CTRL_HEALTH_IE_POS)) /**< CTRL_HEALTH_IE Mask */ - -#define MXC_F_TRNG_CTRL_MEU_KEYGEN_POS 3 /**< CTRL_MEU_KEYGEN Position */ -#define MXC_F_TRNG_CTRL_MEU_KEYGEN ((uint32_t)(0x1UL << MXC_F_TRNG_CTRL_MEU_KEYGEN_POS)) /**< CTRL_MEU_KEYGEN Mask */ - -#define MXC_F_TRNG_CTRL_XIP_KEYGEN_POS 4 /**< CTRL_XIP_KEYGEN Position */ -#define MXC_F_TRNG_CTRL_XIP_KEYGEN ((uint32_t)(0x1UL << MXC_F_TRNG_CTRL_XIP_KEYGEN_POS)) /**< CTRL_XIP_KEYGEN Mask */ +#define MXC_F_TRNG_CTRL_HEALTH_EN_POS 2 /**< CTRL_HEALTH_EN Position */ +#define MXC_F_TRNG_CTRL_HEALTH_EN ((uint32_t)(0x1UL << MXC_F_TRNG_CTRL_HEALTH_EN_POS)) /**< CTRL_HEALTH_EN Mask */ -#define MXC_F_TRNG_CTRL_OD_ROMON_POS 6 /**< CTRL_OD_ROMON Position */ -#define MXC_F_TRNG_CTRL_OD_ROMON ((uint32_t)(0x1UL << MXC_F_TRNG_CTRL_OD_ROMON_POS)) /**< CTRL_OD_ROMON Mask */ +#define MXC_F_TRNG_CTRL_AESKG_USR_POS 3 /**< CTRL_AESKG_USR Position */ +#define MXC_F_TRNG_CTRL_AESKG_USR ((uint32_t)(0x1UL << MXC_F_TRNG_CTRL_AESKG_USR_POS)) /**< CTRL_AESKG_USR Mask */ -#define MXC_F_TRNG_CTRL_OD_EE_POS 7 /**< CTRL_OD_EE Position */ -#define MXC_F_TRNG_CTRL_OD_EE ((uint32_t)(0x1UL << MXC_F_TRNG_CTRL_OD_EE_POS)) /**< CTRL_OD_EE Mask */ - -#define MXC_F_TRNG_CTRL_ROMON_EE_FOE_POS 8 /**< CTRL_ROMON_EE_FOE Position */ -#define MXC_F_TRNG_CTRL_ROMON_EE_FOE ((uint32_t)(0x1UL << MXC_F_TRNG_CTRL_ROMON_EE_FOE_POS)) /**< CTRL_ROMON_EE_FOE Mask */ - -#define MXC_F_TRNG_CTRL_ROMON_EE_FOD_POS 9 /**< CTRL_ROMON_EE_FOD Position */ -#define MXC_F_TRNG_CTRL_ROMON_EE_FOD ((uint32_t)(0x1UL << MXC_F_TRNG_CTRL_ROMON_EE_FOD_POS)) /**< CTRL_ROMON_EE_FOD Mask */ - -#define MXC_F_TRNG_CTRL_EBLS_POS 10 /**< CTRL_EBLS Position */ -#define MXC_F_TRNG_CTRL_EBLS ((uint32_t)(0x1UL << MXC_F_TRNG_CTRL_EBLS_POS)) /**< CTRL_EBLS Mask */ +#define MXC_F_TRNG_CTRL_AESKG_SYS_POS 4 /**< CTRL_AESKG_SYS Position */ +#define MXC_F_TRNG_CTRL_AESKG_SYS ((uint32_t)(0x1UL << MXC_F_TRNG_CTRL_AESKG_SYS_POS)) /**< CTRL_AESKG_SYS Mask */ #define MXC_F_TRNG_CTRL_KEYWIPE_POS 15 /**< CTRL_KEYWIPE Position */ #define MXC_F_TRNG_CTRL_KEYWIPE ((uint32_t)(0x1UL << MXC_F_TRNG_CTRL_KEYWIPE_POS)) /**< CTRL_KEYWIPE Mask */ -#define MXC_F_TRNG_CTRL_GET_TERO_CNT_POS 16 /**< CTRL_GET_TERO_CNT Position */ -#define MXC_F_TRNG_CTRL_GET_TERO_CNT ((uint32_t)(0x1UL << MXC_F_TRNG_CTRL_GET_TERO_CNT_POS)) /**< CTRL_GET_TERO_CNT Mask */ - -#define MXC_F_TRNG_CTRL_EE_DONE_IE_POS 23 /**< CTRL_EE_DONE_IE Position */ -#define MXC_F_TRNG_CTRL_EE_DONE_IE ((uint32_t)(0x1UL << MXC_F_TRNG_CTRL_EE_DONE_IE_POS)) /**< CTRL_EE_DONE_IE Mask */ - -#define MXC_F_TRNG_CTRL_ROMON_DIS_POS 24 /**< CTRL_ROMON_DIS Position */ -#define MXC_F_TRNG_CTRL_ROMON_DIS ((uint32_t)(0x7UL << MXC_F_TRNG_CTRL_ROMON_DIS_POS)) /**< CTRL_ROMON_DIS Mask */ -#define MXC_V_TRNG_CTRL_ROMON_DIS_RO_0 ((uint32_t)0x1UL) /**< CTRL_ROMON_DIS_RO_0 Value */ -#define MXC_S_TRNG_CTRL_ROMON_DIS_RO_0 (MXC_V_TRNG_CTRL_ROMON_DIS_RO_0 << MXC_F_TRNG_CTRL_ROMON_DIS_POS) /**< CTRL_ROMON_DIS_RO_0 Setting */ -#define MXC_V_TRNG_CTRL_ROMON_DIS_RO_1 ((uint32_t)0x2UL) /**< CTRL_ROMON_DIS_RO_1 Value */ -#define MXC_S_TRNG_CTRL_ROMON_DIS_RO_1 (MXC_V_TRNG_CTRL_ROMON_DIS_RO_1 << MXC_F_TRNG_CTRL_ROMON_DIS_POS) /**< CTRL_ROMON_DIS_RO_1 Setting */ -#define MXC_V_TRNG_CTRL_ROMON_DIS_RO_2 ((uint32_t)0x4UL) /**< CTRL_ROMON_DIS_RO_2 Value */ -#define MXC_S_TRNG_CTRL_ROMON_DIS_RO_2 (MXC_V_TRNG_CTRL_ROMON_DIS_RO_2 << MXC_F_TRNG_CTRL_ROMON_DIS_POS) /**< CTRL_ROMON_DIS_RO_2 Setting */ - /**@} end of group TRNG_CTRL_Register */ /** @@ -160,68 +131,20 @@ typedef struct { #define MXC_F_TRNG_STATUS_RDY_POS 0 /**< STATUS_RDY Position */ #define MXC_F_TRNG_STATUS_RDY ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_RDY_POS)) /**< STATUS_RDY Mask */ -#define MXC_F_TRNG_STATUS_OD_HEALTH_POS 1 /**< STATUS_OD_HEALTH Position */ -#define MXC_F_TRNG_STATUS_OD_HEALTH ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_OD_HEALTH_POS)) /**< STATUS_OD_HEALTH Mask */ +#define MXC_F_TRNG_STATUS_ODHT_POS 1 /**< STATUS_ODHT Position */ +#define MXC_F_TRNG_STATUS_ODHT ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_ODHT_POS)) /**< STATUS_ODHT Mask */ -#define MXC_F_TRNG_STATUS_HEALTH_POS 2 /**< STATUS_HEALTH Position */ -#define MXC_F_TRNG_STATUS_HEALTH ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_HEALTH_POS)) /**< STATUS_HEALTH Mask */ +#define MXC_F_TRNG_STATUS_HT_POS 2 /**< STATUS_HT Position */ +#define MXC_F_TRNG_STATUS_HT ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_HT_POS)) /**< STATUS_HT Mask */ #define MXC_F_TRNG_STATUS_SRCFAIL_POS 3 /**< STATUS_SRCFAIL Position */ #define MXC_F_TRNG_STATUS_SRCFAIL ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_SRCFAIL_POS)) /**< STATUS_SRCFAIL Mask */ -#define MXC_F_TRNG_STATUS_AES_KEYGEN_POS 4 /**< STATUS_AES_KEYGEN Position */ -#define MXC_F_TRNG_STATUS_AES_KEYGEN ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_AES_KEYGEN_POS)) /**< STATUS_AES_KEYGEN Mask */ - -#define MXC_F_TRNG_STATUS_OD_ROMON_POS 6 /**< STATUS_OD_ROMON Position */ -#define MXC_F_TRNG_STATUS_OD_ROMON ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_OD_ROMON_POS)) /**< STATUS_OD_ROMON Mask */ - -#define MXC_F_TRNG_STATUS_OD_EE_POS 7 /**< STATUS_OD_EE Position */ -#define MXC_F_TRNG_STATUS_OD_EE ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_OD_EE_POS)) /**< STATUS_OD_EE Mask */ - -#define MXC_F_TRNG_STATUS_PP_ERR_POS 8 /**< STATUS_PP_ERR Position */ -#define MXC_F_TRNG_STATUS_PP_ERR ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_PP_ERR_POS)) /**< STATUS_PP_ERR Mask */ - -#define MXC_F_TRNG_STATUS_ROMON_0_ERR_POS 9 /**< STATUS_ROMON_0_ERR Position */ -#define MXC_F_TRNG_STATUS_ROMON_0_ERR ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_ROMON_0_ERR_POS)) /**< STATUS_ROMON_0_ERR Mask */ - -#define MXC_F_TRNG_STATUS_ROMON_1_ERR_POS 10 /**< STATUS_ROMON_1_ERR Position */ -#define MXC_F_TRNG_STATUS_ROMON_1_ERR ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_ROMON_1_ERR_POS)) /**< STATUS_ROMON_1_ERR Mask */ - -#define MXC_F_TRNG_STATUS_ROMON_2_ERR_POS 11 /**< STATUS_ROMON_2_ERR Position */ -#define MXC_F_TRNG_STATUS_ROMON_2_ERR ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_ROMON_2_ERR_POS)) /**< STATUS_ROMON_2_ERR Mask */ +#define MXC_F_TRNG_STATUS_AESKGD_POS 4 /**< STATUS_AESKGD Position */ +#define MXC_F_TRNG_STATUS_AESKGD ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_AESKGD_POS)) /**< STATUS_AESKGD Mask */ -#define MXC_F_TRNG_STATUS_EE_ERR_THR_POS 12 /**< STATUS_EE_ERR_THR Position */ -#define MXC_F_TRNG_STATUS_EE_ERR_THR ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_EE_ERR_THR_POS)) /**< STATUS_EE_ERR_THR Mask */ - -#define MXC_F_TRNG_STATUS_EE_ERR_OOB_POS 13 /**< STATUS_EE_ERR_OOB Position */ -#define MXC_F_TRNG_STATUS_EE_ERR_OOB ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_EE_ERR_OOB_POS)) /**< STATUS_EE_ERR_OOB Mask */ - -#define MXC_F_TRNG_STATUS_EE_ERR_LOCK_POS 14 /**< STATUS_EE_ERR_LOCK Position */ -#define MXC_F_TRNG_STATUS_EE_ERR_LOCK ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_EE_ERR_LOCK_POS)) /**< STATUS_EE_ERR_LOCK Mask */ - -#define MXC_F_TRNG_STATUS_TERO_CNT_RDY_POS 16 /**< STATUS_TERO_CNT_RDY Position */ -#define MXC_F_TRNG_STATUS_TERO_CNT_RDY ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_TERO_CNT_RDY_POS)) /**< STATUS_TERO_CNT_RDY Mask */ - -#define MXC_F_TRNG_STATUS_RC_ERR_POS 17 /**< STATUS_RC_ERR Position */ -#define MXC_F_TRNG_STATUS_RC_ERR ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_RC_ERR_POS)) /**< STATUS_RC_ERR Mask */ - -#define MXC_F_TRNG_STATUS_AP_ERR_POS 18 /**< STATUS_AP_ERR Position */ -#define MXC_F_TRNG_STATUS_AP_ERR ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_AP_ERR_POS)) /**< STATUS_AP_ERR Mask */ - -#define MXC_F_TRNG_STATUS_DATA_DONE_POS 19 /**< STATUS_DATA_DONE Position */ -#define MXC_F_TRNG_STATUS_DATA_DONE ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_DATA_DONE_POS)) /**< STATUS_DATA_DONE Mask */ - -#define MXC_F_TRNG_STATUS_DATA_NIST_DONE_POS 20 /**< STATUS_DATA_NIST_DONE Position */ -#define MXC_F_TRNG_STATUS_DATA_NIST_DONE ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_DATA_NIST_DONE_POS)) /**< STATUS_DATA_NIST_DONE Mask */ - -#define MXC_F_TRNG_STATUS_HEALTH_DONE_POS 21 /**< STATUS_HEALTH_DONE Position */ -#define MXC_F_TRNG_STATUS_HEALTH_DONE ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_HEALTH_DONE_POS)) /**< STATUS_HEALTH_DONE Mask */ - -#define MXC_F_TRNG_STATUS_ROMON_DONE_POS 22 /**< STATUS_ROMON_DONE Position */ -#define MXC_F_TRNG_STATUS_ROMON_DONE ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_ROMON_DONE_POS)) /**< STATUS_ROMON_DONE Mask */ - -#define MXC_F_TRNG_STATUS_EE_DONE_POS 23 /**< STATUS_EE_DONE Position */ -#define MXC_F_TRNG_STATUS_EE_DONE ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_EE_DONE_POS)) /**< STATUS_EE_DONE Mask */ +#define MXC_F_TRNG_STATUS_LD_CNT_POS 24 /**< STATUS_LD_CNT Position */ +#define MXC_F_TRNG_STATUS_LD_CNT ((uint32_t)(0xFFUL << MXC_F_TRNG_STATUS_LD_CNT_POS)) /**< STATUS_LD_CNT Mask */ /**@} end of group TRNG_STATUS_Register */ @@ -237,19 +160,8 @@ typedef struct { /**@} end of group TRNG_DATA_Register */ -/** - * @ingroup trng_registers - * @defgroup TRNG_DATA_NIST TRNG_DATA_NIST - * @brief Data NIST Register. - * @{ - */ -#define MXC_F_TRNG_DATA_NIST_DATA_POS 0 /**< DATA_NIST_DATA Position */ -#define MXC_F_TRNG_DATA_NIST_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_TRNG_DATA_NIST_DATA_POS)) /**< DATA_NIST_DATA Mask */ - -/**@} end of group TRNG_DATA_NIST_Register */ - #ifdef __cplusplus } #endif -#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_TRNG_REGS_H_ +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32672_INCLUDE_TRNG_REGS_H_ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32572/Include/uart_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32572/Include/uart_regs.h index 821ed0942d4..3ea33786811 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32572/Include/uart_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32572/Include/uart_regs.h @@ -25,8 +25,8 @@ * ******************************************************************************/ -#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_UART_REGS_H_ -#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_UART_REGS_H_ +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32672_INCLUDE_UART_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32672_INCLUDE_UART_REGS_H_ /* **** Includes **** */ #include @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile @@ -76,8 +80,8 @@ extern "C" { typedef struct { __IO uint32_t ctrl; /**< \b 0x0000: UART CTRL Register */ __I uint32_t status; /**< \b 0x0004: UART STATUS Register */ - __IO uint32_t inten; /**< \b 0x0008: UART INTEN Register */ - __IO uint32_t intfl; /**< \b 0x000C: UART INTFL Register */ + __IO uint32_t int_en; /**< \b 0x0008: UART INT_EN Register */ + __IO uint32_t int_fl; /**< \b 0x000C: UART INT_FL Register */ __IO uint32_t clkdiv; /**< \b 0x0010: UART CLKDIV Register */ __IO uint32_t osr; /**< \b 0x0014: UART OSR Register */ __IO uint32_t txpeek; /**< \b 0x0018: UART TXPEEK Register */ @@ -98,8 +102,8 @@ typedef struct { */ #define MXC_R_UART_CTRL ((uint32_t)0x00000000UL) /**< Offset from UART Base Address: 0x0000 */ #define MXC_R_UART_STATUS ((uint32_t)0x00000004UL) /**< Offset from UART Base Address: 0x0004 */ -#define MXC_R_UART_INTEN ((uint32_t)0x00000008UL) /**< Offset from UART Base Address: 0x0008 */ -#define MXC_R_UART_INTFL ((uint32_t)0x0000000CUL) /**< Offset from UART Base Address: 0x000C */ +#define MXC_R_UART_INT_EN ((uint32_t)0x00000008UL) /**< Offset from UART Base Address: 0x0008 */ +#define MXC_R_UART_INT_FL ((uint32_t)0x0000000CUL) /**< Offset from UART Base Address: 0x000C */ #define MXC_R_UART_CLKDIV ((uint32_t)0x00000010UL) /**< Offset from UART Base Address: 0x0010 */ #define MXC_R_UART_OSR ((uint32_t)0x00000014UL) /**< Offset from UART Base Address: 0x0014 */ #define MXC_R_UART_TXPEEK ((uint32_t)0x00000018UL) /**< Offset from UART Base Address: 0x0018 */ @@ -164,8 +168,8 @@ typedef struct { #define MXC_F_UART_CTRL_BCLKSRC ((uint32_t)(0x3UL << MXC_F_UART_CTRL_BCLKSRC_POS)) /**< CTRL_BCLKSRC Mask */ #define MXC_V_UART_CTRL_BCLKSRC_PERIPHERAL_CLOCK ((uint32_t)0x0UL) /**< CTRL_BCLKSRC_PERIPHERAL_CLOCK Value */ #define MXC_S_UART_CTRL_BCLKSRC_PERIPHERAL_CLOCK (MXC_V_UART_CTRL_BCLKSRC_PERIPHERAL_CLOCK << MXC_F_UART_CTRL_BCLKSRC_POS) /**< CTRL_BCLKSRC_PERIPHERAL_CLOCK Setting */ -#define MXC_V_UART_CTRL_BCLKSRC_EXTERNAL_CLOCK ((uint32_t)0x1UL) /**< CTRL_BCLKSRC_EXTERNAL_CLOCK Value */ -#define MXC_S_UART_CTRL_BCLKSRC_EXTERNAL_CLOCK (MXC_V_UART_CTRL_BCLKSRC_EXTERNAL_CLOCK << MXC_F_UART_CTRL_BCLKSRC_POS) /**< CTRL_BCLKSRC_EXTERNAL_CLOCK Setting */ +#define MXC_V_UART_CTRL_BCLKSRC_CLK1 ((uint32_t)0x1UL) /**< CTRL_BCLKSRC_CLK1 Value */ +#define MXC_S_UART_CTRL_BCLKSRC_CLK1 (MXC_V_UART_CTRL_BCLKSRC_CLK1 << MXC_F_UART_CTRL_BCLKSRC_POS) /**< CTRL_BCLKSRC_CLK1 Setting */ #define MXC_V_UART_CTRL_BCLKSRC_CLK2 ((uint32_t)0x2UL) /**< CTRL_BCLKSRC_CLK2 Value */ #define MXC_S_UART_CTRL_BCLKSRC_CLK2 (MXC_V_UART_CTRL_BCLKSRC_CLK2 << MXC_F_UART_CTRL_BCLKSRC_POS) /**< CTRL_BCLKSRC_CLK2 Setting */ #define MXC_V_UART_CTRL_BCLKSRC_CLK3 ((uint32_t)0x3UL) /**< CTRL_BCLKSRC_CLK3 Value */ @@ -222,61 +226,61 @@ typedef struct { /** * @ingroup uart_registers - * @defgroup UART_INTEN UART_INTEN + * @defgroup UART_INT_EN UART_INT_EN * @brief Interrupt Enable control register * @{ */ -#define MXC_F_UART_INTEN_RX_FERR_POS 0 /**< INTEN_RX_FERR Position */ -#define MXC_F_UART_INTEN_RX_FERR ((uint32_t)(0x1UL << MXC_F_UART_INTEN_RX_FERR_POS)) /**< INTEN_RX_FERR Mask */ +#define MXC_F_UART_INT_EN_RX_FERR_POS 0 /**< INT_EN_RX_FERR Position */ +#define MXC_F_UART_INT_EN_RX_FERR ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_FERR_POS)) /**< INT_EN_RX_FERR Mask */ -#define MXC_F_UART_INTEN_RX_PAR_POS 1 /**< INTEN_RX_PAR Position */ -#define MXC_F_UART_INTEN_RX_PAR ((uint32_t)(0x1UL << MXC_F_UART_INTEN_RX_PAR_POS)) /**< INTEN_RX_PAR Mask */ +#define MXC_F_UART_INT_EN_RX_PAR_POS 1 /**< INT_EN_RX_PAR Position */ +#define MXC_F_UART_INT_EN_RX_PAR ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_PAR_POS)) /**< INT_EN_RX_PAR Mask */ -#define MXC_F_UART_INTEN_CTS_EV_POS 2 /**< INTEN_CTS_EV Position */ -#define MXC_F_UART_INTEN_CTS_EV ((uint32_t)(0x1UL << MXC_F_UART_INTEN_CTS_EV_POS)) /**< INTEN_CTS_EV Mask */ +#define MXC_F_UART_INT_EN_CTS_EV_POS 2 /**< INT_EN_CTS_EV Position */ +#define MXC_F_UART_INT_EN_CTS_EV ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_CTS_EV_POS)) /**< INT_EN_CTS_EV Mask */ -#define MXC_F_UART_INTEN_RX_OV_POS 3 /**< INTEN_RX_OV Position */ -#define MXC_F_UART_INTEN_RX_OV ((uint32_t)(0x1UL << MXC_F_UART_INTEN_RX_OV_POS)) /**< INTEN_RX_OV Mask */ +#define MXC_F_UART_INT_EN_RX_OV_POS 3 /**< INT_EN_RX_OV Position */ +#define MXC_F_UART_INT_EN_RX_OV ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_OV_POS)) /**< INT_EN_RX_OV Mask */ -#define MXC_F_UART_INTEN_RX_THD_POS 4 /**< INTEN_RX_THD Position */ -#define MXC_F_UART_INTEN_RX_THD ((uint32_t)(0x1UL << MXC_F_UART_INTEN_RX_THD_POS)) /**< INTEN_RX_THD Mask */ +#define MXC_F_UART_INT_EN_RX_THD_POS 4 /**< INT_EN_RX_THD Position */ +#define MXC_F_UART_INT_EN_RX_THD ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_THD_POS)) /**< INT_EN_RX_THD Mask */ -#define MXC_F_UART_INTEN_TX_OB_POS 5 /**< INTEN_TX_OB Position */ -#define MXC_F_UART_INTEN_TX_OB ((uint32_t)(0x1UL << MXC_F_UART_INTEN_TX_OB_POS)) /**< INTEN_TX_OB Mask */ +#define MXC_F_UART_INT_EN_TX_OB_POS 5 /**< INT_EN_TX_OB Position */ +#define MXC_F_UART_INT_EN_TX_OB ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_TX_OB_POS)) /**< INT_EN_TX_OB Mask */ -#define MXC_F_UART_INTEN_TX_HE_POS 6 /**< INTEN_TX_HE Position */ -#define MXC_F_UART_INTEN_TX_HE ((uint32_t)(0x1UL << MXC_F_UART_INTEN_TX_HE_POS)) /**< INTEN_TX_HE Mask */ +#define MXC_F_UART_INT_EN_TX_HE_POS 6 /**< INT_EN_TX_HE Position */ +#define MXC_F_UART_INT_EN_TX_HE ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_TX_HE_POS)) /**< INT_EN_TX_HE Mask */ -/**@} end of group UART_INTEN_Register */ +/**@} end of group UART_INT_EN_Register */ /** * @ingroup uart_registers - * @defgroup UART_INTFL UART_INTFL + * @defgroup UART_INT_FL UART_INT_FL * @brief Interrupt status flags Control register * @{ */ -#define MXC_F_UART_INTFL_RX_FERR_POS 0 /**< INTFL_RX_FERR Position */ -#define MXC_F_UART_INTFL_RX_FERR ((uint32_t)(0x1UL << MXC_F_UART_INTFL_RX_FERR_POS)) /**< INTFL_RX_FERR Mask */ +#define MXC_F_UART_INT_FL_RX_FERR_POS 0 /**< INT_FL_RX_FERR Position */ +#define MXC_F_UART_INT_FL_RX_FERR ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_RX_FERR_POS)) /**< INT_FL_RX_FERR Mask */ -#define MXC_F_UART_INTFL_RX_PAR_POS 1 /**< INTFL_RX_PAR Position */ -#define MXC_F_UART_INTFL_RX_PAR ((uint32_t)(0x1UL << MXC_F_UART_INTFL_RX_PAR_POS)) /**< INTFL_RX_PAR Mask */ +#define MXC_F_UART_INT_FL_RX_PAR_POS 1 /**< INT_FL_RX_PAR Position */ +#define MXC_F_UART_INT_FL_RX_PAR ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_RX_PAR_POS)) /**< INT_FL_RX_PAR Mask */ -#define MXC_F_UART_INTFL_CTS_EV_POS 2 /**< INTFL_CTS_EV Position */ -#define MXC_F_UART_INTFL_CTS_EV ((uint32_t)(0x1UL << MXC_F_UART_INTFL_CTS_EV_POS)) /**< INTFL_CTS_EV Mask */ +#define MXC_F_UART_INT_FL_CTS_EV_POS 2 /**< INT_FL_CTS_EV Position */ +#define MXC_F_UART_INT_FL_CTS_EV ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_CTS_EV_POS)) /**< INT_FL_CTS_EV Mask */ -#define MXC_F_UART_INTFL_RX_OV_POS 3 /**< INTFL_RX_OV Position */ -#define MXC_F_UART_INTFL_RX_OV ((uint32_t)(0x1UL << MXC_F_UART_INTFL_RX_OV_POS)) /**< INTFL_RX_OV Mask */ +#define MXC_F_UART_INT_FL_RX_OV_POS 3 /**< INT_FL_RX_OV Position */ +#define MXC_F_UART_INT_FL_RX_OV ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_RX_OV_POS)) /**< INT_FL_RX_OV Mask */ -#define MXC_F_UART_INTFL_RX_THD_POS 4 /**< INTFL_RX_THD Position */ -#define MXC_F_UART_INTFL_RX_THD ((uint32_t)(0x1UL << MXC_F_UART_INTFL_RX_THD_POS)) /**< INTFL_RX_THD Mask */ +#define MXC_F_UART_INT_FL_RX_THD_POS 4 /**< INT_FL_RX_THD Position */ +#define MXC_F_UART_INT_FL_RX_THD ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_RX_THD_POS)) /**< INT_FL_RX_THD Mask */ -#define MXC_F_UART_INTFL_TX_OB_POS 5 /**< INTFL_TX_OB Position */ -#define MXC_F_UART_INTFL_TX_OB ((uint32_t)(0x1UL << MXC_F_UART_INTFL_TX_OB_POS)) /**< INTFL_TX_OB Mask */ +#define MXC_F_UART_INT_FL_TX_OB_POS 5 /**< INT_FL_TX_OB Position */ +#define MXC_F_UART_INT_FL_TX_OB ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_TX_OB_POS)) /**< INT_FL_TX_OB Mask */ -#define MXC_F_UART_INTFL_TX_HE_POS 6 /**< INTFL_TX_HE Position */ -#define MXC_F_UART_INTFL_TX_HE ((uint32_t)(0x1UL << MXC_F_UART_INTFL_TX_HE_POS)) /**< INTFL_TX_HE Mask */ +#define MXC_F_UART_INT_FL_TX_HE_POS 6 /**< INT_FL_TX_HE Position */ +#define MXC_F_UART_INT_FL_TX_HE ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_TX_HE_POS)) /**< INT_FL_TX_HE Mask */ -/**@} end of group UART_INTFL_Register */ +/**@} end of group UART_INT_FL_Register */ /** * @ingroup uart_registers @@ -397,4 +401,4 @@ typedef struct { } #endif -#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_UART_REGS_H_ +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32672_INCLUDE_UART_REGS_H_ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32572/Include/usbhs_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32572/Include/usbhs_regs.h index 71986f957c2..15d6cee296b 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32572/Include/usbhs_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32572/Include/usbhs_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32572/Include/usr_aeskeys_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32572/Include/usr_aeskeys_regs.h new file mode 100644 index 00000000000..03135f3188e --- /dev/null +++ b/Libraries/CMSIS/Device/Maxim/MAX32572/Include/usr_aeskeys_regs.h @@ -0,0 +1,105 @@ +/** + * @file usr_aeskeys_regs.h + * @brief Registers, Bit Masks and Bit Positions for the USR_AESKEYS Peripheral Module. + * @note This file is @generated. + * @ingroup usr_aeskeys_registers + */ + +/****************************************************************************** + * + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32672_INCLUDE_USR_AESKEYS_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32672_INCLUDE_USR_AESKEYS_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup usr_aeskeys + * @ingroup aes + * @defgroup usr_aeskeys_registers USR_AESKEYS_Registers + * @brief Registers, Bit Masks and Bit Positions for the USR_AESKEYS Peripheral Module. + * @details User AES Key Registers. + */ + +/** + * @ingroup usr_aeskeys_registers + * Structure type to access the USR_AESKEYS Registers. + */ +typedef struct { + __IO uint32_t sram_key; /**< \b 0x00: USR_AESKEYS SRAM_KEY Register */ + __R uint32_t rsv_0x4_0x1f[7]; + __IO uint32_t code_key; /**< \b 0x20: USR_AESKEYS CODE_KEY Register */ + __R uint32_t rsv_0x24_0x3f[7]; + __IO uint32_t data_key; /**< \b 0x40: USR_AESKEYS DATA_KEY Register */ +} mxc_usr_aeskeys_regs_t; + +/* Register offsets for module USR_AESKEYS */ +/** + * @ingroup usr_aeskeys_registers + * @defgroup USR_AESKEYS_Register_Offsets Register Offsets + * @brief USR_AESKEYS Peripheral Register Offsets from the USR_AESKEYS Base Peripheral Address. + * @{ + */ +#define MXC_R_USR_AESKEYS_SRAM_KEY ((uint32_t)0x00000000UL) /**< Offset from USR_AESKEYS Base Address: 0x0000 */ +#define MXC_R_USR_AESKEYS_CODE_KEY ((uint32_t)0x00000020UL) /**< Offset from USR_AESKEYS Base Address: 0x0020 */ +#define MXC_R_USR_AESKEYS_DATA_KEY ((uint32_t)0x00000040UL) /**< Offset from USR_AESKEYS Base Address: 0x0040 */ +/**@} end of group usr_aeskeys_registers */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32672_INCLUDE_USR_AESKEYS_REGS_H_ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32572/Include/wdt_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32572/Include/wdt_regs.h index 74c4ecbc473..0d7dc1f2ee9 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32572/Include/wdt_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32572/Include/wdt_regs.h @@ -25,8 +25,8 @@ * ******************************************************************************/ -#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_WDT_REGS_H_ -#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_WDT_REGS_H_ +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32672_INCLUDE_WDT_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32672_INCLUDE_WDT_REGS_H_ /* **** Includes **** */ #include @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile @@ -312,4 +316,4 @@ typedef struct { } #endif -#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_WDT_REGS_H_ +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32672_INCLUDE_WDT_REGS_H_ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32650/Include/adc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32650/Include/adc_regs.h index 517293d73dc..06c1d2a7cbb 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32650/Include/adc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32650/Include/adc_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32650/Include/aeskeys_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32650/Include/aeskeys_regs.h index f522ba544a5..9b558d8aa61 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32650/Include/aeskeys_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32650/Include/aeskeys_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32650/Include/bbfc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32650/Include/bbfc_regs.h index ab327407f8f..9fdea97f230 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32650/Include/bbfc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32650/Include/bbfc_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32650/Include/clcd_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32650/Include/clcd_regs.h index 636cb5c1e75..b7a3bc1eb9f 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32650/Include/clcd_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32650/Include/clcd_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32650/Include/dma_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32650/Include/dma_regs.h index ae90de2e518..6413fb9237c 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32650/Include/dma_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32650/Include/dma_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile @@ -88,7 +92,7 @@ typedef struct { __IO uint32_t cn; /**< \b 0x000: DMA CN Register */ __I uint32_t intr; /**< \b 0x004: DMA INTR Register */ __R uint32_t rsv_0x8_0xff[62]; - __IO mxc_dma_ch_regs_t ch[16]; /**< \b 0x100: DMA CH Register */ + __IO mxc_dma_ch_regs_t ch[16]; /**< \b 0x100: DMA CH Register */ } mxc_dma_regs_t; /* Register offsets for module DMA */ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32650/Include/emcc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32650/Include/emcc_regs.h index 120fe776f0c..3803fc3f415 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32650/Include/emcc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32650/Include/emcc_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32650/Include/flc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32650/Include/flc_regs.h index adb286f57ff..9cf6bdd44ed 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32650/Include/flc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32650/Include/flc_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32650/Include/gcr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32650/Include/gcr_regs.h index f6a72d1afb9..40ff58658a5 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32650/Include/gcr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32650/Include/gcr_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32650/Include/gpio_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32650/Include/gpio_regs.h index f6de54eb293..6c201399eb8 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32650/Include/gpio_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32650/Include/gpio_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32650/Include/hpb_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32650/Include/hpb_regs.h index 9d29b30abf4..799f4a48426 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32650/Include/hpb_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32650/Include/hpb_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32650/Include/i2c_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32650/Include/i2c_regs.h index a3deba45519..c15992a1984 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32650/Include/i2c_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32650/Include/i2c_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32650/Include/icc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32650/Include/icc_regs.h index 93ed5016da3..28f2c1568b7 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32650/Include/icc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32650/Include/icc_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32650/Include/nbbfc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32650/Include/nbbfc_regs.h index e6212b82712..db753697cd6 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32650/Include/nbbfc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32650/Include/nbbfc_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32650/Include/owm_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32650/Include/owm_regs.h index 6dc8b62c0da..17338898806 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32650/Include/owm_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32650/Include/owm_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32650/Include/pt_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32650/Include/pt_regs.h index a9832e98294..d8d75b17028 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32650/Include/pt_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32650/Include/pt_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32650/Include/ptg_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32650/Include/ptg_regs.h index cfc6e97196a..42bd9223da8 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32650/Include/ptg_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32650/Include/ptg_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32650/Include/pwrseq_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32650/Include/pwrseq_regs.h index 9340338e7a3..fdc5343c045 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32650/Include/pwrseq_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32650/Include/pwrseq_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32650/Include/rtc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32650/Include/rtc_regs.h index 3672ff1e0c7..9fcd2de875f 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32650/Include/rtc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32650/Include/rtc_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32650/Include/sdhc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32650/Include/sdhc_regs.h index d716bfff30c..56f0e425f45 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32650/Include/sdhc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32650/Include/sdhc_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32650/Include/sema_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32650/Include/sema_regs.h index 77460e80c48..e2d2e0522d9 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32650/Include/sema_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32650/Include/sema_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32650/Include/sir_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32650/Include/sir_regs.h index b9bcd37cbc5..78277ce0f91 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32650/Include/sir_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32650/Include/sir_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32650/Include/smon_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32650/Include/smon_regs.h index a9e1ea1e08f..8dba1fe2aa3 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32650/Include/smon_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32650/Include/smon_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32650/Include/spi_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32650/Include/spi_regs.h index 2135595a45e..7c49b30edc8 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32650/Include/spi_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32650/Include/spi_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32650/Include/spimss_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32650/Include/spimss_regs.h index 2b436a101ec..99b86841e6e 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32650/Include/spimss_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32650/Include/spimss_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32650/Include/spixf_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32650/Include/spixf_regs.h index 962dafab529..012ab6e266e 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32650/Include/spixf_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32650/Include/spixf_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32650/Include/spixfc_fifo_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32650/Include/spixfc_fifo_regs.h index 564b55bb966..1aa1bfee168 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32650/Include/spixfc_fifo_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32650/Include/spixfc_fifo_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32650/Include/spixfc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32650/Include/spixfc_regs.h index 855a27445d5..7a302be31a3 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32650/Include/spixfc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32650/Include/spixfc_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32650/Include/spixr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32650/Include/spixr_regs.h index 10b6d85975b..f213d67fa79 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32650/Include/spixr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32650/Include/spixr_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32650/Include/tmr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32650/Include/tmr_regs.h index f4a8874c732..6ca1ea6bffa 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32650/Include/tmr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32650/Include/tmr_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32650/Include/tpu_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32650/Include/tpu_regs.h index 275a73f2257..fe32e903df9 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32650/Include/tpu_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32650/Include/tpu_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32650/Include/trimsir_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32650/Include/trimsir_regs.h index cc245af9a1a..0db86136f73 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32650/Include/trimsir_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32650/Include/trimsir_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32650/Include/trng_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32650/Include/trng_regs.h index 01561f83423..fd2f5dade27 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32650/Include/trng_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32650/Include/trng_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32650/Include/uart_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32650/Include/uart_regs.h index c107b868ec1..1841cae8881 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32650/Include/uart_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32650/Include/uart_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32650/Include/usbhs_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32650/Include/usbhs_regs.h index d8cc44a40ee..f0f0dbb7169 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32650/Include/usbhs_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32650/Include/usbhs_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32650/Include/wdt_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32650/Include/wdt_regs.h index a19ac37a771..b5dc07ff450 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32650/Include/wdt_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32650/Include/wdt_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32655/Include/adc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32655/Include/adc_regs.h index 2746c764855..62a3b777543 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32655/Include/adc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32655/Include/adc_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32655/Include/aes_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32655/Include/aes_regs.h index 48b5df3fcea..d394f588bc1 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32655/Include/aes_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32655/Include/aes_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32655/Include/aeskeys_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32655/Include/aeskeys_regs.h index bfdfe969bf5..0caf1f5882d 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32655/Include/aeskeys_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32655/Include/aeskeys_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32655/Include/crc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32655/Include/crc_regs.h index 1e45ea4380a..7ceb4197b38 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32655/Include/crc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32655/Include/crc_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile @@ -77,8 +81,8 @@ typedef struct { __IO uint32_t ctrl; /**< \b 0x0000: CRC CTRL Register */ union { __IO uint32_t datain32; /**< \b 0x0004: CRC DATAIN32 Register */ - __IO uint16_t datain16[2]; /**< \b 0x0004: CRC DATAIN16 Register */ - __IO uint8_t datain8[4]; /**< \b 0x0004: CRC DATAIN8 Register */ + __IO uint16_t datain16; /**< \b 0x0004: CRC DATAIN16 Register */ + __IO uint8_t datain8; /**< \b 0x0004: CRC DATAIN8 Register */ }; __IO uint32_t poly; /**< \b 0x0008: CRC POLY Register */ __IO uint32_t val; /**< \b 0x000C: CRC VAL Register */ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32655/Include/dma_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32655/Include/dma_regs.h index f70b125069f..3082ce1c6e8 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32655/Include/dma_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32655/Include/dma_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile @@ -88,7 +92,7 @@ typedef struct { __IO uint32_t inten; /**< \b 0x000: DMA INTEN Register */ __I uint32_t intfl; /**< \b 0x004: DMA INTFL Register */ __R uint32_t rsv_0x8_0xff[62]; - __IO mxc_dma_ch_regs_t ch[4]; /**< \b 0x100: DMA CH Register */ + __IO mxc_dma_ch_regs_t ch[4]; /**< \b 0x100: DMA CH Register */ } mxc_dma_regs_t; /* Register offsets for module DMA */ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32655/Include/dvs_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32655/Include/dvs_regs.h index 479d7641192..e30cac3cad0 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32655/Include/dvs_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32655/Include/dvs_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32655/Include/fcr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32655/Include/fcr_regs.h index c290aaaf6c8..a3e5a7bb991 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32655/Include/fcr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32655/Include/fcr_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32655/Include/flc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32655/Include/flc_regs.h index 19312d65118..e7fd73342f4 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32655/Include/flc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32655/Include/flc_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32655/Include/gcfr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32655/Include/gcfr_regs.h index 761c36f6c69..605308df651 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32655/Include/gcfr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32655/Include/gcfr_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32655/Include/gcr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32655/Include/gcr_regs.h index 38e9f2e2748..0a934d051b9 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32655/Include/gcr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32655/Include/gcr_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32655/Include/gpio_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32655/Include/gpio_regs.h index 4b361f644e3..8898846b7c5 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32655/Include/gpio_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32655/Include/gpio_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32655/Include/i2c_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32655/Include/i2c_regs.h index d6c38fe82c9..3cb1253150d 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32655/Include/i2c_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32655/Include/i2c_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32655/Include/i2s_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32655/Include/i2s_regs.h index 198013f6d9e..6e4a46c5755 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32655/Include/i2s_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32655/Include/i2s_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32655/Include/icc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32655/Include/icc_regs.h index 63225d0cee8..54608be8b55 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32655/Include/icc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32655/Include/icc_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32655/Include/lpcmp_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32655/Include/lpcmp_regs.h index bf2ef78c5f1..d2e0329519f 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32655/Include/lpcmp_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32655/Include/lpcmp_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile @@ -99,14 +103,14 @@ typedef struct { #define MXC_F_LPCMP_CTRL_POL_POS 5 /**< CTRL_POL Position */ #define MXC_F_LPCMP_CTRL_POL ((uint32_t)(0x1UL << MXC_F_LPCMP_CTRL_POL_POS)) /**< CTRL_POL Mask */ -#define MXC_F_LPCMP_CTRL_INT_EN_POS 6 /**< CTRL_INT_EN Position */ -#define MXC_F_LPCMP_CTRL_INT_EN ((uint32_t)(0x1UL << MXC_F_LPCMP_CTRL_INT_EN_POS)) /**< CTRL_INT_EN Mask */ +#define MXC_F_LPCMP_CTRL_INTEN_POS 6 /**< CTRL_INTEN Position */ +#define MXC_F_LPCMP_CTRL_INTEN ((uint32_t)(0x1UL << MXC_F_LPCMP_CTRL_INTEN_POS)) /**< CTRL_INTEN Mask */ #define MXC_F_LPCMP_CTRL_OUT_POS 14 /**< CTRL_OUT Position */ #define MXC_F_LPCMP_CTRL_OUT ((uint32_t)(0x1UL << MXC_F_LPCMP_CTRL_OUT_POS)) /**< CTRL_OUT Mask */ -#define MXC_F_LPCMP_CTRL_INT_FL_POS 15 /**< CTRL_INT_FL Position */ -#define MXC_F_LPCMP_CTRL_INT_FL ((uint32_t)(0x1UL << MXC_F_LPCMP_CTRL_INT_FL_POS)) /**< CTRL_INT_FL Mask */ +#define MXC_F_LPCMP_CTRL_INTFL_POS 15 /**< CTRL_INTFL Position */ +#define MXC_F_LPCMP_CTRL_INTFL ((uint32_t)(0x1UL << MXC_F_LPCMP_CTRL_INTFL_POS)) /**< CTRL_INTFL Mask */ /**@} end of group LPCMP_CTRL_Register */ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32655/Include/lpgcr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32655/Include/lpgcr_regs.h index 830ac020ffb..23fd2dc77af 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32655/Include/lpgcr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32655/Include/lpgcr_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32655/Include/max32655.svd b/Libraries/CMSIS/Device/Maxim/MAX32655/Include/max32655.svd index e371f1600cc..fe453eda1b2 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32655/Include/max32655.svd +++ b/Libraries/CMSIS/Device/Maxim/MAX32655/Include/max32655.svd @@ -700,9 +700,7 @@ - 2 - 2 - DATAIN16[%s] + DATAIN16 CRC Data Input 0x0004 16 @@ -718,9 +716,7 @@ - 4 - 1 - DATAIN8[%s] + DATAIN8 CRC Data Input 0x0004 8 @@ -6727,7 +6723,7 @@ 1 - INT_EN + INTEN IRQ Enable. 6 1 @@ -6739,7 +6735,7 @@ 1 - INT_FL + INTFL IRQ Flag 15 1 diff --git a/Libraries/CMSIS/Device/Maxim/MAX32655/Include/mcr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32655/Include/mcr_regs.h index 0f753b1fc60..1f82a75977e 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32655/Include/mcr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32655/Include/mcr_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32655/Include/owm_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32655/Include/owm_regs.h index 794022ca573..cc76b9aff1b 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32655/Include/owm_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32655/Include/owm_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32655/Include/pt_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32655/Include/pt_regs.h index 52c223902e9..e9feab0f603 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32655/Include/pt_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32655/Include/pt_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32655/Include/ptg_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32655/Include/ptg_regs.h index b8224ba89b3..e471052e3af 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32655/Include/ptg_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32655/Include/ptg_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32655/Include/pwrseq_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32655/Include/pwrseq_regs.h index af468afcf52..c28ad030c09 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32655/Include/pwrseq_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32655/Include/pwrseq_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32655/Include/rtc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32655/Include/rtc_regs.h index 8d15dabbff9..5ddd76ceac3 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32655/Include/rtc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32655/Include/rtc_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32655/Include/sema_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32655/Include/sema_regs.h index e28a0d96a36..f52f1630d26 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32655/Include/sema_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32655/Include/sema_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32655/Include/simo_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32655/Include/simo_regs.h index bf5af562c21..6da5d06f1da 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32655/Include/simo_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32655/Include/simo_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32655/Include/sir_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32655/Include/sir_regs.h index 42173bc2a56..f9c15c29964 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32655/Include/sir_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32655/Include/sir_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32655/Include/spi_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32655/Include/spi_regs.h index 4c56b8d9423..d8e33b0299e 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32655/Include/spi_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32655/Include/spi_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32655/Include/tmr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32655/Include/tmr_regs.h index 2879c76d103..55a40a62d91 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32655/Include/tmr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32655/Include/tmr_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32655/Include/trimsir_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32655/Include/trimsir_regs.h index 5fb5d64cdeb..2b13d2c88e2 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32655/Include/trimsir_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32655/Include/trimsir_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32655/Include/trng_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32655/Include/trng_regs.h index 3f537729e72..45451014450 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32655/Include/trng_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32655/Include/trng_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32655/Include/uart_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32655/Include/uart_regs.h index 1517297035c..89b65f06217 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32655/Include/uart_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32655/Include/uart_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32655/Include/wdt_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32655/Include/wdt_regs.h index 7b461e29e3e..9bdbbb3edc3 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32655/Include/wdt_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32655/Include/wdt_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32655/Include/wut_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32655/Include/wut_regs.h index 1a8f39644c9..a756b3d5130 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32655/Include/wut_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32655/Include/wut_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32660/Include/dma_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32660/Include/dma_regs.h index 1bb24b5d210..9dd977e9562 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32660/Include/dma_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32660/Include/dma_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile @@ -88,7 +92,7 @@ typedef struct { __IO uint32_t int_en; /**< \b 0x000: DMA INT_EN Register */ __I uint32_t int_fl; /**< \b 0x004: DMA INT_FL Register */ __R uint32_t rsv_0x8_0xff[62]; - __IO mxc_dma_ch_regs_t ch[4]; /**< \b 0x100: DMA CH Register */ + __IO mxc_dma_ch_regs_t ch[4]; /**< \b 0x100: DMA CH Register */ } mxc_dma_regs_t; /* Register offsets for module DMA */ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32660/Include/fcr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32660/Include/fcr_regs.h index 85c06f99f0c..ee376617b84 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32660/Include/fcr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32660/Include/fcr_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32660/Include/flc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32660/Include/flc_regs.h index c1b04c2f0ae..6c45e05c24f 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32660/Include/flc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32660/Include/flc_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32660/Include/gcr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32660/Include/gcr_regs.h index 244be25f433..8cc96ba356b 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32660/Include/gcr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32660/Include/gcr_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32660/Include/gpio_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32660/Include/gpio_regs.h index 582babc7f9f..539764dbd30 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32660/Include/gpio_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32660/Include/gpio_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32660/Include/i2c_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32660/Include/i2c_regs.h index 72e5a30d3e9..d129225a6a1 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32660/Include/i2c_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32660/Include/i2c_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32660/Include/icc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32660/Include/icc_regs.h index eae43325b60..601378bfbfa 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32660/Include/icc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32660/Include/icc_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32660/Include/pwrseq_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32660/Include/pwrseq_regs.h index b542e462290..064f2324a2b 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32660/Include/pwrseq_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32660/Include/pwrseq_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32660/Include/rtc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32660/Include/rtc_regs.h index 6448352a81d..bf58f0233c1 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32660/Include/rtc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32660/Include/rtc_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32660/Include/sir_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32660/Include/sir_regs.h index 30515ea0b8c..0ad8d85939f 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32660/Include/sir_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32660/Include/sir_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32660/Include/spi_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32660/Include/spi_regs.h index a275abfa02e..6ee5c32642a 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32660/Include/spi_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32660/Include/spi_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32660/Include/spimss_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32660/Include/spimss_regs.h index afe68140db7..cb58c4320a6 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32660/Include/spimss_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32660/Include/spimss_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32660/Include/tmr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32660/Include/tmr_regs.h index 0541a4d15c5..71409a3c457 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32660/Include/tmr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32660/Include/tmr_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32660/Include/uart_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32660/Include/uart_regs.h index e11a0a7ca7d..d4e20c5e766 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32660/Include/uart_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32660/Include/uart_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32660/Include/wdt_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32660/Include/wdt_regs.h index 3085b0c497c..b74f2db4c5b 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32660/Include/wdt_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32660/Include/wdt_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32662/Include/adc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32662/Include/adc_regs.h index c10502a4631..39445a29897 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32662/Include/adc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32662/Include/adc_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32662/Include/aes_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32662/Include/aes_regs.h index dc8f2bdbb86..f577e10671d 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32662/Include/aes_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32662/Include/aes_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32662/Include/aeskeys_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32662/Include/aeskeys_regs.h index a28513e6630..ef68f0a98df 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32662/Include/aeskeys_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32662/Include/aeskeys_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32662/Include/can_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32662/Include/can_regs.h index 6218ee6ad87..c5268bf0bf8 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32662/Include/can_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32662/Include/can_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32662/Include/dma_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32662/Include/dma_regs.h index bdf6d3dd648..aea8c68e741 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32662/Include/dma_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32662/Include/dma_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile @@ -88,7 +92,7 @@ typedef struct { __IO uint32_t inten; /**< \b 0x000: DMA INTEN Register */ __I uint32_t intfl; /**< \b 0x004: DMA INTFL Register */ __R uint32_t rsv_0x8_0xff[62]; - __IO mxc_dma_ch_regs_t ch[4]; /**< \b 0x100: DMA CH Register */ + __IO mxc_dma_ch_regs_t ch[4]; /**< \b 0x100: DMA CH Register */ } mxc_dma_regs_t; /* Register offsets for module DMA */ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32662/Include/fcr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32662/Include/fcr_regs.h index 507e2574329..e24148c8e16 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32662/Include/fcr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32662/Include/fcr_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32662/Include/flc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32662/Include/flc_regs.h index fabdd0b1de7..afd3c07a783 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32662/Include/flc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32662/Include/flc_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32662/Include/gcr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32662/Include/gcr_regs.h index 3d79e50119b..2519e08a538 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32662/Include/gcr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32662/Include/gcr_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32662/Include/gpio_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32662/Include/gpio_regs.h index 89c4bfad577..67f189cc5a8 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32662/Include/gpio_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32662/Include/gpio_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32662/Include/i2c_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32662/Include/i2c_regs.h index 10f02480225..7f1bd7e8122 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32662/Include/i2c_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32662/Include/i2c_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32662/Include/i2s_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32662/Include/i2s_regs.h index f84f34a52b1..43e084280f2 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32662/Include/i2s_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32662/Include/i2s_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32662/Include/icc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32662/Include/icc_regs.h index 63a57c87547..4b628559c8a 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32662/Include/icc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32662/Include/icc_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32662/Include/mcr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32662/Include/mcr_regs.h index a8a5bec6908..65a324d3c74 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32662/Include/mcr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32662/Include/mcr_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32662/Include/pt_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32662/Include/pt_regs.h index 1b79928a3fb..d52c84d55f3 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32662/Include/pt_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32662/Include/pt_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32662/Include/ptg_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32662/Include/ptg_regs.h index e27aa458038..b68e36e355f 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32662/Include/ptg_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32662/Include/ptg_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32662/Include/pwrseq_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32662/Include/pwrseq_regs.h index 3b0fcd3d1f7..14d19c63549 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32662/Include/pwrseq_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32662/Include/pwrseq_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32662/Include/rtc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32662/Include/rtc_regs.h index bfeebbc2105..743c7e63240 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32662/Include/rtc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32662/Include/rtc_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32662/Include/sir_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32662/Include/sir_regs.h index bbb3593fe41..75eb032255f 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32662/Include/sir_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32662/Include/sir_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32662/Include/spi_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32662/Include/spi_regs.h index 2ab7c8814b4..4c872297d34 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32662/Include/spi_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32662/Include/spi_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32662/Include/tmr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32662/Include/tmr_regs.h index 2a53d4255f6..04fb2ffe546 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32662/Include/tmr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32662/Include/tmr_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32662/Include/trimsir_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32662/Include/trimsir_regs.h index cb6de33b397..a4ad2301d5a 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32662/Include/trimsir_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32662/Include/trimsir_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32662/Include/trng_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32662/Include/trng_regs.h index 6ded4bba7ac..3b2c030cd2a 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32662/Include/trng_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32662/Include/trng_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32662/Include/uart_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32662/Include/uart_regs.h index 88a5e70c34e..4403e90592a 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32662/Include/uart_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32662/Include/uart_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32662/Include/wdt_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32662/Include/wdt_regs.h index 73e7ca01dfb..73ad52e344f 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32662/Include/wdt_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32662/Include/wdt_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32670/Include/aes_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32670/Include/aes_regs.h index cc88a0c9a93..ab558f5964f 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32670/Include/aes_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32670/Include/aes_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32670/Include/aeskeys_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32670/Include/aeskeys_regs.h index 26c10d79f55..3fb854994d5 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32670/Include/aeskeys_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32670/Include/aeskeys_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32670/Include/crc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32670/Include/crc_regs.h index 40385f46151..e94e78711ee 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32670/Include/crc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32670/Include/crc_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile @@ -77,8 +81,8 @@ typedef struct { __IO uint32_t ctrl; /**< \b 0x0000: CRC CTRL Register */ union { __IO uint32_t datain32; /**< \b 0x0004: CRC DATAIN32 Register */ - __IO uint16_t datain16[2]; /**< \b 0x0004: CRC DATAIN16 Register */ - __IO uint8_t datain8[4]; /**< \b 0x0004: CRC DATAIN8 Register */ + __IO uint16_t datain16; /**< \b 0x0004: CRC DATAIN16 Register */ + __IO uint8_t datain8; /**< \b 0x0004: CRC DATAIN8 Register */ }; __IO uint32_t poly; /**< \b 0x0008: CRC POLY Register */ __IO uint32_t val; /**< \b 0x000C: CRC VAL Register */ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32670/Include/dma_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32670/Include/dma_regs.h index 419decde33a..463fd2a72fe 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32670/Include/dma_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32670/Include/dma_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile @@ -88,7 +92,7 @@ typedef struct { __IO uint32_t inten; /**< \b 0x000: DMA INTEN Register */ __I uint32_t intfl; /**< \b 0x004: DMA INTFL Register */ __R uint32_t rsv_0x8_0xff[62]; - __IO mxc_dma_ch_regs_t ch[8]; /**< \b 0x100: DMA CH Register */ + __IO mxc_dma_ch_regs_t ch[8]; /**< \b 0x100: DMA CH Register */ } mxc_dma_regs_t; /* Register offsets for module DMA */ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32670/Include/ecc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32670/Include/ecc_regs.h index c0f857a2e10..54d59f9d29a 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32670/Include/ecc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32670/Include/ecc_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32670/Include/fcr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32670/Include/fcr_regs.h index 0df9482cf3c..ecb69d28f02 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32670/Include/fcr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32670/Include/fcr_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32670/Include/flc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32670/Include/flc_regs.h index bf8a3dfe11d..c9fb778ac89 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32670/Include/flc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32670/Include/flc_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32670/Include/gcr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32670/Include/gcr_regs.h index 081f786eefd..71942c71f33 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32670/Include/gcr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32670/Include/gcr_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32670/Include/gpio_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32670/Include/gpio_regs.h index 5a5210afa50..5895844ba42 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32670/Include/gpio_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32670/Include/gpio_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32670/Include/i2c_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32670/Include/i2c_regs.h index a860595dda6..7a33927499a 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32670/Include/i2c_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32670/Include/i2c_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32670/Include/i2s_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32670/Include/i2s_regs.h index 945f56ed6a2..387cda300a7 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32670/Include/i2s_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32670/Include/i2s_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32670/Include/icc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32670/Include/icc_regs.h index 08ebb4d0929..58bbc3ff486 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32670/Include/icc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32670/Include/icc_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32670/Include/max32670.svd b/Libraries/CMSIS/Device/Maxim/MAX32670/Include/max32670.svd index 006d874bdc9..e9dc97607e2 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32670/Include/max32670.svd +++ b/Libraries/CMSIS/Device/Maxim/MAX32670/Include/max32670.svd @@ -361,9 +361,7 @@ - 2 - 2 - DATAIN16[%s] + DATAIN16 CRC Data Input 0x0004 16 @@ -379,9 +377,7 @@ - 4 - 1 - DATAIN8[%s] + DATAIN8 CRC Data Input 0x0004 8 diff --git a/Libraries/CMSIS/Device/Maxim/MAX32670/Include/mcr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32670/Include/mcr_regs.h index 14798c014e3..5178a7011c4 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32670/Include/mcr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32670/Include/mcr_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32670/Include/pwrseq_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32670/Include/pwrseq_regs.h index 1352c20585e..da7984e03bd 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32670/Include/pwrseq_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32670/Include/pwrseq_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32670/Include/rtc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32670/Include/rtc_regs.h index d2b479884bc..480d0fe86ca 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32670/Include/rtc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32670/Include/rtc_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32670/Include/sir_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32670/Include/sir_regs.h index 5266d8bc8c5..9765e4a46da 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32670/Include/sir_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32670/Include/sir_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32670/Include/spi_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32670/Include/spi_regs.h index 96850c49ef3..34984674345 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32670/Include/spi_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32670/Include/spi_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32670/Include/tmr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32670/Include/tmr_regs.h index f12fbd4aee6..7e88a04ed02 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32670/Include/tmr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32670/Include/tmr_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32670/Include/trng_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32670/Include/trng_regs.h index 29e5ac6c80b..d793dc2a32c 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32670/Include/trng_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32670/Include/trng_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32670/Include/uart_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32670/Include/uart_regs.h index 293204c9dd4..744ea80c157 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32670/Include/uart_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32670/Include/uart_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32670/Include/wdt_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32670/Include/wdt_regs.h index 3c4e78724a4..033b9a2364a 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32670/Include/wdt_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32670/Include/wdt_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32672/Include/adc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32672/Include/adc_regs.h index 06012c6fe92..ba7c0cfc0b4 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32672/Include/adc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32672/Include/adc_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32672/Include/aes_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32672/Include/aes_regs.h index 825969a3990..24d747ef58c 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32672/Include/aes_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32672/Include/aes_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32672/Include/ctb_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32672/Include/ctb_regs.h index 86c6261c7b2..7c3346c0ac3 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32672/Include/ctb_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32672/Include/ctb_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32672/Include/dma_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32672/Include/dma_regs.h index 10990d0d7d5..887a405f73e 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32672/Include/dma_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32672/Include/dma_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile @@ -88,7 +92,7 @@ typedef struct { __IO uint32_t inten; /**< \b 0x000: DMA INTEN Register */ __I uint32_t intfl; /**< \b 0x004: DMA INTFL Register */ __R uint32_t rsv_0x8_0xff[62]; - __IO mxc_dma_ch_regs_t ch[12]; /**< \b 0x100: DMA CH Register */ + __IO mxc_dma_ch_regs_t ch[12]; /**< \b 0x100: DMA CH Register */ } mxc_dma_regs_t; /* Register offsets for module DMA */ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32672/Include/fcr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32672/Include/fcr_regs.h index 734b7b8ea24..a724871e65a 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32672/Include/fcr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32672/Include/fcr_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32672/Include/flc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32672/Include/flc_regs.h index ca1fa06db96..b7f4d4bedb0 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32672/Include/flc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32672/Include/flc_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32672/Include/gcr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32672/Include/gcr_regs.h index c4fa747e3f5..3fb4495a4a5 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32672/Include/gcr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32672/Include/gcr_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32672/Include/gpio_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32672/Include/gpio_regs.h index 91364274b9c..8512980e956 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32672/Include/gpio_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32672/Include/gpio_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32672/Include/i2c_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32672/Include/i2c_regs.h index f45638671f3..86ca9ce0e58 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32672/Include/i2c_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32672/Include/i2c_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32672/Include/i2s_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32672/Include/i2s_regs.h index 1c5827fcdfd..7ee0408bd63 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32672/Include/i2s_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32672/Include/i2s_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32672/Include/icc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32672/Include/icc_regs.h index fcc1a68a3be..11394e51e7a 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32672/Include/icc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32672/Include/icc_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32672/Include/max32672.svd b/Libraries/CMSIS/Device/Maxim/MAX32672/Include/max32672.svd index e37f71f6e05..98e5cbfeace 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32672/Include/max32672.svd +++ b/Libraries/CMSIS/Device/Maxim/MAX32672/Include/max32672.svd @@ -12177,7 +12177,7 @@ 0 - External_Clock + CLK1 Clock 1 1 diff --git a/Libraries/CMSIS/Device/Maxim/MAX32672/Include/mcr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32672/Include/mcr_regs.h index d81eca0fbce..443fbd4d40a 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32672/Include/mcr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32672/Include/mcr_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32672/Include/pwrseq_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32672/Include/pwrseq_regs.h index 6a71edd3dca..63406b1dd78 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32672/Include/pwrseq_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32672/Include/pwrseq_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32672/Include/qdec_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32672/Include/qdec_regs.h index 4acfc136386..cf3a0e23021 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32672/Include/qdec_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32672/Include/qdec_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32672/Include/rtc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32672/Include/rtc_regs.h index d527fa22b5f..74a6aa80245 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32672/Include/rtc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32672/Include/rtc_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32672/Include/sir_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32672/Include/sir_regs.h index 9691c096809..8b1b3d57419 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32672/Include/sir_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32672/Include/sir_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32672/Include/spi_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32672/Include/spi_regs.h index db2446793b8..2b11e5223ca 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32672/Include/spi_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32672/Include/spi_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32672/Include/sys_aeskeys_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32672/Include/sys_aeskeys_regs.h index 06235a5847e..30a311515da 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32672/Include/sys_aeskeys_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32672/Include/sys_aeskeys_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32672/Include/tmr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32672/Include/tmr_regs.h index e51a801c978..5bb43b39acf 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32672/Include/tmr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32672/Include/tmr_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32672/Include/trimsir_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32672/Include/trimsir_regs.h index 68d1dedc5fa..8c9b5eb8fbc 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32672/Include/trimsir_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32672/Include/trimsir_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32672/Include/trng_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32672/Include/trng_regs.h index 6d6fa2fc541..506873f0a75 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32672/Include/trng_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32672/Include/trng_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32672/Include/uart_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32672/Include/uart_regs.h index 0a57351af67..3ea33786811 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32672/Include/uart_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32672/Include/uart_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile @@ -164,8 +168,8 @@ typedef struct { #define MXC_F_UART_CTRL_BCLKSRC ((uint32_t)(0x3UL << MXC_F_UART_CTRL_BCLKSRC_POS)) /**< CTRL_BCLKSRC Mask */ #define MXC_V_UART_CTRL_BCLKSRC_PERIPHERAL_CLOCK ((uint32_t)0x0UL) /**< CTRL_BCLKSRC_PERIPHERAL_CLOCK Value */ #define MXC_S_UART_CTRL_BCLKSRC_PERIPHERAL_CLOCK (MXC_V_UART_CTRL_BCLKSRC_PERIPHERAL_CLOCK << MXC_F_UART_CTRL_BCLKSRC_POS) /**< CTRL_BCLKSRC_PERIPHERAL_CLOCK Setting */ -#define MXC_V_UART_CTRL_BCLKSRC_EXTERNAL_CLOCK ((uint32_t)0x1UL) /**< CTRL_BCLKSRC_EXTERNAL_CLOCK Value */ -#define MXC_S_UART_CTRL_BCLKSRC_EXTERNAL_CLOCK (MXC_V_UART_CTRL_BCLKSRC_EXTERNAL_CLOCK << MXC_F_UART_CTRL_BCLKSRC_POS) /**< CTRL_BCLKSRC_EXTERNAL_CLOCK Setting */ +#define MXC_V_UART_CTRL_BCLKSRC_CLK1 ((uint32_t)0x1UL) /**< CTRL_BCLKSRC_CLK1 Value */ +#define MXC_S_UART_CTRL_BCLKSRC_CLK1 (MXC_V_UART_CTRL_BCLKSRC_CLK1 << MXC_F_UART_CTRL_BCLKSRC_POS) /**< CTRL_BCLKSRC_CLK1 Setting */ #define MXC_V_UART_CTRL_BCLKSRC_CLK2 ((uint32_t)0x2UL) /**< CTRL_BCLKSRC_CLK2 Value */ #define MXC_S_UART_CTRL_BCLKSRC_CLK2 (MXC_V_UART_CTRL_BCLKSRC_CLK2 << MXC_F_UART_CTRL_BCLKSRC_POS) /**< CTRL_BCLKSRC_CLK2 Setting */ #define MXC_V_UART_CTRL_BCLKSRC_CLK3 ((uint32_t)0x3UL) /**< CTRL_BCLKSRC_CLK3 Value */ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32672/Include/usr_aeskeys_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32672/Include/usr_aeskeys_regs.h index 338d9c2973b..03135f3188e 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32672/Include/usr_aeskeys_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32672/Include/usr_aeskeys_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32672/Include/wdt_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32672/Include/wdt_regs.h index 3c8646d158f..0d7dc1f2ee9 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32672/Include/wdt_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32672/Include/wdt_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32675/Include/aes_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32675/Include/aes_regs.h index 1d36333bdaf..e6777156bcf 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32675/Include/aes_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32675/Include/aes_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32675/Include/aeskeys_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32675/Include/aeskeys_regs.h index 777a2cb914b..37ff185083d 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32675/Include/aeskeys_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32675/Include/aeskeys_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32675/Include/afe_adc_one_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32675/Include/afe_adc_one_regs.h index 83955ac348e..67758c32e7f 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32675/Include/afe_adc_one_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32675/Include/afe_adc_one_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32675/Include/afe_adc_zero_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32675/Include/afe_adc_zero_regs.h index 81eaedf7b90..e48033ae227 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32675/Include/afe_adc_zero_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32675/Include/afe_adc_zero_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32675/Include/afe_dac_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32675/Include/afe_dac_regs.h index b31d4ae6f27..595126c3e83 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32675/Include/afe_dac_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32675/Include/afe_dac_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32675/Include/afe_hart_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32675/Include/afe_hart_regs.h index ea5b9c618d1..b1d5544eb57 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32675/Include/afe_hart_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32675/Include/afe_hart_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32675/Include/crc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32675/Include/crc_regs.h index 0ebb5ddb9d3..57838514c1b 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32675/Include/crc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32675/Include/crc_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32675/Include/dma_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32675/Include/dma_regs.h index 38a910b1f6a..c961dfed7ff 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32675/Include/dma_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32675/Include/dma_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32675/Include/ecc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32675/Include/ecc_regs.h index 5e33ce97596..a4ba90e0ccb 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32675/Include/ecc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32675/Include/ecc_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32675/Include/fcr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32675/Include/fcr_regs.h index 0f88767c27e..0ce55ff21c4 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32675/Include/fcr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32675/Include/fcr_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32675/Include/flc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32675/Include/flc_regs.h index 7bdfc2037af..82da4971bb2 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32675/Include/flc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32675/Include/flc_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32675/Include/gcr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32675/Include/gcr_regs.h index 253c5d86b9d..585767c6f08 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32675/Include/gcr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32675/Include/gcr_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32675/Include/gpio_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32675/Include/gpio_regs.h index 96a5a433e4c..dd2b4e43d38 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32675/Include/gpio_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32675/Include/gpio_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32675/Include/i2c_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32675/Include/i2c_regs.h index f2c9ee9c40b..7050520c151 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32675/Include/i2c_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32675/Include/i2c_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32675/Include/i2s_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32675/Include/i2s_regs.h index e502e617997..0787e97a02a 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32675/Include/i2s_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32675/Include/i2s_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32675/Include/icc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32675/Include/icc_regs.h index c951c4a54ed..564a841c1bc 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32675/Include/icc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32675/Include/icc_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32675/Include/mcr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32675/Include/mcr_regs.h index ef317aa995b..a499c67f240 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32675/Include/mcr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32675/Include/mcr_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32675/Include/pwrseq_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32675/Include/pwrseq_regs.h index ccd1b0b1206..a0579302151 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32675/Include/pwrseq_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32675/Include/pwrseq_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32675/Include/rtc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32675/Include/rtc_regs.h index d1bf6842e57..9189d2342ef 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32675/Include/rtc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32675/Include/rtc_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32675/Include/sir_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32675/Include/sir_regs.h index 38e4957ee84..7ab6a902b35 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32675/Include/sir_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32675/Include/sir_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32675/Include/spi_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32675/Include/spi_regs.h index 3e394c72c0d..2343296e9db 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32675/Include/spi_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32675/Include/spi_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32675/Include/tmr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32675/Include/tmr_regs.h index e9704c5db17..9fc3e78122f 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32675/Include/tmr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32675/Include/tmr_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32675/Include/trng_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32675/Include/trng_regs.h index 6dee8558337..4adc2a1f2c8 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32675/Include/trng_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32675/Include/trng_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32675/Include/uart_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32675/Include/uart_regs.h index c28b29df627..9bc01dd91ca 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32675/Include/uart_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32675/Include/uart_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32675/Include/wdt_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32675/Include/wdt_regs.h index 3bed3bcd42a..ebefadb713d 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32675/Include/wdt_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32675/Include/wdt_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32680/Include/adc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32680/Include/adc_regs.h index a817c52dbb7..c3c5537be3b 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32680/Include/adc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32680/Include/adc_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32680/Include/aes_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32680/Include/aes_regs.h index bb533a2fd89..5d4ecabfb26 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32680/Include/aes_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32680/Include/aes_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32680/Include/aeskeys_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32680/Include/aeskeys_regs.h index 85b73126ab3..ceff45c85f1 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32680/Include/aeskeys_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32680/Include/aeskeys_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32680/Include/afe_adc_one_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32680/Include/afe_adc_one_regs.h index 310cfe77b67..dd7de652c6e 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32680/Include/afe_adc_one_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32680/Include/afe_adc_one_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32680/Include/afe_adc_zero_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32680/Include/afe_adc_zero_regs.h index 949029fc267..539e23b11e0 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32680/Include/afe_adc_zero_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32680/Include/afe_adc_zero_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32680/Include/afe_dac_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32680/Include/afe_dac_regs.h index a9953a453fa..583f08cf3ea 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32680/Include/afe_dac_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32680/Include/afe_dac_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32680/Include/afe_hart_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32680/Include/afe_hart_regs.h index 7ac2675f937..836c800a991 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32680/Include/afe_hart_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32680/Include/afe_hart_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32680/Include/crc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32680/Include/crc_regs.h index adf5ca1c914..25c6820a720 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32680/Include/crc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32680/Include/crc_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32680/Include/dma_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32680/Include/dma_regs.h index f0f6b9b475f..8131b85045c 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32680/Include/dma_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32680/Include/dma_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32680/Include/dvs_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32680/Include/dvs_regs.h index 91ea6ef8e4e..0ca668fd0fc 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32680/Include/dvs_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32680/Include/dvs_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32680/Include/fcr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32680/Include/fcr_regs.h index 0df60946ee0..5594f8a1e7b 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32680/Include/fcr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32680/Include/fcr_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32680/Include/flc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32680/Include/flc_regs.h index 960dc7b5f86..dccaf4e6fa7 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32680/Include/flc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32680/Include/flc_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32680/Include/gcfr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32680/Include/gcfr_regs.h index 30e9ce7717d..d71655d24d2 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32680/Include/gcfr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32680/Include/gcfr_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32680/Include/gcr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32680/Include/gcr_regs.h index ff049258432..b342915faa1 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32680/Include/gcr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32680/Include/gcr_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32680/Include/gpio_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32680/Include/gpio_regs.h index 1f3604f5547..111608e9e0c 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32680/Include/gpio_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32680/Include/gpio_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32680/Include/i2c_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32680/Include/i2c_regs.h index 87c47a595a7..62194aee5e5 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32680/Include/i2c_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32680/Include/i2c_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32680/Include/i2s_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32680/Include/i2s_regs.h index 943d6d39920..55662dd96ab 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32680/Include/i2s_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32680/Include/i2s_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32680/Include/icc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32680/Include/icc_regs.h index 17a37c41c2a..132e58862a0 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32680/Include/icc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32680/Include/icc_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32680/Include/lpcmp_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32680/Include/lpcmp_regs.h index bb3e1696d03..f8e10721f43 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32680/Include/lpcmp_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32680/Include/lpcmp_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32680/Include/lpgcr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32680/Include/lpgcr_regs.h index 380b507a5db..118514b472f 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32680/Include/lpgcr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32680/Include/lpgcr_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32680/Include/mcr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32680/Include/mcr_regs.h index b9472190005..85eea183755 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32680/Include/mcr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32680/Include/mcr_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32680/Include/owm_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32680/Include/owm_regs.h index 3aa62b1e9c5..176c5ba69fb 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32680/Include/owm_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32680/Include/owm_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32680/Include/pt_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32680/Include/pt_regs.h index b99e56ceb78..936ada4affb 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32680/Include/pt_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32680/Include/pt_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32680/Include/ptg_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32680/Include/ptg_regs.h index 26078a7f4e2..cb8c2f8dde7 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32680/Include/ptg_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32680/Include/ptg_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32680/Include/pwrseq_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32680/Include/pwrseq_regs.h index fd253a20a43..c1d0c30da4f 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32680/Include/pwrseq_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32680/Include/pwrseq_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32680/Include/rtc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32680/Include/rtc_regs.h index 6279e98ae72..085457695d0 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32680/Include/rtc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32680/Include/rtc_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32680/Include/sema_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32680/Include/sema_regs.h index c11a4213f8a..471a6f0b175 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32680/Include/sema_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32680/Include/sema_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32680/Include/simo_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32680/Include/simo_regs.h index b8f06b0be59..c7cc4c0a76d 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32680/Include/simo_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32680/Include/simo_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32680/Include/sir_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32680/Include/sir_regs.h index 4f8c04c21dc..68e051d504a 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32680/Include/sir_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32680/Include/sir_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32680/Include/spi_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32680/Include/spi_regs.h index 91247840486..fedb58174d6 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32680/Include/spi_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32680/Include/spi_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32680/Include/tmr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32680/Include/tmr_regs.h index e4a6c3e0479..045d69e6d47 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32680/Include/tmr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32680/Include/tmr_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32680/Include/trimsir_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32680/Include/trimsir_regs.h index 4b7f0c56bda..8cdf00c534b 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32680/Include/trimsir_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32680/Include/trimsir_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32680/Include/trng_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32680/Include/trng_regs.h index 040abdec55e..828cf4c8842 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32680/Include/trng_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32680/Include/trng_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32680/Include/uart_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32680/Include/uart_regs.h index a7b6a6dfe55..7d2cfd0e515 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32680/Include/uart_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32680/Include/uart_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32680/Include/wdt_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32680/Include/wdt_regs.h index 6ae7e523c88..b47a5f23599 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32680/Include/wdt_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32680/Include/wdt_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32680/Include/wut_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32680/Include/wut_regs.h index 05cfec40e84..6f0caa229f8 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32680/Include/wut_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32680/Include/wut_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32690/Include/adc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32690/Include/adc_regs.h index dcdded49aca..b2724c79edb 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32690/Include/adc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32690/Include/adc_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32690/Include/aeskeys_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32690/Include/aeskeys_regs.h index 010df6d62df..f942991d29e 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32690/Include/aeskeys_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32690/Include/aeskeys_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32690/Include/can_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32690/Include/can_regs.h index e3fd81ba010..08ddb0c1651 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32690/Include/can_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32690/Include/can_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32690/Include/ctb_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32690/Include/ctb_regs.h index cfa2bcd0255..d35c9f669be 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32690/Include/ctb_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32690/Include/ctb_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32690/Include/dma_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32690/Include/dma_regs.h index 26296faf768..d84fc655603 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32690/Include/dma_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32690/Include/dma_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile @@ -88,7 +92,7 @@ typedef struct { __IO uint32_t inten; /**< \b 0x000: DMA INTEN Register */ __I uint32_t intfl; /**< \b 0x004: DMA INTFL Register */ __R uint32_t rsv_0x8_0xff[62]; - __IO mxc_dma_ch_regs_t ch[16]; /**< \b 0x100: DMA CH Register */ + __IO mxc_dma_ch_regs_t ch[16]; /**< \b 0x100: DMA CH Register */ } mxc_dma_regs_t; /* Register offsets for module DMA */ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32690/Include/emcc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32690/Include/emcc_regs.h index 2e880607122..ffc65ebe458 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32690/Include/emcc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32690/Include/emcc_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32690/Include/fcr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32690/Include/fcr_regs.h index b512d0a05d0..d7ba0386712 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32690/Include/fcr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32690/Include/fcr_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32690/Include/flc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32690/Include/flc_regs.h index 39e79f561ff..b3d0a9f2528 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32690/Include/flc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32690/Include/flc_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32690/Include/gcfr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32690/Include/gcfr_regs.h index d710ac3a3e5..9a9e7670852 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32690/Include/gcfr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32690/Include/gcfr_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32690/Include/gcr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32690/Include/gcr_regs.h index 1ab61adfec3..1b7e9f84794 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32690/Include/gcr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32690/Include/gcr_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32690/Include/gpio_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32690/Include/gpio_regs.h index 0c49b4d6b57..f695d452cde 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32690/Include/gpio_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32690/Include/gpio_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32690/Include/hpb_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32690/Include/hpb_regs.h index 9a322a2fb87..8673b0d690d 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32690/Include/hpb_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32690/Include/hpb_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32690/Include/i2c_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32690/Include/i2c_regs.h index 160c66ea15d..77f437cf7d8 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32690/Include/i2c_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32690/Include/i2c_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32690/Include/i2s_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32690/Include/i2s_regs.h index 6175fa7c288..a587cd0ff03 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32690/Include/i2s_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32690/Include/i2s_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32690/Include/icc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32690/Include/icc_regs.h index c0cdf9b292e..8e971739906 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32690/Include/icc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32690/Include/icc_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32690/Include/lpcmp_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32690/Include/lpcmp_regs.h index 1a5ffc7fc1e..0ff0aad60a0 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32690/Include/lpcmp_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32690/Include/lpcmp_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile @@ -99,14 +103,14 @@ typedef struct { #define MXC_F_LPCMP_CTRL_POL_POS 5 /**< CTRL_POL Position */ #define MXC_F_LPCMP_CTRL_POL ((uint32_t)(0x1UL << MXC_F_LPCMP_CTRL_POL_POS)) /**< CTRL_POL Mask */ -#define MXC_F_LPCMP_CTRL_INT_EN_POS 6 /**< CTRL_INT_EN Position */ -#define MXC_F_LPCMP_CTRL_INT_EN ((uint32_t)(0x1UL << MXC_F_LPCMP_CTRL_INT_EN_POS)) /**< CTRL_INT_EN Mask */ +#define MXC_F_LPCMP_CTRL_INTEN_POS 6 /**< CTRL_INTEN Position */ +#define MXC_F_LPCMP_CTRL_INTEN ((uint32_t)(0x1UL << MXC_F_LPCMP_CTRL_INTEN_POS)) /**< CTRL_INTEN Mask */ #define MXC_F_LPCMP_CTRL_OUT_POS 14 /**< CTRL_OUT Position */ #define MXC_F_LPCMP_CTRL_OUT ((uint32_t)(0x1UL << MXC_F_LPCMP_CTRL_OUT_POS)) /**< CTRL_OUT Mask */ -#define MXC_F_LPCMP_CTRL_INT_FL_POS 15 /**< CTRL_INT_FL Position */ -#define MXC_F_LPCMP_CTRL_INT_FL ((uint32_t)(0x1UL << MXC_F_LPCMP_CTRL_INT_FL_POS)) /**< CTRL_INT_FL Mask */ +#define MXC_F_LPCMP_CTRL_INTFL_POS 15 /**< CTRL_INTFL Position */ +#define MXC_F_LPCMP_CTRL_INTFL ((uint32_t)(0x1UL << MXC_F_LPCMP_CTRL_INTFL_POS)) /**< CTRL_INTFL Mask */ /**@} end of group LPCMP_CTRL_Register */ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32690/Include/lpgcr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32690/Include/lpgcr_regs.h index 92b69f6d807..b26e5bf697f 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32690/Include/lpgcr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32690/Include/lpgcr_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32690/Include/max32690.svd b/Libraries/CMSIS/Device/Maxim/MAX32690/Include/max32690.svd index 56af430f311..5a67f4cede8 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32690/Include/max32690.svd +++ b/Libraries/CMSIS/Device/Maxim/MAX32690/Include/max32690.svd @@ -10224,7 +10224,7 @@ memory. 1 - INT_EN + INTEN IRQ Enable. 6 1 @@ -10236,7 +10236,7 @@ memory. 1 - INT_FL + INTFL IRQ Flag 15 1 @@ -16304,7 +16304,7 @@ signal(s) on transition(s) from low to high or high to low when PM.USBWKEN is se SPI1 SPI peripheral. 1 - 0x400BE000 + 0x40047000 SPI1 SPI1 IRQ @@ -16315,7 +16315,7 @@ signal(s) on transition(s) from low to high or high to low when PM.USBWKEN is se SPI2 SPI peripheral. 2 - 0x400BE400 + 0x40048000 SPI2 SPI2 IRQ @@ -16323,6 +16323,28 @@ signal(s) on transition(s) from low to high or high to low when PM.USBWKEN is se + + SPI3 + SPI peripheral. 3 + 0x400BE000 + + SPI3 + SPI3 IRQ + 56 + + + + + SPI4 + SPI peripheral. 4 + 0x400BE400 + + SPI4 + SPI4 IRQ + 105 + + + SPIXR SPIXR peripheral. diff --git a/Libraries/CMSIS/Device/Maxim/MAX32690/Include/mcr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32690/Include/mcr_regs.h index 57f50820656..259d1d91bd1 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32690/Include/mcr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32690/Include/mcr_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32690/Include/owm_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32690/Include/owm_regs.h index e4951aa7808..d0843ea46c5 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32690/Include/owm_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32690/Include/owm_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32690/Include/pt_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32690/Include/pt_regs.h index b5eb0e69ce1..6e9d28c17ad 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32690/Include/pt_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32690/Include/pt_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32690/Include/ptg_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32690/Include/ptg_regs.h index d2eb524d14d..f21606414b9 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32690/Include/ptg_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32690/Include/ptg_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32690/Include/pwrseq_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32690/Include/pwrseq_regs.h index c2a038a1591..3977a4f9e47 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32690/Include/pwrseq_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32690/Include/pwrseq_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32690/Include/rtc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32690/Include/rtc_regs.h index 0f91b03ff95..88f044c6871 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32690/Include/rtc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32690/Include/rtc_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32690/Include/sema_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32690/Include/sema_regs.h index b40f8be1dd8..b4dff7d373c 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32690/Include/sema_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32690/Include/sema_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32690/Include/sir_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32690/Include/sir_regs.h index d1b5f527224..3fabacff594 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32690/Include/sir_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32690/Include/sir_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32690/Include/smon_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32690/Include/smon_regs.h index 611cfa137dc..19f65c6b8ea 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32690/Include/smon_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32690/Include/smon_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32690/Include/spi_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32690/Include/spi_regs.h index 3df96bfb9c3..9beddbb08ac 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32690/Include/spi_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32690/Include/spi_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32690/Include/spixfc_fifo_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32690/Include/spixfc_fifo_regs.h index 56039a5f63a..ff651a86685 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32690/Include/spixfc_fifo_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32690/Include/spixfc_fifo_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32690/Include/spixfc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32690/Include/spixfc_regs.h index 7c0ebdd4aab..0564fa8f552 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32690/Include/spixfc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32690/Include/spixfc_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32690/Include/spixfm_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32690/Include/spixfm_regs.h index 36ab39212e3..821373d2a4a 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32690/Include/spixfm_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32690/Include/spixfm_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32690/Include/spixr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32690/Include/spixr_regs.h index 841909cb166..dac2754f458 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32690/Include/spixr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32690/Include/spixr_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32690/Include/tmr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32690/Include/tmr_regs.h index f27708a87dd..3d01330a99b 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32690/Include/tmr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32690/Include/tmr_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32690/Include/trimsir_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32690/Include/trimsir_regs.h index 26a6d5111aa..5ee67dda077 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32690/Include/trimsir_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32690/Include/trimsir_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32690/Include/trng_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32690/Include/trng_regs.h index 9f1576bb569..733dabe3a6a 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32690/Include/trng_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32690/Include/trng_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32690/Include/uart_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32690/Include/uart_regs.h index 2f84a78d3ea..3fec0d695f3 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32690/Include/uart_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32690/Include/uart_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32690/Include/usbhs_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32690/Include/usbhs_regs.h index d33ededcce3..810b9d062a0 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32690/Include/usbhs_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32690/Include/usbhs_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32690/Include/wdt_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32690/Include/wdt_regs.h index 0c464a67638..ee478a87efa 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32690/Include/wdt_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32690/Include/wdt_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX32690/Include/wut_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32690/Include/wut_regs.h index ea1fd050522..fcaf9c2ba48 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32690/Include/wut_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32690/Include/wut_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX78000/Include/adc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX78000/Include/adc_regs.h index d7dbebfe356..63d2bb4f0bd 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX78000/Include/adc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX78000/Include/adc_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX78000/Include/aes_regs.h b/Libraries/CMSIS/Device/Maxim/MAX78000/Include/aes_regs.h index 092a7069b78..96fd6490c63 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX78000/Include/aes_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX78000/Include/aes_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX78000/Include/aeskeys_regs.h b/Libraries/CMSIS/Device/Maxim/MAX78000/Include/aeskeys_regs.h index 44b240065df..ad3015172ce 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX78000/Include/aeskeys_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX78000/Include/aeskeys_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX78000/Include/cameraif_regs.h b/Libraries/CMSIS/Device/Maxim/MAX78000/Include/cameraif_regs.h index fbce62602dc..922d64ce810 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX78000/Include/cameraif_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX78000/Include/cameraif_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX78000/Include/crc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX78000/Include/crc_regs.h index c285689074f..3cfee7a2679 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX78000/Include/crc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX78000/Include/crc_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile @@ -77,8 +81,8 @@ typedef struct { __IO uint32_t ctrl; /**< \b 0x0000: CRC CTRL Register */ union { __IO uint32_t datain32; /**< \b 0x0004: CRC DATAIN32 Register */ - __IO uint16_t datain16[2]; /**< \b 0x0004: CRC DATAIN16 Register */ - __IO uint8_t datain8[4]; /**< \b 0x0004: CRC DATAIN8 Register */ + __IO uint16_t datain16; /**< \b 0x0004: CRC DATAIN16 Register */ + __IO uint8_t datain8; /**< \b 0x0004: CRC DATAIN8 Register */ }; __IO uint32_t poly; /**< \b 0x0008: CRC POLY Register */ __IO uint32_t val; /**< \b 0x000C: CRC VAL Register */ diff --git a/Libraries/CMSIS/Device/Maxim/MAX78000/Include/dma_regs.h b/Libraries/CMSIS/Device/Maxim/MAX78000/Include/dma_regs.h index 304085e67e6..f0fe4847693 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX78000/Include/dma_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX78000/Include/dma_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile @@ -88,7 +92,7 @@ typedef struct { __IO uint32_t inten; /**< \b 0x000: DMA INTEN Register */ __I uint32_t intfl; /**< \b 0x004: DMA INTFL Register */ __R uint32_t rsv_0x8_0xff[62]; - __IO mxc_dma_ch_regs_t ch[4]; /**< \b 0x100: DMA CH Register */ + __IO mxc_dma_ch_regs_t ch[4]; /**< \b 0x100: DMA CH Register */ } mxc_dma_regs_t; /* Register offsets for module DMA */ diff --git a/Libraries/CMSIS/Device/Maxim/MAX78000/Include/dvs_regs.h b/Libraries/CMSIS/Device/Maxim/MAX78000/Include/dvs_regs.h index a2d722ee706..06ae466bb82 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX78000/Include/dvs_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX78000/Include/dvs_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX78000/Include/fcr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX78000/Include/fcr_regs.h index d952d53df54..c78764778da 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX78000/Include/fcr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX78000/Include/fcr_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX78000/Include/flc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX78000/Include/flc_regs.h index 53e180c10c5..fd254ef172a 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX78000/Include/flc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX78000/Include/flc_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX78000/Include/gcfr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX78000/Include/gcfr_regs.h index 6be3ebf86f4..7379f142ef0 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX78000/Include/gcfr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX78000/Include/gcfr_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX78000/Include/gcr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX78000/Include/gcr_regs.h index 1006d201df1..486e9efbfdb 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX78000/Include/gcr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX78000/Include/gcr_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX78000/Include/gpio_regs.h b/Libraries/CMSIS/Device/Maxim/MAX78000/Include/gpio_regs.h index 7b0038299bb..0331c449547 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX78000/Include/gpio_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX78000/Include/gpio_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX78000/Include/i2c_regs.h b/Libraries/CMSIS/Device/Maxim/MAX78000/Include/i2c_regs.h index f217a2a74b6..fab003f3241 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX78000/Include/i2c_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX78000/Include/i2c_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX78000/Include/i2s_regs.h b/Libraries/CMSIS/Device/Maxim/MAX78000/Include/i2s_regs.h index e5279e36253..a9b8995dc32 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX78000/Include/i2s_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX78000/Include/i2s_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX78000/Include/icc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX78000/Include/icc_regs.h index 7a93516e80f..5b521a55793 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX78000/Include/icc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX78000/Include/icc_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX78000/Include/lpcmp_regs.h b/Libraries/CMSIS/Device/Maxim/MAX78000/Include/lpcmp_regs.h index 555d8043451..c6f7ddc73ea 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX78000/Include/lpcmp_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX78000/Include/lpcmp_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile @@ -99,14 +103,14 @@ typedef struct { #define MXC_F_LPCMP_CTRL_POL_POS 5 /**< CTRL_POL Position */ #define MXC_F_LPCMP_CTRL_POL ((uint32_t)(0x1UL << MXC_F_LPCMP_CTRL_POL_POS)) /**< CTRL_POL Mask */ -#define MXC_F_LPCMP_CTRL_INT_EN_POS 6 /**< CTRL_INT_EN Position */ -#define MXC_F_LPCMP_CTRL_INT_EN ((uint32_t)(0x1UL << MXC_F_LPCMP_CTRL_INT_EN_POS)) /**< CTRL_INT_EN Mask */ +#define MXC_F_LPCMP_CTRL_INTEN_POS 6 /**< CTRL_INTEN Position */ +#define MXC_F_LPCMP_CTRL_INTEN ((uint32_t)(0x1UL << MXC_F_LPCMP_CTRL_INTEN_POS)) /**< CTRL_INTEN Mask */ #define MXC_F_LPCMP_CTRL_OUT_POS 14 /**< CTRL_OUT Position */ #define MXC_F_LPCMP_CTRL_OUT ((uint32_t)(0x1UL << MXC_F_LPCMP_CTRL_OUT_POS)) /**< CTRL_OUT Mask */ -#define MXC_F_LPCMP_CTRL_INT_FL_POS 15 /**< CTRL_INT_FL Position */ -#define MXC_F_LPCMP_CTRL_INT_FL ((uint32_t)(0x1UL << MXC_F_LPCMP_CTRL_INT_FL_POS)) /**< CTRL_INT_FL Mask */ +#define MXC_F_LPCMP_CTRL_INTFL_POS 15 /**< CTRL_INTFL Position */ +#define MXC_F_LPCMP_CTRL_INTFL ((uint32_t)(0x1UL << MXC_F_LPCMP_CTRL_INTFL_POS)) /**< CTRL_INTFL Mask */ /**@} end of group LPCMP_CTRL_Register */ diff --git a/Libraries/CMSIS/Device/Maxim/MAX78000/Include/lpgcr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX78000/Include/lpgcr_regs.h index ad215c4bf69..bd98322604f 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX78000/Include/lpgcr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX78000/Include/lpgcr_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX78000/Include/max78000.svd b/Libraries/CMSIS/Device/Maxim/MAX78000/Include/max78000.svd index b629eb55959..3ea4a1309c7 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX78000/Include/max78000.svd +++ b/Libraries/CMSIS/Device/Maxim/MAX78000/Include/max78000.svd @@ -993,9 +993,7 @@ - 2 - 2 - DATAIN16[%s] + DATAIN16 CRC Data Input 0x0004 16 @@ -1011,9 +1009,7 @@ - 4 - 1 - DATAIN8[%s] + DATAIN8 CRC Data Input 0x0004 8 @@ -6791,7 +6787,7 @@ 1 - INT_EN + INTEN IRQ Enable. 6 1 @@ -6803,7 +6799,7 @@ 1 - INT_FL + INTFL IRQ Flag 15 1 diff --git a/Libraries/CMSIS/Device/Maxim/MAX78000/Include/mcr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX78000/Include/mcr_regs.h index 8aa33b7a9f9..e27e1ea4e42 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX78000/Include/mcr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX78000/Include/mcr_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX78000/Include/owm_regs.h b/Libraries/CMSIS/Device/Maxim/MAX78000/Include/owm_regs.h index 145461e6289..85cad8bce0d 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX78000/Include/owm_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX78000/Include/owm_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX78000/Include/pt_regs.h b/Libraries/CMSIS/Device/Maxim/MAX78000/Include/pt_regs.h index 0a93f7962ae..346f3f06f96 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX78000/Include/pt_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX78000/Include/pt_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX78000/Include/ptg_regs.h b/Libraries/CMSIS/Device/Maxim/MAX78000/Include/ptg_regs.h index a03d5a507a5..c716c9fb46b 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX78000/Include/ptg_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX78000/Include/ptg_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX78000/Include/pwrseq_regs.h b/Libraries/CMSIS/Device/Maxim/MAX78000/Include/pwrseq_regs.h index 9713937480b..7c13756ab06 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX78000/Include/pwrseq_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX78000/Include/pwrseq_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX78000/Include/rtc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX78000/Include/rtc_regs.h index a9084c6a3f5..91d24017a9f 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX78000/Include/rtc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX78000/Include/rtc_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX78000/Include/sema_regs.h b/Libraries/CMSIS/Device/Maxim/MAX78000/Include/sema_regs.h index 32ee4fef2e9..8be31723e40 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX78000/Include/sema_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX78000/Include/sema_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX78000/Include/simo_regs.h b/Libraries/CMSIS/Device/Maxim/MAX78000/Include/simo_regs.h index 999743cfea9..e962a9067cf 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX78000/Include/simo_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX78000/Include/simo_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX78000/Include/sir_regs.h b/Libraries/CMSIS/Device/Maxim/MAX78000/Include/sir_regs.h index 144adfc88ce..9000aec8138 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX78000/Include/sir_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX78000/Include/sir_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX78000/Include/spi_regs.h b/Libraries/CMSIS/Device/Maxim/MAX78000/Include/spi_regs.h index 582fe393933..1cb64e218bc 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX78000/Include/spi_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX78000/Include/spi_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX78000/Include/tmr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX78000/Include/tmr_regs.h index 6957d7828af..33e8ce74a0e 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX78000/Include/tmr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX78000/Include/tmr_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX78000/Include/trimsir_regs.h b/Libraries/CMSIS/Device/Maxim/MAX78000/Include/trimsir_regs.h index 92420ede714..a1400b4463c 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX78000/Include/trimsir_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX78000/Include/trimsir_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX78000/Include/trng_regs.h b/Libraries/CMSIS/Device/Maxim/MAX78000/Include/trng_regs.h index 7c5610bee95..15e74455023 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX78000/Include/trng_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX78000/Include/trng_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX78000/Include/uart_regs.h b/Libraries/CMSIS/Device/Maxim/MAX78000/Include/uart_regs.h index 0d981c3e250..047366def38 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX78000/Include/uart_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX78000/Include/uart_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX78000/Include/wdt_regs.h b/Libraries/CMSIS/Device/Maxim/MAX78000/Include/wdt_regs.h index efc7615fcbe..c4ad995e90e 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX78000/Include/wdt_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX78000/Include/wdt_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX78000/Include/wut_regs.h b/Libraries/CMSIS/Device/Maxim/MAX78000/Include/wut_regs.h index 62d0c05f1e2..e4ccfa311aa 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX78000/Include/wut_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX78000/Include/wut_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX78002/Include/adc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX78002/Include/adc_regs.h index ac3ae7df72d..9818e33cf2f 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX78002/Include/adc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX78002/Include/adc_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX78002/Include/aes_regs.h b/Libraries/CMSIS/Device/Maxim/MAX78002/Include/aes_regs.h index e0f7f126b76..bb55af48060 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX78002/Include/aes_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX78002/Include/aes_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX78002/Include/aeskeys_regs.h b/Libraries/CMSIS/Device/Maxim/MAX78002/Include/aeskeys_regs.h index a5ad03f8bc2..2b015afcb4a 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX78002/Include/aeskeys_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX78002/Include/aeskeys_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX78002/Include/cameraif_regs.h b/Libraries/CMSIS/Device/Maxim/MAX78002/Include/cameraif_regs.h index e8bc9684a39..c968f523924 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX78002/Include/cameraif_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX78002/Include/cameraif_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX78002/Include/crc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX78002/Include/crc_regs.h index e4a713a82f9..708eb64c68e 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX78002/Include/crc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX78002/Include/crc_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile @@ -77,8 +81,8 @@ typedef struct { __IO uint32_t ctrl; /**< \b 0x0000: CRC CTRL Register */ union { __IO uint32_t datain32; /**< \b 0x0004: CRC DATAIN32 Register */ - __IO uint16_t datain16[2]; /**< \b 0x0004: CRC DATAIN16 Register */ - __IO uint8_t datain8[4]; /**< \b 0x0004: CRC DATAIN8 Register */ + __IO uint16_t datain16; /**< \b 0x0004: CRC DATAIN16 Register */ + __IO uint8_t datain8; /**< \b 0x0004: CRC DATAIN8 Register */ }; __IO uint32_t poly; /**< \b 0x0008: CRC POLY Register */ __IO uint32_t val; /**< \b 0x000C: CRC VAL Register */ diff --git a/Libraries/CMSIS/Device/Maxim/MAX78002/Include/csi2_regs.h b/Libraries/CMSIS/Device/Maxim/MAX78002/Include/csi2_regs.h index 8382fccf264..ef5c60e21e2 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX78002/Include/csi2_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX78002/Include/csi2_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX78002/Include/dma_regs.h b/Libraries/CMSIS/Device/Maxim/MAX78002/Include/dma_regs.h index 7930d87d93e..a520c3b6034 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX78002/Include/dma_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX78002/Include/dma_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile @@ -88,7 +92,7 @@ typedef struct { __IO uint32_t inten; /**< \b 0x000: DMA INTEN Register */ __I uint32_t intfl; /**< \b 0x004: DMA INTFL Register */ __R uint32_t rsv_0x8_0xff[62]; - __IO mxc_dma_ch_regs_t ch[8]; /**< \b 0x100: DMA CH Register */ + __IO mxc_dma_ch_regs_t ch[8]; /**< \b 0x100: DMA CH Register */ } mxc_dma_regs_t; /* Register offsets for module DMA */ diff --git a/Libraries/CMSIS/Device/Maxim/MAX78002/Include/dvs_regs.h b/Libraries/CMSIS/Device/Maxim/MAX78002/Include/dvs_regs.h index 717a38067a2..6c63a282a93 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX78002/Include/dvs_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX78002/Include/dvs_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX78002/Include/fcr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX78002/Include/fcr_regs.h index 3ccdbf44a32..7929c8c3e9b 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX78002/Include/fcr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX78002/Include/fcr_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX78002/Include/flc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX78002/Include/flc_regs.h index 8cc6ccaabbc..34d9f247dec 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX78002/Include/flc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX78002/Include/flc_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX78002/Include/gcfr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX78002/Include/gcfr_regs.h index f84cbdcb42d..4171c732e53 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX78002/Include/gcfr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX78002/Include/gcfr_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX78002/Include/gcr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX78002/Include/gcr_regs.h index 7991b94e222..7ac17ac7847 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX78002/Include/gcr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX78002/Include/gcr_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX78002/Include/gpio_regs.h b/Libraries/CMSIS/Device/Maxim/MAX78002/Include/gpio_regs.h index 313fa8a55ad..d7eae47b6a8 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX78002/Include/gpio_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX78002/Include/gpio_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX78002/Include/i2c_regs.h b/Libraries/CMSIS/Device/Maxim/MAX78002/Include/i2c_regs.h index f350981398b..ecdef623dc6 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX78002/Include/i2c_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX78002/Include/i2c_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX78002/Include/i2s_regs.h b/Libraries/CMSIS/Device/Maxim/MAX78002/Include/i2s_regs.h index 48ca8737f97..4bed047323f 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX78002/Include/i2s_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX78002/Include/i2s_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX78002/Include/icc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX78002/Include/icc_regs.h index 7d578b9006a..558f427fe89 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX78002/Include/icc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX78002/Include/icc_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX78002/Include/lpcmp_regs.h b/Libraries/CMSIS/Device/Maxim/MAX78002/Include/lpcmp_regs.h index 46de4ca0ef5..4fcc974c239 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX78002/Include/lpcmp_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX78002/Include/lpcmp_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile @@ -99,14 +103,14 @@ typedef struct { #define MXC_F_LPCMP_CTRL_POL_POS 5 /**< CTRL_POL Position */ #define MXC_F_LPCMP_CTRL_POL ((uint32_t)(0x1UL << MXC_F_LPCMP_CTRL_POL_POS)) /**< CTRL_POL Mask */ -#define MXC_F_LPCMP_CTRL_INT_EN_POS 6 /**< CTRL_INT_EN Position */ -#define MXC_F_LPCMP_CTRL_INT_EN ((uint32_t)(0x1UL << MXC_F_LPCMP_CTRL_INT_EN_POS)) /**< CTRL_INT_EN Mask */ +#define MXC_F_LPCMP_CTRL_INTEN_POS 6 /**< CTRL_INTEN Position */ +#define MXC_F_LPCMP_CTRL_INTEN ((uint32_t)(0x1UL << MXC_F_LPCMP_CTRL_INTEN_POS)) /**< CTRL_INTEN Mask */ #define MXC_F_LPCMP_CTRL_OUT_POS 14 /**< CTRL_OUT Position */ #define MXC_F_LPCMP_CTRL_OUT ((uint32_t)(0x1UL << MXC_F_LPCMP_CTRL_OUT_POS)) /**< CTRL_OUT Mask */ -#define MXC_F_LPCMP_CTRL_INT_FL_POS 15 /**< CTRL_INT_FL Position */ -#define MXC_F_LPCMP_CTRL_INT_FL ((uint32_t)(0x1UL << MXC_F_LPCMP_CTRL_INT_FL_POS)) /**< CTRL_INT_FL Mask */ +#define MXC_F_LPCMP_CTRL_INTFL_POS 15 /**< CTRL_INTFL Position */ +#define MXC_F_LPCMP_CTRL_INTFL ((uint32_t)(0x1UL << MXC_F_LPCMP_CTRL_INTFL_POS)) /**< CTRL_INTFL Mask */ /**@} end of group LPCMP_CTRL_Register */ diff --git a/Libraries/CMSIS/Device/Maxim/MAX78002/Include/lpgcr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX78002/Include/lpgcr_regs.h index 6b536501c6b..91338d88d08 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX78002/Include/lpgcr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX78002/Include/lpgcr_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX78002/Include/max78002.svd b/Libraries/CMSIS/Device/Maxim/MAX78002/Include/max78002.svd index f20a8a91f1e..0919269cd44 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX78002/Include/max78002.svd +++ b/Libraries/CMSIS/Device/Maxim/MAX78002/Include/max78002.svd @@ -1598,9 +1598,7 @@ - 2 - 2 - DATAIN16[%s] + DATAIN16 CRC Data Input 0x0004 16 @@ -1616,9 +1614,7 @@ - 4 - 1 - DATAIN8[%s] + DATAIN8 CRC Data Input 0x0004 8 @@ -10468,7 +10464,7 @@ 1 - INT_EN + INTEN IRQ Enable. 6 1 @@ -10480,7 +10476,7 @@ 1 - INT_FL + INTFL IRQ Flag 15 1 @@ -17380,7 +17376,7 @@ signal(s) on transition(s) from low to high or high to low when PM.USBWKEN is se 0 - External_Clock + CLK1 Clock 1 1 diff --git a/Libraries/CMSIS/Device/Maxim/MAX78002/Include/mcr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX78002/Include/mcr_regs.h index 150142c5ce0..bb506e98e90 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX78002/Include/mcr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX78002/Include/mcr_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX78002/Include/owm_regs.h b/Libraries/CMSIS/Device/Maxim/MAX78002/Include/owm_regs.h index 9da39347288..a653a18faaf 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX78002/Include/owm_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX78002/Include/owm_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX78002/Include/pt_regs.h b/Libraries/CMSIS/Device/Maxim/MAX78002/Include/pt_regs.h index 382a78011c2..4a2a0c0162a 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX78002/Include/pt_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX78002/Include/pt_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX78002/Include/ptg_regs.h b/Libraries/CMSIS/Device/Maxim/MAX78002/Include/ptg_regs.h index 5fa7f97bcd0..4e7e7f2eb68 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX78002/Include/ptg_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX78002/Include/ptg_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX78002/Include/pwrseq_regs.h b/Libraries/CMSIS/Device/Maxim/MAX78002/Include/pwrseq_regs.h index 06e906e986c..dc581b595db 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX78002/Include/pwrseq_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX78002/Include/pwrseq_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX78002/Include/rtc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX78002/Include/rtc_regs.h index 25a8db7cc30..f6b2e6b99be 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX78002/Include/rtc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX78002/Include/rtc_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX78002/Include/sdhc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX78002/Include/sdhc_regs.h index 67bf3aed270..fd1e9ec7d18 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX78002/Include/sdhc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX78002/Include/sdhc_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX78002/Include/sema_regs.h b/Libraries/CMSIS/Device/Maxim/MAX78002/Include/sema_regs.h index 0dc79ee0ced..ded231578a2 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX78002/Include/sema_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX78002/Include/sema_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX78002/Include/simo_regs.h b/Libraries/CMSIS/Device/Maxim/MAX78002/Include/simo_regs.h index f77e64e9442..d1937d670bb 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX78002/Include/simo_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX78002/Include/simo_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX78002/Include/sir_regs.h b/Libraries/CMSIS/Device/Maxim/MAX78002/Include/sir_regs.h index d6e8672a88c..a88ee0b608e 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX78002/Include/sir_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX78002/Include/sir_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX78002/Include/spi_regs.h b/Libraries/CMSIS/Device/Maxim/MAX78002/Include/spi_regs.h index bf411b5eea8..2d35d11559c 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX78002/Include/spi_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX78002/Include/spi_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX78002/Include/tmr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX78002/Include/tmr_regs.h index 4057913ec03..013b23f71e7 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX78002/Include/tmr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX78002/Include/tmr_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX78002/Include/trimsir_regs.h b/Libraries/CMSIS/Device/Maxim/MAX78002/Include/trimsir_regs.h index ddafdaad899..3c1e16363c7 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX78002/Include/trimsir_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX78002/Include/trimsir_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX78002/Include/trng_regs.h b/Libraries/CMSIS/Device/Maxim/MAX78002/Include/trng_regs.h index 9d4cb42b6e8..7a75eb404f7 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX78002/Include/trng_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX78002/Include/trng_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX78002/Include/uart_regs.h b/Libraries/CMSIS/Device/Maxim/MAX78002/Include/uart_regs.h index f521b7e4918..dcc71354407 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX78002/Include/uart_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX78002/Include/uart_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile @@ -164,8 +168,8 @@ typedef struct { #define MXC_F_UART_CTRL_BCLKSRC ((uint32_t)(0x3UL << MXC_F_UART_CTRL_BCLKSRC_POS)) /**< CTRL_BCLKSRC Mask */ #define MXC_V_UART_CTRL_BCLKSRC_PERIPHERAL_CLOCK ((uint32_t)0x0UL) /**< CTRL_BCLKSRC_PERIPHERAL_CLOCK Value */ #define MXC_S_UART_CTRL_BCLKSRC_PERIPHERAL_CLOCK (MXC_V_UART_CTRL_BCLKSRC_PERIPHERAL_CLOCK << MXC_F_UART_CTRL_BCLKSRC_POS) /**< CTRL_BCLKSRC_PERIPHERAL_CLOCK Setting */ -#define MXC_V_UART_CTRL_BCLKSRC_EXTERNAL_CLOCK ((uint32_t)0x1UL) /**< CTRL_BCLKSRC_EXTERNAL_CLOCK Value */ -#define MXC_S_UART_CTRL_BCLKSRC_EXTERNAL_CLOCK (MXC_V_UART_CTRL_BCLKSRC_EXTERNAL_CLOCK << MXC_F_UART_CTRL_BCLKSRC_POS) /**< CTRL_BCLKSRC_EXTERNAL_CLOCK Setting */ +#define MXC_V_UART_CTRL_BCLKSRC_CLK1 ((uint32_t)0x1UL) /**< CTRL_BCLKSRC_CLK1 Value */ +#define MXC_S_UART_CTRL_BCLKSRC_CLK1 (MXC_V_UART_CTRL_BCLKSRC_CLK1 << MXC_F_UART_CTRL_BCLKSRC_POS) /**< CTRL_BCLKSRC_CLK1 Setting */ #define MXC_V_UART_CTRL_BCLKSRC_CLK2 ((uint32_t)0x2UL) /**< CTRL_BCLKSRC_CLK2 Value */ #define MXC_S_UART_CTRL_BCLKSRC_CLK2 (MXC_V_UART_CTRL_BCLKSRC_CLK2 << MXC_F_UART_CTRL_BCLKSRC_POS) /**< CTRL_BCLKSRC_CLK2 Setting */ #define MXC_V_UART_CTRL_BCLKSRC_CLK3 ((uint32_t)0x3UL) /**< CTRL_BCLKSRC_CLK3 Value */ diff --git a/Libraries/CMSIS/Device/Maxim/MAX78002/Include/usbhs_regs.h b/Libraries/CMSIS/Device/Maxim/MAX78002/Include/usbhs_regs.h index f2d9b7a3ab6..6d2f9b88ff0 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX78002/Include/usbhs_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX78002/Include/usbhs_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX78002/Include/wdt_regs.h b/Libraries/CMSIS/Device/Maxim/MAX78002/Include/wdt_regs.h index c99fbe44eb5..c4aac1e881e 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX78002/Include/wdt_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX78002/Include/wdt_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/CMSIS/Device/Maxim/MAX78002/Include/wut_regs.h b/Libraries/CMSIS/Device/Maxim/MAX78002/Include/wut_regs.h index 0a0c7ebfa91..1a0b4c398e4 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX78002/Include/wut_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX78002/Include/wut_regs.h @@ -50,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile diff --git a/Libraries/PeriphDrivers/Source/UART/uart_ai87.c b/Libraries/PeriphDrivers/Source/UART/uart_ai87.c index ac6c0cb42a9..c2d802fbad0 100644 --- a/Libraries/PeriphDrivers/Source/UART/uart_ai87.c +++ b/Libraries/PeriphDrivers/Source/UART/uart_ai87.c @@ -191,8 +191,7 @@ int MXC_UART_GetFrequency(mxc_uart_regs_t *uart) if (uart == MXC_UART3) { if ((uart->ctrl & MXC_F_UART_CTRL_BCLKSRC) == MXC_S_UART_CTRL_BCLKSRC_PERIPHERAL_CLOCK) { periphClock = IBRO_FREQ; - } else if ((uart->ctrl & MXC_F_UART_CTRL_BCLKSRC) == - MXC_S_UART_CTRL_BCLKSRC_EXTERNAL_CLOCK) { + } else if ((uart->ctrl & MXC_F_UART_CTRL_BCLKSRC) == MXC_S_UART_CTRL_BCLKSRC_CLK1) { periphClock = ERTCO_FREQ * 2; } else { return E_BAD_PARAM; diff --git a/Libraries/PeriphDrivers/Source/UART/uart_me21.c b/Libraries/PeriphDrivers/Source/UART/uart_me21.c index 1d26031563c..5eeb090e9f7 100644 --- a/Libraries/PeriphDrivers/Source/UART/uart_me21.c +++ b/Libraries/PeriphDrivers/Source/UART/uart_me21.c @@ -237,7 +237,7 @@ int MXC_UART_GetFrequency(mxc_uart_regs_t *uart) // check if UARt is LP UART if (uart == MXC_UART3) { - if ((uart->ctrl & MXC_F_UART_CTRL_BCLKSRC) == MXC_S_UART_CTRL_BCLKSRC_EXTERNAL_CLOCK) { + if ((uart->ctrl & MXC_F_UART_CTRL_BCLKSRC) == MXC_S_UART_REVB_CTRL_BCLKSRC_CLK1) { periphClock = EXTCLK2_FREQ * 2; } else if ((uart->ctrl & MXC_F_UART_CTRL_BCLKSRC) == MXC_S_UART_CTRL_BCLKSRC_PERIPHERAL_CLOCK) { From 7500d4f154aee84e0b6010e2bdae1ba0555bc976 Mon Sep 17 00:00:00 2001 From: Jeremy Kongs Date: Fri, 15 Nov 2024 14:28:51 -0600 Subject: [PATCH 35/37] fix(PeriphDrivers): Fix GPIO Structure Collision for HART UART (#1272) --- Libraries/PeriphDrivers/Include/MAX32675/mxc_pins.h | 3 +++ Libraries/PeriphDrivers/Include/MAX32680/mxc_pins.h | 2 ++ Libraries/PeriphDrivers/Source/AFE/hart_uart.c | 4 ++-- Libraries/PeriphDrivers/Source/SYS/pins_me16.c | 4 ++++ Libraries/PeriphDrivers/Source/SYS/pins_me20.c | 4 ++++ 5 files changed, 15 insertions(+), 2 deletions(-) diff --git a/Libraries/PeriphDrivers/Include/MAX32675/mxc_pins.h b/Libraries/PeriphDrivers/Include/MAX32675/mxc_pins.h index 370041103fd..344dbe93c1c 100644 --- a/Libraries/PeriphDrivers/Include/MAX32675/mxc_pins.h +++ b/Libraries/PeriphDrivers/Include/MAX32675/mxc_pins.h @@ -44,6 +44,9 @@ extern const mxc_gpio_cfg_t gpio_cfg_uart0_flow; extern const mxc_gpio_cfg_t gpio_cfg_uart0_flow_disable; extern const mxc_gpio_cfg_t gpio_cfg_uart1; extern const mxc_gpio_cfg_t gpio_cfg_uart1_flow; + +extern const mxc_gpio_cfg_t gpio_cfg_hart; + extern const mxc_gpio_cfg_t gpio_cfg_uart2; extern const mxc_gpio_cfg_t gpio_cfg_uart2_flow; extern const mxc_gpio_cfg_t gpio_cfg_uart2_flow_disable; diff --git a/Libraries/PeriphDrivers/Include/MAX32680/mxc_pins.h b/Libraries/PeriphDrivers/Include/MAX32680/mxc_pins.h index 45028d36480..5289f4de006 100644 --- a/Libraries/PeriphDrivers/Include/MAX32680/mxc_pins.h +++ b/Libraries/PeriphDrivers/Include/MAX32680/mxc_pins.h @@ -41,6 +41,8 @@ extern const mxc_gpio_cfg_t gpio_cfg_i2c2; extern const mxc_gpio_cfg_t gpio_cfg_i2c2b; extern const mxc_gpio_cfg_t gpio_cfg_i2c2c; +extern const mxc_gpio_cfg_t gpio_cfg_hart; + extern const mxc_gpio_cfg_t gpio_cfg_uart0; extern const mxc_gpio_cfg_t gpio_cfg_uart0_flow; extern const mxc_gpio_cfg_t gpio_cfg_uart0_flow_disable; diff --git a/Libraries/PeriphDrivers/Source/AFE/hart_uart.c b/Libraries/PeriphDrivers/Source/AFE/hart_uart.c index c1782bae8ec..4cd3fa8c259 100644 --- a/Libraries/PeriphDrivers/Source/AFE/hart_uart.c +++ b/Libraries/PeriphDrivers/Source/AFE/hart_uart.c @@ -193,12 +193,12 @@ static int hart_uart_init(mxc_uart_regs_t *uart, unsigned int baud, mxc_uart_clo switch (MXC_UART_GET_IDX(uart)) { case 0: - MXC_AFE_GPIO_Config(&gpio_cfg_uart0); + MXC_AFE_GPIO_Config(&gpio_cfg_hart); MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_UART0); break; case 2: - MXC_AFE_GPIO_Config(&gpio_cfg_uart2); + MXC_AFE_GPIO_Config(&gpio_cfg_hart); MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_UART2); break; diff --git a/Libraries/PeriphDrivers/Source/SYS/pins_me16.c b/Libraries/PeriphDrivers/Source/SYS/pins_me16.c index 5a897c98630..0fd55ce6960 100644 --- a/Libraries/PeriphDrivers/Source/SYS/pins_me16.c +++ b/Libraries/PeriphDrivers/Source/SYS/pins_me16.c @@ -55,6 +55,10 @@ const mxc_gpio_cfg_t gpio_cfg_uart1_flow = { MXC_GPIO0, (MXC_GPIO_PIN_30 | MXC_G const mxc_gpio_cfg_t gpio_cfg_uart1_flow_disable = { MXC_GPIO0, (MXC_GPIO_PIN_30 | MXC_GPIO_PIN_31), MXC_GPIO_FUNC_IN, MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +// NOTE: UART2 mapping B is tied to HART modem in the AFE and cannot be moved. +const mxc_gpio_cfg_t gpio_cfg_hart = { MXC_GPIO0, (MXC_GPIO_PIN_14 | MXC_GPIO_PIN_15), MXC_GPIO_FUNC_ALT2, + MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; + const mxc_gpio_cfg_t gpio_cfg_uart2 = { MXC_GPIO1, (MXC_GPIO_PIN_8 | MXC_GPIO_PIN_9), MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; const mxc_gpio_cfg_t gpio_cfg_uart2_flow = { MXC_GPIO1, (MXC_GPIO_PIN_10 | MXC_GPIO_PIN_11), MXC_GPIO_FUNC_ALT1, diff --git a/Libraries/PeriphDrivers/Source/SYS/pins_me20.c b/Libraries/PeriphDrivers/Source/SYS/pins_me20.c index ecb6a2f794e..f3247bfdc74 100644 --- a/Libraries/PeriphDrivers/Source/SYS/pins_me20.c +++ b/Libraries/PeriphDrivers/Source/SYS/pins_me20.c @@ -41,6 +41,10 @@ const mxc_gpio_cfg_t gpio_cfg_i2c1 = { MXC_GPIO0, (MXC_GPIO_PIN_16 | MXC_GPIO_PI const mxc_gpio_cfg_t gpio_cfg_i2c2 = { MXC_GPIO0, (MXC_GPIO_PIN_30 | MXC_GPIO_PIN_31), MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +// NOTE: UART0 is tied to HART modem in the AFE and cannot be moved. +const mxc_gpio_cfg_t gpio_cfg_hart = { MXC_GPIO0, (MXC_GPIO_PIN_0 | MXC_GPIO_PIN_1), MXC_GPIO_FUNC_ALT1, + MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; + const mxc_gpio_cfg_t gpio_cfg_uart0 = { MXC_GPIO0, (MXC_GPIO_PIN_0 | MXC_GPIO_PIN_1), MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; const mxc_gpio_cfg_t gpio_cfg_uart0_flow = { MXC_GPIO0, (MXC_GPIO_PIN_2 | MXC_GPIO_PIN_3), MXC_GPIO_FUNC_ALT2, From 247e670846cba468d5d1a2d24ec3613ca1525564 Mon Sep 17 00:00:00 2001 From: EricB-ADI <122300463+EricB-ADI@users.noreply.github.com> Date: Tue, 19 Nov 2024 14:18:09 -0600 Subject: [PATCH 36/37] build(ThirdParty): Added flag to select BLE_API directory (#1274) --- Libraries/libs.mk | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Libraries/libs.mk b/Libraries/libs.mk index 121f83a9f53..9bafe060948 100644 --- a/Libraries/libs.mk +++ b/Libraries/libs.mk @@ -78,8 +78,9 @@ INIT_EXTENDED ?= 0 # Default directory for libphy LIB_PHY_DIR ?= $(LIBS_DIR)/BlePhy +BLE_API ?= Cordio # Include the Cordio Library -CORDIO_DIR ?= $(LIBS_DIR)/Cordio +CORDIO_DIR ?= $(LIBS_DIR)/$(BLE_API) include $(CORDIO_DIR)/platform/targets/maxim/build/cordio_lib.mk PROJ_CFLAGS += -D__CORDIO__ From 98f390c9973b71c4066a2e35f7f598b8d8ba0f97 Mon Sep 17 00:00:00 2001 From: Cristian Cruz <71054319+crsz20@users.noreply.github.com> Date: Tue, 19 Nov 2024 15:14:44 -0600 Subject: [PATCH 37/37] fix(Examples): Link to the libphy.a directory in MAX32657 BLE5_ctr (#1275) --- Examples/MAX32657/Bluetooth/BLE5_ctr/project.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Examples/MAX32657/Bluetooth/BLE5_ctr/project.mk b/Examples/MAX32657/Bluetooth/BLE5_ctr/project.mk index e41ee807593..f1de6ad0dda 100644 --- a/Examples/MAX32657/Bluetooth/BLE5_ctr/project.mk +++ b/Examples/MAX32657/Bluetooth/BLE5_ctr/project.mk @@ -28,7 +28,7 @@ LIB_CORDIO = 1 CORDIO_DIR = $(LIBS_DIR)/Packetcraft-ADI -RF_PHY_DIR = $(LIBS_DIR)/RF-PHY +LIB_PHY_DIR ?= $(LIBS_DIR)/RF-PHY # Cordio library options BLE_HOST = 0