ROHD HCL provides a generic abstract Memory class which accepts a dynamic number of writePorts and readPorts, where each port is of type DataPortInterface. A DataPortInterface is a simple interface with en and addr as control signals and data signal(s). In a write interface, all signals are in the same direction. In a read interface, the control signals are in the opposite direction of the data signal(s).
A sub-class of DataPortInterface is theMaskedDataPortInterface, which adds mask to the data group of signals. The mask signal is a byte-enable signal, where each bit of mask controls one byte of data.
A sub-class of Memory is the RegisterFile, which inherits the same flexible interface from Memory. It has a configurable number of entries via numEntries.
The RegisterFile accepts masks on writes, but not on reads.
Currently, RegisterFile only generates flop-based memory (no latches).
The read path is combinational, so data is provided immediately according to the control signals.
The MemoryModel has the same interface as a Memory, but is non-synthesizable and uses a software-based SparseMemoryStorage as a backing for data storage. This is a useful tool for testing systems that have relatively large memories.