diff --git a/CMakeLists.txt b/CMakeLists.txt index 178f3455..2c7f7641 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -142,6 +142,7 @@ add_custom_command(TARGET ${EXECUTABLE} POST_BUILD install(TARGETS ${EXECUTABLE} RUNTIME DESTINATION ${INSTALL_PATH} COMPONENT applications) install(FILES ${CMAKE_CURRENT_SOURCE_DIR}/imgui.ini DESTINATION ${INSTALL_PATH}) +install(DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}/third_party/stlink/chips DESTINATION ${INSTALL_PATH}) if(WIN32) if(PRODUCTION) @@ -158,7 +159,6 @@ if(WIN32) endif() if(UNIX) - install(DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}/third_party/stlink/chips DESTINATION ${INSTALL_PATH}) install(FILES ${CMAKE_CURRENT_SOURCE_DIR}/launch/icon.png DESTINATION ${INSTALL_PATH}) install(FILES ${CMAKE_CURRENT_SOURCE_DIR}/launch/STMViewer.desktop PERMISSIONS OWNER_READ OWNER_WRITE OWNER_EXECUTE GROUP_READ GROUP_EXECUTE WORLD_READ WORLD_EXECUTE diff --git a/src/TargetMemoryHandler/StlinkHandler.cpp b/src/TargetMemoryHandler/StlinkHandler.cpp index 6f4e6439..3c14f4bf 100644 --- a/src/TargetMemoryHandler/StlinkHandler.cpp +++ b/src/TargetMemoryHandler/StlinkHandler.cpp @@ -2,11 +2,13 @@ #include +#include "logging.h" + StlinkHandler::StlinkHandler() { -#if defined(unix) || defined(__unix__) || defined(__unix) + // #if defined(unix) || defined(__unix__) || defined(__unix) init_chipids("./chips"); -#endif + // #endif } bool StlinkHandler::startAcqusition() diff --git a/third_party/stlink/inc/backend.h b/third_party/stlink/inc/backend.h index a45dccd8..6b9c9c0a 100644 --- a/third_party/stlink/inc/backend.h +++ b/third_party/stlink/inc/backend.h @@ -1,37 +1,39 @@ -#ifndef STLINK_BACKEND_H_ -#define STLINK_BACKEND_H_ +#ifndef BACKEND_H +#define BACKEND_H + +#include typedef struct _stlink_backend { void (*close) (stlink_t * sl); - int (*exit_debug_mode) (stlink_t * sl); - int (*enter_swd_mode) (stlink_t * sl); - int (*enter_jtag_mode) (stlink_t * stl); - int (*exit_dfu_mode) (stlink_t * stl); - int (*core_id) (stlink_t * stl); - int (*reset) (stlink_t * stl); - int (*jtag_reset) (stlink_t * stl, int value); - int (*run) (stlink_t * stl, enum run_type type); - int (*status) (stlink_t * stl); - int (*version) (stlink_t *sl); - int (*read_debug32) (stlink_t *sl, uint32_t addr, uint32_t *data); - int (*read_mem32) (stlink_t *sl, uint32_t addr, uint16_t len); - int (*write_debug32) (stlink_t *sl, uint32_t addr, uint32_t data); - int (*write_mem32) (stlink_t *sl, uint32_t addr, uint16_t len); - int (*write_mem8) (stlink_t *sl, uint32_t addr, uint16_t len); - int (*read_all_regs) (stlink_t *sl, struct stlink_reg * regp); - int (*read_reg) (stlink_t *sl, int r_idx, struct stlink_reg * regp); - int (*read_all_unsupported_regs) (stlink_t *sl, struct stlink_reg *regp); - int (*read_unsupported_reg) (stlink_t *sl, int r_idx, struct stlink_reg *regp); - int (*write_unsupported_reg) (stlink_t *sl, uint32_t value, int idx, struct stlink_reg *regp); - int (*write_reg) (stlink_t *sl, uint32_t reg, int idx); - int (*step) (stlink_t * stl); - int (*current_mode) (stlink_t * stl); - int (*force_debug) (stlink_t *sl); + int32_t (*exit_debug_mode) (stlink_t * sl); + int32_t (*enter_swd_mode) (stlink_t * sl); + int32_t (*enter_jtag_mode) (stlink_t * stl); + int32_t (*exit_dfu_mode) (stlink_t * stl); + int32_t (*core_id) (stlink_t * stl); + int32_t (*reset) (stlink_t * stl); + int32_t (*jtag_reset) (stlink_t * stl, int32_t value); + int32_t (*run) (stlink_t * stl, enum run_type type); + int32_t (*status) (stlink_t * stl); + int32_t (*version) (stlink_t *sl); + int32_t (*read_debug32) (stlink_t *sl, uint32_t addr, uint32_t *data); + int32_t (*read_mem32) (stlink_t *sl, uint32_t addr, uint16_t len); + int32_t (*write_debug32) (stlink_t *sl, uint32_t addr, uint32_t data); + int32_t (*write_mem32) (stlink_t *sl, uint32_t addr, uint16_t len); + int32_t (*write_mem8) (stlink_t *sl, uint32_t addr, uint16_t len); + int32_t (*read_all_regs) (stlink_t *sl, struct stlink_reg * regp); + int32_t (*read_reg) (stlink_t *sl, int32_t r_idx, struct stlink_reg * regp); + int32_t (*read_all_unsupported_regs) (stlink_t *sl, struct stlink_reg *regp); + int32_t (*read_unsupported_reg) (stlink_t *sl, int32_t r_idx, struct stlink_reg *regp); + int32_t (*write_unsupported_reg) (stlink_t *sl, uint32_t value, int32_t idx, struct stlink_reg *regp); + int32_t (*write_reg) (stlink_t *sl, uint32_t reg, int32_t idx); + int32_t (*step) (stlink_t * stl); + int32_t (*current_mode) (stlink_t * stl); + int32_t (*force_debug) (stlink_t *sl); int32_t (*target_voltage) (stlink_t *sl); - int (*set_swdclk) (stlink_t * stl, int freq_khz); - int (*trace_enable) (stlink_t * sl, uint32_t frequency); - int (*trace_disable) (stlink_t * sl); - int (*trace_read) (stlink_t * sl, uint8_t* buf, size_t size); + int32_t (*set_swdclk) (stlink_t * stl, int32_t freq_khz); + int32_t (*trace_enable) (stlink_t * sl, uint32_t frequency); + int32_t (*trace_disable) (stlink_t * sl); + int32_t (*trace_read) (stlink_t * sl, uint8_t* buf, uint32_t size); } stlink_backend_t; -#endif // STLINK_BACKEND_H_ +#endif // BACKEND_H diff --git a/third_party/stlink/inc/calculate.h b/third_party/stlink/inc/calculate.h new file mode 100644 index 00000000..ca0a39df --- /dev/null +++ b/third_party/stlink/inc/calculate.h @@ -0,0 +1,15 @@ +/* + * File: calculate.h + * + * Calculation of sector numbers and pages + */ + +#ifndef CALCULATE_H +#define CALCULATE_H + +uint32_t calculate_F4_sectornum(uint32_t); +uint32_t calculate_F7_sectornum(uint32_t); +uint32_t calculate_H7_sectornum(stlink_t *, uint32_t, uint32_t); +uint32_t calculate_L4_page(stlink_t *, uint32_t); + +#endif // CALCULATE_H diff --git a/third_party/stlink/inc/chipid.h b/third_party/stlink/inc/chipid.h index 1eae2cc3..6726a742 100644 --- a/third_party/stlink/inc/chipid.h +++ b/third_party/stlink/inc/chipid.h @@ -1,8 +1,11 @@ -#ifndef STLINK_CHIPID_H_ -#define STLINK_CHIPID_H_ +/* + * File: chipid.h + * + * Chip-ID parametres + */ -#include -#include +#ifndef CHIPID_H +#define CHIPID_H /* Chipid parametres */ struct stlink_chipid_params { @@ -18,10 +21,13 @@ struct stlink_chipid_params { uint32_t option_base; uint32_t option_size; uint32_t flags; - struct stlink_chipid_params * next; + struct stlink_chipid_params *next; }; struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chipid); - void init_chipids(char *dir_to_scan); -#endif // STLINK_CHIPID_H_ +void dump_a_chip(struct stlink_chipid_params *dev); +void process_chipfile(char *fname); +void init_chipids(char *dir_to_scan); + +#endif // CHIPID_H diff --git a/third_party/stlink/inc/commands.h b/third_party/stlink/inc/commands.h index 136adf80..64cecce1 100644 --- a/third_party/stlink/inc/commands.h +++ b/third_party/stlink/inc/commands.h @@ -1,5 +1,11 @@ -#ifndef STLINK_COMMANDS_H_ -#define STLINK_COMMANDS_H_ +/* + * File: commands.h + * + * stlink commands + */ + +#ifndef COMMANDS_H +#define COMMANDS_H enum stlink_commands { STLINK_GET_VERSION = 0xF1, @@ -54,4 +60,4 @@ enum stlink_dfu_commands { STLINK_DFU_EXIT = 0x07 }; -#endif // STLINK_COMMANDS_H_ +#endif // COMMANDS_H diff --git a/third_party/stlink/inc/common_flash.h b/third_party/stlink/inc/common_flash.h new file mode 100644 index 00000000..9b2b8405 --- /dev/null +++ b/third_party/stlink/inc/common_flash.h @@ -0,0 +1,51 @@ +/* + * File: common_flash.h + * + * Flash operations + */ + +#ifndef COMMON_FLASH_H +#define COMMON_FLASH_H + +#define BANK_1 0 +#define BANK_2 1 + +uint32_t get_stm32l0_flash_base(stlink_t *); +uint32_t read_flash_cr(stlink_t *, uint32_t); +void lock_flash(stlink_t *); +// static inline int32_t write_flash_sr(stlink_t *sl, uint32_t bank, uint32_t val); +void clear_flash_error(stlink_t *); +uint32_t read_flash_sr(stlink_t *sl, uint32_t bank); +uint32_t is_flash_busy(stlink_t *sl); +void wait_flash_busy(stlink_t *); +int32_t check_flash_error(stlink_t *); +// static inline uint32_t is_flash_locked(stlink_t *sl); +// static void unlock_flash(stlink_t *sl); +int32_t unlock_flash_if(stlink_t *); +int32_t lock_flash_option(stlink_t *); +// static bool is_flash_option_locked(stlink_t *sl); +// static int32_t unlock_flash_option(stlink_t *sl); +int32_t unlock_flash_option_if(stlink_t *); +void write_flash_cr_psiz(stlink_t *, uint32_t, uint32_t); +void clear_flash_cr_pg(stlink_t *, uint32_t); +// static void wait_flash_busy_progress(stlink_t *sl); +// static inline void write_flash_ar(stlink_t *sl, uint32_t n, uint32_t bank); +// static inline void write_flash_cr_snb(stlink_t *sl, uint32_t n, uint32_t bank); +// static void set_flash_cr_per(stlink_t *sl, uint32_t bank); +// static void clear_flash_cr_per(stlink_t *sl, uint32_t bank); +// static inline void write_flash_cr_bker_pnb(stlink_t *sl, uint32_t n); +// static void set_flash_cr_strt(stlink_t *sl, uint32_t bank); +// static void set_flash_cr_mer(stlink_t *sl, bool v, uint32_t bank); +int32_t stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr); +int32_t stlink_erase_flash_section(stlink_t *sl, stm32_addr_t base_addr, uint32_t size, bool align_size); +int32_t stlink_erase_flash_mass(stlink_t *sl); +int32_t stlink_mwrite_flash(stlink_t *sl, uint8_t *data, uint32_t length, stm32_addr_t addr); +int32_t stlink_fwrite_flash(stlink_t *sl, const char *path, stm32_addr_t addr); +int32_t stlink_fcheck_flash(stlink_t *sl, const char *path, stm32_addr_t addr); +int32_t stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, uint32_t length); +int32_t stlink_check_address_range_validity(stlink_t *sl, stm32_addr_t addr, uint32_t size); +int32_t stlink_check_address_alignment(stlink_t *sl, stm32_addr_t addr); +int32_t stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len, uint8_t eraseonly); +void stlink_fwrite_finalize(stlink_t *, stm32_addr_t); + +#endif // COMMON_FLASH_H diff --git a/third_party/stlink/inc/flash_loader.h b/third_party/stlink/inc/flash_loader.h index 85b92bef..33edc7ac 100644 --- a/third_party/stlink/inc/flash_loader.h +++ b/third_party/stlink/inc/flash_loader.h @@ -1,20 +1,28 @@ /* - * File: stlink.h + * File: flash_loader.h * - * This should contain all the common top level stlink interfaces, - * regardless of how the backend does the work.... + * Flash loaders */ -#ifndef STLINK_FLASH_LOADER_H_ -#define STLINK_FLASH_LOADER_H_ +#ifndef FLASH_LOADER_H +#define FLASH_LOADER_H -#include -#include +int32_t stlink_flash_loader_init(stlink_t *sl, flash_loader_t* fl); +// static int32_t loader_v_dependent_assignment(stlink_t *sl, +// const uint8_t **loader_code, uint32_t *loader_size, +// const uint8_t *high_v_loader, uint32_t high_v_loader_size, +// const uint8_t *low_v_loader, uint32_t low_v_loader_size); +int32_t stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, uint32_t* size); +int32_t stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, uint32_t size); -#include -int stlink_flash_loader_init(stlink_t *sl, flash_loader_t* fl); -int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size); -int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, size_t size); +/* === Functions from old header file flashloader.h === */ -#endif // STLINK_FLASH_LOADER_H_ +int32_t stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len, uint32_t pagesize); +// static void set_flash_cr_pg(stlink_t *sl, uint32_t bank); +// static void set_dma_state(stlink_t *sl, flash_loader_t *fl, int32_t bckpRstr); +int32_t stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl); +int32_t stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t addr, uint8_t *base, uint32_t len); +int32_t stlink_flashloader_stop(stlink_t *sl, flash_loader_t *fl); + +#endif // FLASH_LOADER_H diff --git a/third_party/stlink/inc/helper.h b/third_party/stlink/inc/helper.h index 96467377..ef374a5b 100644 --- a/third_party/stlink/inc/helper.h +++ b/third_party/stlink/inc/helper.h @@ -1,8 +1,13 @@ -#ifndef SYS_HELPER_H -#define SYS_HELPER_H +/* + * File: helper.h + * + * General helper functions + */ -unsigned time_ms(); +#ifndef HELPER_H +#define HELPER_H -int arg_parse_freq(const char *str); +uint32_t time_ms(); +int32_t arg_parse_freq(const char *str); -#endif /* SYS_HELPER_H */ +#endif // HELPER_H diff --git a/third_party/stlink/inc/lib_md5.h b/third_party/stlink/inc/lib_md5.h new file mode 100644 index 00000000..7275fd0b --- /dev/null +++ b/third_party/stlink/inc/lib_md5.h @@ -0,0 +1,65 @@ +/* + * WjCryptLib_Md5 (https://github.com/WaterJuice/WjCryptLib) + * Implementation of MD5 hash function. Originally written by Alexander Peslyak. + * Modified by WaterJuice retaining Public Domain license. + * This is free and unencumbered software released into the public domain - June 2013 - waterjuice.org + */ + +#ifndef LIB_MD5_H +#define LIB_MD5_H + +#pragma once + +/* TYPES */ + +/* Md5Context + * This must be initialised using Md5Initialised. + * Do not modify the contents of this structure directly. + */ +typedef struct { + uint32_t lo; + uint32_t hi; + uint32_t a; + uint32_t b; + uint32_t c; + uint32_t d; + uint8_t buffer[64]; + uint32_t block[16]; +} Md5Context; + +#define MD5_HASH_SIZE (128 / 8) + +typedef struct { + uint8_t bytes [MD5_HASH_SIZE]; +} MD5_HASH; + +/* PUBLIC FUNCTIONS */ + +/* Md5Initialise + * Initialises an MD5 Context. + * Use this to initialise/reset a context. + */ +void Md5Initialise(Md5Context* Context /* [out] */); + +/* Md5Update + * Adds data to the MD5 context. + * This will process the data and update the internal state of the context. + * Keep on calling this function until all the data has been added. + * Then call Md5Finalise to calculate the hash. + */ +void Md5Update(Md5Context* Context /* [in out] */, void const* Buffer /* [in] */, uint32_t BufferSize /* [in] */); + +/* Md5Finalise + * Performs the final calculation of the hash and returns the digest + * (16 byte buffer containing 128bit hash). + * After calling this, Md5Initialised must be used to reuse the context. + */ +void Md5Finalise(Md5Context* Context /* [in out] */, MD5_HASH* Digest /* [in] */); + +/* Md5Calculate + * Combines Md5Initialise, Md5Update, and Md5Finalise into one function. + * Calculates the MD5 hash of the buffer. + */ +void Md5Calculate(void const* Buffer /* [in] */, uint32_t BufferSize /* [in] */, MD5_HASH* Digest /* [in] */); + +#endif // LIB_MD5_H \ No newline at end of file diff --git a/third_party/stlink/inc/libusb_settings.h b/third_party/stlink/inc/libusb_settings.h index 2a595238..b0a51ad3 100644 --- a/third_party/stlink/inc/libusb_settings.h +++ b/third_party/stlink/inc/libusb_settings.h @@ -1,3 +1,9 @@ +/* + * File: libusb_settings.h + * + * Settings for libusb library + */ + #ifndef LIBUSB_SETTINGS_H #define LIBUSB_SETTINGS_H @@ -19,6 +25,7 @@ * v1.0.23 | 0x01000107 * v1.0.24 | 0x01000108 * v1.0.25 | 0x01000109 + * v1.0.26 | 0x01000110 */ #if defined (__FreeBSD__) @@ -32,11 +39,9 @@ #if defined (__FreeBSD__) #define MINIMAL_API_VERSION 0x01000102 // v1.0.16 #elif defined (__OpenBSD__) - #define MINIMAL_API_VERSION 0x01000105 // v1.0.21 + #define MINIMAL_API_VERSION 0x01000106 // v1.0.22 #elif defined (__linux__) - #define MINIMAL_API_VERSION 0x01000105 // v1.0.21 -#elif defined (__APPLE__) - #define MINIMAL_API_VERSION 0x01000109 // v1.0.25 + #define MINIMAL_API_VERSION 0x01000106 // v1.0.22 #elif defined (_WIN32) #define MINIMAL_API_VERSION 0x01000109 // v1.0.25 #endif diff --git a/third_party/stlink/inc/logging.h b/third_party/stlink/inc/logging.h index 6c97eb89..de5403ca 100644 --- a/third_party/stlink/inc/logging.h +++ b/third_party/stlink/inc/logging.h @@ -1,15 +1,18 @@ /* + * File: logging.h + * + * UglyLogging: Slow, yet another wheel reinvented, but enough to make the rest of our code pretty enough. * Ugly, low performance, configurable level, logging "framework" */ -#ifndef UGLYLOGGING_H -#define UGLYLOGGING_H +#ifndef LOGGING_H +#define LOGGING_H #include "spdlogWrapper.h" #ifdef __cplusplus extern "C" { -#endif +#endif // __cplusplus enum ugly_loglevel { UDEBUG = 90, @@ -22,16 +25,18 @@ enum ugly_loglevel { #define PRINTF_ARRT __attribute__ ((format (printf, 3, 4))) #else #define PRINTF_ARRT -#endif +#endif // __GNUC__ -int ugly_init(int maximum_threshold); -int ugly_log(int level, const char *tag, const char *format, ...) PRINTF_ARRT; -int ugly_libusb_log_level(enum ugly_loglevel v); +int32_t ugly_init(int32_t maximum_threshold); +int32_t ugly_log(int32_t level, const char *tag, const char *format, ...) PRINTF_ARRT; +int32_t ugly_libusb_log_level(enum ugly_loglevel v); #define UGLY_LOG_FILE (strstr(__FILE__, "/") != NULL ? \ strrchr(__FILE__, '/') + 1 : strstr(__FILE__, "\\") != NULL ? \ strrchr(__FILE__, '\\') + 1 : __FILE__) +// TODO: we need to write this in a more generic way, for now this should compile +// on visual studio (See http://stackoverflow.com/a/8673872/1836746) #define DLOG(...) spdlogLog(UDEBUG, __VA_ARGS__) #define ILOG(...) spdlogLog(UINFO, __VA_ARGS__) #define WLOG(...) spdlogLog(UWARN, __VA_ARGS__) @@ -39,6 +44,6 @@ int ugly_libusb_log_level(enum ugly_loglevel v); #ifdef __cplusplus } -#endif +#endif // __cplusplus -#endif // UGLYLOGGING_H +#endif // LOGGING_H diff --git a/third_party/stlink/inc/map_file.h b/third_party/stlink/inc/map_file.h new file mode 100644 index 00000000..f25602d1 --- /dev/null +++ b/third_party/stlink/inc/map_file.h @@ -0,0 +1,33 @@ +/* + * File: map_file.h + * + * File mapping + */ + +#ifndef MAP_FILE_H +#define MAP_FILE_H + +#ifndef O_BINARY +#define O_BINARY 0 +#endif // O_BINARY + +#ifdef STLINK_HAVE_SYS_MMAN_H +#include +#else +#include +#endif // STLINK_HAVE_SYS_MMAN_H + +/* Memory mapped file */ +typedef struct mapped_file { + uint8_t *base; + uint32_t len; +} mapped_file_t; + +#define MAPPED_FILE_INITIALIZER \ + { NULL, 0 } + +int32_t check_file(stlink_t *, mapped_file_t *, stm32_addr_t); +int32_t map_file(mapped_file_t *, const char *); +void unmap_file(mapped_file_t *); + +#endif // MAP_FILE_H diff --git a/third_party/stlink/inc/md5.h b/third_party/stlink/inc/md5.h index a69d7fc6..f5591e2c 100644 --- a/third_party/stlink/inc/md5.h +++ b/third_party/stlink/inc/md5.h @@ -1,63 +1,15 @@ /* - * WjCryptLib_Md5 (https://github.com/WaterJuice/WjCryptLib) - * Implementation of MD5 hash function. Originally written by Alexander Peslyak. - * Modified by WaterJuice retaining Public Domain license. - * This is free and unencumbered software released into the public domain - June 2013 - waterjuice.org + * File: md5.h + * + * MD5 hash function */ -#pragma once +#ifndef MD5_H +#define MD5_H -#include -#include +#include "map_file.h" -/* TYPES */ +void md5_calculate(mapped_file_t *); +void stlink_checksum(mapped_file_t *); -/* Md5Context - * This must be initialised using Md5Initialised. - * Do not modify the contents of this structure directly. - */ -typedef struct { - uint32_t lo; - uint32_t hi; - uint32_t a; - uint32_t b; - uint32_t c; - uint32_t d; - uint8_t buffer[64]; - uint32_t block[16]; -} Md5Context; - -#define MD5_HASH_SIZE (128 / 8) - -typedef struct { - uint8_t bytes [MD5_HASH_SIZE]; -} MD5_HASH; - -/* PUBLIC FUNCTIONS */ - -/* Md5Initialise - * Initialises an MD5 Context. - * Use this to initialise/reset a context. - */ -void Md5Initialise(Md5Context* Context /* [out] */); - -/* Md5Update - * Adds data to the MD5 context. - * This will process the data and update the internal state of the context. - * Keep on calling this function until all the data has been added. - * Then call Md5Finalise to calculate the hash. - */ -void Md5Update(Md5Context* Context /* [in out] */, void const* Buffer /* [in] */, uint32_t BufferSize /* [in] */); - -/* Md5Finalise - * Performs the final calculation of the hash and returns the digest - * (16 byte buffer containing 128bit hash). - * After calling this, Md5Initialised must be used to reuse the context. - */ -void Md5Finalise(Md5Context* Context /* [in out] */, MD5_HASH* Digest /* [in] */); - -/* Md5Calculate - * Combines Md5Initialise, Md5Update, and Md5Finalise into one function. - * Calculates the MD5 hash of the buffer. - */ -void Md5Calculate(void const* Buffer /* [in] */, uint32_t BufferSize /* [in] */, MD5_HASH* Digest /* [in] */); +#endif // MD5_H \ No newline at end of file diff --git a/third_party/stlink/inc/option_bytes.h b/third_party/stlink/inc/option_bytes.h new file mode 100644 index 00000000..7ab3e295 --- /dev/null +++ b/third_party/stlink/inc/option_bytes.h @@ -0,0 +1,47 @@ +/* + * File: option_bytes.h + * + * Read and write option bytes and option control registers + */ + +#ifndef OPTION_BYTES_H +#define OPTION_BYTES_H + +int32_t stlink_read_option_control_register_f0(stlink_t *sl, uint32_t *option_byte); +// static int32_t stlink_write_option_bytes_f0(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t len); +// static int32_t stlink_write_option_control_register_f0(stlink_t *sl, uint32_t option_cr); +int32_t stlink_read_option_control_register_f2(stlink_t *sl, uint32_t *option_byte); +int32_t stlink_read_option_bytes_f2(stlink_t *sl, uint32_t *option_byte); +int32_t stlink_read_option_control_register_f4(stlink_t *sl, uint32_t *option_byte); +int32_t stlink_read_option_bytes_f4(stlink_t *sl, uint32_t *option_byte); +// static int32_t stlink_write_option_bytes_f4(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len); +int32_t stlink_read_option_bytes_f7(stlink_t *sl, uint32_t *option_byte); +// static int32_t stlink_write_option_bytes_f7(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len); +int32_t stlink_read_option_control_register_f7(stlink_t *sl, uint32_t *option_byte); +// static int32_t stlink_write_option_control_register_f7(stlink_t *sl, uint32_t option_cr); +int32_t stlink_read_option_control_register1_f7(stlink_t *sl, uint32_t *option_byte); +// static int32_t stlink_write_option_control_register1_f7(stlink_t *sl, uint32_t option_cr1); +int32_t stlink_read_option_bytes_boot_add_f7(stlink_t *sl, uint32_t *option_byte); +// static int32_t stlink_write_option_bytes_boot_add_f7(stlink_t *sl, uint32_t option_byte_boot_add); +int32_t stlink_read_option_control_register_gx(stlink_t *sl, uint32_t *option_byte); +int32_t stlink_read_option_bytes_gx(stlink_t *sl, uint32_t *option_byte); +// static int32_t stlink_write_option_bytes_gx(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len); +// static int32_t stlink_write_option_bytes_h7(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len); +// static int32_t stlink_write_option_bytes_l0(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len); +// static int32_t stlink_write_option_bytes_l4(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len); +// static int32_t stlink_write_option_bytes_wb(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len); +int32_t stlink_read_option_control_register_wb(stlink_t *sl, uint32_t *option_byte); +// static int32_t stlink_write_option_control_register_wb(stlink_t *sl, uint32_t option_cr); +int32_t stlink_read_option_bytes_generic(stlink_t *sl, uint32_t *option_byte); +int32_t stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len); +int32_t stlink_fwrite_option_bytes(stlink_t *sl, const char *path, stm32_addr_t addr); +int32_t stlink_read_option_control_register32(stlink_t *sl, uint32_t *option_byte); +int32_t stlink_write_option_control_register32(stlink_t *sl, uint32_t option_cr); +int32_t stlink_read_option_control_register1_32(stlink_t *sl, uint32_t *option_byte); +int32_t stlink_write_option_control_register1_32(stlink_t *sl, uint32_t option_cr1); +int32_t stlink_read_option_bytes32(stlink_t *sl, uint32_t* option_byte); +int32_t stlink_write_option_bytes32(stlink_t *sl, uint32_t option_byte); +int32_t stlink_read_option_bytes_boot_add32(stlink_t *sl, uint32_t* option_byte); +int32_t stlink_write_option_bytes_boot_add32(stlink_t *sl, uint32_t option_bytes_boot_add); + +#endif // OPTION_BYTES_H diff --git a/third_party/stlink/inc/reg.h b/third_party/stlink/inc/register.h similarity index 98% rename from third_party/stlink/inc/reg.h rename to third_party/stlink/inc/register.h index b581a269..f1e9574c 100644 --- a/third_party/stlink/inc/reg.h +++ b/third_party/stlink/inc/register.h @@ -1,5 +1,11 @@ -#ifndef STLINK_REG_H_ -#define STLINK_REG_H_ +/* + * File: register.h + * + * Common STM32 registers + */ + +#ifndef REGISTER_H +#define REGISTER_H #define STLINK_REG_CM3_CPUID 0xE000ED00 @@ -123,4 +129,4 @@ #define STLINK_REG_CM7_ICIALLU 0xE000EF50 #define STLINK_REG_CM7_CCSIDR 0xE000ED80 -#endif // STLINK_REG_H_ +#endif // REGISTER_H diff --git a/third_party/stlink/inc/sg.h b/third_party/stlink/inc/sg.h index 212d03b2..b10d0f6f 100644 --- a/third_party/stlink/inc/sg.h +++ b/third_party/stlink/inc/sg.h @@ -1,13 +1,19 @@ +/* == nightwalker-87: TODO: CONTENT AND USE OF THIS SOURCE FILE IS TO BE VERIFIED (07.06.2023) == */ + /* - * File: sg.h - * Author: karl + * File: sg.h + * + * */ -#ifndef STLINK_SG_H -#define STLINK_SG_H +#ifndef SG_H +#define SG_H + +#include #include -#include + +#include "libusb_settings.h" /* Device access */ #define RDWR 0 @@ -35,15 +41,15 @@ struct stlink_libsg { libusb_context* libusb_ctx; libusb_device_handle *usb_handle; - unsigned ep_rep; - unsigned ep_req; + uint32_t ep_rep; + uint32_t ep_req; - int sg_fd; - int do_scsi_pt_err; + int32_t sg_fd; + int32_t do_scsi_pt_err; unsigned char cdb_cmd_blk[CDB_SL]; - int q_data_dir; // Q_DATA_IN, Q_DATA_OUT + int32_t q_data_dir; // Q_DATA_IN, Q_DATA_OUT // the start of the query data in the device memory space uint32_t q_addr; @@ -54,6 +60,46 @@ struct stlink_libsg { struct stlink_reg reg; }; -stlink_t* stlink_v1_open(const int verbose, int reset); +// static void clear_cdb(struct stlink_libsg *sl); +void _stlink_sg_close(stlink_t *sl); +// static int32_t get_usb_mass_storage_status(libusb_device_handle *handle, uint8_t endpoint, uint32_t *tag); +// static int32_t dump_CDB_command(uint8_t *cdb, uint8_t cdb_len); +int32_t send_usb_mass_storage_command(libusb_device_handle *handle, uint8_t endpoint_out, uint8_t *cdb, uint8_t cdb_length, + uint8_t lun, uint8_t flags, uint32_t expected_rx_size); +// static void get_sense(libusb_device_handle *handle, uint8_t endpoint_in, uint8_t endpoint_out); +int32_t send_usb_data_only(libusb_device_handle *handle, unsigned char endpoint_out, + unsigned char endpoint_in, unsigned char *cbuf, uint32_t length); +int32_t stlink_q(stlink_t *sl); +void stlink_stat(stlink_t *stl, char *txt); +int32_t _stlink_sg_version(stlink_t *stl); +int32_t _stlink_sg_current_mode(stlink_t *stl); +int32_t _stlink_sg_enter_swd_mode(stlink_t *sl); +int32_t _stlink_sg_enter_jtag_mode(stlink_t *sl); +int32_t _stlink_sg_exit_dfu_mode(stlink_t *sl); +int32_t _stlink_sg_core_id(stlink_t *sl); +int32_t _stlink_sg_reset(stlink_t *sl); +int32_t _stlink_sg_jtag_reset(stlink_t *sl, int32_t value); +int32_t _stlink_sg_status(stlink_t *sl); +int32_t _stlink_sg_force_debug(stlink_t *sl); +int32_t _stlink_sg_read_all_regs(stlink_t *sl, struct stlink_reg *regp); +int32_t _stlink_sg_read_reg(stlink_t *sl, int32_t r_idx, struct stlink_reg *regp); +int32_t _stlink_sg_write_reg(stlink_t *sl, uint32_t reg, int32_t idx); +void stlink_write_dreg(stlink_t *sl, uint32_t reg, uint32_t addr); +int32_t _stlink_sg_run(stlink_t *sl, enum run_type type); +int32_t _stlink_sg_step(stlink_t *sl); +void stlink_set_hw_bp(stlink_t *sl, int32_t fp_nr, uint32_t addr, int32_t fp); +void stlink_clr_hw_bp(stlink_t *sl, int32_t fp_nr); +int32_t _stlink_sg_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len); +int32_t _stlink_sg_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len); +int32_t _stlink_sg_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len); +int32_t _stlink_sg_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data); +int32_t _stlink_sg_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data); +int32_t _stlink_sg_exit_debug_mode(stlink_t *stl); + +// static stlink_backend_t _stlink_sg_backend = { }; + +// static stlink_t* stlink_open(const int32_t verbose); +stlink_t* stlink_v1_open_inner(const int32_t verbose); +stlink_t* stlink_v1_open(const int32_t verbose, int32_t reset); -#endif // STLINK_SG_H +#endif // SG_H diff --git a/third_party/stlink/inc/spdlogWrapper.h b/third_party/stlink/inc/spdlogWrapper.h index 09276557..26f34c8b 100644 --- a/third_party/stlink/inc/spdlogWrapper.h +++ b/third_party/stlink/inc/spdlogWrapper.h @@ -7,7 +7,7 @@ #define EXTERNC #endif -EXTERNC int spdlogLog(int level, const char* str, ...); +EXTERNC int spdlogLog(int level, const char *str, ...); #undef EXTERNC diff --git a/third_party/stlink/inc/stlink copy.h b/third_party/stlink/inc/stlink copy.h deleted file mode 100644 index 17601fda..00000000 --- a/third_party/stlink/inc/stlink copy.h +++ /dev/null @@ -1,331 +0,0 @@ - -/* - * File: stlink.h - * - * This should contain all the common top level stlink interfaces, - * regardless of how the backend does the work.... - */ - -#ifndef STLINK_H -#define STLINK_H - -#include -#include -#include - -#include "stm32.h" -#include "stm32flash.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#define STLINK_ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0])) - -/* Max data transfer size */ -// 6kB = max mem32_read block, 8kB sram -// #define Q_BUF_LEN 96 -#define Q_BUF_LEN (1024 * 100) - -/* Statuses of core */ -enum target_state { - TARGET_UNKNOWN = 0, - TARGET_RUNNING = 1, - TARGET_HALTED = 2, - TARGET_RESET = 3, - TARGET_DEBUG_RUNNING = 4, -}; - -#define STLINK_CORE_RUNNING 0x80 -#define STLINK_CORE_HALTED 0x81 - -/* STLINK modes */ -#define STLINK_DEV_DFU_MODE 0x00 -#define STLINK_DEV_MASS_MODE 0x01 -#define STLINK_DEV_DEBUG_MODE 0x02 -#define STLINK_DEV_UNKNOWN_MODE -1 - -/* NRST pin states */ -#define STLINK_DEBUG_APIV2_DRIVE_NRST_LOW 0x00 -#define STLINK_DEBUG_APIV2_DRIVE_NRST_HIGH 0x01 - -/* Baud rate divisors for SWDCLK */ -#define STLINK_SWDCLK_4MHZ_DIVISOR 0 -#define STLINK_SWDCLK_1P8MHZ_DIVISOR 1 -#define STLINK_SWDCLK_1P2MHZ_DIVISOR 2 -#define STLINK_SWDCLK_950KHZ_DIVISOR 3 -#define STLINK_SWDCLK_480KHZ_DIVISOR 7 -#define STLINK_SWDCLK_240KHZ_DIVISOR 15 -#define STLINK_SWDCLK_125KHZ_DIVISOR 31 -#define STLINK_SWDCLK_100KHZ_DIVISOR 40 -#define STLINK_SWDCLK_50KHZ_DIVISOR 79 -#define STLINK_SWDCLK_25KHZ_DIVISOR 158 -#define STLINK_SWDCLK_15KHZ_DIVISOR 265 -#define STLINK_SWDCLK_5KHZ_DIVISOR 798 - -#define STLINK_SERIAL_LENGTH 24 -#define STLINK_SERIAL_BUFFER_SIZE (STLINK_SERIAL_LENGTH + 1) - -#define STLINK_V3_MAX_FREQ_NB 10 - -#define STLINK_TRACE_BUF_LEN 2048 -#define STLINK_V2_MAX_TRACE_FREQUENCY 2000000 -#define STLINK_V3_MAX_TRACE_FREQUENCY 24000000 -#define STLINK_DEFAULT_TRACE_FREQUENCY 2000000 - -/* Map the relevant features, quirks and workaround for specific firmware version of stlink */ -#define STLINK_F_HAS_TRACE (1 << 0) -#define STLINK_F_HAS_SWD_SET_FREQ (1 << 1) -#define STLINK_F_HAS_JTAG_SET_FREQ (1 << 2) -#define STLINK_F_HAS_MEM_16BIT (1 << 3) -#define STLINK_F_HAS_GETLASTRWSTATUS2 (1 << 4) -#define STLINK_F_HAS_DAP_REG (1 << 5) -#define STLINK_F_QUIRK_JTAG_DP_READ (1 << 6) -#define STLINK_F_HAS_AP_INIT (1 << 7) -#define STLINK_F_HAS_DPBANKSEL (1 << 8) -#define STLINK_F_HAS_RW8_512BYTES (1 << 9) - -/* Additional MCU features */ -#define CHIP_F_HAS_DUAL_BANK (1 << 0) -#define CHIP_F_HAS_SWO_TRACING (1 << 1) - -/* Error code */ -#define STLINK_DEBUG_ERR_OK 0x80 -#define STLINK_DEBUG_ERR_FAULT 0x81 -#define STLINK_DEBUG_ERR_WRITE 0x0c -#define STLINK_DEBUG_ERR_WRITE_VERIFY 0x0d -#define STLINK_DEBUG_ERR_AP_WAIT 0x10 -#define STLINK_DEBUG_ERR_AP_FAULT 0x11 -#define STLINK_DEBUG_ERR_AP_ERROR 0x12 -#define STLINK_DEBUG_ERR_DP_WAIT 0x14 -#define STLINK_DEBUG_ERR_DP_FAULT 0x15 -#define STLINK_DEBUG_ERR_DP_ERROR 0x16 - -#define CMD_CHECK_NO 0 -#define CMD_CHECK_REP_LEN 1 -#define CMD_CHECK_STATUS 2 -#define CMD_CHECK_RETRY 3 /* check status and retry if wait error */ - -#define C_BUF_LEN 32 - -struct stlink_reg { - uint32_t r[16]; - uint32_t s[32]; - uint32_t xpsr; - uint32_t main_sp; - uint32_t process_sp; - uint32_t rw; - uint32_t rw2; - uint8_t control; - uint8_t faultmask; - uint8_t basepri; - uint8_t primask; - uint32_t fpscr; -}; - -typedef uint32_t stm32_addr_t; - -typedef struct flash_loader { - stm32_addr_t loader_addr; // loader sram addr - stm32_addr_t buf_addr; // buffer sram address - uint32_t rcc_dma_bkp; // backup RCC DMA enable state - uint32_t iwdg_kr; // IWDG key register address -} flash_loader_t; - -typedef struct _cortex_m3_cpuid_ { - uint16_t implementer_id; - uint16_t variant; - uint16_t part; - uint8_t revision; -} cortex_m3_cpuid_t; - -enum stlink_jtag_api_version { - STLINK_JTAG_API_V1 = 1, - STLINK_JTAG_API_V2, - STLINK_JTAG_API_V3, -}; - -typedef struct stlink_version_ { - uint32_t stlink_v; - uint32_t jtag_v; - uint32_t swim_v; - uint32_t st_vid; - uint32_t stlink_pid; - // jtag api version supported - enum stlink_jtag_api_version jtag_api; - // one bit for each feature supported. See macros STLINK_F_* - uint32_t flags; -} stlink_version_t; - -enum transport_type { - TRANSPORT_TYPE_ZERO = 0, - TRANSPORT_TYPE_LIBSG, - TRANSPORT_TYPE_LIBUSB, - TRANSPORT_TYPE_INVALID -}; - -enum connect_type { - CONNECT_HOT_PLUG = 0, - CONNECT_NORMAL = 1, - CONNECT_UNDER_RESET = 2, -}; - -enum reset_type { - RESET_AUTO = 0, - RESET_HARD = 1, - RESET_SOFT = 2, - RESET_SOFT_AND_HALT = 3, -}; - -enum run_type { - RUN_NORMAL = 0, - RUN_FLASH_LOADER = 1, -}; - - -typedef struct _stlink stlink_t; - -#include -#include - -struct _stlink { - struct _stlink_backend *backend; - void *backend_data; - - // room for the command header - unsigned char c_buf[C_BUF_LEN]; - // data transferred from or to device - unsigned char q_buf[Q_BUF_LEN]; - int q_len; - - // transport layer verboseness: 0 for no debug info, 10 for lots - int verbose; - int opt; - uint32_t core_id; // set by stlink_core_id(), result from STLINK_DEBUGREADCOREID - uint32_t chip_id; // set by stlink_load_device_params(), used to identify flash and sram - enum target_state core_stat; // set by stlink_status() - - char serial[STLINK_SERIAL_BUFFER_SIZE]; - int freq; // set by stlink_open_usb(), values: STLINK_SWDCLK_xxx_DIVISOR - - enum stm32_flash_type flash_type; - // stlink_chipid_params.flash_type, set by stlink_load_device_params(), values: STM32_FLASH_TYPE_xx - - stm32_addr_t flash_base; // STM32_FLASH_BASE, set by stlink_load_device_params() - size_t flash_size; // calculated by stlink_load_device_params() - size_t flash_pgsz; // stlink_chipid_params.flash_pagesize, set by stlink_load_device_params() - - /* sram settings */ - stm32_addr_t sram_base; // STM32_SRAM_BASE, set by stlink_load_device_params() - size_t sram_size; // stlink_chipid_params.sram_size, set by stlink_load_device_params() - - /* option settings */ - stm32_addr_t option_base; - size_t option_size; - - // bootloader - // sys_base and sys_size are not used by the tools, but are only there to download the bootloader code - // (see tests/sg.c) - stm32_addr_t sys_base; // stlink_chipid_params.bootrom_base, set by stlink_load_device_params() - size_t sys_size; // stlink_chipid_params.bootrom_size, set by stlink_load_device_params() - - struct stlink_version_ version; - - uint32_t chip_flags; // stlink_chipid_params.flags, set by stlink_load_device_params(), values: CHIP_F_xxx - - uint32_t max_trace_freq; // set by stlink_open_usb() -}; - -int stlink_enter_swd_mode(stlink_t *sl); -int stlink_enter_jtag_mode(stlink_t *sl); -int stlink_exit_debug_mode(stlink_t *sl); -int stlink_exit_dfu_mode(stlink_t *sl); -void stlink_close(stlink_t *sl); -int stlink_core_id(stlink_t *sl); -int stlink_reset(stlink_t *sl, enum reset_type type); -int stlink_run(stlink_t *sl, enum run_type type); -int stlink_status(stlink_t *sl); -int stlink_version(stlink_t *sl); -int stlink_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data); -int stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len); -int stlink_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data); -int stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len); -int stlink_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len); -int stlink_read_all_regs(stlink_t *sl, struct stlink_reg *regp); -int stlink_read_all_unsupported_regs(stlink_t *sl, struct stlink_reg *regp); -int stlink_read_reg(stlink_t *sl, int r_idx, struct stlink_reg *regp); -int stlink_read_unsupported_reg(stlink_t *sl, int r_idx, struct stlink_reg *regp); -int stlink_write_unsupported_reg(stlink_t *sl, uint32_t value, int r_idx, struct stlink_reg *regp); -int stlink_write_reg(stlink_t *sl, uint32_t reg, int idx); -int stlink_step(stlink_t *sl); -int stlink_current_mode(stlink_t *sl); -int stlink_force_debug(stlink_t *sl); -int stlink_target_voltage(stlink_t *sl); -int stlink_set_swdclk(stlink_t *sl, int freq_khz); -int stlink_trace_enable(stlink_t* sl, uint32_t frequency); -int stlink_trace_disable(stlink_t* sl); -int stlink_trace_read(stlink_t* sl, uint8_t* buf, size_t size); -int stlink_erase_flash_mass(stlink_t* sl); -int stlink_erase_flash_section(stlink_t *sl, stm32_addr_t base_addr, size_t size, bool align_size); -int stlink_write_flash(stlink_t* sl, stm32_addr_t address, uint8_t* data, uint32_t length, uint8_t eraseonly); -int stlink_parse_ihex(const char* path, uint8_t erased_pattern, uint8_t * * mem, size_t * size, uint32_t * begin); -uint8_t stlink_get_erased_pattern(stlink_t *sl); -int stlink_mwrite_flash(stlink_t *sl, uint8_t* data, uint32_t length, stm32_addr_t addr); -int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr); -int stlink_mwrite_sram(stlink_t *sl, uint8_t* data, uint32_t length, stm32_addr_t addr); -int stlink_fwrite_sram(stlink_t *sl, const char* path, stm32_addr_t addr); -int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, uint32_t length); - -//int stlink_chip_id(stlink_t *sl, uint32_t *chip_id); -int stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid); - -int stlink_erase_flash_page(stlink_t* sl, stm32_addr_t flashaddr); -uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr); -int stlink_check_address_range_validity(stlink_t *sl, stm32_addr_t addr, size_t size); -int stlink_check_address_alignment(stlink_t *sl, stm32_addr_t addr); -uint16_t read_uint16(const unsigned char *c, const int pt); -//void stlink_core_stat(stlink_t *sl); -void stlink_print_data(stlink_t *sl); -unsigned int is_bigendian(void); -uint32_t read_uint32(const unsigned char *c, const int pt); -void write_uint32(unsigned char* buf, uint32_t ui); -void write_uint16(unsigned char* buf, uint16_t ui); -bool stlink_is_core_halted(stlink_t *sl); -int write_buffer_to_sram(stlink_t *sl, flash_loader_t* fl, const uint8_t* buf, size_t size); -int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size); -int stlink_fread(stlink_t* sl, const char* path, bool is_ihex, stm32_addr_t addr, size_t size); -int stlink_load_device_params(stlink_t *sl); - -int stlink_read_option_bytes32(stlink_t *sl, uint32_t* option_byte); -int stlink_read_option_bytes_boot_add32(stlink_t *sl, uint32_t* option_byte); -int stlink_read_option_control_register32(stlink_t *sl, uint32_t* option_byte); -int stlink_read_option_control_register1_32(stlink_t *sl, uint32_t* option_byte); - -int stlink_write_option_bytes32(stlink_t *sl, uint32_t option_byte); -int stlink_write_option_bytes_boot_add32(stlink_t *sl, uint32_t option_bytes_boot_add); -int stlink_write_option_control_register32(stlink_t *sl, uint32_t option_control_register); -int stlink_write_option_control_register1_32(stlink_t *sl, uint32_t option_control_register1); - -int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t len); -int stlink_fwrite_option_bytes(stlink_t *sl, const char* path, stm32_addr_t addr); - -int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl); -int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t addr, uint8_t* base, uint32_t len); -int stlink_flashloader_stop(stlink_t *sl, flash_loader_t *fl); - -int stlink_target_connect(stlink_t *sl, enum connect_type connect); - -#include -#include -#include -#include -#include -#include -#include -#include - -#ifdef __cplusplus -} -#endif - -#endif // STLINK_H diff --git a/third_party/stlink/inc/stlink.h b/third_party/stlink/inc/stlink.h index 17601fda..0a5c8564 100644 --- a/third_party/stlink/inc/stlink.h +++ b/third_party/stlink/inc/stlink.h @@ -1,23 +1,21 @@ - /* * File: stlink.h * - * This should contain all the common top level stlink interfaces, - * regardless of how the backend does the work.... + * All common top level stlink interfaces, regardless of how the backend does the work.... */ #ifndef STLINK_H #define STLINK_H -#include -#include #include - -#include "stm32.h" -#include "stm32flash.h" +#include +#include +#include +#include #ifdef __cplusplus -extern "C" { +extern "C" +{ #endif #define STLINK_ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0])) @@ -27,305 +25,283 @@ extern "C" { // #define Q_BUF_LEN 96 #define Q_BUF_LEN (1024 * 100) -/* Statuses of core */ -enum target_state { - TARGET_UNKNOWN = 0, - TARGET_RUNNING = 1, - TARGET_HALTED = 2, - TARGET_RESET = 3, - TARGET_DEBUG_RUNNING = 4, -}; + /* Statuses of core */ + enum target_state + { + TARGET_UNKNOWN = 0, + TARGET_RUNNING = 1, + TARGET_HALTED = 2, + TARGET_RESET = 3, + TARGET_DEBUG_RUNNING = 4, + }; -#define STLINK_CORE_RUNNING 0x80 -#define STLINK_CORE_HALTED 0x81 +#define STLINK_CORE_RUNNING 0x80 +#define STLINK_CORE_HALTED 0x81 /* STLINK modes */ -#define STLINK_DEV_DFU_MODE 0x00 -#define STLINK_DEV_MASS_MODE 0x01 -#define STLINK_DEV_DEBUG_MODE 0x02 -#define STLINK_DEV_UNKNOWN_MODE -1 +#define STLINK_DEV_DFU_MODE 0x00 +#define STLINK_DEV_MASS_MODE 0x01 +#define STLINK_DEV_DEBUG_MODE 0x02 +#define STLINK_DEV_UNKNOWN_MODE -1 /* NRST pin states */ #define STLINK_DEBUG_APIV2_DRIVE_NRST_LOW 0x00 #define STLINK_DEBUG_APIV2_DRIVE_NRST_HIGH 0x01 /* Baud rate divisors for SWDCLK */ -#define STLINK_SWDCLK_4MHZ_DIVISOR 0 -#define STLINK_SWDCLK_1P8MHZ_DIVISOR 1 -#define STLINK_SWDCLK_1P2MHZ_DIVISOR 2 -#define STLINK_SWDCLK_950KHZ_DIVISOR 3 -#define STLINK_SWDCLK_480KHZ_DIVISOR 7 -#define STLINK_SWDCLK_240KHZ_DIVISOR 15 -#define STLINK_SWDCLK_125KHZ_DIVISOR 31 -#define STLINK_SWDCLK_100KHZ_DIVISOR 40 -#define STLINK_SWDCLK_50KHZ_DIVISOR 79 -#define STLINK_SWDCLK_25KHZ_DIVISOR 158 -#define STLINK_SWDCLK_15KHZ_DIVISOR 265 -#define STLINK_SWDCLK_5KHZ_DIVISOR 798 - -#define STLINK_SERIAL_LENGTH 24 -#define STLINK_SERIAL_BUFFER_SIZE (STLINK_SERIAL_LENGTH + 1) - -#define STLINK_V3_MAX_FREQ_NB 10 - -#define STLINK_TRACE_BUF_LEN 2048 -#define STLINK_V2_MAX_TRACE_FREQUENCY 2000000 +#define STLINK_SWDCLK_4MHZ_DIVISOR 0 +#define STLINK_SWDCLK_1P8MHZ_DIVISOR 1 +#define STLINK_SWDCLK_1P2MHZ_DIVISOR 2 +#define STLINK_SWDCLK_950KHZ_DIVISOR 3 +#define STLINK_SWDCLK_480KHZ_DIVISOR 7 +#define STLINK_SWDCLK_240KHZ_DIVISOR 15 +#define STLINK_SWDCLK_125KHZ_DIVISOR 31 +#define STLINK_SWDCLK_100KHZ_DIVISOR 40 +#define STLINK_SWDCLK_50KHZ_DIVISOR 79 +#define STLINK_SWDCLK_25KHZ_DIVISOR 158 +#define STLINK_SWDCLK_15KHZ_DIVISOR 265 +#define STLINK_SWDCLK_5KHZ_DIVISOR 798 + +#define STLINK_SERIAL_LENGTH 24 +#define STLINK_SERIAL_BUFFER_SIZE (STLINK_SERIAL_LENGTH + 1) + +#define STLINK_V3_MAX_FREQ_NB 10 + +#define STLINK_TRACE_BUF_LEN 2048 +#define STLINK_V2_MAX_TRACE_FREQUENCY 2000000 #define STLINK_V3_MAX_TRACE_FREQUENCY 24000000 -#define STLINK_DEFAULT_TRACE_FREQUENCY 2000000 +#define STLINK_DEFAULT_TRACE_FREQUENCY 2000000 /* Map the relevant features, quirks and workaround for specific firmware version of stlink */ -#define STLINK_F_HAS_TRACE (1 << 0) -#define STLINK_F_HAS_SWD_SET_FREQ (1 << 1) -#define STLINK_F_HAS_JTAG_SET_FREQ (1 << 2) -#define STLINK_F_HAS_MEM_16BIT (1 << 3) -#define STLINK_F_HAS_GETLASTRWSTATUS2 (1 << 4) -#define STLINK_F_HAS_DAP_REG (1 << 5) -#define STLINK_F_QUIRK_JTAG_DP_READ (1 << 6) -#define STLINK_F_HAS_AP_INIT (1 << 7) -#define STLINK_F_HAS_DPBANKSEL (1 << 8) -#define STLINK_F_HAS_RW8_512BYTES (1 << 9) +#define STLINK_F_HAS_TRACE (1 << 0) +#define STLINK_F_HAS_SWD_SET_FREQ (1 << 1) +#define STLINK_F_HAS_JTAG_SET_FREQ (1 << 2) +#define STLINK_F_HAS_MEM_16BIT (1 << 3) +#define STLINK_F_HAS_GETLASTRWSTATUS2 (1 << 4) +#define STLINK_F_HAS_DAP_REG (1 << 5) +#define STLINK_F_QUIRK_JTAG_DP_READ (1 << 6) +#define STLINK_F_HAS_AP_INIT (1 << 7) +#define STLINK_F_HAS_DPBANKSEL (1 << 8) +#define STLINK_F_HAS_RW8_512BYTES (1 << 9) /* Additional MCU features */ -#define CHIP_F_HAS_DUAL_BANK (1 << 0) -#define CHIP_F_HAS_SWO_TRACING (1 << 1) +#define CHIP_F_HAS_DUAL_BANK (1 << 0) +#define CHIP_F_HAS_SWO_TRACING (1 << 1) /* Error code */ -#define STLINK_DEBUG_ERR_OK 0x80 -#define STLINK_DEBUG_ERR_FAULT 0x81 -#define STLINK_DEBUG_ERR_WRITE 0x0c -#define STLINK_DEBUG_ERR_WRITE_VERIFY 0x0d -#define STLINK_DEBUG_ERR_AP_WAIT 0x10 -#define STLINK_DEBUG_ERR_AP_FAULT 0x11 -#define STLINK_DEBUG_ERR_AP_ERROR 0x12 -#define STLINK_DEBUG_ERR_DP_WAIT 0x14 -#define STLINK_DEBUG_ERR_DP_FAULT 0x15 -#define STLINK_DEBUG_ERR_DP_ERROR 0x16 - -#define CMD_CHECK_NO 0 -#define CMD_CHECK_REP_LEN 1 -#define CMD_CHECK_STATUS 2 -#define CMD_CHECK_RETRY 3 /* check status and retry if wait error */ +#define STLINK_DEBUG_ERR_OK 0x80 +#define STLINK_DEBUG_ERR_FAULT 0x81 +#define STLINK_DEBUG_ERR_WRITE 0x0c +#define STLINK_DEBUG_ERR_WRITE_VERIFY 0x0d +#define STLINK_DEBUG_ERR_AP_WAIT 0x10 +#define STLINK_DEBUG_ERR_AP_FAULT 0x11 +#define STLINK_DEBUG_ERR_AP_ERROR 0x12 +#define STLINK_DEBUG_ERR_DP_WAIT 0x14 +#define STLINK_DEBUG_ERR_DP_FAULT 0x15 +#define STLINK_DEBUG_ERR_DP_ERROR 0x16 + +#define CMD_CHECK_NO 0 +#define CMD_CHECK_REP_LEN 1 +#define CMD_CHECK_STATUS 2 +#define CMD_CHECK_RETRY 3 /* check status and retry if wait error */ #define C_BUF_LEN 32 -struct stlink_reg { - uint32_t r[16]; - uint32_t s[32]; - uint32_t xpsr; - uint32_t main_sp; - uint32_t process_sp; - uint32_t rw; - uint32_t rw2; - uint8_t control; - uint8_t faultmask; - uint8_t basepri; - uint8_t primask; - uint32_t fpscr; -}; - -typedef uint32_t stm32_addr_t; - -typedef struct flash_loader { - stm32_addr_t loader_addr; // loader sram addr - stm32_addr_t buf_addr; // buffer sram address - uint32_t rcc_dma_bkp; // backup RCC DMA enable state - uint32_t iwdg_kr; // IWDG key register address -} flash_loader_t; - -typedef struct _cortex_m3_cpuid_ { - uint16_t implementer_id; - uint16_t variant; - uint16_t part; - uint8_t revision; -} cortex_m3_cpuid_t; - -enum stlink_jtag_api_version { - STLINK_JTAG_API_V1 = 1, - STLINK_JTAG_API_V2, - STLINK_JTAG_API_V3, -}; - -typedef struct stlink_version_ { - uint32_t stlink_v; - uint32_t jtag_v; - uint32_t swim_v; - uint32_t st_vid; - uint32_t stlink_pid; - // jtag api version supported - enum stlink_jtag_api_version jtag_api; - // one bit for each feature supported. See macros STLINK_F_* - uint32_t flags; -} stlink_version_t; - -enum transport_type { - TRANSPORT_TYPE_ZERO = 0, - TRANSPORT_TYPE_LIBSG, - TRANSPORT_TYPE_LIBUSB, - TRANSPORT_TYPE_INVALID -}; - -enum connect_type { - CONNECT_HOT_PLUG = 0, - CONNECT_NORMAL = 1, - CONNECT_UNDER_RESET = 2, -}; - -enum reset_type { - RESET_AUTO = 0, - RESET_HARD = 1, - RESET_SOFT = 2, - RESET_SOFT_AND_HALT = 3, -}; - -enum run_type { - RUN_NORMAL = 0, - RUN_FLASH_LOADER = 1, -}; - - -typedef struct _stlink stlink_t; + struct stlink_reg + { + uint32_t r[16]; + uint32_t s[32]; + uint32_t xpsr; + uint32_t main_sp; + uint32_t process_sp; + uint32_t rw; + uint32_t rw2; + uint8_t control; + uint8_t faultmask; + uint8_t basepri; + uint8_t primask; + uint32_t fpscr; + }; + + typedef uint32_t stm32_addr_t; + + typedef struct flash_loader + { + stm32_addr_t loader_addr; // loader sram addr + stm32_addr_t buf_addr; // buffer sram address + uint32_t rcc_dma_bkp; // backup RCC DMA enable state + uint32_t iwdg_kr; // IWDG key register address + } flash_loader_t; + + typedef struct _cortex_m3_cpuid_ + { + uint16_t implementer_id; + uint16_t variant; + uint16_t part; + uint8_t revision; + } cortex_m3_cpuid_t; + + enum stlink_jtag_api_version + { + STLINK_JTAG_API_V1 = 1, + STLINK_JTAG_API_V2, + STLINK_JTAG_API_V3, + }; + + typedef struct stlink_version_ + { + uint32_t stlink_v; + uint32_t jtag_v; + uint32_t swim_v; + uint32_t st_vid; + uint32_t stlink_pid; + // jtag api version supported + enum stlink_jtag_api_version jtag_api; + // one bit for each feature supported. See macros STLINK_F_* + uint32_t flags; + } stlink_version_t; + + enum transport_type + { + TRANSPORT_TYPE_ZERO = 0, + TRANSPORT_TYPE_LIBSG, + TRANSPORT_TYPE_LIBUSB, + TRANSPORT_TYPE_INVALID + }; + + enum connect_type + { + CONNECT_HOT_PLUG = 0, + CONNECT_NORMAL = 1, + CONNECT_UNDER_RESET = 2, + }; + + enum reset_type + { + RESET_AUTO = 0, + RESET_HARD = 1, + RESET_SOFT = 2, + RESET_SOFT_AND_HALT = 3, + }; + + enum run_type + { + RUN_NORMAL = 0, + RUN_FLASH_LOADER = 1, + }; + + typedef struct _stlink stlink_t; -#include #include +#include + + struct _stlink + { + struct _stlink_backend* backend; + void* backend_data; + + // room for the command header + unsigned char c_buf[C_BUF_LEN]; + // data transferred from or to device + unsigned char q_buf[Q_BUF_LEN]; + int32_t q_len; + + // transport layer verboseness: 0 for no debug info, 10 for lots + int32_t verbose; + int32_t opt; + uint32_t core_id; // set by stlink_core_id(), result from STLINK_DEBUGREADCOREID + uint32_t chip_id; // set by stlink_load_device_params(), used to identify flash and sram + enum target_state core_stat; // set by stlink_status() + + char serial[STLINK_SERIAL_BUFFER_SIZE]; + int32_t freq; // set by stlink_open_usb(), values: STLINK_SWDCLK_xxx_DIVISOR + + enum stm32_flash_type flash_type; + // stlink_chipid_params.flash_type, set by stlink_load_device_params(), values: STM32_FLASH_TYPE_xx + + stm32_addr_t flash_base; // STM32_FLASH_BASE, set by stlink_load_device_params() + uint32_t flash_size; // calculated by stlink_load_device_params() + uint32_t flash_pgsz; // stlink_chipid_params.flash_pagesize, set by stlink_load_device_params() + + /* sram settings */ + stm32_addr_t sram_base; // STM32_SRAM_BASE, set by stlink_load_device_params() + uint32_t sram_size; // stlink_chipid_params.sram_size, set by stlink_load_device_params() + + /* option settings */ + stm32_addr_t option_base; + uint32_t option_size; + + // bootloader + // sys_base and sys_size are not used by the tools, but are only there to download the bootloader code + // (see tests/sg.c) + stm32_addr_t sys_base; // stlink_chipid_params.bootrom_base, set by stlink_load_device_params() + uint32_t sys_size; // stlink_chipid_params.bootrom_size, set by stlink_load_device_params() + + struct stlink_version_ version; + + uint32_t chip_flags; // stlink_chipid_params.flags, set by stlink_load_device_params(), values: CHIP_F_xxx + + uint32_t max_trace_freq; // set by stlink_open_usb() + }; + + /* Functions defined in common.c */ + + int32_t stlink_enter_swd_mode(stlink_t* sl); + int32_t stlink_enter_jtag_mode(stlink_t* sl); + int32_t stlink_exit_debug_mode(stlink_t* sl); + int32_t stlink_exit_dfu_mode(stlink_t* sl); + void stlink_close(stlink_t* sl); + int32_t stlink_core_id(stlink_t* sl); + int32_t stlink_reset(stlink_t* sl, enum reset_type type); + int32_t stlink_run(stlink_t* sl, enum run_type type); + int32_t stlink_status(stlink_t* sl); + int32_t stlink_version(stlink_t* sl); + int32_t stlink_read_debug32(stlink_t* sl, uint32_t addr, uint32_t* data); + int32_t stlink_read_mem32(stlink_t* sl, uint32_t addr, uint16_t len); + int32_t stlink_write_debug32(stlink_t* sl, uint32_t addr, uint32_t data); + int32_t stlink_write_mem32(stlink_t* sl, uint32_t addr, uint16_t len); + int32_t stlink_write_mem8(stlink_t* sl, uint32_t addr, uint16_t len); + int32_t stlink_read_all_regs(stlink_t* sl, struct stlink_reg* regp); + int32_t stlink_read_all_unsupported_regs(stlink_t* sl, struct stlink_reg* regp); + int32_t stlink_read_reg(stlink_t* sl, int32_t r_idx, struct stlink_reg* regp); + int32_t stlink_read_unsupported_reg(stlink_t* sl, int32_t r_idx, struct stlink_reg* regp); + int32_t stlink_write_unsupported_reg(stlink_t* sl, uint32_t value, int32_t r_idx, struct stlink_reg* regp); + int32_t stlink_write_reg(stlink_t* sl, uint32_t reg, int32_t idx); + int32_t stlink_step(stlink_t* sl); + int32_t stlink_current_mode(stlink_t* sl); + int32_t stlink_force_debug(stlink_t* sl); + int32_t stlink_target_voltage(stlink_t* sl); + int32_t stlink_set_swdclk(stlink_t* sl, int32_t freq_khz); + int32_t stlink_trace_enable(stlink_t* sl, uint32_t frequency); + int32_t stlink_trace_disable(stlink_t* sl); + int32_t stlink_trace_read(stlink_t* sl, uint8_t* buf, uint32_t size); + int32_t stlink_parse_ihex(const char* path, uint8_t erased_pattern, uint8_t** mem, uint32_t* size, uint32_t* begin); + uint8_t stlink_get_erased_pattern(stlink_t* sl); + int32_t stlink_mwrite_sram(stlink_t* sl, uint8_t* data, uint32_t length, stm32_addr_t addr); + int32_t stlink_fwrite_sram(stlink_t* sl, const char* path, stm32_addr_t addr); + // int32_t stlink_chip_id(stlink_t *sl, uint32_t *chip_id); + int32_t stlink_cpu_id(stlink_t* sl, cortex_m3_cpuid_t* cpuid); + uint32_t stlink_calculate_pagesize(stlink_t* sl, uint32_t flashaddr); + uint16_t read_uint16(const unsigned char* c, const int32_t pt); + // void stlink_core_stat(stlink_t *sl); + void stlink_print_data(stlink_t* sl); + uint32_t is_bigendian(void); + uint32_t read_uint32(const unsigned char* c, const int32_t pt); + void write_uint32(unsigned char* buf, uint32_t ui); + void write_uint16(unsigned char* buf, uint16_t ui); + bool stlink_is_core_halted(stlink_t* sl); + int32_t write_buffer_to_sram(stlink_t* sl, flash_loader_t* fl, const uint8_t* buf, uint32_t size); + int32_t write_loader_to_sram(stlink_t* sl, stm32_addr_t* addr, size_t* size); + int32_t stlink_fread(stlink_t* sl, const char* path, bool is_ihex, stm32_addr_t addr, uint32_t size); + int32_t stlink_load_device_params(stlink_t* sl); + int32_t stlink_target_connect(stlink_t* sl, enum connect_type connect); -struct _stlink { - struct _stlink_backend *backend; - void *backend_data; - - // room for the command header - unsigned char c_buf[C_BUF_LEN]; - // data transferred from or to device - unsigned char q_buf[Q_BUF_LEN]; - int q_len; - - // transport layer verboseness: 0 for no debug info, 10 for lots - int verbose; - int opt; - uint32_t core_id; // set by stlink_core_id(), result from STLINK_DEBUGREADCOREID - uint32_t chip_id; // set by stlink_load_device_params(), used to identify flash and sram - enum target_state core_stat; // set by stlink_status() - - char serial[STLINK_SERIAL_BUFFER_SIZE]; - int freq; // set by stlink_open_usb(), values: STLINK_SWDCLK_xxx_DIVISOR - - enum stm32_flash_type flash_type; - // stlink_chipid_params.flash_type, set by stlink_load_device_params(), values: STM32_FLASH_TYPE_xx - - stm32_addr_t flash_base; // STM32_FLASH_BASE, set by stlink_load_device_params() - size_t flash_size; // calculated by stlink_load_device_params() - size_t flash_pgsz; // stlink_chipid_params.flash_pagesize, set by stlink_load_device_params() - - /* sram settings */ - stm32_addr_t sram_base; // STM32_SRAM_BASE, set by stlink_load_device_params() - size_t sram_size; // stlink_chipid_params.sram_size, set by stlink_load_device_params() - - /* option settings */ - stm32_addr_t option_base; - size_t option_size; - - // bootloader - // sys_base and sys_size are not used by the tools, but are only there to download the bootloader code - // (see tests/sg.c) - stm32_addr_t sys_base; // stlink_chipid_params.bootrom_base, set by stlink_load_device_params() - size_t sys_size; // stlink_chipid_params.bootrom_size, set by stlink_load_device_params() - - struct stlink_version_ version; - - uint32_t chip_flags; // stlink_chipid_params.flags, set by stlink_load_device_params(), values: CHIP_F_xxx - - uint32_t max_trace_freq; // set by stlink_open_usb() -}; - -int stlink_enter_swd_mode(stlink_t *sl); -int stlink_enter_jtag_mode(stlink_t *sl); -int stlink_exit_debug_mode(stlink_t *sl); -int stlink_exit_dfu_mode(stlink_t *sl); -void stlink_close(stlink_t *sl); -int stlink_core_id(stlink_t *sl); -int stlink_reset(stlink_t *sl, enum reset_type type); -int stlink_run(stlink_t *sl, enum run_type type); -int stlink_status(stlink_t *sl); -int stlink_version(stlink_t *sl); -int stlink_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data); -int stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len); -int stlink_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data); -int stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len); -int stlink_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len); -int stlink_read_all_regs(stlink_t *sl, struct stlink_reg *regp); -int stlink_read_all_unsupported_regs(stlink_t *sl, struct stlink_reg *regp); -int stlink_read_reg(stlink_t *sl, int r_idx, struct stlink_reg *regp); -int stlink_read_unsupported_reg(stlink_t *sl, int r_idx, struct stlink_reg *regp); -int stlink_write_unsupported_reg(stlink_t *sl, uint32_t value, int r_idx, struct stlink_reg *regp); -int stlink_write_reg(stlink_t *sl, uint32_t reg, int idx); -int stlink_step(stlink_t *sl); -int stlink_current_mode(stlink_t *sl); -int stlink_force_debug(stlink_t *sl); -int stlink_target_voltage(stlink_t *sl); -int stlink_set_swdclk(stlink_t *sl, int freq_khz); -int stlink_trace_enable(stlink_t* sl, uint32_t frequency); -int stlink_trace_disable(stlink_t* sl); -int stlink_trace_read(stlink_t* sl, uint8_t* buf, size_t size); -int stlink_erase_flash_mass(stlink_t* sl); -int stlink_erase_flash_section(stlink_t *sl, stm32_addr_t base_addr, size_t size, bool align_size); -int stlink_write_flash(stlink_t* sl, stm32_addr_t address, uint8_t* data, uint32_t length, uint8_t eraseonly); -int stlink_parse_ihex(const char* path, uint8_t erased_pattern, uint8_t * * mem, size_t * size, uint32_t * begin); -uint8_t stlink_get_erased_pattern(stlink_t *sl); -int stlink_mwrite_flash(stlink_t *sl, uint8_t* data, uint32_t length, stm32_addr_t addr); -int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr); -int stlink_mwrite_sram(stlink_t *sl, uint8_t* data, uint32_t length, stm32_addr_t addr); -int stlink_fwrite_sram(stlink_t *sl, const char* path, stm32_addr_t addr); -int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, uint32_t length); - -//int stlink_chip_id(stlink_t *sl, uint32_t *chip_id); -int stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid); - -int stlink_erase_flash_page(stlink_t* sl, stm32_addr_t flashaddr); -uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr); -int stlink_check_address_range_validity(stlink_t *sl, stm32_addr_t addr, size_t size); -int stlink_check_address_alignment(stlink_t *sl, stm32_addr_t addr); -uint16_t read_uint16(const unsigned char *c, const int pt); -//void stlink_core_stat(stlink_t *sl); -void stlink_print_data(stlink_t *sl); -unsigned int is_bigendian(void); -uint32_t read_uint32(const unsigned char *c, const int pt); -void write_uint32(unsigned char* buf, uint32_t ui); -void write_uint16(unsigned char* buf, uint16_t ui); -bool stlink_is_core_halted(stlink_t *sl); -int write_buffer_to_sram(stlink_t *sl, flash_loader_t* fl, const uint8_t* buf, size_t size); -int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size); -int stlink_fread(stlink_t* sl, const char* path, bool is_ihex, stm32_addr_t addr, size_t size); -int stlink_load_device_params(stlink_t *sl); - -int stlink_read_option_bytes32(stlink_t *sl, uint32_t* option_byte); -int stlink_read_option_bytes_boot_add32(stlink_t *sl, uint32_t* option_byte); -int stlink_read_option_control_register32(stlink_t *sl, uint32_t* option_byte); -int stlink_read_option_control_register1_32(stlink_t *sl, uint32_t* option_byte); - -int stlink_write_option_bytes32(stlink_t *sl, uint32_t option_byte); -int stlink_write_option_bytes_boot_add32(stlink_t *sl, uint32_t option_bytes_boot_add); -int stlink_write_option_control_register32(stlink_t *sl, uint32_t option_control_register); -int stlink_write_option_control_register1_32(stlink_t *sl, uint32_t option_control_register1); - -int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t len); -int stlink_fwrite_option_bytes(stlink_t *sl, const char* path, stm32_addr_t addr); - -int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl); -int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t addr, uint8_t* base, uint32_t len); -int stlink_flashloader_stop(stlink_t *sl, flash_loader_t *fl); - -int stlink_target_connect(stlink_t *sl, enum connect_type connect); - -#include -#include -#include -#include #include -#include +#include #include -#include #ifdef __cplusplus } #endif -#endif // STLINK_H +#endif // STLINK_H diff --git a/third_party/stlink/inc/stm32.h b/third_party/stlink/inc/stm32.h index 2d533eca..cf9a8a2a 100644 --- a/third_party/stlink/inc/stm32.h +++ b/third_party/stlink/inc/stm32.h @@ -7,11 +7,13 @@ #ifndef STM32_H #define STM32_H +#include + /* STM32 Cortex-M core ids (CPUTAPID) */ enum stm32_core_id { STM32_CORE_ID_M0_SWD = 0x0bb11477, // (RM0091 Section 32.5.3) F0 SW-DP - // (RM0444 Section 40.5.3) G0 SW-DP - STM32_CORE_ID_M0P_SWD = 0x0bc11477, // (RM0385 Section 27.5.3) L0 SW-DP + STM32_CORE_ID_M0P_SWD = 0x0bc11477, // (RM0444 Section 40.5.3) G0 SW-DP + // (RM0377 Section 27.5.3) L0 SW-DP STM32_CORE_ID_M3_r1p1_SWD = 0x1ba01477, // (RM0008 Section 31.8.3) F1 SW-DP STM32_CORE_ID_M3_r1p1_JTAG = 0x3ba00477, // (RM0008 Section 31.6.3) F1 JTAG STM32_CORE_ID_M3_r2p0_SWD = 0x2ba01477, // (RM0033 Section 32.8.3) F2 SW-DP @@ -29,9 +31,15 @@ enum stm32_core_id { STM32_CORE_ID_M4F_r0p1_JTAG = 0x4ba00477, // (RM0090 Section 38.6.3) F4 JTAG // (RM0090 Section 47.6.3) G4 JTAG STM32_CORE_ID_M7F_SWD = 0x5ba02477, // (RM0385 Section 40.8.3) F7 SW-DP + // (RM0473 Section 33.4.4) WB SW-DP + // (RM0453 Section 38.4.1) WL SW-DP STM32_CORE_ID_M7F_JTAG = 0x5ba00477, // (RM0385 Section 40.6.3) F7 JTAG - STM32_CORE_ID_M7F_H7_SWD = 0x6ba02477, // (RM0433 Section 60.4.1) H7 SW-DP - STM32_CORE_ID_M7F_H7_JTAG = 0x6ba00477, // (RM0433 Section 60.4.1) H7 JTAG + STM32_CORE_ID_M7F_M33_SWD = 0x6ba02477, // (RM0481 Section 58.3.3) H5 SW-DP + // (RM0433 Section 60.4.1) H7 SW-DP + STM32_CORE_ID_M7F_M33_JTAG = 0x6ba00477, // (RM0481 Section 58.3.1) H5 JTAG + // (RM0433 Section 60.4.1) H7 JTAG + // (RM0473 Section 33.4.1) WB JTAG + // (RM0453 Section 38.3.8) WL JTAG STM32_CORE_ID_M33_SWD = 0x0be02477, // (RM0438 Section 52.2.10) L5 SW-DP // (RM0456 Section 65.3.3) U5 SW-DP STM32_CORE_ID_M33_JTAGD = 0x0be01477, // (RM0438 Section 52.2.10) L5 JTAG-DP @@ -51,8 +59,8 @@ enum stm32_flash_type { STM32_FLASH_TYPE_G4 = 6, STM32_FLASH_TYPE_H7 = 7, STM32_FLASH_TYPE_L0_L1 = 8, - STM32_FLASH_TYPE_L4_L4P = 9, - STM32_FLASH_TYPE_L5_U5 = 10, + STM32_FLASH_TYPE_L4 = 9, + STM32_FLASH_TYPE_L5_U5_H5 = 10, STM32_FLASH_TYPE_WB_WL = 11, }; @@ -70,7 +78,7 @@ enum stm32_chipids { STM32_CHIPID_F1_HD = 0x414, /* high density */ STM32_CHIPID_L4 = 0x415, STM32_CHIPID_L1_MD = 0x416, /* medium density */ - STM32_CHIPID_L0 = 0x417, + STM32_CHIPID_L0_CAT3 = 0x417, STM32_CHIPID_F1_CONN = 0x418, /* connectivity line */ STM32_CHIPID_F4_HD = 0x419, /* high density */ STM32_CHIPID_F1_VL_MD_LD = 0x420, /* value line medium & low density */ @@ -104,22 +112,25 @@ enum stm32_chipids { STM32_CHIPID_F76xxx = 0x451, STM32_CHIPID_F72xxx = 0x452, /* Nucleo F722ZE board */ STM32_CHIPID_G0_CAT4 = 0x456, /* G051/G061 */ - STM32_CHIPID_L011 = 0x457, + STM32_CHIPID_L0_CAT1 = 0x457, STM32_CHIPID_F410 = 0x458, - STM32_CHIPID_G0_CAT2 = 0x460, /* G070/G071/G081 */ + STM32_CHIPID_G0_CAT2 = 0x460, /* G07x/G08x */ STM32_CHIPID_L496x_L4A6x = 0x461, STM32_CHIPID_L45x_L46x = 0x462, STM32_CHIPID_F413 = 0x463, STM32_CHIPID_L41x_L42x = 0x464, - STM32_CHIPID_G0_CAT1 = 0x466, /* G030/G031/G041 */ - STM32_CHIPID_G0_CAT3 = 0x467, /* G0B1/G0C1 */ + STM32_CHIPID_G0_CAT1 = 0x466, /* G03x/G04x */ + STM32_CHIPID_G0_CAT3 = 0x467, /* G0Bx/G0Cx */ STM32_CHIPID_G4_CAT2 = 0x468, /* RM0440, section 46.6.1 "MCU device ID code" */ STM32_CHIPID_G4_CAT3 = 0x469, STM32_CHIPID_L4Rx = 0x470, /* RM0432, p.2247, found on the STM32L4R9I-DISCO board */ STM32_CHIPID_L4PX = 0x471, /* RM0432, p.2247 */ + STM32_CHIPID_L5x2xx = 0x472, /* RM0438, p.2157 */ STM32_CHIPID_G4_CAT4 = 0x479, STM32_CHIPID_H7Ax = 0x480, /* RM0455, p.2863 */ + STM32_CHIPID_U5x5 = 0x482, /* RM0456, p.2991 */ STM32_CHIPID_H72x = 0x483, /* RM0468, p.3199 */ + STM32_CHIPID_H5xx = 0x484, /* RM0481, p.3085 */ STM32_CHIPID_WB55 = 0x495, STM32_CHIPID_WLE = 0x497, }; @@ -196,10 +207,16 @@ enum stm32_chipids { #define STM32L1_RCC_AHBENR 0x4002381C #define STM32L1_RCC_DMAEN 0x30000000 // DMA2EN | DMA1EN +#define STM32L5_RCC_AHB1ENR 0x40021048 // RM0438, p. 91,377 +#define STM32L5_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN // RM0438, p. 378 + #define STM32H7_RCC_AHB1ENR 0x58024538 #define STM32H7_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN #define STM32WB_RCC_AHB1ENR 0x58000048 #define STM32WB_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN +#define STM32L5_PWR_CR1 0x40007000 // RM0438, p. 93,324 +#define STM32L5_PWR_CR1_VOS 9 + #endif // STM32_H diff --git a/third_party/stlink/inc/stm32flash.h b/third_party/stlink/inc/stm32flash.h index 5e7ad2e4..69c6206e 100644 --- a/third_party/stlink/inc/stm32flash.h +++ b/third_party/stlink/inc/stm32flash.h @@ -1,8 +1,10 @@ #ifndef STM32FLASH_H #define STM32FLASH_H -/* stm32f FPEC flash controller interface, pm0063 manual */ -// STM32F05x is identical, based on RM0091 (DM00031936, Doc ID 018940 Rev 2, August 2012) +#include + +/* STM32Fx FPEC flash controller interface, PM0063 manual */ +// STM32F05x is identical, based on RM0091 (DM00031936, Doc ID 018940 Rev.2, Aug 2012) #define FLASH_REGS_ADDR 0x40022000 #define FLASH_REGS_SIZE 0x28 @@ -15,32 +17,19 @@ #define FLASH_OBR (FLASH_REGS_ADDR + 0x1c) #define FLASH_WRPR (FLASH_REGS_ADDR + 0x20) -// STM32F10x_XL has two flash memory banks with separate registers to control -// the second bank. +// STM32F10x_XL has two flash memory banks +// with separate registers to control the second bank. #define FLASH_KEYR2 (FLASH_REGS_ADDR + 0x44) #define FLASH_SR2 (FLASH_REGS_ADDR + 0x4c) #define FLASH_CR2 (FLASH_REGS_ADDR + 0x50) #define FLASH_AR2 (FLASH_REGS_ADDR + 0x54) -// For STM32F05x, the RDPTR_KEY may be wrong, but as it is not used anywhere... #define FLASH_RDPTR_KEY 0x00a5 #define FLASH_KEY1 0x45670123 #define FLASH_KEY2 0xcdef89ab -#define FLASH_L0_PRGKEY1 0x8c9daebf -#define FLASH_L0_PRGKEY2 0x13141516 - -#define FLASH_L0_PEKEY1 0x89abcdef -#define FLASH_L0_PEKEY2 0x02030405 - -#define FLASH_OPTKEY1 0x08192A3B -#define FLASH_OPTKEY2 0x4C5D6E7F - -#define FLASH_F0_OPTKEY1 0x45670123 -#define FLASH_F0_OPTKEY2 0xCDEF89AB - -#define FLASH_L0_OPTKEY1 0xFBEAD9C8 -#define FLASH_L0_OPTKEY2 0x24252627 +#define FLASH_OPTKEY1 0x08192a3b +#define FLASH_OPTKEY2 0x4c5d6e7f #define FLASH_SR_BSY 0 #define FLASH_SR_PG_ERR 2 @@ -59,170 +48,6 @@ #define FLASH_CR_OPTWRE 9 #define FLASH_CR_OBL_LAUNCH 13 -#define STM32L_FLASH_REGS_ADDR ((uint32_t)0x40023c00) -#define STM32L_FLASH_ACR (STM32L_FLASH_REGS_ADDR + 0x00) -#define STM32L_FLASH_PECR (STM32L_FLASH_REGS_ADDR + 0x04) -#define STM32L_FLASH_PDKEYR (STM32L_FLASH_REGS_ADDR + 0x08) -#define STM32L_FLASH_PEKEYR (STM32L_FLASH_REGS_ADDR + 0x0c) -#define STM32L_FLASH_PRGKEYR (STM32L_FLASH_REGS_ADDR + 0x10) -#define STM32L_FLASH_OPTKEYR (STM32L_FLASH_REGS_ADDR + 0x14) -#define STM32L_FLASH_SR (STM32L_FLASH_REGS_ADDR + 0x18) -#define STM32L_FLASH_OBR (STM32L_FLASH_REGS_ADDR + 0x1c) -#define STM32L_FLASH_WRPR (STM32L_FLASH_REGS_ADDR + 0x20) -#define FLASH_L1_FPRG 10 -#define FLASH_L1_PROG 3 - -// Flash registers common to STM32G0 and STM32G4 series. -#define STM32Gx_FLASH_REGS_ADDR ((uint32_t)0x40022000) -#define STM32Gx_FLASH_ACR (STM32Gx_FLASH_REGS_ADDR + 0x00) -#define STM32Gx_FLASH_KEYR (STM32Gx_FLASH_REGS_ADDR + 0x08) -#define STM32Gx_FLASH_OPTKEYR (STM32Gx_FLASH_REGS_ADDR + 0x0c) -#define STM32Gx_FLASH_SR (STM32Gx_FLASH_REGS_ADDR + 0x10) -#define STM32Gx_FLASH_CR (STM32Gx_FLASH_REGS_ADDR + 0x14) -#define STM32Gx_FLASH_ECCR (STM32Gx_FLASH_REGS_ADDR + 0x18) -#define STM32Gx_FLASH_OPTR (STM32Gx_FLASH_REGS_ADDR + 0x20) - -// G0 (RM0444 Table 1, sec 3.7) -// Mostly the same as G4 chips, but the notation -// varies a bit after the 'OPTR' register. -#define STM32G0_FLASH_REGS_ADDR (STM32Gx_FLASH_REGS_ADDR) -#define STM32G0_FLASH_PCROP1ASR (STM32G0_FLASH_REGS_ADDR + 0x24) -#define STM32G0_FLASH_PCROP1AER (STM32G0_FLASH_REGS_ADDR + 0x28) -#define STM32G0_FLASH_WRP1AR (STM32G0_FLASH_REGS_ADDR + 0x2C) -#define STM32G0_FLASH_WRP1BR (STM32G0_FLASH_REGS_ADDR + 0x30) -#define STM32G0_FLASH_PCROP1BSR (STM32G0_FLASH_REGS_ADDR + 0x34) -#define STM32G0_FLASH_PCROP1BER (STM32G0_FLASH_REGS_ADDR + 0x38) -#define STM32G0_FLASH_SECR (STM32G0_FLASH_REGS_ADDR + 0x80) - -// G4 (RM0440 Table 17, sec 3.7.19) -// Mostly the same as STM32G0 chips, but there are a few extra -// registers because 'cat 3' devices can have two Flash banks. -#define STM32G4_FLASH_REGS_ADDR (STM32Gx_FLASH_REGS_ADDR) -#define STM32G4_FLASH_PDKEYR (STM32G4_FLASH_REGS_ADDR + 0x04) -#define STM32G4_FLASH_PCROP1SR (STM32G4_FLASH_REGS_ADDR + 0x24) -#define STM32G4_FLASH_PCROP1ER (STM32G4_FLASH_REGS_ADDR + 0x28) -#define STM32G4_FLASH_WRP1AR (STM32G4_FLASH_REGS_ADDR + 0x2C) -#define STM32G4_FLASH_WRP1BR (STM32G4_FLASH_REGS_ADDR + 0x30) -#define STM32G4_FLASH_PCROP2SR (STM32G4_FLASH_REGS_ADDR + 0x44) -#define STM32G4_FLASH_PCROP2ER (STM32G4_FLASH_REGS_ADDR + 0x48) -#define STM32G4_FLASH_WRP2AR (STM32G4_FLASH_REGS_ADDR + 0x4C) -#define STM32G4_FLASH_WRP2BR (STM32G4_FLASH_REGS_ADDR + 0x50) -#define STM32G4_FLASH_SEC1R (STM32G4_FLASH_REGS_ADDR + 0x70) -#define STM32G4_FLASH_SEC2R (STM32G4_FLASH_REGS_ADDR + 0x74) - -// G0/G4 FLASH control register -#define STM32Gx_FLASH_CR_PG (0) /* Program */ -#define STM32Gx_FLASH_CR_PER (1) /* Page erase */ -#define STM32Gx_FLASH_CR_MER1 (2) /* Mass erase */ -#define STM32Gx_FLASH_CR_PNB (3) /* Page number */ -#define STM32G0_FLASH_CR_PNG_LEN (5) /* STM32G0: 5 page number bits */ -#define STM32G4_FLASH_CR_PNG_LEN (7) /* STM32G4: 7 page number bits */ -#define STM32Gx_FLASH_CR_MER2 (15) /* Mass erase (2nd bank)*/ -#define STM32Gx_FLASH_CR_STRT (16) /* Start */ -#define STM32Gx_FLASH_CR_OPTSTRT \ - (17) /* Start of modification of option bytes */ -#define STM32Gx_FLASH_CR_FSTPG (18) /* Fast programming */ -#define STM32Gx_FLASH_CR_EOPIE (24) /* End of operation interrupt enable */ -#define STM32Gx_FLASH_CR_ERRIE (25) /* Error interrupt enable */ -#define STM32Gx_FLASH_CR_OBL_LAUNCH (27) /* Forces the option byte loading */ -#define STM32Gx_FLASH_CR_OPTLOCK (30) /* Options Lock */ -#define STM32Gx_FLASH_CR_LOCK (31) /* FLASH_CR Lock */ - -// G0/G4 FLASH status register -#define STM32Gx_FLASH_SR_ERROR_MASK (0x3fa) -#define STM32Gx_FLASH_SR_PROGERR (3) -#define STM32Gx_FLASH_SR_WRPERR (4) -#define STM32Gx_FLASH_SR_PGAERR (5) -#define STM32Gx_FLASH_SR_BSY (16) /* FLASH_SR Busy */ -#define STM32Gx_FLASH_SR_EOP (0) /* FLASH_EOP End of Operation */ - -// G4 FLASH option register -#define STM32G4_FLASH_OPTR_DBANK (22) /* FLASH_OPTR Dual Bank Mode */ - -// WB (RM0434) -#define STM32WB_FLASH_REGS_ADDR ((uint32_t)0x58004000) -#define STM32WB_FLASH_ACR (STM32WB_FLASH_REGS_ADDR + 0x00) -#define STM32WB_FLASH_KEYR (STM32WB_FLASH_REGS_ADDR + 0x08) -#define STM32WB_FLASH_OPT_KEYR (STM32WB_FLASH_REGS_ADDR + 0x0C) -#define STM32WB_FLASH_SR (STM32WB_FLASH_REGS_ADDR + 0x10) -#define STM32WB_FLASH_CR (STM32WB_FLASH_REGS_ADDR + 0x14) -#define STM32WB_FLASH_ECCR (STM32WB_FLASH_REGS_ADDR + 0x18) -#define STM32WB_FLASH_OPTR (STM32WB_FLASH_REGS_ADDR + 0x20) -#define STM32WB_FLASH_PCROP1ASR (STM32WB_FLASH_REGS_ADDR + 0x24) -#define STM32WB_FLASH_PCROP1AER (STM32WB_FLASH_REGS_ADDR + 0x28) -#define STM32WB_FLASH_WRP1AR (STM32WB_FLASH_REGS_ADDR + 0x2C) -#define STM32WB_FLASH_WRP1BR (STM32WB_FLASH_REGS_ADDR + 0x30) -#define STM32WB_FLASH_PCROP1BSR (STM32WB_FLASH_REGS_ADDR + 0x34) -#define STM32WB_FLASH_PCROP1BER (STM32WB_FLASH_REGS_ADDR + 0x38) -#define STM32WB_FLASH_IPCCBR (STM32WB_FLASH_REGS_ADDR + 0x3C) -#define STM32WB_FLASH_C2ACR (STM32WB_FLASH_REGS_ADDR + 0x5C) -#define STM32WB_FLASH_C2SR (STM32WB_FLASH_REGS_ADDR + 0x60) -#define STM32WB_FLASH_C2CR (STM32WB_FLASH_REGS_ADDR + 0x64) -#define STM32WB_FLASH_SFR (STM32WB_FLASH_REGS_ADDR + 0x80) -#define STM32WB_FLASH_SRRVR (STM32WB_FLASH_REGS_ADDR + 0x84) - -// WB Flash control register. -#define STM32WB_FLASH_CR_STRT (16) /* Start */ -#define STM32WB_FLASH_CR_OPTSTRT (17) /* Start writing option bytes */ -#define STM32WB_FLASH_CR_OBL_LAUNCH (27) /* Forces the option byte loading */ -#define STM32WB_FLASH_CR_OPTLOCK (30) /* Option Lock */ -#define STM32WB_FLASH_CR_LOCK (31) /* Lock */ -// WB Flash status register. -#define STM32WB_FLASH_SR_ERROR_MASK (0x3f8) /* SR [9:3] */ -#define STM32WB_FLASH_SR_PROGERR (3) /* Programming alignment error */ -#define STM32WB_FLASH_SR_WRPERR (4) /* Write protection error */ -#define STM32WB_FLASH_SR_PGAERR (5) /* Programming error */ -#define STM32WB_FLASH_SR_BSY (16) /* Busy */ - -// 32L4 register base is at FLASH_REGS_ADDR (0x40022000) -#define STM32L4_FLASH_KEYR (FLASH_REGS_ADDR + 0x08) -#define STM32L4_FLASH_OPTKEYR (FLASH_REGS_ADDR + 0x0C) -#define STM32L4_FLASH_SR (FLASH_REGS_ADDR + 0x10) -#define STM32L4_FLASH_CR (FLASH_REGS_ADDR + 0x14) -#define STM32L4_FLASH_OPTR (FLASH_REGS_ADDR + 0x20) - -#define STM32L4_FLASH_SR_ERROR_MASK 0x3f8 /* SR [9:3] */ -#define STM32L4_FLASH_SR_PROGERR 3 -#define STM32L4_FLASH_SR_WRPERR 4 -#define STM32L4_FLASH_SR_PGAERR 5 -#define STM32L4_FLASH_SR_BSY 16 - -#define STM32L4_FLASH_CR_LOCK 31 /* Lock control register */ -#define STM32L4_FLASH_CR_OPTLOCK 30 /* Lock option bytes */ -#define STM32L4_FLASH_CR_PG 0 /* Program */ -#define STM32L4_FLASH_CR_PER 1 /* Page erase */ -#define STM32L4_FLASH_CR_MER1 2 /* Bank 1 erase */ -#define STM32L4_FLASH_CR_MER2 15 /* Bank 2 erase */ -#define STM32L4_FLASH_CR_STRT 16 /* Start command */ -#define STM32L4_FLASH_CR_OPTSTRT 17 /* Start writing option bytes */ -#define STM32L4_FLASH_CR_BKER 11 /* Bank select for page erase */ -#define STM32L4_FLASH_CR_PNB 3 /* Page number (8 bits) */ -#define STM32L4_FLASH_CR_OBL_LAUNCH 27 /* Option bytes reload */ -// Bits requesting flash operations (useful when we want to clear them) -#define STM32L4_FLASH_CR_OPBITS \ - (uint32_t)((1lu << STM32L4_FLASH_CR_PG) | (1lu << STM32L4_FLASH_CR_PER) | \ - (1lu << STM32L4_FLASH_CR_MER1) | (1lu << STM32L4_FLASH_CR_MER1)) -// Page is fully specified by BKER and PNB -#define STM32L4_FLASH_CR_PAGEMASK (uint32_t)(0x1fflu << STM32L4_FLASH_CR_PNB) - -#define STM32L4_FLASH_OPTR_DUALBANK 21 - -// STM32L0x flash register base and offsets RM0090 - DM00031020.pdf -#define STM32L0_FLASH_REGS_ADDR ((uint32_t)0x40022000) - -#define STM32L0_FLASH_PELOCK (0) -#define STM32L0_FLASH_OPTLOCK (2) -#define STM32L0_FLASH_OBL_LAUNCH (18) - -#define STM32L0_FLASH_SR_ERROR_MASK 0x00013F00 -#define STM32L0_FLASH_SR_WRPERR 8 -#define STM32L0_FLASH_SR_PGAERR 9 -#define STM32L0_FLASH_SR_NOTZEROERR 16 - -#define STM32L1_FLASH_SR_ERROR_MASK 0x00003F00 -#define STM32L1_FLASH_SR_WRPERR 8 -#define STM32L1_FLASH_SR_PGAERR 9 - #define FLASH_ACR_OFF ((uint32_t)0x00) #define FLASH_PECR_OFF ((uint32_t)0x04) #define FLASH_PDKEYR_OFF ((uint32_t)0x08) @@ -233,7 +58,55 @@ #define FLASH_OBR_OFF ((uint32_t)0x1c) #define FLASH_WRPR_OFF ((uint32_t)0x20) -// STM32F7 +// == STM32F0 == +#define FLASH_F0_OPTKEY1 0x45670123 +#define FLASH_F0_OPTKEY2 0xcdef89ab + +// == STM32F2 == +#define FLASH_F2_REGS_ADDR ((uint32_t)0x40023c00) +#define FLASH_F2_KEYR (FLASH_F2_REGS_ADDR + 0x04) +#define FLASH_F2_OPT_KEYR (FLASH_F2_REGS_ADDR + 0x08) +#define FLASH_F2_SR (FLASH_F2_REGS_ADDR + 0x0c) +#define FLASH_F2_CR (FLASH_F2_REGS_ADDR + 0x10) +#define FLASH_F2_OPT_CR (FLASH_F2_REGS_ADDR + 0x14) +#define FLASH_F2_OPT_LOCK_BIT (1u << 0) + +// F2 Flash control register +#define FLASH_F2_CR_STRT 16 +#define FLASH_F2_CR_LOCK 31 +#define FLASH_F2_CR_SER 1 +#define FLASH_F2_CR_SNB 3 +#define FLASH_F2_CR_SNB_MASK 0x78 + +// F2 Flash status register +#define FLASH_F2_SR_BSY 16 + +// == STM32F4 == +// F4 Flash registers +#define FLASH_F4_REGS_ADDR ((uint32_t)0x40023c00) +#define FLASH_F4_KEYR (FLASH_F4_REGS_ADDR + 0x04) +#define FLASH_F4_OPT_KEYR (FLASH_F4_REGS_ADDR + 0x08) +#define FLASH_F4_SR (FLASH_F4_REGS_ADDR + 0x0c) +#define FLASH_F4_CR (FLASH_F4_REGS_ADDR + 0x10) +#define FLASH_F4_OPTCR (FLASH_F4_REGS_ADDR + 0x14) +#define FLASH_F4_OPTCR_LOCK 0 +#define FLASH_F4_OPTCR_START 1 + +// F4 Flash control register +#define FLASH_F4_CR_STRT 16 +#define FLASH_F4_CR_LOCK 31 +#define FLASH_F4_CR_SER 1 +#define FLASH_F4_CR_SNB 3 +#define FLASH_F4_CR_SNB_MASK 0xf8 + +// F4 Flash status register +#define FLASH_F4_SR_ERROR_MASK 0x000000F0 +#define FLASH_F4_SR_PGAERR 5 +#define FLASH_F4_SR_WRPERR 4 +#define FLASH_F4_SR_BSY 16 + +// == STM32F7 == +// F7 Flash registers #define FLASH_F7_REGS_ADDR ((uint32_t)0x40023c00) #define FLASH_F7_KEYR (FLASH_F7_REGS_ADDR + 0x04) #define FLASH_F7_OPT_KEYR (FLASH_F7_REGS_ADDR + 0x08) @@ -243,11 +116,17 @@ #define FLASH_F7_OPTCR1 (FLASH_F7_REGS_ADDR + 0x18) #define FLASH_F7_OPTCR_LOCK 0 #define FLASH_F7_OPTCR_START 1 +#define FLASH_F7_OPTCR1_BOOT_ADD0 0 +#define FLASH_F7_OPTCR1_BOOT_ADD1 16 + +// F7 Flash control register #define FLASH_F7_CR_STRT 16 #define FLASH_F7_CR_LOCK 31 #define FLASH_F7_CR_SER 1 #define FLASH_F7_CR_SNB 3 #define FLASH_F7_CR_SNB_MASK 0xf8 + +// F7 Flash status register #define FLASH_F7_SR_BSY 16 #define FLASH_F7_SR_ERS_ERR 7 /* Erase Sequence Error */ #define FLASH_F7_SR_PGP_ERR 6 /* Programming parallelism error */ @@ -255,50 +134,106 @@ #define FLASH_F7_SR_WRP_ERR 4 /* Write protection error */ #define FLASH_F7_SR_OP_ERR 1 /* Operation error */ #define FLASH_F7_SR_EOP 0 /* End of operation */ -#define FLASH_F7_OPTCR1_BOOT_ADD0 0 -#define FLASH_F7_OPTCR1_BOOT_ADD1 16 - -#define FLASH_F7_SR_ERROR_MASK \ - ((1 << FLASH_F7_SR_ERS_ERR) | (1 << FLASH_F7_SR_PGP_ERR) | \ - (1 << FLASH_F7_SR_PGA_ERR) | (1 << FLASH_F7_SR_WRP_ERR) | \ +#define FLASH_F7_SR_ERROR_MASK \ + ((1 << FLASH_F7_SR_ERS_ERR) | (1 << FLASH_F7_SR_PGP_ERR) | \ + (1 << FLASH_F7_SR_PGA_ERR) | (1 << FLASH_F7_SR_WRP_ERR) | \ (1 << FLASH_F7_SR_OP_ERR)) -// STM32F4 -#define FLASH_F4_REGS_ADDR ((uint32_t)0x40023c00) -#define FLASH_F4_KEYR (FLASH_F4_REGS_ADDR + 0x04) -#define FLASH_F4_OPT_KEYR (FLASH_F4_REGS_ADDR + 0x08) -#define FLASH_F4_SR (FLASH_F4_REGS_ADDR + 0x0c) -#define FLASH_F4_CR (FLASH_F4_REGS_ADDR + 0x10) -#define FLASH_F4_OPTCR (FLASH_F4_REGS_ADDR + 0x14) -#define FLASH_F4_OPTCR_LOCK 0 -#define FLASH_F4_OPTCR_START 1 -#define FLASH_F4_CR_STRT 16 -#define FLASH_F4_CR_LOCK 31 -#define FLASH_F4_CR_SER 1 -#define FLASH_F4_CR_SNB 3 -#define FLASH_F4_CR_SNB_MASK 0xf8 -#define FLASH_F4_SR_ERROR_MASK 0x000000F0 -#define FLASH_F4_SR_PGAERR 5 -#define FLASH_F4_SR_WRPERR 4 -#define FLASH_F4_SR_BSY 16 +// == STM32G0/G4 == +// G0/G4 Flash registers (RM0440, p.146) +#define FLASH_Gx_REGS_ADDR ((uint32_t)0x40022000) +#define FLASH_Gx_ACR (FLASH_Gx_REGS_ADDR + 0x00) +#define FLASH_Gx_KEYR (FLASH_Gx_REGS_ADDR + 0x08) +#define FLASH_Gx_OPTKEYR (FLASH_Gx_REGS_ADDR + 0x0c) +#define FLASH_Gx_SR (FLASH_Gx_REGS_ADDR + 0x10) +#define FLASH_Gx_CR (FLASH_Gx_REGS_ADDR + 0x14) +#define FLASH_Gx_ECCR (FLASH_Gx_REGS_ADDR + 0x18) +#define FLASH_Gx_OPTR (FLASH_Gx_REGS_ADDR + 0x20) + +// G0/G4 Flash control register +#define FLASH_Gx_CR_PG (0) /* Program */ +#define FLASH_Gx_CR_PER (1) /* Page erase */ +#define FLASH_Gx_CR_MER1 (2) /* Mass erase */ +#define FLASH_Gx_CR_PNB (3) /* Page number */ +#define FLASH_G0_CR_PNG_LEN (5) /* STM32G0: 5 page number bits */ +#define FLASH_G4_CR_PNG_LEN (7) /* STM32G4: 7 page number bits */ +#define FLASH_Gx_CR_MER2 (15) /* Mass erase (2nd bank)*/ +#define FLASH_Gx_CR_STRT (16) /* Start */ +#define FLASH_Gx_CR_OPTSTRT (17) /* Start of modification of option bytes */ +#define FLASH_Gx_CR_FSTPG (18) /* Fast programming */ +#define FLASH_Gx_CR_EOPIE (24) /* End of operation interrupt enable */ +#define FLASH_Gx_CR_ERRIE (25) /* Error interrupt enable */ +#define FLASH_Gx_CR_OBL_LAUNCH (27) /* Forces the option byte loading */ +#define FLASH_Gx_CR_OPTLOCK (30) /* Options Lock */ +#define FLASH_Gx_CR_LOCK (31) /* FLASH_CR Lock */ + +// G0/G4 Flash status register +#define FLASH_Gx_SR_ERROR_MASK (0x3fa) +#define FLASH_Gx_SR_PROGERR (3) +#define FLASH_Gx_SR_WRPERR (4) +#define FLASH_Gx_SR_PGAERR (5) +#define FLASH_Gx_SR_BSY (16) /* FLASH_SR Busy */ +#define FLASH_Gx_SR_EOP (0) /* FLASH_EOP End of Operation */ + +// == STM32G0 == (RM0444 Table 1, sec. 3.7) +// Mostly the same as G4 chips, but the notation +// varies a bit after the 'OPTR' register. +#define FLASH_G0_REGS_ADDR (FLASH_Gx_REGS_ADDR) +#define FLASH_G0_PCROP1ASR (FLASH_G0_REGS_ADDR + 0x24) +#define FLASH_G0_PCROP1AER (FLASH_G0_REGS_ADDR + 0x28) +#define FLASH_G0_WRP1AR (FLASH_G0_REGS_ADDR + 0x2c) +#define FLASH_G0_WRP1BR (FLASH_G0_REGS_ADDR + 0x30) +#define FLASH_G0_PCROP1BSR (FLASH_G0_REGS_ADDR + 0x34) +#define FLASH_G0_PCROP1BER (FLASH_G0_REGS_ADDR + 0x38) +#define FLASH_G0_SECR (FLASH_G0_REGS_ADDR + 0x80) + +// == STM32G4 == (RM0440 Table 17, sec. 3.7.19) + +#define FLASH_G4_OPTR_DBANK (22) /* FLASH option register FLASH_OPTR Dual-Bank Mode */ + +// There are a few extra registers because 'cat 3' devices can have +// two Flash banks. +#define FLASH_G4_REGS_ADDR (FLASH_Gx_REGS_ADDR) +#define FLASH_G4_PDKEYR (FLASH_G4_REGS_ADDR + 0x04) +#define FLASH_G4_PCROP1SR (FLASH_G4_REGS_ADDR + 0x24) +#define FLASH_G4_PCROP1ER (FLASH_G4_REGS_ADDR + 0x28) +#define FLASH_G4_WRP1AR (FLASH_G4_REGS_ADDR + 0x2c) +#define FLASH_G4_WRP1BR (FLASH_G4_REGS_ADDR + 0x30) +#define FLASH_G4_PCROP2SR (FLASH_G4_REGS_ADDR + 0x44) +#define FLASH_G4_PCROP2ER (FLASH_G4_REGS_ADDR + 0x48) +#define FLASH_G4_WRP2AR (FLASH_G4_REGS_ADDR + 0x4c) +#define FLASH_G4_WRP2BR (FLASH_G4_REGS_ADDR + 0x50) +#define FLASH_G4_SEC1R (FLASH_G4_REGS_ADDR + 0x70) +#define FLASH_G4_SEC2R (FLASH_G4_REGS_ADDR + 0x74) + +// == STM32H7 == +// H7 Flash registers +#define FLASH_H7_REGS_ADDR ((uint32_t)0x52002000) +#define FLASH_H7_KEYR1 (FLASH_H7_REGS_ADDR + 0x04) +#define FLASH_H7_KEYR2 (FLASH_H7_REGS_ADDR + 0x104) +#define FLASH_H7_OPT_KEYR (FLASH_H7_REGS_ADDR + 0x08) +#define FLASH_H7_OPT_KEYR2 (FLASH_H7_REGS_ADDR + 0x108) +#define FLASH_H7_CR1 (FLASH_H7_REGS_ADDR + 0x0c) +#define FLASH_H7_CR2 (FLASH_H7_REGS_ADDR + 0x10c) +#define FLASH_H7_SR1 (FLASH_H7_REGS_ADDR + 0x10) +#define FLASH_H7_SR2 (FLASH_H7_REGS_ADDR + 0x110) +#define FLASH_H7_CCR1 (FLASH_H7_REGS_ADDR + 0x14) +#define FLASH_H7_CCR2 (FLASH_H7_REGS_ADDR + 0x114) +#define FLASH_H7_OPTCR (FLASH_H7_REGS_ADDR + 0x18) +#define FLASH_H7_OPTCR2 (FLASH_H7_REGS_ADDR + 0x118) +#define FLASH_H7_OPTSR_CUR (FLASH_H7_REGS_ADDR + 0x1c) +#define FLASH_H7_OPTCCR (FLASH_H7_REGS_ADDR + 0x24) -// STM32F2 -#define FLASH_F2_REGS_ADDR ((uint32_t)0x40023c00) -#define FLASH_F2_KEYR (FLASH_F2_REGS_ADDR + 0x04) -#define FLASH_F2_OPT_KEYR (FLASH_F2_REGS_ADDR + 0x08) -#define FLASH_F2_SR (FLASH_F2_REGS_ADDR + 0x0c) -#define FLASH_F2_CR (FLASH_F2_REGS_ADDR + 0x10) -#define FLASH_F2_OPT_CR (FLASH_F2_REGS_ADDR + 0x14) -#define FLASH_F2_OPT_LOCK_BIT (1u << 0) -#define FLASH_F2_CR_STRT 16 -#define FLASH_F2_CR_LOCK 31 +#define FLASH_H7_OPTCR_OPTLOCK 0 +#define FLASH_H7_OPTCR_OPTSTART 1 +#define FLASH_H7_OPTCR_MER 4 -#define FLASH_F2_CR_SER 1 -#define FLASH_F2_CR_SNB 3 -#define FLASH_F2_CR_SNB_MASK 0x78 -#define FLASH_F2_SR_BSY 16 +#define FLASH_H7_OPTSR_OPT_BUSY 0 +#define FLASH_H7_OPTSR_OPTCHANGEERR 30 -// STM32H7xx +#define FLASH_H7_OPTCCR_CLR_OPTCHANGEERR 30 + +// H7 Flash control register #define FLASH_H7_CR_LOCK 0 #define FLASH_H7_CR_PG 1 #define FLASH_H7_CR_SER 2 @@ -308,6 +243,7 @@ #define FLASH_H7_CR_SNB 8 #define FLASH_H7_CR_SNB_MASK 0x700 +// H7 Flash status register #define FLASH_H7_SR_QW 2 #define FLASH_H7_SR_WRPERR 17 #define FLASH_H7_SR_PGSERR 18 @@ -316,29 +252,162 @@ ((1 << FLASH_H7_SR_PGSERR) | (1 << FLASH_H7_SR_STRBERR) | \ (1 << FLASH_H7_SR_WRPERR)) -#define FLASH_H7_OPTCR_OPTLOCK 0 -#define FLASH_H7_OPTCR_OPTSTART 1 -#define FLASH_H7_OPTCR_MER 4 +// == STM32L0/L1/L4/L5 == +// Lx Flash registers +#define FLASH_Lx_REGS_ADDR ((uint32_t)0x40023c00) +#define FLASH_Lx_ACR (FLASH_Lx_REGS_ADDR + 0x00) +#define FLASH_Lx_PECR (FLASH_Lx_REGS_ADDR + 0x04) +#define FLASH_Lx_PDKEYR (FLASH_Lx_REGS_ADDR + 0x08) +#define FLASH_Lx_PEKEYR (FLASH_Lx_REGS_ADDR + 0x0c) +#define FLASH_Lx_PRGKEYR (FLASH_Lx_REGS_ADDR + 0x10) +#define FLASH_Lx_OPTKEYR (FLASH_Lx_REGS_ADDR + 0x14) +#define FLASH_Lx_SR (FLASH_Lx_REGS_ADDR + 0x18) +#define FLASH_Lx_OBR (FLASH_Lx_REGS_ADDR + 0x1c) +#define FLASH_Lx_WRPR (FLASH_Lx_REGS_ADDR + 0x20) + +// == STM32L0 == +// L0 Flash registers +#define FLASH_L0_PEKEY1 0x89abcdef +#define FLASH_L0_PEKEY2 0x02030405 -#define FLASH_H7_OPTSR_OPT_BUSY 0 -#define FLASH_H7_OPTSR_OPTCHANGEERR 30 +#define FLASH_L0_PRGKEY1 0x8c9daebf +#define FLASH_L0_PRGKEY2 0x13141516 -#define FLASH_H7_OPTCCR_CLR_OPTCHANGEERR 30 +#define FLASH_L0_OPTKEY1 0xFBEAD9C8 +#define FLASH_L0_OPTKEY2 0x24252627 -#define FLASH_H7_REGS_ADDR ((uint32_t)0x52002000) -#define FLASH_H7_KEYR1 (FLASH_H7_REGS_ADDR + 0x04) -#define FLASH_H7_KEYR2 (FLASH_H7_REGS_ADDR + 0x104) -#define FLASH_H7_OPT_KEYR (FLASH_H7_REGS_ADDR + 0x08) -#define FLASH_H7_OPT_KEYR2 (FLASH_H7_REGS_ADDR + 0x108) -#define FLASH_H7_CR1 (FLASH_H7_REGS_ADDR + 0x0c) -#define FLASH_H7_CR2 (FLASH_H7_REGS_ADDR + 0x10c) -#define FLASH_H7_SR1 (FLASH_H7_REGS_ADDR + 0x10) -#define FLASH_H7_SR2 (FLASH_H7_REGS_ADDR + 0x110) -#define FLASH_H7_CCR1 (FLASH_H7_REGS_ADDR + 0x14) -#define FLASH_H7_CCR2 (FLASH_H7_REGS_ADDR + 0x114) -#define FLASH_H7_OPTCR (FLASH_H7_REGS_ADDR + 0x18) -#define FLASH_H7_OPTCR2 (FLASH_H7_REGS_ADDR + 0x118) -#define FLASH_H7_OPTSR_CUR (FLASH_H7_REGS_ADDR + 0x1c) -#define FLASH_H7_OPTCCR (FLASH_H7_REGS_ADDR + 0x24) +#define FLASH_L0_REGS_ADDR ((uint32_t)0x40022000) + +#define FLASH_L0_PELOCK (0) +#define FLASH_L0_OPTLOCK (2) +#define FLASH_L0_OBL_LAUNCH (18) + +// L0 Flash status register +#define FLASH_L0_SR_ERROR_MASK 0x00013f00 +#define FLASH_L0_SR_WRPERR 8 +#define FLASH_L0_SR_PGAERR 9 +#define FLASH_L0_SR_NOTZEROERR 16 + +// == STM32L1 == +// L1 Flash registers +#define FLASH_L1_FPRG 10 +#define FLASH_L1_PROG 3 + +// L1 Flash status register +#define FLASH_L1_SR_ERROR_MASK 0x00003f00 +#define FLASH_L1_SR_WRPERR 8 +#define FLASH_L1_SR_PGAERR 9 + +// == STM32L4 == +// L4 Flash registers +// L4 register base is at FLASH_REGS_ADDR (0x40022000) +#define FLASH_L4_KEYR (FLASH_REGS_ADDR + 0x08) +#define FLASH_L4_OPTKEYR (FLASH_REGS_ADDR + 0x0c) +#define FLASH_L4_SR (FLASH_REGS_ADDR + 0x10) +#define FLASH_L4_CR (FLASH_REGS_ADDR + 0x14) +#define FLASH_L4_OPTR (FLASH_REGS_ADDR + 0x20) + +// L4 Flash status register +#define FLASH_L4_SR_ERROR_MASK 0x3f8 /* SR [9:3] */ +#define FLASH_L4_SR_PROGERR 3 +#define FLASH_L4_SR_WRPERR 4 +#define FLASH_L4_SR_PGAERR 5 +#define FLASH_L4_SR_BSY 16 + +// L4 Flash control register +#define FLASH_L4_CR_LOCK 31 /* Lock control register */ +#define FLASH_L4_CR_OPTLOCK 30 /* Lock option bytes */ +#define FLASH_L4_CR_PG 0 /* Program */ +#define FLASH_L4_CR_PER 1 /* Page erase */ +#define FLASH_L4_CR_MER1 2 /* Bank 1 erase */ +#define FLASH_L4_CR_MER2 15 /* Bank 2 erase */ +#define FLASH_L4_CR_STRT 16 /* Start command */ +#define FLASH_L4_CR_OPTSTRT 17 /* Start writing option bytes */ +#define FLASH_L4_CR_BKER 11 /* Bank select for page erase */ +#define FLASH_L4_CR_PNB 3 /* Page number (8 bits) */ +#define FLASH_L4_CR_OBL_LAUNCH 27 /* Option bytes reload */ +// Bits requesting flash operations (useful when we want to clear them) +#define FLASH_L4_CR_OPBITS \ + (uint32_t)((1lu << FLASH_L4_CR_PG) | (1lu << FLASH_L4_CR_PER) | \ + (1lu << FLASH_L4_CR_MER1) | (1lu << FLASH_L4_CR_MER1)) +// Page is fully specified by BKER and PNB +#define FLASH_L4_CR_PAGEMASK (uint32_t)(0x1fflu << FLASH_L4_CR_PNB) + +#define FLASH_L4_OPTR_DUALBANK 21 + +// == STM32L5 == (RM0438, p.241) +// L5 Flash registers +#define FLASH_L5_REGS_ADDR ((uint32_t)0x40022000) +#define FLASH_L5_ACR (FLASH_L5_REGS_ADDR + 0x00) +#define FLASH_L5_NSKEYR (FLASH_L5_REGS_ADDR + 0x08) +#define FLASH_L5_OPTKEYR (FLASH_L5_REGS_ADDR + 0x10) +#define FLASH_L5_NSSR (FLASH_L5_REGS_ADDR + 0x20) +#define FLASH_L5_NSCR (FLASH_L5_REGS_ADDR + 0x28) +#define FLASH_L5_ECCR (FLASH_L5_REGS_ADDR + 0x30) +#define FLASH_L5_OPTR (FLASH_L5_REGS_ADDR + 0x40) + +// FLASH_NSCR control registers (RM0438, p. 242) +#define FLASH_L5_NSCR_NSPG 0 /* Program */ +#define FLASH_L5_NSCR_NSPER 1 /* Page erase */ +#define FLASH_L5_NSCR_NSMER1 2 /* Bank 1 erase */ +#define FLASH_L5_NSCR_NSPNB 3 /* Page number (7 bits) */ +#define FLASH_L5_NSCR_NSBKER 11 /* Bank select for page erase */ +#define FLASH_L5_NSCR_NSMER2 15 /* Bank 2 erase */ +#define FLASH_L5_NSCR_NSSTRT 16 /* Start command */ +#define FLASH_L5_NSCR_NSOPTSTRT 17 /* Start writing option bytes */ +#define FLASH_L5_NSCR_NSEOPIE 24 +#define FLASH_L5_NSCR_NSERRIE 25 +#define FLASH_L5_NSCR_OBL_LAUNCH 27 /* Option bytes reload */ +#define FLASH_L5_NSCR_OPTLOCK 30 /* Lock option bytes */ +#define FLASH_L5_NSCR_NSLOCK 31 /* Lock control register */ + +// FLASH_NSSR status register (RM0438, p. 241) +#define FLASH_L5_NSSR_NSEOP 0 /* End of Operation */ +#define FLASH_L5_NSSR_NSOPERR 1 +#define FLASH_L5_NSSR_NSPROGERR 3 +#define FLASH_L5_NSSR_NSWRPERR 4 +#define FLASH_L5_NSSR_NSPGAERR 5 +#define FLASH_L5_NSSR_NSSIZERR 6 +#define FLASH_L5_NSSR_NSPGSERR 7 +#define FLASH_L5_NSSR_OPTWERR 12 +#define FLASH_L5_NSSR_BSY 16 /* Busy */ +#define FLASH_L5_NSSR_ERROR_MASK (0x20fa) + +// == STM32WB == (RM0434) +// WB Flash registers +#define FLASH_WB_REGS_ADDR ((uint32_t)0x58004000) +#define FLASH_WB_ACR (FLASH_WB_REGS_ADDR + 0x00) +#define FLASH_WB_KEYR (FLASH_WB_REGS_ADDR + 0x08) +#define FLASH_WB_OPT_KEYR (FLASH_WB_REGS_ADDR + 0x0c) +#define FLASH_WB_SR (FLASH_WB_REGS_ADDR + 0x10) +#define FLASH_WB_CR (FLASH_WB_REGS_ADDR + 0x14) +#define FLASH_WB_ECCR (FLASH_WB_REGS_ADDR + 0x18) +#define FLASH_WB_OPTR (FLASH_WB_REGS_ADDR + 0x20) +#define FLASH_WB_PCROP1ASR (FLASH_WB_REGS_ADDR + 0x24) +#define FLASH_WB_PCROP1AER (FLASH_WB_REGS_ADDR + 0x28) +#define FLASH_WB_WRP1AR (FLASH_WB_REGS_ADDR + 0x2c) +#define FLASH_WB_WRP1BR (FLASH_WB_REGS_ADDR + 0x30) +#define FLASH_WB_PCROP1BSR (FLASH_WB_REGS_ADDR + 0x34) +#define FLASH_WB_PCROP1BER (FLASH_WB_REGS_ADDR + 0x38) +#define FLASH_WB_IPCCBR (FLASH_WB_REGS_ADDR + 0x3c) +#define FLASH_WB_C2ACR (FLASH_WB_REGS_ADDR + 0x5c) +#define FLASH_WB_C2SR (FLASH_WB_REGS_ADDR + 0x60) +#define FLASH_WB_C2CR (FLASH_WB_REGS_ADDR + 0x64) +#define FLASH_WB_SFR (FLASH_WB_REGS_ADDR + 0x80) +#define FLASH_WB_SRRVR (FLASH_WB_REGS_ADDR + 0x84) + +// WB Flash control register +#define FLASH_WB_CR_STRT (16) /* Start */ +#define FLASH_WB_CR_OPTSTRT (17) /* Start writing option bytes */ +#define FLASH_WB_CR_OBL_LAUNCH (27) /* Forces the option byte loading */ +#define FLASH_WB_CR_OPTLOCK (30) /* Option Lock */ +#define FLASH_WB_CR_LOCK (31) /* Lock */ + +// WB Flash status register +#define FLASH_WB_SR_ERROR_MASK (0x3f8) /* SR [9:3] */ +#define FLASH_WB_SR_PROGERR (3) /* Programming alignment error */ +#define FLASH_WB_SR_WRPERR (4) /* Write protection error */ +#define FLASH_WB_SR_PGAERR (5) /* Programming error */ +#define FLASH_WB_SR_BSY (16) /* Busy */ #endif // STM32FLASH_H diff --git a/third_party/stlink/inc/usb.h b/third_party/stlink/inc/usb.h index 3f4b71e5..2ec7490a 100644 --- a/third_party/stlink/inc/usb.h +++ b/third_party/stlink/inc/usb.h @@ -1,15 +1,15 @@ /* - * File: usb.h - * Author: karl + * File: usb.h + * + * USB commands & interaction with ST-LINK devices */ -#ifndef STLINK_USB_H -#define STLINK_USB_H +#ifndef USB_H +#define USB_H -#include +#include -#include -#include +#include "libusb_settings.h" #include "logging.h" #define STLINK_USB_VID_ST 0x0483 @@ -46,28 +46,64 @@ #define STLINK_SG_SIZE 31 #define STLINK_CMD_SIZE 16 +enum SCSI_Generic_Direction {SG_DXFER_TO_DEV = 0, SG_DXFER_FROM_DEV = 0x80}; + struct stlink_libusb { libusb_context* libusb_ctx; libusb_device_handle* usb_handle; - unsigned int ep_req; - unsigned int ep_rep; - unsigned int ep_trace; - int protocoll; - unsigned int sg_transfer_idx; - unsigned int cmd_len; + uint32_t ep_req; + uint32_t ep_rep; + uint32_t ep_trace; + int32_t protocoll; + uint32_t sg_transfer_idx; + uint32_t cmd_len; }; -/** - * Open a stlink - * @param verbose Verbosity loglevel - * @param connect Type of connect to target - * @param serial Serial number to search for, when NULL the first stlink found is opened (binary format) - * @retval NULL Error while opening the stlink - * @retval !NULL Stlink found and ready to use - */ - -stlink_t *stlink_open_usb(enum ugly_loglevel verbose, enum connect_type connect, char serial[STLINK_SERIAL_BUFFER_SIZE], int freq); -size_t stlink_probe_usb(stlink_t **stdevs[], enum connect_type connect, int freq); -void stlink_probe_usb_free(stlink_t **stdevs[], size_t size); +// static inline uint32_t le_to_h_u32(const uint8_t* buf); +// static int32_t _stlink_match_speed_map(const uint32_t *map, uint32_t map_size, uint32_t khz); +void _stlink_usb_close(stlink_t* sl); +ssize_t send_recv(struct stlink_libusb* handle, int32_t terminate, unsigned char* txbuf, uint32_t txsize, + unsigned char* rxbuf, uint32_t rxsize, int32_t check_error, const char *cmd); +// static inline int32_t send_only(struct stlink_libusb* handle, int32_t terminate, unsigned char* txbuf, +// uint32_t txsize, const char *cmd); +// static int32_t fill_command(stlink_t * sl, enum SCSI_Generic_Direction dir, uint32_t len); +int32_t _stlink_usb_version(stlink_t *sl); +int32_t _stlink_usb_target_voltage(stlink_t *sl); +int32_t _stlink_usb_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data); +int32_t _stlink_usb_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data); +int32_t _stlink_usb_get_rw_status(stlink_t *sl); +int32_t _stlink_usb_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len); +int32_t _stlink_usb_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len); +int32_t _stlink_usb_current_mode(stlink_t * sl); +int32_t _stlink_usb_core_id(stlink_t * sl); +int32_t _stlink_usb_status_v2(stlink_t *sl); +int32_t _stlink_usb_status(stlink_t * sl); +int32_t _stlink_usb_force_debug(stlink_t *sl); +int32_t _stlink_usb_enter_swd_mode(stlink_t * sl); +int32_t _stlink_usb_exit_dfu_mode(stlink_t* sl); +int32_t _stlink_usb_reset(stlink_t * sl); +int32_t _stlink_usb_jtag_reset(stlink_t * sl, int32_t value); +int32_t _stlink_usb_step(stlink_t* sl); +int32_t _stlink_usb_run(stlink_t* sl, enum run_type type); +int32_t _stlink_usb_set_swdclk(stlink_t* sl, int32_t clk_freq); +int32_t _stlink_usb_exit_debug_mode(stlink_t *sl); +int32_t _stlink_usb_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len); +int32_t _stlink_usb_read_all_regs(stlink_t *sl, struct stlink_reg *regp); +int32_t _stlink_usb_read_reg(stlink_t *sl, int32_t r_idx, struct stlink_reg *regp); +int32_t _stlink_usb_read_unsupported_reg(stlink_t *sl, int32_t r_idx, struct stlink_reg *regp); +int32_t _stlink_usb_read_all_unsupported_regs(stlink_t *sl, struct stlink_reg *regp); +int32_t _stlink_usb_write_unsupported_reg(stlink_t *sl, uint32_t val, int32_t r_idx, struct stlink_reg *regp); +int32_t _stlink_usb_write_reg(stlink_t *sl, uint32_t reg, int32_t idx); +int32_t _stlink_usb_enable_trace(stlink_t* sl, uint32_t frequency); +int32_t _stlink_usb_disable_trace(stlink_t* sl); +int32_t _stlink_usb_read_trace(stlink_t* sl, uint8_t* buf, uint32_t size); + +// static stlink_backend_t _stlink_usb_backend = { }; + +size_t stlink_serial(struct libusb_device_handle *handle, struct libusb_device_descriptor *desc, char *serial); +stlink_t *stlink_open_usb(enum ugly_loglevel verbose, enum connect_type connect, char serial[STLINK_SERIAL_BUFFER_SIZE], int32_t freq); +// static uint32_t stlink_probe_usb_devs(libusb_device **devs, stlink_t **sldevs[], enum connect_type connect, int32_t freq); +size_t stlink_probe_usb(stlink_t **stdevs[], enum connect_type connect, int32_t freq); +void stlink_probe_usb_free(stlink_t **stdevs[], uint32_t size); -#endif // STLINK_USB_H +#endif // USB_H diff --git a/third_party/stlink/inc/version.h b/third_party/stlink/inc/version.h index a33bfc68..39020c0b 100644 --- a/third_party/stlink/inc/version.h +++ b/third_party/stlink/inc/version.h @@ -1,9 +1,9 @@ -#ifndef STLINK_VERSION_H_ -#define STLINK_VERSION_H_ +#ifndef VERSION_H +#define VERSION_H -#define STLINK_VERSION "1.7.0-237-g1bec78c" -#define STLINK_VERSION_MAJOR 1 -#define STLINK_VERSION_MINOR 7 -#define STLINK_VERSION_PATCH 0 +#define STLINK_VERSION "@PROJECT_VERSION@" +#define STLINK_VERSION_MAJOR @PROJECT_VERSION_MAJOR@ +#define STLINK_VERSION_MINOR @PROJECT_VERSION_MINOR@ +#define STLINK_VERSION_PATCH @PROJECT_VERSION_PATCH@ -#endif // STLINK_VERSION_H_ +#endif // VERSION_H diff --git a/third_party/stlink/lib/linux/libstlink.a b/third_party/stlink/lib/linux/libstlink.a index 077e7f6d..c44908c8 100644 Binary files a/third_party/stlink/lib/linux/libstlink.a and b/third_party/stlink/lib/linux/libstlink.a differ diff --git a/third_party/stlink/lib/windows/libstlink.a b/third_party/stlink/lib/windows/libstlink.a index b7cfa8c9..f28320c3 100644 Binary files a/third_party/stlink/lib/windows/libstlink.a and b/third_party/stlink/lib/windows/libstlink.a differ diff --git a/third_party/stlink/lib/windows/libstlink.dll b/third_party/stlink/lib/windows/libstlink.dll deleted file mode 100644 index 9410267d..00000000 Binary files a/third_party/stlink/lib/windows/libstlink.dll and /dev/null differ diff --git a/third_party/stlink/lib/windows/libstlink.dll.a b/third_party/stlink/lib/windows/libstlink.dll.a deleted file mode 100644 index c64acdf7..00000000 Binary files a/third_party/stlink/lib/windows/libstlink.dll.a and /dev/null differ diff --git a/third_party/stlink/lib/windows/libusb-1.0.dll b/third_party/stlink/lib/windows/libusb-1.0.dll deleted file mode 100644 index 5e85790c..00000000 Binary files a/third_party/stlink/lib/windows/libusb-1.0.dll and /dev/null differ