diff --git a/arch/arm/mach-omap2/board-am335xevm.c b/arch/arm/mach-omap2/board-am335xevm.c
index 66d761371457b0..ab41bb5fe5f29e 100644
--- a/arch/arm/mach-omap2/board-am335xevm.c
+++ b/arch/arm/mach-omap2/board-am335xevm.c
@@ -40,6 +40,7 @@
 #include <linux/pwm/pwm.h>
 #include <linux/w1-gpio.h>
 #include <linux/can/platform/mcp251x.h>
+#include <linux/input/ti_tscadc.h>
 
 /* LCD controller is similar to DA850 */
 #include <video/da8xx-fb.h>
@@ -298,7 +299,6 @@ struct da8xx_lcdc_platform_data dvi_pdata = {
 };
 
 /* TSc controller */
-#include <linux/input/ti_tscadc.h>
 #include <linux/lis3lv02d.h>
 
 /* TSc controller */
@@ -481,7 +481,7 @@ struct beaglebone_cape_eeprom_config {
 	char	partnumber[16];
 	u16  numpins;
 	char	serial[12];
-	u8	muxdata[170];
+	u16	muxdata[74];
 	u16  current_3v3;
 	u16  current_vdd5v;
 	u16  current_sys5v;
@@ -1428,6 +1428,7 @@ static struct pinmux_config bone_pin_mux[] = {
     {"gpmc_a8.rgmii2_rd3", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
     /* Grounding gpio1_6 (pin 3 Conn A) signals bone tester to start diag tests */
     {"gpmc_ad6.gpio1_6", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
+	{NULL, 0},
 };
 
 /* Module pin mux for eCAP0 */
@@ -2180,15 +2181,313 @@ static void tt3201_init(int evm_id, int profile)
 
 	am33xx_d_can_init(1);
 }
+
+static const char* cape_pins[] = {
+/*
+  From SRM RevA5.0.1:
+*/
+  /* offset  88 - P9-22 */ "uart2_rxd",
+  /* offset  90 - P9-21 */ "uart2_txd",
+  /* offset  92 - P9-18 */ "spi0_d1",
+  /* offset  94 - P9-17 */ "spi0_cs0",
+  /* offset  96 - P9-42 */ "ecap0_in_pwm0_out",
+  /* offset  98 - P8-35 */ "lcd_data12",
+  /* offset 100 - P8-33 */ "lcd_data13",
+  /* offset 102 - P8-31 */ "lcd_data14",
+  /* offset 104 - P8-32 */ "lcd_data15",
+  /* offset 106 - P9-19 */ "uart1_rtsn",
+  /* offset 108 - P9-20 */ "uart1_ctsn",
+  /* offset 110 - P9-26 */ "uart1_rxd",
+  /* offset 112 - P9-24 */ "uart1_txd",
+  /* offset 114 - P9-41 */ "xdma_event_intr1",
+  /* offset 116 - P8-19 */ "gpmc_ad8",
+  /* offset 118 - P8-13 */ "gpmc_ad9",
+  /* offset 120 - P8-14 */ "gpmc_ad10",
+  /* offset 122 - P8-17 */ "gpmc_ad12",
+  /* offset 124 - P9-11 */ "gpmc_wait0",
+  /* offset 126 - P9-13 */ "gpmc_wpn",
+  /* offset 128 - P8-25 */ "gpmc_ad0",
+  /* offset 130 - P8-24 */ "gpmc_ad1",
+  /* offset 132 - P8- 5 */ "gpmc_ad2",
+  /* offset 134 - P8- 6 */ "gpmc_ad3",
+  /* offset 136 - P8-23 */ "gpmc_ad4",
+  /* offset 138 - P8-22 */ "gpmc_ad5",
+  /* offset 140 - P8- 3 */ "gpmc_ad6",
+  /* offset 142 - P8- 4 */ "gpmc_ad7",
+  /* offset 144 - P8-12 */ "gpmc_ad12",
+  /* offset 146 - P8-11 */ "gpmc_ad13",
+  /* offset 148 - P8-16 */ "gpmc_ad14",
+  /* offset 150 - P8-15 */ "gpmc_ad15",
+  /* offset 152 - P9-15 */ "gpmc_a0",
+  /* offset 154 - P9-23 */ "gpmc_a1",
+  /* offset 156 - P9-14 */ "gpmc_a2",
+  /* offset 158 - P9-16 */ "gpmc_a3",
+  /* offset 160 - P9-12 */ "gpmc_be1n",
+  /* offset 162 - P8-26 */ "gpmc_csn0",
+  /* offset 164 - P8-21 */ "gpmc_csn1",
+  /* offset 166 - P8-20 */ "gpmc_csn2",
+  /* offset 168 - P8-18 */ "gpmc_clk",
+  /* offset 170 - P8-7  */ "gpmc_advn_ale",
+  /* offset 172 - P8-9  */ "gpmc_ben0_cle",
+  /* offset 174 - P8-10 */ "gpmc_wen",
+  /* offset 176 - P8-8  */ "gpmc_csn3",
+  /* offset 178 - P8-45 */ "lcd_data0",
+  /* offset 180 - P8-46 */ "lcd_data1",
+  /* offset 182 - P8-43 */ "lcd_data2",
+  /* offset 184 - P8-44 */ "lcd_data3",
+  /* offset 186 - P8-41 */ "lcd_data4",
+  /* offset 188 - P8-42 */ "lcd_data5",
+  /* offset 190 - P8-39 */ "lcd_data6",
+  /* offset 192 - P8-40 */ "lcd_data7",
+  /* offset 194 - P8-37 */ "lcd_data8",
+  /* offset 196 - P8-38 */ "lcd_data9",
+  /* offset 198 - P8-36 */ "lcd_data10",
+  /* offset 200 - P8-34 */ "lcd_data11",
+  /* offset 202 - P8-27 */ "lcd_vsync",
+  /* offset 204 - P8-29 */ "lcd_hsync",
+  /* offset 206 - P8-28 */ "lcd_pclk",
+  /* offset 208 - P8-30 */ "lcd_ac_bias_en",
+  /* offset 210 - P9-29 */ "mcasp0_fsx",
+  /* offset 212 - P9-30 */ "mcasp0_axr0",
+  /* offset 214 - P9-28 */ "mcasp0_ahclkr",
+  /* offset 216 - P9-27 */ "mcasp0_fsr",
+  /* offset 218 - P9-31 */ "mcasp0_aclkx",
+  /* offset 220 - P9-25 */ "mcasp0_ahclkx",
+  /* offset 222 - P9-39 */ "ain0",
+  /* offset 224 - P9-40 */ "ain1",
+  /* offset 226 - P9-37 */ "ain2",
+  /* offset 228 - P9-38 */ "ain3",
+  /* offset 230 - P9-33 */ "ain4",
+  /* offset 232 - P9-36 */ "ain5",
+  /* offset 234 - P9-35 */ "ain6",
+};
+
+#define BIG_ENDIAN_16( i) ( ((i & 255) << 8) | ((i >> 8) & 255) )
+#define NR_ITEMS( x) (sizeof( (x)) / sizeof( *(x)))
+
+extern int am33xx_mux_get_entry( int index, struct omap_mux** mux);
+
+typedef union {
+/*
+  From SRM RevA5.0.1:
+  Bit 15     Pin is used or not: 0=Unused by Cape 1=Used by Cape
+  Bit 14-13  Pin Direction: 10=Output 01=Input 11=BDIR
+  Bit 12-7   Reserved
+  Bit 6	     Slew Rate: 0=Fast 1=Slow
+  Bit 5	     Rx Enable: 0=Disabled 1=Enabled
+  Bit 4	     Pull Up/Dn Select: 0=Pulldown 1=PullUp
+  Bit 3	     Pull Up/DN enabled: 0=Enabled 1=Disabled
+  Bit 2-0    Mux Mode Selection: Mode 0-7
+*/
+	struct {
+		uint16_t    mux		    : 3;
+		uint16_t    pull_enable	    : 1;
+		uint16_t    pull_up	    : 1;
+		uint16_t    rx_enable	    : 1;
+		uint16_t    slew_rate	    : 1;
+		uint16_t    reserved	    : 6;
+		uint16_t    direction	    : 2;
+		uint16_t    used	    : 1;
+	};
+	uint16_t      value;
+} pin_def;
+
+#define DEBUG_EEPROM_CONFIG 0
+
+static int bone_io_get_mux_setting( pin_def setting)
+{
+	int pin_setting;
+
+	switch (setting.direction) {
+	case 1:
+	/* input */
+		if (setting.pull_enable) {
+			if (setting.pull_up) {
+				pin_setting = AM33XX_PIN_INPUT_PULLUP;
+			} else {
+				pin_setting = AM33XX_PIN_INPUT_PULLDOWN;
+			}
+		} else {
+			pin_setting = AM33XX_PIN_INPUT;
+		}
+		if (!setting.rx_enable) {
+			pr_debug( "  pin is set as input but the receiver is not enabled!\n");
+		}
+		break;
+	case 2:
+	/* output */
+		pin_setting = AM33XX_PIN_OUTPUT;
+		break;
+	case 3:
+	/* bi-dir */
+	default:
+	/* reserved */
+		pr_debug( "  pin ignored because it uses an unsupported mode: 0x%04x\n",
+			setting.direction);
+		return -1;
+	}
+	pr_debug("  pin is configured as %s\n",
+		(pin_setting & AM33XX_PIN_INPUT) ? "input" : "output");
+	switch (setting.mux) {
+	case 0: pin_setting |= OMAP_MUX_MODE0; break;
+	case 1: pin_setting |= OMAP_MUX_MODE1; break;
+	case 2: pin_setting |= OMAP_MUX_MODE2; break;
+	case 3: pin_setting |= OMAP_MUX_MODE3; break;
+	case 4: pin_setting |= OMAP_MUX_MODE4; break;
+	case 5: pin_setting |= OMAP_MUX_MODE5; break;
+	case 6: pin_setting |= OMAP_MUX_MODE6; break;
+	case 7: pin_setting |= OMAP_MUX_MODE7; break;
+	}
+	return pin_setting;
+}
+
+static struct omap_mux* bone_io_pin_lookup( const char* pin_name)
+{
+	int index = 0;
+	struct omap_mux* mux;
+
+	for (;;) {
+		if (am33xx_mux_get_entry( index, &mux) < 0) {
+			/* no more entries */
+			pr_debug( "   configuration error, pin '%s' not found in mux database\n",
+				pin_name);
+			return NULL;
+		}
+		if (mux != NULL &&
+		    mux->muxnames[ 0] != NULL &&
+		    strcmp( mux->muxnames[ 0], pin_name) == 0)
+		{
+			/* entry found */
+			pr_debug( "   found pin '%s' at index %d in mux database'\n",
+				pin_name, index);
+			return mux;
+		}
+		++index;
+	}
+}
+
+static int bone_io_config_pin( const char* pin_name, pin_def eeprom_setting)
+{
+	struct omap_mux* mux;
+	char* signal_name;
+	int pin_setting = bone_io_get_mux_setting( eeprom_setting);
+	int l1, l2;
+	char full_name[ 50];
+
+	if (pin_setting < 0) {
+		return -1;
+	}
+
+	mux = bone_io_pin_lookup( pin_name);
+
+	if (mux == NULL) {
+		return -1;
+	}
+
+	signal_name = mux->muxnames[ eeprom_setting.mux];
+
+	if (signal_name == NULL) {
+		pr_debug( "    Configuration error, no signal found for pin '%s' in mode %d\n",
+			pin_name, eeprom_setting.mux);
+		return -1;
+	}
+	pr_debug( "    setting pin '%s' to signal '%s'\n",
+		 pin_name, signal_name);
+	l1 = strlen( pin_name);
+	l2 = strlen( signal_name);
+
+	if (l1 + 1 + l2 + 1 > sizeof( full_name)) {
+		pr_debug( "    Internal error, combined signal name too long\n");
+		return -1;
+	} else {
+		memcpy( full_name, pin_name, l1);
+		full_name[ l1] = '.';
+		memcpy( full_name + l1 + 1, signal_name, l2);
+		full_name[ l1 + 1 + l2] = '\0';
+		if (omap_mux_init_signal( full_name, pin_setting) < 0) {
+			return -1;
+		}
+		pr_debug( "	mux '%s' was set to mode 0x%04x\n",
+			 full_name, pin_setting);
+	}
+	// return 0 for input, 1 for output
+	return (pin_setting & AM33XX_PIN_INPUT) ? 0 : 1;
+}
+
+#define RULER( x) \
+	do { \
+		char* p = status; \
+		int i = 0; \
+		int cnt = x; \
+		status[ cnt] = '\0'; \
+		while (cnt--) { \
+			if (++i == 10) { \
+				*p++ = '+'; \
+				i = 0; \
+			} else { \
+				*p++ = '-'; \
+			} \
+		} \
+		pr_info( "+%s+\n", status); \
+	} while (0)
+
+static int bone_io_config_from_cape_eeprom( void)
+{
+	int i;
+	int cnt = BIG_ENDIAN_16( cape_config.numpins);
+	u16* pmuxdata;
+	char status[ NR_ITEMS( cape_config.muxdata) + 1];
+	char revision[ NR_ITEMS( cape_config.format_revision) + 1];
+
+	strncpy( revision, cape_config.format_revision, NR_ITEMS( revision) - 1);
+	revision[ NR_ITEMS( revision) - 1] = '\0';
+	if (strcmp( revision, "A0") != 0) {
+		pr_warn( "BeagleBone cape: configuration revision '%s' is not supported\n",
+			revision);
+		return -1;
+	}
+
+	// Workaround for capes that have encoded this as ASCII
+	if (cnt > 256) {
+		pr_info( "BeagleBone cape: workaround for bad 'numpins' setting\n");
+		cnt = (cape_config.numpins & 255) - '0';
+		cnt = 10 * cnt + ((cape_config.numpins >> 8) & 255) - '0';
+	}
+	pr_info( "BeagleBone cape: revision %s format, configuring %2d out of %2d signals:\n",
+		revision, cnt, NR_ITEMS( cape_config.muxdata));
+	RULER( NR_ITEMS( cape_config.muxdata));
+	for (i = 0, pmuxdata = cape_config.muxdata ; i < NR_ITEMS( cape_config.muxdata) ; ++i, ++pmuxdata) {
+		const char* pin_name = cape_pins[ i];
+		pin_def pin_setting = { .value = BIG_ENDIAN_16( *pmuxdata) };
+
+		// Detect broken I2C configuration to prevent bus hangup!
+		if (i >= 9 && i <= 10) {
+			status[ i] = '-';
+		} else if (pin_setting.used) {
+			switch (bone_io_config_pin( pin_name, pin_setting)) {
+			case 0:	 status[ i] = 'i'; break;
+			case 1:	 status[ i] = 'o'; break;
+			default: status[ i] = '#'; break;
+			}
+		} else {
+			status[ i] = ' ';
+		}
+	}
+	status[ NR_ITEMS( cape_config.muxdata)] = '\0';
+	pr_info( "|%s|\n", status);
+	RULER( NR_ITEMS( cape_config.muxdata));
+	return 0;
+}
+
 static void beaglebone_cape_setup(struct memory_accessor *mem_acc, void *context)
 {
-	capecount++;
 	int ret;
 	char tmp[32];
 	char name[32];
 	char version[4];
 	char manufacturer[32];
 
+	capecount++;
 	/* get cape specific data */
 	ret = mem_acc->read(mem_acc, (char *)&cape_config, 0, sizeof(cape_config));
 	if (ret != sizeof(cape_config)) {
@@ -2215,6 +2514,12 @@ static void beaglebone_cape_setup(struct memory_accessor *mem_acc, void *context
 	snprintf(tmp, sizeof(cape_config.partnumber) + 1, "%s", cape_config.partnumber);
 	pr_info("BeagleBone cape partnumber: %s\n", tmp);   
 
+	if (!strncmp( "BEBOPR", cape_config.name, 6)) {
+		pr_info( "BeagleBone cape: initializing BEBOPR cape\n");
+		bone_io_config_from_cape_eeprom();
+		return;	// if configured from eeprom, skip all other initialization
+	}
+
 	if (!strncmp("BB-BONE-DVID-01", cape_config.partnumber, 15)) {
 			pr_info("BeagleBone cape: initializing DVI cape\n");
 			dvi_init(0,0);
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index e1cc75d1a57ac0..193259a4d408eb 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -522,41 +522,57 @@ static inline void omap_mux_decode(struct seq_file *s, u16 val)
 	i++;
 	flags[i] = mode;
 
-	OMAP_MUX_TEST_FLAG(val, OMAP_PIN_OFF_WAKEUPENABLE);
-	if (val & OMAP_OFF_EN) {
-		if (!(val & OMAP_OFFOUT_EN)) {
-			if (!(val & OMAP_OFF_PULL_UP)) {
-				OMAP_MUX_TEST_FLAG(val,
-					OMAP_PIN_OFF_INPUT_PULLDOWN);
+	if (cpu_is_am33xx()) {
+		// For compatibility with existing programs, the OMAP_ prefix
+		// is used instead of the more correctly AM33X_ one.
+		if (val & AM33XX_INPUT_EN) {
+			if (val & AM33XX_PULL_DISA) {
+				flags[ ++i] = "OMAP_PIN_INPUT";
+			} else if (val & AM33XX_PULL_UP) {
+				flags[ ++i] = "OMAP_PIN_INPUT_PULLUP";
 			} else {
-				OMAP_MUX_TEST_FLAG(val,
-					OMAP_PIN_OFF_INPUT_PULLUP);
+				flags[ ++i] = "OMAP_PIN_INPUT_PULLDOWN";
 			}
 		} else {
-			if (!(val & OMAP_OFFOUT_VAL)) {
-				OMAP_MUX_TEST_FLAG(val,
-					OMAP_PIN_OFF_OUTPUT_LOW);
+			flags[ ++i] = "OMAP_PIN_OUTPUT";
+		}
+	} else {
+		OMAP_MUX_TEST_FLAG(val, OMAP_PIN_OFF_WAKEUPENABLE);
+		if (val & OMAP_OFF_EN) {
+			if (!(val & OMAP_OFFOUT_EN)) {
+				if (!(val & OMAP_OFF_PULL_UP)) {
+					OMAP_MUX_TEST_FLAG(val,
+							OMAP_PIN_OFF_INPUT_PULLDOWN);
+				} else {
+					OMAP_MUX_TEST_FLAG(val,
+							OMAP_PIN_OFF_INPUT_PULLUP);
+				}
 			} else {
-				OMAP_MUX_TEST_FLAG(val,
-					OMAP_PIN_OFF_OUTPUT_HIGH);
+				if (!(val & OMAP_OFFOUT_VAL)) {
+					OMAP_MUX_TEST_FLAG(val,
+							OMAP_PIN_OFF_OUTPUT_LOW);
+				} else {
+					OMAP_MUX_TEST_FLAG(val,
+							OMAP_PIN_OFF_OUTPUT_HIGH);
+				}
 			}
 		}
-	}
 
-	if (val & OMAP_INPUT_EN) {
-		if (val & OMAP_PULL_ENA) {
-			if (!(val & OMAP_PULL_UP)) {
-				OMAP_MUX_TEST_FLAG(val,
-					OMAP_PIN_INPUT_PULLDOWN);
+		if (val & OMAP_INPUT_EN) {
+			if (val & OMAP_PULL_ENA) {
+				if (!(val & OMAP_PULL_UP)) {
+					OMAP_MUX_TEST_FLAG(val,
+							OMAP_PIN_INPUT_PULLDOWN);
+				} else {
+					OMAP_MUX_TEST_FLAG(val, OMAP_PIN_INPUT_PULLUP);
+				}
 			} else {
-				OMAP_MUX_TEST_FLAG(val, OMAP_PIN_INPUT_PULLUP);
+				OMAP_MUX_TEST_FLAG(val, OMAP_PIN_INPUT);
 			}
 		} else {
-			OMAP_MUX_TEST_FLAG(val, OMAP_PIN_INPUT);
+			i++;
+			flags[i] = "OMAP_PIN_OUTPUT";
 		}
-	} else {
-		i++;
-		flags[i] = "OMAP_PIN_OUTPUT";
 	}
 
 	do {
diff --git a/arch/arm/mach-omap2/mux33xx.c b/arch/arm/mach-omap2/mux33xx.c
index 25dcedbff79e50..43c89893c8e79e 100644
--- a/arch/arm/mach-omap2/mux33xx.c
+++ b/arch/arm/mach-omap2/mux33xx.c
@@ -28,82 +28,87 @@
 }
 
 /* AM33XX pin mux super set */
+/* 20120513 - SJL added a lot of missing signals using datasheet rev. C.
+ *            Converted all names to lower case, except for the A and B
+ *            channel suffixes, as that seems to be the rule.
+ *            Marked lines with completed spec by leading empty comment.
+ */
 static struct omap_mux __initdata am33xx_muxmodes[] = {
-	_AM33XX_MUXENTRY(GPMC_AD0, 0,
+/**/	_AM33XX_MUXENTRY(GPMC_AD0, 0,
 		"gpmc_ad0", "mmc1_dat0", NULL, NULL,
 		NULL, NULL, NULL, "gpio1_0"),
-	_AM33XX_MUXENTRY(GPMC_AD1, 0,
+/**/	_AM33XX_MUXENTRY(GPMC_AD1, 0,
 		"gpmc_ad1", "mmc1_dat1", NULL, NULL,
 		NULL, NULL, NULL, "gpio1_1"),
-	_AM33XX_MUXENTRY(GPMC_AD2, 0,
+/**/	_AM33XX_MUXENTRY(GPMC_AD2, 0,
 		"gpmc_ad2", "mmc1_dat2", NULL, NULL,
 		NULL, NULL, NULL, "gpio1_2"),
-	_AM33XX_MUXENTRY(GPMC_AD3, 0,
+/**/	_AM33XX_MUXENTRY(GPMC_AD3, 0,
 		"gpmc_ad3", "mmc1_dat3", NULL, NULL,
 		NULL, NULL, NULL, "gpio1_3"),
-	_AM33XX_MUXENTRY(GPMC_AD4, 0,
+/**/	_AM33XX_MUXENTRY(GPMC_AD4, 0,
 		"gpmc_ad4", "mmc1_dat4", NULL, NULL,
 		NULL, NULL, NULL, "gpio1_4"),
-	_AM33XX_MUXENTRY(GPMC_AD5, 0,
+/**/	_AM33XX_MUXENTRY(GPMC_AD5, 0,
 		"gpmc_ad5", "mmc1_dat5", NULL, NULL,
 		NULL, NULL, NULL, "gpio1_5"),
-	_AM33XX_MUXENTRY(GPMC_AD6, 0,
+/**/	_AM33XX_MUXENTRY(GPMC_AD6, 0,
 		"gpmc_ad6", "mmc1_dat6", NULL, NULL,
 		NULL, NULL, NULL, "gpio1_6"),
-	_AM33XX_MUXENTRY(GPMC_AD7, 0,
+/**/	_AM33XX_MUXENTRY(GPMC_AD7, 0,
 		"gpmc_ad7", "mmc1_dat7", NULL, NULL,
 		NULL, NULL, NULL, "gpio1_7"),
-	_AM33XX_MUXENTRY(GPMC_AD8, 0,
-		"gpmc_ad8", "lcd_data16", "mmc1_dat0", "mmc2_dat4",
-		NULL, NULL, NULL, "gpio0_22"),
-	_AM33XX_MUXENTRY(GPMC_AD9, 0,
-		"gpmc_ad9", "lcd_data17", "mmc1_dat1", "mmc2_dat5",
-		"ehrpwm2B", NULL, NULL, "gpio0_23"),
-	_AM33XX_MUXENTRY(GPMC_AD10, 0,
-		"gpmc_ad10", "lcd_data18", "mmc1_dat2", "mmc2_dat6",
-		NULL, NULL, NULL, "gpio0_26"),
-	_AM33XX_MUXENTRY(GPMC_AD11, 0,
-		"gpmc_ad11", "lcd_data19", "mmc1_dat3", "mmc2_dat7",
-		NULL, NULL, NULL, "gpio0_27"),
-	_AM33XX_MUXENTRY(GPMC_AD12, 0,
-		"gpmc_ad12", "lcd_data20", "mmc1_dat4", "mmc2_dat0",
-		NULL, NULL, NULL, "gpio1_12"),
-	_AM33XX_MUXENTRY(GPMC_AD13, 0,
-		"gpmc_ad13", "lcd_data21", "mmc1_dat5", "mmc2_dat1",
-		NULL, NULL, NULL, "gpio1_13"),
-	_AM33XX_MUXENTRY(GPMC_AD14, 0,
-		"gpmc_ad14", "lcd_data22", "mmc1_dat6", "mmc2_dat2",
-		NULL, NULL, NULL, "gpio1_14"),
-	_AM33XX_MUXENTRY(GPMC_AD15, 0,
-		"gpmc_ad15", "lcd_data23", "mmc1_dat7", "mmc2_dat3",
-		NULL, NULL, NULL, "gpio1_15"),
-	_AM33XX_MUXENTRY(GPMC_A0, 0,
-		"gpmc_a0", "mii2_txen", "rgmii2_tctl", "rmii2_txen",
-		NULL, NULL, NULL, "gpio1_16"),
-	_AM33XX_MUXENTRY(GPMC_A1, 0,
-		"gpmc_a1", "mii2_rxdv", "rgmii2_rctl", "mmc2_dat0",
-		NULL, NULL, NULL, "gpio1_17"),
-	_AM33XX_MUXENTRY(GPMC_A2, 0,
-		"gpmc_a2", "mii2_txd3", "rgmii2_td3", "mmc2_dat1",
-		NULL, NULL, "ehrpwm1A", "gpio1_18"),
-	_AM33XX_MUXENTRY(GPMC_A3, 0,
-		"gpmc_a3", "mii2_txd2", "rgmii2_td2", "mmc2_dat2",
-		NULL, NULL, NULL, "gpio1_19"),
-	_AM33XX_MUXENTRY(GPMC_A4, 0,
-		"gpmc_a4", "mii2_txd1", "rgmii2_td1", "rmii2_txd1",
-		"gpmc_a20", NULL, NULL, "gpio1_20"),
-	_AM33XX_MUXENTRY(GPMC_A5, 0,
-		"gpmc_a5", "mii2_txd0", "rgmii2_td0", "rmii2_txd0",
-		"gpmc_a21", NULL, NULL, "gpio1_21"),
-	_AM33XX_MUXENTRY(GPMC_A6, 0,
-		"gpmc_a6", "mii2_txclk", "rgmii2_tclk", "mmc2_dat4",
-		"gpmc_a22", NULL, NULL, "gpio1_22"),
-	_AM33XX_MUXENTRY(GPMC_A7, 0,
-		"gpmc_a7", "mii2_rxclk", "rgmii2_rclk", "mmc2_dat5",
-		NULL, NULL, NULL, "gpio1_23"),
-	_AM33XX_MUXENTRY(GPMC_A8, 0,
-		"gpmc_a8", "mii2_rxd3", "rgmii2_rd3", "mmc2_dat6",
-		NULL, NULL, "mcasp0_aclkx", "gpio1_24"),
+/**/	_AM33XX_MUXENTRY(GPMC_AD8, 0,
+		"gpmc_ad8", "lcd_data23", "mmc1_dat0", "mmc2_dat4",
+		"ehrpwm2A", "pr1_mii_mt0_clk", NULL, "gpio0_22"),
+/**/	_AM33XX_MUXENTRY(GPMC_AD9, 0,
+		"gpmc_ad9", "lcd_data22", "mmc1_dat1", "mmc2_dat5",
+		"ehrpwm2B", "pr1_mii0_col", NULL, "gpio0_23"),
+/**/	_AM33XX_MUXENTRY(GPMC_AD10, 0,
+		"gpmc_ad10", "lcd_data21", "mmc1_dat2", "mmc2_dat6",
+		"ehrpwm2_tripzone_input", "pr1_mii0_txen", NULL, "gpio0_26"),
+/**/	_AM33XX_MUXENTRY(GPMC_AD11, 0,
+		"gpmc_ad11", "lcd_data20", "mmc1_dat3", "mmc2_dat7",
+		"ehrpwm0_synco", "pr1_mii0_txd3", NULL, "gpio0_27"),
+/**/	_AM33XX_MUXENTRY(GPMC_AD12, 0,
+		"gpmc_ad12", "lcd_data19", "mmc1_dat4", "mmc2_dat0",
+		"eqep2a_in", "pr1_mii0_txd2", "pr1_pru0_pru_r30_14", "gpio1_12"),
+/**/	_AM33XX_MUXENTRY(GPMC_AD13, 0,
+		"gpmc_ad13", "lcd_data18", "mmc1_dat5", "mmc2_dat1",
+		"eqep2B_in", "pr1_mii0_txd", "pr1_pru0_pru_r30_15", "gpio1_13"),
+/**/	_AM33XX_MUXENTRY(GPMC_AD14, 0,
+		"gpmc_ad14", "lcd_data17", "mmc1_dat6", "mmc2_dat2",
+		"eqep2_index", "pr1_mii0_txd0", "pr1_pru0_pru_r31_14", "gpio1_14"),
+/**/	_AM33XX_MUXENTRY(GPMC_AD15, 0,
+		"gpmc_ad15", "lcd_data16", "mmc1_dat7", "mmc2_dat3",
+		"eqep2_strobe", "pr1_ecap0_ecap_capin_apwm_o", "pr1_pru0_pru_r31_15", "gpio1_15"),
+/**/	_AM33XX_MUXENTRY(GPMC_A0, 0,
+		"gpmc_a0", "gmii2_txen", "rgmii2_tctl", "rmii2_txen",
+		"gpmc_a16", "pr1_mii_mt1_clk", "ehrpwm1_tripzone_input", "gpio1_16"),
+/**/	_AM33XX_MUXENTRY(GPMC_A1, 0,
+		"gpmc_a1", "gmii2_rxdv", "rgmii2_rctl", "mmc2_dat0",
+		"gpmc_a17", "pr1_mii1_txd3", "ehrpwm0_synco", "gpio1_17"),
+/**/	_AM33XX_MUXENTRY(GPMC_A2, 0,
+		"gpmc_a2", "gmii2_txd3", "rgmii2_td3", "mmc2_dat1",
+		"gpmc_a18", "pr1_mii1_txd2", "ehrpwm1A", "gpio1_18"),
+/**/	_AM33XX_MUXENTRY(GPMC_A3, 0,
+		"gpmc_a3", "gmii2_txd2", "rgmii2_td2", "mmc2_dat2",
+		"gpmc_a19", "pr1_mii1_txd1", "ehrpwm1B", "gpio1_19"),
+/**/	_AM33XX_MUXENTRY(GPMC_A4, 0,
+		"gpmc_a4", "gmii2_txd1", "rgmii2_td1", "rmii2_txd1",
+		"gpmc_a20", "pr1_mii1_txd0", "eqep1a_in", "gpio1_20"),
+/**/	_AM33XX_MUXENTRY(GPMC_A5, 0,
+		"gpmc_a5", "gmii2_txd0", "rgmii2_td0", "rmii2_txd0",
+		"gpmc_a21", "pr1_mii1_rxd3", "eqep1b_in", "gpio1_21"),
+/**/	_AM33XX_MUXENTRY(GPMC_A6, 0,
+		"gpmc_a6", "gmii2_txclk", "rgmii2_tclk", "mmc2_dat4",
+		"gpmc_a22", "pr1_mii1_rxd2", "eqep1_index", "gpio1_22"),
+/**/	_AM33XX_MUXENTRY(GPMC_A7, 0,
+		"gpmc_a7", "gmii2_rxclk", "rgmii2_rclk", "mmc2_dat5",
+		"gpmc_a23", "pr1_mii1_rxd1", "eqep1_strobe", "gpio1_23"),
+/**/	_AM33XX_MUXENTRY(GPMC_A8, 0,
+		"gpmc_a8", "gmii2_rxd3", "rgmii2_rd3", "mmc2_dat6",
+		"gpmc_a24", "pr1_mii1_rxd0", "mcasp0_aclkx", "gpio1_24"),
 	_AM33XX_MUXENTRY(GPMC_A9, 0,
 		"gpmc_a9", "mii2_rxd2", "rgmii2_rd2", "mmc2_dat7",
 		NULL, NULL, "mcasp0_fsx", "gpio1_25"),
@@ -122,18 +127,18 @@ static struct omap_mux __initdata am33xx_muxmodes[] = {
 	_AM33XX_MUXENTRY(GPMC_BEN1, 0,
 		"gpmc_ben1", "mii2_col", NULL, "mmc2_dat3",
 		NULL, NULL, "mcasp0_aclkr", "gpio1_28"),
-	_AM33XX_MUXENTRY(GPMC_CSN0, 0,
+/**/	_AM33XX_MUXENTRY(GPMC_CSN0, 0,
 		"gpmc_csn0", NULL, NULL, NULL,
 		NULL, NULL, NULL, "gpio1_29"),
-	_AM33XX_MUXENTRY(GPMC_CSN1, 0,
-		"gpmc_csn1", NULL, "mmc1_clk", NULL,
-		NULL, NULL, NULL, "gpio1_30"),
-	_AM33XX_MUXENTRY(GPMC_CSN2, 0,
-		"gpmc_csn2", NULL, "mmc1_cmd", NULL,
-		NULL, NULL, NULL, "gpio1_31"),
-	_AM33XX_MUXENTRY(GPMC_CSN3, 0,
+/**/	_AM33XX_MUXENTRY(GPMC_CSN1, 0,
+		"gpmc_csn1", "gpmc_clk", "mmc1_clk", "pr1_edio_data_in6",
+		"pr1_edio_data_out6", "pr1_pru1_pru_r30_12", "pr1_pru1_pru_r31_12", "gpio1_30"),
+/**/	_AM33XX_MUXENTRY(GPMC_CSN2, 0,
+		"gpmc_csn2", "gpmc_be1n", "mmc1_cmd", "pr1_edio_data_in7",
+		"pr1_edio_data_out7", "pr1_pru1_pru_r30_13", "pr1_pru1_pru_r31_13", "gpio1_31"),
+/**/	_AM33XX_MUXENTRY(GPMC_CSN3, 0,
 		"gpmc_csn3", NULL, NULL, "mmc2_cmd",
-		NULL, NULL, NULL, "gpio2_0"),
+		"pr1_mii0_crs", "pr1_mdio_data", "EMU4", "gpio2_0"),
 	_AM33XX_MUXENTRY(GPMC_CLK, 0,
 		"gpmc_clk", "lcd_memory_clk_mux", NULL, "mmc2_clk",
 		NULL, NULL, "mcasp0_fsr", "gpio2_1"),
@@ -149,39 +154,39 @@ static struct omap_mux __initdata am33xx_muxmodes[] = {
 	_AM33XX_MUXENTRY(GPMC_BEN0_CLE, 0,
 		"gpmc_ben0_cle", NULL, NULL, NULL,
 		NULL, NULL, NULL, "gpio2_5"),
-	_AM33XX_MUXENTRY(LCD_DATA0, 0,
-		"lcd_data0", "gpmc_a0", NULL, NULL,
-		NULL, NULL, NULL, "gpio2_6"),
-	_AM33XX_MUXENTRY(LCD_DATA1, 0,
-		"lcd_data1", "gpmc_a1", NULL, NULL,
-		NULL, NULL, NULL, "gpio2_7"),
-	_AM33XX_MUXENTRY(LCD_DATA2, 0,
-		"lcd_data2", "gpmc_a2", NULL, NULL,
-		NULL, NULL, NULL, "gpio2_8"),
-	_AM33XX_MUXENTRY(LCD_DATA3, 0,
-		"lcd_data3", "gpmc_a3", NULL, NULL,
-		NULL, NULL, NULL, "gpio2_9"),
-	_AM33XX_MUXENTRY(LCD_DATA4, 0,
-		"lcd_data4", "gpmc_a4", NULL, NULL,
-		NULL, NULL, NULL, "gpio2_10"),
-	_AM33XX_MUXENTRY(LCD_DATA5, 0,
-		"lcd_data5", "gpmc_a5", NULL, NULL,
-		NULL, NULL, NULL, "gpio2_11"),
-	_AM33XX_MUXENTRY(LCD_DATA6, 0,
-		"lcd_data6", "gpmc_a6", NULL, NULL,
-		NULL, NULL, NULL, "gpio2_12"),
-	_AM33XX_MUXENTRY(LCD_DATA7, 0,
-		"lcd_data7", "gpmc_a7", NULL, NULL,
-		NULL, NULL, NULL, "gpio2_13"),
+/**/	_AM33XX_MUXENTRY(LCD_DATA0, 0,
+		"lcd_data0", "gpmc_a0", "pr1_mii_mt0_clk", "ehrpwm2A",
+		NULL, "pr1_pru1_pru_r30_0", "pr1_pru1_pru_r31_0", "gpio2_6"),
+/**/	_AM33XX_MUXENTRY(LCD_DATA1, 0,
+		"lcd_data1", "gpmc_a1", "pr1_mii0_txen", "ehrpwm2B",
+		NULL, "pr1_pru1_pru_r30_1", "pr1_pru1_pru_r31_1", "gpio2_7"),
+/**/	_AM33XX_MUXENTRY(LCD_DATA2, 0,
+		"lcd_data2", "gpmc_a2", "pr1_mii0_txd3", "ehrpwm2_tripzone_input",
+		NULL, "pr1_pru1_pru_r30_2", "pr1_pru1_pru_r31_2", "gpio2_8"),
+/**/	_AM33XX_MUXENTRY(LCD_DATA3, 0,
+		"lcd_data3", "gpmc_a3", "pr1_mii0_txd2","ehrpwm0_synco",
+		NULL, "pr1_pru1_pru_r30_3", "pr1_pru1_pru_r31_3", "gpio2_9"),
+/**/	_AM33XX_MUXENTRY(LCD_DATA4, 0,
+		"lcd_data4", "gpmc_a4", "pr1_mii0_txd1", "eQEP2A_in",
+		NULL, "pr1_pru1_pru_r30_4", "pr1_pru1_pru_r31_4", "gpio2_10"),
+/**/	_AM33XX_MUXENTRY(LCD_DATA5, 0,
+		"lcd_data5", "gpmc_a5", "pr1_mii0_txd0", "eqep2b_in",
+		NULL, "pr1_pru1_pru_r30_5", "pr1_pru1_pru_r31_5", "gpio2_11"),
+/**/	_AM33XX_MUXENTRY(LCD_DATA6, 0,
+		"lcd_data6", "gpmc_a6", "pr1_edio_data_in6", "eqep2_index",
+		"pr1_edio_data_out6", "pr1_pru1_pru_r30_6", "pr1_pru1_pru_r31_6", "gpio2_12"),
+/**/	_AM33XX_MUXENTRY(LCD_DATA7, 0,
+		"lcd_data7", "gpmc_a7", "pr1_edio_data_in7", "eqep2_strobe",
+		"pr1_pru1_pru_r30_7", "pr1_pru_pru1_r30_7", "pr1_pru1_pru_r31_7", "gpio2_13"),
 	_AM33XX_MUXENTRY(LCD_DATA8, 0,
 		"lcd_data8", "gpmc_a12", NULL, "mcasp0_aclkx",
 		NULL, NULL, "uart2_ctsn", "gpio2_14"),
 	_AM33XX_MUXENTRY(LCD_DATA9, 0,
 		"lcd_data9", "gpmc_a13", NULL, "mcasp0_fsx",
 		NULL, NULL, "uart2_rtsn", "gpio2_15"),
-	_AM33XX_MUXENTRY(LCD_DATA10, 0,
-		"lcd_data10", "gpmc_a14", NULL, "mcasp0_axr0",
-		NULL, NULL, NULL, "gpio2_16"),
+/**/	_AM33XX_MUXENTRY(LCD_DATA10, 0,
+		"lcd_data10", "gpmc_a14", "ehrpwm1A", "mcasp0_axr0",
+		"mcasp0_axr0", "pr1_mii0_rxd1", "uart3_ctsn", "gpio2_16"),
 	_AM33XX_MUXENTRY(LCD_DATA11, 0,
 		"lcd_data11", "gpmc_a15", NULL, "mcasp0_ahclkr",
 		"mcasp0_axr2", NULL, NULL, "gpio2_17"),
@@ -197,18 +202,18 @@ static struct omap_mux __initdata am33xx_muxmodes[] = {
 	_AM33XX_MUXENTRY(LCD_DATA15, 0,
 		"lcd_data15", "gpmc_a19", NULL, "mcasp0_ahclkx",
 		"mcasp0_axr3", NULL, NULL, "gpio0_11"),
-	_AM33XX_MUXENTRY(LCD_VSYNC, 0,
-		"lcd_vsync", NULL, NULL, NULL,
-		NULL, NULL, NULL, "gpio2_22"),
-	_AM33XX_MUXENTRY(LCD_HSYNC, 0,
-		"lcd_hsync", NULL, NULL, NULL,
-		NULL, NULL, NULL, "gpio2_23"),
-	_AM33XX_MUXENTRY(LCD_PCLK, 0,
-		"lcd_pclk", NULL, NULL, NULL,
-		NULL, NULL, NULL, "gpio2_24"),
-	_AM33XX_MUXENTRY(LCD_AC_BIAS_EN, 0,
-		"lcd_ac_bias_en", NULL, NULL, NULL,
-		NULL, NULL, NULL, "gpio2_25"),
+/**/	_AM33XX_MUXENTRY(LCD_VSYNC, 0,
+		"lcd_vsync", "gpmc_a8", NULL, "pr1_edio_data_in2",
+		"pr1_edio_data_out2", "pr1_pru1_pru_r30_8", "pr1_pru1_pru_r31_8", "gpio2_22"),
+/**/	_AM33XX_MUXENTRY(LCD_HSYNC, 0,
+		"lcd_hsync", "gpmc_a9", NULL, "pr1_edio_data_in3",
+		"pr1_edio_data_out3", "pr1_pru1_pru_r30_9", "pr1_pru1_pru_r31_9", "gpio2_23"),
+/**/	_AM33XX_MUXENTRY(LCD_PCLK, 0,
+		"lcd_pclk", "gpmc_a10", "pr1_mii0_crs", "pr1_edio_data_in4",
+		"pr1_edio_data_out4", "pr1_pru1_pru_r30_10", "pr1_pru1_pru_r31_10", "gpio2_24"),
+/**/	_AM33XX_MUXENTRY(LCD_AC_BIAS_EN, 0,
+		"lcd_ac_bias_en", "gpmc_a11", "pr1_mii1_crs", "pr1_edio_data_in5",
+		"pr1_edio_data_out5", "pr1_pru1_pru_r30_11", "pr1_pru1_pru_r31_11", "gpio2_25"),
 	_AM33XX_MUXENTRY(MMC0_DAT3, 0,
 		"mmc0_dat3", NULL, NULL, NULL,
 		NULL, NULL, NULL, "gpio2_26"),
@@ -296,9 +301,9 @@ static struct omap_mux __initdata am33xx_muxmodes[] = {
 	_AM33XX_MUXENTRY(SPI0_CS1, 0,
 		"spi0_cs1", "uart3_rxd", NULL, "mmc0_pow",
 		NULL, "mmc0_sdcd", NULL, "gpio0_6"),
-	_AM33XX_MUXENTRY(ECAP0_IN_PWM0_OUT, 0,
-		"ecap0_in_pwm0_out", "uart3_txd", "spi1_cs1", NULL,
-		"spi1_sclk", "mmc0_sdwp", NULL, "gpio0_7"),
+/**/	_AM33XX_MUXENTRY(ECAP0_IN_PWM0_OUT, 0,
+		"ecap0_in_pwm0_out", "uart3_txd", "spi1_cs1", "pr1_ecap0_ecap_capin_apwm_o",
+		"spi1_sclk", "mmc0_sdwp", "xdma_event_intr2", "gpio0_7"),
 	_AM33XX_MUXENTRY(UART0_CTSN, 0,
 		"uart0_ctsn", NULL, "d_can1_tx", "i2c1_sda",
 		"spi1_d0", NULL, NULL, "gpio1_8"),
@@ -389,11 +394,11 @@ static struct omap_mux __initdata am33xx_muxmodes[] = {
 	_AM33XX_MUXENTRY(TRSTN, 0,
 		NULL, NULL, NULL, NULL,
 		NULL, NULL, NULL, NULL),
-	_AM33XX_MUXENTRY(EMU0, 0,
-		NULL, NULL, NULL, NULL,
+/**/	_AM33XX_MUXENTRY(EMU0, 0,
+		"emu0", NULL, NULL, NULL,
 		NULL, NULL, NULL, "gpio3_7"),
-	_AM33XX_MUXENTRY(EMU1, 0,
-		NULL, NULL, NULL, NULL,
+/**/	_AM33XX_MUXENTRY(EMU1, 0,
+		"emu1", NULL, NULL, NULL,
 		NULL, NULL, NULL, "gpio3_8"),
 	_AM33XX_MUXENTRY(RTC_XTALIN, 0,
 		NULL, NULL, NULL, NULL,
@@ -572,34 +577,34 @@ static struct omap_mux __initdata am33xx_muxmodes[] = {
 	_AM33XX_MUXENTRY(DDR_VTP, 0,
 		NULL, NULL, NULL, NULL,
 		NULL, NULL, NULL, NULL),
-	_AM33XX_MUXENTRY(AIN0, 0,
+/**/	_AM33XX_MUXENTRY(AIN0, 0,
 		"ain0", NULL, NULL, NULL,
 		NULL, NULL, NULL, NULL),
-	_AM33XX_MUXENTRY(AIN1, 0,
+/**/	_AM33XX_MUXENTRY(AIN1, 0,
 		"ain1", NULL, NULL, NULL,
 		NULL, NULL, NULL, NULL),
-	_AM33XX_MUXENTRY(AIN2, 0,
+/**/	_AM33XX_MUXENTRY(AIN2, 0,
 		"ain2", NULL, NULL, NULL,
 		NULL, NULL, NULL, NULL),
-	_AM33XX_MUXENTRY(AIN3, 0,
+/**/	_AM33XX_MUXENTRY(AIN3, 0,
 		"ain3", NULL, NULL, NULL,
 		NULL, NULL, NULL, NULL),
-	_AM33XX_MUXENTRY(AIN4, 0,
+/**/	_AM33XX_MUXENTRY(AIN4, 0,
 		"ain4", NULL, NULL, NULL,
 		NULL, NULL, NULL, NULL),
-	_AM33XX_MUXENTRY(AIN5, 0,
+/**/	_AM33XX_MUXENTRY(AIN5, 0,
 		"ain5", NULL, NULL, NULL,
 		NULL, NULL, NULL, NULL),
-	_AM33XX_MUXENTRY(AIN6, 0,
+/**/	_AM33XX_MUXENTRY(AIN6, 0,
 		"ain6", NULL, NULL, NULL,
 		NULL, NULL, NULL, NULL),
-	_AM33XX_MUXENTRY(AIN7, 0,
+/**/	_AM33XX_MUXENTRY(AIN7, 0,
 		"ain7", NULL, NULL, NULL,
 		NULL, NULL, NULL, NULL),
-	_AM33XX_MUXENTRY(VREFP, 0,
+/**/	_AM33XX_MUXENTRY(VREFP, 0,
 		"vrefp", NULL, NULL, NULL,
 		NULL, NULL, NULL, NULL),
-	_AM33XX_MUXENTRY(VREFN, 0,
+/**/	_AM33XX_MUXENTRY(VREFN, 0,
 		"vrefn", NULL, NULL, NULL,
 		NULL, NULL, NULL, NULL),
 	{ .reg_offset = OMAP_MUX_TERMINATOR },
@@ -611,6 +616,20 @@ int __init am33xx_mux_init(struct omap_board_mux *board_subset)
 			AM33XX_CONTROL_PADCONF_MUX_SIZE, am33xx_muxmodes,
 			NULL, board_subset, NULL);
 }
+
+#define NR_ITEMS( x) (sizeof( (x)) / sizeof( *(x)))
+
+int am33xx_mux_get_entry( int index, struct omap_mux** mux)
+{
+  if (index >= 0 && index < NR_ITEMS( am33xx_muxmodes)) {
+    *mux = &am33xx_muxmodes[ index];
+    return 0;
+  } else {
+    *mux = NULL;
+    return -1;
+  }
+}
+
 #else
 int __init am33xx_mux_init(struct omap_board_mux *board_subset)
 {