-
Notifications
You must be signed in to change notification settings - Fork 10
/
z80.h
4050 lines (3587 loc) · 132 KB
/
z80.h
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
/* Z80 CPU Emulator.
https://github.com/kosarev/z80
Copyright (c) 2017 Ivan Kosarev <ivan@kosarev.info>
Published under the MIT license.
*/
#ifndef Z80_H
#define Z80_H
#include <cassert>
#include <climits>
#include <cstdint>
#include <cstdio>
#include <cstdlib>
#include <utility>
namespace z80 {
#if UINT_FAST8_MAX < UINT_MAX
typedef unsigned fast_u8;
#else
typedef uint_fast8_t fast_u8;
#endif
#if UINT_FAST16_MAX < UINT_MAX
typedef unsigned fast_u16;
#else
typedef uint_fast16_t fast_u16;
#endif
typedef uint_fast32_t fast_u32;
typedef uint_least8_t least_u8;
typedef uint_least16_t least_u16;
typedef uint_least32_t least_u32;
static inline void unused(...) {}
[[noreturn]] static inline void unreachable(const char *msg) {
#if !defined(NDEBUG)
std::fprintf(stderr, "%s\n", msg);
std::abort();
#elif defined(_MSC_VER)
__assume(0);
#else
__builtin_unreachable();
#endif
}
template<typename T>
static inline constexpr fast_u8 mask8(T n) {
return n & 0xff;
}
static inline constexpr fast_u16 mask16(fast_u16 n) {
return n & 0xffff;
}
static inline constexpr bool get_sign8(fast_u8 n) {
return (n & 0x80) != 0;
}
static inline constexpr fast_u8 add8(fast_u8 a, fast_u8 b) {
return mask8(a + b);
}
static inline constexpr fast_u8 sub8(fast_u8 a, fast_u8 b) {
return mask8(a - b);
}
static inline constexpr fast_u8 inc8(fast_u8 n) {
return add8(n, 1);
}
static inline constexpr fast_u8 dec8(fast_u8 n) {
return sub8(n, 1);
}
static inline constexpr fast_u8 rol8(fast_u8 n) {
return mask8((n << 1) | (n >> 7));
}
static inline constexpr fast_u8 ror8(fast_u8 n) {
return mask8((n >> 1) | (n << 7));
}
static inline constexpr fast_u8 neg8(fast_u8 n) {
return mask8(~n + 1);
}
static inline constexpr fast_u8 abs8(fast_u8 n) {
return !get_sign8(n) ? n : neg8(n);
}
static inline constexpr int sign_extend8(fast_u8 n) {
return !get_sign8(n) ? static_cast<int>(n) :
-static_cast<int>(neg8(n));
}
static inline constexpr fast_u8 get_low8(fast_u16 n) {
return mask8(static_cast<fast_u8>(n));
}
static inline constexpr fast_u8 get_high8(fast_u16 n) {
return mask8(static_cast<fast_u8>(n >> 8));
}
static inline constexpr fast_u16 make16(fast_u8 hi, fast_u8 lo) {
return (static_cast<fast_u16>(hi) << 8) | lo;
}
static inline constexpr fast_u16 add16(fast_u16 a, fast_u16 b) {
return mask16(a + b);
}
static inline constexpr fast_u16 sub16(fast_u16 a, fast_u16 b) {
return mask16(a - b);
}
static inline constexpr fast_u16 inc16(fast_u16 n) {
return add16(n, 1);
}
static inline constexpr fast_u16 dec16(fast_u16 n) {
return sub16(n, 1);
}
enum class reg { b, c, d, e, h, l, at_hl, a };
enum class regp { bc, de, hl, sp };
enum class regp2 { bc, de, hl, af };
enum class iregp { hl, ix, iy };
enum class alu { add, adc, sub, sbc, and_a, xor_a, or_a, cp };
enum class rot { rlc, rrc, rl, rr, sla, sra, sll, srl };
enum class block_ld { ldi, ldd, ldir, lddr };
enum class block_cp { cpi, cpd, cpir, cpdr };
enum class block_in { ini, ind, inir, indr };
enum class block_out { outi, outd, otir, otdr };
enum class condition { nz, z, nc, c, po, pe, p, m };
enum class z80_variant {
common,
cmos, // Newer chips.
};
// Entities for internal needs of the library.
class internals {
private:
// Returns false, but not earlier than on instantiation.
template<typename T> static constexpr bool get_false() { return false; }
template<typename B> class decoder_base;
template<typename B> class disasm_base;
template<typename B> class cpu_state_base;
template<typename B> class executor_base;
template<typename D> friend class root;
template<typename B> friend class i8080_decoder;
template<typename B> friend class z80_decoder;
template<typename D> friend class i8080_disasm;
template<typename D> friend class z80_disasm;
template<typename B> friend class i8080_state;
template<typename B> friend class z80_state;
template<typename B> friend class i8080_executor;
template<typename B> friend class z80_executor;
};
template<typename D>
class root {
public:
typedef D derived;
iregp on_get_iregp_kind() const { return iregp::hl; }
void on_set_iregp_kind(iregp r) { unused(r); }
fast_u8 on_get_b() const { return 0; }
void on_set_b(fast_u8 n) { unused(n); }
fast_u8 on_get_c() const { return 0; }
void on_set_c(fast_u8 n) { unused(n); }
fast_u8 on_get_d() const { return 0; }
void on_set_d(fast_u8 n) { unused(n); }
fast_u8 on_get_e() const { return 0; }
void on_set_e(fast_u8 n) { unused(n); }
fast_u8 on_get_h() const { return 0; }
void on_set_h(fast_u8 n) { unused(n); }
fast_u8 on_get_l() const { return 0; }
void on_set_l(fast_u8 n) { unused(n); }
fast_u8 on_get_a() const { return 0; }
void on_set_a(fast_u8 n) { unused(n); }
fast_u8 on_get_f() const { return 0; }
void on_set_f(fast_u8 n) { unused(n); }
fast_u8 on_get_ixh() const { return 0; }
void on_set_ixh(fast_u8 n) { unused(n); }
fast_u8 on_get_ixl() const { return 0; }
void on_set_ixl(fast_u8 n) { unused(n); }
fast_u8 on_get_iyh() const { return 0; }
void on_set_iyh(fast_u8 n) { unused(n); }
fast_u8 on_get_iyl() const { return 0; }
void on_set_iyl(fast_u8 n) { unused(n); }
fast_u8 on_get_i() const { return 0; }
void on_set_i(fast_u8 n) { unused(n); }
fast_u8 on_get_r() const { return 0; }
void on_set_r(fast_u8 n) { unused(n); }
fast_u16 on_get_pc() const { return 0; }
void on_set_pc(fast_u16 n) { unused(n); }
fast_u16 on_get_sp() const { return 0; }
void on_set_sp(fast_u16 n) { unused(n); }
fast_u16 on_get_wz() const { return 0; }
void on_set_wz(fast_u16 n) { unused(n); }
bool on_is_halted() const { return false; }
void on_set_is_halted(bool f) { unused(f); }
bool on_get_iff() const { return false; }
void on_set_iff(bool f) { unused(f); }
bool on_get_iff1() const { return false; }
void on_set_iff1(bool f) { unused(f); }
bool on_get_iff2() const { return false; }
void on_set_iff2(bool f) { unused(f); }
unsigned on_get_int_mode() const { return 0; }
void on_set_int_mode(unsigned mode) { unused(mode); }
void on_set_is_int_disabled(bool f) { unused(f); }
fast_u8 on_get_int_vector() { return 0xff; }
void set_i_on_ld(fast_u8 i) { self().on_set_i(i); }
fast_u16 get_pc_on_disp_read() { return self().on_get_pc(); }
void set_pc_on_disp_read(fast_u16 pc) { self().on_set_pc(pc); }
fast_u16 get_pc_on_block_instr() { return self().on_get_pc(); }
void set_pc_on_block_instr(fast_u16 pc) { self().on_set_pc(pc); }
void set_iff_on_di(bool iff) { self().on_set_iff(iff); }
void set_iff_on_ei(bool iff) { self().on_set_iff(iff); }
void set_iff1_on_di(bool f) { self().on_set_iff1(f); }
void set_iff1_on_ei(bool f) { self().on_set_iff1(f); }
void set_iff1_on_reti_retn(bool f) { self().on_set_iff1(f); }
void set_iff2_on_di(bool f) { self().on_set_iff2(f); }
void set_iff2_on_ei(bool f) { self().on_set_iff2(f); }
bool get_iff2_on_reti_retn() { return self().on_get_iff2(); }
fast_u16 on_get_bc() {
// Always get the low byte first.
fast_u8 l = self().on_get_c();
fast_u8 h = self().on_get_b();
return make16(h, l); }
void on_set_bc(fast_u16 n) {
// Always set the low byte first.
self().on_set_c(get_low8(n));
self().on_set_b(get_high8(n)); }
fast_u16 on_get_de() {
// Always get the low byte first.
fast_u8 l = self().on_get_e();
fast_u8 h = self().on_get_d();
return make16(h, l); }
void on_set_de(fast_u16 n) {
// Always set the low byte first.
self().on_set_e(get_low8(n));
self().on_set_d(get_high8(n)); }
fast_u16 on_get_hl() {
// Always get the low byte first.
fast_u8 l = self().on_get_l();
fast_u8 h = self().on_get_h();
return make16(h, l); }
void on_set_hl(fast_u16 n) {
// Always set the low byte first.
self().on_set_l(get_low8(n));
self().on_set_h(get_high8(n)); }
fast_u16 on_get_af() {
// Always get the low byte first.
fast_u8 f = self().on_get_f();
fast_u8 a = self().on_get_a();
return make16(a, f); }
void on_set_af(fast_u16 n) {
// Always set the low byte first.
self().on_set_f(get_low8(n));
self().on_set_a(get_high8(n)); }
fast_u16 on_get_ix() {
// Always get the low byte first.
fast_u8 l = self().on_get_ixl();
fast_u8 h = self().on_get_ixh();
return make16(h, l); }
void on_set_ix(fast_u16 ix) {
// Always set the low byte first.
self().on_set_ixl(get_low8(ix));
self().on_set_ixh(get_high8(ix)); }
fast_u16 on_get_iy() {
// Always get the low byte first.
fast_u8 l = self().on_get_iyl();
fast_u8 h = self().on_get_iyh();
return make16(h, l); }
void on_set_iy(fast_u16 iy) {
// Always set the low byte first.
self().on_set_iyl(get_low8(iy));
self().on_set_iyh(get_high8(iy)); }
fast_u16 on_get_ir() {
// Always get the low byte first.
fast_u8 l = self().on_get_r();
fast_u8 h = self().on_get_i();
return make16(h, l); }
fast_u8 on_get_reg(reg r) {
switch(r) {
case reg::b: return self().on_get_b();
case reg::c: return self().on_get_c();
case reg::d: return self().on_get_d();
case reg::e: return self().on_get_e();
case reg::at_hl: unreachable("Can't get (HL) value.");
case reg::a: return self().on_get_a();
case reg::h: return self().on_get_h();
case reg::l: return self().on_get_l();
}
unreachable("Unknown register.");
}
void on_set_reg(reg r, fast_u8 n) {
switch(r) {
case reg::b: return self().on_set_b(n);
case reg::c: return self().on_set_c(n);
case reg::d: return self().on_set_d(n);
case reg::e: return self().on_set_e(n);
case reg::at_hl: unreachable("Can't set (HL) value.");
case reg::a: return self().on_set_a(n);
case reg::h: return self().on_set_h(n);
case reg::l: return self().on_set_l(n);
}
unreachable("Unknown register.");
}
fast_u8 on_get_reg(reg r, iregp irp) {
switch(r) {
case reg::b: return self().on_get_b();
case reg::c: return self().on_get_c();
case reg::d: return self().on_get_d();
case reg::e: return self().on_get_e();
case reg::at_hl: unreachable("Can't get (HL) value.");
case reg::a: return self().on_get_a();
case reg::h:
switch(irp) {
case iregp::hl: return self().on_get_h();
case iregp::ix: return self().on_get_ixh();
case iregp::iy: return self().on_get_iyh();
}
break;
case reg::l:
switch(irp) {
case iregp::hl: return self().on_get_l();
case iregp::ix: return self().on_get_ixl();
case iregp::iy: return self().on_get_iyl();
}
break;
}
unreachable("Unknown register.");
}
void on_set_reg(reg r, iregp irp, fast_u8 n) {
switch(r) {
case reg::b: return self().on_set_b(n);
case reg::c: return self().on_set_c(n);
case reg::d: return self().on_set_d(n);
case reg::e: return self().on_set_e(n);
case reg::at_hl: unreachable("Can't set (HL) value.");
case reg::a: return self().on_set_a(n);
case reg::h:
switch(irp) {
case iregp::hl: return self().on_set_h(n);
case iregp::ix: return self().on_set_ixh(n);
case iregp::iy: return self().on_set_iyh(n);
}
break;
case reg::l:
switch(irp) {
case iregp::hl: return self().on_set_l(n);
case iregp::ix: return self().on_set_ixl(n);
case iregp::iy: return self().on_set_iyl(n);
}
break;
}
unreachable("Unknown register.");
}
fast_u16 on_get_iregp(iregp irp) {
switch(irp) {
case iregp::hl: return self().on_get_hl();
case iregp::ix: return self().on_get_ix();
case iregp::iy: return self().on_get_iy();
}
unreachable("Unknown index register.");
}
void on_set_iregp(iregp irp, fast_u16 nn) {
switch(irp) {
case iregp::hl: return self().on_set_hl(nn);
case iregp::ix: return self().on_set_ix(nn);
case iregp::iy: return self().on_set_iy(nn);
}
unreachable("Unknown index register.");
}
fast_u16 on_get_regp(regp rp) {
switch(rp) {
case regp::bc: return self().on_get_bc();
case regp::de: return self().on_get_de();
case regp::hl: return self().on_get_hl();
case regp::sp: return self().on_get_sp();
}
unreachable("Unknown register.");
}
void on_set_regp(regp rp, fast_u16 nn) {
switch(rp) {
case regp::bc: return self().on_set_bc(nn);
case regp::de: return self().on_set_de(nn);
case regp::hl: return self().on_set_hl(nn);
case regp::sp: return self().on_set_sp(nn);
}
unreachable("Unknown register.");
}
fast_u16 on_get_regp(regp rp, iregp irp) {
return rp == regp::hl ? self().on_get_iregp(irp) :
self().on_get_regp(rp);
}
void on_set_regp(regp rp, iregp irp, fast_u16 nn) {
return rp == regp::hl ? self().on_set_iregp(irp, nn) :
self().on_set_regp(rp, nn);
}
fast_u16 on_get_regp2(regp2 rp) {
switch(rp) {
case regp2::bc: return self().on_get_bc();
case regp2::de: return self().on_get_de();
case regp2::hl: return self().on_get_hl();
case regp2::af: return self().on_get_af();
}
unreachable("Unknown register.");
}
void on_set_regp2(regp2 rp, fast_u16 nn) {
switch(rp) {
case regp2::bc: return self().on_set_bc(nn);
case regp2::de: return self().on_set_de(nn);
case regp2::hl: return self().on_set_hl(nn);
case regp2::af: return self().on_set_af(nn);
}
unreachable("Unknown register.");
}
fast_u16 on_get_regp2(regp2 rp, iregp irp) {
return rp == regp2::hl ? self().on_get_iregp(irp) :
self().on_get_regp2(rp);
}
void on_set_regp2(regp2 rp, iregp irp, fast_u16 nn) {
return rp == regp2::hl ? self().on_set_iregp(irp, nn) :
self().on_set_regp2(rp, nn);
}
// No dummy implementations for the following handlers as
// being forgotten to be implemented, they would lead to
// problems that are hard to diagnose.
void on_ex_de_hl_regs() {
static_assert(internals::get_false<derived>(),
"on_ex_de_hl_regs() has to be implemented!"); }
void on_ex_af_alt_af_regs() {
static_assert(!derived::z80_enabled,
"on_ex_af_alt_af_regs() has to be implemented!"); }
void on_exx_regs() {
static_assert(!derived::z80_enabled,
"on_exx_regs() has to be implemented!"); }
fast_u8 on_read(fast_u16 addr) {
unused(addr);
return 0x00; }
void on_write(fast_u16 addr, fast_u8 n) {
unused(addr, n); }
// TODO: Should we provide separate 8-bit and 16-bit versions
// of these?
fast_u8 on_input(fast_u16 port) {
unused(port);
return 0xff; }
void on_output(fast_u16 port, fast_u8 n) {
unused(port, n); }
void on_tick(unsigned t) {
unused(t); }
void on_reset_decoder() {}
void on_reset_cpu(bool soft = false) {
unused(soft);
self().on_reset_decoder(); }
void on_reset_memory() {}
void on_reset(bool soft = false) {
self().on_reset_cpu(soft);
if (!soft)
self().on_reset_memory(); }
fast_u8 on_m1_fetch_cycle() {
fast_u8 n = self().on_fetch_cycle();
return n; }
void on_fetch_cycle_extra_1t() {
self().on_tick(1); }
void on_fetch_cycle_extra_2t() {
self().on_tick(2); }
void on_fetch_cycle_extra_3t() {
self().on_tick(3); }
fast_u8 on_read_cycle(fast_u16 addr) {
self().on_set_addr_bus(addr);
fast_u8 n = self().on_read(addr);
self().on_tick(2);
self().on_mreq_wait(addr);
self().on_tick(1);
return n; }
void on_read_cycle_extra_1t() {
self().on_tick(1); }
void on_read_cycle_extra_2t() {
self().on_tick(2); }
void on_write_cycle(fast_u16 addr, fast_u8 n) {
self().on_set_addr_bus(addr);
self().on_write(addr, n);
self().on_tick(2);
self().on_mreq_wait(addr);
self().on_tick(1); }
void on_write_cycle_extra_2t() {
self().on_tick(2); }
void on_3t_exec_cycle() {
self().on_tick(3); }
void on_4t_exec_cycle() {
self().on_tick(4); }
void on_5t_exec_cycle() {
self().on_tick(5); }
void on_mreq_wait(fast_u16 addr) {
unused(addr); }
void on_iorq_wait(fast_u16 port) {
unused(port); }
void on_ed_xnop(fast_u8 op) {
unused(op);
self().on_nop(); }
void on_xcall_nn(fast_u8 op, fast_u16 nn) {
unused(op);
self().on_call_nn(nn); }
void on_xim(fast_u8 op, fast_u8 mode) {
unused(op);
self().on_im(mode); }
void on_xjp_nn(fast_u16 nn) {
self().on_jp_nn(nn); }
void on_xneg(fast_u8 op) {
unused(op);
self().on_neg(); }
void on_xnop(fast_u8 op) {
unused(op);
self().on_nop(); }
void on_xret() {
self().on_ret(); }
void on_xretn(fast_u8 op) {
unused(op);
self().on_retn(); }
z80_variant on_get_z80_variant() {
return z80_variant::common; }
fast_u8 on_get_out_c_r_op() {
switch(self().on_get_z80_variant()) {
case z80_variant::common: return 0;
case z80_variant::cmos: return 0xff;
}
unreachable("Unknown Z80 variant."); }
protected:
const derived &self() const{ return static_cast<const derived&>(*this); }
derived &self() { return static_cast<derived&>(*this); }
};
template<typename B>
class z80_decoder_state : public B {
public:
using base = B;
z80_decoder_state() {}
iregp get_iregp_kind() const { return fields.irp; }
void set_iregp_kind(iregp r) { fields.irp = r; }
iregp on_get_iregp_kind() const { return get_iregp_kind(); }
void on_set_iregp_kind(iregp r) { set_iregp_kind(r); }
void on_reset_decoder() {
base::on_reset_decoder();
fields = state_fields();
}
private:
struct state_fields {
iregp irp = iregp::hl;
};
state_fields fields;
};
template<typename B>
class internals::decoder_base : public B {
public:
typedef B base;
void disable_int_on_index_prefix() {
self().on_set_is_int_disabled(true); }
void on_instr_prefix(iregp irp) {
self().on_set_iregp_kind(irp);
self().disable_int_on_index_prefix(); }
protected:
bool is_hl_iregp() {
return self().on_get_iregp_kind() == iregp::hl;
}
fast_u8 read_disp_or_null(bool may_need_disp) {
if(!may_need_disp || is_hl_iregp())
return 0;
fast_u8 d = self().on_disp_read();
self().on_5t_exec_cycle();
return d;
}
fast_u8 read_disp_or_null(reg r) {
return read_disp_or_null(r == reg::at_hl);
}
fast_u8 read_disp_or_null(reg r1, reg r2) {
return read_disp_or_null(r1 == reg::at_hl || r2 == reg::at_hl);
}
// Transfers.
public:
void on_decode_ld_r_n(reg r) {
fast_u8 d, n;
if(!self().on_is_z80() || r != reg::at_hl || is_hl_iregp()) {
d = 0;
n = self().on_imm8_read();
} else {
d = self().on_disp_read();
n = self().on_imm8_read();
self().on_read_cycle_extra_2t();
}
self().on_ld_r_n(r, d, n); }
void on_decode_ld_r_r(reg rd, reg rs) {
fast_u8 d = !self().on_is_z80() ? 0 : read_disp_or_null(rd, rs);
self().on_ld_r_r(rd, rs, d); }
void on_decode_ld_sp_irp() {
if(!self().on_is_z80())
self().on_fetch_cycle_extra_1t();
else
self().on_fetch_cycle_extra_2t();
self().on_ld_sp_irp(); }
// Swaps.
void on_decode_ex_af_alt_af() {
if(!self().on_is_z80())
return self().on_xnop(/* op= */ 0x08);
self().on_ex_af_alt_af(); }
void on_decode_ex_de_hl() {
if(!self().on_is_z80())
self().on_fetch_cycle_extra_1t();
self().on_ex_de_hl(); }
void on_decode_exx() {
if(!self().on_is_z80())
return self().on_xret();
self().on_exx(); }
// Arithmetic.
void on_decode_alu_r(alu k, reg r) {
fast_u8 d = !self().on_is_z80() ? 0 : read_disp_or_null(r);
self().on_alu_r(k, r, d); }
void on_decode_inc_r(reg r) {
fast_u8 d;
if(!self().on_is_z80()) {
d = 0;
if(r != reg::at_hl)
self().on_fetch_cycle_extra_1t();
} else {
d = read_disp_or_null(r);
}
self().on_inc_r(r, d); }
void on_decode_dec_r(reg r) {
fast_u8 d;
if(!self().on_is_z80()) {
d = 0;
if(r != reg::at_hl)
self().on_fetch_cycle_extra_1t();
} else {
d = read_disp_or_null(r);
}
self().on_dec_r(r, d); }
void on_decode_inc_rp(regp rp) {
if(!self().on_is_z80())
self().on_fetch_cycle_extra_1t();
else
self().on_fetch_cycle_extra_2t();
self().on_inc_rp(rp); }
void on_decode_dec_rp(regp rp) {
if(!self().on_is_z80())
self().on_fetch_cycle_extra_1t();
else
self().on_fetch_cycle_extra_2t();
self().on_dec_rp(rp); }
// Jumps.
void on_decode_xcall_nn(fast_u8 op) {
fast_u16 nn = self().on_imm16_read();
self().on_read_cycle_extra_1t();
self().on_xcall_nn(op, nn); }
void on_decode_call_cc_nn(condition cc) {
if(!self().on_is_z80())
self().on_fetch_cycle_extra_1t();
self().on_call_cc_nn(cc, self().on_imm16_read()); }
void on_decode_jp_irp() {
if(!self().on_is_z80())
self().on_fetch_cycle_extra_1t();
self().on_jp_irp(); }
void on_decode_jr() {
if(!self().on_is_z80())
return self().on_xnop(/* op= */ 0x18);
self().on_jr(self().on_disp_read()); }
void on_decode_jr_cc(fast_u8 op) {
if(!self().on_is_z80())
return self().on_xnop(op);
auto cc = static_cast<condition>((op & (y_mask - 0040)) >> 3);
self().on_jr_cc(cc, self().on_disp_read()); }
void on_decode_djnz() {
if(!self().on_is_z80())
return self().on_xnop(/* op= */ 0x10);
self().on_fetch_cycle_extra_1t();
self().on_djnz(self().on_disp_read()); }
// Interrupts.
void on_decode_halt() {
if(!self().on_is_z80())
self().on_fetch_cycle_extra_3t();
self().on_halt(); }
// Prefixes.
void on_decode_dd_prefix() {
if(!self().on_is_z80())
return self().on_decode_xcall_nn(0xdd);
self().on_instr_prefix(iregp::ix); }
void on_decode_fd_prefix() {
if(!self().on_is_z80())
return self().on_decode_xcall_nn(0xfd);
self().on_instr_prefix(iregp::iy); }
void on_decode_cb_prefix() {
if(!self().on_is_z80())
return self().on_xjp_nn(self().on_imm16_read());
fast_u8 d = 0;
iregp irp = self().on_get_iregp_kind();
if(irp != iregp::hl)
d = self().on_disp_read();
fast_u8 op;
if(irp == iregp::hl) {
op = self().on_m1_fetch_cycle();
} else {
// In ddcb- and fdcb-prefixed instructions the
// reading of the 3rd opcode is not an M1 cycle.
op = self().on_fetch_cycle();
self().on_fetch_cycle_extra_1t();
}
fast_u8 y = get_y_part(op);
fast_u8 z = get_z_part(op);
auto r = static_cast<reg>(z);
switch(op & x_mask) {
case 0000: {
// rot[y] r[z]
// rot r f(4) f(4)
// rot (HL) f(4) f(4) r(4) w(3)
// rot (i+d) f(4) f(4) r(3) f(5) r(4) w(3)
auto k = static_cast<rot>(y);
return self().on_rot(k, r, d); }
case 0100: {
// BIT y, r[z]
// BIT b, r f(4) f(4)
// BIT b, (HL) f(4) f(4) r(4)
// BIT b, (i+d) f(4) f(4) r(3) f(5) r(4)
auto b = static_cast<unsigned>(y);
return self().on_bit(b, r, d); }
case 0200: {
// RES y, r[z]
// RES b, r f(4) f(4)
// RES b, (HL) f(4) f(4) r(4) w(3)
// RES b, (i+d) f(4) f(4) r(3) f(5) r(4) w(3)
auto b = static_cast<unsigned>(y);
return self().on_res(b, r, d); }
case 0300: {
// SET y, r[z]
// SET b, r f(4) f(4)
// SET b, (HL) f(4) f(4) r(4) w(3)
// SET b, (i+d) f(4) f(4) r(3) f(5) r(4) w(3)
auto b = static_cast<unsigned>(y);
return self().on_set(b, r, d); }
}
unreachable("Unknown opcode encountered!");
}
void on_decode_ed_prefix() {
if(!self().on_is_z80())
return self().on_decode_xcall_nn(0xed);
fast_u8 op = self().on_m1_fetch_cycle();
fast_u8 y = get_y_part(op);
fast_u8 p = get_p_part(op);
switch(op) {
// TODO: Combine with decoding xneg's.
case 0x44:
// NEG f(4) f(4)
return self().on_neg();
// TODO: Combine with decoding xim's.
case 0x46:
// IM im[y] f(4) f(4)
return self().on_im(0);
case 0x56:
case 0x5e:
return self().on_im(y - 1);
// TODO: Combine with decoding xretn's.
case 0x4d:
// RETI f(4) f(4) r(3) r(3)
return self().on_reti();
case 0x45:
// RETN f(4) f(4) r(3) r(3)
return self().on_retn();
case 0x47:
// LD I, A f(4) f(5)
self().on_fetch_cycle_extra_1t();
return self().on_ld_i_a();
case 0x4f:
// LD R, A f(4) f(5)
self().on_fetch_cycle_extra_1t();
return self().on_ld_r_a();
case 0x57:
// LD A, I f(4) f(5)
self().on_fetch_cycle_extra_1t();
return self().on_ld_a_i();
case 0x5f:
// LD A, R f(4) f(5)
self().on_fetch_cycle_extra_1t();
return self().on_ld_a_r();
case 0x67:
// RRD f(4) f(4) r(3) e(4) w(3)
return self().on_rrd();
case 0x6f:
// RLD f(4) f(4) r(3) e(4) w(3)
return self().on_rld();
}
// TODO: Can be just switch(op & (x_mask | z_mask)) ?
if((op & x_mask) == 0100) {
switch(op & z_mask) {
case 0: {
// IN r[y], (C) f(4) f(4) i(4)
// IN (C) f(4) f(4) i(4)
auto r = static_cast<reg>(y);
return self().on_in_r_c(r); }
case 1: {
// OUT (C), r[y] f(4) f(4) o(4)
// OUT (C), 0 f(4) f(4) o(4)
auto r = static_cast<reg>(y);
return self().on_out_c_r(r); }
case 2: {
// ADC HL, rp[p] f(4) f(4) e(4) e(3)
// SBC HL, rp[p] f(4) f(4) e(4) e(3)
auto rp = static_cast<regp>(p);
return op & q_mask ? self().on_adc_hl_rp(rp) :
self().on_sbc_hl_rp(rp); }
case 3: {
// LD rp[p], (nn) f(4) f(4) r(3) r(3) r(3) r(3)
// LD (nn), rp[p] f(4) f(4) r(3) r(3) w(3) w(3)
auto rp = static_cast<regp>(p);
fast_u16 nn = self().on_imm16_read();
return op & q_mask ? self().on_ld_rp_at_nn(rp, nn) :
self().on_ld_at_nn_rp(nn, rp); }
case 4:
// XNEG f(4) f(4)
return self().on_xneg(op);
case 5:
// XRETN f(4) f(4) r(3) r(3)
return self().on_xretn(op);
case 6: {
// IM im[y] f(4) f(4)
fast_u8 n = y & 3;
return self().on_xim(op, n == 0 ? 0 : n - 1); }
}
}
if((op & x_mask) == 0200 && y >= 4) {
fast_u8 n = y - 4;
switch(op & z_mask) {
case 0: {
// LDI, LDD, LDIR, LDDR f(4) f(4) r(3) w(5) + e(5)
auto k = static_cast<block_ld>(n);
return self().on_block_ld(k); }
case 1: {
// CPI, CPD, CPIR, CPDR f(4) f(4) r(3) e(5) + e(5)
auto k = static_cast<block_cp>(n);
return self().on_block_cp(k); }
case 2: {
// INI, IND, INIR, INDR f(4) f(5) i(4) w(3) + e(5)
auto k = static_cast<block_in>(n);
return self().on_block_in(k); }
case 3: {
// OUTI, OUTD, OTIR, OTDR f(4) f(5) r(3) o(4) + e(5)
auto k = static_cast<block_out>(n);
return self().on_block_out(k); }
}
}
return self().on_ed_xnop(op);
}
private:
void do_decode(fast_u8 op) {
fast_u8 y = get_y_part(op);
fast_u8 z = get_z_part(op);
fast_u8 p = get_p_part(op);
// TODO: Collect some statistics and see if these
// switches come in a good order.
switch(op & x_mask) {
case 0100: {
// LD/MOV r[y], r[z] or
// HALT/HLT (in place of LD (HL), (HL)/MOV M, M)
// MOV r, r f(5)
// LD r, r f(4)
// LD r, (HL) f(4) r(3)
// LD r, (i+d) f(4) f(4) r(3) e(5) r(3)
// LD (HL), r f(4) w(3)
// LD (i+d), r f(4) f(4) r(3) e(5) w(3)
// HLT f(7)
// HALT f(4)
auto rd = static_cast<reg>(y);
auto rs = static_cast<reg>(z);
if(rd == reg::at_hl && rs == reg::at_hl)
return self().on_decode_halt();
return self().on_decode_ld_r_r(rd, rs); }
case 0200: {
// alu[y] r[z]
// alu r f(4) (both i8080 and z80)
// alu M f(4) r(3)
// alu (HL) f(4) r(3)
// alu (i+d) f(4) f(4) r(3) e(5) r(3)
auto k = static_cast<alu>(y);
auto r = static_cast<reg>(z);
return self().on_decode_alu_r(k, r); }
}
switch(op & (x_mask | z_mask)) {
case 0004: {
// INR/INC r[y]
// INR r f(5)
// INR M f(4) r(3) w(3)
// INC r f(4)
// INC (HL) f(4) r(4) w(3)
// INC (i+d) f(4) f(4) r(3) e(5) r(4) w(3)
auto r = static_cast<reg>(y);
return self().on_decode_inc_r(r); }
case 0005: {
// DCR/DEC r[y]
// DCR r f(5)
// DCR M f(4) r(3) w(3)
// DEC r f(4)
// DEC (HL) f(4) r(4) w(3)
// DEC (i+d) f(4) f(4) r(3) e(5) r(4) w(3)
auto r = static_cast<reg>(y);
return self().on_decode_dec_r(r); }
case 0006: {
// LD/MVI r[y], n
// MVI r, n f(4) r(3)
// LD r, n f(4) r(3)
// LD (HL), n f(4) r(3) w(3)
// LD (i+d), n f(4) f(4) r(3) r(5) w(3)
auto r = static_cast<reg>(y);
return self().on_decode_ld_r_n(r); }
case 0300: {
// RET cc[y]/Rcc[y] f(5) + r(3) r(3)
self().on_fetch_cycle_extra_1t();
auto cc = static_cast<condition>(y);
return self().on_ret_cc(cc); }
case 0302: {