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report.ctsrpt
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###############################################################
# Generated by: Cadence Encounter 09.11-s084_1
# OS: Linux x86_64(Host ID srge04.ecn.purdue.edu)
# Generated on: Thu Apr 26 12:43:45 2012
# Command: ckSynthesis -rguide cts.rguide -report report.ctsrpt -...
###############################################################
###############################################################
# Complete Clock Tree Timing Report
#
# CLOCK: clk
#
# Mode: preRoute
#
# Mode : Setup
# Library Name : osu05_stdcells
# Operating Condition : typical
# Process : 1
# Voltage : 5
# Temperature : 25
#
###############################################################
Nr. of Subtrees : 2
Nr. of Sinks : 171
Nr. of Buffer : 9
Nr. of Level (including gates) : 3
Root Rise Input Tran : 120(ps)
Root Fall Input Tran : 120(ps)
Max trig. edge delay at sink(R): I0/U_3/U_4/usbDataMinusOutputReg_reg/CLK 762.6(ps)
Min trig. edge delay at sink(R): I0/U_1/part4/pre_val_reg[3]/CLK 715(ps)
(Actual) (Required)
Rise Phase Delay : 715~762.6(ps) 0~7000(ps)
Fall Phase Delay : 675.9~725.8(ps) 0~7000(ps)
Trig. Edge Skew : 47.6(ps) 300(ps)
Rise Skew : 47.6(ps)
Fall Skew : 49.9(ps)
Max. Rise Buffer Tran : 372.7(ps) 400(ps)
Max. Fall Buffer Tran : 373.5(ps) 400(ps)
Max. Rise Sink Tran : 258.5(ps) 400(ps)
Max. Fall Sink Tran : 260.1(ps) 400(ps)
Min. Rise Buffer Tran : 63(ps) 0(ps)
Min. Fall Buffer Tran : 56.7(ps) 0(ps)
Min. Rise Sink Tran : 231.2(ps) 0(ps)
Min. Fall Sink Tran : 233.6(ps) 0(ps)
***** NO Max Transition Time Violation *****
***** NO Min Transition Time Violation *****
***** NO Max_Fanout Violation *****
***** NO AC Irms Limit Violation *****
**** Sub Tree Report ****
OUTPUT_TERM: clk [0(ps) 0(ps)]
Main Tree:
nrSink : 171
Rise Delay : [715(ps) 762.6(ps)]
Rise Skew : 47.6(ps)
Fall Delay : [675.9(ps) 725.8(ps)]
Fall Skew : 49.9(ps)
Child Tree 1 from U6/YPAD:
nrSink : 171
Rise Delay [715(ps) 762.6(ps)] Skew [47.6(ps)]
Fall Delay[675.9(ps) 725.8(ps)] Skew=[49.9(ps)]
Main Tree from clk w/o tracing through gates:
nrSink : 0
nrGate : 1
**** Sub Tree Report ****
INPUT_TERM: U6/YPAD [3.6(ps) 3.6(ps)]
OUTPUT_TERM: U6/DI [137.5(ps) 151(ps)]
Main Tree:
nrSink : 171
Rise Delay : [715(ps) 762.6(ps)]
Rise Skew : 47.6(ps)
Fall Delay : [675.9(ps) 725.8(ps)]
Fall Skew : 49.9(ps)
Main Tree from U6/DI w/o tracing through gates:
nrSink : 171
nrGate : 0
Rise Delay [715(ps) 762.6(ps)] Skew [47.6(ps)]
Fall Delay [675.9(ps) 725.8(ps)] Skew=[49.9(ps)]
clk (0 0) load=0.450181(pf)
U6/YPAD (0.0036 0.0036)
U6/DI (0.1375 0.151) load=0.246678(pf)
nclk__L1_I0/A (0.1478 0.1612)
nclk__L1_I0/Y (0.4388 0.4617) load=1.13139(pf)
nclk__L2_I7/A (0.4513 0.4742)
nclk__L2_I7/Y (0.7246 0.6872) load=0.577575(pf)
nclk__L2_I6/A (0.4508 0.4737)
nclk__L2_I6/Y (0.7287 0.6919) load=0.596683(pf)
nclk__L2_I5/A (0.4508 0.4737)
nclk__L2_I5/Y (0.72 0.682) load=0.560343(pf)
nclk__L2_I4/A (0.4514 0.4743)
nclk__L2_I4/Y (0.7377 0.702) load=0.631789(pf)
nclk__L2_I3/A (0.4502 0.4731)
nclk__L2_I3/Y (0.7173 0.679) load=0.551431(pf)
nclk__L2_I2/A (0.4532 0.4761)
nclk__L2_I2/Y (0.7331 0.6966) load=0.605176(pf)
nclk__L2_I1/A (0.4538 0.4767)
nclk__L2_I1/Y (0.7143 0.6752) load=0.524109(pf)
nclk__L2_I0/A (0.4544 0.4773)
nclk__L2_I0/Y (0.7241 0.6861) load=0.562285(pf)
I0/U_4/tsrDataReg_reg[1]/CLK (0.743 0.7056)
I0/U_6/sdc_reg/CLK (0.743 0.7056)
I0/U_2/U_0/gregData_reg[1][6]/CLK (0.7361 0.6987)
I0/U_2/U_0/gregData_reg[0][7]/CLK (0.7414 0.704)
I0/U_4/tsrDummyReg_reg[0]/CLK (0.7423 0.7049)
I0/U_4/tsrDataReg_reg[7]/CLK (0.7391 0.7017)
I0/U_4/tsrDataReg_reg[6]/CLK (0.7398 0.7024)
I0/U_4/tsrDataReg_reg[5]/CLK (0.7385 0.7011)
I0/U_4/tsrDataReg_reg[0]/CLK (0.7427 0.7053)
I0/U_4/load_reg/CLK (0.7416 0.7042)
I0/U_4/load2_reg/CLK (0.7404 0.703)
I0/U_2/U_0/gregData_reg[3][7]/CLK (0.7389 0.7015)
I0/U_2/U_0/gregData_reg[2][7]/CLK (0.7362 0.6988)
I0/U_2/U_0/gregData_reg[2][3]/CLK (0.7428 0.7054)
I0/U_2/U_0/gregData_reg[1][7]/CLK (0.7412 0.7038)
I0/U_2/U_0/gregData_reg[1][4]/CLK (0.7403 0.7029)
I0/U_2/U_0/gregData_reg[1][2]/CLK (0.7429 0.7055)
I0/U_2/U_0/gregData_reg[0][6]/CLK (0.7387 0.7013)
I0/U_2/U_0/gregData_reg[0][4]/CLK (0.7425 0.7051)
I0/U_2/U_0/gregData_reg[0][2]/CLK (0.742 0.7046)
I0/U_2/U_0/gregData_reg[3][6]/CLK (0.735 0.6976)
I0/U_3/U_0/eopInt1_reg/CLK (0.7395 0.7027)
I0/U_1/part2/cur_EOP_reg/CLK (0.7611 0.7243)
I0/U_3/U_0/eopInt2_reg/CLK (0.7423 0.7055)
I0/U_1/part5/CS_reg[0]/CLK (0.7467 0.7099)
I0/U_3/U_4/state_reg[0]/CLK (0.7468 0.71)
I0/U_3/U_4/usbDataMinusSync_reg/CLK (0.7618 0.725)
I0/U_3/U_4/usbInt2_reg/CLK (0.7537 0.7169)
I0/U_3/U_4/usbInt1_reg/CLK (0.7515 0.7147)
I0/U_3/U_4/usbDataPlusSync_reg/CLK (0.7594 0.7226)
I0/U_3/U_4/usbDataPlusSync2_reg/CLK (0.7609 0.7241)
I0/U_3/U_4/usbDataPlusOutputReg_reg/CLK (0.7541 0.7173)
I0/U_3/U_4/usbDataMinusSync2_reg/CLK (0.7625 0.7257)
I0/U_3/U_4/usbDataMinusOutputReg_reg/CLK (0.7626 0.7258)
I0/U_3/U_4/state_reg[3]/CLK (0.7541 0.7173)
I0/U_3/U_1/computerLock_reg/CLK (0.7603 0.7235)
I0/U_3/U_0/usbInt2_reg/CLK (0.755 0.7182)
I0/U_3/U_0/usbInt1_reg/CLK (0.7491 0.7123)
I0/U_3/U_0/computerDataPlusSync_reg/CLK (0.7612 0.7244)
I0/U_3/U_0/computerDataPlusOutput_reg/CLK (0.7592 0.7224)
I0/U_3/U_0/computerDataMinusSync_reg/CLK (0.7587 0.7219)
I0/U_3/U_0/computerDataMinusOutput_reg/CLK (0.7575 0.7207)
I0/U_3/U_1/usbLock_reg/CLK (0.7606 0.7238)
I0/U_1/part2/cur_EGDE_reg/CLK (0.7349 0.6981)
I0/U_0/dr_reg/CLK (0.7351 0.6971)
I0/U_0/sd_reg/CLK (0.7235 0.6855)
I0/U_1/part5/CS_reg[2]/CLK (0.7329 0.6949)
I0/U_1/part5/CS_reg[3]/CLK (0.7312 0.6932)
I0/U_2/U_0/fifoEmptyReg_reg/CLK (0.723 0.685)
I0/U_2/U_0/fifoFullReg_reg/CLK (0.7266 0.6886)
I0/U_2/U_1/count_reg[0]/CLK (0.7268 0.6888)
I0/U_2/U_2/count_reg[0]/CLK (0.7255 0.6875)
I0/U_3/U_4/cntr_reg[0]/CLK (0.7423 0.7043)
I0/U_3/U_4/cntr_reg[1]/CLK (0.7432 0.7052)
I0/U_3/U_4/cntr_reg[3]/CLK (0.7386 0.7006)
I0/U_3/U_4/cntr_reg[4]/CLK (0.7397 0.7017)
I0/U_3/U_4/state_reg[1]/CLK (0.7371 0.6991)
I0/U_3/U_4/state_reg[2]/CLK (0.7332 0.6952)
I0/U_6/count1_reg[0]/CLK (0.7402 0.7022)
I0/U_2/U_1/count_reg[1]/CLK (0.7234 0.6854)
I0/U_1/part5/dclk_cur_reg/CLK (0.7333 0.6953)
I0/U_1/part5/cur_shift_en_reg/CLK (0.727 0.689)
I0/U_3/U_4/cntr_reg[2]/CLK (0.7433 0.7053)
I0/U_1/part5/CS_reg[1]/CLK (0.7272 0.6892)
I0/U_6/count1_reg[2]/CLK (0.7415 0.7035)
I0/U_1/part2/cur_FEGDE_reg/CLK (0.7274 0.6894)
I0/U_2/U_0/gregData_reg[2][6]/CLK (0.747 0.7113)
I0/U_0/dr1_reg/CLK (0.746 0.7103)
I0/U_6/count1_reg[3]/CLK (0.7536 0.7179)
I0/U_6/sd_reg[0]/CLK (0.7481 0.7124)
I0/U_0/dr2_reg/CLK (0.7481 0.7124)
I0/U_6/count1_reg[1]/CLK (0.7507 0.715)
I0/U_6/count2_reg[2]/CLK (0.7564 0.7207)
I0/U_6/sd_reg[3]/CLK (0.7501 0.7144)
I0/U_6/sd_reg[2]/CLK (0.7527 0.717)
I0/U_6/sd_reg[1]/CLK (0.7544 0.7187)
I0/U_6/count3_reg[2]/CLK (0.7534 0.7177)
I0/U_6/count3_reg[1]/CLK (0.7532 0.7175)
I0/U_6/count3_reg[0]/CLK (0.7515 0.7158)
I0/U_6/count2_reg[4]/CLK (0.7562 0.7205)
I0/U_6/count2_reg[3]/CLK (0.7557 0.72)
I0/U_6/count2_reg[1]/CLK (0.7537 0.718)
I0/U_6/count2_reg[0]/CLK (0.7535 0.7178)
I0/U_6/count1_reg[6]/CLK (0.7546 0.7189)
I0/U_6/count1_reg[5]/CLK (0.7555 0.7198)
I0/U_6/count1_reg[4]/CLK (0.7539 0.7182)
I0/U_4/load1_reg/CLK (0.7501 0.7144)
I0/U_0/eopCount_reg[2]/CLK (0.7463 0.708)
I0/U_2/U_0/gregData_reg[2][0]/CLK (0.731 0.6927)
I0/U_0/eopCount_reg[1]/CLK (0.7458 0.7075)
I0/U_1/cur_data_reg[0]/CLK (0.7433 0.705)
I0/U_0/usb_reg[2]/CLK (0.7451 0.7068)
I0/U_0/usb_reg[1]/CLK (0.7439 0.7056)
I0/U_0/usb_reg[0]/CLK (0.7446 0.7063)
I0/U_0/eopCount_reg[0]/CLK (0.7456 0.7073)
I0/U_1/CS_reg[0]/CLK (0.74 0.7017)
I0/U_1/CS_reg[1]/CLK (0.7264 0.6881)
I0/U_1/CS_reg[3]/CLK (0.7422 0.7039)
I0/U_1/data_ready_0_reg/CLK (0.7386 0.7003)
I0/U_1/data_ready_1_reg/CLK (0.736 0.6977)
I0/U_1/part4/cnt_reg[0]/CLK (0.7304 0.6921)
I0/U_1/part4/cnt_reg[1]/CLK (0.735 0.6967)
I0/U_1/part4/cnt_reg[2]/CLK (0.7314 0.6931)
I0/U_1/part4/pre_val_reg[0]/CLK (0.7291 0.6908)
I0/U_2/U_0/gregData_reg[0][0]/CLK (0.7305 0.6922)
I0/U_2/U_0/gregData_reg[1][0]/CLK (0.7299 0.6916)
I0/U_2/U_0/gregData_reg[1][3]/CLK (0.731 0.6927)
I0/U_1/part4/cur_data_ready_reg/CLK (0.7349 0.6966)
I0/U_2/U_0/gregData_reg[0][1]/CLK (0.753 0.7165)
I0/U_2/U_0/gregData_reg[1][1]/CLK (0.7534 0.7169)
I0/U_2/U_0/gregData_reg[3][2]/CLK (0.754 0.7175)
I0/U_5/count_reg[6]/CLK (0.7538 0.7173)
I0/U_5/count_reg[1]/CLK (0.7493 0.7128)
I0/U_5/count_reg[0]/CLK (0.7509 0.7144)
I0/U_4/tsrDataReg_reg[3]/CLK (0.7558 0.7193)
I0/U_4/tsrDataReg_reg[2]/CLK (0.7572 0.7207)
I0/U_2/U_0/gregData_reg[3][1]/CLK (0.7471 0.7106)
I0/U_2/U_0/gregData_reg[2][2]/CLK (0.7521 0.7156)
I0/U_2/U_0/gregData_reg[2][1]/CLK (0.7495 0.713)
I0/U_5/count_reg[2]/CLK (0.7509 0.7144)
I0/U_5/count_reg[3]/CLK (0.7531 0.7166)
I0/U_5/count_reg[4]/CLK (0.7536 0.7171)
I0/U_5/count_reg[5]/CLK (0.7537 0.7172)
I0/U_5/count_reg[7]/CLK (0.7593 0.7228)
I0/U_5/count_reg[8]/CLK (0.759 0.7225)
I0/U_5/sclReg_reg/CLK (0.7567 0.7202)
I0/U_6/sd_clock1_reg/CLK (0.7586 0.7221)
I0/U_6/sd_clock2_reg/CLK (0.7576 0.7211)
I0/U_2/U_0/gregData_reg[3][3]/CLK (0.7438 0.7073)
I0/U_4/tsrDataReg_reg[4]/CLK (0.7549 0.7184)
I0/U_2/U_0/gregData_reg[0][3]/CLK (0.7534 0.7169)
I0/U_1/CS_reg[2]/CLK (0.7338 0.6947)
I0/U_1/cur_data_reg[1]/CLK (0.734 0.6949)
I0/U_1/cur_inst_reg[0]/CLK (0.7335 0.6944)
I0/U_1/cur_inst_reg[1]/CLK (0.7327 0.6936)
I0/U_1/part3/data_out_reg/CLK (0.7324 0.6933)
I0/U_1/part4/pre_val_reg[2]/CLK (0.7269 0.6878)
I0/U_1/part4/pre_val_reg[4]/CLK (0.7295 0.6904)
I0/U_1/part4/pre_val_reg[5]/CLK (0.7309 0.6918)
I0/U_1/part4/pre_val_reg[7]/CLK (0.7311 0.692)
I0/U_2/U_0/gregData_reg[1][5]/CLK (0.7307 0.6916)
I0/U_2/U_0/gregData_reg[3][4]/CLK (0.7228 0.6837)
I0/U_2/U_0/gregData_reg[3][5]/CLK (0.7297 0.6906)
I0/U_2/U_2/count_reg[1]/CLK (0.7314 0.6923)
I0/U_1/cur_inst_reg[3]/CLK (0.7321 0.693)
I0/U_2/U_0/gregData_reg[2][4]/CLK (0.7193 0.6802)
I0/U_1/part4/pre_val_reg[6]/CLK (0.7314 0.6923)
I0/U_2/U_0/gregData_reg[2][5]/CLK (0.7251 0.686)
I0/U_1/part4/pre_val_reg[3]/CLK (0.715 0.6759)
I0/U_1/part4/pre_val_reg[1]/CLK (0.715 0.6759)
I0/U_2/U_0/gregData_reg[3][0]/CLK (0.7151 0.676)
I0/U_2/U_0/gregData_reg[0][5]/CLK (0.731 0.6919)
I0/U_0/writeCount_reg[2]/CLK (0.7376 0.6996)
I0/U_3/U_1/state_reg[2]/CLK (0.7451 0.7071)
I0/U_3/U_1/state_reg[0]/CLK (0.7485 0.7105)
I0/U_3/U_1/locku_reg/CLK (0.7494 0.7114)
I0/U_3/U_1/eopIn1_reg/CLK (0.7454 0.7074)
I0/U_1/part3/data0_buf0_reg/CLK (0.7498 0.7118)
I0/U_1/part2/d2_reg/CLK (0.7495 0.7115)
I0/U_1/part2/d1_reg/CLK (0.7498 0.7118)
I0/U_0/writeCount_reg[1]/CLK (0.7468 0.7088)
I0/U_0/eop1_reg/CLK (0.7472 0.7092)
I0/U_0/eop2_reg/CLK (0.7482 0.7102)
I0/U_0/eopf_reg/CLK (0.7497 0.7117)
I0/U_3/U_1/eopFound_reg/CLK (0.7498 0.7118)
I0/U_3/U_1/eopIn2_reg/CLK (0.7489 0.7109)
I0/U_3/U_1/state_reg[1]/CLK (0.7496 0.7116)
I0/U_0/usb_reg[3]/CLK (0.7421 0.7041)
I0/U_3/U_1/lockc_reg/CLK (0.7496 0.7116)
I0/U_0/writeCount_reg[0]/CLK (0.7395 0.7015)
I0/U_1/cur_inst_reg[2]/CLK (0.7331 0.6951)