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skew.post_troute_local.ctsrpt
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###############################################################
# Generated by: Cadence Encounter 09.11-s084_1
# OS: Linux x86_64(Host ID srge04.ecn.purdue.edu)
# Generated on: Thu Apr 26 12:43:48 2012
# Command: reportClockTree -postRoute -localSkew -report skew.pos...
###############################################################
###############################################################
# Complete Clock Tree Timing Report
#
# CLOCK: clk
#
# Mode: postRoute
#
# Mode : Setup
# Library Name : osu05_stdcells
# Operating Condition : typical
# Process : 1
# Voltage : 5
# Temperature : 25
#
###############################################################
Nr. of Subtrees : 2
Nr. of Sinks : 171
Nr. of Buffer : 9
Nr. of Level (including gates) : 3
Root Rise Input Tran : 120(ps)
Root Fall Input Tran : 120(ps)
Max trig. edge delay at sink(R): I0/U_5/count_reg[4]/CLK 770.4(ps)
Min trig. edge delay at sink(R): I0/U_1/part4/pre_val_reg[1]/CLK 723.5(ps)
(Actual) (Required)
Rise Phase Delay : 723.5~770.4(ps) 0~7000(ps)
Fall Phase Delay : 683.8~733.7(ps) 0~7000(ps)
Trig. Edge Skew : 46.9(ps) 300(ps)
Rise Skew : 46.9(ps)
Fall Skew : 49.9(ps)
Max. Rise Buffer Tran : 395.1(ps) 400(ps)
Max. Fall Buffer Tran : 398.1(ps) 400(ps)
Max. Rise Sink Tran : 297.3(ps) 400(ps)
Max. Fall Sink Tran : 298.6(ps) 400(ps)
Min. Rise Buffer Tran : 79.9(ps) 0(ps)
Min. Fall Buffer Tran : 72.5(ps) 0(ps)
Min. Rise Sink Tran : 258.8(ps) 0(ps)
Min. Fall Sink Tran : 260.8(ps) 0(ps)
**** Local Skew Report ****
Total number of adjacent register pair : 1777
Max. Local Skew : 37.3(ps)
I0/U_6/sd_reg[3]/CLK(R)->
I0/U_0/dr1_reg/CLK(R)
***** NO Max Transition Time Violation *****
***** NO Min Transition Time Violation *****
***** NO Max_Fanout Violation *****
***** NO AC Irms Limit Violation *****
**** Sub Tree Report ****
OUTPUT_TERM: clk [0(ps) 0(ps)]
Main Tree:
nrSink : 171
Rise Delay : [723.5(ps) 770.4(ps)]
Rise Skew : 46.9(ps)
Fall Delay : [683.8(ps) 733.7(ps)]
Fall Skew : 49.9(ps)
Child Tree 1 from U6/YPAD:
nrSink : 171
Rise Delay [723.5(ps) 770.4(ps)] Skew [46.9(ps)]
Fall Delay[683.8(ps) 733.7(ps)] Skew=[49.9(ps)]
Main Tree from clk w/o tracing through gates:
nrSink : 0
nrGate : 1
**** Sub Tree Report ****
INPUT_TERM: U6/YPAD [3.6(ps) 3.6(ps)]
OUTPUT_TERM: U6/DI [135.5(ps) 148.2(ps)]
Main Tree:
nrSink : 171
Rise Delay : [723.5(ps) 770.4(ps)]
Rise Skew : 46.9(ps)
Fall Delay : [683.8(ps) 733.7(ps)]
Fall Skew : 49.9(ps)
Main Tree from U6/DI w/o tracing through gates:
nrSink : 171
nrGate : 0
Rise Delay [723.5(ps) 770.4(ps)] Skew [46.9(ps)]
Fall Delay [683.8(ps) 733.7(ps)] Skew=[49.9(ps)]
clk (0 0) load=0.450181(pf)
U6/YPAD (0.0036 0.0036)
U6/DI (0.1355 0.1482) load=0.287815(pf)
nclk__L1_I0/A (0.1503 0.1629)
nclk__L1_I0/Y (0.4359 0.4568) load=1.15091(pf)
nclk__L2_I7/A (0.4526 0.4735)
nclk__L2_I7/Y (0.7251 0.6859) load=0.632288(pf)
nclk__L2_I6/A (0.4503 0.4713)
nclk__L2_I6/Y (0.7411 0.7044) load=0.691488(pf)
nclk__L2_I5/A (0.4526 0.4735)
nclk__L2_I5/Y (0.7385 0.7011) load=0.639071(pf)
nclk__L2_I4/A (0.4526 0.4735)
nclk__L2_I4/Y (0.722 0.6828) load=0.651973(pf)
nclk__L2_I3/A (0.4495 0.4704)
nclk__L2_I3/Y (0.7268 0.6885) load=0.628938(pf)
nclk__L2_I2/A (0.4493 0.4702)
nclk__L2_I2/Y (0.7367 0.7) load=0.694692(pf)
nclk__L2_I1/A (0.451 0.472)
nclk__L2_I1/Y (0.7196 0.6799) load=0.593123(pf)
nclk__L2_I0/A (0.4511 0.472)
nclk__L2_I0/Y (0.7294 0.6915) load=0.637331(pf)
I0/U_2/U_0/gregData_reg[3][7]/CLK (0.7541 0.715)
I0/U_2/U_0/gregData_reg[3][6]/CLK (0.735 0.6958)
I0/U_2/U_0/gregData_reg[2][7]/CLK (0.7386 0.6994)
I0/U_2/U_0/gregData_reg[2][3]/CLK (0.7528 0.7137)
I0/U_2/U_0/gregData_reg[1][7]/CLK (0.7508 0.7117)
I0/U_2/U_0/gregData_reg[1][6]/CLK (0.7433 0.7041)
I0/U_2/U_0/gregData_reg[1][4]/CLK (0.7506 0.7114)
I0/U_2/U_0/gregData_reg[1][2]/CLK (0.7527 0.7135)
I0/U_2/U_0/gregData_reg[0][7]/CLK (0.7525 0.7134)
I0/U_2/U_0/gregData_reg[0][6]/CLK (0.7459 0.7067)
I0/U_2/U_0/gregData_reg[0][4]/CLK (0.7528 0.7136)
I0/U_2/U_0/gregData_reg[0][2]/CLK (0.7519 0.7127)
I0/U_4/load2_reg/CLK (0.759 0.7199)
I0/U_4/load_reg/CLK (0.7594 0.7203)
I0/U_4/tsrDummyReg_reg[0]/CLK (0.7598 0.7207)
I0/U_4/tsrDataReg_reg[0]/CLK (0.7599 0.7208)
I0/U_4/tsrDataReg_reg[1]/CLK (0.7602 0.721)
I0/U_4/tsrDataReg_reg[5]/CLK (0.756 0.7168)
I0/U_4/tsrDataReg_reg[6]/CLK (0.7588 0.7196)
I0/U_4/tsrDataReg_reg[7]/CLK (0.758 0.7189)
I0/U_6/sdc_reg/CLK (0.7601 0.721)
I0/U_1/part2/cur_EOP_reg/CLK (0.7583 0.7216)
I0/U_1/part2/cur_EGDE_reg/CLK (0.7515 0.7148)
I0/U_1/part5/CS_reg[0]/CLK (0.7521 0.7154)
I0/U_3/U_0/computerDataPlusSync_reg/CLK (0.7543 0.7176)
I0/U_3/U_0/computerDataMinusSync_reg/CLK (0.7664 0.7297)
I0/U_3/U_0/usbInt1_reg/CLK (0.7668 0.7301)
I0/U_3/U_0/usbInt2_reg/CLK (0.7665 0.7299)
I0/U_3/U_0/eopInt1_reg/CLK (0.7513 0.7146)
I0/U_3/U_0/eopInt2_reg/CLK (0.7516 0.7149)
I0/U_3/U_0/computerDataPlusOutput_reg/CLK (0.763 0.7263)
I0/U_3/U_0/computerDataMinusOutput_reg/CLK (0.7652 0.7285)
I0/U_3/U_1/usbLock_reg/CLK (0.7584 0.7217)
I0/U_3/U_1/computerLock_reg/CLK (0.761 0.7243)
I0/U_3/U_4/usbInt1_reg/CLK (0.7668 0.7301)
I0/U_3/U_4/usbInt2_reg/CLK (0.7673 0.7306)
I0/U_3/U_4/state_reg[0]/CLK (0.7522 0.7155)
I0/U_3/U_4/state_reg[3]/CLK (0.7677 0.731)
I0/U_3/U_4/usbDataMinusSync_reg/CLK (0.768 0.7313)
I0/U_3/U_4/usbDataMinusSync2_reg/CLK (0.7687 0.732)
I0/U_3/U_4/usbDataMinusOutputReg_reg/CLK (0.7688 0.7321)
I0/U_3/U_4/usbDataPlusSync_reg/CLK (0.7667 0.73)
I0/U_3/U_4/usbDataPlusSync2_reg/CLK (0.7674 0.7307)
I0/U_3/U_4/usbDataPlusOutputReg_reg/CLK (0.7677 0.731)
I0/U_2/U_0/fifoEmptyReg_reg/CLK (0.7456 0.7082)
I0/U_2/U_0/fifoFullReg_reg/CLK (0.7453 0.7079)
I0/U_2/U_1/count_reg[0]/CLK (0.7452 0.7078)
I0/U_2/U_1/count_reg[1]/CLK (0.7474 0.71)
I0/U_2/U_2/count_reg[0]/CLK (0.7449 0.7075)
I0/U_0/dr_reg/CLK (0.7496 0.7122)
I0/U_0/sd_reg/CLK (0.7476 0.7102)
I0/U_1/part2/cur_FEGDE_reg/CLK (0.7459 0.7085)
I0/U_1/part5/CS_reg[2]/CLK (0.7475 0.7101)
I0/U_1/part5/CS_reg[3]/CLK (0.7473 0.7099)
I0/U_1/part5/CS_reg[1]/CLK (0.7458 0.7085)
I0/U_1/part5/cur_shift_en_reg/CLK (0.7458 0.7084)
I0/U_1/part5/dclk_cur_reg/CLK (0.7482 0.7108)
I0/U_3/U_4/cntr_reg[0]/CLK (0.7523 0.715)
I0/U_3/U_4/cntr_reg[4]/CLK (0.7519 0.7146)
I0/U_3/U_4/state_reg[1]/CLK (0.7485 0.7111)
I0/U_3/U_4/cntr_reg[1]/CLK (0.7532 0.7158)
I0/U_3/U_4/cntr_reg[2]/CLK (0.7533 0.7159)
I0/U_3/U_4/cntr_reg[3]/CLK (0.7488 0.7114)
I0/U_3/U_4/state_reg[2]/CLK (0.7482 0.7108)
I0/U_6/count1_reg[0]/CLK (0.7514 0.7141)
I0/U_6/count1_reg[2]/CLK (0.752 0.7146)
I0/U_2/U_0/gregData_reg[2][6]/CLK (0.7314 0.6923)
I0/U_4/load1_reg/CLK (0.7698 0.7306)
I0/U_0/dr1_reg/CLK (0.7323 0.6931)
I0/U_0/dr2_reg/CLK (0.7447 0.7055)
I0/U_6/sd_reg[0]/CLK (0.7394 0.7002)
I0/U_6/sd_reg[2]/CLK (0.7686 0.7294)
I0/U_6/sd_reg[1]/CLK (0.7556 0.7165)
I0/U_6/sd_reg[3]/CLK (0.7696 0.7304)
I0/U_6/count1_reg[3]/CLK (0.7636 0.7244)
I0/U_6/count1_reg[6]/CLK (0.7599 0.7208)
I0/U_6/count1_reg[1]/CLK (0.747 0.7079)
I0/U_6/count1_reg[4]/CLK (0.7635 0.7243)
I0/U_6/count1_reg[5]/CLK (0.7634 0.7242)
I0/U_6/count3_reg[0]/CLK (0.769 0.7298)
I0/U_6/count3_reg[1]/CLK (0.7685 0.7294)
I0/U_6/count3_reg[2]/CLK (0.7683 0.7292)
I0/U_6/count2_reg[0]/CLK (0.7678 0.7287)
I0/U_6/count2_reg[4]/CLK (0.7641 0.725)
I0/U_6/count2_reg[3]/CLK (0.7618 0.7227)
I0/U_6/count2_reg[2]/CLK (0.7648 0.7256)
I0/U_6/count2_reg[1]/CLK (0.7674 0.7282)
I0/U_2/U_0/gregData_reg[2][0]/CLK (0.7405 0.7022)
I0/U_2/U_0/gregData_reg[1][3]/CLK (0.7405 0.7022)
I0/U_2/U_0/gregData_reg[1][0]/CLK (0.7402 0.7019)
I0/U_2/U_0/gregData_reg[0][0]/CLK (0.7403 0.702)
I0/U_0/eopCount_reg[0]/CLK (0.7514 0.7131)
I0/U_0/eopCount_reg[1]/CLK (0.7517 0.7134)
I0/U_0/eopCount_reg[2]/CLK (0.752 0.7137)
I0/U_0/usb_reg[2]/CLK (0.7513 0.713)
I0/U_0/usb_reg[1]/CLK (0.7501 0.7119)
I0/U_0/usb_reg[0]/CLK (0.7511 0.7128)
I0/U_1/data_ready_0_reg/CLK (0.7463 0.708)
I0/U_1/data_ready_1_reg/CLK (0.7461 0.7078)
I0/U_1/CS_reg[0]/CLK (0.7467 0.7085)
I0/U_1/CS_reg[1]/CLK (0.7396 0.7013)
I0/U_1/CS_reg[3]/CLK (0.7483 0.71)
I0/U_1/cur_data_reg[0]/CLK (0.7496 0.7113)
I0/U_1/part4/cnt_reg[0]/CLK (0.742 0.7037)
I0/U_1/part4/cnt_reg[1]/CLK (0.7457 0.7074)
I0/U_1/part4/cnt_reg[2]/CLK (0.7407 0.7024)
I0/U_1/part4/pre_val_reg[0]/CLK (0.7399 0.7016)
I0/U_1/part4/cur_data_ready_reg/CLK (0.7442 0.7059)
I0/U_2/U_0/gregData_reg[3][3]/CLK (0.7533 0.7166)
I0/U_2/U_0/gregData_reg[3][2]/CLK (0.765 0.7283)
I0/U_2/U_0/gregData_reg[3][1]/CLK (0.7571 0.7205)
I0/U_2/U_0/gregData_reg[2][2]/CLK (0.7621 0.7254)
I0/U_2/U_0/gregData_reg[2][1]/CLK (0.7583 0.7216)
I0/U_2/U_0/gregData_reg[1][1]/CLK (0.7595 0.7228)
I0/U_2/U_0/gregData_reg[0][3]/CLK (0.7594 0.7227)
I0/U_2/U_0/gregData_reg[0][1]/CLK (0.7593 0.7226)
I0/U_5/count_reg[0]/CLK (0.7602 0.7235)
I0/U_5/count_reg[8]/CLK (0.7684 0.7318)
I0/U_5/count_reg[7]/CLK (0.7691 0.7325)
I0/U_5/count_reg[6]/CLK (0.7696 0.733)
I0/U_5/count_reg[5]/CLK (0.7702 0.7335)
I0/U_5/count_reg[4]/CLK (0.7704 0.7337)
I0/U_5/count_reg[3]/CLK (0.7592 0.7225)
I0/U_5/count_reg[2]/CLK (0.758 0.7214)
I0/U_5/count_reg[1]/CLK (0.7576 0.7209)
I0/U_5/sclReg_reg/CLK (0.7659 0.7292)
I0/U_4/tsrDataReg_reg[2]/CLK (0.7659 0.7292)
I0/U_4/tsrDataReg_reg[3]/CLK (0.7654 0.7287)
I0/U_4/tsrDataReg_reg[4]/CLK (0.7651 0.7284)
I0/U_6/sd_clock1_reg/CLK (0.7676 0.7309)
I0/U_6/sd_clock2_reg/CLK (0.7668 0.7301)
I0/U_2/U_0/gregData_reg[3][5]/CLK (0.7409 0.7012)
I0/U_2/U_0/gregData_reg[3][4]/CLK (0.7364 0.6967)
I0/U_2/U_0/gregData_reg[3][0]/CLK (0.7263 0.6866)
I0/U_2/U_0/gregData_reg[2][5]/CLK (0.7389 0.6992)
I0/U_2/U_0/gregData_reg[2][4]/CLK (0.7305 0.6908)
I0/U_2/U_0/gregData_reg[1][5]/CLK (0.7424 0.7027)
I0/U_2/U_0/gregData_reg[0][5]/CLK (0.7435 0.7038)
I0/U_2/U_2/count_reg[1]/CLK (0.7436 0.7039)
I0/U_1/CS_reg[2]/CLK (0.7437 0.704)
I0/U_1/cur_data_reg[1]/CLK (0.7439 0.7042)
I0/U_1/cur_inst_reg[3]/CLK (0.7425 0.7028)
I0/U_1/cur_inst_reg[1]/CLK (0.7429 0.7032)
I0/U_1/cur_inst_reg[0]/CLK (0.7434 0.7037)
I0/U_1/part3/data_out_reg/CLK (0.7425 0.7028)
I0/U_1/part4/pre_val_reg[7]/CLK (0.7416 0.7019)
I0/U_1/part4/pre_val_reg[6]/CLK (0.7437 0.704)
I0/U_1/part4/pre_val_reg[5]/CLK (0.7438 0.7041)
I0/U_1/part4/pre_val_reg[4]/CLK (0.7405 0.7009)
I0/U_1/part4/pre_val_reg[3]/CLK (0.7237 0.684)
I0/U_1/part4/pre_val_reg[2]/CLK (0.7394 0.6997)
I0/U_1/part4/pre_val_reg[1]/CLK (0.7235 0.6838)
I0/U_0/eop1_reg/CLK (0.7499 0.712)
I0/U_0/eop2_reg/CLK (0.751 0.7131)
I0/U_0/eopf_reg/CLK (0.7522 0.7143)
I0/U_0/writeCount_reg[2]/CLK (0.7445 0.7067)
I0/U_0/usb_reg[3]/CLK (0.7473 0.7094)
I0/U_0/writeCount_reg[0]/CLK (0.7444 0.7065)
I0/U_0/writeCount_reg[1]/CLK (0.7498 0.7119)
I0/U_1/cur_inst_reg[2]/CLK (0.7394 0.7015)
I0/U_1/part2/d1_reg/CLK (0.7513 0.7134)
I0/U_1/part2/d2_reg/CLK (0.7515 0.7136)
I0/U_1/part3/data0_buf0_reg/CLK (0.7517 0.7139)
I0/U_3/U_1/eopIn1_reg/CLK (0.7489 0.711)
I0/U_3/U_1/eopIn2_reg/CLK (0.7511 0.7132)
I0/U_3/U_1/eopFound_reg/CLK (0.7522 0.7143)
I0/U_3/U_1/state_reg[2]/CLK (0.7486 0.7108)
I0/U_3/U_1/state_reg[1]/CLK (0.7523 0.7144)
I0/U_3/U_1/state_reg[0]/CLK (0.7512 0.7134)
I0/U_3/U_1/locku_reg/CLK (0.7515 0.7136)
I0/U_3/U_1/lockc_reg/CLK (0.7518 0.7139)